Loongson 7A1000 Bridge User Manual. Loongson Technology Corporation Limited Version 2.00 - page 6

 

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Loongson 7A1000 Bridge User Manual. Loongson Technology Corporation Limited Version 2.00 - page 6

 

 

Address Offset
Register
Size (bit)
Description
0x800
GPIO_OEN
57
GPIO output enable (active low). Each byte controls
one GPIO pin, bit 0 is valid.
0x900
GPIO_O
57
GPIO output. Each byte controls one GPIO pin, bit 0
is valid.
0xA00
GPIO_I
57
GPIO input. Each byte controls one GPIO pin, bit 0 is
valid.
GPIO interrupt enable. Each byte controls one GPIO
0xB00
GPIO_INT_EN
57
pin, bit 0 is valid.
For example, the output input direction of GPIO03 can be controlled either by bit[3] with offset address
0x0 (taking care not to affect other bits) or by a byte with offset address 0x803 (only bit[0] is valid).
14.2. Description of Registers
GPIO Direction Control
Address Offset: 00-03h
Attribute: R/W
Default value: FFFFFFF0h
Size: 4
Table 210. GPIO direction control
Bit Field
Name
Read/Write
Description
R/W
Corresponds to the direction control of
31:0
GPIO_OEN
GPIO[31:0].
0: Output
1: Input
Address Offset: 04-07h
Attribute: R/W
Default value: FFFFFFFFh
Size: 4
Table 211. GPIO direction control
Bit Field
Name
Read/Write
Description
R/W
Reserved.
31:26
Reserved
150
Bit Field
Name
Read/Write
Description
25:0
GPIO_OEN
R/W
Corresponds to the direction control of
GPIO[57:32].
0: Output
1: Input
GPIO Output
Address Offset: 00-03h
Attribute: R/W
Default value: 0000000Fh
Size: 4
Table 212. GPIO output
Bit Field
Name
Read/Write
Description
31:0
GPIO_O
R/W
Corresponds to the output of GPIO[31:0].
Address Offset: 04-07h
Attribute: R/W
Default value: 00000000h
Size: 4
Table 213. GPIO output
Bit Field
Name
Read/Write
Description
31:26
Reserved
R/W
Reserved.
R/W
Corresponds to the output of
25:0
GPIO_O
GPIO[57:32].
GPIO Input
Address Offset: 00-03h
Attribute: RO
Default value: N/A
Size: 4
Table 214. GPIO input
Bit Field
Name
Read/Write
Description
RO
31:0
GPIO_I
Corresponds to the input of GPIO[31:0].
Address Offset: 04-07h
151
Attribute: RO
Default value: 00000000h
Size: 4
Table 215. GPIO input
Bit Field
Name
Read/Write
Description
31:26
Reserved
R/W
Reserved.
RO
25:0
GPIO_I
Corresponds to the input of GPIO[57:32].
GPIO Interrupt Enable
Address Offset: 00-03h
Attribute: R/W
Default value: 00000000h
Size: 4
Table 216. GPIO interrupt enable
Bit Field
Name
Read/Write
Description
31:0
GPIO_OEN
R/W
Corresponds to the interrupt enable of
GPIO[31:0].
0: Disable interrupt
1: Enable interrput
Address Offset: 04-07h
Attribute: R/W
Default value: 00000000h
Size: 4
Table 217. GPIO interrupt enable
Bit Field
Name
Read/Write
Description
R/W
Reserved.
31:26
Reserved
R/W
Corresponds to the interrupt enable of
25:0
GPIO_OEN
GPIO[57:32].
0: Disable interrupt
1: Enable interrput
152
Chapter 15. GMAC Controller (D3:F0, D3:F1)
The bridge integrates two GMAC controllers, which have the same functions.
Note: See Notes on the Use of the Software for software enablement of 64-bit DMA for the GMAC
controllers.
15.1. GMAC Configuration Register (D3:F0, D3:F1)
Table 218. GMAC controller configuration registers
Address
Abbreviatio
Description
Default value
Read/Write
Offset
n
00h-01h
VID
Vendor ID
0014h
RO
02h-03h
DID
Device ID
7A03h
RO
PCI Command
R/W, RO
04h-05h
PCICMD
0000h
Revision ID
RO
08h
RID
00h
Programming Interface
RO
09h
PI
00h
Sub Class Code
RO
0Ah
SCC
00h
0Bh
BCC
Base Class Code
02h
RO
0Ch
CLS
Cache Line Size
00h
RO
0Eh
HEADTYP
Header Type
80h
RO
Control Block Base Address Register
R/W, RO
10h-17h
CNL_BAR
0000000000000004h
Subsystem Vendor ID
RO
2Ch-2Dh
SVID
0000h
Subsystem Identification
RO
2Eh-2Fh
SID
0000h
3Ch
INT_LN
Interrupt Line
00h
R/W
3Dh
INT_PN
Interrupt Pin
01h
RO
Note: Address space not listed in the table indicates reserved.
Registers that differ slightly from the PCI configuration header specification and their descriptions are
listed below.
PCICMD - PCI Command Register (GMAC - D3:F0, D3:F1)
Address Offset: 04-05h
Attribute: R/W, RO
Default value: 0000h
Size: 16 bits
Table 219. PCI command register
153
Bit Field
Name
Read/Write
Description
15:2
Reserved
RO
Reserved.
R/W
This bit is used to control whether access to
1
Memory Space Enable
the GMAC control registers is enabled.
0: Disable access.
1: Enable access to the GMAC control
registers. The BAR register must be
configured before this bit can be configured
to 1.
RO
Reserved.
0
Reserved
CNL_BAR - Control Base Address Register
This register is used to configure the base address of the control registers of the GMAC controller.
Address Offset: 10-13h
Attribute: R/W, RO
Default value: 00000004h
Size: 32 bits
Table 220. Control base address register
Bit Field
Name
Read/Write
Description
RW
The software writes to this register field the
31:15
Base Address
low address of the base address allocated to
the GMAC control register.
RO
The address space size of GMAC control
14:4
Memory Size
register is 32KB.
RO
3
Prefetchable Memory
Set to 0 to indicate that it is not
prefetchable.
RO
2:1
Memory Type
Set to 10b to indicate 64-bit BAR.
0
Memory/ I/O Space
RO
Set to 0 to indicate Memory space BAR.
Address Offset: 14-17h
Attribute: R/W
Default value: 00000000h
Size: 32 bits
Table 221. Control base address register
Bit Field
Name
Read/Write
Description
31:0
Base Address
RW
The software writes to this register field the
high 32-bit address of the base address
allocated to the GMAC control register.
154
Chapter 16. USB Controller (D4:F0/1, D5:F0/1)
The bridge contains two USB controllers, each containing three ports.
The USB ports of the bridge have the following features.
• Compatible with USB Rev 1.1, USB Rev 2.0 protocols
• Compatible with OHCI Rev 1.0, EHCI Rev 1.0 protocols
• Supports LS (Low Speed), FS (Full Speed) and HS (High Speed) USB devices
• Works in Host mode, OTG mode is not supported
Each USB controller module of the bridge includes an EHCI controller and an OHCI controller, with each
EHCI controller and OHCI controller supporting 3 ports. The EHCI controller is used by default, and control
is transferred to the OHCI controller only when the hooked up device is a full-speed or low-speed device.
When a full-speed or low-speed device is unplugged, control is returned to the EHCI controller.
Note: The Memory Space Enable control for the OHCI and EHCI device headers of USB devices requires
special handling, see Notes on the Use of the Software.
16.1. EHCI Controller
16.1.1. EHCI Configuration Register (D4:F1, D5:F1)
Table 222. USB-EHCI controller configuration registers
Address
Abbreviatio
Description
Default value
Read/Write
Offset
n
00h-01h
Vendor ID
RO
VID
0014h
02h-03h
Device ID
RO
DID
7A14h
04h-05h
PCICMD
PCI Command
0000h
R/W, RO
08h
Revision ID
RO
RID
00h
09h
Programming Interface
RO
PI
20h
0Ah
SCC
Sub Class Code
03h
RO
0Bh
Base Class Code
RO
BCC
0Ch
0Ch
Cache Line Size
RO
CLS
00h
0Eh
HEADTYP
Header Type
80h
RO
10h-17h
Control Block Base Address Register
R/W, RO
CNL_BAR
0000000000000004h
2Ch-2Dh
Subsystem Vendor ID
RO
SVID
0000h
2Eh-2Fh
SID
Subsystem Identification
0000h
RO
3Ch
Interrupt Line
R/W
INT_LN
00h
3Dh
Interrupt Pin
RO
INT_PN
01h
Note: Address space not listed in the table indicates reserved.
Registers that differ slightly from the PCI configuration header specification and their descriptions are
listed below.
155
PCICMD - PCI Command Register (USB EHCI - D4:F1, D5:F1)
Address Offset: 04-05h
Attribute: R/W, RO
Default value: 0000h
Size: 16 bits
Table 223. PCI command register
Bit Field
Name
Read/Write
Description
15:2
Reserved
RO
Reserved.
1
Memory Space Enable
R/W
This bit is used to control whether access to
the USB EHCI control registers is enabled.
0: Disable access.
1: Enable access to the USB EHCI control
registers. The BAR register must be
configured before this bit can be configured
to 1.
In rev. 00, this bit controls the Memory
Space Enable of the OHCI. The Memory
Space Enable of the EHCI is controlled by
the corresponding bit of the OHCI
controller.
0
Reserved
RO
Reserved.
CNL_BAR - Control Base Address Register
This register is used to configure the base address of the control registers of the EHCI controller.
Address Offset: 10-13h
Attribute: R/W, RO
Default value: 00000004h
Size: 32 bits
Table 224. Control base address register
Bit Field
Name
Read/Write
Description
RW
The software writes to this register field the
31:15
Base Address
low address of the base address allocated to
the EHCI control register.
RO
The address space size of EHCI control
14:4
Memory Size
register is 32KB.
RO
3
Prefetchable Memory
Set to 0 to indicate that it is not
prefetchable.
156
Bit Field
Name
Read/Write
Description
2:1
Memory Type
RO
Set to 10b to indicate 64-bit BAR.
0
Memory/ I/O Space
RO
Set to 0 to indicate Memory space BAR.
Address Offset: 14-17h
Attribute: R/W
Default value: 00000000h
Size: 32 bits
Table 225. Control base address register
Bit Field
Name
Read/Write
Description
RW
Software writes to this register field the high
31:0
Base Address
32-bit address of the base address allocated
to the EHCI control register.
The bridge’s USB host controller is compatible with the EHCI Rev 1.0 protocol. Refer to the Enhanced Host
Controller Interface Rev 1.0 Specification for details of the Capability register and Operational register.
16.2. OHCI Controller
16.2.1. OHCI Configuration Register (D4:F0, D5:F0)
Table 226. USB-OHCI controller configuration registers
Address
Abbreviatio
Description
Default value
Read/Write
Offset
n
00h-01h
VID
Vendor ID
0014h
RO
02h-03h
Device ID
RO
DID
7A24h
04h-05h
PCI Command
R/W, RO
PCICMD
0000h
08h
RID
Revision ID
00h
RO
09h
Programming Interface
RO
PI
10h
0Ah
Sub Class Code
RO
SCC
03h
0Bh
BCC
Base Class Code
0Ch
RO
0Ch
Cache Line Size
RO
CLS
00h
0Eh
Header Type
RO
HEADTYP
80h
10h-17h
CNL_BAR
Control Block Base Address Register
0000000000000004h
R/W, RO
2Ch-2Dh
Subsystem Vendor ID
RO
SVID
0000h
2Eh-2Fh
Subsystem Identification
RO
SID
0000h
3Ch
INT_LN
Interrupt Line
00h
R/W
3Dh
Interrupt Pin
RO
INT_PN
01h
Note: Address space not listed in the table indicates reserved.
157
Registers that differ slightly from the PCI configuration header specification and their descriptions are
listed below.
PCICMD - PCI Command Register (USB OHCI - D4:F0, D5:F0)
Address Offset: 04-05h
Attribute: R/W, RO
Default value: 0000h
Size: 16 bits
Table 227. PCI command register
Bit Field
Name
Read/Write
Description
15:2
Reserved
RO
Reserved.
R/W
This bit is used to control whether access to
1
Memory Space Enable
the USB OHCI control registers is enabled.
0: Disable access.
1: Enable access to the USB OHCI control
registers. The BAR register must be
configured before this bit can be configured
to 1.
In rev. 00, this bit controls the Memory
Space Enable of the EHCI. The Memory
Space Enable of the OHCI is controlled by
the corresponding bit of the EHCI controller.
RO
Reserved.
0
Reserved
CNL_BAR - Control Base Address Register
This register is used to configure the base address of the control registers of the OHCI controller.
Address Offset: 10-13h
Attribute: R/W, RO
Default value: 00000004h
Size: 32 bits
Table 228. Control base address register
Bit Field
Name
Read/Write
Description
31:15
Base Address
RW
The software writes to this register field the
low address of the base address allocated to
the OHCI control register.
RO
The address space size of OHCI control
14:4
Memory Size
register is 32KB.
158
Bit Field
Name
Read/Write
Description
3
Prefetchable Memory
RO
Set to 0 to indicate that it is not
prefetchable.
RO
2:1
Memory Type
Set to 10b to indicate 64-bit BAR.
RO
0
Memory/ I/O Space
Set to 0 to indicate Memory space BAR.
Address Offset: 14-17h
Attribute: R/W
Default value: 00000000h
Size: 32 bits
Table 229. Control base address register
Bit Field
Name
Read/Write
Description
RW
Software writes to this register field the high
31:0
Base Address
32-bit address of the base address allocated
to the OHCI control register.
The bridge’s USB host controller is compatible with the OHCI Rev 1.0 protocol. Refer to the Open Host
Controller Interface Rev 1.0 Specification for details of the operational registers.
159
Chapter 17. Graphics Processor (D6:F0)
17.1. GPU Configuration Register (D6:F0)
Table 230. GPU controller configuration registers
Address
Abbreviatio
Description
Default value
Read/Write
Offset
n
00h-01h
Vendor ID
RO
VID
0014h
02h-03h
DID
Device ID
7A15h
RO
04h-05h
PCICMD
PCI Command
0000h
R/W, RO
08h
Revision ID
RO
RID
00h
09h
PI
Programming Interface
00h
RO
0Ah
SCC
Sub Class Code
02h
RO
0Bh
Base Class Code
RO
BCC
03h
0Ch
CLS
Cache Line Size
00h
RO
0Eh
HEADTYP
Header Type
80h
RO
10h-17h
Control Block Base Address Register
R/W, RO
CNL_BAR
0000000000000004h
18h-1Fh
GMEM_BAR
Graphic Memory Base Address
0000000000000004h
R/W, RO
Register
27h-20h
Reserved Base Address Register
R/W, RO
RSV_BAR
0000000000000004h
2Ch-2Dh
Subsystem Vendor ID
RO
SVID
0000h
2Eh-2Fh
SID
Subsystem Identification
0000h
RO
3Ch
Interrupt Line
R/W
INT_LN
00h
3Dh
Interrupt Pin
RO
INT_PN
01h
Note: Address space not listed in the table indicates reserved.
Registers that differ slightly from the PCI configuration header specification and their descriptions are
listed below.
PCICMD - PCI Command Register (GPU - D6:F0)
Address Offset: 04-05h
Attribute: R/W, RO
Default value: 0000h
Size: 16 bits
Table 231. PCI command register
Bit Field
Name
Read/Write
Description
RO
Reserved.
15:2
Reserved
160
Bit Field
Name
Read/Write
Description
1
Memory Space Enable
R/W
This bit is used to control whether access to
the GPU control registers is enabled.
0: Disable access.
1: Enable access to the GMAC control
registers and GMEN space. The BAR register
must be configured before this bit can be
configured to 1.
RO
Reserved.
0
Reserved
CNL_BAR - Control Base Address Register
This register is used to configure the base address of the control registers of the GMAC controller.
Address Offset: 10-13h
Attribute: R/W, RO
Default value: 00000004h
Size: 32 bits
Table 232. Control base address register
Bit Field
Name
Read/Write
Description
31:18
Base Address
RW
Software writes to this register field the low
address of the base address allocated to the
GPU control register.
17:4
Memory Size
RO
The address space size of the GPU control
registers is 32KB.
RO
3
Prefetchable Memory
Set to 0 to indicate that it is not
prefetchable.
2:1
Memory Type
RO
Set to 10b to indicate 64-bit BAR.
RO
0
Memory/ I/O Space
Set to 0 to indicate Memory space BAR.
Address Offset: 14-17h
Attribute: R/W
Default value: 00000000h
Size: 32 bits
Table 233. Control base address register
Bit Field
Name
Read/Write
Description
RW
Software writes to this register field the high
31:0
Base Address
32-bit address of the base address allocated
to the GPU control register.
161
GMEM_BAR - Video Memory Base Address Register
This register is used to configure the base address of the video memory.
Address Offset: 18-1Bh
Attribute: R/W, RO
Default value: 00000004h
Size: 32 bits
Table 234. Video memory base address register
Bit Field
Name
Read/Write
Description
RW
The software writes to this register field the
31:X
Base Address
low bit of the base address allocated to the
video memory.
RO
The memory size is configured by the BIOS.
X:4
Memory Size
The maximum is not more than 512MB.
RO
3
Prefetchable Memory
Set to 0 to indicate that it is not
prefetchable.
2:1
Memory Type
RO
Set to 10b to indicate 64-bit BAR.
0
Memory/ I/O Space
RO
Set to 0 to indicate Memory space BAR.
Address Offset: 1C-1Fh
Attribute: R/W
Default value: 00000000h
Size: 32 bits
Table 235. Video memory base address register
Bit Field
Name
Read/Write
Description
RW
The software writes to this register field the
31:0
Base Address
high 32-bit address allocated to the base
address of the video memory.
RSV_BAR - Reserved Window Base Address Register
This register is used to configure the base address of the reserved registers of the GPU controller.
Address Offset: 20-23h
Attribute: R/W, RO
Default value: 00000004h
Size: 32 bits
Table 236. Reserved window base address register
162
Bit Field
Name
Read/Write
Description
31:18
Base Address
RW
The software writes to this register field the
low address of the base address allocated to
the GPU reserved register.
17:4
Memory Size
RO
The address space size of the GPU reserved
registers is 256B.
3
Prefetchable Memory
RO
Set to 0 to indicate that it is not
prefetchable.
2:1
Memory Type
RO
Set to 10b to indicate 64-bit BAR.
RO
0
Memory/ I/O Space
Set to 0 to indicate Memory space BAR.
Address Offset: 24-27h
Attribute: R/W
Default value: 00000000h
Size: 32 bits
Table 237. Reserved window base address register
Bit Field
Name
Read/Write
Description
RW
The software writes to this register field the
31:0
Base Address
high 32-bit address of the base address
allocated to the GPU reserved register.
17.2. DDR3 Memory Interface
The bridge chip’s integrated memory interface complies with the DDR3 SDRAM standard (JESD79-3).
The bridge supports 1 chip select, 16 row addresses, 15 column addresses, and 3 logical body addresses.
The bridge chip’s memory controller has the following characteristics.
• Full-flow operation of commands, read and write data on the interface
• Memory command merging and sorting to improve the overall bandwidth
• Basic parameters of memory devices can be modified
•
Supports 133-667MHz clock frequency
Access Address
The DDR3 memory controller consists of two address spaces: the memory space for video memory
controller configuration register and the memory space for the video memory. These two address spaces
share the same address space (the video memory address space, the address space allocated to
GMEM_BAR). The final access to the memory address space is determined by the parameter
disable_gmem_confspace — bit 3 of general configuration register 0 of the bridge configuration register
addr_0x420[3].
When the configuration parameter disable_gmem_confspace
=
0, all accesses to the memory are
configuration register accesses. When the configuration parameter disable_gmem_confspace = 1, the
accesses to the memory are normal memory read and write accesses.
163
Chapter 18. Display Controller (D6:F1)
The features supported by the display controller of the bridge include the following.
• Dual DVO interface displays
•
Each display supports up to 1920x1080@60Hz
• Two hardware cursors modes: Monochrome, ARGB8888
• Four color depths: RGB444, RGB555, RGB565, RGB888
• Output dithering and gamma correction
• Switchable dual routability frame buffer
• Interrupt and soft reset
18.1. DC Configuration Register (D6:F1)
Table 238. DC controller configuration registers
Address
Abbreviatio
Description
Default value
Read/Write
Offset
n
00h-01h
VID
Vendor ID
0014h
RO
02h-03h
Device ID
RO
DID
7A06h
04h-05h
PCI Command
R/W, RO
PCICMD
0000h
08h
RID
Revision ID
00h
RO
09h
Programming Interface
RO
PI
00h
0Ah
Sub Class Code
RO
SCC
03h
0Bh
BCC
Base Class Code
0Ch
RO
0Ch
Cache Line Size
RO
CLS
00h
0Eh
Header Type
RO
HEADTYP
80h
10h-17h
CNL_BAR
Control Block Base Address Register
0000000000000004h
R/W, RO
2Ch-2Dh
Subsystem Vendor ID
RO
SVID
0000h
2Eh-2Fh
Subsystem Identification
RO
SID
0000h
3Ch
INT_LN
Interrupt Line
00h
R/W
3Dh
Interrupt Pin
RO
INT_PN
01h
Note: Address space not listed in the table indicates reserved.
Registers that differ slightly from the PCI configuration header specification and their descriptions are
listed below.
PCICMD - PCI Command Register (DC - D6:F1)
Address Offset: 04-05h
Attribute: R/W, RO
164
Default value: 0000h
Size: 16 bits
Table 239. PCI command register
Bit Field
Name
Read/Write
Description
RO
Reserved.
15:2
Reserved
1
Memory Space Enable
R/W
This bit is used to control whether access to
the DC control registers is enabled.
0: Disable access.
1: Enable access to the DC control registers.
The BAR register must be configured before
this bit can be configured to 1.
0
Reserved
RO
Reserved.
CNL_BAR - Control Base Address Register
This register is used to configure the base address of the control registers of the GMAC controller.
Address Offset: 10-13h
Attribute: R/W, RO
Default value: 00000004h
Size: 32 bits
Table 240. Control base address register
Bit Field
Name
Read/Write
Description
RW
The software writes to this register field the
31:16
Base Address
low address of the base address assigned to
the DC control register.
RO
The address space size of DC control
15:4
Memory Size
register is 64KB.
RO
3
Prefetchable Memory
Set to 0 to indicate that it is not
prefetchable.
RO
2:1
Memory Type
Set to 10b to indicate 64-bit BAR.
0
Memory/ I/O Space
RO
Set to 0 to indicate Memory space BAR.
Address Offset: 14-17h
Attribute: R/W
Default value: 00000000h
Size: 32 bits
Table 241. Control base address register
165
Bit Field
Name
Read/Write
Description
31:0
Base Address
RW
Software writes to this register field the high
32-bit address of the base address assigned
to the DC control register.
18.2. DC Control Register
18.2.1. Display Detection Register
The 7A bridge contains two sets of I2C bus pins specifically for display detection. These two sets of I2C
bus pins need to be emulated by software using GPIO pins. These two sets of GPIO pins differ from the
GPIO pins in the MISC in that their control registers are placed in the control register space of the DC. The
I2C bus of DVO0 is controlled by bit[1:0] of the GPIO register, and the I2C bus of DVO1 is controlled by
bit[3:2] of the GPIO register. The correspondence between I2C pins and GPIO registers is shown in the
following table.
Table 242. Correspondence between the I2C pins of the DVO and the control registers
Pin Name
GPIO control bit
DVO0_SDA
0
DVO0_SCL
1
DVO1_SDA
2
DVO1_SCL
3
Each GPIO control bit is controlled by three registers. The addresses of the GPIO control registers are
shown in the following table.
Table 243. DVO’s I2C pin control register address
Register Name
Address Offset
Read/Wri
Description
Reset Value
te
WO
Output register
GPIO_OUT
0x1650
0h
RO
Input register
N/A
GPIO_IN
0x1650
GPIO_EN
0x1660
R/W
GPIO direction control register
0h
Bit
Description
Initial Value
GPIO_OUT
DVO0_SDA_OUT
0
Control the output value of the DVO0_SDA pin (write
0
only)
DVO0_SCL_OUT
1
Control the output value of the DVO0_SCL pin (write
0
only)
DVO1_SDA_OUT
2
Control the output value of the DVO1_SDA pin (write
0
only)
DVO1_SCL_OUT
3
Control the output value of the DVO1_SCL pin (write
0
only)
Bit
Description
Initial Value
GPIO_IN
N/A
DVO0_SDA_IN
0
Control the input value of the DVO0_SDA pin (read
only)
166
DVO0_SCL_IN
1
Control the input value of the DVO0_SCL pin (write
N/A
only)
N/A
DVO1_SDA_IN
2
Control the input value of the DVO1_SDA pin (write
only)
N/A
DVO1_SCL_IN
3
Control the input value of the DVO1_SCL pin (write
only)
GPIO_EN
Bit
Description
Initial Value
DVO0_SDA_EN
0
Control the direction of the DVO0_SDA pin
0
(read/write)
DVO0_SCL_EN
1
Control the direction of the DVO0_SCL pin
0
(read/write)
DVO1_SDA_EN
2
Control the direction of the DVO1_SDA pin
0
(read/write)
DVO1_SCL_EN
3
Control the direction of the DVO1_SCL pin
0
(read/write)
167
Chapter 19. HDA Controller (D7:F0)
The HDA controller is compatible with High Definition Audio Specification Revision 1.0a.
See PLL1 Configuration Register for HDA-related pin setup registers.
19.1. HDA Configuration Register (D7:F0)
Table 244. HDA controller configuration registers
Address
Abbreviatio
Description
Default value
Read/Write
Offset
n
00h-01h
VID
Vendor ID
0014h
RO
02h-03h
Device ID
RO
DID
7A07h
04h-05h
PCI Command
R/W, RO
PCICMD
0000h
08h
RID
Revision ID
00h
RO
09h
PI
Programming Interface
00h
RO
0Ah
Sub Class Code
RO
SCC
03h
0Bh
BCC
Base Class Code
04h
RO
0Ch
CLS
Cache Line Size
00h
RO
0Eh
Header Type
RO
HEADTYP
00h
10h-17h
CNL_BAR
Control Block Base Address Register
0000000000000004h
R/W, RO
2Ch-2Dh
SVID
Subsystem Vendor ID
0000h
RO
2Eh-2Fh
Subsystem Identification
RO
SID
0000h
3Ch
INT_LN
Interrupt Line
00h
R/W
3Dh
INT_PN
Interrupt Pin
01h
RO
Note:
1. The HDA configuration header is only visible when the relevant pin is configured for HDA mode.
2. Address space not listed in the table indicates reserved.
Registers that differ slightly from the PCI configuration header specification and their descriptions are
listed below.
PCICMD - PCI Command Register (HDA - D7:F0)
Address Offset: 04-05h
Attribute: R/W, RO
Default value: 0000h
Size: 16 bits
Table 245. PCI command register
168
Bit Field
Name
Read/Write
Description
15:2
Reserved
RO
Reserved.
R/W
This bit is used to control whether access to
1
Memory Space Enable
the HDA control registers is enabled.
0: Disable access.
1: Enable access to the HDA control
registers. The BAR register must be
configured before this bit can be configured
to 1.
RO
Reserved.
0
Reserved
CNL_BAR - Control Base Address Register
This register is used to configure the base address of the HDA controller’s control registers.
Address Offset: 10-13h
Attribute: R/W, RO
Default value: 00000004h
Size: 32 bits
Table 246. Control base address register
Bit Field
Name
Read/Write
Description
RW
Software writes to this register field the low
31:16
Base Address
address of the base address assigned to the
HDA control register.
RO
The HDA control register has an address
15:4
Memory Size
space size of 64KB.
RO
3
Prefetchable Memory
Set to 0 to indicate that it is not
prefetchable.
RO
2:1
Memory Type
Set to 10b to indicate 64-bit BAR.
0
Memory/ I/O Space
RO
Set to 0 to indicate Memory space BAR.
Address Offset: 14-17h
Attribute: R/W
Default value: 00000000h
Size: 32 bits
Table 247. Control base address register
Bit Field
Name
Read/Write
Description
31:0
Base Address
RW
The software writes to this register field the
high 32-bit address assigned to the base
address of the HDA control register.
169
19.2. Description of HDA Control Register
The HDA control registers are designed in full accordance with the HD audio Rev 1.0 specification. The
following table lists the main register parameters.[1] Refer to the HD audio Rev 1.0 manual for details.
1. Translator’s note: The original table is missing.
170
Chapter 20. AC97 Controller (D7:F1)
20.1. AC97 Configuration Register (D7:F1)
Table 248. AC97 controller configuration registers
Address
Abbreviatio
Description
Default value
Read/Write
Offset
n
00h-01h
Vendor ID
RO
VID
0014h
02h-03h
DID
Device ID
7A17h
RO
04h-05h
PCICMD
PCI Command
0000h
R/W, RO
08h
Revision ID
RO
RID
00h
09h
PI
Programming Interface
00h
RO
0Ah
SCC
Sub Class Code
01h
RO
0Bh
Base Class Code
RO
BCC
04h
0Ch
CLS
Cache Line Size
00h
RO
0Eh
HEADTYP
Header Type
00h
RO
10h-17h
Control Block Base Address Register
R/W, RO
CNL_BAR
0000000000000004h
2Ch-2Dh
SVID
Subsystem Vendor ID
0000h
RO
2Eh-2Fh
SID
Subsystem Identification
0000h
RO
3Ch
Interrupt Line
R/W
INT_LN
00h
3Dh
Interrupt Pin
RO
INT_PN
01h
Note:
1. The AC97 configuration header is only visible when the relevant pin is configured for AC97 mode.
2. Address space not listed in the table indicates reserved.
Registers that differ slightly from the PCI configuration header specification and their descriptions are
listed below.
PCICMD - PCI Command Register (AC97 - D7:F1)
Address Offset: 04-05h
Attribute: R/W, RO
Default value: 0000h
Size: 16 bits
Table 249. PCI command register
Bit Field
Name
Read/Write
Description
RO
Reserved.
15:2
Reserved
171
Bit Field
Name
Read/Write
Description
1
Memory Space Enable
R/W
This bit is used to control whether access to
the AC97 control registers is enabled.
0: Disable access.
1: Enable access to the AC97 control
registers. The BAR register must be
configured before this bit can be configured
to 1.
RO
Reserved.
0
Reserved
CNL_BAR - Control Base Address Register
This register is used to configure the base address of the control registers of the AC97 control register.
Address Offset: 10-13h
Attribute: R/W, RO
Default value: 00000004h
Size: 32 bits
Table 250. Control base address register
Bit Field
Name
Read/Write
Description
31:16
Base Address
RW
The software writes to this register field the
low address of the base address allocated to
the AC97 control register.
15:4
Memory Size
RO
The address space size of AC97 control
register is 64KB.
RO
3
Prefetchable Memory
Set to 0 to indicate that it is not
prefetchable.
2:1
Memory Type
RO
Set to 10b to indicate 64-bit BAR.
RO
0
Memory/ I/O Space
Set to 0 to indicate Memory space BAR.
Address Offset: 14-17h
Attribute: R/W
Default value: 00000000h
Size: 32 bits
Table 251. Control base address register
Bit Field
Name
Read/Write
Description
RW
The software writes to this register field the
31:0
Base Address
high 32-bit address of the base address
allocated to the AC97 control register.
172
20.2. AC97 Controller Register
Table 252. List of AC97 control registers
Address
Abbreviatio
Description
Default Value
Read/Write
Offset
n
00h-01h
VID
Vendor ID
0014h
RO
Device ID
RO
02h-03h
DID
7A17h
04h-05h
PCICMD
PCI Command
0000h
R/W, RO
08h
RID
Revision ID
00h
RO
Programming Interface
RO
09h
PI
00h
0Ah
SCC
Sub Class Code
01h
RO
0Bh
BCC
Base Class Code
04h
RO
Cache Line Size
RO
0Ch
CLS
00h
Header Type
RO
0Eh
HEADTYP
00h
10h-17h
CNL_BAR
Control Block Base Address Register
0000000000000004h
R/W, RO
Subsystem Vendor ID
RO
2Ch-2Dh
SVID
0000h
Subsystem Identification
RO
2Eh-2Fh
SID
0000h
3Ch
INT_LN
Interrupt Line
00h
R/W
Interrupt Pin
RO
3Dh
INT_PN
01h
CSR Register
Offset address: 0x00
Reset value: 0x00000000
Table 253. CSR register
Bit Field
Name
Length
Read/Write
Description
31:2
Reserved
30
RO
Reserved.
RESUME
R/W
Hanging. Read this bit to return the
1
1
current state of the AC97 subsystem.
1: AC97 subsystem hanged
0: Normal operating state
Writing 1 to this bit in the pending
state will start the recovery operation.
RST_FORCE
W
AC97 cold boot.
0
1
Writing 1 will cause the AC97 Codec to
cold boot.
OCC Register
173
Offset address: 0x04
Reset value: 0x00004141
Table 254. OCC register
Bit Field
Name
Length
Read/Write
Description
31:24
Reserved
10
R/W
Reserved.
23:16
Reserved
10
R/W
Reserved.
OC1_CFG_R
R/W
Output channel 1: Right channel
15:10
10
configuration.
7:0
OC0_CFG_L
10
R/W
Output channel 0: Left channel
configuration.
ICC Register
Offset address: 0x10
Reset value: 0x00410000
Table 255. ICC register
Bit Field
Name
Length
Read/Write
Description
31:24
Reserved
10
R/W
Reserved.
IC_CFG_MIC
R/W
Input channel 2: MIC channel
23:16
10
configuration.
15:10
Reserved
10
R/W
Reserved.
Reserved
R/W
Reserved.
7:0
10
Table 256. Description of the sound channel format
Bit Field
Name
Length
Read/Write
Description
Reserved
R/W
Reserved.
7
1
6
DMA_EN
1
R/W
DMA enable.
1: DMA enable.
0: DMA disable.
FIFO_THRES
R/W
FIFO threshold
5:4
2
5:4
Output
Input
channel
channel
FIFO 1/4
FIFO 1/4
00
empty
full
01
FIFO 1/2
FIFO 1/2
empty
full
FIFO 3/4
FIFO 3/4
10
empty
full
11
FIFO empty
FIFO full
174
Bit Field
Name
Length
Read/Write
Description
3:2
SW
2
R/W
Number of sampling bits
00: 10 bits
10: 16 bits
VSR
R/W
Sampling rate
1
1
1: Variable sampling rate
0: Fixed sampling rate (410KHz)
0
CH_EN
1
R/W
Channel enable
1: Channel enable
0: Channel disable (or go to energy-
saving state)
Codec Register Access Command
Offset address: 0x110
Reset value: 0x00000000
Table 257. Codec register access command
Bit Field
Name
Length
Read/Write
Description
CODEC_WR
R/W
31
1
Read/write selection
1: Read. When reading data, first set
CODEC_WR to read mode, and set the
register address you want to access in
CODEC_ADR. Wait until the return data
completes interrupt and then read the
CODEC_DAT register to read the value.
0: Write.
Reserved
R
Reserved.
30:23
10
CODEC_ADR
R/W
Codec register address
22:16
7
15:0
CODEC_DAT
16
R/W
Codec register data
Interrupt Status Register/Interrupt Mask Register
Offset address: 0x54/510
Reset value: 0x00000000
Table 258. Interrupt Status Register/Interrupt Mask Register
Bit Field
Name
Length
Read/Write
Description
IC_FULL
R/W
Input channel 2: FIFO full
31
1
175
Bit Field
Name
Length
Read/Write
Description
30
IC_TH_INT
1
R/W
Input channel 2: FIFO reaches
threshold
Reserved
R/W
Reserved.
29:10
22
7
OC1_FULL
1
R/W
Output channel 1: FIFO full
OC1_EMPTY
R/W
Output channel 1: FIFO empty
6
1
OC1_ TH_INT
R/W
Output channel 1: FIFO reaches
5
1
threshold
4
OC0_FULL
1
R/W
Output channel 0: FIFO full
OC0_EMPTY
R/W
Output channel 0: FIFO empty
3
1
2
OC0_ TH_INT
1
R/W
Output channel 0: FIFO reaches
threshold
CW_DONE
R/W
Codec register write complete
1
1
CR_DONE
R/W
Codec register read complete
0
1
Interrupt Status/Clear Register
Offset address: 0x5c
Reset value: 0x00000000
Table 259. Interrupt status/clear register
Bit Field
Name
Length
Read/Write
Description
31:0
INT_CLR
32
RO
After masking the interrupt status
register, a read of this register will
clear all interrupt status in register
0x54.
OC Interrupt Clear Register
Offset address: 0x60
Reset value: 0x00000000
Table 260. OC interrupt clear register
Bit Field
Name
Length
Read/Write
Description
INT_OC_CLR
RO
A read operation of this register will
31:0
32
clear the bits[7:2] corresponding to
the interrupt status of all output
channels in register 0x54.
IC Interrupt Clear Register
Offset address: 0x64
Reset value: 0x00000000
Table 261. IC interrupt clear register
176
Bit Field
Name
Length
Read/Write
Description
31:0
INT_IC_CLR
32
RO
A read operation of this register will
clear the bits[31:30] corresponding
to the interrupt status of all input
channels in register 0x54.
CODEC WRITE Interrupt Clear Register
Offset address: 0x610
Reset value: 0x00000000
Table 262. CODEC WRITE interrupt clear register
Bit Field
Name
Length
Read/Write
Description
31:0
INT_CW_CLR
32
RO
A read operation of this register will
clear the bit[1] in register 0x54.
CODEC READ Interrupt Clear Register
Offset address: 0x6c
Reset value: 00000000h
Table 263. CODEC READ interrupt clear register
Bit Field
Name
Length
Read/Write
Description
INT_CR_CLR
RO
A read operation of this register will
31:0
32
clear the bit[0] in register 0x54.
DMA Command Register
This register is used to control the internal DMA controller of the AC97. The DMA controller is described in
detail in the following section.
Offset address: 0x100
Reset value: 00000000h
Table 264. DMA command register
Bit Field
Name
Read/Write
Description
ask_addr
R/W
63:5
bit[63:5] of the DMA descriptor address,
the lower 5 bits are 0.
Reserved
R/W
Reserved.
5
4
dma_stop
R/W
Stop DMA operation. The DMA controller
stops when it has completed reading or
writing the current data.
3
dma_start
R/W
Start DMA operation. The DMA controller
reads the descriptor address (ask_addr)
and then clears some bits to zero.
177
Bit Field
Name
Read/Write
Description
2
ask_valid
R/W
The DMA working register is written back to
the memory pointed to by (ask_addr) and
cleared to zero when finished.
1
Reserved
R/W
Reserved.
dma_64bit
R/W
DMA controller 64-bit address support.
0
20.3. DMA Controller
20.3.1. Description of DMA Controller Structure
The bridge contains 2 DMA controllers for data migration between memory and AC97, which can save
resources and improve the efficiency of system data transfer. This saves resources and improves the
efficiency of system data transfer.
The process of transporting data by DMA consists of three stages.
1. Pre-processing before transport: The CPU configures the registers related to the DMA descriptor.
2. Data transport: done automatically under the control of the DMA controller.
3. End-of-transport processing: sending an interrupt request.
This DMA controller is limited to data handling in words (4-byte).
The DMA controller supports 64-bit address space, which is mainly controlled by dma_64bit. When this bit
is set to 1, it means that the DMA controller works in 64-bit address space, and vice versa for 32-bit
address space. In 64-bit address mode, it is necessary to extend DMA_ORDER_ADDR and DMA_SADDR to 64-
bit registers.
20.3.2. DMA Descriptor
DMA_ORDER_ADDR_LOW
Offset address: 0x0
Reset value: 0x00000000
Table 265. DMA_ORDER_ADDR_LOW
Bit Field
Name
Length
Read/Write
Description
31:1
dma_order_addr
31
R/W
Memory internal next descriptor
address register (low 32 bits).
Dma_order_en
R/W
Whether the descriptor is a valid
0
1
signal.
Description: Store the address of the next DMA descriptor. dma_order_en is the enable bit of the next
DMA descriptor. If this bit is 1, the next descriptor is valid; if this bit is 0, the next descriptor is invalid and
no operation is performed. When the DMA descriptor is configured, this register holds the address of the
next descriptor. After the DMA operation is performed, the dma_order_en signal is used to determine
whether to start the next DMA operation. In 64-bit address mode, this register stores the low 32-bit address.
DMA_SADDR
178
Offset address: 0x4
Reset value: 0x00000000
Table 266. DMA_SADDR
Bit Field
Name
Length
Read/Write
Description
31:0
dma_saddr
32
R/W
System memory address for DMA
operations (low 32 bits).
Description: DMA operations are divided into Memory Read and Memory Write. Memory Read: reads data
from memory, saves it in the DMA controller’s cache, and then writes it to the AC97 device; this register
specifies the address of the read memory. Memory Write: Read data from AC97 device is saved in the DMA
cache, and when the data in the DMA cache exceeds a certain number, it is written to the memory, and this
register specifies the address of the write memory. In 64-bit address mode, this register stores the low 32-
bit address.
DMA_DADDR
Offset address: 0x8
Reset value: 0x00000000
Table 267. DMA_DADDR
Bit Field
Name
Length
Read/Write
Description
31
AC97_wr_en
1
R/W
AC97 write enable. 1: Indicate a write
operation.
AC97_mode
R/W
30
1
0: mono
1: 2 stero
29:28
AC97_wr_mode
2
R/W
AC97 write mode.
0: 1-byte
1: 2-byte
2: 4-byte
dma_daddr
R/W
AC97 device address for DMA
27:0
28
operation.
DMA_LENGTH
Offset address: 0xc
Reset value: 0x00000000
Table 268. DMA_LENGTH
Bit Field
Name
Length
Read/Write
Description
dma_length
R/W
Transport data length register.
31:0
32
Description: Represents the length of a piece of content to be carried, in words. When the length of the
179
word has been carried, the next step is started, i.e. the next loop. When a new loop is started, the length of
data is carried again. When step becomes 1, the single DMA descriptor operation ends and the next
descriptor is read.
DMA_STEP_LENGTH
Offset address: 0x10
Reset value: 0x00000000
Table 269. DMA_STEP_LENGTH
Bit Field
Name
Length
Read/Write
Description
31:0
dma_step_length
32
R/W
Data transport interval length register.
Description: The length of the interval between two blocks of memory data being carried, the interval
between the end address of the previous step and the start address of the next step.
DMA_STEP_TIMES
Offset address: 0x14
Reset value: 0x00000000
Table 270. DMA_STEP_TIMES
Bit Field
Name
Length
Read/Write
Description
31:0
dma_step_times
32
R/W
Data transport cycle count register.
Description: The number of cycles indicates the number of blocks to be carried in a single DMA operation.
If you want to carry only one consecutive block, the value of the cycle count register can be assigned to 1.
DMA_CMD
Offset address: 0x18
Reset value: 0x00000000
Table 271. DMA_CMD
Bit Field
Name
Length
Read/Write
Description
14:13
Dma_cmd
2
R/W
Source and destination address
generation method.
dma_r_w
R/W
12
1
DMA operation type, 1 is read ddr2
write device, 0 is read device write
ddr2.
dma_write_state
R/W
DMA write data status.
11:8
4
7:4
dma_read_state
4
R/W
DMA read data status.
3
dma_trans_over
1
R/W
The DMA has executed all the
configured descriptor operations.
dma_single_trans_over
R/W
The DMA has executed a descriptor
2
1
operation.
180

 

 

 

 

 

 

 

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