Loongson 7A1000 Bridge User Manual. Loongson Technology Corporation Limited Version 2.00

Bit Field

Name

Length

Read/Write

Description

dma_int

R/W

DMA interrupt signal.

dma_int_mask

R/W

Whether DMA interrupts are masked.

Description: dma_single_trans_over=1 means the end of one DMA operation, when length=0 and

step_times=1, the descriptor of the next DMA operation will be taken. The descriptor address of the next

DMA operation is stored in the DMA_ORDER_ADDR register. If dma_order_en=0 in the DMA_ORDER_ADDR

descriptors to read. If dma_order_en=1, then dma_trans_over is set to 0 and the next dma descriptor is

read. dma_int is the interrupt of the DMA, which occurs after a configured DMA operation if there is no

interrupt mask. The CPU can set it low directly after processing the interrupt, or it can wait until the DMA

makes its next transfer. dma_int_mask is the interrupt mask for the corresponding dma_int.

dma_read_state describes the current read state of the DMA. dma_write_state describes the current

write state of the DMA.

The DMA write state (WRITE_STATE[3:0]) describes that the DMA includes the following write states.

Table 272. DMA write state

Write_state

[3:0]

Description

Write state is in idle state

Write_idle

4’h0

Dma determines that it needs to perform a read device write

W_ddr_wait

4’h1

memory operation and initiates a write memory request, but the

memory is not ready to respond to the request, so dma keeps

waiting for a response from the memory

Memory has received a dma write request, but has not yet

Write_ddr

4’h2

finished executing the write operation

Write_ddr_end

4’h3

The memory receives the dma write request and completes the

write operation, at which point the dma is in the write memory

operation complete state

Write_dma_wait

4’h4

Dma sends a request to write the dma status register back to

memory and waits for memory to receive the request

Memory receives a write dma status request, but the operation is

Write_dma

4’h5

not yet complete

Write_dma_end

4’h6

Memory completes write dma status operation

Dma completes a length length operation (i.e. completes a step)

Write_step_end

4’h7

The DMA read state (READ_STATE[3:0]) describes that the DMA includes the following read states.

Table 273. DMA read state

Read_state

[3:0]

Description

Read state is in idle state

Read_idle

4’h0

After receiving the start signal to start the dma operation, enter

Read_ready

4’h1

the ready state and start reading the descriptor

Issue a read descriptor request to memory and wait for a memory

Get_order

4’h2

answer

Read_order

4’h3

Memory receives a read descriptor request and is performing a

read operation

181

Read_state

[3:0]

Description

Finish_order_end

4’h4

Memory read out dma descriptor

Dma sends a read data request to memory and waits for a

R_ddr_wait

4’h5

memory answer

Read_ddr

4’h6

Memory receives dma read data request and is performing read

data operation

Memory completes a read data request from dma

Read_ddr_end

4’h7

Read_dev

4’h8

Dma enters read device status

Read_dev_end

4’h9

The device returns read data, ending the read device request

Read_step_end

4’ha

End a step operation, step times minus 1

DMA_ORDER_ADDR_HIGH

Offset address: 0x20

Reset value: 0x00000000

Table 274. DMA_ORDER_ADDR_HIGH

Bit Field

Name

Length

Read/Write

Description

31:0

dma_order_addr

R/W

Memory internal next descriptor

address register (high 32 bits)

DMA_SADDR_HIGH

Offset address: 0x24

Reset value: 0x00000000

Table 275. DMA_SADDR_HIGH

Bit Field

Name

Length

Read/Write

Description

31:0

dma_saddr

R/W

Memory address for DMA operation

(high 32 bits)

182

Chapter 21. SATA Controller (D8:F0/1/2)

The features of SATA are as follows.

•

Supports SATA Generation 1 at 1.5Gbps and SATA Generation 2 at 3Gbps

• Compatible with Serial ATA 2.6 specification and AHCI 1.1 specification

21.1. SATA Configuration Register (D8:F0/1/2)

Table 276. SATA controller configuration registers

Address

Abbreviatio

Description

Default value

Read/Write

Offset

00h-01h

Vendor ID

VID

0014h

02h-03h

Device ID

DID

7A08h

04h-05h

PCICMD

PCI Command

0000h

R/W, RO

08h

Revision ID

RID

00h

09h

Programming Interface

01h

0Ah

SCC

Sub Class Code

06h

0Bh

Base Class Code

BCC

01h

0Ch

Cache Line Size

CLS

00h

0Eh

HEADTYP

Header Type

80h

10h-17h

Control Base Address Register

R/W, RO

CNL_BAR

0000000000000004h

2Ch-2Dh

Subsystem Vendor ID

SVID

0000h

2Eh-2Fh

SID

Subsystem Identification

0000h

3Ch

Interrupt Line

R/W

INT_LN

00h

3Dh

Interrupt Pin

INT_PN

01h

Note: Address space not listed in the table indicates reserved.

Registers that differ slightly from the PCI configuration header specification and their descriptions are

listed below.

PCICMD - PCI Command Register (SATA - D8:F0/1/2)

Address Offset: 04-05h

Attribute: R/W, RO

Default value: 0000h

Size: 16 bits

Table 277. PCI command register

183

Bit Field

Name

Read/Write

Description

15:2

Reserved

Reserved.

R/W

This bit is used to control whether access to

Memory Space Enable

the SATA control registers is enabled.

0: Disable access.

1: Enable access to the SATA control

registers. The BAR register must be

configured before this bit can be configured

to 1.

Reserved.

Reserved

CNL_BAR - Control Base Address Register

This register is used to configure the base address of the control registers of the SATA controller.

Address Offset: 10-13h

Attribute: R/W, RO

Default value: 00000004h

Size: 32 bits

Table 278. Control base address register

Bit Field

Name

Read/Write

Description

The software writes to this register field the

31:13

Base Address

low address of the base address allocated to

the SATA control register.

The address space size of SATA control

12:4

Memory Size

Prefetchable Memory

Set to 0 to indicate that it is not

prefetchable.

2:1

Memory Type

Set to 10b to indicate 64-bit BAR.

Memory/ I/O Space

Set to 0 to indicate Memory space BAR.

Address Offset: 14-17h

Attribute: R/W

Default value: 00000000h

Size: 32 bits

Table 279. Control base address register

Bit Field

Name

Read/Write

Description

31:0

Base Address

The software writes to this register field the

high 32-bit address of the base address

allocated to the SATA control register.

184

21.2. Description of SATA Control Register

The base address of SATA is given by BAR0 of SATA and the register definition is identical to the protocol

standard definition.

Table 280. List of SATA control registers

Address

Length

Name

Description

Offset

HBA characteristic register

0x000

CAP

Global HBA control register

0x004

GHC

0x008

Interrupt status register

Port register

0x00c

AHCI version register

0x010

0x014

CCC_CTL

Command completion merge control

Command completion merge port

0x018

CCC_PORTS

0x024

CAP2

HBA characteristic expansion register

BIST active FIS

0x0A0

BISTAFR

BIST control register

0x0A4

BISTCR

0x0A8

BISTCTR

BIST FIS count register

BIST status register

0x0AC

BISTSR

BIST double word error count register

0x0B0

BISTDECR

0x0BC

OOBR

OOB register

0x0E0

TIMER1MS

1ms count register

0x0E8

GPARAM1R

Global parameter register 1

Global parameter register 2

0x0EC

GPARAM2R

0x0F0

PPARAMR

Port parameter register

0x0F4

TESTR

Test register

Version register

0x0F8

VERIONR

0x0FC

IDR

ID register

0x100

P0_CLB

Command list base address low 32

bits

Command list base address high 32

0x104

P0_CLBU

bits

FIS base address low 32 bits

0x108

P0_FB

FIS base address high 32 bits

0x10c

P0_FBU

0x110

P0_IS

Interrupt status register

Interrupt enable register

0x114

P0_IE

Command register

0x118

P0_CMD

185

Address

Length

Name

Description

Offset

Task file data register

0x120

P0_TFD

0x124

P0_SIG

Signature register

SATA status register

0x128

P0_SSTS

SATA control register

0x12C

P0_SCTL

0x130

P0_SERR

SATA error register

SATA active register

0x134

P0_SACT

Command send register

0x138

P0_CI

0x13C

P0_SNTF

SATA command notification register

DMA control register

0x170

P0_DMACR

PHY control register

0x178

P0_PHYCR

0x17C

P0_PHYSR

PHY status register

Command list base address low 32

0x180

P1_CLB

bits

Command list base address high 32

0x184

P1_CLBU

bits

FIS base address low 32 bits

0x188

P1_FB

FIS base address high 32 bits

0x18c

P1_FBU

0x190

P1_IS

Interrupt status register

Interrupt enable register

0x194

P1_IE

Command register

0x108

P1_CMD

0x1a0

P1_TFD

Task file data register

Signature register

0x1a4

P1_SIG

SATA status register

0x1a8

P1_SSTS

0x1aC

P1_SCTL

SATA control register

SATA error register

0x1b0

P1_SERR

SATA active register

0x1b4

P1_SACT

0x1b8

P1_CI

Command send register

SATA command notification register

0x1bC

P1_SNTF

DMA control register

0x1f0

P1_DMACR

0x1f8

P1_PHYCR

PHY control register

PHY status register

0x1fC

P1s_PHYSR

186

Chapter 22. PCIE Controller (D9:F0, D10:F0,

D11:F0, D12:F0, D13:F0, D14:F0, D15:F0,

D16:F0, D17:F0, D18:F0, D19:F0, D20:F0)

The PCIEs of the bridge chip are divided into 5 groups: PCIE_F0, PCIE_F1, PCIE_H, PCIE_G0, PCIE_G1,

with a total of 32 lanes. Each group of PCIE interfaces has its own corresponding control port. The bridge

contains 12 PCIE control ports (ports), namely port 0, port 1, port 2, port 3 of PCIE_F0, port 0, port 1 of

PCIE_F1, port 0, port 1 of PCIE_G0, port 0, port 1 of PCIE_G1, port 0, port 1 of PCIE_H, port 1 of PCIE_H.

Each port corresponds to a PCIE controller, and each PCIE controller contains a TYPE1 type PCI

configuration header.

PCIE_F0 includes 4 lanes and can be used as one x4 PCIE or 4 x1 PCIEs. Among them, port 0 controls

lane0 in non x4 mode, port 0 controls lane0, and lane0-3 in x4 mode. In non-x4 mode, port 1 controls lane1,

port In non-x4 mode, port 1 controls lane1, port 2 controls lane2, and port 3 controls lane3.

PCIE_F1 includes 4 lanes, which can be used as one x4 PCIE or 2 x1 PCIEs. Among them, port 0 controls

lane0 in non lane0 in non-x4 mode and lane0-3 in x4 mode. In non-x4 mode, port 1 controls lane1, lane2 and

lane3 are not available.

PCIE_H includes 8 lanes and can be used as one x8 PCIE or 2 x4 PCIEs. Among them, port 0 controls

lane0-3 in non port 0 controls lane0-3 in non-x8 mode and lane0-7 in x8 mode. In non-x8 mode, port 1

controls lane4-7.

PCIE_G0 includes 8 lanes, which can be used as one x8 PCIE or two x4 PCIEs. Among them, port 0

controls lane4-7 in Port 0 controls lane0-3 in non-x8 mode and lane0-7 in x8 mode. In non-x8 mode, port 1

controls lane4-7.

PCIE_G1 includes 8 lanes, which can be used as one x8 PCIE or two x4 PCIEs. Among them, port 0

controls lane4-7 in port 0 controls lane0-3 in non-x8 mode and lane0-7 in x8 mode. In non-x8 mode, port 1

controls lane4-7.

The PCIE controller of the bridge chip can be used only as RC, not as EP.

The configuration methods supported by PCIE and the corresponding control ports are shown in the tables

below.

Table 281. Configuration methods and control ports supported by PCIE_F0

lane0

lane1

lane2

lane3

x4 (P0)

x1 (P0)

x1 (P1)

x1 (P2)

x1 (P3)

Table 282. Configuration methods and control ports supported by PCIE_F1

lane0

lane1

lane2

lane3

x4 (P0)

x1 (P0)

x1 (P1)

Table 283. Configuration methods and control ports supported by PCIE_G0, PCIE_G1 and PCIE_H

lane0

lane1

lane2

lane3

lane4

lane5

lane6

lane7

x8 (P0)

187

x4 (P0)

x4 (P1)

22.1. PCI Configuration Register

The following table lists the configuration header defaults for PCIE ports, the Device ID may be different for

different ports, all other fields are the same.

Table 284. PCIE controller configuration registers

Address

Abbreviatio

Description

Default value

Read/Write

Offset

00h-01h

VID

Vendor ID

0014h

02h-03h

Device ID

See description of

DID

registers

04h-05h

PCICMD

PCI Command

0000h

R/W, RO

06h-07h

PCI Status

PCISTS

0010h

08h

Revision ID

RID

01h

09h

Programming Interface

00h

0Ah

Sub Class Code

SCC

04h

0Bh

Base Class Code

BCC

06h

0Ch

CLS

Cache Line Size

00h

0Dh

PLT

Primary Latency Timer

00h

0Eh

Header Type

HEADTYP

01h

10h-17h

CNL_BAR

Control Block Base Address Register

0000000000000004h

R/W, RO

18h

PBNUM

Primary Bus Number

00h

R/W

19h

Secondary Bus Number

R/W

SBNUM

00h

1Ah

SUBNUM

Subordinate Bus Number

00h

R/W

1Bh

SLT

Secondary Latency Timer

00h

1Ch

I/O Base

R/W

IOBASE

01h

1Dh

IOLMT

I/O Limit

01h

R/W

1Eh-1Fh

SSTS

Secondary Status

0000h

20h-21h

Memory Base

R/W

MBASE

0000h

22h-23h

MLMT

Memory Limit

0000h

R/W

25h-24h

PMBASE

Prefetchable Memory Base

0000h

R/W

27h-26h

Prefetchable Memory Limit

R/W

PMLMT

0000h

28h-2Bh

Prefetchable Memory Base Upper 32

R/W

PMBU32

00000000h

Bits

2Ch-2Fh

Prefetchable Memory Limit Upper 32

R/W

PMLU32

00000000h

Bits

30h-31h

IOBU

I/O Base Upper 16 Bits

0000h

R/W

32h-33h

I/O Limit Upper 16 Bits

R/W

IOLMTU

0000h

188

Address

Abbreviatio

Description

Default value

Read/Write

Offset

34h

Capabilities Pointer

CAPP

40h

3Ch

INT_LN

Interrupt Line

FFh

R/W

3Dh

Interrupt Pin

INT_PN

01h

3Eh-3Fh

Bridge Control Register

R/W

BCTRL

0000h

Note: Address space not listed in the table indicates reserved.

Registers that differ slightly from the PCI configuration header specification and their descriptions are

listed below.

DID - Device Identity Register (PCIE)

Address Offset: 02-03h

Attribute: RO

Default value: See description

Size: 16 bits

Table 285. Device identity register

Bit Field

Name

Read/Write

Description

15:0

DID

PCIE device identity register. The

corresponding DID of each PCIE port is

shown in the following table.

Table 286. Table of DID of PCIE port

PCI Device Number

Description

Device Identity Register

D9:F0

PCIE_F0 port 0

7A19h

D10:F0

PCIE_F0 port 1

7A09h

D11:F0

PCIE_F0 port 2

7A09h

D12:F0

PCIE_F0 port 3

7A09h

D13:F0

PCIE_F1 port 0

7A19h

D14:F0

PCIE_F1 port 1

7A09h

D15:F0

PCIE_G0 port 0

7A29h

D16:F0

PCIE_G0 port 1

7A19h

D17:F0

PCIE_G1 port 0

7A29h

D18:F0

PCIE_G1 port 1

7A19h

D19:F0

PCIE_H port 0

7A29h

D20:F0

PCIE_H port 1

7A19h

Note:

189

1. The correct value of the subclass code for all PCIE controllers integrated in the bridge should be 0x04

for the PCI-to-PCI bridge, but this bridge incorrectly implements this value as 0x00 (for the Host bridge).

The software needs to ignore this bit field and still handle the bridge-integrated PCIE controllers as PCI-

to-PCI bridges, see Notes on the Use of the Software.

2. Only one device (Device 0) can be mounted on the bus below all PCIE controllers integrated in the

bridge, but when the software scans the PCIE bus for non-Device 0 devices, this PCIE controller will

return the information of Device 0, causing Device 0 to be discovered repeatedly. Therefore, the

software must not actively scan for non-Device 0 devices below the PCIE controller, see Notes on the

Use of the Software.

22.2. Address Space Division

The PCIE controller in the bridge has a standard PCIE configuration header, so the internal registers of the

PCIE controller and the address space of its downstream devices are managed by the information in its

configuration header. The address-related registers in the configuration header are determined during the

PCI device scan.

Because the bridge’s PCIE controller can only operate in RC mode, its configuration header is of type

TYPE1.

Each PCIE port acts as a separate device in the bridge slice, and each port contains a PCIE configuration

header. When the PCIE is operating in X4 mode, the port software for the other X1 is not visible, and the

other X1 ports are only accessible when the PCIE is operating in X1 mode.

For each PCIE port, the address space can be divided into the following parts.

Configuration header address space: This part of the space corresponds to the configuration header of the

PCIE and is accessed through configuration requests up to 4KB. See Access Address of the PCI

Configuration for accessing address space above 256B.

Configuration Access Address Space: This portion of the address space is used to access the PCIE

controller’s downstream device configuration header information via configuration requests. Depending on

the Bus number of the downstream device, it is up to the PCIE controller to decide whether to send a TYPE0

type or TYPE1 type configuration access.

The addresses of the above two address spaces are calculated from the configuration address space base

address, BUS number, device number, function number, and register offset address, and can be accessed

by word.

PCIE controller internal register space: This part of the address space is used to access the internal

registers of the PCIE controller. These registers are used to control the behavior and characteristics of the

PCIE controller and belong to two address spaces with the PCIE configuration header space. This address

space is of type MEM, 64-bit address space, 4KB in size, with a base address equal to the value of 64-bit

BAR0, which is assigned by the PCI scan software during initialization.

MEM address space: This part of the address space contains all the MEM address space of the devices

downstream of the PCIE controller. For the 32-bit address space, this is determined by the memory base

and memory limit of the PCIE configuration header. For the 64-bit address space, this is determined by the

prefetchable memory base (combined upper 32 bits) and prefetchable memory limit (combined upper 32

bits) of the PCIE configuration header. This address space is enabled and controlled by the command

I/O address space: This part of the address space contains all the I/O address space of the devices

downstream of the PCIE controller. It is determined by the IO base (combined upper 16 bits) and IO limit

(combined upper 16 bits) of the PCIE configuration header. This address space is enabled and controlled

by the command register bit0 of the PCIE configuration header.

For the MEM address space and I/O address space, if there is no device connected downstream of an X1

190

port in X1 operation mode, the MEM and I/O address space can be disabled by setting bit0 and bit1 of

the command register to 0.

PCIE Controller Enable

General configuration register 0 of the bridge configuration register contains the enable bits for the PCIE

controller. It needs to be enabled when using the corresponding PCIE controller in order to access all

address spaces of that controller and downstream devices, including configuration access to the

controller.

22.3. Special Notes

PCIE Capability

The maximum MPS (Max Payload Size) and MRRS (Max Read Request Size) supported by the integrated

PCIE controller of the bridge are both 256 bytes. The MPS setting can be set under the BIOS through the

PCI negotiation mechanism. Since there is no negotiation mechanism for MRRS, BIOS developers need to

set the MRRS value of the device to a value no larger than 256 bytes.

PCIE MSI

On 3A+7A systems, the destination address for PCI MSI interrupts is 0xfdf8000000 or 0x2ff00000. The

bridge converts the MSI message packets sent by the device to these two address segments into HT

interrupt message packets and sends them to the processor.

PCIE Controller Performance

The PCIE controllers integrated in the bridge are x8, x4, and x1. The P0 control port of PCIE_G0/G1/H is the

x8 controller, the P0 port of PCIE_F0/F1 and the P1 port of PCIE_G0/G1/H are the x4 controllers, and the

P1/P2/P3 port of PCIE_F0 and the P1 port of PCIE_F1 are the x1 controllers.

These three controllers have different numbers of internal flow-controlled buffers, with x8, x4, and x1

controllers decreasing in order, so for some high-bandwidth PCIE devices, using a controller with a larger

number of flow-controlled buffers for the same data width will result in a performance improvement.

Therefore, it is recommended to give preference to controllers with larger number of flow control buffers.

191

Chapter 23. SPI Controller (D22:F0)

23.1. SPI Configuration Register (D22:F0)

Table 287. SPI controller configuration registers

Address

Abbreviatio

Description

Default value

Read/Write

Offset

00h-01h

Vendor ID

VID

0014h

02h-03h

DID

Device ID

7A0Bh

04h-05h

PCICMD

PCI Command

0000h

R/W, RO

08h

Revision ID

RID

00h

09h

Programming Interface

00h

0Ah

SCC

Sub Class Code

08h

0Bh

Base Class Code

BCC

80h

0Ch

CLS

Cache Line Size

00h

0Eh

HEADTYP

Header Type

00h

10h-17h

Control Base Address Register

R/W, RO

CBAR

0000000000000004h

18h-1Fh

MBAR

Memory Base Address Register

0000000000000004h

R/W, RO

2Ch-2Dh

SVID

Subsystem Vendor ID

0000h

2Eh-2Fh

Subsystem Identification

SID

0000h

3Ch

Interrupt Line

R/W

INT_LN

00h

3Dh

INT_PN

Interrupt Pin

01h

Note: Address space not listed in the table indicates reserved.

Registers that differ slightly from the PCI configuration header specification and their descriptions are

listed below.

PCICMD - PCI Command Register (SPI - D22:F0)

Address Offset: 04-05h

Attribute: R/W, RO

Default value: 0000h

Size: 16 bits

Table 288. PCI command register

Bit Field

Name

Read/Write

Description

Reserved.

15:2

Reserved

192

Bit Field

Name

Read/Write

Description

Memory Space Enable

R/W

This bit is used to control whether access to

the SPI control registers and SPI memory

space is enabled.

0: Disable access.

1: Enable access to the SPI control registers

and SPI memory space. The BAR register

must be configured before this bit can be

configured to 1.

Reserved

Reserved.

The SPI controller consists of two address spaces: the control register space and the memory space.

CNL_BAR - Control Base Address Register

This register is used to configure the base address of the control registers of the SPI controler.

Address Offset: 10-13h

Attribute: R/W, RO

Default value: 00000004h

Size: 32 bits

Table 289. Control base address register

Bit Field

Name

Read/Write

Description

31:12

Base Address

The software writes to this register field the

low address of the base address allocated to

the SPI controller.

The address space size of SPI controller is

11:4

Memory Size

4KB.

Prefetchable Memory

Set to 0 to indicate that it is not

prefetchable.

2:1

Memory Type

Set to 10b to indicate 64-bit BAR.

Memory/ I/O Space

Set to 0 to indicate Memory space BAR.

Address Offset: 14-17h

Attribute: R/W

Default value: 00000000h

Size: 32 bits

Table 290. Control base address register

193

Bit Field

Name

Read/Write

Description

31:0

Base Address

The software writes to this register field the

high 32-bit address of the base address

allocated to the SPI controller.

MBAR - MEM Space Base Address Register

This register is used to configure the MEM space base address of the SPI controller.

Address Offset: 18-1Bh

Attribute: R/W, RO

Default value: 00000004h

Size: 32 bits

Table 291. MEM space base address register

Bit Field

Name

Read/Write

Description

The software writes to this register field the

31:24

Base Address

bit[31:24] of the base address allocated

to the SPI MEM space.

23:4

Memory Size

The SPI MEM space size is 16MB.

Prefetchable Memory

Set to 0 to indicate that it is not

prefetchable.

2:1

Memory Type

Set to 10b to indicate 64-bit BAR.

Memory/ I/O Space

Set to 0 to indicate Memory space BAR.

Address Offset: 1C-1Fh

Attribute: R/W

Default value: 00000000h

Size: 32 bits

Table 292. MEM space base address register

Bit Field

Name

Read/Write

Description

The software writes to this register field the

31:0

Base Address

high 32-bit address of the base address

allocated to the SPI MEM space.

23.2. SPI Control Register

Table 293. List of SPI control registers

Address Offset

Name

Description

SPCR

Control register

Status register

SPSR

194

Address Offset

Name

Description

TxFIFO/RxFIFO

Data register

External register

SPER

Parameter control register

SFC_PARAM

SFC_SOFTCS

Chip select control register

Timing control register

SFC_TIMING

Control Register (SPCR)

Offset address: 0x0

Table 294. Control register

Bit Field

Name

Read/Write

Initial Value

Description

spie

R/W

Interrupt output enable signal (active

high)

R/W

System operation enable signal (active

spe

high)

Reserved

master mode select bit. This bit is

mstr

always held 1

R/W

Clock polarity bits

cpol

R/W

cpha

Clock phase. 1 is opposite phase, and

0 is same

1:0

spr

R/W

sclk_o frequency division

configuration. It need to be used with

sper's `spre

Status Register (SPSR)

Offset address: 0x1

Table 295. Status register

Bit Field

Name

Read/Write

Initial Value

Description

spif

R/W

Interrupt flag. 1 indicates an interrupt

request, write 1 to clear

wcol

R/W

Write register overflow flag bit. 1

indicates overflowed, write 1 to clear

Reserved

5:4

Reserved

wffull

Write register full. 1 indicates full

wfempty

Write register empty. 1 indicates

empty

rffull

Read register full. 1 indicates full

rfempty

Read register empty. 1 indicates empty

195

Data Register (TxFIFO/RxFIFO)

Offset address: 0x2

Table 296. Data register

Bit Field

Name

Read/Write

Initial Value

Description

W RO

7:0

TxFIFO RxFIFO

Data transporting port.

Data receiving port

External Register (SPER)

Offset address: 0x3

Table 297. External register

Bit Field

Name

Read/Write

Initial Value

Description

R/W

Bytes transferred before sending an

7:6

icnt

interrupt.

00: 1

01: 2

10: 3

11: 4

Reserved

5:3

mode

R/W

SPI interface mode control

0: Sampling and transporting timing

are simultaneous

1: Sampling and transporting timing

staggered by half a cycle

1:0

spre

R/W

Set the ratio of the frequency division

together with spr

Table 298. SPI Frequency Division Factor

spre

spr

Frequency

128

256

512

1024

2048

4096

Division

Factor

Parameter Control Register (SFC_PARAM)

Offset address: 0x4

Table 299. Parameter control register

196

Bit Field

Name

Read/Write

Initial Value

Description

7:4

clk_div

R/W

Clock division number selection.

The frequency division factor is the

same as the combination of {spre,

spr}

dual_io

R/W

Dual I/O mode with higher priority than

fast read

R/W

Fast Read Mode

fast_read

burst_en

R/W

SPI flash supports sequential address

read mode

R/W

SPI flash read enable. When disabled,

memory_en

csn[0] can be controlled by software

Chip Select Control Register (SFC_SOFTCS)

Offset address: 0x5

Table 300. Chip select control register

Bit Field

Name

Read/Write

Initial Value

Description

7:4

csn

R/W

csn pin output value

3:0

csen

R/W

When the bit is 1, the csn line of the

corresponding bit is controlled by 7:4

bits

Timing Control Register (SFC_TIMING)

Offset address: 0x6

Table 301. Timing control register

Bit Field

Name

Read/Write

Initial Value

Description

Reserved

7:3

tFAST

R/W

SPI flash read sampling mode

0: Rising edge sampling, half SPI cycle

interval

1: Rising edge sampling with one SPI

cycle interval

197

Bit Field

Name

Read/Write

Initial Value

Description

1:0

tCSH

R/W

The minimum invalidation time of the

SPI Flash’s chip select signal, in terms

of the clock period after frequency

division.

Calculation of T

00: 1T

01: 2T

10: 4T

11: 8T

23.3. SPI Software Programming Guide

Read and Write Operations of the SPI Host Controller

Module Initialization

Stop SPI controller operation, write 0 to the spe bit of control register spcr.

Reset the status register spsr and write 1100_0000b to the register.

Set the external register sper, including the interrupt request condition sper[7:6] and the dividing

factor sper[1:0], refer to the register description for details.

Configure SPI timing, including cpol, cpha of spcr and mode of sper. mode is 1 for standard SPI

implementation and 0 for compatible mode.

Configure interrupt enable, spie bit of spcr.

Start the SPI controller and write 1 to the spe bit of the control register spcr.

Send/transport Operations of the Module

1. Write data to the data transport register.

2. Since transporting and receiving occur simultaneously, the SPI slave device must perform a readout

operation even if no valid data is sent.

Interrupt Handling

1. Receive the interrupt request.

Read the value of status register spsr, if spsr[2] is 1, it means data transport is completed, if

spsr[0] is 1, it means data has been received.

3. Read or write the data transport register.

Write 1 to the spif bit of status register spsr to clear the controller’s interrupt request.

Hardware SPI Flash Read

Initialization

Write 1 to the memory_en bit of SFC_PARAM.

198

Chapter 24. LPC Controller (D23:F0)

The LPC controller has the following features.

• Compliant with LPC1.1 specification

• Supports LPC access timeout counter

• Supports Memory Read/Write access type

• Supports Firmware Memory Read/Write access type (single byte)

• Support I/O read/write access type

• Support TPM I/O read/write access type

• Support Memory access type address conversion

• Support Serial IRQ specification, support 17 interrupt sources

24.1. LPC Configuration Register (D23:F0)

Table 302. LPC controller configuration registers

Address

Abbreviatio

Description

Default value

Read/Write

Offset

00h-01h

VID

Vendor ID

0014h

02h-03h

Device ID

DID

7A0Ch

04h-05h

PCICMD

PCI Command

0001h

R/W, RO

08h

RID

Revision ID

00h

09h

Programming Interface

00h

0Ah

Sub Class Code

SCC

01h

0Bh

BCC

Base Class Code

06h

0Ch

Cache Line Size

CLS

00h

0Eh

Header Type

HEADTYP

00h

10h-17h

FIXCREG*

Fixed Control Register

0000000010002004h

18h-1Fh

Fixed Memory Register

FIXMREG*

0000000012000004h

20h-27h

Fixed I/O Register

FIXIOREG*

000000FDFC000001h

2Ch-2Dh

SVID

Subsystem Vendor ID

0000h

2Eh-2Fh

Subsystem Identification

SID

0000h

3Ch

Interrupt Line

R/W

INT_LN

00h

3Dh

INT_PN

Interrupt Pin

01h

Note: Address space not listed in the table indicates reserved.

* See the subsequent FIXCREG/FIXMREG/FIXIOREG and Appendix 2 for more information.

Registers that differ slightly from the PCI configuration header specification and their descriptions are

listed below.

200

PCICMD - PCI Command Register (LPC - D23:F0)

Address Offset: 04-05h

Attribute: R/W, RO

Default value: 0000h

Size: 16 bits

Table 303. PCI command register

Bit Field

Name

Read/Write

Description

15:2

Reserved

Reserved.

Memory Space Enable

R/W

This bit is used to control whether access to

the LPC control registers and MEM space is

enabled.

0: Disable access.

1: Enable access to the LPC control registers

and MEM space

R/W

This bit is used to control whether access to

I/O Space Enable

the LPC I/O space is enabled. The address

of the LPC I/O space is fixed starting from

address 0 of the I/O space.

0: Disable access.

1: Enable access to the LPC I/O space.

FIXCREG - Fixed Control Register

This register is not used as the BAR of the LPC configuration header.

Address Offset: 10-17h

Attribute: RO

Default value: 0000000010002004h

Size: 64 bits

Table 304. Fixed control register

Bit Field

Name

Read/Write

Description

Reserved.

63:0

Reserved

FIXMREG - Fixed MEM Register

This register is not used as the BAR of the LPC configuration header.

Address Offset: 18-1Fh

Attribute: RO

201

Default value: 0000000012000004h

Size: 64 bits

Table 305. Fixed MEM register

Bit Field

Name

Read/Write

Description

Reserved.

63:0

Reserved

FIXIOREG - Fixed I/O Register

This register is not used as the BAR of the LPC configuration header.

Address Offset: 20-27h

Attribute: RO

Default value: 000000FDFC000001h

Size: 64 bits

Table 306. Fixed I/O register

Bit Field

Name

Read/Write

Description

Reserved.

63:0

Reserved

The addresses of FIXCREG, FIXMREG, and FIXIOREG are the same as the BAR registers of the PCI

configuration header, but these registers are not used as the BAR registers of the LPC configuration

header. Software can work around this hardware bug by modifying the PCI configuration read function so

that the upper layer software is not affected. See Notes on the Use of the Software for more details.

24.2. LPC Access Address

The LPC controller consists of three address spaces: the control register space, the MEM space, and the

I/O space.

The LPC control register space is used to configure the LPC controller, which is located in the fixed device

address space of the bridge chip, starting at 0x1000,2000, with a size of 4KB.

The LPC MEM space is used to access the Memory/Firmware Memory devices mounted on the LPC bus.

The LPC MEM space is located in the fixed device address space of the bridge chip starting at

0x1200,0000 and is 32MB in size. Processor accesses to the LPC MEM space are converted to LPC

protocol Memory accesses and sent to the LPC bus. Which type of Memory access is issued by the LPC

controller is determined by the LPC controller’s control registers. Addresses sent by the processor to this

address space can be address converted. The converted address is set by the LPC controller’s

configuration register (LPC_MEM_TRANS).

24.3. LPC Interrupt

The LPC controller internally includes two types of interrupts: SIRQ interrupts and access timeout

interrupts. The LPC controller supports a total of 17 SIRQ interrupts, corresponding to the bits[16:0] of

the interrupt-related register. The access timeout interrupt corresponds to the bit[17] of the interrupt-

related register.

The SIRQ interrupt is a level-triggered interrupt, and the value of the trigger level can be configured by the

202

interrupt of the LPC controller. The SIRQ interrupt does not need to be cleared by software.

The access timeout interrupt is edge-triggered, so if an LPC access timeout interrupt occurs, the software

needs to write bit[17] of the interrupt clear register to clear the interrupt.

24.4. LPC Control Register

Control Register 0

Address Offset: 00-03h

Attribute: R/W

Default value: 0000FFFFh

Size: 4

Table 307. Control register 0

Bit Field

Name

Read/Write

Description

SIRQ_EN

R/W

SIRQ interrupt enable control.

R/W

LPC Memory space address translation

LPC_MEM_TRANS_EN

enable.

22:16

LPC_MEM_TRANS

R/W

The high 7-bit address (bit[31:25]) of the

LPC Memory space after address

translation.

15:0

LPC_SYNC_TIMEOUT

R/W

Threshold for LPC access timeout

(minimum value 64).

Control Register 1

Address Offset: 04-07h

Attribute: R/W

Default value: 00000000h

Size: 4

Table 308. Control register 1

Bit Field

Name

Read/Write

Description

FIRMWARE_TYPE

R/W

LPC Memory space Firmware Memory

access type configuration.

R/W

LPC interrupt enable, each bit corresponds

17:0

LPC_INT_EN

to an interrupt source. For each interrupt

source:

0: Disable interrupt.

1: Enable interrupt.

LPC Interrupt Status Register

203

Address Offset: 08-0Bh

Attribute: R/W

Default value: 00000000h

Size: 4

Table 309. LPC interrupt status register

Bit Field

Name

Read/Write

Description

17:0

LPC_INT_SRC

LPC Interrupt source indication, each bit

corresponds to an interrupt source. For each

interrupt source:

0: Disable interrupt.

1: Enable interrupt.

LPC Interrupt Clear Register

Address Offset: 0C-0Fh

Attribute: WO

Default value: 00000000h

Size: 4

Table 310. LPC interrupt clear register

Bit Field

Name

Read/Write

Description

LPC_TIMEOUT_INT_CLEAR

LPC access timeout interrupt clear (write 1

to clear). Bit 17 corresponds to LPC access

timeout interrupt. Write 1 to clear, write 0 to

be invalid.

LPC SIRQ Interrupt Polarity Register

Address Offset: 10-13h

Attribute: R/W

Default value: 0000FFFBh

Size: 4

Table 311. LPC SIRQ interrupt polarity register

204

Appendix A: Table of Pin Multiplexing

The chip pins are multiplexed as shown in the following table.

Table 312. Table of chip pin function multiplexing

Function 0 (Default)

Function 1

Function 2

Function 3

VSB_GATEn

GPIO01

CLKOUT25M

GPIO02

CLKOUTFLEX

GPIO03

PWM0

GPIO04

PWM1

GPIO05

PWM2

GPIO06

PWM3

GPIO07

I2C0_SCL

GPIO08

I2C0_SDA

GPIO09

I2C1_SCL

GPIO10

I2C1_SDA

GPIO11

SPI_CSn0

GPIO12

I2C4_SCL

SPI_CSn1

GPIO13

I2C4_SDA

SPI_CSn2

GPIO14

I2C5_SCL

SPI_CSn3

GPIO15

I2C5_SDA

SPI_SDI

GPIO16

SPI_SDO

GPIO17

SPI_SCK

GPIO18

HDA_BITCLK

GPIO19

AC97_BITCLK

HDA_SYNC

GPIO20

AC97_SYNC

HDA_RESETn

GPIO21

AC97_RSTn

HDA_SDO

GPIO22

AC97_SDO

HDA_SDI0

GPIO23

AC97_SDI

HDA_SDI1

GPIO24

HDA_SDI2

GPIO25

SATA0_LEDn

GPIO26

SATA1_LEDn

GPIO27

SATA2_LEDn

GPIO28

USB_OC_0

GPIO29

USB_OC_1

GPIO30

USB_OC_2

GPIO31

206

UART3_RXD

GPIO32

UART_DCD

I2C2_SCL

UART3_TXD

GPIO33

UART_RI

I2C2_SDA

UART2_RXD

GPIO34

UART_DSR

I2C3_SCL

UART2_TXD

GPIO35

UART_DTR

I2C3_SDA

UART1_RXD

GPIO36

UART_CTS

UART1_TXD

GPIO37

UART_RTS

UART0_RXD

GPIO38

UART_RXD

UART0_TXD

GPIO39

UART_TXD

LPC_AD0

GPIO40

LPC_AD1

GPIO41

LPC_AD2

GPIO42

LPC_AD3

GPIO43

LPC_SERIRQ

GPIO44

LPC_FRAMEn

GPIO45

SYS_CLKSEL0

GPIO46

SYS_CLKSEL1

GPIO47

SYS_CLKSEL2

GPIO48

SYS_CLKSEL3

GPIO49

SYS_CLKSEL4

GPIO50

SYS_CLKSEL5

GPIO51

SYS_CLKSEL6

GPIO52

SYS_CLKSEL7

GPIO53

SYS_PCIEBRGMODE

GPIO54

HT_8x2

GPIO55

SYS_CLKSEL8

GPIO56

Note: All signals of HDA and LPC can only be multiplexed as a whole, and each pin cannot be controlled

individually. For example, if the AC97 function is enabled, pin HDA_SDI1/2 cannot be used as other

functions.

207

Appendix B: Notes on the Use of the Software

Currently, there are five^[1] problems that need to be fixed by the software for the bridge piece.

PCI device scanning problem

The correct value of the subclass code of the PCI device header of the PCIE bridge integrated in the

bridge chip should be 0x04 (for PCI type bridge), but this bridge chip will now be 0x00 (for Host type

bridge).

Solution: When the read configuration header access is found, if the access address is bus 0 of the

device 9 to 20 and the address is 0x8, directly return 0x06040001, and not return the hardware read

value.

PCI device scanning problem

For the PCIE bridge integrated in the bridge chip, when scanning the lower bus, when scanning the non-

0 device, it should return an invalid value, but this bridge chip will return the configuration header of the

0 device, causing the 0 device to be found repeatedly.

Solution: For PCIE bridges integrated in the bridge, the lower bus only scans for device 0 and no other

device number is scanned.

PCI device scanning problem

The Memory Space Enable control bits of the PCI configuration headers of the OHCI (Function 0)

and EHCI (Function 1) controllers of the USB devices (Device 4 and Device 5) are reversed. That is, the

Memory Space Enable bit of EHCI controls the Mem space enable of OHCI, while the Memory

Space Enable bit of OHCI controls the Mem space enable of EHCI.

Solution: Fix by software.

GMAC DMA64 problem

In 64-bit DMA mode, the high 32-bit register (0x1094) of the GMAC’s transmit descriptor base address

can only be read, but not written.

Solution: Write to the high

32-bit register

(0x1094) by writing the following addresses

{0x10a8[31:8], 0x1068[7:0]}.

LPC FIXIOREG problem

The FIXCREG/FIXMREG/FIXIOREG of the LPC is used as an internal reserved register and is not used as

a BAR in the PCI configuration header, but the hardware implementation incorrectly places its address

in the location of the PCI configuration header BAR. The software should treat the BAR register location

of the LPC as an invalid BAR, but needs to enable I/O and MEM space access for the LPC.

Solution: In the PCI configuration read access function, when the device found to be read is LPC

(B0:D23:F0) and the address is equal to the address of BAR0/1/2/3/4/5 (0x10 to 0x27), return data

0 directly.

Concurrent access of DC control registers problem

The DC’s control registers do not support simultaneous write accesses by multiple processors,

regardless of whether the destination registers for these write accesses are the same. That is, only one

processor can write to the DC’s control register space at any given time.

208

Loongson 7A1000 Bridge User Manual. Loongson Technology Corporation Limited Version 2.00 - page 7