Loongson 7A1000 Bridge User Manual. Loongson Technology Corporation Limited Version 2.00

Attribute: R/W

Default value: 17161514h

Size: 32 bits

Table 101. HT message packet interrupt vector configuration register 6

Bit Field

Name

Read/Write

Description

31:0

Reserved

R/W

Reserved

Address Offset: 218-21Bh

Attribute: R/W

Default value: 1B1A1918h

Size: 32 bits

Table 102. HT message packet interrupt vector configuration register 7

Bit Field

Name

Read/Write

Description

R/W

PWM3 HT Interrupt Vector Configuration Register

31:24

pwm3_int_route

R/W

PWM2 HT Interrupt Vector Configuration Register

23:16

pwm2_int_route

15:8

pwm1_int_route

R/W

PWM1 HT Interrupt Vector Configuration Register

R/W

PWM0 HT Interrupt Vector Configuration Register

7:0

pwm0_int_route

Address Offset: 21C-21Fh

Attribute: R/W

Default value: 1E1F1D1Ch

Size: 32 bits

Table 103. HT message packet interrupt vector configuration register 8

Bit Field

Name

Read/Write

Description

R/W

Thsensor HT Interrupt Vector Configuration Register

31:24

thsens_int_route

23:16

gpu_int_route

R/W

GPU HT Interrupt Vector Configuration Register

R/W

GMEM HT Interrupt Vector Configuration Register

15:8

gmem_int_route

R/W

DC HT Interrupt Vector Configuration Register

7:0

dc_int_route

Address Offset: 220-223h

Attribute: R/W

Default value: 43424140h

Size: 32 bits

Table 104. HT message packet interrupt vector configuration register 9

Bit Field

Name

Read/Write

Description

31:24

pcie_f0_p3_int_rout

R/W

PCIE_F0 Controller 3 HT Interrupt Vector

Configuration Register

R/W

PCIE_F0 Controller 2 HT Interrupt Vector

23:16

pcie_f0_p2_int_rout

Configuration Register

R/W

PCIE_F0 Controller 1 HT Interrupt Vector

15:8

pcie_f0_p1_int_rout

Configuration Register

7:0

pcie_f0_p0_int_rout

R/W

PCIE_F0 Controller 0 HT Interrupt Vector

Configuration Register

Address Offset: 224-227h

Attribute: R/W

Default value: 47464544h

Size: 32 bits

Table 105. HT message packet interrupt vector configuration register 10

Bit Field

Name

Read/Write

Description

R/W

PCIE_H Controller 1 HT Interrupt Vector

31:24

pcie_h_p1_int_route

Configuration Register

R/W

PCIE_H Controller 0 HT Interrupt Vector

23:16

pcie_h_p0_int_route

Configuration Register

R/W

PCIE_F1 Controller 1 HT Interrupt Vector

15:8

pcie_f1_p1_int_rout

Configuration Register

R/W

PCIE_F1 Controller 0 HT Interrupt Vector

7:0

pcie_f1_p0_int_rout

Configuration Register

Address Offset: 228-22Bh

Attribute: R/W

Default value: 4B4A4948h

Size: 32 bits

Table 106. HT message packet interrupt vector configuration register 11

Bit Field

Name

Read/Write

Description

31:24

pcie_g1_p1_int_rout

R/W

PCIE_G1 Controller 1 HT Interrupt Vector

Configuration Register

R/W

PCIE_G1 Controller 0 HT Interrupt Vector

23:16

pcie_g1_p0_int_rout

Configuration Register

R/W

PCIE_G0 Controller 1 HT Interrupt Vector

15:8

pcie_g0_p1_int_rout

Configuration Register

Bit Field

Name

Read/Write

Description

7:0

pcie_g0_p0_int_rout

R/W

PCIE_G0 Controller 0 HT Interrupt Vector

Configuration Register

Address Offset: 22C-22Fh

Attribute: R/W

Default value: 4F4E4D4Ch

Size: 32 bits

Table 107. HT message packet interrupt vector configuration register 12

Bit Field

Name

Read/Write

Description

R/W

ACPI HT Interrupt Vector Configuration Register

31:24

acpi_int_route

23:16

toy2_int_route

R/W

TOY2 HT Interrupt Vector Configuration Register

R/W

TOY1 HT Interrupt Vector Configuration Register

15:8

toy1_int_route

R/W

TOY0 HT Interrupt vector configuration register

7:0

toy0_int_route

Address Offset: 230-233h

Attribute: R/W

Default value: 53525150h

Size: 32 bits

Table 108. HT message packet interrupt vector configuration register 13

Bit Field

Name

Read/Write

Description

31:24

usb1_ohci_int_route

R/W

USB1 OHCI Controller HT Interrupt Vector

Configuration Register

R/W

USB1 EHCI Controller HT Interrupt Vector

23:16

usb1_ehci_p2_int_ro

Configuration Register

ute

15:8

usb0_ohci_int_route

R/W

USB0 OHCI Controller HT Interrupt Vector

Configuration Register

R/W

USB0 EHCI Controller HT Interrupt Vector

7:0

usb0_ehci_int_route

Configuration Register

Address Offset: 234-237h

Attribute: R/W

Default value: 57565554h

Size: 32 bits

Table 109. HT message packet interrupt vector configuration register 14

Bit Field

Name

Read/Write

Description

31:24

hpet_int_route

R/W

HPET HT Interrupt Vector Configuration Register

R/W

RTC2 HT Interrupt Vector Configuration Register

23:16

rtc2_int_route

R/W

RTC1 HT Interrupt Vector Configuration Register

15:8

rtc1_int_route

7:0

rtc0_int_route

R/W

RTC0 HT Interrupt Vector Configuration Register

Address Offset: 238-23Bh

Attribute: R/W

Default value: 5B5A5958h

Size: 32 bits

Table 110. HT message packet interrupt vector configuration register 15

Bit Field

Name

Read/Write

Description

R/W

GPIO high bit (bit[56:4]) HT interrupt vector

31:24

gpio_hi_int_route

configuration register

23:16

ac97/hda_int_route

R/W

AC97/HDA Controller HT Interrupt Vector

Configuration Register

R/W

AC97 DMA1 HT Interrupt vector configuration

15:8

ac97_dma1_int_route

7:0

ac97_dma0_int_route

R/W

AC97 DMA0 HT Interrupt vector configuration

Address Offset: 23C-23Fh

Attribute: R/W

Default value: 5F5E5D5Ch

Size: 32 bits

Table 111. HT message packet interrupt vector configuration register 16

Bit Field

Name

Read/Write

Description

R/W

31:24

gpio3_int_route

GPIO3 HT Interrupt Vector Configuration Register

R/W

23:16

gpio2_int_route

GPIO2 HT Interrupt Vector Configuration Register

15:8

gpio1_int_route

R/W

GPIO1 HT Interrupt Vector Configuration Register

7:0

gpio0_int_route

R/W

GPIO0 HT Interrupt Vector Configuration Register

Interrupts routed to INTn0 are in the Service Status Register

Address Offset: 300-303h

Attribute: RO

Default value: 00000000h

Size: 32 bits

Table 112. HT message packet interrupt vector configuration register 17

Bit Field

Name

Read/Write

Description

31:0

int_isr_0

R/W

Interrupts routed to INTn0 are in the lower 32 bits of

the Service Status Register (bit`[31:0]`)

Address Offset: 304-307h

Attribute: RO

Default value: 00000000h

Size: 32 bits

Table 113. HT message packet interrupt vector configuration register 18

Bit Field

Name

Read/Write

Description

R/W

The interrupt routed to INTn0 is in the high 32 bits of

31:0

int_isr_0

the service status register (bit`[63:32]`)

Interrupts routed to INTn1 are in the service status segiste

Address Offset: 320-323h

Attribute: RO

Default value: 00000000h

Size: 32 bits

Table 114. Interrupts routed to INTn1 are in the service status segister 1

Bit Field

Name

Read/Write

Description

31:0

int_isr_1

R/W

Interrupts routed to INTn1 are in the lower 32 bits of

the service status register (bit`[31:0]`)

Address Offset: 324-327h

Attribute: RO

Default value: 00000000h

Size: 32 bits

Table 115. Interrupts routed to INTn1 are in the service status segister 2

Bit Field

Name

Read/Write

Description

31:0

int_isr_1

R/W

The interrupt routed to INTn1 is in the high 32 bits of

the service status register (bit`[63:32]`)

Interrupt request register

Address Offset: 380-383h

Attribute: RO

Default value: 00000000h

Size: 32 bits

Table 116. Interrupt request register 1

Bit Field

Name

Read/Write

Description

R/W

31:0

int_irr

Low 32 bits of the interrupt request register

(bit`[31:0]`)

Address Offset: 384-387h

Attribute: R/W

Default value: 00000000h

Size: 32 bits

Table 117. Interrupt request register 2

Bit Field

Name

Read/Write

Description

31:0

int_irr

R/W

High 32 bits of the interrupt request register

(bit`[63:32]`)

Interrupt in service status register

Address Offset: 3A0-3A3h

Attribute: RO

Default value: 00000000h

Size: 32 bits

Table 118. Interrupt in service status register 1

Bit Field

Name

Read/Write

Description

R/W

31:0

int_isr

Interrupt in the lower 32 bits of the service status

Address Offset: 3A4-3A7h

Attribute: R/W

Default value: 00000000h

Size: 32 bits

Table 119. Interrupt in service status register 2

Bit Field

Name

Read/Write

Description

31:0

int_isr

R/W

Interrupt in the high 32 bits of the service status

Interrupt level trigger polarity register

Address Offset: 3E0-3E3h

Attribute: R/W

Default value: 00000000h

Size: 32 bits

Table 120. Interrupt level trigger polarity register 1

Bit Field

Name

Read/Write

Description

R/W

31:0

int_polarity

Low 32 bits of the interrupt level trigger polarity

Address Offset: 3E4-3E7h

Attribute: R/W

Default value: 00000000h

Size: 32 bits

Table 121. Interrupt level trigger polarity register 2

Bit Field

Name

Read/Write

Description

31:0

int_polarity

R/W

High 32 bits of the interrupt level trigger polarity

5.3. Device Interrupt Types

For the bridge chip, AC97 DMA interrupts are edge triggered, gpio interrupts can be configured to be level

triggered or edge triggered as needed, and the rest of the interrupts are level triggered and active high.

For PCIE devices, one way is to use the interrupt line of the PCIE controller inside the bridge to transmit the

interrupt; the other way is to use the MSI interrupt of the PCIE device directly.

In the PCIE MSI interrupt method, when the PCIE controller inside the bridge receives an MSI interrupt, it

converts it directly into an HT interrupt message packet to send to the HT controller. Therefore, the

software needs to be careful to distinguish the MSI interrupt vector of the PCIE device from the HT interrupt

vector configured by the internal device of the bridge.

5.4. Interrupt Distribution Modes

The bridge supports dual interrupt outputs, so that different interrupt sources or multiple interrupts from

the same interrupt source can be distributed between the two interrupt outputs. The bridge chip supports

interrupt hardware load balancing, which allows interrupts to be distributed between the two outputs preset

by software in four modes.:

1. Fixed distribution mode - Distribution is done according to the routing method configured in the

interrupt routing configuration register. In this mode, the routing configuration register must be one-hot

encoded, meaning that an interrupt can only be routed to one interrupt output.

2. Rotating distribution mode - In this mode, each new interrupt generated is routed to the next valid

interrupt output according to the route vector configuration in the Route_Entry register. The route to the

next valid interrupt output is configured in the Route_Entry register.

3. Idle distribution mode - jumps to an idle interrupt output. In this mode, when each new interrupt is

generated, it first detects if there is already an unprocessed interrupt on the next interrupt output

according to the routing vector configuration in the Entry register, and if not, it is routed to that interrupt

output; if there is already an unprocessed interrupt on the next interrupt output, it continues to detect

the next processor core.

4. Busy distribution mode - the current interrupt output is busy then jumps to its left (0→1→2→3)

candidate interrupt output. When each new interrupt is generated in this mode, it first detects whether

there is already an unprocessed interrupt on the interrupt output of the last interrupt, and if not,

continues to interrupt that interrupt output, and if there is an unprocessed interrupt, it is routed to the

next interrupt output as configured in the Entry register. It should be noted that once AUTO_CTRL0/1

has been configured, it should not be modified in the middle of the run. It is recommended that the

software use fixed distribution mode.

5.5. Detailed Description of Interrupt Handling Process

In the interrupt line interrupt mode, the interrupt controller of the bridge chip receives the device interrupt

and sets the corresponding interrupt output pin low according to the interrupt routing configuration. The

processor receives the interrupt through the interrupt input pin, and the processor obtains the current

interrupt source routed to itself by reading the corresponding ISR (interrupt in service register) register

within the bridge chip interrupt controller. The interrupt processing process is:

1. The interrupt controller of the bridge receives the device interrupt; (hardware)

2. The interrupt controller of the bridge chip sets the interrupt output pin low; (hardware)

3. The processor’s interrupt controller receives the interrupt pin interrupt; (hardware)

4. The processor turns off the interrupt. (software)

5. The processor reads its own interrupt controller and learns that it is an external interrupt; (software)

6. The processor reads the interrupt controller of the bridge chip to get the interrupt vector; (software)

7. The processor writes the interrupt controller of the bridge chip to mask the corresponding interrupt

source; (software)

8. The processor opens the interrupt. (software)

9. The processor calls the interrupt service program to handle the interrupt; (software)

10. The processor writes the bridge chip’s interrupt controller to clear edge-triggered interrupts; (software)

11. The processor writes the bridge chip’s interrupt controller to turn on the corresponding interrupt source.

(Software)

12. The processor interrupt returns. (Software)

In the HT message packet interrupt method, the interrupt controller and PCIE controller of the bridge

receive the device interrupt and can send the interrupt vector directly to the HT controller of the processor,

thus avoiding the process of the processor querying the internal interrupt vector of the bridge. The interrupt

processing process is as follows.

1. The interrupt controller of the bridge receives the device interrupt; (hardware)

2. The interrupt controller of the bridge slices sends the interrupt vector to the HT controller of the

processor; (hardware)

3. The processor’s interrupt controller receives the HT interrupt; (hardware)

4. The processor turns off the interrupt. (software) 5.

5. The processor reads its own interrupt controller and learns that it is an HT interrupt; (software)

6. The processor reads its own HT controller to get the interrupt vector; (software)

7. The processor writes its own HT controller to clear the interrupt; (software)

8. The processor opens the interrupt. (software) 9.

Chapter 6. HPET Controller

The HPET controller is compatible with standard specifications. Internally, it includes a 64-bit main counter

and three 32-bit timers (comparators). Of the three timers, timer 0 supports both periodic-capable and non-

periodic interrupts, while timers 1 and 2 support only non-periodic interrupts.

6.1. Access Address

The address space size of the HPET controller is 4KB, and the starting address (internal space of the bridge

chip) is configured by the BIOS. The physical address composition of the internal registers of the HPET

controller is as follows:

Table 122. Access address

Address bits

Composition

Remarks

Reserved

[11:08]

Internal register address

[07:00]

REG

Note: The HPET controller only supports 4-byte accesses. Software that needs to use the HPET’s 64-bit

master counter as a timestamp needs to be careful to handle the data rounding introduced by reading the

high and low 32-bit values in two separate readings.

6.2. Description of Registers

Table 123. HPET register list

Description

000-007h

General Capabilities and ID Register

Reserved

008-00Fh

General Configuration Register

010-017h

018-01Fh

Reserved

General Interrupt Status Register

020-027h

Reserved

028-0EFh

0F0-0F7h

Main Counter Value Register

100-107h

Timer 0 Configuration and Capability Register

108-10Fh

Timer 0 Comparator Value Register

110-11Fh

Reserved

120-127h

Timer 1 Configuration and Capability Register

128-12Fh

Timer 1 Comparator Value Register

130-13Fh

Reserved

140-147h

Timer 2 Configuration and Capability Register

148-14Fh

Timer 2 Comparator Value Register

150-15Fh

Reserved

General Capabilities and ID Register

Address Offset: 00-07h

Attribute: RO

Default value: See description

Size:`8`

Table 124. General capabilities and id register

Bit Field

Name

Description

Read/Write

63:32

COUNTER_CLK_

Timing frequency of the master timer in fps (10^-

PERIOD

15s). Default value: 1312D00h (20ns clock period).

31:16

VENDOR_ID

Manufacturer ID. value: 0014h

Reserved

15:14

Reserved

COUNT_SIZE_C

The width of the master timer. This chip is a 64-bit

master timer. Value: 1b.

0: 32 bits

1: 64 bits

Number of timers; the value of this field indicates

12:8

NUM_TIM_CAP

the number of the last timer. This chip contains 3

timers.

This chip contains 3 timers. Value: 2h.

7:0

REV_ID

Version number; value: 02h

General Configuaration Register

Address Offset: 10-17h

Attribute: RO, R/W

Default value: 0h

Size:8

Table 125. General configuaration register

Bit Field

Name

Description

Read/Write

Reserved

63:1

Reserved

ENABLE_CNF

HPET enable control.

0: the main timer stops timing and all timers are no

longer generating interrupts.

1: the main timer counts and the timers are allowed

to generate interrupts.

General Interrupt Status Register

Address Offset: 20-27h

Attribute: RO, R/WC

Default value: 0h

Size:8

Table 126. General interrupt status register

Bit Field

Name

Description

Read/Write

63:3

Reserved

T2_INT_STS

Timer 2 interrupt status. Same function as

R/WC

T0_INT_STS.

R/WC

T1_INT_STS

Timer 1 interrupt status. Same function as

T0_INT_STS.

R/WC

T0_INT_STS

Timer 0 interrupt state.

When the timer’s interrupt trigger mode is level-

triggered, this timer defaults to 0. When the

corresponding timer interrupt occurs, then the

hardware will set it to 1. Once set, software writing 1

to this timer will clear it. Once it is set, software

writing 1 to this timer will clear this timer. Writing 0

to this timer will be meaningless. When the interrupt

triggering mode of the timer is edge triggering

mode. Software will ignore this bit. Software usually

writes 0 to this bit.

The interrupt trigger mode of each timer is determined by the Tn_TYPE_CNF bit

the respective

Configuartion and Capability register.

Main Counter Value Register

Address Offset: F0-F7h

Attribute: R/W

Default value: 0h

Size:`8`

Table 127. Main counter value register

Bit Field

Name

Description

Read/Write

63:0

Main_Counter

Master timer. Modifying the value of this register is

R/W

only allowed when the main timer stops timing.

Timer 0 Configuration and Capabilities Registe

Address Offset: 100-107h

Attribute: RO, R/W

Default value: 10h

Size:`8`

Table 128. Timer 0 configuration and capabilities registe

Bit Field

Name

Description

Read/Write

63:9

Reserved

T0_32MODE_CN

Timer 0 32-bit mode configuration. When the timer

is 64-bit, the software writes 1 to this bit to use the

timer as a 32-bit. This version of the timer does not

support 64-bit, and the bit is not writable.

Reserved

R/W

T0_VAL_SET_C

Timer 0 value setting. Only timers that can generate

periodic interrupts will use this field. By writing 1 to

this field, software can directly modify the periodic

The software can directly modify the accumulator

for the periodic period by writing 1 to this field.

Software does not need to clear 0 to this field.

T0_SIZE_CAP

Timer 0 Width indication.

0: 32-bit width

1: 64-bit width

T0_PER_INT_C

Timer 0 Periodic interrupt indication.

1: the timer is capable of generating periodic

interrupts.

0: the timer is not capable of generating periodic

interrupts.

Timer 0 cycle interrupt configuration. If the

R/W

T0_TYPE_CNF

corresponding T0_PER_INT_CAP bit is 0, then this

bit is read-only and defaults to 0. If the

corresponding T0_PER_INT_CAP bit is 1, then this

bit is readable and writable. It is used to enable the

corresponding timer to generate periodic interrupts.

1: Enable the timer to generate periodic interrupts

0: Enable the timer to generate non-periodic

interrupts

T0_INT_ENB_C

Enable Timer 0 to generate interrupts

R/W

T0_INT_TYPE_

Timer 0 interrupt type configuration.

CNF

0: The interrupt triggering mode of the timer is edge

triggered; this means that the corresponding timer

will generate an edge triggered interrupt. If another

interrupt is generated, then another edge will be

generated. 1: The interrupt trigger mode of the timer

is level triggered; this means that the corresponding

timer will generate a level triggered interrupt. This

interrupt will remain active until it is cleared by

software (General Interrupt Status Register).

100

Bit Field

Name

Description

Read/Write

Reserved

Timer 0 Comparator Value Register

Address Offset: 108-10Fh

Attribute: R/W

Default value: FFFFFFFFh

Size:`8`

Table 129. Timer 0 comparator value register

Bit Field

Name

Description

Read/Write

Reserved

63:32

Reserved

31:0

T0_Com_VAL

The value of the timer 0 comparator. When the

R/W

corresponding timer is configured in non-periodic

mode. the value of this register will be compared

with the value of the main timer register. If the value

of the main timer is equal to the value of the

comparator, a timing interrupt is generated (if; the

corresponding interrupt enable is on). The

comparator value will not change due to the

interrupt generation If the corresponding timer is

configured in periodic mode. interrupt is generated

when the value of the comparator in the value field

of the main timer is equal (if; the corresponding

interrupt enable is turned on). If an interrupt is

generated, then the comparator value is

accumulated from the last software write to the

comparator. For example, when the comparator

value is written to 0x0123h then an interrupt is

generated when the value of the main timer is

0x123h; the comparator value is modified by

hardware to 0x246h. When the value of the main

timer reaches 0x246h, another interrupt is

generated; the comparator value is modified by

hardware to 0x369h. Whenever an interrupt is

generated, the comparator value will be

accumulated; until the comparator value reaches the

maximum (0xffffffff), then the accumulator

value will continue to accumulate. For example,

when the comparator value is FFFF0000h, and the

last time the comparator was written by software,

the value is 20000. When the interrupt occurs, the

comparator value becomes 00010000h.

Timer 1 Configuration and Capabilities Registe

Address Offset: 120-127h

Attribute: RO, R/W

101

Chapter 7. HT Controller

The bridge HT interface supports a maximum bi-directional 16-bit data width and an operating frequency of

2.0 GHz. After the connection is established by automatic system initialization, the user can change the

width and operating frequency and re-initialize by modifying the corresponding configuration registers in

the protocol.

The main features of the bridge HT interface are as follows:

• Support HT1.0/3.0 protocol

• Support 200/400/800/1600/2000 MHz operating frequency

• Support 8/16 bit width

• Support dual processors with bridge chip direct connection (each link can only work in 8-bit mode)

7.1. HT User Guide

7.1.1. HT Working Mode

When chip pin HT_8x2 is configured to 0, the bridge operates in single mode, where only one processor is

directly connected to the bridge via the HT bus, and only one HT controller (HT lo) is operating inside the

bridge, while the other HT controller (HT hi) is not available.

The HT link can operate in either 8-bit or 16-bit mode, and the software can configure the data width used

(the maximum available width also depends on the PCB hardware connection), when the data link is

controlled by controller lo. The data link is controlled by the controller lo.

When the chip pin HT_8x2 is configured to 1, the bridge operates in dual mode, where two processors can

be connected directly to the bridge via the HT bus, and the two HT controllers inside the bridge are

operating simultaneously, controlling the low 8 bits and high 8 bits of the data link respectively. Software

can control both HT controllers via the HT bus of both processors. When operating in dual mode, the

software needs to configure the HT DMA routing configuration (see section 4.1 HT Clock Enable and DMA

Routing Configuration) to send DMA accesses to the corresponding HT controller.

7.1.2. HT Address Space

The address space for processor accesses is described in Section 3.

The HT module has several internal address windows for configuring CPU accesses and DMA accesses.

For CPU accesses, the bridge chip acts as the accessee and the corresponding configuration window is

called the receive window; for DMA accesses, the bridge chip acts as the access initiator and the

corresponding window is called the send window.

The receive window consists of two types: the P2P access window and the normal access window.

Accesses that fall within the P2P access window are forwarded directly back to the HT bus as P2P

commands and are not sent to the internal devices of the bridge chip; accesses that fall within the normal

access window are sent to the internal devices of the bridge chip as accesses to the internal devices of the

bridge chip. The P2P access window has a higher priority than the normal access window. Accesses that

do not hit in either of the two types of receive windows are forwarded directly back to the HT bus as P2P

commands.

DMA accesses are sent out through the HT’s non-Post channel by default, and the Post send window is set

internally in the bridge to send DMA accesses out through the HT’s Post channel. That is, DMA accesses

that hit in the Post send window are sent to the HT bus via the HT’s Post channel, and DMA accesses that

do not hit in the Post send window are sent to the HT bus via the HT’s non-Post channel. In general, the

Post send window should not be enabled and all DMA accesses should be sent out through the HT’s non-

Post channel.

103

7.2. HT Configuration Register

HT Configuration Register

Table 130. HT configuration register

Address

Abbreviations

Description

Default value

Read/Write

Offset

Vendor ID

00h-01h

VID

0014h

02h-03h

DID

Device ID

7A00h

PCI Command

R/W, RO

04h-05h

PCICMD

0000h

PCI Status

06h-07h

PCISTS

0010h

08h

RID

Revision ID

00h

Programming Interface

09h

00h

Sub Class Code

0Ah

SCC

00h

0Bh

BCC

Base Class Code

06h

Cache Line Size

0Ch

CLS

00h

Header Type

0Eh

HEADTYP

80h

2Ch-2Dh

SVID

Subsystem Vendor ID

0014h

Subsystem Identification

2Eh-2Fh

SID

7A00h

Capabilities Pointer

34h

CAPP

40h

3Ch

INT_LN

Interrupt Line

00h

R/W

Interrupt Pin

3Dh

INT_PN

00h

Bridge Control Register

R/W

3Eh-3Fh

BCTRL

0000h

42h-43h

DIDCMD

Device ID Command Register

0000h

R/W, RO

Link Status and Control

R/W

44h-45h

LKSC0

0020h

46h-47h

LKWDSC0

Link Width Status and

0000h

R/W

Control Register 0

HT Revision ID

4Ch

HTRID

60h

Link Frequency Status and

R/W, RO

4Dh-4Fh

LKFREQSC0

000000h

Control Register 0

Receive Window 0

R/W

140h-147h

RXWIN0

0000F00080000000h

Receive Window 1

R/W

148h-14Fh

RXWIN1

FDFCFFFF80000000h

150h-157h

RXWIN2

Receive Window 2

0000000000000000h

R/W

Receive Window 3

R/W

158h-15Fh

RXWIN3

0000000000000000h

Receive Window 4

R/W

160h-167h

RXWIN4

0000000000000000h

170h-177h

TXPOSTWIN0

Transmit Post Window 0

0000000000000000h

R/W,RO

178h-17Fh

TXPOSTWIN1

Transmit Post Window 1

0000000000000000h

R/W,RO

Receive P2P Window 0

R/W,RO

1B0h-1B7h

RXP2PWIN0

0000000000000000h

104

Address

Abbreviations

Description

Default value

Read/Write

Offset

Receive P2P Window 1

R/W,RO

1B8h-1BFh

RXP2PWIN1

0000000000000000h

1F4h-1F7h

HTPLLCTRL

HT Pll Control Register

00000000h

R/W,RO

Note: Address spaces not listed in the table indicate reservations.

BCTRL-HT bridge control register

Address Offset: 3E-3Fh

Attribute: R/W, RO

Default value: 0000h

Size: 16 bits

Table 131. BCTRL-HT bridge control register

Bit Field

Name

Read/Write

Description

Reserved

15:7

Reserved

R/W

This bit controls the HT reset.

HT Reset

0: unreset.

1: Reset.

5:0

Reserved

DIDCMD - device ID command register

Address Offset: 42-43h

Attribute: R/W, RO

Default value: 0000h

Size: 16 bits

Table 132. DIDCMD-device ID command register

Bit Field

Name

Read/Write

Description

15:13

Command Format

Reserved

12:10

Reserved

R/W

Provided to the software for recording the current

9:5

Unit Count

number of units

4:0

Unit ID

R/W

Record the number of IDs used

LKSC0-Link status control register 0

Address Offset: 44-45h

Attribute: R/W, RO

105

Default value: 2000h

Size: 16 bits

Table 133. LKSC0-Link status control register 0

Bit Field

Name

Read/Write

Description

Reserved

15:14

Reserved

LDTSTOP# Tristate

R/W

Whether to turn off the HT PHY when the HT bus

enters the HT Disconnect state.

Enable

0: Not to turn off;

1: To turn off.

Reserved

12:10

Reserved

R/W

CRC error occurs in high 8 bits

CRC Error (hi)

CRC Error (lo)

R/W

CRC error occurs on low 8 bits

Trans off

R/W

HT PHY off control. When in 16-bit bus operation,

1: Turn off the high/low 8-bit HT PHY;

0: Enable the low 8-bit HT PHY, the high 8-bit HT

PHY is controlled by bit 0

End of Chain

HT Bus End

HT bus initialization complete

Init Complete

Connection failure indication

Link Fail

3:2

Reserved

R/W

CRC Flood Enable

Whether to flood the HT bus in case of CRC error

Trans off (hi)

R/W

When running an 8-bit protocol using a 16-bit HT

bus, the high 8-bit PHY is off control.

0: Enables the high 8-bit HT PHY.

1: Disables high 8-bit HT PHY.

LKWDSC0-Link data width status and control register

Address Offset: 46-47h

Attribute: R/W, RO

Default value: 0011h or 0000h

Table 134. LKWDSC0-Link data width status and control register

Bit Field

Name

Read/Write

Description

Reserved

106

Bit Field

Name

Read/Write

Description

14:12

Link TX Width

R/W

Link Sender Width. The value after a cold reset is the

maximum width of the current connection, and the

value written to this register will take effect after the

next hot reset or HT Disconnect.

000b: 8 bits.

001b: 16 bits.

Reserved

R/W

Link Sender Width. The value after a cold reset is the

10:8

Link RX Width

maximum width of the current connection, and the

value written to this register will take effect after the

next hot reset or HT Disconnect.

000b: 8 bits.

001b: 16 bits.

TX DW FC

The transmitter supports double-word flow control.

0: not supported.

1: Supported.

Maximum width of the link transmitter.

6:4

Link TX Max Width

000b: 8 bits.

001b: 16 bits.

RX DW FC

The receiver side supports double-word flow control.

0: Not supported.

1: Supported.

2:0

Link RX Max Width

Maximum width at the receiver end of the link.

000b: 8 bits.

001b: 16 bits.

Note: When HT_8x2 is 0, the default value is 0011h;

when HT_8x2 is 1, the default value is 0000h.

LKFREQCFG0-Link frequency configuration register

Address Offset: 4C-4Dh

Attribute: R/W, RO

Default value: 0060h

Size: 32 bits

107

Table 135. LKFREQCFG0-Link frequency configuration register 1

Bit Field

Name

Read/Write

Description

15:14

Reserved

HT bus packet overflow

Overflow Error

Protocol error, referring to an unrecognized

Protocol Error

command received on the HT bus

11:8

Link Frequency

R/W

HT Bus Operating Frequency Configuration, the

configuration value corresponds to the bit of Link

Control

Frequency Capability. For example, setting this

configured to 600 MHz (the frequency represented

by bit 4 of Link Frequency Capability). The value

written to this register must be the value available

as indicated by the Link Frequency Capability

to this register will take effect after the next thermal

reset or HT Disconnect (when using the software

configuration

PLL (0x1F4), this bit has no meaning)

Revision ID

Address Offset: 4E-4Fh

Attribute: RO

Default value: 0000h

Table 136. LKFREQCFG0-Link frequency configuration register 2

Bit Field

Name

Read/Write

Description

15:0

Link Frequency

The supported HT bus frequency, which produces a

different value depending on the external PLL

Capability

setting (when using the software configuration PLL

(0x1F4) is used, this bit is meaningless). Each bit

represents an HT bus frequency, and when the bit is

1 it indicates that the frequency is supported; when

the bit is 0 it indicates that the frequency is not

supported. The frequencies represented by each bit

are as follows:

bit0:200MHz bit1:300MHz bit2:400MHz

bit3:500MHz bit4:600MHz bit5:800MHz bit6:1.0GHz

bit7:1.2GHz bit8:1.4GHz bit9:1.6GHz bit10:1.8GHz

bit11:2.0GHz bit12:2.2GHz bit13:2.4GHz

bit14:2.6GHz bit15:3.2GHz

RXWIN - receive address window

Receive address window hits are sent to the internal devices of the bridge chip only when the access is hit.

The receive address window includes the following fields:

Table 137. RXWIN-receive address window

Bit Field

Name

Read/Write

Description

R/W

Window Base Address

64:48

WIN_BASE

108

Bit Field

Name

Read/Write

Description

47:32

WIN_MASK

R/W

Window Mask

R/W

Window Enable

WIN_EN

R/W

Window address conversion enable

WIN_TRANS_EN

29:0

WIN_TRANS

R/W

Window converted address high bit of address

bit`[53:24]` When the window is enabled, the

address window hit condition is: ( ADDR &

WIN_MASK ) == ( WIN_BASE & WIN_MASK ). If

address translation is enabled, the output address

is: (ADDR & ~WIN_MASK)

RXWIN0-Receive window register 0

Address Offset: 140-147h

Attribute: R/W

Default value: 0000F00080000000h

Size:`64` bit

Table 138. RXWIN0-Receive window register 0

Bit Field

Name

Read/Write

Description

R/W

64:48

RXWIN0_BASE

Receive Window 0 Base Address

R/W

47:32

RXWIN0_MASK

Receive Window 0 Mask

RXWIN0_EN

R/W

Receive Window 0 Enable

RXWIN0_TRANS_EN

R/W

Receive Window 0 Address Conversion Enable

29:0

RXWIN0_TRANS

R/W

Receive Window 0 Converted high address,

bit[53:24] of address

RXWIN1-Receive window register 1

Address Offset: 148-14Fh

Attribute: R/W

Default value: FDFCFFFF80000000h

Size: 64 bit

Table 139. RXWIN1-Receive window register 1

Bit Field

Name

Read/Write

Description

64:48

RXWIN1_BASE

R/W

Receive Window 1 Base Address

R/W

47:32

RXWIN1_MASK

Receive Window 1 Mask

R/W

RXWIN1_EN

Receive Window 1 Enable

R/W

RXWIN1_TRANS_EN

Receive Window 1 Address Conversion Enable

109

Bit Field

Name

Read/Write

Description

29:0

RXWIN1_TRANS

R/W

Receive Window 1 Converted high address,

bit`[53:24]` of the address

RXWIN2-Receive window register 2

Address Offset: 150-147h |Attribute: R/W Default value: 0000000000000000h |Size: 64 bit

Table 140. RXWIN2-Receive window register 2

Bit Field

Name

Read/Write

Description

64:48

RXWIN2_BASE

R/W

Receive Window 2 Base Address

47:32

RXWIN2_MASK

R/W

Receive Window 2 Mask

R/W

RXWIN2_EN

Receive Window 2 Enable

R/W

RXWIN2_TRANS_EN

Receive Window 2 Address Conversion Enable

R/W

29:0

RXWIN2_TRANS

Receive Window 2 Converted High Address,

bit`[53:24]` of the address

RXWIN3-Receive window register 3

Address Offset: 158-14Fh

Attribute: R/W

Default value: 0000000000000000h

Size: 64 bit

Table 141. RXWIN3-Receive window register 3

Bit Field

Name

Read/Writ

Description

64:48

RXWIN3_BASE

R/W

Receive Window 3 Base Address

47:32

RXWIN3_MASK

R/W

Receive Window 3 Mask

R/W

RXWIN3_EN

Receive Window 3 Enable

R/W

RXWIN3_TRANS_EN

Receive Window 3 Address Conversion Enable

R/W

29:0

RXWIN3_TRANS

Receive Window 3 Converted High Address,

bit`[53:24]` of the address

RXWIN4-Receive window register 4

Address Offset: 160-147h

Attribute: R/W

Default value: 0000000000000000h

Size: 64 bit

Table 142. RXWIN4-Receive window register 4

110

Bit Field

Name

Read/Wri

Description

64:48

RXWIN4_BASE

R/W

Receive Window 4 Base Address

47:32

RXWIN4_MASK

R/W

Receive Window 4 Mask

RXWIN4_EN

R/W

Receive Window 4 Enable

RXWIN4_TRANS_EN

R/W

Receive Window 4 Address Conversion

Enable

29:0

RXWIN4_TRANS

R/W

Receive Window 4 Converted High

Address, bit`[53:24]` of the address

TXPOSTWIN - quick send window

Visits hit by the Quick Send window give a direct response, thus speeding up the request for the request

initiator. The Quick Send window includes the following fields:

Table 143. TXPOSTWIN - quick send window

Bit Field

Name

Read/Wri

Description

Window Base Address

64:48

WIN_BASE

R/W

Window Mask

47:32

WIN_MASK

R/W

WIN_EN

R/W

Window Enable

Reserved

30:0

Reserved

When the window is enabled, the address window hit condition is: ( ADDR & WIN_MASK ) == ( WIN_BASE &

WIN_MASK ). Note: ADDR here refers to the high 16 bits of the address (bit`[39:24], the address sent

the

bus

only

40 bits).

For

example,

`1111111100000000b

,1100000000000000b are all legal configurations, while The number of zeros in MASK indicates the size

of the address window.

TXPOSTWIN0-Quick send window register 0

Address Offset: 170-177h

Attribute: R/W,RO

Default value: 0000000000000000h

Size:`64` bit

Table 144. TXPOSTWIN0-Quick send window register 0

Bit Field

Name

Read/Wri

Description

64:48

TXPOSTWIN0_BASE

R/W

Quick Send Window 0 Base Address

47:32

TXPOSTWIN0_MASK

R/W

Fast Send Window 0 Mask

TXPOSTWIN0_EN

R/W

Fast Send Window 0 Enable

30:0

Reserved

TXPOSTWIN1 - Quick send window register 1

111

Address Offset: 178-17Fh

Attribute: R/W,RO

Default value: 000000000000000h

Size: 64 bit

Table 145. TXPOSTWIN1-Quick send window register 1

Bit Field

Name

Read/Wri

Description

64:48

TXPOSTWIN1_BASE

R/W

Quick Send Window 1 Base Address

47:32

TXPOSTWIN1_MASK

R/W

Fast Send Window 1 Mask

TXPOSTWIN1_EN

R/W

Fast Send Window 1 Enable

Reserved

30:0

Reserved

RXP2PWIN-P2P receive window

Accesses hit by the P2P receive window are sent directly back to the HT bus as P2P commands. the P2P

receive window has a higher priority than the normal receive window. the P2P receive window includes the

following fields.

Table 146. RXP2PWIN-P2P receive window

Bit Field

Name

Read/Wri

Description

Window Base Address

64:48

WIN_BASE

R/W

Window Mask

47:32

WIN_MASK

R/W

WIN_EN

R/W

Window Enable

30:0

Reserved

When the window is enabled, the address window hit condition is: ( ADDR & WIN_MASK ) == ( WIN_BASE &

WIN_MASK ). Note: ADDR here refers to the high 16 bits of the address (bit[39:24], the address sent to the

HT bus is only 40 bits).

For

example,

1111111100000000b,1100000000000000b are legal configurations, while

1011111100000000b,11010000000000b are not. The number of zeros in MASK indicates the size of the

address window.

RXP2PWIN0-P2P receive window 0

Address Offset: 180-187h

Attribute: R/W,RO

Default value: 00000`00000000000h

Size: 64 bit

Table 147. RXP2PWIN0-P2P receive window 0

112

Bit Field

Name

Read/Wri

Description

64:48

RXP2PWIN0_BASE

R/W

P2P Receive Window 0 Base Address

47:32

RXP2PWIN0_MASK

R/W

P2P receive window 0 mask

RXP2PWIN0_EN

R/W

P2P receive window 0 enable

30:0

Reserved

RXP2PWIN0-P2P receive window 1

Address Offset: 188-18Fh

Attribute: R/W,RO

Default value: 000000000000000h

Size: 64 bit

Table 148. RXP2PWIN1-P2P receive window 1

Bit Field

Name

Read/Wri

Description

64:48

RXP2PWIN1_BASE

R/W

P2P Receive Window 1 Base Address

47:32

RXP2PWIN1_MASK

R/W

P2P receive window 1 mask

RXP2PWIN1_EN

R/W

P2P receive window 1 enable

Reserved

30:0

Reserved

Htpllctrl-ht pll control register

This register is used to enable the software configuration of the HT’s PLL, which is used to modify the

frequency of the HT PHY and controller.

Address Offset: 1F4-1F7h

Attribute: R/W,RO

Default value: 00000000h

Size: 32 bits

Table 149. Htpllctrl-ht pll control register

Bit Field

Name

Read/Wri

Description

31:26

Reserved

R/W

Reserved

PHY low output crossover

25:22

pll_div_phy_lo

R/W

PHY high output crossover

21:18

pll_div_phy_hi

R/W

17:16

pll_div_refc

R/W

HT PLL input frequency division

HT PLL Multiplier

15:9

pll_loopc

R/W

113

Chapter 8. MISC Low-speed Devices

MISC low speed devices include: UART, I2C, PWM, ACPI, RTC, and GPIO. these devices run at a fixed

frequency of 50MHz.

8.1. MISC Low-speed Devices Configuration Register

The address space size of the MISC low-speed device block is 512KB, and the starting address (internal

space of the bridge chip) is configured by the BIOS.

8.2. Internal Device Address Routing

Multiple devices within the MISC low-speed device block are distinguished by the bits [18:16] of the

address bits, and different devices support only specific types of access. The device routing and supported

access types are shown in the following table.

Table 150. MISC Low-speed device address routing and access types

bit[18:16]

Device

UART

I2C

PWM

ACPI/RTC

GPIO

Read/Write

For UART, I2C, PWM, and ACPI/RTC, they require further routing due to the inclusion of multiple controllers.

The internal routing of these device blocks is shown in the fllow table The number of routing address bits

required varies from one device block to another.

Table 151. MISC Low-speed device address routing

UART(bit[9

UART0

UART1

UART2

UART3

:8])

I2C(bit[10

I2C0

I2C1

I2C2

I2C3

I2C4

I2C5

:8])

PWM(bit[9:

PWM0

PWM1

PWM2

PWM3

8])

ACPI/RTC(b

ACPI

RTC

it[8])

These low-speed devices are described separately in subsequent sections.

115

Chapter 9. UART Controller

The integrated UART controller of the bridge chip complies with the RS232 standard and the controller is

designed to be compatible with the 16550A. The internal clock frequency of the UART controller is 50 MHz

and the maximum baud rate supported by the UART bus is 460800.

The bridge chip integrates four UART controllers, which are arranged in the UART module. In addition,

UART1, UART2 and UART3 can only work in two-wire UART mode, and UART0 can work in full-function

UART mode or two-wire UART mode. In addition, UART can be multiplexed as GPIO function and some

UART pins can be multiplexed as I2C function. The pin multiplexing configuration registers related to UART

are described in Section 4.4.

Table 152. UART function reuse

UART_TXD/RXD

UART_RTS/CTS

UART_DTR/DSR

UART_RI/DCD

UART0

UART1

UART2

UART3

9.1. Access Address

The access base address of the UART controller is the base address of the MISC low-speed device block

plus offset 0x0. Note: The UART module supports byte access only.

The 4 UART controllers are distinguished by bit [9:8], and the internal physical address division of the

UART module is shown in the following table.

Table 153. Module physical address composition

Address bit

Composition

Remarks

[15:10]

Reserved

[09:08]

UART number

0x0 - 0x3 for each UART

controller

[07:00]

REG

internal register address

9.2. Description of Registers

Data register (DAT)

Offset: 0x00

Reset value: 0x00

Table 154. UART function reuse

Bit Field

Name

Length

Read/Write

Tx FIFO

Description

7:0

Interrupt enable register (IER)

Offset: 0x01

Reset value: 0x00

116

Table 155. Interrupt enable register (IER)

Bit Field

Name

Length

Read/Write

Description

7:4

Reserved

R/W

Reserved

R/W

Modem Status Interrupt Enable

IME

0: off

1: On

ILE

R/W

Receiver line status interrupt enable

0: off

1: Open

ITxE

R/W

Transmission save register is air break enable

0: off

1: open

R/W

Receive valid data interrupt enable

IRxE

0: off

1: Open

Interrupt identification register (IIR)

Offset: 0x02

Reset value: 0xc1

Table 156. Interrupt identification register (IIR)

Bit Field

Name

Length

Read/Write

Description

7:4

Reserved

Interrupt source indication bits, see the following

3:1

table for details

INTp

Interrupt bits

Interrupt control menu

Table 157. Interrupt control menu

Bit 3

Bit 2

Bit 1

Priority

Interrupt Type

Interrupt Source

Interrupt Reset

Control

Receive line status

parity, overflow or

Read LSR

1st

frame errors.

2nd

Valid data received

or interrupt interrupt

The number of

characters in the

FIFO is lower than

the value of the

trigger

117

Bit 3

Bit 2

Bit 1

Priority

Interrupt Type

Interrupt Source

Interrupt Reset

Control

Receive timeout

The number of

Read the receive

2nd

characters in the

FIFO

FIFO reaches the

level of a trigger

3rd

Transmission save

There is at least one

Write data to THR or

character in the

multi-IIR

FIFO, but no

operation, including

read and write

operations, within 4

characters

Modem Status

Transfer save

Read MSR

4th

FIFO control register (FCR)

Offset: 0x02

Reset value: 0xc0

Table 158. FIFO control register (FCR)

Bit Field

Name

Length

Read/Write

Description

7:6

Receive trigger value for interrupt request from FIFO

00b: 1 byte

01b: 4 bytes

10b: 8 bytes

11b: 14 bytes

5:3

Reserved

Clears the contents of the transmit FIFO and resets

Txset

its logic

Clears the contents of the receive FIFO and resets

Rxset

its logic

Reserved

Line control register (LCR)

Offset: 0x03

Reset value: 0x03

Table 159. Line control register (LCR)

118

Loongson 7A1000 Bridge User Manual. Loongson Technology Corporation Limited Version 2.00 - page 4