Loongson 3A3000/3B3000 processor user manual. Part ii GS464E processor core V1.2

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7.32 Config4 Register (CP0 Register 16, Select 4)

The Config4 register is used to provide some configuration information for the processor and to control the

page size of the FTLB.

Figure 7-34 illustrates the Config4 register format. Table 7-36 describes the Config4 register fields.

Figure 7-34 Config4 register format

MMU

VTLBSizeExt

KScrExist

FTLBPageSize

FTLBWays

FTLBSets

ExtDef

Table 7-36 Config4 register field description

Domain

positi

Functiona

Read

Reset

name

/wri

value

descripti

A value of 1 indicates the existence of the Config5 register.

0 x1

IE ¹

30.. 29

A value of 0 indicates that the TLBINV and TLBINVF directives are not implemented

0 x0

and the EntryHi domain is not implemented. EHINV

A value of 0 indicates that the EntryHi field width is still 8 bits wide. ASID

0 x0

The value is 0, which is splice with the Mmusize-1 field of Config1 register to form a 10-

VTLB -

bit value:

27.. 24

0 x0

SizeExt

Config4. VTLBSizeExt | | Config1. MMUSize - 1;

3..05..0 The value after splicing is 63, indicating that

VTLB is 64 items.

A value of 0b11111100 indicates that registers KScratch1~6 (CP0 Register 31, Selct 2~7)

KScrExist

23.. 16

0 XFC

can be in

Kernel mind for software access.

MMU -

The value is 3 and is used to interpret the Config4 register format. Where Config4[3:0] is FTLBSets, Config4[7:4]

15.. 14

0 x3

ExtDef

FTLBWays, Config4[10:8] is FTLBPageSize, Config4[27:24] is VTLBSizeExt.

Read only is always 0.

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The IE field value is set to 0 to maintain compatibility with the MIPS specification. In fact, the GS464E

processor core implements the TLBINVF instruction (config4.ie =3), which invalidated the entire TLB table entry

by the hardware when executing a TLBINVF instruction. In addition, the TLBINV instruction is also implemented

in the GS464E processor core, but its execution effect is different from the MIPS specification definition and is

equivalent to the TLBINVF instruction.

The GS464E processor core also implements the entryhi. EHINV field: When the entryhi. EHINV position is

1, TLBWI will disable the entry. When the TLBR instruction is executed, the value of the invalid VPN2 bit for

the TLB table entry read is updated to the entryhi.ehinv bit.

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Domain

posit

Functional

Read

Reset

name

ion

descriptio

/writ

value

Represents the page size used by FTLB. The page sizes and encoding values supported

by FTLB in GS464E are as follows: page size encoding values

4 kb1

16 kb2

64 kb3

256 kb4

FTLB -

12.. 8

1 mb5

R/W

0 x1

PageSize

4 mb6

16 mb7

64 mb8

256 mb9

1 gb10

If the value the software writes to the field is not included in the table above,

the value of the field remains the same. The software must clear FTLB

before modifying the domain, otherwise the processor's behavior is

uncertain.

FTLB -

7.. 4

A value of 6 indicates that FTLB contains 8 channels

0 x6

Ways

FTLB -

3.. 0

A value of 7 means that FTLB contains 128 items in each path.

0 x7

Sets.

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7.33 Config5 Register (CP0 Register 16, Select 5)

The Config5 register is used to provide some configuration information for the processor.

Figure 7-35 illustrates the Config5 register format. Table 7-37 Table 7-32 Config register field description

Describes each field of THE Config5 register.

Figure 7-35 Config5 register format

NFExists

Table 7-37 Config5 register field description

Domain

positi

Functiona

Read

Reset

name

/wri

value

descripti

Read only is always 0.

Since the Segmentation Control pattern is not implemented, the field is meaningless.

0 x0

Since the Segmentation Control pattern is not implemented, the field is meaningless.

0 x0

Since the Segmentation Control pattern is not implemented, the field is meaningless.

0 x0

Because the MIPS Vector Module (SIMD Module) is not implemented, this field is

0 x0

meaningless.

26.. 1

Read only is always 0.

NFExists

The value is 1.

0 x1

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7.34 GSConfig Register (CP0 Register 16, Select 6)

The GSConfig register is used to dynamically configure the microstructure-related functions of the processor

core portion. The e software can turn on or off the corresponding functions according to the specific characteristics

of the program to achieve the best performance.

Figure 7-36 illustrates the format of the GSConfig register; Table 7-38 describes the fields of the GSConfig

Figure 7-36 GSConfig register format

KPos

Table 7-38 Description of GSConfig register fields

Domain

positi

Functiona

Read

Reset

name

/wri

value

descripti

EJTAG instruction and data breakpoint response mechanism control.

0: Any condition that satisfies an instruction breakpoint and a data breakpoint triggers an

exception.

1: EJTAG instruction breakpoint and data breakpoint exceptions Automatically ignore

the condition that the instruction breakpoint and data breakpoint were met the first time

BpPass

R/W

0 x0

when the exception handler returns for re-execution.

When the location of 0, the processor will be treated in accordance with the requirements

for MIPS EJTAG specification instruction breakpoints and data breakpoints, which

means the EJTAG exception handler must change in processing instruction breakpoint or

data breakpoints judgement conditions, in order to ensure the current trigger breakpoints

exception instruction DERET again after return will not trigger the exception again into

dead circulation, and to ensure that the program can new judgment conditions in time to

stop, make an exception

The handler has time to set the breakpoint condition correctly before the observed

program executes to the observed breakpoint again.

Read only is always 0.

KPos

29.. 24

Indicates which bit K is located in the page table entry (PTE).

R/W

0 x3d

The TLB page table kernel performs protection enabled bits.

0: Turn off the function. The K bits of the EntryLo0 and EntryLo1 registers will disable

R/W

0 x0

writing and force them to be 0;

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1: Enable this function. The K bits of the EntryLo0 and EntryLo1 registers work fine.

When set to 1, the processor will only operate the VTLB in the double TLB, which is

VTLB -

equivalent to the traditional single CAM-type TLB of MIPS, so as to ensure that the

R/W

0 x1

Only

original operating system kernel and other underlying software running on GS464 can

still run on GS464E without modifying the MMU part. If you want an MMU with a

double TLB, set the position to 0.

The software should clear the TLB before modifying the bit state, otherwise the processor

behavior will be unknowable.

21.. 18

Read only is always 0.

When set to 1, the Cache consistency component in the chip will initiate the SC/SCD

SCRand

R/W

0 x1

instruction in the processor core

The return delay of a Cache access request is increased by 64 to 128 random clock cycles.

Turn off the function when set to 0.

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Domain

positio

Functional

Read

Reset

name

descriptio

/writ

value

When is 1, the LL/LLD instruction will initiate a Cache access request that must be

returned in an Exclusive state

LLExc

R/W

0 x1

Cache block;

At 0, the LL/LLD instruction initiates a Cache access request that allows the Shared Cache

to be returned

Block.

0: Use VCache;

Dis -

1: Disable VCache.

R/W

0 x0

VCache

In moving from using VCache to disabling VCache, the software needs to ensure that

nothing is valid in VCache

The content.

VCLRU

Configure the VCache replacement algorithm. 1: LRU replacement algorithm; 0: Pseudo-

R/W

0 x1

random replacement algorithm.

DCLRU

Configure the DCache replacement algorithm. 1: LRU replacement algorithm; 0: Pseudo-

R/W

0 x1

random replacement algorithm.

12.. 10

Read only is always 0.

Reserved

The bit must be written to 1 after it is reset and no longer changed to 0.

R/W1

0 x0

Processor Store operation auto write merge function enable bit. 1: Open; 0: Off.

STFill

Before the software can modify this state, it needs to use the SYNC instruction to ensure

R/W

0 x1

that there are no pending accesses in the processor.

When set to 1, the clock interrupt recorded by caus.ti may come from an external timer

belonging to the processor core; When set to 0, the clock interrupt recorded by caus.ti

Ext -

does not come from an external timer belonging to the processor core. It should be

R/W

0 x0

Timer

pointed out that the increase frequency of external timer is not affected by processor core

frequency conversion.

Allows software to set the ExtTimer and InnerTimer bits of the GSConfig register to 1

simultaneously, but requires soft

This is handled correctly and is generally not recommended.

When set to 1, clock interrupts recorded by caus.ti can come from inside the processor

core with Count/Compare

The register realizes the timer;

When set to 0, the clock interrupt recorded by caus.ti does not come from the timer

Inner -

R/W

0 x1

implemented in the Count/Compare register inside the processor core.

Timer

It should be noted that the timer implemented with the Count/Compare register increases

in frequency proportionally with the processor core frequency.

Allows software to set the ExtTimer and InnerTimer bits of the GSConfig register to 1

simultaneously, but requires soft

This is handled correctly and is generally not recommended.

5.. 4

Read only is always 0.

When set to 1, the processor does not automatically prefetch the store operation in the

data access operation; When set to

0, the processor will also perform hardware

automatic prefetching of store operation, and the performance of Store prefetching can

Dis -

be further configured through GSConfig, as described in the next item. NormSTPref

R/W

0 x0

STPref

This domain is only meaningful when GSConfig=1, and modifying it when GSConfig=0

does not cause a performance change. DPrefDPref

Before the software can modify this state, it needs to use the SYNC instruction to ensure

that there are no pending accesses in the processor

Operation.

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Domain

posit

Functional

Read

Reset

name

ion

descriptio

/writ

value

When set to 1, when the processor performs hardware automatic prefetching of the store

operation, the flow control algorithm adopted is the same as the LOAD operation; Set to

0, the processor to store operation hardware automatic prefetching, in addition to adopt

with the load operation flow control mechanism, store over a period of time will be at the

Norm

same time monitoring operation automatically write merger success turns a Cache block

R/W

0 x0

(collecting) the number of times, if success number exceeds a certain threshold, the

STPref

automatic prefetching to suspend hardware store operation.

This domain is only meaningful when GSConfig=1, and modifying it when GSConfig=0

does not cause a performance change. DPrefDPref

Before the software can modify this state, it needs to use the SYNC instruction to ensure

that there are no pending accesses in the processor

Operation.

When set to 1, the processor performs hardware automatic prefetching for finger

operation. Otherwise, turn it off.

IPref

R/W

0 x1

Before the software can modify this state, it needs to use the SYNC instruction to ensure

that there are no pending accesses in the processor.

When set to 1, the processor performs hardware automatic prefetch for data access.

Otherwise, turn it off.

DPref

R/W

0 x1

Before the software can modify this state, it needs to use the SYNC instruction to ensure

that there are no pending accesses in the processor.

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7.35 LLAddr Register (CP0 Register 17, Select 0)

The LLAddr register is a 64-bit read-only register that holds the physical address of the recently occurred

Load Linked instruction. The LLAddr register is cleared when the exception returns.

Figure 7-37 illustrates the format of the LLAddr register; The LLAddr register fields are described in Table 7-

39.

Figure 7-37. LLAddr register format

Table 7-39 Description of the LLAddr register field

Domain

positi

Functional description

Read

Reset

name

/wri

value

PAddr

63.. 0

The physical address of the recently

There is no

occurred Load Linked directive

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7.36 XContext Register (CP0 Register 20, Select 0)

The XContext register is a read-write register that contains some page-table base address high-level

information filled in by the operating system software and some bits of the error virtual address where the TLB

exception occurs. According to the original design intent of the MIPS architecture, the information splited together

in the XContext register can form a pointer to an item in the page table, which can be accessed when a TLB

exception occurs. The page table accessible without any processing of the contents of the XContext register is a

single-level page table structure, with a page size of 4K bytes and each page table entry of 16 bytes, containing an

even page table entry and an odd page table entry with consecutive virtual addresses. When the page table does not

have this structure, the software needs to properly shift and concatenate the contents of the XContext register. For

an operating system with multilevel page tables, the XContext register can only be used to speed up address

generation for the last level of page table access.

The XContext register is primarily used in the XTLB Refill exception handler. However, when exceptions

such as TLB Refill, TLB Invalid, and TLB Mod occur, the BadVPN2 and R fields in the XContext register are also

updated, so the software can also use the XContext register in the corresponding exception handler.

The BadVPN2 and R domains in the XContext register copy some of the information in the BadVAddr

the BadVaddr register will be updated by the hardware, but the BadVPN2 and R fields of the Context register will

not be updated by the hardware.

Figure 7-38 illustrates the format of the XContext register; The XContext register fields are described in

Table 7-40.

Figure 7-38 XContext register format

PTEBase

BadVPN2

31430

BadVPN2

Table 7-40 Description of XContext register fields

Domain

positi

Functiona

Read

Reset

name

/wri

value

descripti

PTEBase

63.. 41

Page table base address high level. Configured by the operating system software according R/W

There is no

to the current page table.

When a TLB exception occurs, store the error virtual address 63.. A 62 - bit.

0B00: General user area;

40.. 39

0B01: Superuser area;

There is no

0B10: Retention;

0B11: Core area.

BadVPN2

38.. 4

When a TLB exception occurs, store the error virtual address of 47.. 13.

There is no

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7.37 Diag Register (CP0 Register 22, Select 0)

The Diag register is a proprietary register that controls the execution of the virtual machine and some internal

queues and special operations.

Figure 7-39 illustrates the format of the Diag register; Table 7-41 Table 7-32 Config register field description

describes each field of the Diag register

Above.

Figure 7-39 Diag register format

MID

Table 7-41 Description of Diag register fields

Domain

position

Function

Read/

Reset

name

write

value

descript

ion

Controls the readout value of the PRId register. When the bit is 0, the PRId readout value is

0x00146308; When the bit is 1, the PRId read value is 0x00006305. The latter is identical to the PRId of

the LS3A1000 chip processor. This bit can be modified to 1 in PMON to enable the

IDSEL

R/W

0 x0

operating system kernel and above running on GS464 to be compatible

with GS464E.

It is important to note that the IDSEL bit can only be modified once after each hard

restart. It is suggested that this revision be made in

PMON.

30.. 20

Read only is always 0.

Stores the MID of the address space accessed by the directive that triggered the

exception when exceptions such as TLB Refill, TLB Invalid, and TLB Mod occur.

When TLBWR and TLBWI are used to fill in THE TLB, the contents of the field will

be written into the TLB table entry to participate in the subsequent virtual and real

MID

19.. 18

R/W

0 x0

address mapping.

When TLB is read using TLBP and TLBR instructions, the MID content stored in the

read table entry is stored in this field. This field is used when the software reads and

writes the PWBase, PWField, PWSize registers to indicate which space the page table

configuration information is to be accessed.

The MID field can be written only when dig.vmm =1, and will be set to 0 no matter what

value is written when dig.vmm =0.

Whether the virtual and real address mapping of PC USES the flag of SpaceID

information, 0: Not used; 1: Use.

INST

R/W

0 x0

This field is only valid if the VMM position of the Diag register is 1, otherwise the field

can read and write normally but does not participate in any other operations.

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Domain

position

Function

Read

Reset

name

/wri

value

descript

ion

Empty FTLB when writing 1 to the bit. Note that the processor is concerned with the

FTLB

R0 / W

behavior of the bit being written to 1, clearing

FTLB is independent of whether the bit value is 1. The bit readout value is always 0.

Clear VTLB when writing 1 to the bit. Note that the processor is concerned with the

VTLB

R0 / W

behavior of the bit being written to 1, clearing

FTLB is independent of whether the bit value is 1. The bit readout value is always 0.

11.. 10

Read only is always 0.

GCAC

R/W

0 x0

When set to 1, CACHE0, CACHE1, CACHE3,

UCAC

R/W

0 x0

The CACHE15, CACHE21, and CACHE23 instructions will not trigger the coprocessor

exception (CpU).

WCAC

Set 1 to unrestrict the wait Cache operation.

R/W

0 x0

WISS

Set 1 to cancel the wait Issue operation.

R/W

0 x0

SISS

Cancel the stall Issue operation restriction when setting 1.

R/W

0 x0

SFET

Cancel the stall fetch operation restriction when set 1.

R/W

0 x0

Write 1 to empty ITLB for that bit. Note that the processor is concerned with the bit

ITLB

R0 / W

being written to 1, emptying FTLB

It doesn't matter if the bit value is 1. The bit readout value is always 0.

Write 1 to empty ITLB for that bit. Note that the processor is concerned with the bit

ITLB

R0 / W

being written to 1, emptying FTLB

It doesn't matter if the bit value is 1. The bit readout value is always 0.

To this bit, BRBTB and BTAC in the 1 empty-branch prediction are written. Note that

BTB

R0 / W

the processor focuses on that bit

Emptying FTLB does not matter whether the bit value is 1 or not. The bit readout value

is always 0.

The

When set 1, RAS is disabled for branch prediction of JR31.

R/W

0 x0

RAS

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7.38 GSCause Register (CP0 Register 22, Select 1)

The GSCause register is a read-only register that contains information related to the loong-core extension

when an exception occurs, such as whether the trigger exception instruction contains a prefix, and the specific

reason for the loong-core extension exception.

Figure 7-40 illustrates the format of the GSCause register; The GSCause register fields are described in Table

7-42.

Figure 7-40 GSCause register format

TLBInst

GSExcCode

Table 7-42 Describes the GSCause register fields

Domain

positi

Functiona

Read

Reset

name

/wri

value

descripti

31.. 12

Read only is always 0.

When the PSI exception is triggered by TLB instructions executed in guest state, the

specific TLB instruction type is recorded.

TLBInst[0] 1 means TLBP instruction;

TLBInst

11.. 8

0 x0

TLBInst[1] is a TLBR instruction.

TLBInst[2] 1 means TLBWR instruction;

A value of 1 for TLBInst[3] indicates a TLBWI, TLBINV, or TLBINVF instruction.

Read only is always 0.

GS -

6.. 2

Loongson extension exception coding.

0 x0

ExcCode

Read only is always 0.

1: The instruction that triggers the exception carries a prefix with a command length of 64

0 x0

bits;

0: The instruction that triggers the exception has no prefix and is 32 bits long.

Table 7-43 GSExcCode codes and corresponding exception types

ExcCode

mnemonic

desc

ribe

0 x00

Floating point stack exception

0 x01

VMMU

Virtual machine memory management unit exception

0 x02

VMTLBL

Virtual machine address space TLB exception (read data or fetch instructions)

0 x03

VMTLBS

Virtual machine address space TLB exception (write data)

0 x04

VMMod

Virtual machine address space TLB modification modification

0 x05

VMTLBRI

Virtual machine address space is not readable exception

0 x06

VMTLBXI

No exceptions can be made to the virtual machine address space

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7.39 VPID Register (CP0 Register 22, Select 2)

The VPID register is a self-defined register used to control the VPID information of the virtual machine.

Figure 7-39 illustrates the format of the Diag register; Table 7-41 Table 7-32 Config register field description

describes each field of the Diag register

Above.

Figure 7-41 VPID register format

VPMSK

VPID

Table 7-44 VPID register field description

Domain

positio

Functional

Read

Reset

name

descriptio

/writ

value

31.. 16

Read only is always 0.

The virtual machine mask is used to control the number of bits of virtual and real address

mapping in the VPID domain of Diag register. The mask also controls the actual bits of

virtual address high position participating in virtual address mapping, that is, it can

considered that the SEGBITS value of the processor at this time has been changed.

VPMSKVPID equivalent

Virtual address valid bit range

Valid value valid range SEGBITS

0 x00048 {Vaddr (63-62), Vaddr [47:0]}

0 x80vpid [7] 47 {Vaddr (63-62), Vaddr [46:0]}

VPMSK

15.. 8

R/W

0 x0

46 {0 xc0vpid [but] Vaddr (63-62), Vaddr [45:0]}

45 {0 xe0vpid [then] Vaddr (63-62), Vaddr [44:0]}

44 {0 xf0vpid [17] Vaddr (63-62), Vaddr [43:0]}

43 {0 xf8vpid [and] Vaddr (63-62), Vaddr [42:0]}

0 xfcvpid [when] {42 Vaddr (63-62), Vaddr [47:0]}

0 xfevpid [7:1] {41 Vaddr (63-62), Vaddr [47:0]}

0 xffvpid [away] {40 Vaddr (63-62), Vaddr [47:0]}

If VPMSK is configured with an invalid value, processor behavior is unpredictable.

This field is only valid if the VMM position of the Diag register is 1, otherwise the field

can read and write normally but does not participate in any other operations.

A virtual machine number whose significant digits are controlled by the VPMSK domain,

as described in the preceding item.

VPID

7.. 0

R/W

0 x0

This field is only valid if the VMM position of the Diag register is 1, otherwise the field

can read and write normally but does not participate in any other operations.

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7.41 DEPC Register (CP0 Register 24, Select 0)

The DEPC register is a 64-bit read-write register that contains the EJTAG debug exception or the PC that

continues to execute instructions after the exception is processed in debug mode.

In response to an exception, the processor writes to the DEPC register: the PC that directly triggers the

instruction of the exception.

When the instruction that directly triggered the exception is in the branch delay slot, record the PC of the

previous branch or jump instruction of the instruction, at the same time caus.bd

Debug.dbd is set to 1.

Figure 7-42 illustrates the FORMAT of the DEPC register; The DEPC register fields are described in Table 7-

45.

Figure 7-42 DEPC register format

DEPC

Table 7-45 Description of DEPC register field

Domain

positi

Functiona

Read

Reset

name

/wri

value

descripti

DEPC

63.. 0

EJTAG continues to execute instructions after completion of the exception processing on

R/W

There is

the PC.

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7.42 PerfCnt Register (CP0 Register 25, Select 0~7)

The PerfCnt register is a set of CP0 registers for processor performance event statistics. Each set of

performance counters is composed of a pair of even and odd-adjacent CP0 registers with Select number, namely,

Select0~1 produces a PerCnt0, Select2~3 produces a PerCnt1, Select4~5 produces a PerCnt2, and Select6~7

produces a PerCnt3. The even-number registers in each set of performance counters are Control registers (PerfCnt

Control Reg) used to define event categories and Control counting conditions. The odd-number register is the

value register (PerfCnt Counter Reg) for recording secondary values. See Table 7-46.

Table 7-46 PerfCnt register Select allocation

Performance

Select

PerfCnt register

counter

the value

The Select 0

PerfCnt Control Register 0

Select 1

The Register 0 PerfCnt

Counter

Select 2

PerfCnt Control Register 1

Select 3

The Register 1 PerfCnt

Counter

Select 4

PerfCnt Control Register 2

Select 5

The Register 2 PerfCnt

Counter

Select 6

PerfCnt Control Register 3

The Select 7

PerfCnt Counter Register 3

GS464E implements four sets of PerfCnt0~PerfCnt3 performance counters, and the register format definition

follows the example given in the MIPS specification. Unlike the MIPS specification, however, the PerfCnt register

in GS464E is actually a read/write interface to the processor core's internal performance counters rather than the

actual counters. In short, the software first establishes a relationship between the event to be operated on and a

specific performance counter inside the processor core by configuring the event information in the PerfCnt register,

and then reads and writes to the PerfCnt register of that group actually act on the specific performance counter

specified. This is designed to break the MIPS architecture limit of four performance events that a single processor

can count at the same time.

Figure 7-43 illustrates the format of the PerfCnt Control register; The PerfCnt Control register fields are

described in Table 7-47. Figure 7-44 illustrates the format of the PerfCnt Counter register; The PerfCnt Counter

Figure 7-43 PerfCnt Control register format

Table 7-47 PerfCnt Control register field description

Domain

positi

Functiona

Read

Reset

name

/wri

value

descripti

A value of 1 indicates that the next set of performance counters is

0 x1/0 x0

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Domain

positio

Functional

Read

Reset

name

descriptio

/writ

value

Event category.

0: Root state event, refers to the event occurring when guestTL0.GM =0.

1: Root state mediates the event, referring to guestTL0.GM =1 and! (root.status. EXL=0

24.. 23

and root.status. ERL=0 and root.debug.dm =0)

R/W

0 x0

22.15

Read only is always 0.

The Event

14.. 5

Event number.

R/W

0 x0

Performance counter overflow interrupt enablement.

0: This performance counter is not allowed to trigger an overflow interrupt.

R/W

0 x0

1: Allows this performance counter to trigger an overflow interrupt.

Event logging enablement bit in user mode. 0: Prohibit recording; 1: Recording is

R/W

0 x0

allowed.

Event recording enablement bit in supervisory mode. 0: Prohibit recording; 1: Recording

R/W

0 x0

is allowed.

Event logging enablement bit in core mode. 0: Prohibit recording; 1: Recording is

R/W

0 x0

allowed.

EXL

Status.EXL=1 and status. ERL=0. 0: Prohibit recording; 1: Recording is allowed.

R/W

0 x0

Figure 7-44 PerfCnt Counter register format

Event Count

Table 7-48 PerfCnt Counter register fields are described

Domain

positio

Functional

Read

Reset

name

descriptio

/writ

value

Performance event counters. The counter value is incremented by 1 each time the

PerfCnt Control register in the same group defines an event trigger. When the highest bit

Event

of the counter is 1, the PCI position of the Cause register is 1.

63.. 0

R/W

0 x0

Although the W bit of PerfCnt Control is always defined as 1,64 bit

Count

wide Event Count field where every bit can be read and written, the

actual Count range for GS464E does not exceed 48 bits. So when the

Event Count is read, it's the result of the actual counter's 48-bit numeric symbol

expanding to 64 bits; When the timer value is reset, only the low of Event Count is present

48 bits to be written.

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7.43 ErrCtl Register (CP0 Register 26, Select 0)

ErrCtl register is a register that can be read and written by the software. It ACTS as an interactive interface

between the Index Load Tag and Index Store Tag class CACHE instructions and the Parity/ECC check value of

Tag part data of all levels of the CACHE.It is also an interactive interface between the Index Load Data and the

Index Store Data class CACHE instruction and the Parity/ECC check value of the Data part of all levels of the

CACHE.

Figure 7-45 illustrates the format of the ErrCtl register; Table

7-49 Table 7-32 Config register field

description describes the ErrCtl register fields.

Figure 7-45 ErrCtl register format

ECC

Table 7-49 Description of ErrCtl register fields

Domain

posi

Functiona

Read

Reset

name

tion

/wri

value

descripti

31.. 8

Read only is always 0.

ECC

7.. 0

The CONTENTS of the ECC check value of the Tag or Data to be written or

R/W

There is

read.

137

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7.44 CacheErr Register (CP0 Register 27, Select 0)

The CacheErr register records the Parity check of I-Cache and ECC check of D-Cache. GS464E for

V-cache and S-Cache also perform ECC "check 1, check 2" checks, but do not store error checks into the

CacheErr register.

The CacheErr register has a different format for recording i-cache and D-cache errors. Figure 7-46 illustrates

the format of the CacheErr register for i-Cache error checking. Table 7-50 Table 7-32 Config Register fields

description describes each register field in this case.

Figure 7-46 Shows the format of the CacheErr register when used for i-Cache error-checking

information

6332

WAY

The

TYPE

Table 7-50 Field description of the CacheErr register when used for I-Cache error-checking

information

Domain

posi

Functiona

Read

Reset

name

tion

/wri

value

descripti

63.. 6

Read only is always 0.

Error flag for parity in the I-Cache Data section. 1: Check error; 0: Check no error.

Partial parity error flags on the I-Cache Tag.

1: Check error; 0: Check no error.

WAY

3.. 2

On which route did the calibration error occur?

The TYPE

1.. 0

Check the error type. Zero: I - Cache; 1: D - the Cache; 2, 3: reservations

Figure 7-47 illustrates the format of the CacheErr register for i-Cache error checking. Table 7-51 describes the

Figure 7-47 Shows the format of the CacheErr register when used for D-Cache error-checking

The

TYPE

Table 7-51 Describes the fields of the CacheErr register when it is used for d-Cache error-

138

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Domain

positi

Functiona

Read

Reset

name

/wri

value

descripti

D-cache Data Bank 6 verifies the 2-bit or more error identifier. 1: There are such

mistakes; 0: No such mistakes.

31.. 30

On which route did the d-Cache Data Bank 6 error occur?

D-cache Data Bank 5 verifies the error id. 1: Make a mistake; 0: No mistake.

D-cache Data Bank 5 verifies the 2-bit or more error identifier. 1: There are such

mistakes; 0: No such mistakes.

27.. 26

On which route did the d-Cache Data Bank 5 error occur?

D-cache Data Bank 4 verifies the error id. 1: Make a mistake; 0: No mistake.

D-cache Data Bank 4 verifies the 2-bit or more error identifier. 1: There are such

mistakes; 0: No such mistakes.

23.. 22

On which route did the d-Cache Data Bank 4 error occur?

D-cache Data Bank 3 verifies the error id. 1: Make a mistake; 0: No mistake.

D-cache Data Bank 3 verifies the 2-bit or more error identifier. 1: There are such

mistakes; 0: No such mistakes.

The W3

19.. 18

On which route did the d-Cache Data Bank 3 error occur?

D-cache Data Bank 2 verifies the error id. 1: Make a mistake; 0: No mistake.

D-cache Data Bank 2 verifies the 2-bit or more error identifier. 1: There are such

mistakes; 0: No such mistakes.

15.. 14

On which route did the d-Cache Data Bank 2 error occur?

D-cache Data Bank 1 verifies the error id. 1: Make a mistake; 0: No mistake.

D-cache Data Bank 1 verifies the 2-bit or more error identifier. 1: There are such

mistakes; 0: No such mistakes.

11.. 10

On which route did the d-Cache Data Bank 1 error occur?

D-cache Data Bank 0 verifies the error id. 1: Make a mistake; 0: No mistake.

D-cache Data Bank 0 verifies the 2-bit or more error identifier. 1: There are such

mistakes; 0: No such mistakes.

7.. 6

On which route did the D-Cache Data Bank 0 error occur?

D-Cache Tag check error flag. 1: Make a mistake; 0: No mistake.

The D-Cache Tag verifies two or more incorrect identifiers. 1: There are such mistakes;

0: No such mistakes.

3.. 2

Where did the D-Cache Tag error occur?

The TYPE

1.. 0

Check the error type. Zero: I - Cache; 1: D - the Cache; 2, 3: reservations

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7.45 CacheErr1 Register (CP0 Register 27, Select 1)

The CacheErr1 register is used to record the PC value of an instruction that checks for an i-cache check error,

as well as the physical address of an access that checks for a D-cache check error. It should be noted that for i-

cache error, the Cache block in error is not necessarily the Cache block with PC value in CacheErr1 register. For a

D-cache error, the Cache block in error is not necessarily the block with the physical address in the CacheErr1

the i-Cache Bank range at the wrong location. Combined with the information in CacheErr register, the error

location can be accurately located.

Figure 7-48 illustrates the format of the CacheErr1 register; Table 7-52 Table 7-32 Config Register field

description describes each field of CacheErr1 register.

Figure 7-48 CacheErr1 register format

BadPC/BadPaddr

Table 7-52 CacheErr1 register field description

Domain

positi

Functiona

Read

Reset

name

/wri

value

descripti

BadPC

63.. 0

Check the PC value of the instruction with an i-cache check error.

BadPaddr

63.. 0

Check the physical address of the access to which the D-cache check

error occurred.

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7.46 TagLo register (CP0 Register28, Select 0)

The TagLo register is a register that can be read and written by software. Together with the TagHi register, it

ACTS as an interactive interface between the Index Load Tag and Index Store Tag CACHE instructions and the

Tag Data of all levels of the CACHE, as well as the interface between the Index Load Data and Index Store Data

instructions and the Data of all levels of the CACHE.

When TagLo is used to access different caches, the exact format is also different. Figure 7-49 illustrates the

TagLo register for access

I-cache Tag format; Table 7-53 Table 7-32 Config Register fields description describes the register fields in

this case. Figure 7-49 Shows the format of the TagLo register used to access the I-Cache Tag

SCWAY

Table 7-53 TagLo registers describe the fields used to access the I-Cache Tag

Domain

positi

Functiona

Read

Reset

name

/wri

value

descripti

31.. 12

Tag low-level content to be written or read, corresponding to the

R/W

There is

physical address [31:12].

11.. 7

Can write and read normally, but do not participate in other operations.

R/W

There is

The state of a Cache block to be written or read.

R/W

There is

0: Cache block invalid; 1: Cache block valid.

5.. 4

Can write and read normally, but do not participate in other operations.

R/W

There is

SCWAY

3.. 0

Where in Scache is the Cache block to be written or read.

R/W

There is

Figure 7-50 illustrates the format of the TagLo register when accessing the D-Cache Tag. Table 7-54

describes the register fields in this case.

Figure 7-50 Shows the format of the TagLo register used to access the D-Cache Tag

SCWAY

Table 7-54 TagLo registers describe the fields used to access the D-Cache Tag

Domain

positi

Functiona

Read

Reset

name

/wri

value

descripti

31.. 12

Tag low-level content to be written or read, corresponding to the

R/W

There is

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physical address [31:12].

11.. 9

Can write and read normally, but do not participate in other operations.

R/W

There is

The "dirty" mark of a Cache block to be written or read.

1: Dirty lump; 0:

R/W

There is

Non-dirty block.

The state of a Cache block to be written or read.

7.. 6

R/W

There is

0: Invalid block; 1: Shared block; 2: Exclusive block; 3: Reserved, if using the processor

the result is uncertain.

5.. 4

Can write and read normally, but do not participate in other operations.

R/W

There is

SCWAY

3.. 0

Where in Scache is the Cache block to be written or read.

R/W

There is

Figure 7-51 illustrates the format of the TagLo register when accessing the V-Cache Tag. Table 7-55 shows

the register fields in this case

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The

descript

Figure 7-51 TagLo register is used to access the V-Cache Tag format

ion.

SCWAY

Table 7-55 TagLo registers describe the fields used to access the V-Cache Tag

Domain

positi

Functiona

Read

Reset

name

/wri

value

descripti

31.. 12

Tag low-level content to be written or read, corresponding to the

R/W

There is

physical address [31:12].

11.. 10

Can write and read normally, but do not participate in other operations.

R/W

There is

The instruction/data property of a Cache block to be written or read.

R/W

There is

Instruction block; 0: Data block.

The "dirty" mark of a Cache block to be written or read.

1: Dirty lump; 0:

R/W

There is

Non-dirty block.

The state of a Cache block to be written or read.

7.. 6

R/W

There is

0: Invalid block; 1: Shared block; 2: Exclusive block; 3: Reserved, if using the processor

the result is uncertain.

5.. 4

Can write and read normally, but do not participate in other operations.

R/W

There is

SCWAY

3.. 0

Where in Scache is the Cache block to be written or read.

R/W

There is

Figure 7-52 illustrates the format of the TagLo register for accessing the S-Cache Tag. Table 7-56 describes

the register fields in this case.

Figure 7-52 Shows the format of the TagLo register used to access the S-Cache Tag

PGC

Table 7-56 TagLo registers describe the fields used to access the S-Cache Tag

Domain

positi

Functiona

Read

Reset

name

/wri

value

descripti

31.. 16

Tag low-level content to be written or read, corresponding to the

R/W

There is

physical address [31:16].

15.. 12

Can write and read normally, but do not participate in other operations.

R/W

There is

143

The PageColor bit of the Cache block to be written or read. When the

PGC

11.. 10

system USES 4KB base page size, both digits are significant, while when

R/W

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the system USES 8KB base page size, only the 13th digit is significant.

The relevant PageColor

For a detailed description of bits, see section 5.4.5.

On a write operation, setting 0 means clearing the directory entry of

R/W

There is

the Cache block to be written, and setting 1 means waiting

The contents of the directory entry written to the Cache block remain

unchanged. The field contents are meaningless when read out.

The "dirty" mark of a Cache block to be written or read.

1: Dirty lump; 0:

R/W

There is

Non-dirty block.

The state of the directory entry corresponding to the Cache block to be

R/W

There is

written or read.

1: Dirty directory; 0: The catalog is clean.

The state of the Cache block to be written or read.

1: Effective block; 0:

R/W

There is

Invalid block.

5.. 0

Can write and read normally, but do not participate in other operations.

R/W

There is

Figure 7-53 illustrates the format of the TagLo register when it is used to access the Data portion of the Cache

at each level. Table 7-57 describes the register fields in this case.

144

Loongson 3A3000/3B3000 processor user manual. Part ii GS464E processor core V1.2 - page 8