Loongson 3A3000/3B3000 processor user manual. Part ii GS464E processor core V1.2

龙芯 3A3000/3B3000 处理器用户手册 y 下册

Figure 7-53 The TagLo

Format for each level of Cache Data

The DATA

Table 7-57 TagLo registers describe the fields used to access each level of Cache Data

Domain

positi

Functiona

Read

Reset

name

/wri

value

descripti

The

31.. 0

The low 32-bit contents of the Data Bank in a Cache block to be written

R/W

There is

DATA

or read.

Programming tip: Maintain all levels of the Cache as the software fills the contents of the Cache

using the Index Store Tag and Index Store Data instructions

To satisfy the Cache consistency requirements of GS464E. Otherwise the behavior of the processor will be

uncertain.

143

龙芯 3A3000/3B3000 处理器用户手册 y 下册

7.47 DataLo Register (CP0 Register 28, Select 1)

In GS464E, the DataLo and DataHi registers are not used as interactive interfaces to access the Data parts of

the various levels of caches, but only as interactive interfaces to the pre-encoded Data parts of the I-cache when the

Index Load Data and Index Store Data class Cache instructions access the I-cache. In other cases, DataLo allows

the software to read and write without participating in anything else.

Figure 7-54 illustrates the format of the DataLo register used to access the I-cache; Table 7-58 Table 7-32

Config register fields description describes the register fields in this case.

Figure 7-54 The DataLo register is in the format used for i-Cache access

ITYPE

Table 7-58 Describes the fields the DataLo registers are used for i-Cache access

Domain

positio

Functional

Read

Reset

name

descriptio

/writ

value

ITYPE

31.. 0

The [31:0] bit of the pre-decoded information of the I-cache block to be written or read.

R/W

There is no

Programming tip: Maintain all levels of the Cache as the software fills the contents of the Cache

using the Index Store Tag and Index Store Data instructions

To satisfy the Cache consistency requirements of GS464E. Otherwise the behavior of the processor will be uncertain.

144

龙芯 3A3000/3B3000 处理器用户手册 y 下册

7.48 TagHi Register (CP0 Register 29, Select 0)

The TagHi register is a register that can be read and written by software. Together with the TagLo register, it

ACTS as an interactive interface between the Index Load Tag and Index Store Tag CACHE instructions and the

Tag Data of all levels of the caches, as well as the interface between the Index Load Data and Index Store Data

instructions and the Data of all levels of the caches.

Figure 7-55 illustrates the format of the TagHi register for accessing the Cache tags at each level. Table 7-59

describes the register fields in this case.

Figure 7-55 Shows the format of the TagHi register used to access the various Cache tags

Table 7-59 Field descriptions of the TagHi registers used to access the various Cache tags

Domain

positio

Functional

Read

Reset

name

descriptio

/writ

value

31.. 12

Can write and read normally, but do not participate in other operations.

R/W

There is no

15.. 0

Tag high-level content to be written or read, corresponding to the physical address

R/W

There is no

[47:32].

Figure 7-56 illustrates the format of the TagLo register for accessing each level of Cache Data. Table 7-60

describes the register fields in this case.

Figure 7-56 Shows the format of the TagHi register used to access each level of Cache Data

The DATA

Table 7-60 Describes the fields used to access each level of Cache Data in the TagHi register

Domain

positio

Functional

Read

Reset

name

descriptio

/writ

value

The

31.. 0

The 32-bit height of the Data Bank in the Cache block to be written or read.

R/W

There is no

DATA

Programming tip: Maintain all levels of the Cache as the software fills the contents of the Cache

using the Index Store Tag and Index Store Data instructions

To satisfy the Cache consistency requirements of GS464E. Otherwise the behavior of the processor will be

uncertain.

145

龙芯 3A3000/3B3000 处理器用户手册 y 下册

7.49 DataHi Register (CP0 Register 29, Select 1)

In GS464E, the DataLo and DataHi registers are not used as interactive interfaces to access the Data parts of

the various levels of caches, but only as interactive interfaces to the pre-encoded Data parts of the I-cache when the

Index Load Data and Index Store Data class Cache instructions access the I-cache. In other cases, DataHi allows

the software to read and write without participating in anything else.

Figure 7-57 illustrates the format of the DataHi register used to access i-cache; Table 7-61 Table 7-32 Config

Figure 7-57 DataHi register in the format used for i-Cache access

ITYPE

Table 7-61 DataHi registers describe the fields used for i-Cache access

Domain

positio

Functional

Read

Reset

name

descriptio

/writ

value

31.. 24

Can write and read normally, but do not participate in other operations.

R/W

There is no

ITYPE

23.0

The [55:32] bit of the pre-decoded information of the I-cache block to be written or read.

R/W

There is no

Programming tip: Maintain all levels of the Cache as the software fills the contents of the Cache

using the Index Store Tag and Index Store Data instructions

To satisfy the Cache consistency requirements of GS464E. Otherwise the behavior of the processor will be

uncertain.

146

龙芯 3A3000/3B3000 处理器用户手册 y 下册

7.50 ErrorEPC Register (CP0 Register 30, Select 0)

The ErrorEPC register is a 64-bit read-write register that functions similar to the EPC register except that it is

only used to store the INSTRUCTIONS that continue to execute after cold reset, soft reset, non-blocking interrupt,

and Cache error exception processing have been completed, and the ErrorEPC register does not have an EPClike

branch delay slot identifier (Cause.BD).

In response to the above exception, the processor

hardware writes to the ErrorEPC register: the PC

that directly triggers the exception's instruction.

When an instruction that directly triggers an exception is in a branch delay

slot, record the PC of the previous branch or jump instruction of the

instruction. Figure 7-58 illustrates the format of the ErrorEPC register;

Table 7-62 describes the fields of the ErrorEPC register.

Figure 7-58. ErrorEPC register format

DEPC

Table 7-62 Description of ErrorEPC register fields

Domain

positio

Functional

Read

Reset

name

descriptio

/writ

value

ErrorEPC

63.. 0

The PC of the instruction that continues to execute after the exception processing

R/W

There is no

completes.

147

龙芯 3A3000/3B3000 处理器用户手册 y 下册

7.51 DESAVE Register (CP0 Register 31, Select 0)

The DESAVE register is a 64-bit read-write register used to debug exception handlers' temporary data.

Typically, debugging exception handlers save a general purpose register with the DESAVE register and then use

the general purpose register as a base address register for access instructions to save the current context to a

specified area, such as a DMSEG segment.

The DESAVE register is not allowed in kernel mind software.

Figure 7-59 illustrates the format of the DESAVE register; Table 7-63 describes the DESAVE register fields.

Figure 7-59 DESAVE register format

The Data

Table 7-63 Description of DESAVE register fields

Domain

positio

Functional

Read

Reset

name

descriptio

/writ

value

The Data

63.. 0

Debug data stored by exception handlers.

R/W

There is no

148

龙芯 3A3000/3B3000 处理器用户手册 y 下册

7.52 KScratch1~6 registers (CP0 Register 31, Select 2~7)

The KScratch1~6 registers are a set of 64-bit read-write registers used to hold scratch1 ~6 temporary data for

core mental software.

Software in Debug Mode cannot access Kscratch1-6, but at this point the software can scratch1-6 through the

DESAVE register.

Figure 7-60 illustrates the format of the KScratch register; Table 7-64 describes the KScratch register fields.

Figure 7-60 KScratchn register format

The Data

Table 7-64 KScratchn register fields are described

Domain

positio

Functional

Read

Reset

name

descriptio

/writ

value

The Data

63.. 0

Kernel mentality software temporary storage data.

R/W

There is no

149

龙芯 3A3000/3B3000 处理器用户手册 y 下册

8 Analysis and optimization of processor performance

The performance analysis and optimization of GS464E is mainly accomplished through the performance

counter of hardware integration. The performance counter is used to count the occurrence times of some events

within the processor, which is an important support for the performance verification, compiler optimization and

software performance tuning after silicon. In addition, since the statistical significance of certain events recorded

by these performance counters is related to the power consumption of the chip at run time, performance counters

can also be used to guide the power management of the chip.

The performance counter used in GS464E consists of two parts: the processor core performance counter and

the Shared cache performance counter.

8.1 Organization and access method of performance counters

8.1.1 Processor core performance counter

Each PROCESSOR core of GS464E implements 28 sets of performance counters, divided equally into

FETCH module, RMAP module, ROQ module, FIX module, FLOAT module, MEMORY module and

CACHE2MEM module. Each module contains 4 sets of performance counters respectively. Each set of

performance counters corresponds to two physical registers, one for counting (48-bit counters) and one for

controlling counting. Hardware counters within each module can only be used to count events related to that

module. Any set of performance counters within a module can count any performance count event associated with

that module.

The Performance Counter of the GS464E processor core is still configured and accessed by the software

through the CP0 Performance Counter register under the MIPS architecture, but in a slightly different form from

the traditional MIPS processor. Specifically, the Performance Counter register in CP0 exists only as an interface

for configuration and access. The hardware Counter to which read and write operations are delivered is

dynamically determined by the event number configured in the Performance Counter register. The software will

first configure an event on the Performance Counter register with an odd number, and the internal hardware of the

processor will establish a one-to-one mapping relationship between this event and the hardware Counter in the

module it belongs to. After the mapping relationship is established, the software reads and writes the even number

Performance Counter register, then it will directly operate the mapped hardware Counter. Finally, the software

starts the hardware counter to count. In particular, Performance Counter needs to initialize the Performance

counters in all modules as invalid before each configuration. This is done by configuring each module with the

maximum event number allowed for that module event and setting the counter value to 0.

8.1.2 Shared cache performance counters

Each GS464E Shared cache body implements four sets of 48-bit performance counters. Each set of

performance counters corresponds to two physical registers, one for counting (48-bit counters) and one for

controlling counting. Each performance counter can count any performance count events that occur within the

Shared cache.

Performance counters of the four Shared cache bodies in the Loongson 3A3000 are accessed via the Chip's

150

龙芯 3A3000/3B3000 处理器用户手册 y 下册

Scache0

Scache1

Scache2

Scache3

name

PerfCnt2

0 x0828

0 x0928

0 x0a28

0 x0b28

PerfCtl3

0 x0830

0 x0930

0 x0a30

0 x0b30

PerfCnt3

0 x0838

0 x0938

0 x0a38

0 x0b38

Using an example

If you want to count the total number of Scread and DMaread received by Scache0, you can do the

following:

z Step1: write sc0_perfcnt0 as 0 (sd $0, 0x3ff00808), sc0_perfcnt1 as 0 (sd $0, 0x3ff00818), and

sc0_perfcnt2 as 0 (sd $0, 0x3ff00828)

z Step2: write sc0_perfctrl0 as 1 (sd value_1,0x3ff00800), sc_perfctrl1 as 9 (sd value_9, 0x3ff00810), and

sc_perftrl2 as 10 (sd value_10,0x3ff00820)

z Step3: execute the program

z Step4: read sc0_perfcnt0 (ld t0, 0x3ff00808), sc0_perfcnt1 (ld t1, 0x3ff00818), sc0_perfcnt2 (ld t2,

0x3ff00828); The result of T0 is scread total, and that of T1 + T2 is DMaread total.

8.2 Processor performance count events

The performance events defined by GS464E fall into three broad categories:

The first is used to analyze the characteristics of a program at the instruction set level. Specifically, the number

of different types of instructions in pipeline submission phase is counted so as to obtain the distribution of

instruction types in dynamic execution of the program.

The second category is used to analyze performance bottlenecks that occur when program code interacts with

processor microstructures, with the goal of optimizing the program. Mainly by counting the various events that

cause the pipeline to block. In addition to basic events such as Cache misses, queue full times, and branch

prediction error times, GS464E also added a batch of statistics on delay cycles, such as the number of cycles in

regmap pipelines-level disconnection caused by clearing the front-end pipeline after branch misprediction.

The third category is used to accumulate data for design space exploration, and the starting point is to optimize

the microstructure. For example, the current dual-access memory component is implemented with full-function

dual-port RAM, which is much more expensive than single-port RAM. Therefore, statistics are added on the

number of collisions between the two load operations dcache RAM in the same stroke. In the existing structure,

such collisions do not actually cause pipeline blocking, so it does not affect program performance.

8.2.1 Processor core performance count event definition

The performance counter event definition for the GS464E processor core is shown in Table 8-2.

Table 8-2 Processor core performance counter event definitions

Event

no.

descripti

The FETCH module

The number of cycles the Inst Queue is completely empty

151

龙芯 3A3000/3B3000 处理器用户手册 y 下册

Event

no.

descripti

The number of instructions entering the Inst Queue is equal to 6

The number of instructions entering the Inst Queue is equal to 7

The number of instructions entering the Inst Queue is equal to 8

In cache space the number of instructions to InstQueue is less than 8 because they cross the cacheline boundary

The number of front line blocking cycles due to a full Inst Queue

Number of decoded instructions per period

Number of decoded instructions per cycle from the Loop Buffer

The number of loops to fetch the instruction from the Loop Buffer

Number of identified loops (both available and unavailable)

The number of branch instructions decoded per period is equal to 0

The number of branch instructions decoded per period is equal to 1

The number of branch instructions decoded per period is equal to 2

Front-end pipeline block due to Icache Miss

BrBTB failed to predict the front-end pipeline blockage caused by Taken Branch

The number of Icache misses initiated by the Icahe module and received by MISSq

Number of ITLB Misses but hits in TLB

Number of times ITLB was flushed

The RMAP module

Resource allocation is blocked

GR renames resource full blocked

GR renaming resource full false block (when the incoming instruction does not require a fixed point renaming

resource)

FR rename resource full block

FR renaming resource full false block (no floating-point renaming resource required for incoming instructions)

FCR renames resource full block

FCR renaming resource full false block (no need for FCR renaming resource when entering instruction)

ACC rename resource full block

ACC rename resource full false block (there is no need for ACC rename resource to enter instruction)

DSPCtrl renames resource full block

DSPCtrl rename resource full false block (there is no need for DSPCtrl to rename resource when entering

command)

BRQ full block

BRQ full false blocking (there is no need to enter BRQ in order to enter)

FXQ full block

FXQ full false block (there is no need to enter FXQ in the instruction to be entered)

FTQ full block

FTQ full false blocking (there is no need to enter FTQ in order to enter)

MMQ full block

MMQ full false block (no need to enter MMQ instruction)

CP0Q full block

CP0Q full false block (no need to enter CP0Q in order to enter)

153

龙芯 3A3000/3B3000 处理器用户手册 y 下册

Event

no.

descripti

Operands emitted from the RegMap to each transmitter queue per cycle

Exception (not including branch error prediction) The cost of cleaning the assembly line (after the Regmap

assembly line is cleared by exception until the first instruction reaches the Regmap assembly line)

The branch mispredicted the cost of clearing the pipeline

ROQ module

128

Internal pipeline clock

129

Number of instructions per cycle

130

Committed ALU operation

131

The FALU operation is committed

132

Committed Memory/CP0/ floating point swap operation

133

The load operation submitted

134

Committed Store operations

135

Committed LL class operations

136

Committed SC class operations

137

Committed non-aligned load operation

138

Committed non-aligned Store operations

139

Number of exceptions and interrupts

140

Number of interrupts

141

From the time the interrupt signal is received by ROQ to the time the interrupt exception is generated

142

The first instruction from the interrupt signal received by the ROQ to the interrupt exception handler enters the

ROQ

143

Number of virtual machine exceptions

144

Number of wrong address exceptions

145

TLB related exception number

146

Number of TLB Refill exceptions

147

Processing time of THE TLB Refill exception (the TLB Refill exception starts the cleanup line and returns the

ERET of the TLB Refill exception)

148

Branch instructions submitted by BRQ

149

The jump Register branch instruction submitted by BRQ

150

BRQ submits jump and link branch instructions

151

BRQ submits branch and Link branch instructions

152

BRQ submits BHT branch instructions

153

Likely branch instructions submitted by BRQ

154

Branch instructions from NOT Taken submitted by BRQ

155

Branch instructions from THE TAKEN submitted by BRQ

156

BRQ submits branch instructions that predict incorrectly

157

BRQ submits an incorrect jump Register branch instruction

158

BRQ submits an incorrect prediction for the jump and link branch instruction

159

BRQ submitted branch and Link branch instructions that predicted wrong

160

BRQ submits BHT branch instructions that predict incorrectly

161

A likely branch of a BRQ submission that predicts something wrong

162

Branch instructions not taken submitted by BRQ that predicted wrong

155

龙芯 3A3000/3B3000 处理器用户手册 y 下册

Event

no.

descripti

192

No launch FXQ

193

FXQ emits execution operands

194

The operands emitted by FXQ to the FU0 feature

195

The operands that FXQ emits to the FU1 feature to perform

196

In FU0, the fixed-point multiplication component is in execution state

197

In FU0, the fixed-point division component is in execution state

198

In FU1, the fixed-point multiplication component is in the execution state

199

The fixed-point division component in FU1 is in execution state

FLOAT module

256

No launch FTQ

257

FTQ emits execution operands

258

Operands performed by FTQ emitted to FU3 features

259

The operands that FTQ transmits to the FU4 feature to perform

260

FU3 is free and FU4 is full, but FTQ only has FU4 to launch

261

FU4 is free and FU3 is full, but FTQ only has FU3 to launch

262

Emits a scalar floating point operand per period

263

Number of 64-bit multimedia acceleration instructions per cycle (instruction names with "GS" prefix)

264

Number of 64-bit multimedia acceleration instructions emitted per cycle (instruction names without "GS"

prefix)

272

The floating - point division/root in FU3 is in the execution state

274

The floating - point division/root in FU4 is in the execution state

The MEMORY module

320

No launch MMQ

321

MMQ transmits execute operands

322

In MMQ, FU2 instructions are emitted per beat

323

In MMQ, FU5 instructions are emitted per beat

324

Load times

325

Store launches

326

The source operand has at least one floating-point access instruction number

327

The number of times an instruction is emitted with both fixed - point and floating - point operands

329

Number of blocks for wait_first

330

The number of cycles the SYNC operation blocks

331

Number of cycles stall_issue blocks

332

The software pre-fetch operation is launched

333

The number of times a newly emitted access operation has blocked a store operation from writing to dCache

334

There is a bank conflict between two Loads in the same beat

337

The number of times dcachewrite0 and 1 are both valid

338

Number of successful SC class instructions executed

339

Number of Store dCAhe Misses (including misses and non-EXC states)

340

The number of Dcache misses caused by the dcache Shared status of the store instruction

CACHE2MEM module

157

龙芯 3A3000/3B3000 处理器用户手册 y 下册

Event

no.

descripti

342

Load hit times

343

Fwdbus2 number

344

Fwdbus5 number

345

Total number of FWDBUS, FWdbus2 + FWdbus5

346

Number of callback operations caused by load and store address conflicts (DWaitStore)

347

Number of exceptions caused by load and store address conflicts (MISPEC)

348

The number of times cp0qhead was rolled back due to a dcacheWrite failure

349

Cp0q dMEMread request times

350

Number of Duncache requests issued by CP0Q

351

Resbus2 occupies resbus5 times, LQ, LQC1, and so on have two dest accesses

352

Software prefetch hit times in L1 Dcache

353

Store prefetch hit times in L1 Dcache

354

Number of Misses in L1 Dcache prefetched by store software

355

Load prefetch hits in L1 Dcache

356

Number of misses in L1 Dcache prefetched by LOAD software

357

The number of times store software prefetches share State in L1 Dcache

358

Specfwdbus2 number

359

Specfwdbus5 number

360

Specfwdbus frequency: SPECFWdbus2 + SpecfWdbus5

384

Number of times vCache was accessed by a data load request

385

Number of data Store requests to vCache

386

Number of times the data request accessed vCache

387

Number of times the instruction requested vcache access

388

Number of Vcache visits

389

The number of times the software prefetches vCache

390

Number of vcache load hits

391

Number of vcache Store hits

392

Number of Vcache data hits

393

Number of vcache directive hits

394

Number of Vcache hits

395

The Vcache software configuration prefetch hit times

396

Number of vcache load failures

397

Number of vCache store failures

398

Vcache data invalidation times

399

Vcache instruction invalidation times

400

Vcache invalidation times

401

Vcache software configuration prefetch invalidation times

402

The number of times that valid blocks are invalid dropped by vCache under extreQ operation

403

The number of times vcache was degraded by a WTBK operation

404

The number of times an INV operation has invalidated a vcache block

159

龙芯 3A3000/3B3000 处理器用户手册 y 下册

Event

no.

descripti

406

Number of processor core read requests to the external bus

407

Number of processor core write requests to the external bus

408

Number of bus write requests with write data

409

The bus read request is blocked because of a conflict with the bus write request address

410

Number of WTBK requests processed by MISSq

411

Missq handles the number of INVWTBK requests

412

Number of INV requests processed by MISSq

413

The number of INV class requests (the three above) that MISSq handles

414

Total number of refill (including exreq and replace+ Refill)

415

Total number of times for icache of Refill

416

Total number of times against dCache of Refill

417

The number of times the refill (replace + refill)

418

Number of times a DCache Shared block refill

419

Number of exc blocks of a Dcache refill

420

Total number of refill data (replace+ Refill)

421

Total number of refill instructions (replace+ Refill)

422

The number of times a valid block is replaced by dcache

423

The number of times a Shared block is replaced by dcache

424

The number of times dcache replaces an exC block

425

Number of times dcache replaces a dirty block

426

The number of times icache replaces valid data

427

Vcache replacement times

428

The number of times vcache replaces a useful block

429

The number of times vcache replaces a Shared block

430

The number of times vcache replaces an EXC block

431

Number of times vcache replaces a dirty block

432

The number of times vcache replaces a useful DC block

433

The number of times vcache replaces a useful IC block

434

Accumulate the number of load requests not returned from scache per beat (missq has only 15 items at most for

processing scache requests)

435

Add up the number of store requests not returned from scache per beat

436

Add up the number of finger requests not returned from scache per beat

437

The total number of SC Reads sent

438

The total number of load sent in scread

439

Total number of stores sent in Scread

440

Total number of scread data access

441

Total number of scread directive accesses

442

Scread non-prefetched total number

443

Scread total number of non-prefetched data Load

444

Total number of scread non-prefetched data Store

445

Total number of non-prefetch data access in Scread

161

龙芯 3A3000/3B3000 处理器用户手册 y 下册

Event

no.

descripti

447

The total number of scread prefetches sent out

448

Number of load prefetch in scread sent

449

Number of store prefetch sent in Scread

450

Total number of scread prefetch data access

451

Total number of scread prefetch instruction accesses

452

Number of software prefetch requests processed by MISSq

453

The number of SCwrite emitted by MISSq

454

Number of SCwrite initiated by MISSq due to replace operation

455

The number of RESP class SCwrite issued by MISSq because of invalid operation

456

Missq is a SCwrite operation initiated by the replace operation and the replace is a valid block

457

Missq actually accepts the number of requests miss_en

458

Missq really accepts the number of load requests MISS_en

459

Missq actually accepts the number of store requests miss_en

460

The number of data accesses that MISSq actually accepts

461

The number of instruction accesses that MISSq actually receives

462

Item occupancy condition of MISSq (NON-null item of MISSq)

463

Missq normal access possession condition

464

Missq refers to the access possession condition

465

Missq external request occupancy condition

466

Missq prefetch request occupancy condition

467

The number of beats occupied by MISSq (the number of beats with valid items in MISSq, i.e., the time when

MISSq is not empty)

468

Missq ordinary access to the number of item beats

469

Number of beats in MISSq to refer to the item

470

Missq external request item number of beats

471

Missq prefetch request number of item beats

472

Missq full count (MISSq cannot accept normal access, missq valid item is not less than 15)

473

The number of times the LOAD request encounters a prefetch in MISSq

474

Number of times the LOAD request encounters a prefetch pre_scref in MISSq

475

The number of times the LOAD request encounters a prefetch pre_wait in MISSq

476

The number of times the LOAD request encounters a prefetch pre_rdy in MISSq

477

The number of times the store request encounters a prefetch pre_scref and load operation in MISSq

478

Store request encounters prefetch pre_rdy and state=shard times in MISSq

479

The store request encounters prefetch pre_wait and load operations in MISSq

480

The number of times a store request encounters a prefetch pre_scref and a store operation in MISSq

481

Store request encounters prefetch pre_rdy and state=exc times in MISSq

482

The number of times a store request encounters a prefetch pre_wait and store operation in MISSq

483

Number of times store request encounters prefetch in MISSq (including hit prefetch in Store and hit prefetch in

Load)

484

Number of times the store request encounters a valid prefetch in MISSq (hit prefetch in Store)

485

Number of times all requests are prefetched in MISSq (load+store)

163

龙芯 3A3000/3B3000 处理器用户手册 y 下册

Event

no.

descripti

488

Number of times all requests are prefetched in MISSq with pre_wait (load+store)

489

The number of times a finger request encounters a prefetch in MISSq

490

Number of times the fetch request encounters prefetch in MISSq by prescref

491

The number of times the finger request encounters prefetch pre_rdy in MISSq

492

The number of times the fetch request encounters pre_wait prefetch in MISSq

495

The number of times the data and fetchfinger are prefetched by PRE_rdy in MISSq

496

The number of times the data and fetching point encounters pre_wait prefetch in MISSq

497

Number of times the hardware Load prefetch request is cancelled by Scache ¹⁵

498

Number of times the hardware Store prefetch request is cancelled by Scache

499

Number of times the hardware data access prefetch request is cancelled by Scache

500

Hardware fetch refers to the number of Scache cancels for a prefetch request

501

Number of times the hardware prefetch request is cancelled by Scache

502

The number of hardware load prefetches

503

Number of hardware Store prefetches

504

The number of hardware data access prefetches

505

Hardware fetch refers to the number of prefetches

506

Number of hardware prefetches

507

Tagged triggered load pre-fetch number

508

The number of load prefetches triggered by MISS

509

Number of store pre-fetches triggered by Tagged

510

The number of store prefetches triggered by Miss

511

Number of pre-fetches of data access triggered by TAGGED

512

The number of pre-fetching data triggered by MISS

513

Number of pre-fetches of tagged triggered instructions

514

The number of prefetch instructions triggered by MISS

515

Number of pre-fetches tagged triggers

516

The number of prefetches triggered by MISS

517

The number of load prefetches accepted by MISSq

518

The number of store prefetches accepted by Missq

519

The number of data access prefetches accepted by MISSq

520

The number of prefetches of instructions accepted by MISSq

521

Number of prefetters accepted by MISSq (repeat requests do not enter MISSq)

522

The number of valid load prefetches back from scache

523

Number of valid store prefetches returned from scache

524

Number of valid data access prefetches returned from scache

525

Number of prefetches of instructions coming back from scache

526

Effective prefetch from scache (pre_scref->rdy || pre_scref->pre_rdy)

527

The number of load prefetters that can enter PRE_rdy

528

The number of prefetchings from the store that can enter pre_rdy

529

The number of data access prefetchings that can enter PRE_rDY

165

龙芯 3A3000/3B3000 处理器用户手册 y 下册

Event

no.

descripti

530

Prefetching number of instructions that can enter PRE_rdy

531

Number of prefetchings that can enter pre_rdy (pre_scref-> pre_rdy)

532

Accumulate the number of load prefetch requests per beat in PRE_rdy

533

Accumulate the number of store prefetch requests in PRE_Rdy per beat

534

Add up the number of data access prefetch requests in PRE_Rdy per beat

535

Add up the number of prefetch requests per beat in PRE_Rdy

536

Add up the number of pre_rdy requests per beat

537

Accumulate the number of prefetches per beat that are in pre_scref and hit by the normal load request

539

Accumulate the number of prefetches per beat that are in pre_scref and hit by normal store requests

540

Accumulate the number of prefetches per beat that are in pre_scref and hit by the normal data access request

541

Accumulate the number of prefetches per beat that are in pre_scref and are hit by normal fetches

542

Accumulate the number of prefetches per beat that are in pre_scref and hit by normal access

543

The number of prefetches hit is accessed by load in the pre_scref state

544

The number of prefetches that are hit by store access in the pre_scref state

545

The number of prefetches that are hit by data access in the pre_scref state

546

In the prescref state the number of prefetches to access the hit is referred to

547

The number of prefetches hit in the pre_scref state, that is, the number of rdy from pre_scref->

548

Number of loads from the pre_scref state back to the MISS state

553

The number of prefetches of hits that are accessed by load in the pre_wait state

554

The number of prefetches that are store-accessed hits in the pre_wait state

555

The number of prefetchings that are hit by data access in the pre_wait state

556

In the pre_wait state, the number of prefetchings to the hit is referred to

557

The number of prefetchings hit in pre_wait state, that is, the number of pcmisses from pre_wait ->

558

Prefetch item in pre_wait state that is replaced because MISSq cannot accept normal access

559

Prefetch item in pre_rdy state that is replaced because MISSq cannot accept normal access

560

The number of times the prefetch item is INV

561

Accumulate the prefetching of each load

562

Accumulates whether this load prefetches an item

563

Accumulates the prefetching item of each auction store

564

Whether the total prefetch of this auction store occupies the item

565

Accumulate the prefetching item of each beat

566

Whether to prefetch the item of the accumulative auction data

567

Accumulates the precapture of each beat

568

Whether the cumulative prefetching refers to the item of prefetching

569

Cumulative load prefetch number of hits in pre_scref and PRE_RDY

570

Cumulative store prefetch number of hits in pre_scref and PRE_Rdy

571

Cumulative number of prefetched data hits in PRE_scref and PRE_RDY

572

Cumulative number of prefetches in prescref and PRE_RDY

573

Cumulative number of prefetches in PRE_SCREf and PRE_RDY

166

龙芯 3A3000/3B3000 处理器用户手册 y 下册

8.2.2 Shared cache performance count event definition

Table 8-3 Shared cache performance counter event definitions

Event

no.

descripti

Since there is no switch marker in CTRL, a configuration of 0 indicates that it is not on.

Number of requests received for all requests

Number of cachable requests received

Receive all non-DMA operations of cachable's request request

Received all non - fetching attributes of the Cachable request request

All REQ_READ requests received for cached

All REQ_WRITE requests received for cached

REQ_READ for cached received for all non-prefetched properties

REQ_WRITE for all non-prefetched properties received from cached

All DMAREAD requests received for cached

All DMAWRITE requests received for cached

Received all of uncached's DMAREAD

Received all DMAWRITE of Uncached

Number of ALL DMA requests received

All the types you'll receive will be the number of requests for scache_prefx

The number of prefetches accepted by the Scache hardware itself

All received types are the number of requests for STORE_fill_full

All responses received for conformance requests

The number of all responses received for consistency with dirty data

A write back to the previous cache active replacement received

The number of higher-level active substitutions received with dirty data

Number of read requests to Memory caused by cached access

Number of write requests to Memory caused by cached access

The number of times the scache result is Miss

The query scache result is the number of all reqreads of Miss

Query the scache result as the number of all REqwrites of Miss

Query scache for the number of scache hits but pagecolor does not hit

REQREAD queries scache, resulting in a hit in a clean block

REQREAD queries scache, resulting in a hit in someone else's EXC block

REQWRITE queries scache, and the result hits the clean block

REQWRITE query scache, result hit in someone else's EXC block

A WRITE query scache results in a block that is being Shared by multiple cores

Cached DMAREAD queries scache and hits

Cached DMAWRITE queried scache, did not hit

Cached DMAWRITE queries scache with an INVALIDATION of the CPU

Number of INV requests made to the CPU for consistency

Number of WTBK requests made to the CPU for consistency

The number of INVWTBK requests made to the CPU for consistency

161

Loongson 3A3000/3B3000 processor user manual. Part ii GS464E processor core V1.2 - page 9