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Loongson 3A3000/3B3000 processor user manual. Part ii GS464E processor core V1.2 - page 6

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The interrupt source of hardware interrupt comes from the processor, and the 6 interrupt input pins on the

processor interface are sampled by the hardware beat by beat. The software needs to reverse traverse the interrupt

routing path of the system to clear the interrupt state on the terminal device or routing path, so as to clear the

processor's hardware interrupt.

In addition to global interrupt enablement, each interrupt source contains an interrupt mask bit. The generation

relationships of each interrupt request are shown in Table 6-4.

Table 6-4 Generation of each interrupt request in compatible interrupt mode

Interrupt type

The

Interrupt request

interru

generation

pt

source

Hardware interrupt, timer interrupt, or

HW5

Cause. IP7 & Status.

performance counter overflow interrupt

IM7

Hardware interrupt

HW4

Cause. IP6 & Status.

IM6

HW3

Cause the IP5 & Status.

IM5

HW2

Cause. IP4 & Status.

IM4

HW1

Cause the IP3 & Status.

IM3

HW0

Cause. IP2 & Status.

IM2

Software interrupt

SW1

Cause. IP1 & Status.

IM1

SW0

Cause. IP0 & Status.

IM0

The same exception entry offset is used for all interrupts, whether the general exception entry offset (0x180) or

the special exception entry offset (0x200) is cause.IV determined. See Table 6-3 on page 72 for details.

The interrupt exception handler queries cause.ip and status.im to determine the specific interrupt source. In

the case of multiple effective interrupt sources, the priority of interrupt processing can be realized by adjusting the

order of the query.

Mode two, vector interrupt mode

This mode specifies a unique exception entry vector for each interrupt based on a compatible interrupt mode

(see Table 6-3 on page 72 for calculation) and defines a fixed priority relationship for all interrupts, as shown in

Table 6-5.

Table 6-5 Priority relationship among interrupts in vector interrupt mode

priority

Interrupt

The

Interrupt request

Interrupt

type

interru

generation

vector

pt

number

source

Highest

Hardware

HW5

Cause. IP7 & Status. IM7

7

priority

interrupt

HW4

Cause. IP6 & Status. IM6

6

HW3

Cause the IP5 & Status.

5

IM5

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HW2

Cause. IP4 & Status. IM4

4

HW1

Cause the IP3 & Status.

3

IM3

HW0

Cause. IP2 & Status. IM2

2

Software

SW1

Cause. IP1 & Status. IM1

1

interrupt

Lowest

SW0

Cause. IP0 & Status. IM0

0

priority

In vector interrupt mode, which hardware interrupt source the timer interrupts to reuse is defined by the

INTCTL.IPTI domain, see Table 7-25 on page 109. In vector interrupt mode, which hardware interrupt source the

performance counter overflows the interrupt multiplexes is defined by the INTCTL.ippCI field, see the table on

page 109

7 to 25.

GS464E does not implement shadow registers, so all interrupts in vector interrupt mode correspond to the same set of

logical general purpose registers (GPR).

Which interrupt mode the processor currently adopts is determined by the status.bev, cause.IV, and INTctL.vs

domains. The corresponding relationship is shown in Table 6-6

Shown below.

Table 6-6 Interrupt mode determination

Status. BEV

Cause. IV

IntCtl. VS.

Interrup

t mode

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Status. BEV

Cause. IV

IntCtl.

Interrupt

VS.

mode

1

The x1

x

Compatible interrupt mode

x

0

x

Compatible interrupt mode

x

x

= 0

Compatible interrupt mode

0

1

! = 0

Vector interrupt mode

6.2.3 Additional notes on interrupt handling

This manual only describes the structure and response mechanism of the interrupt system of GS464E. When

designing the loongson 3A3000 chip interrupt system, the software staff should refer to chapter 6 and 7 of

"Loongson 3A3000/3B3000 Processor Household Manual -- Volume I" at the same time.

The processor is only responsible for direct sampling and recording the external input high level hardware

interrupt request. It is not responsible for level conversion, nor is it responsible for extending the pulse interrupt

signal to the level signal. This work is done by the interrupt controller in the chip. See chapters 6 and 7 of the

Loongson 3A30000/3B3000 Processor User Manual, Vol. 1.

Depending on the signal behavior of the external hardware interrupt input, the interrupt request bits internally

connected directly to the external interrupt input (root.cause.ip [7:2] or gueve.cause.ip [7:2]) may change from 1 to

0 after the interrupt request is triggered and before the interrupt handler queries these request bits. Interrupt

handlers need to be able to handle this situation. It is recommended to return directly without doing any processing.

If special treatment is done for system diagnosis, please do not affect the normal behavior of the system.

For hardware interrupts directly affected by external hardware, the software usually needs to clear the interrupt

state of a terminal device. From the command sequence issued by the processor to clear interrupts, to the device

receiving the command to clear its interrupt state, to the level of the processor's interrupt input pin changing from 1

to 0

The process (interrupt input undo) may have an indefinite delay. If interrupt enablement is turned on

prematurely, the same interrupt may be re-sampled, a phenomenon known as "spurious interrupt". Software needs

to be able to handle this situation correctly. It is recommended that the software, after issuing a write command to

clear the device's interrupt state, explicitly read the interrupt state tag of the device concerned until the read status

tag has been cleared, and then fully enable the device's interrupt within the processor or on the interrupt routing

path. 2 The Longson 3A3000 chip has guaranteed that the delay of each interrupt source signal passing through the

interrupt routing path to the interrupt input pin of the processor is always less than the delay of the interrupt state

returning to the processor through the data access path. If "false interrupt" is still found during debugging, please

ask the software personnel to further inquire the data manual and user manual of the device chip and bridge

involved in the system.

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7 Coprocessor register 0

7.1 Root coprocessor 0 register overview

The coprocessor 0 register in the root mode context of the GS464E processor core is called the "root coprocessor 0 register"

The stores are listed

in Table 7-1.

Table 7-1 List of coprocessor 0 registers

Reg.

Sel.

Register name

Function

The

definiti

inde

on

x

0

0

The Index

VTLB accesses the specified index register with FTLB

Page 85, section 7.2

1

0

The Random

VTLB with FTLB access to random index registers

Page 86, section 7.3

2

0

EntryLo0

VTLB and FTLB table entry low order content associated with even

Page 87, section 7.4

number of virtual pages

3

0

EntryLo1

VTLB and FTLB table entry low order content related to odd

Page 87, section 7.4

number of virtual pages

4

0

The Context

A pointer to an in-memory page table entry

Page 90, section 7.5

4

2

UserLocal

Store user information that allows user-mode software to read

Page 91, section 7.6

through RDHWR commands

5

0

PageMask

VTLB page table size control

Page 92, section 7.7

5

1

PageGrain

1KB small pages and other page table property control

Page 93, section 7.8

5

5

PWBase

Page table base address register

Page 94, section 7.9

5

6

PWField

Configure the page table address index location for each level

Page 95, section 7.10

5

7

PWSize

Configure the page table pointer size for each level

Page 96, section 7.11

6

0

Wired

Control the number of fixed items in VTLB

Page 97, section 7.12

6

6

PWCtl

Control multilevel page table configuration

Page 98, section 7.13

7

0

HWRENa

RDHWR instruction access register enable control

Page 99, section 7.14

8

0

BadVAddr

Record the error address for the latest address-related exception

Page 100, section

7.15

9

0

The Count

Processor clock counter

Page 101, section

7.16

9

6

GSEBase

Loongson extension exception entry base address register

Page 102, section

7.17

9

7

PGD

Page table pointer register

Page 103, section

7.18

10

0

EntryHi

VTLB and FTLB table entries high content

Page 104, section

7.19

11

0

The Compare

Timer interrupt control

Page 106, section

7.20

12

0

The Status

Processor status and control registers

Page 107, section

7.21

12

1

IntCtl

Interrupts system state and control registers

Page 109, section

7.22

12

2

SRSCtl

Shadow register status and control register

Page 110, section

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7.23

13

0

Cause

Store last exception reason

Page 111, section

7.24

14

0

The EPC

Store the PC on which the last exception instruction occurred

Page 113, section

7.25

15

0

PRId

The processor ID

Page 114, section

7.26

15

1

EBase

Exception entry base address register

Page 115, section

7.27

16

0

The Config

Configuration register

Page 116, section

7.28

16

1

Config1

Configure register 1

Page 117, section

7.29

16

2

Config2

Configure register 2

Page 118, section

7.30

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7.2 Index Register (CP0 Register 0, Select 0)

The Index register is a 32-bit read-write register in which the Index information is used for TLBP, TLBR,

TLBWI instruction access

TLB.

Figure 7-1 illustrates the format of the Index register; Table 7-2 describes the Index register fields.

Figure 7-1 Index register format

31

30

11

10

0

P

0

The

Index

Table 7-2 Description of Index register field

Domain

positio

Functional

Read

Reset

name

n

descriptio

/writ

value

n

e

TLB queries failed flags. When the TLBP instruction fails to find a match in TLB, the

P

31

R

0 x0

position is 1;

Otherwise set to 0.

0

30.. 11

Read only is always 0.

0

0

TLB accesses the index. The field is configured by the software to instruct subsequent

TLBR or TLBWI instructions to read or write the specified item of the TLB.

When the TLBP instruction executes, if a match is found, the index value of the match is

stored in the field; When no match is found, the contents of the Index field of the Index

The Index

10.. 0

R/W

0 x0

register can be any value.

The Index value of 0.. 63 The number 0.. used to indicate VTLB. A total of 63.

The Index value of 64..

1087 is used to indicate FTLB. Where ((index-64) div 128) is

used to indicate which path to visit FTLB, and which path to visit is determined by the

value of ((index-64) mod 128). For example, when the Index value is 798, it indicates

access to item ((798-64) mod 128 = 94 of the path to ((798-64) div 128 = 5).

Programming tips:

The reasonable value range of the Index field is 0 ~ 1087. When the value of the Index field is written beyond this range,

the processor result will be uncertain.

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7.3 Random Register (CP0 Register 1, Select 0)

The Random register is a read-only register that holds the index value of TLBWR instruction access to TLB.

The index value stored in the Random register changes every clock cycle. The upper bound (including) of the value

change is 63, and the lower bound (including) of the value change is the value set in the Wired register. The

Random register will automatically Reset to the upper bound when the Reset exception occurs and the Wired

register is written, i.e. 63.

When the value of the page size represented in the PageMask register is inconsistent with the page size

configured in the FTLB, the TLBWR instruction will operate only on THE VTLB, with the value in the current

Random register determining which entry is written to the VTLB.

The TLBWR instruction will operate only when the value of the page size represented in the PageMask

register is the same as the page size configured in FTLB

FTLB, which routing processor writes to FTLB is internally randomly determined, not using the contents of

the Random register. Figure 7-2 illustrates the format of the Random register; Table 7-3 describes each field of the

Random register.

Figure 7-2 Random register format

31

6

5

0

0

The

Random

Table 7-3 Description of Random register field

Domain

posit

Functional

Read

Reset

name

ion

descriptio

/writ

value

n

e

0

31.. 6

Read only is always 0.

0

0

The

5.. 0

The random index value written by VTLB.

R

0 x3f

Random

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7.4 EntryLo0 and EntryLo1 registers (CP0 Register 2 and 3, Select 0)

The EntryLo0 and EntryLo1 registers serve as interfaces for TLBP, TLBR, TLBWI, and TLBWR instructions

to access the TLB, where EntryLo0 is used

The EntryLo1 register holds information for odd pages.

The EntryLo0 and EntryLo1 registers present a different format when accessed using DMFC0/DMTC0 and

MFC0/MTC0 instructions.

Figure 7-3 illustrates the format of the EntryLo0 and EntryLo1 registers when accessed by DMFC0/DMTC0

instructions; Table 7-4 describes the register fields in this case.

Figure 7-3 Register formats for EntryLo0 and EntryLo1 when accessed by DMFC0/DMTC0

instructions

63

62

61

60

42

41

32

RI

XI

K.

0

PFNX

31

30

29

6

5

4

3

2

1

0

PFNX

PFN

C

D

V

G

Table 7-4 Description of the register fields of EntryLo0 and EntryLo1 for DMFC0/DMTC0

instruction access

Domain

positio

Functional

Read

Reset

name

n

descriptio

/writ

value

n

e

Read prevents identifying bits. When the RI position of a TLB table entry is 1, the

processor fires an exception when an access instruction attempts to read on the page.

RI

63

Depending on the PageGrain register IEC field, the triggered exception could be a TLBL

R/W

0 x0

invalid exception or a TLBRI exception.

The XI fields of EntryLo0 and EntryLo1 can only be written if PageGrain=1. RIE

PageGrain = 0 RIE

, the RI fields of EntryLo0 and EntryLo1 will be read to 0 regardless of the value to be

written.

Execution block identification bits. When the XI position of a TLB table entry is 1, the

occurrence on the page is indicated and the processor fires the exception. Depending

XI

62

on the PageGrain register IEC field, the triggered exception could be a TLBL invalid

R/W

0 x0

exception or a TLBXI exception.

The XI fields of EntryLo0 and EntryLo1 can only be written if PageGrain=1. XIE

PageGrain = 0 XIE

, the XI fields of EntryLo0 and EntryLo1 will be read to 0 regardless of the value to be

written.

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The kernel executes protection bits. If the processor is in kernel mentality, the processor will trigger

the TLB Invalid exception by pointing to the page K=0.

K.

61

R/W

0 x0

The K fields for EntryLo0 and EntryLo1 can only be written if gsconfig. KE=1.

GSConfig. KE = 0

, the K fields for EntryLo0 and EntryLo1 will be read to 0 regardless of the value to be

written.

0

60.. 42

Read only is always 0.

0

0

Physical page number extension. When the processor is configured to support the large physical

address space pattern (Config3=1 and PageGrain=1), the domain contents are splicedto the high

order of the PFN domain to form a complete physical page number, thus supporting the 48-bit

PFNX

41.. 30

R/W

0 x0

physical address space. LPAELPA The PFNX domain corresponds to the 47.. of the physical

address.

36.

If the processor is configured to not support the large physical address space pattern

(PageGrain=0), the PFNX field will ELPA1

Cannot write and reads return 0. Thus achieving compatibility with system software written based

on Release 1 of the MIPS specification.

1. The Config in the godson 3A1500 chip is always 1, so it is impossible to turn off the large physical address space mode support because of Config=0.

LPALPA

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Domain

positi

Functiona

Read

Reset

name

on

l

/wri

value

descripti

te

on

Basic section of physical page number. When the processor is configured to support the large

physical address space pattern (Config3=1 and PageGrain=1), the field contents are splicedinto the

PFN

29.. 6

lower part of the PFNX field to form a complete physical page number, thus supporting the 48-bit

R/W

0 x0

physical address space. LPAELPA The PFN domain corresponds to 35.. of the physical

address.

12.

When the processor is configured to not support a large physical address space pattern

(PageGrain=0), the PFN field itself ELPA

The final physical page number is formed to support the 36-bit physical address space.

The Cache property of the physical page. See this section for a detailed definition of the

C

5.. 3

R/W

0 x0

Cache property and its encoding

That's shown in table 7 minus 6.

Dirty bits. When the dirty position in the page table is 1, the page can be written;

D

2

R/W

0 x0

Otherwise for a dirty location it is 0

The TLB Mod exception will be triggered if the page of.

Significant bit. When the valid position in the page table is 1, it means that the page is

V

1

R/W

0 x0

accessible; Otherwise access a valid location

A page of 0 would trigger the TLB Invalid exception.

The global level. When a page table entry is filled into a TLB, the EntryLo0 and

EntryLo1 register's two G-bit values are logically matched, resulting in the global

G

0

identity bit for the page table entry. When the global identity bit in the page table is 1, asids are

R/W

0 x0

not compared in the TLB address match lookup.

When page table entries are read from TLB, both G bits of the EntryLo0 and EntryLo1

registers reflect both reads

G bit information for page table entries.

Figure 7-4 illustrates the format of the EntryLo0 and EntryLo1 registers when accessed by the MFC0/MTC0

instructions; Table 7-5 describes the register fields in this case. Note that the KE bit of the page table cannot be

accessed at this time. The KE bit of the TLB table entry will be written to the default value 0.

Figure 7-4 Register formats for EntryLo0 and EntryLo1 when accessed by MFC0/MTC0 instructions

63

32

SignExt

31

30

29

6

5

4

3

2

1

0

RI

XI

PFN

C

D

V

G

Table 7-5 Description of the register fields for EntryLo0 and EntryLo1 at MFC0/MTC0

instruction access

Domain

positi

Functiona

Read

Reset

name

on

l

/wri

value

descripti

te

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on

When MTC0 is used to write, the contents corresponding to this part in the register are

SignExt

63.. 32

R

0 x0

ignored and the PFNX field is written 0.

When MFC0 is read out, this part of the contents returned to the general purpose register

is extended by the RI bit symbol.

Read prevents identifying bits. When the RI position of a TLB table entry is 1, the

processor fires an exception when an access instruction attempts to read on the page.

RI

31

Depending on the PageGrain register IEC field, the triggered exception could be a TLBL

R/W

0 x0

invalid exception or a TLBRI exception.

The XI fields of EntryLo0 and EntryLo1 can only be written if PageGrain=1. RIE

PageGrain = 0 RIE

, the RI fields of EntryLo0 and EntryLo1 will be read to 0 regardless of the value to be

written.

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Domain

positio

Functional

Read

Reset

name

n

descriptio

/writ

value

n

e

Execution block identification bits. When the XI position of a TLB table entry is 1, the

occurrence on the page is indicated and the processor fires the exception. Depending

XI

30

on the PageGrain register IEC field, the triggered exception could be a TLBL invalid

R/W

0 x0

exception or a TLBXI exception.

The XI fields of EntryLo0 and EntryLo1 can only be written if PageGrain=1. XIE

PageGrain = 0 XIE

, the XI fields of EntryLo0 and EntryLo1 will be read to 0 regardless of the value to be

written.

Basic section of physical page number. When the processor is configured to support the large

physical address space pattern (Config3=1 and PageGrain=1), the field contents are splicedinto the

PFN

29.. 6

lower part of the PFNX field to form a complete physical page number, thus supporting the 48-bit

R/W

0 x0

physical address space. LPAELPA The PFN domain corresponds to 35.. of the physical

address.

12.

When the processor is configured to not support a large physical address space pattern

(PageGrain=0), the PFN field itself ELPA

The final physical page number is formed to support the 36-bit physical address space.

The Cache property of the physical page. See this section for a detailed definition of the

C

5.. 3

R/W

0 x0

Cache property and its encoding

That's shown in table 7 minus 6.

Dirty bits. When the dirty position in the page table is 1, the page can be written;

D

2

R/W

0 x0

Otherwise for a dirty location it is 0

The TLB Mod exception will be triggered if the page of.

Significant bit. When the valid position in the page table is 1, it means that the page is

V

1

R/W

0 x0

accessible; Otherwise access a valid location

A page of 0 would trigger the TLB Invalid exception.

The global level. When a page table entry is filled into a TLB, the EntryLo0 and

EntryLo1 register's two G-bit values are logically matched, resulting in the global

G

0

identity bit for the page table entry. When the global identity bit in the page table is 1, asids are

R/W

0 x0

not compared in the TLB address match lookup.

When page table entries are read from TLB, both G bits of the EntryLo0 and EntryLo1

registers reflect both reads

G bit information for page table entries.

Programming tips:

Before any field contents of the PageGrain register are modified, the PFNX and PFN fields in the EntryLo0 and EntryLo1

registers must be written to 0, and all TLBS must be cleared. All the above operations must be done in the

Unmapped Address Space. If you do not follow the instructions here, the processor behavior

is uncertain.

Table 7-6 Cache attribute encoding table

Page table C

Cache

domain

attribute ¹

encoding

0

Reserve, forced configuration will cause a crash

1

Reserve, forced configuration will cause a crash

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2

Uncached

3

Cached

4

Reserve, forcing the configuration is equivalent to Cached

5

Reserve, forcing the configuration is equivalent to Cached

6

Reserved, forced configuration will access the EJTAG Dseg

space, there is a risk of crash

7

Uncached Accelerated

1 For definitions of the Uncached, Cacheable, and Uncached Accelerated properties, see section 5.2 on page 60.

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7.5 Context Register (CP0 Register 4, Select 0)

The Context register is a read-write register that contains some page-table base address high level information

filled in by the operating system software and some bits of the error virtual address with the TLB exception.

According to the original design intent of the MIPS architecture, the information splited together in the Context

register can form a pointer to an item in the page table, which can be accessed when a TLB exception occurs. The

page table that can be accessed without any processing of the contents in the Context register is a single-level page

table structure. The page size is 4K bytes, and each page table item is 16 bytes. It contains an even page table item

and an odd page table item with consecutive virtual address, totaling 512K odd and even page table items. When

the page table does not adopt this structure, the software needs to properly shift and concatenate the contents of the

Context register. For an operating system with multilevel page tables, the Context register can only be used to

speed up address generation for the last level of page table access.

The Context register is primarily used in the TLB Refill exception handler. But when exceptions such as

XTLB Refill, TLB Invalid, and TLB Mod occur, the BadVPN2 domain in the Context register is also updated, so

the software can also use the Context register in the corresponding exception handler.

The BadVPN2 domain in the Context register copies some of the information in the BadVAddr register, but

this does not mean that this part is completely equivalent. When the Address Error exception occurs, the BadVaddr

register is updated by the hardware, but the BadVPN2 domain of the Context register is not updated by the

hardware.

Figure 7-5 illustrates the format of the Context register; Table 7-7 describes the fields of the Context register.

Figure 7-5 Context register format

63

32

PTEBase

31

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PTEBase

BadVPN2

0

Table 7-7 Description of the Context register fields

Domain

positio

Functional

Read

Reset

name

n

descriptio

/writ

value

n

e

PTEBase

63.. 23

Page table base address high level. Configured by the operating system software according R/W

There is no

to the current page table.

BadVPN2

22.. 4

When a TLB exception occurs, store the error virtual address of 31.. 13.

R

There is no

0

3.. 0

Read only is always 0.

0

0

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7.6 UserLocal Register (CP0 Register 4, Selelct 2)

The UserLocal register is a read-write register that is not used to control the processor's hardware and is not

changed by the hardware.

The contents of the UserLocal can be read in user mode via the RDHWR instruction, and whether it can be

read is controlled by the HWRENCH a register bit 29. Figure 7-6 illustrates the format of the UserLocal register;

Table 7-8 describes the UserLocal register fields.

Figure 7-6 UserLocal register format

63

0

UserInformation

Table 7-8 Description of UserLocal register fields

Domain

positi

Functiona

Read

Reset

name

on

l

/wri

value

descripti

te

on

UserInfor

63.. 0

The information stored is not affected by or affected by the processor

R/W

There is

- mation

hardware.

no

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7.7 PageMask Register (CP0 Register 5, Select 0)

The PageMask register is a read-write register, used in the process of reading and writing TLB; It contains a

comparison mask for each TLB

Table entries set different page sizes.

Figure 7-7 illustrates the format of the PageMask register; The PageMask register fields are described in

Table 7-9.

Figure 7-7 PageMask register format

6332

0

31

30

13

12

11

10

0

0

Mask

MaskX

0

Table 7-9 PageMask register field description

Domain

positio

Functional

Read

Reset

name

n

descriptio

/writ

value

n

e

0

63.. 31

Read only is always 0.

0

0

When translating between real and virtual addresses, each bit in the Mask field [17:0] is

Mask

30.. 13

used to indicate whether the corresponding bit in the virtual address [30:13] bit is

R/W

0 x3

compared. 1: No comparison; 0: Compare.

See Table 7-10 below for the Mask codes supported by longson and their corresponding

page sizes.

MaskX

12.. 11

Constant 3, 1KB pages are not supported.

R

0 x3

0

10.. 0

Read only is always 0.

0

0

Table 7-10 shows the Mask domain codes supported by GS464E and their corresponding page sizes.

Table 7-10 Mask domain codes and page sizes

Mask encoding

Page size

0 x0

4 KB

0 x3

16 KB

0 xf

64 KB

0 x3f

256 KB

0 XFF

1 MB

0 x3ff

4 MB

0 XFFF

16

MB

0 x3fff

64

MB

0 XFFFF

256 MB

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7.8 PageGrain Register (CP0 Register 5, Select 1)

The PageGrain register is a read-write register. The GS464E implements only the parts of it that are related to

the TLB XI/RI protection bit and large physical address pattern control.

Figure 7-8 illustrates the format of the PageGrain register; The fields of the PageGrain register are described

in Table 7-11.

Figure 7-8 PageGrain register format

31

30

29

28

27

26

0

RIE

XIEELPA

IEC

0

Table 7-11 Description of PageGrain register field

Domain

positio

Functional

Read

Reset

name

n

descriptio

/writ

value

n

e

When I made a detour to the TLB wedge, I stopped in to make a functional detour.

RIE

31

0: Turn off the function. The RI bits of the EntryLo0 and EntryLo1 registers will disable

R/W

0 x0

writing and force them to be 0;

1: Enable this function. RI bits of the EntryLo0 and EntryLo1 registers work fine.

When I stopped in to the TLB short wedge function, I made a short detour.

XIE

30

0: Turn off the function. The XI bits of the EntryLo0 and EntryLo1 registers are disabled

R/W

0 x0

and forced to be 0;

1: Enable this function. The XI bits of the EntryLo0 and EntryLo1 registers work fine.

Large physical address function enablement bit.

ELPA

29

0: Turn off the function. The PFNX fields of the EntryLo0 and EntryLo1 registers disable

R/W

0 x0

writing and force 0;

1: Enable this function. The PFNX fields for the EntryLo0 and EntryLo1 registers work

fine.

0

28

Read only is always 0.

0

0

TLB reads block and performs block exception encoding and entry control bits.

0: TLB read block and execute block exception encoding and entrance multiplexing TLBL

IEC

27

R/W

0 x0

exception encoding and entrance;

1: TLB read block exception USES TLBRI exception encoding and entry, TLB performs

block exception USES TLBXI exception encoding and entry.

0

26.. 0

Read only is always 0.

0

0

Programming tips:

Before the software attempts to modify PageGrain any fields, all TLBS must be cleared and the fields of the

COP0 register listed below must be set to the specified value, otherwise the behavior of the processor will be

uncertain.

COP0 register field

Specif

y a

value

94

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7.9 PWBase Register (CP0 Register 5, Select 5)

The PWBase register is a 64-bit read-write register that holds the virtual address of the page table base address.

This register is used in conjunction with the PWField, PWSize, and PWCtl registers and is used in GS464E to

provide configuration information for the execution of the LDDIR and LDPTE directives. The LDDIR and LDPTE

directives support traversal lookup of multilevel page table structure, which can contain up to four levels of catalog

tables and one level of page table entries. The supported page table structure is shown in Figure 7-9.

Figure 7-9 Page table access procedures supported by PWBase,PWField,PWSize and PWCtl

PWSizePWSize BDW GDW

PWSizePWSizePWSize UDW MDW

PTW

Address

Bindex

Uindex

Mindex

PTindex

to look up

Gindex

BadVAddr

PWField BDI

PWField

PWFieldPWFieldPWField UDI MDI

PTI

GDI

PWBase

EntryLo0

Base address directory table

>>

EntryLo1

Global table of contents

32 b

32 b

/ 64

/ 64

32

b

Upper

b?

b?

or

PWField

64 b?

32

table of

b

PTEI

Intermedia

Or

contents

64 b?

te

directory

table

PWSize PTE

Page table table

PWSize PS

Figure 7-10 illustrates the format of the PWBase register; Table 7-12 describes the PWBase

register fields.

Figure 7-10. PWBase register format

63

0

PWBase

Table 7-12 Description of the PWBase register fields

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7.10 PWField Register (CP0 Register 5, Select 6)

The PWField register is used in conjunction with the PWBase, PWSize, and PWCtl registers in GS464E to

provide configuration information for the execution of the LDDIR and LDPTE directives. The LDDIR and LDPTE

directives support traversal lookup of multilevel page table structure, which can contain up to four levels of catalog

tables and one level of page table entries. See Figure 7-9 on page 94 for the supported page table structure and

access procedure. The index value of each level page table to the next level page table or the final page table entry

is obtained by intercepting part of the contiguous bit from the virtual address to be looked up (BadVAddr). The

PWField register is used to identify the starting point of the page table index truncated in the pending virtual

address (BadVAddr).

Figure 7-11 illustrates the format of the PWField register; Table 7-13 describes the PWField

register fields.

Figure 7-11. PWField register format

63

38

37

32

0

BDI

31

30

29

24

23

18

17

12

11

6

5

0

0

GDI

UDI

MDI

PTI

PTEI

Table 7-13 Description of PWField register fields

Domain

positio

Functional

Read

Reset

name

n

descriptio

/writ

value

n

e

0

63.. 38

Read only is always 0.

0

0

The Base Directory starts the index.

BDI

37.. 32

The use of the base directory table is controlled by the PWCtl. PWDirExt The base directory

R/W

0 x0

table can be used to distinguish between different page tables, such as the user page table and the kernel

page table, which can be maintained separately.

0

31.. 30

Read only is always 0.

0

0

GDI

29.. 24

Global Directory index starting position.

R/W

0 x0

UDI

23.. 18

The Upper Directory starts the index.

R/W

0 x0

MDI

17.. 12

MIddle Directory is the starting point of an index.

R/W

0 x0

PTI

11.. 6

Page Table index starting position.

R/W

0 x0

Page table item shift amount.

The content of the page table entry read out will be logically shifted to the right pTEI-2 bit

PTEI

5.. 0

to remove the information in the page table entry that is only used for software and does

R/W

0 x0

not need to be put into TLB. The loop is then rotated 2 bits to the right to move the RI and

XI two-bit information to either the highest two bits of EntryLo0 or EntryLo1. Therefore,

98

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7.11 PWSize Register 5, Select 6

The PWSize registers are used in conjunction with the PWBase, PWField, and PWCtl registers and are used in

GS464E to provide configuration information for the execution of the LDDIR and LDPTE directives. The LDDIR

and LDPTE directives support traversal lookup of multilevel page table structure, which can contain up to four

levels of catalog tables and one level of page table entries. See Figure 7-9 on page 94 for the supported page table

structure and access procedure. The index value of each level page table to the next level page table or the final

page table entry is obtained by intercepting part of the contiguous bit from the virtual address to be looked up

(BadVAddr). The PWSize register is used to identify the number of contiguous bits intercepted by the page table

index at each level in the virtual address to be looked up (BadVAddr).

The PWSize field is used to control whether the bit width of the pointer in the directory table is 32 or 64 bits.

PS The index value taken from the virtual address to be looked up (BadVAddr) by the various table of contents

according to PWField and PWSize needs to be multiplied by the width of the pointer in the table of contents

(moved 2 bits left or moved 3 bits left) to form a true access address. Only 64-bit Pointers can be used in the

XTLB Refill exception and 32-bit or 64-bit Pointers can be used in the TLB Refill exception.

Figure 7-12 illustrates the format of the PWField register; Table 7-13 describes the PWField

register fields.

Figure 7-12. PWSize register format

63

38

37

32

0

BDW

31

30

29

24

23

18

17

12

11

6

5

0

0

PS

GDW

UDW

MDW

PTW

PTEW

Table 7-14 Description of the PWSize register fields

Domain

positio

Functional

Read

Reset

name

n

descriptio

/writ

value

n

e

0

63.. 38

Read only is always 0.

0

0

BDW

37.. 32

Base directory table index bit width. A value of 0 means that the base address directory

R/W

0 x0

table does not need to be looked up.

0

31

Read only is always 0.

0

0

PS

30

Level directory table pointer bit width. 0:32 pointer; 1:64 pointer.

R/W

0 x0

GDW

29.. 24

Global directory table index bit width. 0 is meaningless and the processor result is

R/W

0 x0

uncertain when configured as 0.

UDW

23.. 18

Upper directory table index bit width. 0 is meaningless and the processor result is

R/W

0 x0

uncertain when configured as 0.

MDW

17.. 12

Intermediate directory table index bit width. 0 is meaningless and the processor result is

R/W

0 x0

100

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