Loongson 1C300 Processor User Manual (Version 1.0, 2014) - page 6
When the bit of GOTGCTL.VbalidOvEn is
set, the bit of VbalidOvVal is used reset
vbus valid signal.
Ɣ1’b0: When GOTGCTL.VbalidOvEn = 1,
the value of vbus valid signal is 0;
Ɣ1’b1: When GOTGCTL. VbalidOvEn = 1,
the value of vbus valid signal is 1;
2
VBUS Valid reset enable (AvalidOvEn)
Host only
1'b0
R_W
This bit is used to enable the software to
override
Bvalid
signal
by
GOTGCTL.BbValidOvVal bit.
Ɣ1'b1: The vbus valid signal received
from PHY is reset by VbvalidOvVal.
Ɣ1'b0: vbus valid signal reset function is
disabled, and the value of vbus valid signal
used by OTG controller, namely, the value
received from PHY
1
Session Request (SesReq)
Device only
1'b0
R_W
The software sends a session request
through setting the SesReq Bit in USB bus.
When the bit of Host Negotiation Success
Status Change in OTG interrupt controller
is set, the software is cleared by writing 0
to
the
bit.
When the bit of
HstNegSucStsChng is 0, OTG controller
clears the bit.
Ɣ1'b0: No session request
Ɣ1'b1: Session request
0
Session Request (SesReq)
Device only
1'b0
R_W
Ɣ1'b0: Session request failure
Ɣ1'b1: Session request success
Interrupt register (GOTGINT)
Offset address: 004h
Field
Note
Operating mode
Reset
Access
value
characteristics
31:20
Reserved field
Host; Device
RO
19
Debounce Done (DbnceDone )
Host only
1'b0
R_SS_W
After the debounce in device connection is
C
finished, OTG controller asserts the bit.
After the application notices this interrupt,
USB reset operation starts.
18
A
device
timeout
changeHost; Device
1'b0
R_SS_W
(ADevTOUTChg)
C
When A device waits for B device
connection overtime, OTG controller
asserts the bit
17
detects the Host Negotiation (HstNegDet):
Host; Device
1'b0
R_SS_W
After the Host Negotiation Request is
C
found in bus, OTG controller asserts this
bit.
16:10
Reserved domain
Host and Device
RO
9
HstNegSucStsChng: Host NegotiationHost and Device
1'b0
R_SS_W C
Successful Status Change. When the host
negotiation request in bus succeeds or fails,
-98-
OTG controller will assert this bit. The
software can determine whether the host
negotiation
succeeds by searching
GOTGCTL.HstNegSus.
8
Session request successful status changeHost and Device
1'b0
R_SS_W C
(SesReqSusStsChng) Session Request
Success Status Change
When the session request in USB bus
succeeds or fails, OTG controller asserts
this bit. The software can determine
whether the session request succeeds by
searching GOTGCTL.SesReqScs.
7:3
Reserved domain
Host and Device
1'b0
RO
2
Session end detect (SesEndDet):
Device
1'b0
R_SS_W C
Session End Detected
When utmisrp_bvalid signal is pulled
down, OTG controller asserts this bit.
1:0
Reserved domain
Host and Device
RO
AHB configuration register (GAHBCFG)
Offset address: 008h
This register is used to configure OTG controller in case of power on or change in operating mode, the configured
contents mainly include system parameters related to AHB. After the initial configuration, the value of this register
can’t be modified. No matter the transaction is initiated in AHB bus or USB bus, this register needs reconfiguring.
Field
Note
Operating mode
Reset
Access
value
characteristics
31:23
Reserved domain
Host; Device
RO
22
Notify All DMA Write Transactions
Host; Device
1'b0
R_W
(NotiAllDmaWrit): NotifyAllDma Write
Transactions
It’s used to enable DMA Done function of
all
DMA write transactions
(to
endpoint/Channel). Only when the bit of
GAHBCFG.RemMemSupp is 1'b1, this bit
is significant.
Ɣ1'b1: For all DMA write transactions,
OTG controller must assert dma_req,
int_dma_done, chep_last_transact and
chep_number signals in AHB bus. In order
to
finish
certain
channel/endpoint
transmission, OTG controller needs to wait
for the sys_dma_done signal of all write
transactions.
Ɣ1'b0: only for the last transaction in write
transaction, will OTG controller assert
int_dma_done signal. Similarly, in order to
finish
certain
channel/endpoint
transmission, OTG controller needs to wait
for the sys_dma_done signal of that DMA
write transactions.
21
RemoteMemorySupport
Host and Device
1'b0
R_W
(RemMemSupp)
Enable the DMA write transfer wait system
DMA DONE signal function
Ɣ1'b1: When OTG DMA starts the
-99-
transfer towards the external memory
space, the output signal int_dma_req is
asserted. When this transfer is finished,
OTG controller asserts int_dma_done
signal to indicate that the DMA write from
OTG controller is finished. Then, OTG
controller waits for the sys_dma_done
signal from system, so as to complete
certain channel/endpoint data transfer.
Ɣ It’s unnecessary to assert int_dma_req
and int_dma_done signals; once DMA
write transfer is finished, XferComp
interrupts and OTG controller continues
operating. It’s unnecessary to wait for
sys_dma_done signal to finish data transfer.
8
PTxFIFOEmpLvl:
Host only
1'b0
R_W
periodic TxFIFO Empty Level indicates
that the when the periodic TxFIFO empty
interrupt bit
(GINTSTS.PTxFEMp) is
asserted. The bit is only used in slave mode.
Ɣ1’b0: GINTSTS.PTxFEMp interrupt bit
indicates when the periodic TxFIFO is half
empty;
Ɣ1'b1: GINTSTS.PTxFEMp interrupt bit
indicates that the periodic TxFIFO is fully
empty
7
NPTxFIFOEmpLvl:
Host and device
1'b0
R_W
Non-periodic TxFIFO Empty Level is used
in slave mode.
It indicates when the TxFIFO empty
interrupt bit of IN endpoint is asserted.
Host mode:
Ɣ1'b0: GINTSTS.PTxFEMp interrupt bit
indicates the non-periodic TxFIFO half
empty;
Ɣ1'b1: GINTSTS.PTxFEMp interrupt bit
indicates the non-periodic TxFIFO fully
empty;
Device mode:
Ɣ1’b0: DIEPINTn.TxFEmp interrupt bit
indicates the TxFIFO half empty of IN
endpoint;
Ɣ1'b1: DIEPINTn.TxFEmp interrupt bit
indicates the TxFIFO fully empty of IN
endpoint;
6
Reserved domain
Host; Device
RO
5
DMA enable (DMAEn)
Host; Device
1'b0
R_W
Ɣ1'b0: OTG working in Slave mode
Ɣ1'b1: OTG working in DMA mode
4:1
Burst length (HBstLen)
Host; Device
4'b0
R_W
Burst type of AHB Master
Ɣ4'b0000: Single
Ɣ4'b0001: INCR
Ɣ4'b0000: INCR4
Ɣ4'b0000: INCR8
Ɣ4'b0000: INCR16
Others: Reserved
-100-
0
Global interrupt mask (GlblIntrMsk)
Host; Device
1'b0
R_W
For software interrupt mask No matter
whether the bit is asserted, OTG controller
always updates the interrupt status register.
Ɣ1'b0: Interruption is invisible to
software
Ɣ1'b0: Interruption is visible to software
USB configuration register (GUSBCFG)
Offset address: 00Ch
This register is used to configure OTG controller in case of power on or change in operating mode, the configured
contents mainly include parameters related to USB and USB-PHY. No matter the transaction is initiated in AHB
bus or USB bus, this register needs reconfiguring. After the initial configuration, the value of this register can’t be
modified.
Field
Note
Operating
Reset
Access
mode
value
characteristic
s
31
Corrupt Tx package ()
Host; Device
1'b0
WO
Only for debugging, not writable 1
30
Force device register (ForceDevMod)
Host; Device
1'b0
R_W
Writing
1 indicates that the OTG controller
operates in device mode, regardless the value of
utmiotg_iddig input pin.
Ɣ1'b0: Normal operating mode
Ɣ1'b1: Enforcement device mode
After 1 is written to this bit, the software must wait
for the effective time of at least
25ms. In the
simulation environment in scale down mode, 500us
is enough.
29
If the Force Host Mode (ForceHostMod) writes 1,Host; Device
1'b0
R_W
it indicates that the OTG controller will work in
Host mode, regardless the value of utmiotg_iddig
input pin.
Ɣ1'b0: Normal operating mode
Ɣ1'b1: Enforcement host mode
After 1 is written to this bit, the software must wait
for the effective time of at least
25ms. In the
simulation environment in scale down mode, 500us
is enough.
28
Tx End Delay (TxEndDelay)
Device only
1'b0
R_W
Write 1, and enable TxEndDelay timer
Ɣ1'b0: Normal mode
Ɣ1'b1: Introduce Tx end delay timer
27: 23
Reserved
Host; Device
RO
22
TermSelDLinePulsing select
Device
1'b0
R_W
(TermSelDLPulse)
It’s used in SRP process to select utmi_termselect
data line pulse.
Ɣ1'b0: It uses utmi_txvalid data line pulse
(default)
Ɣ1'b1: It uses utmi_termselect data line pulse
21: 16
Reserved
Host; Device
RO
15
PHY low power clock select (PhyLpwClkSel)
Host; Device
1'b0
R_W
Choose to use 480MHz or 48Mhz (low power)
PHY mode. In FS and LS modes, PHY always
operate at 48MHz to save power.
-101-
Ɣ1'b0: 480MHz internal PLL clock
Ɣ1'b1: 48MHz external clock
14
Reserved bit
Host; Device
RO
13:10
USB cycle time (USBTrdTime): USB
Device
4'h5
R_W
Turnaround Time
Sets the cycle time of PHY clock bit unit
It specifies MAC request PFC
(data FIFO
controller) to clear the response time of obtaining
data in data FIFO. Its value must be set as follows:
Ɣ4'h5: When MAC interface is the 16bit UTM+
Ɣ4'h6: When MAC interface is the 16bit UTM+
9
HNP-Capable(HNPCap)
Host, Device
1'b0
R_W
The software uses this to control the HNP function
of OTG controller.
Ɣ1’b0: Unavailable HNP function
Ɣ1'b0: Available HNP function
Note: if the HNP function is disabled by software,
the corresponding OTG signal of PHY domain
must be fixed as the decided value (?)
8
SRP-Capable(SRPCap)
Host; Device
1'b0
R_W
The software uses this to control the SRP function
of OTG controller.
Ɣ1'b0: Unavailable SRP function
Ɣ1'b0: Available SRP function
Note: if the SRP function is disabled by software,
the corresponding OTG signal of PHY domain
must be fixed as the decided value
7: 4
Reserved bit
Host; Device
RO
3
PHY interface (PHYIf)
Host; Device
Configura
RO
It’s used to configure the interface of UTMI+PHY.
ble
Ɣ1'b0: 8bits
Ɣ1'b1: 16bits
If ULPI interface is selected, only 8bits can be set.
2:0
HS timeout calibration (TOutCal): HS Timeout
Host; Device
3'h0
R_W
The calibration unit is a PHY clock. It’s used to
correct the timeout between packets caused by
PHY. Different PHY introducing different delay.
For HS, the time-out value of USB standard is 736
-816 bit times; the software must set this domain
based on enumerating speed. The bits time of each
PHY clock is explained as follows:
HS:
Ɣ One 30MHz PHY clock = 16bit times
Ɣ One 60MHz PHY clock = 16bit times
Reset register (GRSTCTL)
Offset address: 010h
Field
Note
Operating
Reset value
Access
mode
characteristics
31
.AHB Master Idle(AHBIdle)
Host;
1'b1
RO
It indicates that AHB Master state machine is inDevice
IDLE state.
30
DMA request signal (DMAReq)
Host;
1'b0
RO
It indicates that there is a DMA request in bus;
Device
29:11
Reserved domain
Host;
RO
-102-
Device
10:6
TxFIFO number (TxFNum)
Host;
5'h0
R_W
Debugging use indication must use the FIFODevice
signal cleared by TxFIFO Flus. Only after
TxFIFO bit is cleared by controller, can
TxFNum be changed.
Ɣ5'h0:
-Clear non-periodic TxFIFO in -host mode
-Clear TxFIFO 0 in -device mode
Ɣ5'h1:
-Clear periodic TxFIFO in host mode
-Clear TxFIFO 0 in -device mode
Ɣ5'h2:
-Clear TxFIFO 0 in -device mode
Ɣ5'h3:
-Clear TxFIFO 0 in -device mode
…
Ɣ5'H10:
Clear all TxFIFOs (no matter in host mode or
device mode)
5
TxFIFO clear (TxFFlsh)
Host;
1'b0
R_WS_S
Is used to select and clear one or all TxFIFOs.Device
C
But this operation can’t be performed when the
transaction is under progress. Only when the
software confirms that OTG controller doesn’t
read or write TxFIFO, can this bit be written.
Acknowledged method is as follows:
Read -NAK valid interrupt can make sure OTG
controller doesn’t read FIFO;
Write
-GRSTCTL.AHBIdle can make sure
OTG controller doesn’t write FIFO
FIFO clear operations can be used in the
following circumstances. For example, FIFO
needs to reset or convert in share FIFO mode
and dedicated FIFO mode, and disables certain
device endpoint.
Only after the software must wait for OTG
controller to clear this bit, can other operations
be continued. It may take 8 hours, and use the
slower clock between phy_clk and hclk.
4
RxFIFO flash (RxFFlsh)
Host;
1'b0
R_WS_S
It’s used to clear the entire RxFIFO, and thisDevice
C
operation can’t be conducted in case of
transaction under progress.
Only when the software confirms that OTG
controller doesn’t read or write RxFIFO, can
this bit be written.
Only after the software must wait for OTG
controller to clear this bit, can other operations
be continued. It may take 8 hours, and use the
slower clock between phy_clk and hclk.
3
Reserved bit
Host;
RO
Device
2
Host Frame Counter Reset (FrmCntrRst)
Host
1'b0
R_WS_S
The software resets the frame number in OTG
C
-103-
controller by this bit.
Once the frame number is reset, the frame
number of SOF sent by next OTG controller is
0.
1
Reserved domain
Host;
RO
Device
0
OTG controller soft restart
Host;
1'b0
R_WS_S
The contents of resetting hclk and phy_clockDevice
C
clock domains are as follows:
Ɣ Clear all interrupts and CSR registers except
the following
-PCGCCTL.RstPdwn
-PCGCCTL.GateHclk
-PCGCCTL.PwrClmp
-GUSBCFG.DDRSel
-GUSBCFG.PHYSel
-GUSBCFG.FSIntf
-GUSBCFG.ULPI_UTMI_Sel
-GUSBCFG.PHYIf
-HCFG>FSLSPclkSel
-DCFG.DevSpd
-GGPIO
-GPWRDN
-GADPCTL
Ɣ Status machines of all modules (except AHB
Slave unit) are set to IDLE status; clear all
TxFIFOs and RxFIFOs
Ɣ After completing the data of the last AHB
transfer, all AHB Master transactions are ended
at once. An immediate end to all USB
transaction
¡ñ PMU module
(power management unit)
won’t be reset, and the software can soft reset
OTG controller in any time. This bit is self
cleared, namely, the controller will self clear
after all necessary logics are reset. Based on
different states of controllers, this will spend
several hours. Once this bit is cleared, only
after waiting for three PHY clocks, can PHY
domain operate
(sync delay). Before the
software starts any action, the AHBIdle bit
must be maintained at 1.
Interrupt register (GITTSTS)
Offset address: 014h
Field
Note
Operating
Reset
Access
mode
value
characteristics
31
System recovery / remote wake-up interrupt
Host; Device
1'b0
R_SS_W
(WkUpInt):Resume/Remote Wakeup
C
Detected Interrupt
The wakeup interrupt in suspended (L2) state.
Ɣ Device mode: only when the wakeup operation
started by Host is found in USB bus, can this
interrupt generate.
Ɣ Host mode: only when the wakeup operation started
-104-
by device is found in USB bus, can this interrupt
generate.
30
SessionRequest/New Session Detected Interrupt
Host;
1'b0
R_SS_W
Ɣ In Host mode, when the session request fromDevice
C
device is found, the bit is set to 1.
ƔIn device mode, when the utmisrp_bvalid signal is
pulled high, the bit is set to 1.
29
Disconnect interrupt (DisconnInt)
Host
1'b0
R_SS_W
When the device is disconnected, the bit is set to 1.
C
28
Connector ID Status Change (ConIDStsChng)
Host; Device
1'b1
R_SS_W
When the connector ID status changes, the bit is set
C
1.
27
Reserved bit
Host; Device
RO
26
Periodic TxFIFO (PTxFEmp)
Host
1'b1
RO
When the periodic TxFIFO is half empty or full
empty, and there is at least one request in cycle
request queue, this bit is set 1, and whether it’s set
to
1 in half empty or full empty is decided by
GAHBCFG.PTxFEmpLvl.
25
Host Channels Interrupt (HChInt)
Host
1'b0
RO
In Host mode, when there is a pending interrupt in
some channel of OTG controller, it’s set 1. The
software must read HAINT register to determine
the unprocessed interrupt channel number, and then
read the corresponding HCINTn register to
determine reasons for the interrupt. In order to clear
this bit, the software must clear the corresponding
status bit in HCINTn register.
24
Host port interrupt (PrtInt)
Host
1'b0
RO
In Host mode, if some port status of OTG controller
changes, it’s set to 1. The software must read HPRT
register to determine the real reason for the
interrupt. In order to clear this bit, the software
must clear the corresponding status bit in HPRT
register.
23
ResetDet: Reset Detected Interrupt
Device
1'b0
R_SS_W
In device mode, when the OTG controller in
C
suspended state sends the next reset operation, the
bit is set to 1.
Only when the OTG controller is in device mode,
and works in partial Power-down, or gating
suspended status, can it is valid.
When the OTG controller operates in Hibernation
suspended state, the bit is significant.
22
FetSusp: Data Fetch Suspended
Device
1'b0
R_SS_W
Valid only in DMA mode. When TxFIFO or request
C
queue has no space, OTG will stop and obtain data
for IN endpoint, and the bit is set to
1. In the
endpoint mismatching algorithm, the software uses
this interrupt
21
Incomplete periodic transfer (incomplIP)
Host
1'b0
R_SS_W C
In Host mode, when one incomplete periodic
transaction is still waiting processing within the
current frame time, the bit is set 1. In device mode,
the incomplete real-time OUT transmission, ifDevice
within the current frame time, there is at least one
incomplete transmission in a real-time OUT
-105-
endpoint, the bit is set to 1. And EOPF bit
20
Incomplete
real-time
IN
transmissionDevice
1'b0
R_SS_W
(incomplSOIN)
C
If within the current frame time, there is at least one
incomplete transmission in a real-time IN endpoint,
the bit is set to 1. And EOPE bit
19
OUT endpoint interrupt (OEPInt)
Device
1'b0
RO
When there is one pending interrupt in OUT
endpoint, the bit of OTG controller is set to 1. The
software must read DAINT register to determine
which endpoint has the pending interrupt, and then
read DOEPINTn register to determine the causes of
this interrupt. In order to clear this bit, the software
must clear the corresponding status bit in
DOEPINTn register.
18
IN endpoint (IEPInt)
Device
1'b0
RO
When there is one pending interrupt in IN endpoint,
the bit of OTG controller is set to 1. The software
must read DAINT register to determine which
endpoint has the pending interrupt, and then read
DOEPINTn register to determine the causes of this
interrupt. In order to clear this bit, the software
must clear the corresponding status bit in
DOEPINTn register.
17
Reserved bit
Host; Device
RO
16
Reserved bit
Host; Device
RO
15
Periodic frame end (EOPF)
Device
1'b0
R_SS_W
When within the current frame time, the threshold
C
pointed by DCFG.PerFrInt is reached, the bit is set
1.
14
Real-time OUT packet drop (ISOOutDrop)
Device
1'b0
R_SS_W C
If RxFIFO doesn’t have enough space for real-time
OUT endpoint to store the maximum package size
packet, the OTG controller can’t write one real-time
OUT packet to FxFIFO. In case of such
circumstance, the bit is set to 1.
13
EnumDone : Enumeration done
Device
1'b0
R_SS_W
When the speed enumeration ends, the bit is set 1.
C
The software reads DSTS register, and obtains the
specific enumeration speed.
12
USB reset (USBRst)
Device
1'b0
R_SS_W
When there is one reset operation in USB bus, the
C
bit is set to 1.
11
USB suspend (USBSusp)
Device
1'b0
R_SS_W
When the OTG controller detects one suspended
C
operation in USB bus, the bit is set. If within a
longer time, there is no activity in utmi_linestate
signal line, OTG controller enters into the
suspended state.
10
Early Suspend(ErlySusp)
Device
1'b0
R_SS_W
When the USB is detected to enter into idle state for
C
over 3ms, the OTG controller sets the bit to 1.
9:8
Reserved bit
Host;
RO
Device
7
Global OUT NAK Effective (GOUTNakEff)
Device
1'b0
RO
When it’s effective after the software sets the bit of
DCTL.SGOUTNak, the bit is set to 1. Clear this bit
-106-
by clearing 0 DCTL.SGOUTNak bit.
6
Global IN non-periodic
NAK effectiveDevice
1'b0
RO
(GINNakEff)
When it’s effective after the software sets the bit of
DCTL.SGNPInNak, the bit is set to 1
Clear this bit by clearing 0 DCTL. SGNPInNak bit.
5
Reserved bit
Host; Device
RO
4
RxFIFO non-empty (RxFLvl)
Host; Device1
1'b0
RO
When there is at least a packet in RxFIFO, the bit is
set to 1.
3
Start of frame (Sof)
Host; Device
1'b0
R_SS_W
In Host mode, when SOF transmits in USB bus, the
C
OTG controller sets the bit to
1. The software
writes 1 and clears this bit. In Device mode, when
OTG controller receives SOFT token, the bit is set
to
1. The software can obtain the current frame
number by reading Device status register.
2
OTG interrupt (OTGInt)
Host; Device
1'b0
RO
It’s set to 1, and indicates that the OTG protocol
transaction occurs. The software can read
GOTGINT register to determine the causes of
interrupt. In order to clear this bit, the software
must clear the corresponding status bit of
GOTGINT register.
1
Mode mismatch interrupt (ModeMis)
Host; Device
1'b0
R_SS_W
When the software tries to perform the next
C
operation, the bit is set to 1.
¡ñ When OTG operates in device mode, it tries to
access the register in host mode.
When OTG operates in host mode, it tries to
access the register in device mode.
0
Current operating mode (CurMod)
Host; Device
1'b0
RO
It indicates the operating mode of the current OTG
controller.
Ɣ1'b0: device mode
Ɣ1'b1: host mode
Interrupt mask register (GINTMSK)
Offset address: 018h
This register and GINTSTS register are used at the same time. When some interrupt is masked, this interrupt will
not be seen by software. Of course, the bit corresponding to GINTSTS is still set.
Field
Note
Operating
Reset value
Access
mode
characteristic
s
31
System recovery/remote wakeup interrupt mask bit
Host;
1'b0
R_SS_WC
(WkUpInt):Resume/RemoteWakeup
Device
Detected Interrupt Mask
30
SessionRequest/New Session Detected Interrupt
Host;
1'b0
R_SS_WC
(SessReqIntMsk): Session Request/New
Device
Reset Detected Interrupt Mask
29
DisconnIntMsk (disconnect interrupt mask)
Host
1'b0
R_SS_WC
28
Connector ID Status Change
Host;
1'b1
R_SS_WC
(ConIDStsChngMsk)
Device
27
Reserved bit
Host;
RO
Device
26
Periodic TxFIFO Empty Mask (PTxFEmpMsk)
Host
1'b1
RO
-107-
25
Host Channels Interrupt mask (HChIntMsk)
Host
1'b0
RO
24
Host port interrupt mask (PrtIntMsk)
Host
1'b0
RO
23
ResetDetMsk: Reset Detected Interrupt Mask
Device
1'b0
R_SS_WC
22
FetSuspMsk: Data Fetch Suspended Mask
Device
1'b0
R_SS_WC
21
Incomplete periodic transfer mask (incomplIPMsk)
Host
1'b0
R_SS_WC
Incomplete real-time OUT transmission mask
Device
(incomplSOOUTMsk)
20
Incomplete real-time IN transmission mask bit
Device
1'b0
R_SS_WC
(incomplSOINMsk)
19
OUT endpoint interrupt mask (OEPIntMsk)
Device
1'b0
RO
18
IN endpoint interrupt mask (IEPIntMsk)
Device
1'b0
RO
17:16
Reserved bit
Host;
Device
RO
15
End of Periodic frame mask (EOPFMsk)
Device
1'b0
R_SS_WC
14
Read-time
OUT packet Drop
MaskDevice
1'b0
R_SS_WC
(ISOOutDropMsk)
13
Enumeration done mask (EnumDoneMsk):
Device
1'b0
R_SS_WC
Enumeration Mask
12
USB reset mask (USBRstMsk)
Device
1'b0
R_SS_WC
11
USB suspended mask (USBSuspMsk)
Device
1'b0
R_SS_WC
10
Early Suspend mask (ErlySuspMsk)
Device
1'b0
R_SS_WC
9:8
Reserved bit
Host;
RO
Device
7
Global OUTNAK valid mask
Device
1'b0
RO
(GOUTNakEffMsk)
6
Global IN periodic NAK effective mask
Device
1'b0
RO
(GINNakEffMsk)
5
Reserved bit
Host;
RO
Device
4
RxFIFO non-periodic mask (RxFLvlMsk)
Host;
1'b0
RO
Device1
3
Start of Frame Mask Bit (SofMsk)
Host;
1'b0
R_SS_WC
Device
2
OTG interrupt mask (OTGIntMsk)
Host;
1'b0
RO
Device
1
Mode mismatching interrupt mask (ModeMisMsk)
Host;
1'b0
R_SS_WC
Device
0
Current Operating Mode Bit (CurMod)
Host;
1'b0
RO
Device
Receive status debugging register/status read and pop register (GRXSTSR/GRXSTSP)
Read offset address: 01Ch
Pop offset address: 020h
The read operation of receive status debugging register is the first option of RxFIFO. The read operation of status
read and pop register will pop the first option of RxFIFO.
The contents of receive status register have different explanations in host mode and device mode. If RxFIFO is
empty, OTG controller will ignore the read and pop operations of this register, and return 32'h0000_0000. When
the bit of GINTSTS.RxFLvl is 1, the software can only pop the receive Stastus FIFO.
NOTES: in different operating modes of OTG, all domains of this register have different explanations.
Host mode
Field
Note
Reset
Access
value
characteris
tics
-108-
31:21
Reserved domain
1
RO
20:17
Package status (PktSts)
4'b0
RO
Indicate the status of the received packet:
Ɣ4'b0010: IN data packet is received
Ɣ4'b0011: IN transmission end (triggered interrupt)
Ɣ4'b0101: Data toggle error (triggered interrupt)
Ɣ4'b0111: Channel halt (triggered interrupt)
ƔOthers: reserved
16:15
Data PID (DPID)
2'b0
RO
Indicate received packet data PID
Ɣ2'b00:DATA0
Ɣ2'b10:DATA1
Ɣ2'b01:DATA2
Ɣ2'b11:MDATA
14:4
Number of bytes (BCnt)
11'h0
RO
Indicate the byte number o the received IN data packet
3:0
Channel number (ChNum)
4'h0
RO
Indicate the channel number of the currently received
data packet
Device mode
Field
Note
Reset
Access
value
characteris
tics
31:25
Reserved domain
RO
24:21
Frame number (FN)
4'h0
RO
The lowest 4 bits of the frame number of the received
packet frame Only when it supports the real-time OUT
endpoint, is this domain effective.
20:17
Package status (PktSts)
4'b0
RO
Indicate the status of the received packet:
Ɣ4'b0001: Global OUT NAK (triggered interrupts)
Ɣ4'b0010: OUT data packet is received
Ɣ4'b0011: OUT transmission end (triggered interrupts)
Ɣ4'b0100: SETUP transaction end (triggered interrupt)
Ɣ4'b0110: SETUP data packet is received
ƔOthers: reserved
16:15
Data PID (DPID)
2'b0
RO
Indicate the data PID of the received OUT packet
Ɣ2'b00:DATA0
Ɣ2'b10:DATA1
Ɣ2'b01:DATA2
Ɣ2'b11:MDATA
14:4
Number of bytes (BCnt)
11'h0
RO
Indicate the byte number o the received IN data packet
3:0
Endpoint number (EPNum)
4'h0
RO
Indicate the endpoint number of the currently received
data packet
RxFIFO capacity register (GRXFSIZ)
Read offset address: 024h
The RAM size of RxFIFO which the software uses the register to allocate
Field
Note
Reset value
Access
characteristics
-109-
31:16
Reserved domain
RO
15:0
RxFIFO depth (RxFDep)
533
R_W
A 32-bits word as a unit.
ƔThe minimum value is 16
ƔThe maximum value is 32768
Non-periodic TxFIFO capacity register (GNPTXFSIZ)
Read offset address: 028h
The RAM size and starting address which the software uses the register to allocate to non-periodic TxFIFO
Note: no matter the OTG is in host operating mode or device operating mode, the register has
different
explanations.
In Host mode
Field
Note
Reset
Access
value
characteristi
cs
31:16
Non-periodic TxFIFO depth (NPTxDep)
256
R_W
A 32-bits word as a unit.
ƔThe minimum value is 16
ƔThe maximum value is 32768
15:0
Non-periodic TxRAM starting address (NPTxStAddr)
533
R_W
In Device mode
Field
Note
Reset
Access
value
characteristics
31:16
TxFIFO0 Depth of IN endpoint It is effective only in32
R_W
Device mode and OTG_EN_DED_TX_FIFO = 1
ƔThe minimum value is 16
ƔThe maximum value is 32768
15:0
FIFO0 TxRAM initial address of IN endpoint
533
R_W
Synopsys ID register (GSNPSID)
Read offset address: 040h
The version number containing OTG controller
Field
Note
Reset
Access
value
characteristics
31: 0
Synopsys ID (SynopsysID)
32'h4F54
RO
OTG controller version number
User HW Config1 register
Read offset address: 044h
User's hardware configuration register 2, specifying the endpont direction
Field
Note
Reset value
Access
characteristics
31: 14
Reserved domain
18'b0
RO
-110-
13: 0
Bits[13:12]:endpoint 6 direction
14'b0
RO
Bits [11:10]: endpoint 5 direction
Bits[9:8]:endpoint 4 direction
Bits[7:6]:endpoint 3 direction
Bits[5:4]:endpoint 2 direction
Bits[3:2]:endpoint 1 direction
Bits[1:0]:endpoint 0 direction
Ɣ2'b00: Bidirectional endpoint
Ɣ2'b01: IN endpoint
Ɣ2'b10: OUT endpoint
Ɣ2'b11: Reserved
User HW Config2 register
Read offset address: 048h
User's hardware configuration register 2
Field
Note
Reset value
Access
characteristi
cs
[31:26]
Reserved domain
6'b0
RO
25: 24
Aperiodic request queue depth
2'b10
RO
Ɣ2'b00: 2
Ɣ2'b01: 4
Ɣ2'b10: 8
Ɣ2'b11: 16
23: 22
Non-periodic request queue depth
2'b10
RO
Ɣ2'b00: 2
Ɣ2'b01: 4
Ɣ2'b10: 8
Ɣ2'b11: 16
21
Reserved domain
RO
20
Enable multiple processors interrupt
1'b0
RO
Ɣ1'b0: No
Ɣ1’b1: Yes
19
Enable dynamic FIFO size
1'b1
RO
Ɣ1'b0: No
Ɣ1’b1: Yes
18
Enable periodic OUT channel
1'b1
RO
Ɣ1'b0: No
Ɣ1’b1: Yes
17:14
The number of Channel in the Host mode
4'd12
RO
13:10
The number of endpoint in device mode, expect4'd6
RO
endpoint 0
9: 8
Full speed PHY interface type
2'b0
RO
Ɣ2'b00: none
Ɣ2'b01: FS has a dedicated pin
Ɣ2'b10: Shared with UTMI +
Ɣ 2'b11: shared with ULPI
7:6
HS PHY interface type
2'b0
RO
Ɣ2'b00: none
Ɣ2'b01: UTMI+
Ɣ2'b10: ULPI
Ɣ2'b11: UTMI + and ULPI
5
PTP (point-to-point)
1'b1
RO
Ɣ1'b0: No
-111-
Ɣ1’b1: Yes
4: 3
Architecture
2'b10
RO
Ɣ2'b00: Only as slave unit
Ɣ2'b01: External DMA
Ɣ2'b10: Embedded DMA
Ɣ2'b11: Reserved
2:0
Operating mode
3'b000
RO
Ɣ3'b000: support the OTG of HNP and SRP
(host and device)
Ɣ3'b001: only support the OTG of SRP (host
and device)
Ɣ3'b010: not support the OTG of HNP and
SRP (host and device)
Ɣ3'b011:support the device of SRP
Ɣ3'b100: the device of non-OTG
Ɣ3'b101: support the device of SRP
Ɣ3'b110: the host of non-OTG
ƔOthers: reserved
User HW Config3 register
Read offset address: 04Ch
User's hardware configuration register 3
Field
Note
Reset
Access
value
characteristics
[31:16]
DFIFO depth
16'd3072
RO
ƔThe minimum value is 32
ƔThe maximum value is 32768
15
OTG_ENABLE_LPM
1'b0
RO
Specify whether the OTG supports LPM mode
Ɣ1'b0: No
Ɣ1’b1: Yes
14
OTG_BC_SUPPOT
1'b0
RO
Specify whether to support USB charging
function
Ɣ1'b0: No
Ɣ1’b1: Yes
13
OTG_ENABLE_HSIC
1'b0
RO
Specify whether to support HSIC
Ɣ1'b0: No
Ɣ1’b1: Yes
12
OTG_ADP_SUPPORT
1'b0
RO
Specify whether to support ADP
Ɣ1'b0: No
Ɣ1’b1: Yes
11
OTG_SYNC_RESET_TYPE
1'b0
RO
Specify whether to support synchronous reset
Ɣ1'b0: No
Ɣ1’b1: Yes
10
Remove some unnecessary features (OptFeature)
1'b1
RO
Ɣ 1’b0: No
Ɣ 1’b1: Yes
9
Whether to support vendor control interface1'b0
RO
(VndctlSupt)
The interface is used to access PHY internal
register.
Ɣ1'b0: No
-112-
Ɣ 1’b1: Yes
8
Whether to support I2C interface (I2CIntSel)
1'b0
RO
Ɣ1'b0: No
Ɣ1’b1: Yes
7
OTG function enable (OtgEn)
1'b1
RO
Specify whether to enable OTG function
Ɣ1'b0: No
Ɣ1’b1: Yes
6: 4
Packet Counters width (PktSizeWidth)
3'b110
RO
Indicate the maximum number of USB
controller send/ receive Packet in a transmission
Ɣ3'b000: 4bits
Ɣ3'b001: 5bits
Ɣ3'b010: 6bits
Ɣ3'b011: 7bits
Ɣ3'b100: 8bits
Ɣ3'b101: 9bits
Ɣ3'b110: 10bits
ƔOthers: reserved
3: 0
TransferSizeCounters
width(XferSizeWidth),4'b1000
RO
indicate the maximum size of data transmission
Ɣ4'b0000: 11bits
Ɣ4'b0001: 12bits
…
Ɣ4'b1000: 19bits
Others: Reserved
User HW Config4 register
Read offset address: 050h
User's hardware configuration register 4
Field
Note
Reset value
Access
characteristi
cs
31
Reserved
RO
30
Wether to support Scatter/Gather DMA
1'b1
RO
Ɣ1'b0: No
Ɣ1’b1: Yes
29:26
In Device mode, the number of IN endpoint,4
RO
including endpoint0 (INEps)
Ɣ0: 1 IN endpoints
Ɣ1: 2 IN endpoints
…
Ɣ16: 16 IN endpoints
25
For Device In endpoint enable dedicated1'b1
RO
TxFIFO
Ɣ1'b0: No
Ɣ1’b1: Yes
24
Whether to add the de-twitter logic to1'b1
RO
session_end signal
Ɣ1'b0: No
Ɣ1’b1: Yes
23
Whether to add the de-twitter logic to b_valid1'b1
RO
signal
Ɣ1'b0: No
-113-
Ɣ1’b1: Yes
22
Whether to add the de-twitter logic to a_valid1'b1
RO
signal
Ɣ1'b0: No
Ɣ1’b1: Yes
21
Whether to add the de-twitter logic to1'b1
RO
vbus_valid signal
Ɣ1'b0: No
Ɣ1’b1: Yes
20
Whether to add the de-twitter logic to1'b1
RO
iddig_valid signal
Ɣ1'b0: No
Ɣ1’b1: Yes
19:16
Remove endpoint0£¬ control the number of4'b0
RO
ednpoints in device mode
15:14
UTMI + PHY data width
2'b10
RO
Ɣ2'b00: 8bits
Ɣ2'b01: 16bits
Ɣ2'b10: 8/16 bits software selectable
Ɣ2'b11: Reserved
13:7
Reserved domain
RO
6
Enable Hibernation
1'b0
RO
¡ñ1’b0: No
Ɣ1'b1: Yes
5
If AHB frequency lower than the minimum
1'b0
RO
60MHA(AhbFreq)
Ɣ1’b0: No
Ɣ1'b1: Yes
4
Whether to reduce part of the power1'b1
RO
consumption
Ɣ1’b0: No
Ɣ1'b1: Yes
3:0
Reserved field
RO
DFIFO software configuration register (GDFIFOCFG)
Read offset address: 05Ch
Field
Note
Operating mode
Reset value
Access
characteris
tics
31:16
EPInfoBaseAddr
Host; Device
EPINFO_BASEADDR
R_W
Initial
address of Endpoint
controller
15:0
GDFIFOCfg
Host; Device
3072
R_W
Dynamic configuration of DFIFO
size
Periodic TxFIFO capacity register in Host mode (GNPTXFSIZ)
Read offset address: 0100h
Field
Note
Reset value
Access
characteristi
cs
31:16
PTxFSize
512
R_W
Periodic TxFIFO depth (NPTxDep)
32-bits word as a unit.
-114-
ƔThe minimum value is 16
ƔThe maximum value is 32768
15:0
PTxFStAddr
789
R_W
Initial address of periodic TxFIFO in Host mode
IN endpoint TxFIFO1 capacity register in Device mode (DIEPTXF1)
Read offset address: 0104h
Field
Note
Reset value
Access
characteristi
cs
31:16
INEPnTxFDep
256
R_W
IN endpoint TxFIFO1 depth£¬a 32-bit word as a
uint.
ƔThe minimum value is 16
ƔThe maximum value is 32768
15:0
INEPnTxFStAddr
565
R_W
Initial address of IN endpoint FIFO 1
IN endpoint TxFIFO2 capacity register in Device mode (DIEPTXF2)
Read offset address: 0108h
Field
Note
Reset value
Access
characteristics
31:16
INEPnTxFDep
256
R_W
IN endpoint TxFIFO2 depth, 32-bit word
as a uint.
ƔThe minimum value is 16
ƔThe maximum value is 32768
15:0
INEPnTxFStAddr
821
R_W
Initial address of IN endpoint FIFO 2
IN endpoint TxFIFO3 capacity register in Device mode (DIEPTXF3)
Read offset address: 010Ch
Field
Note
Reset value
Access
characteristics
31:16
INEPnTxFDep
512
R_W
IN endpoint TxFIFO3 depth, 32-bit word
as a uint.
ƔThe minimum value is 16
ƔThe maximum value is 32768
15:0
INEPnTxFStAddr
1077
R_W
Initial address of IN endpoint FIFO 3
13.3.3 Host mode register
This register block is only effective in Host mode, and can’t be accessed in host mode.
Host mode configuration register (HCFG)
Offset address: 400h
Field
Note
Reset value
Access
characteristics
31:28
Reserved domain
RO
27
ModeChTimEn
1'b0
R_W
Whether to enable mode changes into ready timer.
-115-
Decide at the end of Resume state whether to enable
host controller to change 2'b10 into 00 of PHY opmode
signal after waiting for 200PHY clocks
Ɣ1'b0: No
Ɣ1'b1: Yes
26
PerSchedEna
1'b0
R_W
Whether to enable periodic schedule.
Ɣ1'b0: No
Ɣ1'b1: Yes
25:24
FrListEn
2'b00
R/W
Frame list number of terms
Ɣ2'b00: 8
Ɣ2'b01: 16
Ɣ2'b00: 32
Ɣ2'b00: 64
23
DescDMA
1'b0
RO
In Host mode, enable Scatter/gather DMA
Note: after resetting, this can only be modified once.
The following configurations are available:
ƔGAHBCFG.DMAEn = 0, HCFG.DescDMA = 0 =>
slave mode;
ƔGAHBCFG.DMAEn= 0, HCFG.DescDMA = 1 =>
illegal configuration;
GAHBCFG.DMAEn= 1, HCFG.DescDMA = 0 =>
Buffered DMA mode;
ƔGAHBCFG.DMAEn= 0, HCFG.DescDMA = 1 =>
Scatter/Gather mode;
15:0
Reserved domain
RO
Host frame interval register (HFIR)
Offset address: 404h
Field
Note
Reset value
Access
characteristics
31:17
Reserved field
RO
16
Reload control
1'b0
R_W
Does it allow the dynamic reloading into HFIR
register
Ɣ1'b0: No
Ɣ1'b1: Yes
15:0
Frame interval (FrInt)
16'd60000
R_W
The software uses this value to determine the interval
between two consecutive micro-SOFs In PHY clock
bit units. Only after the bit of HPRT.PrtEnaPort is set
to 1, can this bit be changed. No changes can be made
after the initial configuration.
125us * (PHY clock frequency)
Host frame number/rest frame time register (HFNUM)
Read offset address: 408h
Field
Note
Reset value
Access
characteristics
31:16
Remaining frame time
16'h0
RO
It indicates the rest time of the current microFrame in
-116-
the unit of PHY clock. When the bit is 0, the value of
HFIR.FrInt is reloaded, and one new SOF is sent in
USB bus
15:0
Frame number (FrNum)
16'h3FFF
RO
In a new SOF transfer, this domain adds 1, and when
reaching 16'h3FFF, it’s reset to 0.
Host periodic TxFIFO/Queue status register (HPTXSTS)
Offset address: 410h
Field
Note
Reset value
Access
characteristics
31:24
PTxQTop
8'h0
RO
The first item of periodic TxFIFO request (TOP) is used
for debugging.
ƔBits [31]: Odd-even frame
-1'b0: Transmit in even frames
-1'b1: Transmit in odd frame
ƔBits [30:27]: channel number
ƔBits [26:25]: type
-2'b00: IN / OUT
-2'b01: 0 length packet
-2'b10: CSPLIT
-2'b11: invalid channel command
ƔBits [24]: Terminate (the last item for the selected
channel)
23:16
PTxQSpcAvali
8
RO
Periodic Tx available request queue number of term.
It indicates the number of null terms in periodic request
queue, and the request queue includes IN and OUT.
Ɣ8'h0: queue full
Ɣ8'h1: 1 null terms
Ɣ8'h2: 2 null terms
。。。。
Ɣ8'h8: 8 null terms
ƔOthers: Reserved
15:0
PTxFSpcAvail
512
RO
Periodic TxFIFO available number of term
A 32-bits word as a unit.
Ɣ16'h0: FIFO full
Ɣ16'h1: 1 null terms
…
Ɣ16'h200: 512 null terms
Host interrupt register in all channels (HAINT)
Read offset address: 414h
Field
Note
Reset value
Access
characteristics
31:16
Reserved domain
RO
15:0
Channel interrupt (HAINT)
16'h0
RO
One bit corresponds to one channel:
Bits [11]: channel 11
。。。
Bits0 : channel 0
-117-