Loongson 1C300 Processor User Manual (Version 1.0, 2014) - page 7
Host All Channel Interrupt Mask Register (HAINTMSK)
Read offset address: 414h
Field
Note
Reset value
Access
characteristics
31:16
Reserved field
RO
15:0
Channel Interrupt Mask (HAINTMSK)
16'h0
R_W
One bit corresponds to one channel:
Bits [11]: channel 11
。。。
Bits 0: channel 0
Host Port Control and Status Registers (HPRT)
Read offset address: 440h
Field
Note
Reset value
Access
characteristics
31:19
Reserved field
RO
18:17
PrtSpd
2'b0
RO
Port Speed
Ɣ2'b00: high speed
Ɣ2'b01: full speed
Ɣ2'b10: low speed
Ɣ2'b11: Reserved
16:13
PrtTstCtl
4'h0
R_W
Port test control
When the software writes non-0 value to this domain,
the port enters into the test mode.
The corresponding Pattern occurs in port.
Ɣ4'b0000: Non-test mode
4'b0001: Test_J mode
Ɣ4'b0010: Test_K mode
Ɣ4'b0011: Test_SE0_NAK mode
Ɣ4'b0100: Test_Packet mode
Ɣ4'b0101: Test_Force mode
ƔOthers: Reserved
12
PrtPwr
1'b0
R_W_SC
Port power supply.
Ɣ1'b0:power off
Ɣ1'b1:power on
11:10
Port Line Status(PrtLnSts)
1'b0
RO
ƔBits [10]: D
ƔBits [11]: D
9
Reserved
RO
8
Port reset (PrtRst)
1'b0
R_W
7
Port suspend (PrtSup)
1'b0
R_WS_SC
6
Port restoration (PrtRes)
1'b0
R_W_SS_
SC
5
Port overcurrent change (PrtOvrCurrChng)
1'b0
R_SS_WC
When PrtOvrCurrAct changes, OTG controller sets the
bit to 1
4
Port Overcurrent Activity (PrtOvrCurrAct)
1'b0
RO
ƔNo
ƔYes
3
Port Enable Status Change (PrtEnChng)
1'b0
R_SS_WC
When PrtEna changes, OTG controller sets the bit to 1
-118-
2
Port enable bit (PrtEna)
1'b0
R_SS_SC
Ɣ1'b0: No
_WC
Ɣ1'b1: Yes
1
When PrtConnDet (Port connection detect) finds the1'b0
R_SS_WC
device connection, it’ll
trigger
interrupt
by
GINTSTS.PrtInt. Write 1 for software and clear this bit.
0
Port connection status (PrtConnSts)
1'b0
RO
ƔNo device is connected to this port
ƔDevice is connected to this port
Host Channel-n characteristic register (HCCHARn)
Channel_num: 0 <= n <= 11
Read the offset address: 500h + (Channel_num * 20h)
Field
Note
Reset value
Access
characteristics
31
Channel enable (ChEna)
1'b0
R_WS_SC
When Scatter/Gather mode is enabled,
Ɣ1'b0: Indicate the descriptor structure is not ready
Ɣ1'b1: It indicates that the descriptor structure and data
buffer have been prepared, and the channel can access the
descriptor
When Scatter/Gather mode is disabled,
Ɣ1'b0: Channel disable
Ɣ1'b1: Channel enable
30
Channel disable (ChDis)
1'b0
R_WS_SC_SS
Even if the transmission in channel hasn’t finished, the
software ware can stop the data transmission and receive
in this channel by setting the bit to 1. The software must
wait that the endpoint valid interrupt happens, can it think
the channel has been invalid.
29
Odd frames (OddFrm)
1'b0
R_W
The software notifies that OTG host must finish one
transmission within odd micro Frame by setting the bit to
1. This domain is only valid to periodic transaction
(real-time and interrupt)
Ɣ1'b0: Even frames
Ɣ1'b1: Odd frames
28:22
Device address (DevAddr)
7'h0
R_W
21:20
MultiCount (MC) /ErrorCount(EC)
2'b0
R_W
When HCSPLTn.SpltEna is 1'b0, this domain indicates
the number of transactions finished within each
microFrame time for each periodic endpoint. For the
non-periodic transmission, this domain is only used in
DMA mode, and is used to specify the number of packets
obtained by host for this channel before the DMA changes
the arbitration.
Ɣ 2'b00: Reserved
Ɣ 2'b01: 1 transaction
Ɣ 2'b10: 2 transaction
Ɣ 2'b11: 3 transaction
When CSPLTn.SpltEna is 1'b1, the domain indicates the
retransmission times in case of a periodic split
transaction. At least set 2'b01
19:18
Endpoint type (EPType)
2'b0
R_W
Ɣ2'b00: Control
-119-
Ɣ2'b01: Real time
Ɣ2'b10: Bulk
Ɣ2'b11: Interrupt
17:16
Reserved
RO
15
Endpoint direction (EPDir)
1'b0
R_W
Ɣ1'b0: OUT
Ɣ1'b1: IN
14:11
Endpoint number
4'b0
R_W
10:0
Maximum packet size (MPS)
11'h0
R_W
Host Channel-n Split control register (HCSPLTn)
Channel_num: 0 <= n <= 11
Read offset address: 504h + (Channel_num * 20h)
Field
Note
Reset value
Access
characteristic
s
31
Split enable
1'b0
R_W
30:17
Reserved
RO
16
Do Complete Split
1'b0
R_W
It indicates OTG host must finish one
complete split transmission
15:14
Transaction position (XactPos)
2'h0
R_W
Ɣ2'b00; all, entire data of this
transaction
(Less than or equal to 188B)
Ɣ2'b01:begin, the starting data of this
transaction (less than or equal to 188B)
Ɣ2'b10:Mid, the intermediate data of
this transaction
(less than or equal to
188B)
Ɣ2'b01: End, the end data of this
transaction (less than or equal to 188B)
13:7
Hub address (HubAddr)
7'b0
R_W
[6£º0]
Port address (PrtAddr)
7'h0
R_W
Host Channe-n interrupt register (HCINTn)
Channel_num: 0 <= n <= 11
Read offset address: 508h + (Channel_num * 20h)
Field
Note
Reset
Access
value
characteristics
31:14
Reserved
RO
13
Descriptor rollover interrupt (DESC_LST_ROLLIntr)
1'b0
R_SS_WC
Only when the Scatter/Gather DMA mode is enabled, this
domain is valid. The bit is set to 1 when the descriptor list in
corresponding channel rolls over.
For non-Scatter/Gather DMA mode, this domain set reserves
the field
12
Excessive transaction error (XCS_XACT_ERR)
1'b0
R_SS_WC
When the Scatter/Gather DMA mode is enabled, this domain
is valid. When three consecutive transactions go wrong, the
bit is set to 1.
For non-Scatter/Gather DMA mode, this domain set reserves
the field
11
BNA(buffer unavailable) interrupt (BNAIntr)
1'b0
R_SS_WC
-120-
When the Scatter/Gather DMA mode is enabled, this domain
is valid. When the descriptor access isn’t prepared, the bit is
set to 1.
For non-Scatter/Gather DMA mode, this domain set reserves
the field
10
Data inversion error (DataTglErr)
1'b0
R_SS_WC
9
Frame overrun (FrmOvrun)
1'b0
R_SS_WC
8
Bubble error (BblErr)
1'b0
R_SS_WC
7
Transaction error (XactErr)
1'b0
R_SS_WC
When the error occurs in USB bus, the bit is set to 1:
ƔCRC verify unsuccessfully
ƔTime-out
ƔBit stuffing error
ƔWrong EOP
6
Receive NYET handshake (NYET)
1'b0
R_SS_WC
5
Receive ACK handshake (ACK)
1'b0
R_SS_WC
4
Receive NAK handshake (NAK)
1'b0
R_SS_WC
3
Receive STALL handshake (STALL)
1'b0
R_SS_WC
2
AHB error (AHBErr)
1'b0
R_SS_WC
1
Channel halted (ChHltd)
1'b0
R_SS_WC
For non- Scatter/Gather DMA mode, the abnormal end of
transmission caused by USB transmission error or software
sets invalid request, or the bit is set to 1 in normal end.
For Scatter/Gather DMA mode, if the transmission ends
because of the following reasons, the bit is set to 1:
Ɣ EOL setting in descriptor
Ɣ AHB error
Ɣ Excessive transaction error
Ɣ Invalid software setting request
Ɣ Vacuole
Ɣ Stall
0
EOT (end of transmission)
1'b0
R_SS_WC
For Scatter/Gather DMA mode, it indicates completing the
process of the current descriptor, and the bit of the descriptor
IOC is set to 1.
For non- Scatter/Gather DMA mode, it indicates the
completion of transmission without any error.
Host Channel-n interrupt mask register *( HCINTMSKn)
Channel_num: 0 <= n <= 11
Read offset address: 50Ch + (Channel_num * 20h)
Field
Note
Reset value
Access
characteristics
31:14
Reserved
RO
13
Descriptor rollover interrupt mask bit
1'b0
R_W
(DESC_LST_ROLLIntrMsk)
Only when the Scatter/Gather DMA mode is
enabled, this domain is valid.
For non-Scatter/Gather DMA mode, this
domain set reserves the field
12
Reserved
RO
11
Reserved
RO
10
Data
reverse
error
interrupt
mask
1'b0
R_W
(DataTglErrMsk)
9
Frame overrun interrupt mask (FrmOvrunMsk)
1'b0
R_W
-121-
8
Bubble error interrupt mask (BblErrMsk)
1'b0
R_W
7
Transaction error mask (XactErrMsk)
1'b0
R_W
6
Receive NYET handshake interrupt mask
1'b0
R_W
(NYETMsk)
5
Receive ACK handshake interrupt mask
1'b0
R_W
(ACKMsk)
4
Receive NAK handshake interrupt mask
1'b0
R_W
(NAKMsk)
3
Receive STALL handshake interrupt mask
1'b0
R_W
(STALLMsk)
2
AHB error interrupt mask (AHBErrMsk)
1'b0
R_W
1
Channel halted interrupt mask (ChHltdMsk)
1'b0
R_W
0
Transfer
complete
interrupt
mask
1'b0
R_W
(XferComplMsk)
Host Channel-n transfer size register (HCTSIZn)
Channel_num: 0 <= n <= 11
Read offset address: 510h + (Channel_num * 20h)
In Scatter/Gather DMA mode, various domains of this register is defined as follows:
Field
Note
Reset value
Access
characteristics
31
Do ping(DoPng)
1'b0
R_W
It’s only valid to OUT transmission, and when the bit is
set to 1, it indicates the Host does the PING protocol.
If the bit is set to 1 in IN transmission, this channel will
be invalid
30:29
PID(Pid)
2'b0
R_W
Ɣ2'b00:DATA0
Ɣ2'b01:DATA2
Ɣ2'b10:DATA1
Ɣ2'b11: MDATA (non-control)
28:16
Reserved domain
9'b0
RO
15:8
NTD (the number of transmitting descriptors)
8'h0
R_W
(Non-real time transmission)
Ɣ0-1 descriptors
Ɣ63-64 descriptors
(Real-time transmission)
Ɣ7-8 descriptors
Ɣ15-16 descriptors
Ɣ31-32 descriptors
Ɣ63-64 descriptors
Ɣ127-128 descriptors
Ɣ255-256 descriptors
7:0
SCHED_INFO (scheduling information)
8'h0
R_W
The corresponding bit represents the angle in the
microFrame. Bit0 represents the scheduling in
1st
microFrame Bits7 represents the scheduling in
8th
microFrame
8'b11111111 represents the scheduling of the
corresponding interrupt channel and one token is sent
every other microFrame in corresponding frame time.
8'b10101010 represents the scheduling of the
corresponding interrupt channel and one token is sent
every other microFrame in corresponding frame time.
Note, this domain is only valid for periodic
-122-
transmission.
In Non-Scatter/Gather DMA mode, various domains of this register are defined as follows:
Field
Note
Reset value
Access
characteristics
31
Do ping(DoPng)
1'b0
R_W
It’s only valid to OUT transmission, and when the bit is
set to 1, it indicates the Host does the PING protocol.
If the bit is set to 1 in IN transmission, this channel will
be invalid
30:29
PID(Pid)
2'b0
R_W
Ɣ2'b00:DATA0
Ɣ2'b01:DATA2
Ɣ2'b10:DATA1
Ɣ2'b11: MDATA (non-control)
28:19
Packet number (PktCnt).
10'h0
R_W
Packet data of software write-in transmission.
When one transmission finishes, host will reduce the
domain by 1. Once it’s 0, the software will receive the
interrupt and indicate the normal end.
18:0
Transmission size (XferSize)
19'h0
R_W
For OUT transmission, it specifies the number of bytes
transited by host; for IN transmission, it specifies the
number data bytes received by host.
Host Channel-n DMA address register (HCDMAn)
Channel_num: 0 <= n <= 11
Read offset address: 514h + (Channel_num * 20h)
In IN/OUT transmission, the register is used to maintain the address of the current buffer. The starting address of
DMA transmission must be double-word aligned.
Field
Note
Reset value
Access
characteristic
s
Buffer DMA Mode
DMA address (DMAAddr)
31:0
Transaction-post accumulation of each AHB
X
R_W
Descriptor DMA mode
DMA address (DMAAddr)
Non-real time transmission: save the starting
address of 512-byte page The first descriptor in
descriptor list is in this address. OTG controller
starts to process descriptor list from CTD
Real-time transmission: save the address of
2*(nTD+1) bytes, and the address is the location of
the real-time descriptor. The N value is based on
nTD, as shown in the table below:
31: N
31:N
N-1: 3
2:0
(Real-time)
Base address
Offset
000
31:9
(Non-real
nTD
N
23'h0
R/W
time)
7
6
15
7
31
8
63
9
127
10
255
11
-123-
N-1: 3
Current transmission descriptor (CTD)
(Real-time)
Non-real time transmission: its unit is descriptor
and the range is
0-63. It indicates the current
8:
processing descriptor.
6'h0
R/W
(Non-real
Real-time transmission: based on the value of the
time)
current micorFrame, it needs clearing by software.
2:0
Reserved
3'h0
RO
Host Channel-n DMA Buffer address register (HCDMAn)
Channel_num: 0 <= n <= 11
Read offset address: 518h + (Channel_num * 20h)
This is only valid in Scatter/Gather DMA mode
Field
Note
Reset value
Access
characteristics
31:0
Current buffer address.
X
RO
Host Frame List base address register (HFLBAddr)
Offset: 41Ch
This is only valid in Scatter/Gather DMA mode
Field
Note
Reset value
Access characteristics
31:0
Initial address of frame list
32'h0
RO
13.3.4 Device Mode Register
This register block is only effective in device mode, and can’t be accessed in host mode.
Device configuration register (DCFG)
Offset: 800h
After the initial configuration, the value of this register can’t be modified.
Field
Note
Reset value
Access
characteristics
31:26
Resume validity (ResValid)
6'd2
R_W
This domain controls the switch time of OTG controller
from suspended state to resume. Clock period as a unit.
Only when DCFG.Ena32KHzSusp is set to 1, this bit is
significant.
25:24
Periodic schedule interval (PerSchIntvl)
2'b00
R_W
Valid only in Scatter/Gather DMA mode.
It’s used to specify the time allocated by DMA engine to
periodic IN endpoint to obtain data. Based on the number of
periodic IN endpoints, its value must be set to
75%microFrame.
ƔWhen any periodic endpoint activates, DMA engine
allocates certain time for periodic IN endpoint to obtain
data.
ƔIgnore this domain when there is no periodic end node
activity
ƔAfter the time is set, DMA engine begins to obtain data for
non-periodic endpoint.
Ɣ2'b00: 25% microFrame
Ɣ2'b01: 50% microFrame
Ɣ2'b10: 75% microFrame
Ɣ2'b11: Reserved
23
In device mode, Scatter/Gather DMA mode (DescDMA) is1'b0
R_W
-124-
enabled.
ƔGAHBCFG. DMAEn=0, DCFG. DescDMA=0 => from mode
ƔGAHBCFG. DMAEn=0, DCFG. DescDMA=1 => illegal
ƔGAHBCFG. DMAEn=1, DCFG. DescDMA=0 => buffer
DMA mode
ƔGAHBCFG.DMAEn=0,DCFG.DescDMA=0=>
Scatter/Gather DMA mode
22:14
Reserved
RO
13
Whether to enable device OUT NAK
1'b0
R_W
Only valid for descriptor DMA mode
Ɣ1'b0: When the bulk OUT transfer ends, OTG controller
doesn’t send out the NAK handshaking signal.
Ɣ1'b0: When the bulk OUT transfer ends, OTG controller
sends out the NAK handshaking signal.
12:11
Periodic frame interval (PerFrInt)
2'h0
R_W
It indicates when one microFrame uses EOP interrupt to
notify the software. This domain is used to decide whether
the current microFrame has finished all real-time transfers.
Ɣ2'b00: 80%
Ɣ2'b01: 85%
Ɣ2'b00: 90%
Ɣ2'b00: 95%
10:4
Device address (DevAddr)
7'h0
R_W
3
Reserved
1'b0
RO
2
Non-zero length Status OUT handshake (NZStsOUTHShk)
1'b0
R_W
If OTG receives a non-zero data packet in OUT event in the
Status stage of control transfer, this domain is used to select
different handshaking signals controlled and transmitted by
OTG.
Ɣ1'b1: STALL
Ɣ1'b0: send out the received OUT data packet, and then
transmit the handshaking signal based on NAK and STALL
bits in device endpoint control register.
1:0
Device speed (DevSpd)
2'b0
R_W
Ɣ2'b00: HS(USB2.0 PHY )
Ɣ2'b01: FS(USB2.0 PHY )
Ɣ2'b10: LS(USB1.1 PHY )
Ɣ2'b11: FS(USB1.1 PHY )
Device control register (DCTL)
Offset: 808h
Field
Note
Reset value
Access
characteristics
31:17
Reserved
RO
16
Send out NAK handshake in the case of babble
1'b0
R_W
15
For real-time endpoint, ignore frame number (IgnrFrmNum)1'b0
R_W
ƔGAHBCFG. DMAEn=0, this domain is invalid
ƔGAHBCFG. DMAEn=1, DCFG. DescDMA = 0: When the
threshold mode is valid, this bit is invalid. Or, the software
uses this bit to enable the periodic transfer interrupt.
-1'b0 invalid periodic transmission interruption
- When 1'b1receives ISOC IN token, it doesn’t need to
clear the packet.
OTG controller ignores the frame number, when the packet
is prepared and receives the corresponding token, this
packet will be sent out. This domain is also used to enable
-125-
periodic interrupt transmission
Ɣ GAHBCFG. DMAEn=1, DCFG. DescDMA = 1: Invalid
high-speed transmission
14:13
Global Multi Count (GMC)
2'h0
R_W
Valid only in Scatter/Gater DMA mode. It is used to
indicate the number of received and transmitted packets
before transferred to next endpoint. Valid only for aperiodic
end nodes.
Ɣ2'b00: Illegal
Ɣ2'b01: One package;
Ɣ2'b00: Two packages;
Ɣ2'b00: Three packages;
When DCFG.DescDMA
=1, this domain will be
automatically changed to 2'h1
12
Reserved domain
RO
11
Powr-on programming is done (PWROnPrgDone)
1'b0
R_W
After recovering from power_down mode, when the register
programming is finished, the bit is set to 1.
10
Clear Global OUT NAK (CGOUTNak)
1'b0
WO
For the write to this bit, Clear Global OUT NAK
9
Set Global OUT NAK(SGOUTNak)
1'b0
WO
For the write to this bit, set Global OUT NAK
8
Clear Global Non-periodic IN NAK (CGNPInNak)
1'b0
WO
For the write to this bit, clear Global Non-periodic IN NAK
7
Set Global Non-periodic IN NAK (SGNPInNak)
1'b0
WO
For the write to this bit, set Global Non-periodic IN NAK
6: 4
Test control (TstCtl)
3'b0
R_W
Ɣ3'b000: Invalid Test mode
Ɣ3'b001: Test_J mode
Ɣ3'b010: Test_K mode
Ɣ3'b011: Test_SE0_NAK mode
Ɣ3'b100: Test_Packet mode
Ɣ3'b101: Test_Force_Enable mode
Ɣ Others: Reserved
3
Global OUT NAK status (GOUTNakSts)
1'b0
RO
Ɣ1'b0: Based on FIFO status, NAK and STALL bit setup,
corresponding handshake is transmitted.
Ɣ1'b1: No matter whether RxFIFO has the null term, no
data is written in RxFIFO. Except SETUP event, all packets
send NAK handshake. Termination of all real-OUT packet.
2
Global non-periodic IN NAK Status Bit
1'b0
RO
Ɣ1’b0: Based on valid data of TxFIFO, corresponding
handshake is sent.
Ɣ1’b1: For all non-periodic IN endpoints, NAK handshake
signals are transmitted, no matter whether TxFIFO has
effective data.
1
Soft disconnection (SftDisCon)
1'b0
R_W
If this bit is set to 1, the host can’t see device connection,
and the device can’t receive the USB signal.
Ɣ1'b0: Normal operation
Ɣ1'b1: OTG controller will set the phy_opmode_o signal
in utmi+ interface to
2'b01, which will generate a
disconnect event to the USB host.
0
Remote Wakeup signal (RmtWkUpSig)
1'b0
R_W
When the bit is set to 1, the OTG controller will send a
remote wakeup signal to wake up the USB host.
-126-
Device status register (DSTS)
Offset: 808h
Field
Note
Reset value
Access
characteristics
[31:22]
Reserved
RO
21:8
Received SOF Frame Number (SOFN)
14'h0
RO
7: 4
Reserved
RO
3
Serious error (ErrticErr)
RO
Through this domain, the OTG controller reports serious
error
(because
PHY
goes
wrong,
phy_rxvalid_i/phy_rxvldh_i or phy_rxactive_i
setting
exceeds 2ms). In the event of serious errors, the OTG
controller will enter into the suspend mode, and
GINTSTS.ErlySusp bit is set to 1, and only the software
can recover through soft break.
2:1
Enumeration speed (EnumSpd)
RO
Ɣ2'b00: HS(USB2.0 PHY )
Ɣ2'b01: FS(USB2.0 PHY )
Ɣ2'b10: LS(USB1.1 PHY )
Ɣ2'b11: FS(USB1.1 PHY )
0
Suspending status (SuspSts)
1'b0
RO
In Device mode, as long as the suspend status found in
USB bus, set it to 1. When utmi_linestate signal doesn’t
activate within certain event, the OTG controller will
enter into the suspended state. The OTG controller will
exit from the suspended state if —:
Ɣ utmi_linestate signal activates
ƔThe software writes 1 in DCTL.RmtWkUpSig bit.
Device In Endpoint Common Interrupt Mask Register (DIEPMSK)
Offset: 810h
Field
Note
Reset value
Access
characteristics
31:14
Reserved
RO
13
NAK Interrupt Mask Bit (NAKMsk)
1'h0
R_W
12:10
Reserved
RO
9
BNA Interrupt Mask Bit (BNAInIntrMsk)
1'h0
R_W
Valid only when descriptor is in the DMA mode
8
FIFO
Underflow
Interrupt
Mask
Bit1'b0
R_W
(TxFifoUndrnMSK)
7
Reserved
1'b0
RO
6
IN endpoint NAK valid interrupt mask bit
1'b0
R_W
(INEPNakEffMsk)
5
Receive the IN token interrupt mask bit mismatching EP
1'b0
R_W
(INTknEPMisMsk)
4
When TxFIFO is empty and receives IN token interrupt1'b0
R_W
mask bit
(INTknTXFEmpMsk)
3
Timeout interrupt mask bit
1'b0
R_W
(TImeOUTMsk)
Valid only for non-real-time end node
2
AHB error interrupt mask bit
1'b0
R_W
(AHBErrMsk)
1
End nodes failure interrupt mask bit
1'b0
R_W
(EPDisbldMsk)
-127-
0
Transmission completion interrupt mask bit
1'b0
R_W
(XferCompIMsk)
device Out Endpoint Common Interrupt Mask Register (DIEPMSK)
Offset: 814h
Field
Note
Reset value
Access
characteristics
31:15
Reserved
RO
14
NYET interrupt mask bit
1'b0
R_W
(NYETMsk)
12
Bubble interrupt mask bit
1'b0
R_W
(BbleErrMsk)
11:10
Reserved
RO
9
BNA interrupt mask bit
1'b0
R_W
(BnaOutIntrMsk)
8
OUT packet error interrupt mask bit
1'b0
R_W
(OutPktErrMsk)
7
Reserved
RO
6
Receives the back-to-back SETUP packet interrupt mask1'b0
R_W
bit
(Back2BackSETup)
5
Reserved
RO
4
When the endpoint is invalid and receives OUT token1'b0
R_W
interrupt mask bit
(OUTTknEPdisMsk)
3
SETUP phase completion interrupt mask bit
1'b0
R_W
(SetUPMsk)
2
AHB error interrupt mask bit
1'b0
R_W
(AHBErrMsk)
1
End nodes failure interrupt mask bit
1'b0
R_W
(EPDisbldMsk)
0
Transmission completion interrupt mask bit
1'b0
R_W
(XferComplMsk)
Device all endpoints common interrupt register (DAINT)
Offset: 818h
Field
Note
Reset value
Access
characteristics
31:16
OUT endpoint interrupt register bit (OutEPInt)
16'h0
RO
1 OUT end node corresponding to
1 bit Bit
16
corresponding to the end node 0
15:0
IN endpoint interrupt register bit (InEPInt)
16'h0
RO
1 IN end node corresponding to
1 bit Bit
0
corresponding to the end node 0
Device all endpoints common interrupt register (DAINTMSK)
Offset:81Ch
Field
Note
Reset
Access
value
characteristics
31:16
OUT endpoint interrupt register bit (OutEPIntMsk)
16'h0
R_W
1 OUT end node corresponding to
1 bit Bit
16
-128-
corresponding to the end node 0
15:0
IN endpoint interrupt register bit (InEPIntMsk)
16'h0
R_W
1 IN end node corresponding to 1 bit Bit 0 corresponding
to the end node 0
Device VBUS Discharge Register (DVBUSDIS)
Offset: 828h
Field
Note
Reset value
Access
characteristics
31:16
Reserved
RO
15:0
Device Vbus Discharge Time (DVBUSDis)
30MHZ:
R_W
During SRP, the discharge time of Vbus after Vbus16'h0B8F
impulse. In PHY clock bit units.
60MHZ:
16'h17D7
Device VBUS Pulse Register (DVBUSPULSE)
Offset: 82Ch
Field
Note
Reset value
Access
characteristics
31:12
Reserved
RO
11:0
Device Vbus Pulse Time ()
30MHZ:
R_W
During SRP, the pulse time of Vbus. In PHY clock bit12'h2c6
units.
60MHZ:
12'h5b8
Device threshold value control register (DTHRCTL)
Offset: 830h
Field
Note
Reset value
Access
characteristics
31:28
Reserved
RO
27
Arbiter parking enable
1'b1
R_W
26
Reserved
RO
25:17
Receive threshold length (RxThrLen)
9'h8
R_W
16
Receive threshold enable (RxTHrEn)
1'b0
R_W
15:13
Reserved
RO
12:11
AHB threshold ratio (AHBThrRatio)
2'b0
R_W
10:2
Transmit threshold length (TxThrLen)
9'h8
R_W
1
Real-time IN Endpoint Threshold Value Enable1'b0
R_W
(ISOThrEn)
0
Non-real Time IN Endpoint Threshold Value Enable1'b0
R_W
(NonISOThrEn)
Device IN Endpoint FIFO Empty Interrupt Mask Register (DIEPEMPMSK)
Offset: 834h
Field
Note
Reset value
Access
characteristic
s
31:16
Reserved
RO
15:0
IN Endpoint Tx FIFO Empty Interrupt Mask Register
16'b0
R_W
(InEpTxfEmpMsk)
As the interrupt mask bit of DIEPINTn, one bit corresponds
to one endpoint.
-129-
Bit0 corresponds to endpoint 0, and so on.
Device Control IN Endpoint 0 Control Register (DIEPCTL0)
Offset: 900h
Field
Note
Reset value
Access
characteristi
cs
31
End node enable (EPEna)
1'b0
R_WS_SC
Ɣ In Scatter/Gather DMA mode, in terms of IN Endpoint, this
threshold 1 means that the descriptor and data buffer have been
prepared.
Ɣ In non- Scatter/Gather DMA mode, this threshold 1 means
that the data buffer has been prepared.
When OTG sets up the following interrupts, this bit will be
cleared 0.
Ɣ End node failure
Ɣ Transmission completion
30
End node failure (EPDis)
1'b0
R_WS_SC
The software sets the bit to 1, and will stop transmitting data
to this endpoint even if the transfer isn’t finished. The
software must wait that the endpoint valid interrupt happens,
can it think the endpoint has been invalid. When the OTG
controller sets endpoint valid interrupt, clear the bit to 0, and
only when EPEna bit is 1, set the bit to 1.
This domain is valid only in DMA mode.
29:28
Reserved
RO
27
Set NAk (SNAK)
1'b0
WO
Set 1, set the NAK bit corresponding to this endpoint to 1.
26
Clear NAK (CNAK)
1'b0
WO
Set 1, set the NAK bit corresponding to this endpoint to 0.
25:22
TxFIFO number (TxFNum)
4'h0
R_W
Set the FIFO number corresponding to IN endpoint 0.
21
STALL handshake (Stall)
1'b0
R_WS_SC
When receiving SETUP packet, the software sets 1, and
OTG controller clears 0. If NAK bit, global non-periodic IN
NAK and Global OUT NAK bit are all set to 1, the priority
of STALL bit will be the highest.
20
Reserved
RO
19:18
Endpoint type (EPType)
2'h0
RO
For the control node 2'b00
17
NAK status (NAKSts)
1'b0
RO
Ɣ1'b0: Based on FIFO status, OTG controller sends out
Non-NAK handshake.
Ɣ1'b1: OTG controller transmission NAK handshake
16
Reserved
RO
15
USB Active Endpoint (USBActEP)
1'b1
RO
If it has been
1, it means that the control endpoint 0 is
always available.
14:2
Reserved
RO
1:0
The maximum packet size (MPS)
2'h0
R_W
Ɣ2'b00: 64B
Ɣ2'b01: 32B
Ɣ2'b10: 16B
Ɣ2'b11: 8B
Device Control OUT Endpoint 0 Control Register (DIEPCTL0)
-130-
Offset: B00h
Field
Note
Reset
Access
value
characteristics
31
End node enable (EPEna)
1'b0
R_WS_SC
Ɣ In Scatter/Gather DMA mode, in terms of OUT Endpoint, this
threshold 1 means that the descriptor and data buffer have been
prepared to receive data.
Ɣ In non- Scatter/Gather DMA mode, this threshold 1 means that the
data buffer has been prepared.
When OTG sets up the following interrupts, this bit will be
cleared 0.
Ɣ SETUP time phase completion
Ɣ End node failure
Ɣ Transmission completion
In DMA mode, if OTG controller transfers SETUP data packet,
the bit must be set to 1.
30
End node failure (EPDis)
1'b0
RO
The software can’t invalidate OUT control node 0.
29:28
Reserved
RO
27
Set NAk (SNAK)
1'b0
WO
Set 1, set the NAK bit corresponding to this endpoint to 1.
26
Clear NAK (CNAK)
1'b0
WO
Set 1, clear the NAK bit corresponding to this endpoint to 1.
25:22
Reserved
RO
21
STALL handshake
1'b0
R_WS_SC
When receiving SETUP packet, the software sets 1, and OTG
controller clears 0. If NAK bit, global non-periodic IN NAK and
Global OUT NAK bit are all set to 1, the priority of STALL bit
will be the highest. No matter whether this bit is set to 1, the
handshake signal that OTG controller corresponds to SETUP data
packet is always ACK.
20
Snoop mode (Snp)
1'b0
R_W
In snoop mode, when transferring the data to the memory, the
OTG controller doesn’t check the correctness of OUT data
packet.
19:18
Endpoint type (EPType)
2'h0
RO
For the control node 2'b00
17
NAK status (NAKSts)
1'b0
RO
Ɣ1'b0: Based on FIFO status, OTG controller sends out
Non-NAK handshake.
Ɣ1'b1: OTG controller transmission NAK handshake
16
Reserved
RO
15
USB Active Endpoint (USBActEP)
1'b1
RO
If it has been 1, it means that the control endpoint 0 is always
available.
14:2
Reserved
RO
1:0
The maximum packet size (MPS)
2'h0
R_W
Ɣ2'b00: 64B
Ɣ2'b01: 32B
Ɣ2'b10: 16B
Ɣ2'b11: 8B
Device endpoint-n control register (DIEPCTLn/DOEPCTLn)
◆
Endpoint_num: 1 <= n <= 6
◆
Offset for IN: 900h +
(Endpoint_num*20h)
-131-
◆
Offset for OUT: B00h +
(Endpoint_num*20h)
Field
Note
Reset
Access
value
characteristics
31
End node enable (EPEna)
1'b0
R_WS_SC
Applied in IN / OUT terminal nodes.
Ɣ In Scatter/Gather DMA mode, for IN endpoint, this threshold
1 means that the descriptor and data buffer have been prepared;
for OUT endpoint, the threshold 1 means that the descriptor and
data buffer have been prepared to receive data.
Ɣ In Scatter/Gather DMA mode, for IN endpoint, this threshold 1
means that the data buffer have been prepared to send data; for IN
endpoint, the threshold 1 means that the data buffer have been
prepared to receive data.
When OTG sets up the following interrupts, this bit will be
cleared 0.
Ɣ SETUP time phase completion
Ɣ End node failure
Ɣ Transmission completion
30
End node failure (EPDis)
1'b0
R_WS_SC
Applied in IN / OUT endpoint.
The software sets the bit to 1, and will stop transmitting data to
this endpoint even if the transfer isn’t finished. The software
must wait that the endpoint valid interrupt happens, can it think
the endpoint has been invalid. When the OTG controller sets
endpoint valid interrupt, clear the bit to 0, and only when EPEna
bit is 1, set the bit to 1.
29
Set DATA1 PID (SetD1PID)
1'b0
WO
It’s only valid for interrupt/bulk IN and OUT endpoint. 1 is
written in this bit, DPID bit is set to DATA1. It’s valid for both
descriptor DMA and non-descriptor DMA mode.
28
Set DATA0 PID (SetD1PID)
1'b0
WO
It’s only valid for interrupt/bulk IN and OUT endpoint. 1 is
written in this bit, DPID bit is set to DATA0.
It’s valid for both descriptor DMA and non-descriptor DMA
mode.
27
Set NAk (SNAK)
1'b0
WO
Applied in IN / OUT endpoint.
Set 1, set the NAK bit corresponding to this endpoint to 1.
26
Clear NAK (CNAK)
1'b0
WO
Applied in IN / OUT endpoint.
Set 1, clear the NAK bit corresponding to this endpoint to 1.
25:22
TxFIFO number (TxFNum)
4'h0
R_W
Valid only for IN end nodes;
Set the FIFO number corresponding to IN endpoint.
21
STALL handshake
1'b0
R_W
It’s only valid for non-control and non-real time IN/OUT
endpoint. Through the setup of this bit, stall all tokens from the
host. If the NAK bit, global non-periodic NAK and global OUT
NAK bit are all set to 1, the priority of STALL bit is the highest.
No matter whether this bit is set to 1, the handshake signal that
OTG controller corresponds to SETUP data packet is always
ACK.
Valid only for control end nodes.
When receiving SETUP packet, the software is set to 1, and the
OTG controller is cleared 0.
If the NAK bit, global non-periodic NAK and global OUT NAK
-132-
bit are all set to 1, the priority of STALL bit is the highest. No
matter whether this bit is set to 1, the handshake signal that
OTG controller corresponds to SETUP data packet is always
ACK.
20
Snoop mode (Snp)
1'b0
R_W
Valid only for OUT endpoint;
In snoop mode, when transferring the data to the memory, the
OTG controller doesn’t check the correctness of OUT data
packet.
19:18
Endpoint type (EPType)
2'h0
R_W
Ɣ2'b00: Control
Ɣ2'b01: Real time
Ɣ2'b10: Bulk
Ɣ2'b11: Interrupt
17
NAK status (NAKSts)
1'b0
RO
Apply to all IN/OUT endpoints.
Ɣ1'b0: Based on FIFO status, OTG controller sends out
Non-NAK handshake.
Ɣ1'b1: OTG controller transmission NAK handshake
16
End node data PID (DPID)
1'b0
RO
Apply to interrupt/bulk IN and OUT endpoint. Include the PID
of data packet received or sent by this endpoint. After this
endpoint activates, the software must set the PID of the first
packet received or sent by this endpoint. Use the SetD0PID and
SetD1PID domains of this register to set DATA0 or DATA1 PID
Ɣ 1'b0: DATA0
Ɣ 1'b1: DATA1
Odd-even frames (EO_FrNum)
In the non-descriptor DMA mode, apply to the real-time
IN/OUT endpoint. It appoints the frame number used by this
endpoint to send or receive the real-time data. It’s set by the
SetEvnFr and SetOddFr domains of this register.
Ɣ 1'b0: Even frames
Ɣ 1'b1: Odd frames
In the descriptor DMA mode, this domain bit remains the
domain.
15
USB active end nodes
1'b0
R_W_Sc
Applied in IN
/ OUT endpoints. It appoints in current
configuration and interface, whether the endpoint activates.
14:11
Reserved
RO
10:0
The maximum packet size (MPS)
11'b0
R_W
Applied in IN / OUT endpoints. Set the maximum packet size,
in bytes
Device endpoint-n interrupt register (DIEPCTLn / DOEPCTLn)
◆ Endpoint_num: 1 <= n <= 6
◆ Offset for IN: 908h +
(Endpoint_num*20h)
◆ Offset for OUT: B08h +
(Endpoint_num*20h)
Field
Note
Reset value
Access
characteristics
31:15
Reserved
RO
14
NYET interrupt (NYETIntrpt)
1'b0
R_SS_WC
13
NAK interrupt (NAKIntrpt)
1'b0
R_SS_WC
12
Bubble error interrupt (BbleErrIntrpt)
1'b0
R_SS_WC
11
Packet drop status (PktDrpSts)
1'b0
R_SS_WC
-133-
10
Reserved
RO
9
BNA (the buffer can’t be used) interrupt (BNAIntr)
1'b0
R_SS_WC
8
FIFO underflow (TxFifoUndrn)
1'b0
R_SS_WC
7
TxFIFO empty (TxFEmp)
1'b0
R_SS_WC
6
IN endpoint NAK effectiveness (PNakEff)
1'b0
R_SS_WC
5
Receive IN token interrupt mismatching EP
1'b0
R_SS_WC
(INTknEPMis)
4
When TxFIFO is empty and receives IN token interrupt
1'b0
R_SS_WC
(INTknTXFEmp)
3
Overtime interrupt
1'b0
R_SS_WC
(TImeOUT)
Valid only for non-real-time end node
2
AHB error interrupt
1'b0
R_SS_WC
(AHBErr)
1
End nodes failure interrupt
1'b0
R_SS_WC
(EPDisbld)
0
Transmission completion interrupt
1'b0
R_SS_WC
(XferCompI)
Device endpoint 0 transfer size register (DIEPTSIZ0/DOEPTSIZ0)
◆
Offset for IN: 910h
◆
Offset for OUT: B10h
For IN end nodes:
Field
Note
Reset
Access
value
characteristics
31:15
Reserved
RO
20:19
The number of packets (PktCnt)
2'b0
R_W
Indicate the number of packets in the number of transmission
size.
When reading a packet from TxFIFO, this domain decreases 1.
18:7
Reserved domain
7'h0
R_W
6:0
Transmission size
7'h0
R_W
It indicates the transfer size of endpoint 0 (in the unit of byte),
and when it exceeds this value, it will cause interrupt. It can be
set MPS of this end node. Every time one packet is written in
TxFIFO, this domain decreases 1.
For OUT end nodes:
Field
Note
Reset
Access
value
characteristics
31
Reserved
RO
30:29
Number of SETUP packets (SUPPktCnt)
2'b0
R_W
It indicates the number of back-to-back SETUP packet
received by this endpoint.
Ɣ2'b01: One package
Ɣ2'b10: Two packages;
Ɣ2'b11: Three packages;
28:20
Reserved domain
7'h0
R_W
19
The number of packets (PktCnt)
1'b0
R_W
Every time one packet is written into RxFIFO, this domain
decreases to 0.
18:7
Reserved
RO
6:0
Transmission size (XferSize)
7'h0
R_W
-134-
It indicates the transfer size of endpoint 0 (in the unit of byte),
and when it exceeds this value, it will cause interrupt. It can
be set MPS of this end node. When reading a packet from
RxFIFO, this domain decreases 1.
Device endpoint-n transfer size register (DIEPSIZn /DOEPSIZn)
◆
Endpoint_num: 1 <= n <= 6
◆
Offset for IN: 910h +
(Endpoint_num*20h)
◆
Offset for OUT: B10h +
(Endpoint_num*20h)
Field
Note
Reset
Access
value
characteris
tics
31:29
Reserved
RO
30:29
MC (MultiCount)
2'b0
R_W
Valid only for IN end nodes.
For the periodic IN endpoint, this domain indicates the number of
packets transferred within one microFrame time. OTG controller
uses this domain as the real-time IN endpoint to calculate the data
PID.
Ɣ2'b01: One package;
Ɣ2'b10: Two packages;
Ɣ2'b11: Three packages;
For non-periodic IN endpoint, it indicates OTG controller must be
the number of packets obtained by this endpoint, when transferred
to the next endpoint appointed by DIEPCTLn.Nextep.
RxPID (received data PID) is only valid for the real-time OUT
endpoint, the data PID of the last packet received by this endpoint.
Ɣ2'b00: DATA0
Ɣ2'b01: DATA2
Ɣ2'b10: DATA1;
Ɣ2'b11: MDATA;
SETUP packets (SUPCnt)
It’s only valid for controlling OUT endpoint, indicating the number
of back-to-back SETUP packets received by this endpoint.
Ɣ2'b01: One package
Ɣ2'b10: Two packages;
Ɣ2'b11: Three packages;
28:19
The number of packets (PktCnt)
10'h0
R_W
It indicates the packet count under this transfer size
(PktCnt =
XferSize/MPS)
ƔIN endpoint: when one packet is read in TxFIFO, this domain
reduces 1.
ƔOUT endpoint: when one packet is written in RxFIFO, this domain
reduces 1.
18:0
Transmission size (XferSize)
19'b0
R_W
Indicate the transfer size of the endpoint (in the unit of byte)
ƔWhen reading a packet from RxFIFO, this domain decreases 1.
Ɣ Every time one packet is written in TxFIFO, this domain decreases 1.
Device endpoint-n DMA address register (DIEPDMAn/DOEPDMAn)
◆
Endpoint_num: 1 <= n <= 6
◆
Offset for IN: 914h +
(Endpoint_num*20h)
-135-
◆
Offset for OUT: B14h +
(Endpoint_num*20h)
Field
Note
Reset value
Access
characteristics
31:0
DMA address (DMAAddr)
X
R_W
Save the initial address of external storage allocated to
this endpoint.
Ɣ In non- Scatter/Gather DMA mode, it’s the initial
address.
Ɣ In Scatter/Gather DMA mode, it’s the base address of
the descriptor table
Device endpoint-n DMA Buffer Address Register (DIEPDMABn/DOEPDMABn)
◆
Endpoint_num: 1 <= n <= 6
◆
Offset for IN: 91Ch +
(Endpoint_num*20h)
◆
Offset for OUT: B1Ch +
(Endpoint_num*20h)
Field
Note
Reset value
Access
characteristics
31:0
DMA Buffer Address (DMABufferAddr)
X
RO
Save current buffer address. When the data is transferring in
this endpoint, the address will be updated in real time.
Valid only in Scatter/Gather DMA mode.
Device IN Endpoint- nTxFIFO status register (DTXSTSn)
◆
Endpoint_num: 1 <= n <= 6
◆
Offset918h +
(Endpoint_num*20h)
Field
Note
Reset value
Access
characteristics
31:16
Reserved
RO
[15:0]
IN endpoint TxFIFO space available
RO
(INEPTxFSpcAvail)
32 bytes as unit.
Ɣ16'h0: End node TxFIFO full
Ɣ16'h1: One word available
。。。
Ɣ16'hn: N words available
ƔOthers: Reserved
13.3.5 Power consumption and clock gating register
Power consumption and gating of clock control register （PCGCCTL）
◆
OffsetE00h
Field
Note
Reset
Access
value
characteristics
31:9
Reserved
RO
8
Reset after suspended (ResetAfterSusp)
1'b1
R_W
If the host needs to reset after suspended, the soft needs to set this
bit to 1 before clearing the clamp. If this bit isn’t set to 1, the host
will send out the reset signal after suspended.
7
Deep sleep (L1 Suspended)
1'b0
RO
In L1 status, PHY enters into the deep sleep
6
PHY sleep (PhySleep)
1'b0
RO
-136-
PHY into sleep status.
5
Enable the sleep gating (Enbl_L1Gating)
1'b0
R_W
If the OTG controller can’t set the bit to utmi_l1_suspend_n, after
the bit setup, the gating can’t apply to the internal clock in deep
sleep
4
Reserved
RO
3
Reset power-down module (RstPdwnModule)
1'b0
R_W
In power-off, the software sets 1, and after power-on and PHY
clock recovers, the software clear 0.
2
Power supply isolation (PwrClmp)
1'b0
R_W
Before power off, the software sets the bit to 1 to isolate the
power-on and power-off modules. Clear software to zero before
power on
1
Gating Hclk (GateHclk)
1'b0
R_W
It sets 1, when the USB in suspended state, use gating clock to
Hclk. When the USB recovers or the new dialogue starts, the
software clears 0.
0
Stop Pclk (StopPclk)
1'b0
R_W
When the bit is set to 1, if the USB is under the suspended state,
stop PHY clock. When the USB recovers or the new dialogue
starts, the software clears 0.
-137-