LoongArch Reference Manual. Volume 1: Basic Architecture (Version 1.02) - page 6
Figure 5. Floating-point Registers
When the floating-point register records a single-precision floating-point number or word integer, the data
always appears in the [31:0] bits of the floating-point register, at this time the [63:32] bits of the
floating-point register can be any value.
3.1.3.2. Condition Flag Register
There are 8 CFRs, denoted as fcc0-fcc7, each of which can be read and written. The length of CFR is 1 bit.
The result of the floating-point comparison will be written into the condition flag register. When the
comparison result is true, it is set to 1, otherwise it is set to 0. The judgment condition of the floating-point
branch instruction comes from the condition register.
3.1.3.3. Floating-point Control and Status Register
There are 4 FCSRs, denoted as fcsr0-fcsr3. Among them, fcsr1-fcsr3 are aliases of some fields in
fcsr0, that is, accessing fcsrl-fcsr3 is actually accessing some fields of fcsr0. When the software
writes fcsr1-fcsr3, the corresponding field in fcsr0 is modified while the remaining bits remain
unchanged. The definition of each field of fcsr0 is shown in the table.
Table 6. Definitions of FCSR0 Register Fields
Bits
Name
Read&writ
Description
e
Enables
RW
4:0
The floating-point operation VZOUI exceptions each allow the enable
bit to trigger the exception trap.
Bit 4 corresponds to V, bit 3 corresponds to Z, bit 2 corresponds to O,
bit 1 corresponds to U, and bit 0 corresponds to I.
RM
RW
Rounding mode control. It contains 4 legal values, each with the
9:8
following meaning:
0: RNE, corresponding to roundTiesToEven in IEEE 754-2008;
1: RZ, corresponding to roundTowardZero in IEE 754-2008;
2: RP, corresponding to roundTowardsPositive in IEEE 754-2008;
3: RM, corresponding to roundTowardsNegative in IEEE 754-2008.
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Bits
Name
Read&writ
Description
e
Flags
RW
Since the last time the Flags field was cleared by the software, the
20:16
cumulative status of various floating-point operations VZOUI
exceptions that were generated but not caught.
Bit 20 corresponds to V, bit 19 corresponds to Z, bit 18 corresponds
to O, bit 17 corresponds to U, and bit 16 corresponds to I.
Cause
RW
28:24
The VZOUI exception caused by the last floating-point operation.
Bit 28 corresponds to V, bit 27 corresponds to Z, bit 26 corresponds
to O, bit 25 corresponds to U, and bit 24 corresponds to I.
FCSR1 is the alias of the Enables field in FCSR0. Its location is the same as in FCSR0.
FCSR2 is the alias of the Cause and Flags fields in FCSR0. The location of each field is consistent with
FCSR0.
FCSR3 is the alias of the RM field in FCSR0. Its location is the same as in FCSR0.
3.1.4. Floating-Point Exceptions
Floating-point exception means that when the floating-point processing unit cannot process the operand or
the result of floating-point calculation in a conventional manner, the floating-point functional unit will
generate a corresponding exception.
The basic floating-point instructions support five floating-point exceptions defined by IEEE 754-2008:
•
Inexact (I)
•
Underflow (U)
•
Overflow (O)
•
Division by Zero (Z)
•
Invalid Operation (V)
Each bit of the Cause field in FCSR0 corresponds to the above-mentioned exceptions. After the execution
of each floating-point instruction, the occurrence of its exception will be updated to the Cause field of
FCSR0.
FCSR0 also contains an enable bit (Enables field) for each floating-point exception. The enable bit
determines whether an exception generated by the floating-point processing unit will trigger an exception
trap or set a status flag. When a floating-point exception occurs, if its corresponding Enable bit is 1, then a
floating-point exception trap will be triggered; if its corresponding Enable bit is 0, then the floating-point
exception trap will not be triggered, but Set the corresponding position of the Flag field in FCSR0 to 1.
During the execution of a floating-point instruction, multiple floating-point exceptions can be generated at
the same time.
When a floating-point exception is generated during the execution of a floating-point instruction but the
floating-point exception is not triggered, the floating-point processing unit will generate a default result.
Different exceptions produce default results in different ways. The table lists specific generation rules.
Table 7. Default results of floating-point exceptions
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Area
Descriptio
Rounding
Default result
n
mode
Inexact
Any mode
The result after rounding or the result after overflow
I
Underflow
RNE
U
The result after rounding may be 0, subnormal, the normal number
with the smallest absolute value (single-precision: ±2-126, double-
precision: ±2-1022)
RZ
The result after rounding, may be 0, subnormal
RP
The rounded result may be 0, subnormal, the smallest positive normal
number (single-precision: +2-126, double-precision: +2-1022)
RM
The rounded result may be 0, subnormal, the largest negative normal
number (single-precision: -2-126, double-precision: -2-1022)
Overflow
RNE
O
Set the result to +∞ or -∞ according to the sign of the intermediate
result
RZ
Set the result to the maximum number according to the sign of the
intermediate result
RP
Correct negative overflow to the smallest negative number, and
correct positive overflow to +∞
RM
Correct the positive overflow to the largest positive number, and
correct the negative overflow to -∞
Division by
Any mode
Provide a corresponding signed infinity number
Z
Zero
InValid
Any mode
Provide a QNaN
V
Operation
3.1.4.1. Illegal Operation Exception (V)
An invalid operation exception notification signal will be sent if and only if there is no valid defined result. If
no exception is triggered, a QNaN will be generated. Please refer to Characteristics of Accessing Control
and Status Registers of the IEEE 754-2008 specification for specific determination details of extraordinary
operation exceptions.
If an exception is allowed to fall into: the result register is not modified, the source register remains.
If exceptions are prohibited from trapping: If no other exceptions occur, QNaN is written to the target
register.
3.1.4.2. Division by Zero Exception (Z)
In the division operation, when the divisor is 0 and the dividend is-a limited non-zero data, the division by
zero exception is signaled.
If an exception is allowed to fall into: the result register is not modified, the source register remains
If an exception is forbidden to fall into: if no trap occurs, the result is a signed infinite value.
3.1.4.3. Overflow Exception (O)
Regarding the exponent field as an unbounded rounding of the intermediate result, when the absolute value
of the result obtained exceeds the maximum finite number of the target format, an overflow exception will
be notified.(This exception sets both inexact exception and flag bit)
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If an exception is allowed to fall into: the result register is not modified, the source register remains.
If exceptions are forbidden to fall into: If no trap occurs, the final result is determined by the rounding mode
and the sign of the intermediate result.
3.1.4.4. Underflow Exception (U)
When the detection result is a small non-zero value, an underflow exception will occur. The way to detect
small non-zero values is to detect after rounding. that is, for a non-zero result is in (-2Emin,
2Emin), the
result is considered to be a small non-zero value (Single-precision number Emin=-126, double-precision
number Emin=-1022). When FCSR.Enable.U=0, if the result is detected, a non-zero tiny value:
1.
If the final rounded result of the floating-point operation is inaccurate, both U and I in FCSR.Cause
should be set to 1;
2.
If the final rounded result of the floating-point operation is accurate, then U and I in FCSR.Cause are
not set to 1.
When FCSR.Enable.U=1, if the result is a non-zero tiny value, regardless of whether the final rounded
result of the floating-point operation is accurate or inaccurate, it will trigger a floating-point exception trap.
3.1.4.5. Inexact Exception (I)
FPU generates inaccurate exceptions when the following situations occur:
• Rounding result is imprecise.
• The rounding result overflows, and the enable bit of the overflow exception is not set.
If an exception is allowed to fall: If an inexact exception trap is enabled, the result register is not modified
and the source register is retained. Because this execution mode affects performance, inaccurate
exception traps are only enabled when necessary.
If an exception is prohibited, trapping is prohibited: If no other software trap occurs, the rounding or
overflow result is sent to the destination register.
3.2. Overview of Floating-Point Instructions
The instructions described in this section, except for FLDX.{S/D}, FSTX.{S/D}, FLD{GT/LE}.{S/D}
and FST{GT/LE}.{S/D} these 12 The floating-point memory access instructions only belong to the LA64,
and all other floating-point instructions are applicable to both LA32 and LA64.
3.2.1. Floating-Point Arithmetic Operation Instructions
3.2.1.1. F{ADD/SUB/MUL/DIV}.{S/D}
Instruction formats:
fadd.s
fd, fj, fk
fadd.d
fd, fj, fk
fsub.s
fd, fj, fk
fsub.d
fd, fj, fk
fmul.s
fd, fj, fk
fmul.d
fd, fj, fk
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fdiv.s
fd, fj, fk
fdiv.d
fd, fj, fk
The FADD.{S/D} instruction performs the operation that the single-precision/double-precision floating-
point number in the floating-point register fj plus the single-precision/double-precision floating-point
number in the floating-point register fk; then writes the result of the single-precision/double-precision
floating-point number to floating-point register fd. Floating-point addition operation follows the
specification of addition(x,y) operation in the IEEE 754-2008 standard.
FADD.S:
FR[fd][31:0] = FP32_addition(FR[fj][31:0], FR[fk][31:0])
FADD.D:
FR[fd] = FP64_addition(FR[fj], FR[fk])
The FSUB.{S/D} instruction performs the operation that the single-precision/double-precision floating-
point number in the floating-point register fj minus the single-precision/double-precision floating-point
number in the floating-point register fk, and write the result of the single-precision/double-precision
floating-point number to floating-point register fd. The floating-point subtraction operation follows the
subtraction(xy) operation specification in the IEEE 754-2008 standard.
FSUB.S:
FR[fd][31:0] = FP32_subtraction(FR[fj][31:0], FR[fk][31:0])
FSUB.D:
FR[fd] = FP64_subtraction(FR[fj], FR[fk])
The FMUL.{S/D} instruction performs the operation that multiplies the single-precision/double-precision
floating-point number in the floating-point register fj by the single-precision/double-precision floating-
point number in the floating-point register fk, and writes the result of the single-precision/double-precision
floating-point number To the floating-point register fd. The floating-point multiplication operation follows
the multiplication(xy) operation specification in the IEE 754-2008 standard.
FMUL.S:
FR[fd][31:0] = FP32_multiplication(FR[fj][31:0], FR[fk][31:0])
FMUL.D:
FR[fd] = FP64_multiplication(FR[fj], FR[fk])
The FDIV.{S/D} instruction performs the operation that divides the single-precision/double-precision
floating-point number in the floating-point register fj by the single-precision/double-precision floating-
point number in the floating-point register fk, and writes the result of the single-precision/double-precision
floating-point number To the floating-point register fd. The floating-point division operation follows the
division(x, y) operation specification in the IEEE 754-2008 standard.
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FDIV.S:
FR[fd][31:0] = FP32_division(FR[fj][31:0], FR[fk][31:0])
FDIV.D:
FR[fd] = FP64_division(FR[fj], FR[fk])
When the operand is a single-precision floating-point number, the upper 32 bits of the resulting floating-
point register can be any value.
3.2.1.2. F{MADD/MSUB/NMADD/NMSUB}.{S/D}
Instruction formats:
fmadd.s
fd,fj,fk,fa
fmadd.d
fd,fj,fk,fa
fmsub.s
fd,fj,fk,fa
fmsub.d
fd,fj,fk,fa
fnmadd.s
fd,fj,fk,fa
fnmadd.d
fd,fj,fk,fa
fnmsub.s
fd,fj,fk,fa
fnmsub.d
fd,fj,fk,fa
The FMADD.{S/D} instruction performs the operation that multiplies the single-precision/double-precision
floating point number in floating point register fj with the single-precision/double-precision floating point
number in floating point register fk. The result is added to the single-precision/double-precision floating
point number in the floating point register fa. The result of the single-precision/double-precision floating
point number is written to the floating point register fd
FMADD.S:
FR[fd][31:0] = FP32_fusedMultiplyAdd(FR[fj][31:0], FR[fk][31:0],
FR[fa][31:0])
FMADD.D:
FR[fd] = FP64_fusedMultiplyAdd(FR[fj], FR[fk], FR[fa])
The FMSUB.{S/D} instruction performs the operation that multiplies the single-precision/double-precision
floating-point number in the floating-point register fj with the single-precision/double-precision floating-
point number in the floating-point register fk, the result minus the floating-point register fa Single-
precision/double-precision floating-point numbers, the single-precision/double-precision floating-point
number results obtained are written into the floating-point register fd.
FMSUB.S:
FR[fd][31:0] = FP32_fusedMultiplyAdd(FR[fj][31:0], FR[fk][31:0],
-FR[fa][31:0])
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FMSUB.D:
FR[fd] = FP64_fusedMultiplyAdd(FR[fj], FR[fk], -FR[fa])
The FNMADD.{S/D} instruction performs the operation that multiplies the single-precision/double-
precision floating-point number in the floating-point register fj with the single-precision/double-precision
floating-point number in the floating-point register fk, the result plus the single-precision/double-precision
floating-point number in the floating-point register fa Precision/double-precision floating-point number, the
obtained single-precision/double-precision floating-point number result is negative and written into the
floating-point register fd.
FNMADD.S:
FR[fd][31:0] = -FP32_fusedMultiplyAdd(FR[fj][31:0], FR[fk][31:0],
FR[fa][31:0])
FNMADD.D:
FR[fd] = -FP64_fusedMultiplyAdd(FR[fj], FR[fk], FR[fa])
The FNMSUB.{S/D} instruction performs the operation that multiplies the single-precision/double-
precision floating-point number in the floating-point register fj with the single-precision/double-precision
floating-point number in the floating-point register fk, the result minus the floating-point register fa Single-
precision/double-precision floating-point number, the result of the single-precision/double-precision
floating-point number obtained is negative and written into the floating-point register fd.
FNMSUB.S:
FR[fd][31:0] = -FP32_fusedMultiplyAdd(FR[fj][31:0], FR[fk][31:0],
-FR[fa][31:0])
FNMSUB.D:
FR[fd] = -FP64_fusedMultiplyAdd(FR[fj], FR[fk], -FR[fa])
The above four floating-point fusion multiply-add operations follow the specification of the
fusedMultiplyAdd(xy,z) operation in the IEEE 754-2008 standard.
3.2.1.3. F{MAX/MIN}{S/D}
Instruction formats:
fmax.s
fd, fj, fk
fmax.d
fd, fj, fk
fmin.s
fd, fj, fk
fmin.d
fd, fj, fk
The FMAX.{S/D} instruction selects the larger of the single-precision/double-precision floating-point
number in the floating-point register fj and the single-precision/double-precision floating-point number in
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the floating-point register fk to write into the floating-point register fd. The operation of these two
instructions follows the specification of maxNum(x,y) operation in the IEEE 754-2008 standard.
FMAX.S:
FR[fd][31:0] = FP32_maxNum(FR[fj][31:0], FR[fk][31:0])
FMAX.D:
FR[fd] = FP64_maxNum(FR[fj], FR[fk])
The FMIN.{S/D} instruction selects the smaller of the single-precision/double-precision floating-point
number in the floating-point register fj and the single-precision/double-precision floating-point number in
the floating-point register fk to write into the floating-point register fd. The operation of these two
instructions follows the minNum(x,y) operation specification in the IEEE 754-2008 standard.
FMIN.S:
FR[fd][31:0] = FP32_minNum(FR[fj][31:0], FR[fk][31:0])
FMIN.D:
FR[fd] = FP64_minNum(FR[fj], FR[fk])
3.2.1.4. F{MAXA/MINA}.{S/D}
Instruction formats:
fmaxa.s
fd, fj, fk
fmaxa.d
fd, fj, fk
fmina.s
fd, fj, fk
fmina.d
fd, fj, fk
The FMAXA.{S/D} instruction selects the larger absolute value of the single-precision/double-precision
floating-point number in the floating-point register fj and the single-precision/double-precision floating-
point number in the floating-point register fk to write to the floating-point register fd. The floating-point
addition operation follows the specification of maxNumMag(x.v) operation in IEEE 754-2008 standard.
FMAXA.S:
FR[fd][31:0] = FP32_maxNumMag(FR[fj][31:0], FR[fk][31:0])
FMAXA.D:
FR[fd] = FP64_maxNumMag(FR[fj], FR[fk])
The FMINA.{S/D} instruction selects the smaller absolute value of the single-precision/double-precision
floating-point number in the floating-point register fj and the single-precision/double-precision floating-
point number in the floating-point register fk to write to the floating-point register fd. The floating-point
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addition operation follows the specification of minNumMag(x,y) operation in IEEE 754-2008 standard.
FMINA.S:
FR[fd][31:0] = FP32_minNumMag(FR[fj][31:0], FR[fk][31:0])
FMINA.D:
FR[fd] = FP64_minNumMag(FR[fj], FR[fk])
3.2.1.5. F{ABS/NEG}.{S/D}
Instruction formats:
fabs.s
fd, fj
fabs.d
fd, fj
fneg.s
fd, fj
fneg.d
fd, fj
The FABS.{S/D} instruction selects the single-precision/double-precision floating-point number in the
floating-point register fj, takes its absolute value(that is, the symbol position is 0, and other parts remain
unchanged), and writes it into the floating-point register fd. Floating-point addition operations follow the
specification of abs(x) operation in the EEE 754-2008 standard.
FABS.S:
FR[fd][31:0] = FP32_abs(FR[fj][31:0])
FABS.D:
FR[fd] = FP64_abs(FR[fj])
The FNEG.{S/D} instruction selects the single-precision/double-precision floating-point number in the
floating-point register fj, takes the opposite number(that is, inverts the sign bit, and other parts remain
unchanged), and writes it into the floating-point register fd. Floating-point addition operations follow the
negate(x) operation specification in the EEE 754-2008 standard.
FNEG.S:
FR[fd][31:0] = FP32_negate(FR[fj][31:0])
FNEG.D:
FR[fd] = FP64_negate(FR[fj])
3.2.1.6. F{SQRT/RECIP/RSQRT}.{S/D}
Instruction formats:
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fsqrt.s
fd, fj
fsqrt.d
fd, fj
frecip.s
fd, fj
frecip.d
fd, fj
frsqrt.s
fd, fj
frsqrt.d
fd, fj
These instructions are operations related to square root and reciprocal.
The FSQRT.{S/D} instruction selects the single-precision/double-precision floating-point number in the
floating-point register fj, and writes the single-precision/double-precision floating-point number obtained
after the square root to the floating-point register fd. The floating-point root operation follows the
squareRoot(x) operation specification in the IEEE 754-2008 standard.
FSQRT.S:
FR[fd][31:0] = FP32_squareRoot(FR[fj][31:0])
FSQRT.D:
FR[fd] = FP64_squareRoot(FR[fj])
The FRECIP.{S/D} instruction selects the single-precision/double-precision floating-point number in the
floating-point register fj, divides the floating-point number by
1.0, and writes the resulting single-
precision/double-precision floating-point number into the floating-point register fd. It is equivalent to the
division(1.0, x) operation in the IEEE 754-2008 standard.
FRECIP.S:
FR[fd][31:0] = FP32_division(1.0,FR[fj][31:0])
FRECIP.D:
FR[fd] = FP64_division(1.0,FR[fj])
The FRSQRT.{S/D} instruction selects the single-precision/double-precision floating-point number in the
floating-point register fj, takes its square root and then divides the obtained single-precision/double-
precision floating-point number by 1.0, and the obtained single-precision/double-precision floating-point
number is written to the floating-point register fd. The floating-point squared-inverse operation follows the
specification of rSqrt(x) operation in IEEE 754-2008 standard.
FRSQRT.S:
FR[fd][31:0] = FP32_division(1.0, FP_squareRoot(FR[fj][31:0]))
FRSQRT.D:
FR[fd] = FP64_division(1.0, FP_squareRoot(R[fj]))
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3.2.1.7. F{SCALEB/LOGB/COPYSIGN}.{S/D}
Instruction formats:
fscaleb.s
fd, fj, fk
fscaleb.d
fd, fj, fk
flogb.s
fd, fj
flogb.d
fd, fj
fcopysign.s
fd, fj, fk
fcopysign.d
fd, fj, fk
The FSCALEB.{S/D} instruction selects the single-precision/double-precision floating point number a in
the floating point register fj, Then take the word/double word integer N in the floating point register fk,
and calculate a*2N, The obtained single-precision/double-precision floating point number is written to the
floating point register fd. These two instructions follow the IEEE754-2008 standard scaleB(x, N)
operation specification.
FSCALEB.S:
FR[fd][31:0] = FP32_scaleB(FR[fj][31:0], FR[fk][31:0])
FSCALEB.D:
FR[fd] = FP64_scaleB(FR[fj], FR[fk])
The FLOGB.{S/D} instruction selects the single-precision/double-precision floating-point number in the
floating-point register fj, calculates its logarithm based on
2, and writes the obtained single-
precision/double-precision floating-point number into the floating-point register fd . Floating-point
exponential operations follow the specification of logB(x) operation in the IEEE 754-2008 standard.
FLOGB.S:
FR[fd][31:0] = FP32_logB(FR[fj][31:0])
FLOGB.D:
FR[fd] = FP64_logB(FR[fj])
The FCOPYSIGN.{S/D} instruction selects the single-precision/double-precision floating-point number in
the floating-point register fj, and changes its sign bit to the sign bit of the single-precision/double-
precision floating-point number in the floating-point register fk, and the new one is obtained Single-
precision/double-precision floating-point numbers are written into the floating-point register fd. The
floating-point copy sign operation follows the specification of copySign(x, y) operation in the IEEE 754-
2008 standard.
FCOPYSIGN.S:
FR[fd][31:0] = FP32_copySign(FR[fi][31:01, FR[fk][31:0]])
FCOPYSIGN.D:
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FR[fd] = FP64_copySign(FR[fj], FR[fk])
3.2.1.8. FCLASS.{S/D}
Instruction formats:
fclass.s
fd, fj
fclass.d
fd, fj
This instruction judges the category of the floating-point number in the floating-point register fj. The result
of the judgment is composed of 10 bits of information. The meaning of each bit is shown in the following
table:
Table 8. Results of floating-point classification
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
SNaN
QNaN
Negative value
Positive value
Normal
Subnorm
Normal
Subnorm
∞
0
∞
0
al
al
When the determined data meets the condition corresponding to a certain bit, the corresponding bit of the
result information vector will be set to 1. This instruction corresponds to the class(x) function in the
IEEE-754-2008 standard.
FCLASS.S:
FR[fd][31:0] = FP32_class(FR[fj][31:0])
FCLASS.D:
FR[fd] = FP64_class(FR[fj])
sedMultiplyAdd(FR[fj], FR[fk], FR[fa])
3.2.2. Floating-Point Comparison Instructions
3.2.2.1. FCMP.cond.{S/D}
Instruction formats:
fcmp.cond.s
cc, fj, fk
fcmp.cond.d
cc, fj, fk
This is a floating-point comparison instruction, which stores the result of the comparison into the specified
status code (CC). There are 22 types of cond for this instruction. These comparison conditions and
judgment standards are listed in the following table.
Table 9. Floating-point comparison conditions and judgment standards
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Mnemoni
Cond
Meaning
True
QNaN
IEEE 754-2008 Funtion
c
Conditio
Exceptio
n
n
None
None
No
CAF
0x0
Incomparable
CUN
0x8
UN
compareQuietUnordered
Equal
CEQ
0x4
EQ
compareQuietEqual
Equal or
CUEQ
0xC
UN EQ
incomparable
Less than
CLT
0x2
IT
compareQuietLess
Less than or
CULT
0xA
UN LT
compareQuietLessUnordered
incomparable
Less than or equal
CLE
0x6
LT EQ
compareQuietLessEqual
to
Less than or equal
CULE
0xE
UN LT
compareQuietNotGreater
to or incomparable
EQ
Vary
CNE
0x10
GT LT
Orderly
COR
0x14
GT LT
EQ
Incomparable or
CUNE
0x18
UN GT
compareSignalingNotEqual
unequal
LT
None
None
Yes
SAF
0x1
Is not greater than
SUN
0x9
UN
or equal to
equal
SEQ
0x5
EQ
compareSignalingEqual
Not greater than or
SUEQ
0xD
UN EQ
less than
Less than
SLT
0x3
IT
compareSignalingLess
Is not greater than
SULT
0xB
UN LT
compareSignalingLessUnordered
or equal to
Less than or equal
SLE
0x7
IT EQ
compareSignalingLessEqual
to
Not greater than
SULE
0xF
UN LT
compareSignalingNotGreater
EQ
Vary
SNE
0x11
GT LT
Orderly
SOR
0x15
GT LT
EQ
Incomparable or
SUNE:
0x19
UN GT
unequal
LT
Note: UN means no comparison, EQ means equal, IT means less than. When there is at least one NaN in
two operands, the two numbers cannot be compared.
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3.2.3. Floating-Point Conversion Instructions
3.2.3.1. FCVT.S.D, FCVT.D.S
Instruction formats:
fcvt.s.d
fd, fj
fcvt.d.s
fd, fj
The FCVT.S.D instruction performs the operation that the double-precision floating-point number in the
floating-point register fj to be converted into a single-precision floating-point number, and the obtained
single-precision floating-point number is written into the floating-point register fd.
FCVT.S.D:
FR[fd][31:0] = FP32_convertFormat(FR[fj], FP64)
The FCVT.D.S instruction performs the operation that the single-precision floating-point number in the
floating-point register fj to be converted into a double-precision floating-point number, and the obtained
double-precision floating-point number is written into the floating-point register fd.
FCVT.D.S:
FR[fd] = FP64_convertFormat(FR[fj][31:0], FP32)
The floating-point format conversion operation follows the specification of the convertFormat(x)
operation in the IEEE 754-2008 standard.
3.2.3.2. FFINT{S/D}.{W/L}, FTINT.{W/L}.{S/D}
Instruction formats:
ffint.s.w
fj
ffint.s.I
fj
ffint.d.w
fj
ffint.d.I
fj
ftint.w.s
fj
ftint.w.d
fj
ftint.l.s
fj
ftint.l.d
fj
The FFINT{S/D}.{W/L} instruction selects the integer/long-integer fixed-point number in the floating-
point register fj and converts it into a single-degree/double-precision floating-point number, and the
obtained single-precision/double-precision floating-point number is written to Floating-point register fd.
This floating-point format conversion operation follows the convertFromInt(x) operation specification
in the EEE 754-2008 standard.
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FFINT.S.W:
FR[fd][31:0] = FP32_convertFromInt(FR[fj][31:0], SINT32)
FFINT.S.L:
FR[fd][31:0] = FP32_convertFromInt(FR[fj], SINT64)
FFINT.D.W:
FR[fd] = FP64_convertFromInt(FR[fj][31:0], SINT32)
FFINT.D.L:
FR[fd] = FP64_convertFromInt(FR[fj], SINT64)
FTINT{W/L}.{S/D} instruction selects the single-degree/double-precision floating-point number in the
floating-point register fj to be converted into an integer/long-integer fixed-point number, and the obtained
integer/long-integer fixed-point number is written To the floating-point memory fd. According to the
different states in FCSR, the operations in the IEEE 754-2008 standard followed by this floating-point format
conversion operation are shown in the following table.
Table 10. Standard for converting to integer
Rounding mode
Whether to report
IEEE 754-2008 Function
floating-point
imprecision exceptions
Round to the nearest
Yes
convertToIntegerTiesToEven(X)
even number
Round towards zero
convertToIntegerTowardZero(x)
Round towards positive
convertToIntegerTowardPositive(x)
infinity
Round towards negative
converrtToIntegerTowardNegative(x)
infinity
Round to the nearest
No
convertToIntegerExactTiesToEven(x)
even number
Round towards zero
convertToIntegerExactTowardZero(x)
Round towards positive
convertToIntegerExactTowardPositive(x)
infinity
Round towards negative
convertToIntegerExactTowardNegative(x)
infinity
FTINT.W.S:
FR[fd][31:0] = FP32convertToSint32(FR[fj][31:0], FCSR.Enables.I,
FCSR.RM)
FTINT.W.D:
FR[fd] = FP64convertToSint32(FR[fj], FCSR.Enables.I, FCSR.RM)
FTINT.L.S:
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