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MASKEQZ and MASKNEZ instructions perform conditional assignment operations. When MASKEQZ is
executed, if the value of the general register rk is equal to 0, the general register rd is set to 0, otherwise it
is assigned to the value of the rj register.
MASKEQZ:
GR[rd] = (GR[rk] == 0) ? 0 : GR[rj]
When MASKNEZ is executed, if the value of the general register rk is not equal to 0, the general register rd
is set to 0, otherwise it is assigned to the value of the rj register.
MASKNEZ:
GR[rd] = (GR[rk] != 0) ? 0 : GR[rj]
2.2.4. Branch Instructions
2.2.4.1. BEQ, BNE, BLT[U], BGE[U]
Instruction formats:
beq
rj, rd, offs16
bne
rj, rd, offs16
blt
rj, rd, offs16
bge
rj, rd, offs16
bltu
rj, rd, offs16
bgeu
rj, rd, offs16
The BEQ instruction performs the operation that compares the values of general register rj and general
register rd, if the two are equal, jump to the target address, otherwise it does not jump.
BEQ:
if GR[rj] == GR[rd]:
PC = PC + SignExtend({offs16, 2'b0}, GRLEN)
The BNE instruction performs the operation that compares the values of general register rj and general
register rd, if the two are not equal, jump to the target address, otherwise it does not jump.
BNE:
if GR[rj] != GR[rd]:
PC = PC + SignExtend({offs16, 2'b0}, GRLEN)
The BLT instruction performs the operation that compares the values of general register rj and general
register rd as signed numbers. If the former is smaller than the latter, it jumps to the target address,
37
otherwise it does not jump.
BLT:
if signed(GR[rj]) < signed(GR[rd]):
PC = PC + SignExtend({offs16, 2'b0}, GRLEN)
The BGE instruction performs the operation that compares the values of general register rj and general
register rd as signed numbers. If the former is greater than or equal to the latter, it jumps to the target
address, otherwise it does not jump.
BGE:
if signed(GR[rj]) >= signed(GR[rd]):
PC = PC + SignExtend({offs16, 2'b0}, GRLEN)
The BLTU instruction performs the operation that compares the values of general register rj and general
register rd as unsigned numbers. If the former is less than the latter, it jumps to the target address,
otherwise it does not jump.
BLTU:
if unsigned(GR[rj]) < unsigned(GR[rd]):
PC = PC + SignExtend({offs16, 2'b0}, GRLEN)
The BGEU instruction performs the operation that compares the values of general register rj and general
register rd as unsigned numbers. If the former is greater than or equal to the latter, it jumps to the target
address, otherwise it does not jump.
BGEU:
if unsigned(GR[rj]) >= unsigned(GR[rd]):
PC = PC + SignExtend({offs16, 2'b0}, GRLEN)
The calculation method of the jump target address of the above-mentioned six branch instructions is to
logically shift the 16-bit immediate offs16 in the instruction code by 2 bits and then sign expand, and the
resulting offset value is added to the PC of the branch instruction.
When writing assembly, you need to fill in the immediate field with the real offset value in
TIP
bytes, i.e. (offs16<<2).
2.2.4.2. BEQZ, BNEZ
Instruction formats:
beqz
rj, offs21
bnez
rj, offs21
38
The BEQZ instruction performs the operation that judges the value of the general register rj, if it is equal to
0, jump to the target address, otherwise it does not jump.
BEQZ:
if GR[rj] == 0:
PC = PC + SignExtend({offs21, 2'b0}, GRLEN)
The BNEZ instruction performs the operation that judges the value of the general register rj, if it is not
equal to 0, it jumps to the target address, otherwise it does not jump.
BNEZ:
if GR[rj] != 0:
PC = PC + SignExtend({offs21, 2'b0}, GRLEN)
The jump target address of the above two branch instructions is to logical left shift the 21-bit immediate
offs21 in the instruction code by 2 bits and then sign extension, and the resulting offset value is added to
the PC of the branch instruction.
When writing assembly, you need to fill in the immediate field with the real offset value in
TIP
bytes, i.e. (offs21<<2).
2.2.4.3. B
Instruction formats:
b
offs26
The B instruction performs the operation that jumps to the target address unconditionally. The jump target
address is to logical left shift the 26-bit immediate offs26 in the instruction code by 2 bits and then sign
extension, and the resulting offset value is added to the PC of the branch instruction.
B:
PC = PC + SignExtend({offs26, 2' b0}, GRLEN)
When writing assembly, you need to fill in the immediate field with the real offset value in
TIP
bytes, i.e. (offs26<<2).
2.2.4.4. BL
Instruction formats:
bl
offs26
39
The BL instruction performs the operation that jumps to the target address unconditionally, and writes the
result of adding 4 to the PC value of the instruction into the No.1 general register r1.
The jump target address of the instruction is to shift the 26-bit immediate offs26 in the instruction code to
the left by 2 bits and then sign extend it. The shift value is added to the PC of the branch instruction.
BL:
GR[1] = PC + 4
PC = PC + SignExtend({offs26, 2'b0}, GRLEN)
In LA ABI, the No.1 general register r1 serves as the return address register ra.
When writing assembly, you need to fill in the immediate field with the real offset value in
TIP
bytes, i.e. (offs26<<2).
2.2.4.5. JIRL
Instruction formats:
jirl
rd, rj, offs16
JIRL jumps to the target address unconditionally, and the PC value of the instruction plus 4; then writes the
result into the general register rd.
The jump target address of the instruction is to logically shift the 16-bit immediate offs16 in the
instruction code by 2 bits to the left and then sign extension, and the resulting offset value is added to the
value in the general register rj.
JIRL:
GR[rd] = PC + 4
PC = GR[rj] + SignExtend({offs16, 2'b0}, GRLEN)
When rd is equal to 0, the function of JIRL is a common non-call indirect jump instruction.
JIRL with rd equal to 0, rj equal to 1 and offs16 equal to 0 is often used as an indirect jump from call
return.
When writing assembly, you need to fill in the immediate field with the real offset value in
TIP
bytes, i.e. (offs16<<2).
2.2.5. Common Memory Access Instructions
2.2.5.1. LD.{B[U]/H[U]/W[U]/D}, ST.{B/H/W/D}
Instruction formats:
40
ld.b
rd, rj, si12
ld.h
rd, rj, si12
ld.w
rd, rj, si12
ld.d
rd, rj, si12
ld.bu
rd, rj, si12
ld.hu
rd, rj, si12
ld.wu
rd, rj, si12
st.b
rd, rj, si12
st.h
rd, rj, si12
st.w
rd, rj, si12
st.d
rd, rj, si12
LD.{B/H/W/D} retrieves the data of one byte/halfword/word/double word from the internal sign extension
and writes it into the general register rd.
LD.B:
vaddr = GR[rj] + SignExtend(si12, GRLEN)
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
byte = MemoryLoad(paddr, BYTE)
GR[rd] = SignExtend(byte, GRLEN)
LD.H:
vaddr = GR[rj] + SignExtend(si12, GRLEN)
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
halfword = MemoryLoad(paddr, HALFWORD)
GR[rd] = SignExtend(halfword, GRLEN)
LD.W:
vaddr = GR[rj] + SignExtend(si12, GRLEN)
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
word = MemoryLoad(paddr, WORD)
GR[rd] = SignExtend(word, GRLEN)
LD.D:
vaddr = GR[rj] + SignExtend(si12, GRLEN)
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
GR[rd] = MemoryLoad(paddr, DOUBLEWORD)
LD.{BU/HU/WU} retrieves one byte/halfword/word data from the memory and writes it into the general
41
register rd after zero extension.
LD.BU:
vaddr = GR[rj] + SignExtend(si12, GRLEN)
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
byte = MemoryLoad(paddr, BYTE)
GR[rd] = ZeroExtend(byte, GRLEN)
LD.HU:
vaddr = GR[rj] + SignExtend(si12, GRLEN)
AddressCompli anceCheck(vaddr)
paddr = AddressTranslation(vaddr)
halfword = MemoryLoad(paddr, HALFWORD)
GR[rd] = ZeroExtend(halfword, GRLEN)
LD.WU:
vaddr = GR[rj] + SignExtend(si12, GRLEN)
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
word = MemoryLoad(paddr, WORD)
GR[rd] = ZeroExtend(word, GRLEN)
ST.{B/H/W/D} writes [7:0]/[15:0]/[31:0]/[63:0] bit data in general register rd into the memory.
ST.B:
vaddr = GR[rj] + SignExtend(si12, GRLEN)
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
MemoryStore(GR[rd][7:0], paddr, BYTE)
ST.H:
vaddr = GR[rj] + SignExtend(si12, GRLEN)
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
MemoryStore(GR[rd][15:0], paddr, HALFWORD)
ST.W:
vaddr = GR[rj] + SignExtend(si12, GRLEN)
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
MemoryStore(GR[rd][31:0], paddr, WORD)
42
ST.D:
vaddr = GR[rj] + SignExtend(si12, GRLEN)
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
MemoryStore(GR[rd][63:0], paddr, DOUBLEWORD)
The memory access address calculation method of the above instruction is sum the value in the general
register rj and the sign extension 12-bit immediate value sil2.
For LD.{H[U]/W[U]/D} and ST.{B/H/W/D} instructions, no matter what kind of hardware
implementation and environmental configuration, as long as their memory access addresses are naturally
aligned When the memory access address is not naturally aligned, if the hardware implementation supports
non-aligned memory access and the current computing environment is configured to allow non-aligned
memory access, then the non-aligned exception will not be triggered, otherwise a non-aligned exception will
be triggered.
2.2.5.2. LDX.{B[U]/H[U]/W[U]/D}, STX.{B/H/W/D}
Instruction formats:
ldx.b
rd, rj, rk
ldx.h
rd, rj, rk
ldx.w
rd, rj, rk
ldx.d
rd, rj, rk
ldx.bu
rd, rj, rk
ldx.hu
rd, rj, rk
ldx.wu
rd, rj, rk
stx.b
rd, rj, rk
stx.h
rd, rj, rk
stx.w
rd, rj, rk
sbx.d
rd, rj, rk
LDX.{B/H/W/D} retrieves the data of one byte/halfword/word/double word from the internal sign
extension and writes it into the general register rd.
LDX.B:
vaddr = GR[rj] + GR[rk]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
byte = MemoryLoad(paddr, BYTE)
GR[rd] = SignExtend(byte, GRLEN)
LDX.H:
vaddr = GR[rj] + GR[rk]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
43
halfword = MemoryLoad(paddr, HALFWORD)
GR[rd] = SignExtend(halfword, GRLEN)
LDX.W:
vaddr = GR[rj] + GR[rk]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
word = MemoryLoad(paddr, WORD)
GR[rd] = SignExtend(word, GRLEN)
LDX.D:
vaddr = GR[rj] + GR[rk]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
GR[rd] = MemoryLoad(paddr, DOUBLEWORD)
LDX.{BU/HU/WU} retrieves one byte/halfword/word data from the internal zero extension and writes it
into the general register rd.
LDX.BU:
vaddr = GR[rj] + GR[rk]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
byte = MemoryLoad(paddr, BYTE)
GR[rd] = ZeroExtend(byte, GRLEN)
LDX.HU:
vaddr = GR[rj] + GR[rk]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
halfword = MemoryLoad(paddr, HALFWORD)
GR[rd] = ZeroExtend(halfword, GRLEN)
LDX.WU:
vaddr = GR[rj] + GR[rk]
AddressCompli anceCheck(vaddr)
paddr = AddressTranslation(vaddr)
word = MemoryLoad(paddr, WORD)
GR[rd] = ZeroExtend(word, GRLEN)
STX.{B/H/W/D} writes [7:0], [15:0], [31:0] and [63:0] bits of data in the general register rd into
the memory.
44
STX.B:
vaddr = GR[rj] + GR[rk]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
MemoryStore(GR[rd][7:0], paddr, BYTE)
STX.H:
vaddr = GR[rj] + GR[rk]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
MemoryStore(GR[rd][15:0], paddr, HALFWORD)
STX.W:
vaddr = GR[rj] + GR[rk]
AddressCompli anceCheck(vaddr)
paddr = AddressTranslation(vaddr)
MemoryStore(GR[rd][31:0], paddr, WORD)
STX.D:
vaddr = GR[rj] + GR[rk]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
MemoryStore(GR[rd][63:0], paddr, DOUBLEWORD)
The memory access address calculation method of the above instruction is the value in the general register
rj and the value in the general register rk. For LDX.{H[U]/W[U]/D} and STX.{B/H/W/D} instructions,
no matter what kind of hardware implementation and environment configuration, as long as its memory
access address is natural Aligned, will not trigger non-aligned exception; when the fetch address is not
naturally aligned, if the hardware implementation supports non-aligned memory access and the current
computing environment is configured to allow non-aligned memory access, then the non-aligned exception
will not be triggered, otherwise a non-aligned exception will be triggered.
2.2.5.3. LDPTR.{W/D}, STPTR.{W/D}
Instruction formats:
ldptr.w
rd, rj, si14
ldptr.d
rd, rj, si14
stptr.w
rd, rj, si14
stptr.d
rd, rj, si14
LDPTR.{W/D} retrieves the data of a word/double word from the internal sign extension and writes it into
the general register rd.
LDPTR.W:
45
vaddr = GR[rj] + SignExtend({si14, 2'b0}, GRLEN)
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
word = MemoryLoad(paddr, WORD)
GR[rd] = SignExtend(word, GRLEN)
LDPTR.D:
vaddr = GR[rj] + SignExtend({si14, 2'b0}, GRLEN)
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
GR[rd] = MemoryLoad(paddr, DOUBLEWORD)
STPTR.{W/D} Write the data of bits [31:0]/[63:0] in the general register rd into the memory.
STPTR.W:
vaddr = GR[rj] + SignExtend({si14, 2'b0}, GRLEN)
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
MemoryStore(GR[rd][31:0], paddr, WORD)
STPTR.D:
vaddr = GR[rj] + SignExtend({si14, 2'b0}, GRLEN)
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
MemoryStore(GR[rd][63:0], paddr, DOUBLEWORD)
The memory access address calculation method of the above instruction is to logical left shift the 14-bit
immediate data si14 by 2 bits, sign extension, and then sum the value in the general register rj.
When writing assembly, you need to fill in the immediate field with the real offset value in
TIP
bytes, i.e. (si14<<2).
For LDPTR.{W/D} and STPTR.{W/D} instructions, no matter what kind of hardware implementation and
environmental configuration, as long as the memory access address is naturally aligned, the non-aligned
exception will not be triggered; when the memory address is not naturally aligned, if the hardware
implementation supports unaligned memory access and the current computing environment is configured
to allow unaligned memory access, then the unaligned exception will not be triggered, otherwise it will
trigger the unaligned exception.
LDPTR.{W/D}, STPTR.{W/D} instructions are used in conjunction with ADDU16I.D instructions to
accelerate GOT table-based access in position-independent codes.
2.2.5.4. PRELD
Instruction formats:
46
preld
hint, rj, si12
PRELD Reads a cache-line of data from memory in advance into the Cache. The access address is the 12bit
immediate number of the value in the general register rj plus the symbol extension.
The processor learns from the hint in the PRELD instruction what type will be acquired and which level of
Cache the data to be taken back fill in, hint has 32 optional values (0 to 31), 0 represents load to level 1
Cache, and 8 represents store to level 1 Cache. The remaining hint values are not defined and are
processed for nop instructions when the processor executes.
If the Cache attribute of the access address of the PRELD instruction is not cached, then the instruction
cannot generate a memory access action and is treated as a NOP instruction. The PRELD instruction will
not trigger any exceptions related to MMU or address.
2.2.5.5. PRELDX
Instruction formats:
preldx
hint, rj, rk
The PRELDX instruction continuously prefetches data from memory into the Cache according to the
configuration parameters, and the continuously prefetched data is a block (block) of length block_size
starting from the specified base address (base) with a number of (block_num) spacing stride. The base
address is the sum of the [63:0] bits in the general register rj and the sign extension [15:0] bits in the
general register rk. The [I16] bits in general register rk are the address sequence ascending and
descending flag bits, with 0 indicating address ascending and 1 indicating address descending. The value
of bits [25:20] in general register rk is block_size, the basic unit of block_size is 16 bytes, so the
maximum length of a single block is 1KB. The value of bits [39:32] in general register rk is block_num-
1, so a single instruction can prefetch up to 256 blocks. The value of bits [59:44] in the block general
register rk is treated as a signed number and defines the stride between adjacent blocks, the basic unit of
stride is 1 byte. The value of bits [39:32] in rk is block.num-1, so a single instruction can prefetch up to
256 blocks. The value of bits [59:44] in general register rk is regarded as a signed number, which
defines the corresponding The basic unit of stride and stride between adjacent blocks is 1 byte.
hint in the PRELDX instruction indicates the type of prefetch and the level of Cache into which the fetched
data is to be filled. hint has 32 selectable values from 0 to 31. Currently, hint=0 is defined as load prefetch
to level 1 data Cache, hint=2 is defined as load prefetch to level 3 Cache, hint-8 is defined as store
prefetch to level 1 data Cache. The meaning of the rest of hint values is not defined yet, and the processor
executes it as NOP instruction.
If the Cache attribute of the access address of the PRELDX instruction is not cached, then the instruction
cannot generate a memory access action and is treated as a NOP instruction.
The PRELDX instruction does not trigger any exceptions related to MMU or address.
2.2.6. Bound Check Memory Access Instructions
47
2.2.6.1. LD{GT/LE}.{B/H/W/D}, ST{GT/LE}.{B/H/W/D}
Instruction formats:
ldgt.b
rd, rj, rk
ldgt.h
rd, rj, rk
ldgt.w
rd, rj, rk
ldgt.d
rd, rj, rk
ldle.b
rd, rj, rk
ldle.h
rd, rj, rk
ldle.w
rd, rj, rk
ldle.d
rd, rj, rk
stgt.b
rd, rj, rk
stgt.h
rd, rj, rk
stgt.w
rd, rj, rk
stgt.d
rd, rj, rk
stle.b
rd, rj, rk
stle.h
rd, rj, rk
stle.w
rd, rj, rk
stle.d
rd, rj, rk
LDGT/LDLE.B/H/W/D fetches a byte/half word word/double word data symbol extension from memory
and writes it to the general register rd.
STGT/STLE.B/H/W/D writes the [7:0]/[15:0]/[31:0]/[63:0] bits of data from the general register
rd to memory.
The access addresses of the above instructions come directly from the values in the general register rj.
The access addresses of the above instructions are required to be naturally aligned, otherwise a non-
alignment exception will be triggered.
B/H/W/D and STGT.B/H/W/D instructions check whether the value in general register rj is greater than
the value in general register rk, and terminate the access operation and trigger the bound check exception
if the condition is not satisfied; B/H/W/D and STLE.B/H/W/D instructions check whether the value in
general register rj is less than or equal to the value in general register rk, and if the condition is not
satisfied, the access operation is terminated and the bound check exception is triggered.
LDGT.B:
vaddr = GR[rj]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
if GR[rj] > GR[rk]:
byte = MemoryLoad(paddr, BYTE)
GR[rd] = SignExtend(byte, GRLEN)
else:
RaiseException(BCE)
# Bound Check Exception
48
LDGT.H:
vaddr = GR[rj]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
if GR[rj] > GR[rk]:
halfword = MemoryLoad(paddr, HALFWORD)
GR[rd] = SignExtend(halfword, GRLEN)
else:
RaiseException(BCE)
# Bound Check Exception
LDGT.W:
vaddr = GR[rj]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
if GR[rj] > GR[rk]:
word = MemoryLoad(paddr, WORD)
GR[rd] = SignExtend(word, GRLEN)
else:
RaiseException(BCE)
# Bound Check Exception
LDGT.D:
vaddr = GR[rj]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
if GR[rj] > GR[rk]:
GR[rd] = MemoryLoad(paddr, DOUBLEWORD)
else:
RaiseException(BCE)
# Bound Check Exception
LDLE.B:
vaddr = GR[rj]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
if GR[rj] <= GR[rk]:
byte = MemoryLoad(paddr, BYTE)
GR[rd] = SignExtend(byte, GRLEN)
else:
RaiseException(BCE)
# Bound Check Exception
LDLE.H:
vaddr = GR[rj]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
49
if GR[rj] <= GR[rk]:
halfword = MemoryLoad(paddr, HALFWORD)
GR[rd] = SignExtend(halfword, GRLEN)
else:
RaiseException(BCE)
# Bound Check Exception
LDLE.W:
vaddr = GR[rj]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
if GR[rj] <= GR[rk]:
word = MemoryLoad(paddr, WORD)
GR[rd] = SignExtend(word, GRLEN)
else:
RaiseException(BCE)
# Bound Check Exception
LDLE.D:
vaddr = GR[rj]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
if GR[rj] <= GR[rk]:
GR[rd] = MemoryLoad(paddr, DOUBLEWORD)
else:
RaiseException(BCE)
# Bound Check Exception
STGT.B:
vaddr = GR[rj]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
if GR[rj] > GR[rk]:
MemoryStore(GR[rd][7:0], paddr, BYTE)
else:
RaiseException(BCE)
# Bound Check Exception
STGT.H:
vaddr = GR[rj]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
if GR[rj] > GR[rk]:
MemoryStore(GR[rd][15:0], paddr, HALFWORD)
else:
RaiseException(BCE)
# Bound Check Exception
STGT.W:
50
vaddr = GR[rj]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
if GR[rj] > GR[rk]:
MemoryStore(GR[rd][31:0], paddr, WORD)
else:
RaiseException(BCE)
# Bound Check Exception
STGT.D:
vaddr = GR[rj]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
if GR[rj] > GR[rk]:
MemoryStore(GR[rd][63:0], paddr, DOUBLEWORD)
else:
RaiseException(BCE)
# Bound Check Exception
STLE.B:
vaddr = GR[rj]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
if GR[rj] <= GR[rk]:
MemoryStore(GR[rd][7:0], paddr, BYTE)
else:
RaiseException(BCE)
# Bound Check Exception
STLE.H:
vaddr = GR[rj]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
if GR[rj] <= GR[rk]:
MemoryStore(GR[rd][15:0], paddr, HALFWORD)
else:
RaiseException(BCE)
# Bound Check Exception
STLE.W:
vaddr = GR[rij]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
if GR[rj] <= GR[rk]:
MemoryStore(GR[rd][31:0], paddr, WORD)
else:
RaiseException(BCE)
# Bound Check Exception
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