|
|
|
The ORN instruction performs the operation that reverses the data in the general register rk bit by bit, then
performs a bitwise OR operation with the data in the general register rk and the data in the general register
rj, and the result is written into the general register rd.
ORN:
GR[rd] = GR[rj] | (~GR[rk])
The data length of the above instruction operation is consistent with the length of the general register of
the executed machine.
2.2.1.9. ANDI, ORI, XORI
Instruction formats:
andi
rd, rj, ui12
ori
rd, rj, ui12
xori
rd, rj, ui12
The ANDI instruction performs the bitwise AND operation between the data in the general register rj and
the 12-bit immediate zero extension data; then the result is written into the general register rd.
ANDI:
GR[rd] = GR[rj] & ZeroExtend(ui12, GRLEN)
The ORI instruction performs the bitwise OR operation between the data in the general register rj and the
12-bit immediate zero extension data; then the result is written into the general register rd.
ORI:
GR[rd] = GR[rj] | ZeroExtend(ui12, GRLEN)
The XORI instruction performs the bitwise XOR operation between the data in the general register rj and
the 12-bit immediate zero extension data; then the result is written into the general register rd.
XORI:
GR[rd] = GR[rj] ^ ZeroExtend(ui12, GRLEN)
The data length of the above instruction operation is consistent with the length of the general register of
the executed machine.
2.2.1.10. NOP
The NOP instruction is an alias for the instruction andi r0, r0,
0. Its function is only to occupy the 4-
byte instruction code position and increase the PC by 4, except that it will not change any other software-
visible processor state.
22
2.2.1.11. MUL.{W/D}, MULH, {W[U]/D[U]}
Instruction formats:
mul.w
rd, rj, rk
mulh.w
rd, rj, rk
mulh.wu
rd, rj, rk
mul.d
rd, rj, rk
mulh.d
rd, rj, rk
mulh.du
rd, rj, rk
The MUL.W instruction performs the operation that multiplies the [31:0] bit data in the general register rj
with the [31:0] bit data in the general register rk, the result of the multiplication [31:0] bit data is
signed and written into the general register rd.
MUL.W:
product = signed(GR[rj][31:0]) * signed(GR[rk][31:0])
GR[rd] = SignExtend(product[31:0], GRLEN)
The MULH.W instruction performs the operation that multiplies the [31:0] bit data in the general register
rj with the [31:0] bit data in the general register rk as a signed number, the result of the multiplication
[63:32] bit data is sign extension and written into the general register rd.
MULH.W:
product = signed(GR[rj][31:0]) * signed(GR[rk][31:0])
GR[rd] = SignExtend(product[63:32], GRLEN)
The MULH.WU instruction performs the operation that multiplies the [31:0] bit data in the general register
rj with the [31:0] bit data in the general register rk as unsigned numbers, the result of the multiplication
[63:32] bit data is sign extension and written into the general register rd.
MULH.WU:
product = unsigned(GR[rj][31:0]) * unsigned(GR[rk][31:0])
GR[rd] = SignExtend(product[63:32], GRLEN)
The MUL.D instruction performs the operation that multiplies the [63:0] bit data in the general register rj
with the [63:0] bit data in the general register rk, the result of the multiplication [63:0] bit data and
written into the general register rd.
MUL.D:
product = signed(GR[rj][63:0]) * signed(GR[rk][63:0])
GR[rd] = product[63:0]
23
The MULH.D instruction performs the operation that multiplies the [63:0] bit data in the general register
rj with the [63:0] bit data in the general register rk as a signed number, the result of the multiplication
[127:64] bit data and written into the general register rd.
MULH.D:
product = signed(GR[rj][63:0]) * signed(GR[rk][63:0])
GR[rd] = product[127:64]
The MULH.DU instruction performs the operation that multiplies the [63:0] bit data in the general register
rj and the [63:0] bit data in the general register rk as unsigned numbers, the result of the multiplication
[127:64] bit data and written into the general register rd.
MULH.DU:
product = unsigned(GR[rj][63:0]) * unsigned(GR[rk][63:0])
GR[rd] = product[127:64]
2.2.1.12. MULW.D.W[U]
Instruction formats:
mulw.d.w
rd, rj, rk
mulw.d.wu
rd, rj, rk
The MULW.D.W instruction performs the operation that multiplies the [31:0] bit data in the general
register rj with the [31:0] bit data in the general register rk as a signed number, and the 64-bit product
result is written into the general register rd.
MULW.D.W:
product = signed(GR[rj][31:0]) * signed(GR[rk][31:0])
GR[rd] = product[63:0]
The MULW.D.WU instruction performs the operation that multiplies the [31:0] bit data in the general
register rj with the [31:0] bit data in the general register rk as unsigned numbers, and writes the 64-bit
product result into the general register rd.
MULW.D.WU:
product = unsigned(GR[rj][31:0]) * unsigned(GR[rk][31:0])
GR[rd] = product[63:0]
2.2.1.13. DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
Instruction formats:
24
div.w
rd, rj, rk
mod.w
rd, rj, rk
div.wu
rd, rj, rk
mod.wu
rd, rj, rk
div.d
rd, rj, rk
mod.d
rd, rj, rk
div.du
rd, rj, rk
mod.du
rd, rj, rk
The DIV.W and DIV.WU instruction performs the operation that divide the [31:0] bit data in the general
register rj by the [31:0] bit data in the general register rk, and the resulting quotient is sign extension
and written into the general register rd.
DIV.W:
quotient = signed(GR[rj][31:0]) / signed(GR[rk][31:0])
GR[rd] = SignExtend(quotient[31:0], GRLEN)
DIV.WU:
quotient = unsigned(GR[rj][31:0]) / unsigned(GR[rk][31:0])
GR[rd] = SignExtend(quotient[31:0], GRLEN)
The MOD.W and MOD.WU instruction performs the operation that divide the [31:0] bit data in the general
register rj by the [31:0] bit data in the general register rk, and the resulting remainder is sign extension
and written into the general register rd.
MOD.W:
remainder = signed(GR[rj][31:0]) % signed(GR[rk][31:0])
GR[rd] = SignExtend(remainder[31:0], GRLEN)
MOD.WU:
remainder = unsigned(GR[rj][31:0]) % unsigned(GR[rk][31:0])
GR[rd] = SignExtend(remainder[31:0], GRLEN)
The DIV.D and DIV.DU instruction performs the operation that divide the [63:0] bit data in the general
register rj by the [63:0] bit data in the general register rk, and the resulting quotient sign extension and
written into the general register rd.
DIV.D:
GR[rd] = signed(GR[rj][63:0]) / signed(GR[rk][63:0])
DIV.DU:
GR[rd] = unsigned(GR[rj][63:0]) / unsigned(GR[rk][63:0])
25
The MOD.D and MOD.DU instruction performs the operation that divide the [63:0] bit data in the general
register rj by the [63:0] bit data in the general register rk, and the resulting remainder is sign extension
and written into the general register rd.
MOD.D:
GR[rd] = signed(GR[rj][63:0]) % signed(GR[rk][63:0])
MOD.DU:
GR[rd] = unsigned(GR[rj][63:0]) % unsigned(GR[rk][63:0])
When DIV.W, MOD.W, DIV.D and MOD.D perform division operations, the operands are all regarded as
signed numbers. When DIV.WU, M0D.WU, DIV.DU and MOD.DU perform division operations, the source
operands are all regarded as unsigned numbers.
Each pair of instructions for finding the quotient/remainder satisfies the result of DIV.W/MOD.W, DIV.WU
/MOD.WU, DIV.D/MOD.D, DIV.DU/MOD.DU, the remainder and the dividend The sign is consistent and the
absolute value of the remainder is less than the absolute value of the divisor.
When the divisor is 0, the result can be any value, but no exception will be triggered.
2.2.2. Bit-shift Instructions
2.2.2.1. SLL.W, SRL.W, SRA.W, ROTR.W
Instruction formats:
sll.w
rd, rj, rk
srl.w
rd, rj, rk
sra.w
rd, rj, rk
rotr.w
rd, ri, rk
The SLL.W instruction performs the operation that logical left shifts the bit data of [31:0] in the general
register rj, and writes the sign extension of the shift result into the general register rd.
SLL.W:
tmp = SLL(GR[rj][31:0], GR[rk][4:0])
GR[rd] = SignExtend(tmp[31:0], GRLEN)
The SRL.W instruction performs the operation that logical right shifts the bit data of [31:0] in the general
register rj, and writes the sign extension of the shift result into the general register rd.
SRL.W:
tmp = SRL(GR[rj][31:0], GR[rk][4:0])
GR[rd] = SignExtend(tmp[31:0], GRLEN)
26
The SRA.W instruction performs the operation that arithmetical right shifts [31:0] bit data in the general
register rj, and writes the sign extension of the shift result into the general register rd.
SRA.W:
tmp = SRA(GR[rj][31:0], GR[rk][4:0])
GR[rd] = SignExtend(tmp[31:0], GRLEN)
The ROTR.W instruction performs the operation that cyclical right shifts the [31:0] bit data in the general
register rj, and writes the sign extension of the shift result into the general register rd.
ROTR.W:
tmp = ROTR(GR[rj][31:0], GR[rk][4:0])
GR[rd] = SignExtend(tmp[31:0], GRLEN)
The shift amount of the above-mentioned shift instruction is all [4:0] bit data in the general register rk,
and is regarded as an unsigned number.
2.2.2.2. SLLI.W, SRLI.W, SRAI.W, ROTRI.W
Instruction formats:
sliw
rd, rj, ui5
srli.w
rd, rj, ui5
srai.w
rd, rj, ui5
rotri.w
rd, rj, ui5
The SLLI.W instruction performs the operation that logical left shifts the [31:0] bit data in the general
register rj, and writes the sign extension of the shift result into the general register rd.
SLLI.W:
tmp = SLL(GR[rj][31:0], ui5)
GR[rd] = SignExtend(tmp[31:0], GRLEN)
The SRLI.W instruction performs the operation that logical right shifts the [31:0] bit data in the general
register rj to the right, and writes the sign extension of the shift result into the general register rd.
SRLI.W:
tmp = SRL(GR[rj][31:0], ui5)
GR[rd] = SignExtend(tmp[31:0], GRLEN)
The SRAI.W instruction performs the operation that arithmetical right shifts the bit data of [31:0] in the
general register rj, and writes the sign extension of the shift result into the general register rd.
27
SRAI.W:
tmp = SRA(GR[rj][31:0], ui5)
GR[rd] = SignExtend(tmp[31:0], GRLEN)
The ROTRI.W instruction performs the operation that cyclical right shifts the [31:0] bit data in the general
register rj, and the sign extension of the shift result is written into the general register rd.
ROTRI.W:
tmp = ROTR(GR[rj][31:0], ui5)
GR[rd] = SignExtend(tmp[31:0], GRLEN)
The shift amounts of the above shift instructions are all 5-bit unsigned immediate ui5 in the instruction
code.
2.2.2.3. SLL.D, SRL.D, SRA.D, ROTR.D
Instruction formats:
sl.d
rd, rj, rk
srl.d
rd, rj, rk
sra.d
rd, rj, rk
rotr.d
rd, rj, rk
The SLL.D instruction performs the operation that logical left shifts the bit data of [63:0] in the general
register rj, and writes the sign extension of the shift result into the general register rd.
SLL.D:
GR[rd] = SLL(GR[rj][63:0], GR[rk][5:0])
The SRL.D instruction performs the operation that logical right shifts the bit data of [63:0] in the general
register rj, and writes the sign extension of the shift result into the general register rd.
SRL.D:
GR[rd] = SRL(GR[rj][63:0], GR[rk][5:0])
The SRA.D instruction performs the operation that arithmetic right shifts the bit data of [63:0] in the
general register rj, and writes the sign extension of the shift result into the general register rd.
SRA.D:
GR[rd] = SRA(GR[rj][63:0], GR[rk][5:0])
28
The ROTR.D instruction performs the operation that cyclical right shifts the bit data of [63:0] in the
general register rj, and writes the sign extension of the shift result into the general register rd.
ROTR.D:
GR[rd] = ROTR(GR[rj][63:0], GR[rk][5:0])
The shift amount of the above-mentioned shift instruction is all [5:0] bit data in the general register rk,
and is regarded as an unsigned number.
2.2.2.4. SLLI.D, SRLI.D, SRAI.D, ROTRI.D
Instruction formats:
slli.d
rd, rj, ui6
srli.d
rd, rj, ui6
srai.d
rd, rj, ui6
rotri.d
rd, rj, ui6
The SLII.D instruction performs the operation that logicalleft shifts the bit data of [63:0] in the general
register rj, and the sign extension of the shift result is written into the general register rd.
SLLI.D:
GR[rd] = SLL(GR[rj][63:0], ui6)
The SRLI.D instruction performs the operation that logical right shifts the bit data of [63:0] in the
general register rj, and writes the sign extension of the shift result into the general register rd.
SRLI.D:
GR[rd] = SRL(GR[rj][63:0], ui6)
The SRAI.D instruction performs the operation that arithmetically right shifts the bit data of [63:0] in the
general register rj, and writes the sign extension of the shift result into the general register rd.
SRAI.D:
GR[rd] = SRA(GR[rj][63:0], ui6)
The ROTRI.D instruction performs the operation that cyclical right shifts the [63:0] bit data in the general
register rj, and the sign extension of the shift result is written into the general register rd.
ROTRI.D:
GR[rd] = ROTR(GR[rj][63:0], ui6)
29
The shift amount of the above-mentioned shift instruction is the 6-bit unsigned immediate ui6 in the
instruction code.
2.2.3. Bit-manipulation Instructions
2.2.3.1. EXT.W{B/H}
Instruction formats:
ext.w.b
rd, rj
ext.w.h
rd, rj
The EXT.W.B instruction performs the operation that will sign extension the bit data of [7:0] in the
general register rj and write it into the general register rd.
EXT.W.B:
GR[rd] = SignExtend(GR[rj][7:0], GRLEN)
The EXT.W.H instruction performs the operation that will sign extension the bit data of [15:0] in the
general register rj and write it into the general register rd.
EXT.W.H:
GR[rd] = SignExtend(GR[rj][15:0], GRLEN)
2.2.3.2. CL{O/Z}.{W/D}, CT{O/Z}.{W/D}
Instruction formats:
clo.w
rd, rj
clo.d
rd, rj
clz.w
rd, rj
clz.d
rd, rj
cto.w
rd, rj
cto.d
rd, rj
ctz.w
rd, rj
ctz.d
rd, rj
The CLO.W instruction performs the operation that for the data of bit [31:0] in the general register rj, the
number of continuous bits 1 is measured from bit 31 to bit 0, and the result is written into the universal
register rd.
CLO.W:
GR[rd] = CLO(GR[rj][31:0])
30
The CLZ.W instruction performs the operation that for the data of bit [31:0] in the general register rj, the
number of continuous bits 0 is measured from bit 31 to bit 0, and the result is written into the universal
register rd.
CLZ.W:
GR[rd] = CLZ(GR[rj][31:0])
The CTO.W instruction performs the operation that for the data of bit [31:0] in the general register rj, the
number of continuous bits 1 is measured from bit 0 to bit 31, and the result is written into the universal
register rd.
CTO.W:
GR[rd] = CTO(GR[rj][31:0])
The CTZ.W instruction performs the operation that for the data of bit [31:0] in the general register rj, the
number of continuous bits 0 is measured from bit 0 to bit 31, and the result is written into the universal
register rd.
CTZ.W:
GR[rd] = CTZ(GR[rj][31:0])
The CLO.D instruction performs the operation that for the data of bit [63:0] in the general register rj, the
number of continuous bits 1 is measured from bit 63 to bit 0, and the result is written into the universal
register rd.
CLO.D:
GR[rd] = CL0(GR[rj][63:0])
The CLZ.D instruction performs the operation that for the data of bit [63:0] in the general register rj, the
number of continuous bits 1 is measured from bit 0 to bit 63, and the result is written into the universal
register rd.
CLZ.D:
GR[rd] = CLZ(GR[rj][63:0])
The CTO.D instruction performs the operation that for the data of bit [63:0] in the general register rj, the
number of continuous bits 0 is measured from bit 0 to bit 63, and the result is written into the universal
register rd.
CTO.D:
GR[rd] = CTO(GR[rj][63:0])
31
The CTZ.D instruction performs the operation that for the data of bit [63:0] in the general register rj, the
number of continuous bits 0 is measured from bit 0 to bit 63, and the result is written into the universal
register rd.
CTZ.D:
GR[rd] = CTZ(GR[rj][63:0])
2.2.3.3. BYTEPICK.{W/D}
Instruction formats:
bytepick.w rd, rj, rk, sa2
bytepick.d rd, rj, rk, sa3
The BYTEPICK.W instruction performs the operation that splice [31:0] bits in the general register rj
behind [31:0] bits in the general register rk, and intercepts 4 consecutive bytes starting from the
leftmost sa2 byte, and writes the 32-bit bit string symbol into universal register rd after expansion.
BYTEPICK.W:
tmp = {GR[rk][8*(4-sa2):0], GR[rj][31:8*(4-sa2)]}
GR[rd] = SignExtend(tmp[31:0], GRLEN)
The BYTEPICK.D instruction performs the operation that splice [63:0] bits in the general register rj
behind [63:0] bits in the general register rk, and intercepts 8 consecutive bytes starting from the
leftmost sa3 byte, and writes the 64-bit bit string symbol into universal register rd after expansion.
BYTEPICK.D:
GR[rd] = {GR[rk][8*(8-sa3):0], GR[rj][63:8*(8-sa3)]}
2.2.3.4. REVB.{2H/4H/2W/D}
Instruction formats:
revb.2h
rd, rj
revb.4h
rd, ri
revb.2w
rd, rj
revb.d
rd, rj
The REVB.2H instruction performs the operation that arranges the 2 bytes in the [15:0] bits in the general
register rj in reverse order to form the [15:0] bits of the intermediate result, and reverses the 2 bytes in
the [31:16] in the general register rj Arrange the [31:16] bits of the intermediate result, and write the
32-bit intermediate result sign extended to the general register rd.
32
REVB.2H:
tmp0 = {GR[rj][ 7: 0], GR[rj][15: 8]}
tmp1 = {GR[rj][23:16], GR[rj][31:24]}
GR[rd] = SignExtend({tmp1, tmp0}, GRLEN)
The REVB.4H instruction performs the operation that arranges the 2 bytes in the [15:0] bits of the
general register rj in reverse order and writes them into the [15:0] bits of the general register rd, and
writes 2 words in the [31:16] bits of the general register rj. Write the sections in reverse order to bits
[31:16] of the general register rd, and write the 2 bytes of bits [47:32] in the general register rj in
reverse order to bits [47:32] of the general register rd. The 2 bytes in the [63:48] bits in the register rj
are written in the [63:48] bits in the general register rd in reverse order.
REVB.4H:
tmp0 = {GR[rj][ 7: 0], GR[rj][15: 8]}
tmp1 = {GR[rj][23:16], GR[rj][31:24]}
tmp2 = {GR[rj][39:32], GR[rj][47:40]}
tmp3 = {GR[rj][55:48], GR[rj][63:56]}
GR[rd] = {tmp3, tmp2, tmp1, tmp0}
The REVB.2W instruction performs the operation that writes the 4 bytes in the [31:0] bits of the general
register rj into the [31:0] bits of the general register rd in reverse order, and writes 4 of the [63:32]
bits in the general register rj. Write the byte in reverse order to bits [63:32] of the general register rd.
REVB.2W:
tmp0 = {GR[rj][ 7: 0], GR[rj][15: 8], GR[rj][31:24], GR[rj][23:16]}
tmp1 = {GR[rj][39:32], GR[rj][47:40], GR[rj][55:48], GR[rj][63:56]}
GR[rd] = {tmp1, tmp0}
REVB.D writes the 8 bytes in the [63:0] bits in the general register rj into the general register rd in
reverse order.
REVB.D:
GR[rd] = {GR[rj][ 7: 0], GR[rj][15: 8], GR[rj][31:24],
GR[rj][23:16],
GR[rj][39:32], GR[rj][47:40], GR[rj][55:48], GR[rj][63:56]}
2.2.3.5. REVH.{2W/D}
Instruction formats:
revh.2w
rd, rj
33
revh.d
rd, rj
The REVH.2W instruction performs the operation that writes two half-words in bit [31:0] of general
purpose register rj into bit [31:0] of general purpose register rd, and two half-words in bit [63:32] of
general purpose register rj into bit [63:32] of general purpose register rd.
REVH.2W:
tmp0 = {GR[rj][15: 0], GR[rj][31:16]}
tmp1 = {GR[rj][47:32], GR[rj][63:48]}
GR[rd] = {tmp1, tmp0}
The REVH.D instruction performs the operation that write four half-words in [63:0] bit of universal
register rj in reverse order to universal register rd.
REVH.D:
GR[rd] = {GR[rj][15:0], GR[rj][31:16], GR[rj][47:32], GR[rj][63:48]}
2.2.3.6. BITREV.{4B/8B}
Instruction formats:
bitrev.4b
rd, rj
bitrev.8b
rd, rj
The BITREV.4B instruction performs the operation that the [7:0] bit in general register rj is arranged in
reverse order, the [15:8] bit in general register rj is arranged in reverse order, the [23:16] bit in general
register rj is arranged in reverse order, and the [31:24] bit in general register rj is arranged in reverse
order; the 32-bit intermediate result sign extension is written into general register rd in turn.
BITREV.4B:
bstr32[31:24] = BITREV(GR[rj][31:24])
bstr32[23:16] = BITREV(GR[rj][23:16])
bstr32[15: 8] = BITREV(GR[rj][15: 8])
bstr32[ 7: 0] = BITREV(GR[rj][ 7: 0])
GR[rd] = SignExtend(bstr32, GRLEN)
The BITREV.8B instruction performs the operation that the [7:0] bit in general register rj is arranged in
reverse order, the [15:8] bit in general register rj is arranged in reverse order, the [23:16] bit in general
register rj is arranged in reverse order, the [31:24] bit in general register rj is arranged in reverse order;
the [39:32] bit in general register rj is arranged in reverse order; the [47:40] bit in general register rj
is arranged in reverse order; the [55:48] bit in general register rj is arranged in reverse order; the
[63:56] bit in general register rj is arranged in reverse order; the 32-bit intermediate result sign extension
is written into general register rd in turn.
34
BITREV.8B:
GR[rd][63:56] = BITREV(GR[rj][63:56])
GR[rd][55:48] = BITREV(GR[rj][55:48])
GR[rd][47:40] = BITREV(GR[rj][47:40])
GR[rd][39:32] = BITREV(GR[rj][39:32])
GR[rd][31:24] = BITREV(GR[rj][31:24])
GR[rd][23:16] = BITREV(GR[rj][23:16])
GR[rd][15: 8] = BITREV(GR[rj][15: 8])
GR[rd][ 7: 0] = BITREV(GR[rj][ 7: 0])
2.2.3.7. BITREV.{W/D}
Instruction formats:
bitrev.w
rd, rj
bitrev.d
rd, rj
The BITREV.W instruction performs the operation that the [31:0] bit in general register rj is arranged in
reverse order; the 32-bit intermediate result sign extension is written into general register rd in turn.
BITREV.W:
bstr32[31:0] = BITREV(GR[rj][31:0])
GR[rd] = SignExtend(bstr32, GRLEN)
The BITREV.D instruction performs the operation that the [63:0] bit in general register rj is arranged in
reverse order; the 32-bit intermediate result sign extension is written into general register rd in turn.
BITREV.D:
GR[rd] = BITREV(GR[rj][63:0])
2.2.3.8. BSTRINS.{W/D}
Instruction formats:
bstrins.w
rd, rj, msbw, lsbw
bstrins.d
rd, rj, msbd, lsbd
The BSTRINS.W instruction performs the operation that replaces the [msbw:lsbw] bit in the lowest 32
bits of the general register rd with the [msbw-lsbw:0] bit in the general register rj, and the resulting 32-
bit result is sign extension and written into the general register rd.
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BSTRINS.W:
bstr32[31:msbw+1] = GR[rd][31: msbw+1]
bstr32[msbw:lsbw] = GR[rj][msbw-lsbw:0]
bstr32[lsbw-1:0] = GR[rd][lsbw-1:0]
GR[rd] = SignExtend(bstr32[31:0], GRLEN)
The BSTRINS.D instruction performs the operation that replaces the [msbd:lsbd] bit in the general
register rd with the [msbd-lsbd:0] bit in the general register rj, and the rest of the general register rd
remains unchanged.
BSTRINS.D:
GR[rd][63:msbd+1] = GR[rd][63:msbd+1]
GR[rd][msbd:lsbd] = GR[rj][msbd-lsbd:0]
GR[rd][lsbd-1:0] = GR[rd][lsbd-1:0]
2.2.3.9. BSTRPICK.{W/D}
Instruction formats:
bstrpick.w rd, rj, msbw, lsbw
bstrpick.d rd, rj, msbd, lsbd
BSTRPICK.W extracts the [msbw:Isbw] bit in the general register rj and zero-extends it to 32 bits, and
the formed 32-bit intermediate result is sign extension and written into the general register rd.
BSTRPICK.W:
bstr32[31:0] = ZeroExtend(GR[rj][msbw:lsbw], 32)
GR[rd] = SignExtend(bstr32[31:0], GRLEN)
BSTRPICK.D extracts the [msbd:Isbd] bit in the general register rj and zero-extends it to 64 bits and
writes it into the general register rd.
BSTRPICK.D:
GR[rd] = ZeroExtend(GR[rj][msbd:lsbd], 64)
2.2.3.10. MASKEQZ, MASKNEZ
Instruction formats:
maskeqz
rd, rj, rk
masknez
rd, rj, rk
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