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LoongArch Reference Manual
Volume 1: Basic Architecture
Loongson Technology Corporation Limited
Version 1.02
Table of Contents
List of Figures
1
List of Tables
2
About this manual
5
Copyright Statement
5
Disclaimer
5
Loongson Technology Corporation Limited
5
Reading Guide
5
Translator’s Note
5
License
5
Contributors
5
1. Introduction
7
1.1. Overview of LoongArch ISA
7
1.2. Instruction formats
8
1.3. Assembly Instruction Mnemonic Formats
9
1.4. Conventions Used in this Manual
10
1.4.1. Instruction Abbreviation
10
1.4.2. References to Control and Status Registers
10
2. Basic Integer Instructions
11
2.1. Programming Model of Basic Integer Instruction
11
2.1.1. Data Types
11
2.1.2. Registers
11
2.1.2.1. General-purpose Registers
11
2.1.2.2. PC
12
2.1.3. Running Privilege Levels
12
2.1.3.1. Privileged Resources Accessible by Applications
12
2.1.3.2. Disabling of Some Non-privileged Functions
12
2.1.4. Exceptions and interrupts
12
2.1.5. Memory Address Space
13
2.1.6. Endian
13
2.1.7. Memory Access Types
13
2.1.7.1. Cache Coherency Maintenance of Instruction Cache
14
2.1.8. Unaligned Memory Access
14
2.1.9. Overview of Memory Consistency
14
2.2. Overview of Basic Integer Instructions
14
2.2.1. Arithmetic Operation Instructions
15
15
2.2.1.1. ADD.{W/D}, SUB.{W/D}
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.1.2. ADDI.{W/D}, ADDU16I.D
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.1.3. ALSL.{W[U]/D}
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.1.4. LU12I.W, LU32I.D, LU52I.D
18
2.2.1.5. SLT[U]
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.1.6. SLT[U]I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.1.7. PCADDI, PCADDU121, PCADDU18l, PCALAU12I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.1.8. AND, OR, NOR, XOR, ANDN, ORN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.1.9. ANDI, ORI, XORI
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.1.10. NOP
23
2.2.1.11. MUL.{W/D}, MULH, {W[U]/D[U]}
24
2.2.1.12. MULW.D.W[U]
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.2.1.13. DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
2.2.2. Bit-shift Instructions
26
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.2.2.1. SLL.W, SRL.W, SRA.W, ROTR.W
27
2.2.2.2. SLLI.W, SRLI.W, SRAI.W, ROTRI.W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.2.2.3. SLL.D, SRL.D, SRA.D, ROTR.D
29
2.2.2.4. SLLI.D, SRLI.D, SRAI.D, ROTRI.D
2.2.3. Bit-manipulation Instructions
30
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.2.3.1. EXT.W{B/H}
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.2.3.2. CL{O/Z}.{W/D}, CT{O/Z}.{W/D}
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.2.3.3. BYTEPICK.{W/D}
32
2.2.3.4. REVB.{2H/4H/2W/D}
33
2.2.3.5. REVH.{2W/D}
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.2.3.6. BITREV.{4B/8B}
35
2.2.3.7. BITREV.{W/D}
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.2.3.8. BSTRINS.{W/D}
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.2.3.9. BSTRPICK.{W/D}
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.2.3.10. MASKEQZ, MASKNEZ
2.2.4. Branch Instructions
37
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.2.4.1. BEQ, BNE, BLT[U], BGE[U]
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.2.4.2. BEQZ, BNEZ
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.2.4.3. B
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.2.4.4. BL
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.2.4.5. JIRL
2.2.5. Common Memory Access Instructions
40
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.2.5.1. LD.{B[U]/H[U]/W[U]/D}, ST.{B/H/W/D}
43
2.2.5.2. LDX.{B[U]/H[U]/W[U]/D}, STX.{B/H/W/D}
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.2.5.3. LDPTR.{W/D}, STPTR.{W/D}
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.2.5.4. PRELD
47
2.2.5.5. PRELDX
2.2.6. Bound Check Memory Access Instructions
47
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.2.6.1. LD{GT/LE}.{B/H/W/D}, ST{GT/LE}.{B/H/W/D}
2.2.7. Atomic Memory Access Instructions
52
2.2.7.1. AM{SWAP/ADD/AND/OR/XOR/MAX/MIN}[DB].{W/D},
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
AM{MAX/MIN}[_DB].{WU/DU}
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.2.7.2. LL.{W/D}, SC.{W/D}
2.2.8. Barrier Instructions
54
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.2.8.1. DBAR
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.2.8.2. IBAR
2.2.9. CRC Check Instructions
55
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.2.9.1. CRC[C].W.{B/H/W/D}.W
2.2.10. Other Miscellaneous Instructions
56
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.2.10.1. syscall
56
2.2.10.2. break
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.2.10.3. ASRT{LE/GT}.D
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.2.10.4. RDTIME{L/H}.W, RDTIME.D
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.2.10.5. cpucfg
3. Basic Floating-Point Instructions
64
3.1. Programming Model of Basic Floating-Point Instructions
64
3.1.1. Floating-Point Data Types
64
3.1.1.1. Single-precision Floating-point
64
3.1.1.2. Double-precision Floating-point
65
3.1.1.3. Non-numerical Result of Instructions
66
3.1.2. Fixed-Point Data Types
66
3.1.3. Registers
66
3.1.3.1. Floating-point Registers
66
3.1.3.2. Condition Flag Register
67
3.1.3.3. Floating-point Control and Status Register
67
3.1.4. Floating-Point Exceptions
68
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.1.4.1. Illegal Operation Exception (V)
69
3.1.4.2. Division by Zero Exception (Z)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.1.4.3. Overflow Exception (O)
70
3.1.4.4. Underflow Exception (U)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.1.4.5. Inexact Exception (I)
3.2. Overview of Floating-Point Instructions
70
3.2.1. Floating-Point Arithmetic Operation Instructions
70
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.2.1.1. F{ADD/SUB/MUL/DIV}.{S/D}
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.2.1.2. F{MADD/MSUB/NMADD/NMSUB}.{S/D}
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.2.1.3. F{MAX/MIN}{S/D}
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.2.1.4. F{MAXA/MINA}.{S/D}
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.2.1.5. F{ABS/NEG}.{S/D}
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.2.1.6. F{SQRT/RECIP/RSQRT}.{S/D}
77
3.2.1.7. F{SCALEB/LOGB/COPYSIGN}.{S/D}
78
3.2.1.8. FCLASS.{S/D}
3.2.2. Floating-Point Comparison Instructions
78
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.2.2.1. FCMP.cond.{S/D}
3.2.3. Floating-Point Conversion Instructions
80
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.2.3.1. FCVT.S.D, FCVT.D.S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.2.3.2. FFINT{S/D}.{W/L}, FTINT.{W/L}.{S/D}
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.2.3.3. FTINT{RM/RP/RZ/RNE}.{W/L}.{S/D}
84
3.2.3.4. FRINT.{S/D}
3.2.4. Floating-Point Move Instructions
85
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.2.4.1. FMOV.{S/D}
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.2.4.2. FSEL
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.2.4.3. MOVGR2FR.{W/D}, MOVGR2FRH.W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.2.4.4. MOVFR2GR.{S/D}, MOVFRH2GR.S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.2.4.5. MOVGR2FCSR, MOVFCSR2GR
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.2.4.6. MOVFR2CF, MOVCF2FR
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.2.4.7. MOVGR2CF, MOVCF2GR
3.2.5. Floating-Point Branch Instructions
89
89
3.2.5.1. BCEQZ, BCNEZ
3.2.6. Floating-Point Common Memory Access Instructions
89
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.2.6.1. FLD.{S/D}, FST.{S/D}
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
3.2.6.2. FLDX.{S/D}, FSTX.{S/D}
3.2.7. Floating-Point Bound Check Memory Access Instructions
92
92
3.2.7.1. FLD{GT/LE}.{S/D}, FST{GT/LE}.{S/D}
4. Overview of Privileged Resources
95
4.1. Privilege Levels
95
4.2. Overview of Privilege Instructions
95
4.2.1. CSR Access Instructions
95
4.2.2. IOCSR Access Instructions
96
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.2.2.1. IOCSR{RD/WR}.{B/H/W/D}
4.2.3. Cache Maintenance Instructions
96
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.2.3.1. CACOP
4.2.4. TLB Maintenance Instructions
97
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.2.4.1. TLBSRCH
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.2.4.2. TLBRD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.2.4.3. TLBWR
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.2.4.4. TLBFILL
99
4.2.4.5. TLBCLR
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.2.4.6. TLBFLUSH
99
4.2.4.7. INVTLB
4.2.5. Software page walking Instructions
100
100
4.2.5.1. LDDIR
100
4.2.5.2. LDPTE
4.2.6. Other Miscellaneous Instructions
101
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.2.6.1. ERTN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.2.6.2. DBCL
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.2.6.3. IDLE
5. Memory Management
103
5.1. Physical Address Space
103
5.2. Virtual Address Space and Address Translation Mode
103
5.2.1. Direct Mapped Address Translation Mode
103
5.2.2. 32-bit Address Mode in LA64
104
5.2.3. Virtual Address Reduction Mode in LA64
104
5.3. Memory Access Types
104
5.4. Memory Management of Page Table Mapping
105
5.4.1. TLB Organizational Structure
105
5.4.2. TLB Entry
105
5.4.3. Software Management of TLB
106
5.4.3.1. TLB-related Exceptions
106
5.4.3.2. TLB-related Instructions
107
5.4.3.3. TLB-related CSRs
107
5.4.3.4. Initialization of TLB
108
5.4.4. TLB-based Translation of Virtual Addresses to Physical Addresses
108
5.4.5. Multi-level Page Table Structure Supported by page walking
111
6. Exceptions and interrupts
114
6.1. Interrupts
114
6.1.1. Interrupt Types
114
6.1.2. Interrupt Priority
114
6.1.3. Interrupt Entry
114
6.1.4. Process of Processor Responding to Interrupts
114
6.2. Exceptions
115
6.2.1. Exception Entry
115
6.2.2. Exception Priority
115
6.2.3. General Hardware Exception Handling of General Exceptions
116
6.2.4. Hardware Exception Handling of TLB Refill Exception
116
6.2.5. Hardware Exception Handling of Machine Error Exception
117
6.3. Reset
117
7. Control and Status Registers
119
7.1. Overview of Control and Status Registers
119
7.2. Characteristics of Accessing Control and Status Registers
121
7.2.1. Attributes of Reading and Writing
121
7.2.2. Length of Control and Status Registers in LA32 and LA64
121
7.2.3. Access Effects of Undefined and Unimplemented Control and Status Registers
122
7.3. Conflicts Caused by Control and Status Registers
122
7.4. Basic Control and Status Registers
122
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
7.4.1. Current Mode Information (CRMD)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
7.4.2. Pre-exception Mode Information (PRMD)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
7.4.3. Extended Component Unit Enable (EUEN)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
7.4.4. Miscellaneous Controller (MISC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
7.4.5. Exception Configuration (ECFG)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
7.4.6. Exception Status (ESTAT)
130
7.4.7. Exception Return Address (ERA)
131
7.4.8. Bad Virtual Address (BADV)
131
7.4.9. Bad Instruction (BADI)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
7.4.10. Exception Entry Base Address (EENTRY)
132
7.4.11. Reduced Virtual Address Configuration (RVACFG)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
7.4.12. CPU Identity (CPUID)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
7.4.13. Privileged Resource Configuration 1 (PRCFG1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
7.4.14. Privileged Resource Configuration 2 (PRCFG2)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
7.4.15. Privileged Resource Configuration 3 (PRCFG3)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
7.4.16. Data Save Register (SAVE)
134
7.4.17. LLBit Controller (LLBCTL)
134
7.4.18. Implementation-specific Controller 1 (IMPCTL1)
7.4.19. Implementation-specific Controller 2 (IMPCTL2)
134
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
7.4.20. Cache Tags (CTAG)
7.5. Control and Status Registers Related to Mapped Address Translation
135
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
7.5.1. TLB Index (TLBIDX)
136
7.5.2. TLB Entry High-order Bits (TLBEHI)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
7.5.3. TLB Entry Low-order Bits (TLBELO0, TLBELO1)
138
7.5.4. Address Space Identifier (ASID)
. . . . . . . . . . . . . . . 138
7.5.5. Page Global Directory Base Address for Lower Half Address Space (PGDL)
139
7.5.6. Page Global Directory Base Address for Higher Half Address Space (PGDH)
139
7.5.7. Page Global Directory Base Address (PGD)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
7.5.8. Page Walk Controller for Lower Half Address Space (PWCL)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
7.5.9. Page Walk Controller for Higher Half Address Space (PWCH)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
7.5.10. STLB Page Size (STLBPS)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
7.5.11. TLB Refill Exception Entry Base Address (TLBRENTRY)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
7.5.12. TLB Refill Exception Bad Virtual Address (TLBRBADV)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
7.5.13. TLB Refill Exception Return Address (TLBRERA)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
7.5.14. TLB Refill Exception Data Save Register (TLBRSAVE)
. . . . . . . . . . . . . . . . . . . . . 142
7.5.15. TLB Refill Exception Entry Low-order Bits (TLBRELO0, TLBRELO1)
144
7.5.16. TLB Refill Exception Entry High-order Bits (TLBREHI)
. . . . . . . . . . . . . . . . . . . . . 145
7.5.17. TLB Refill Exception Pre-exception Mode Information (TLBRPRMD)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
7.5.18. Direct Mapping Configuration Window n (DMW0-DMW3)
7.6. Control and Status Registers Related to Timers
146
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
7.6.1. Timer Identity (TID)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
7.6.2. Timer Configuration (TCFG)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
7.6.3. Timer Value (TVAL)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
7.6.4. Counter Compensation (CNTC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
7.6.5. Timer Interrupt Clearing (TICLR)
7.7. Control and Status Registers Related to RAS
148
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
7.7.1. Machine Error Controller (MERRCTL)
149
7.7.2. Machine Error Information (MERRINFO1, MERRINFO2)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
7.7.3. Machine Error Exception Entry Base Address (MERRENTRY)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
7.7.4. Machine Error Exception Return Address (MERRERA)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
7.7.5. Machine Error Exception Data Save Register (MERRSAVE)
7.8. Control and Status Registers Related to Performance Monitoring
151
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
7.8.1. Performance Monitor Configuration n (PMCFG)
151
7.8.2. Performance Monitor Overall Counter n (PMCNT)
7.9. Control and Status Registers Related to Watchpoints
152
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
7.9.1. Memory Load/Store Watchpoint Overall Controller (MWPC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
7.9.2. Memory Load/Store Watchpoint Overall Status (MWPS)
. . . . . . . . . . . . . . . . 153
7.9.3. Memory Load/Store Watchpoint n Configuration (MWPnCFG1-MWPnCFG4)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
7.9.4. Fetch Watchpoint Overall Controller (FWPC)
7.9.5. Fetch Watchpoint Overall Status (FWPS)
157
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
7.9.6. Fetch Watchpoint n Configuration (FWPnCFG1-FWPnCFG3)
7.10. Control and Status Registers Related to Debugging
159
159
7.10.1. Debug Register (DBG)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
7.10.2. Debug Exception Return Address (DERA)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
7.10.3. Debug Data Save Register (DSAVE)
Appendix A: Pseudocode Descriptions of the Function Definitions
161
A.1. Interpretation of Operators in Pseudocode
161
A.2. Pseudocode Descriptions of Functional Functions
164
A.2.1. Logical Left Shift
164
A.2.2. Logical Right Shift
165
A.2.3. Arithmetic Right Shift
165
A.2.4. Circular Right Shift
165
. . . . . . . . . . . . . . . . . . . . . 165
A.2.5. Count the Number of Consecutive 1’s Starting from High Order Bits
. . . . . . . . . . . . . . . . . . . . . 165
A.2.6. Count the Number of Consecutive 0’s Starting from High Order Bits
166
A.2.7. Count the Number of Consecutive 1’s Starting from Low Order Bits
166
A.2.8. Count the Number of Consecutive 0’s Starting from Low Order Bits
A.2.9. Reverse the Order of the Bit String
166
A.2.10. CRC-32 Checksum Calculation
166
A.2.11. Single Precision Floating-point to Signed Word Integer
167
A.2.12. Single Precision Floating-point to Signed Double Word Integer
167
A.2.13. Double Precision Floating-point to Signed Word Integer
167
A.2.14. Double Precision Floating-point to Signed Double Word Integer
168
A.2.15. Round Single Precision Floating-point
168
A.2.16. Round Double Precision Floating-point
168
Appendix B: Table of Instruction Encoding
170
List of Figures
• LoongArch components
• GR and PC
• Single-precision floating-point number format
• Double-precision floating-point number format
• Floating-point registers
• TLB entry formats
• Multi-level page table structure supported by page walking
• Table entry format for common pages
• Table entry format for huge pages
1
List of Tables
•
Typical Instruction Formats in LoongArch
•
Application-level basic integer instructions in LA32
•
The configuration information accessible by the CPUCFG instruction
•
Single-precision floating-point number calculation method
•
Double-precision floating-point number calculation method
•
Definitions of FCSR0 register fields
•
Default results of floating-point exceptions
•
Results of floating-point classification
•
Floating-point comparison conditions and judgment standards
•
Standard for converting to integer
•
Standard for floating-point conversion
•
Standard for rounding to integer
•
Operations corresponding to each op in the INVTLB instruction
•
Overview of Control and Status Registers
•
Definition of current mode information register
•
Definition of pre-exception mode information register
•
Definition of extended component unit enable register
•
Definition of miscellaneous controller register
•
Definition of exception configuration register
•
Definition of exception status register
•
Table of exception encoding
•
Definition of exception program counter register
•
Definition of bad virtual address register
•
Definition of bad instruction register
•
Definition of exception entry base address register
•
Definition of reduced virtual address configuration register
•
Definition of CPU identity register
•
Definition of privileged resource configuration 1 register
•
Definition of privileged resource configuration 2 register
•
Definition of privileged resource configuration 3 register
•
Definition of data save register
•
Definition of LLBit controller register
•
Definition of TLB index register
•
Definition of TLB entry high order bits register in LA64
•
Definition of TLB entry high order bits register in LA32
•
Definition of TLB entry low order bits in LA32
•
Definition of TLB entry low order bits in LA64
•
Definition of address space identifier register
2
•
Definition of page global directory base address for higher half address space register
•
Definition of page global directory base address for lower half address space register
•
Definition of page global directory base address register
•
Definition of page walk controller for lower half address space register
•
Definition of page walk controller for higher half address space register
•
Definition of STLB page size register
•
Definition of TLB refill exception entry base address register in LA64
•
Definition of TLB refill exception entry base address register in LA32
•
Definition of TLB refill exception bad virtual address register
•
Definition of TLB refill exception program counter register
•
Definition of TLB refill exception data save register
•
Definition of TLB refill exception entry low order bits register in LA64
•
Definition of TLB refill exception entry low order bits register in LA32
•
Definition of TLB refill exception entry high order bits register in LA64
•
Definition of TLB refill exception entry high order bits register in LA32
•
Definition of TLB refill exception pre-exception mode information register
•
Definition of direct mapping configuration window n register in LA64
•
Definition of direct mapping configuration window n register in LA32
•
Definition of timer identity register
•
Definition of timer configuration register
•
Definition of timer value register
•
Definition of counter compensation register
•
Definition of timer interrupt clearing register
•
Definition of machine error controller register
•
Definition of machine error exception entry base address register in LA64
•
Definition of machine error exception entry base address register in LA32
•
Definition of machine error exception return address register
•
Definition of machine error exception data save register
•
Definition of performance monitor configuration n register
•
Definition of performance monitor overall counter n register
•
Definition of memory load/store watchpoint overall controller register
•
Definition of memory load/store watchpoint overall status register
•
Definition of load/store watchpoint judgment process mbyten
•
Definition of load store watchpoint bytemask
•
Definition of memory load/store watchpoint n configuration 1 register
•
Definition of memory load/store watchpoint n configuration 2 register
•
Definition of memory load/store watchpoint n configuration 3 register
•
Definition of memory load/store watchpoint n configuration 4 register
•
Definition of fetch watchpoint overall controller register
•
Definition of fetch watchpoint overall status register
3
• Definition of fetch watchpoint n configuration 1 register
• Definition of fetch watchpoint n configuration 2 register
• Definition of fetch watchpoint n configuration 3 register
• Definition of fetch watchpoint n configuration 4 register
• Definition of debug data save register
• Definition of debug exception program counter register
• Definition of debug register
• Interpretation of semantic keyword
• Interpretation of bit string operators
• Interpretation of arithmetic operators
• Interpretation of comparison operators
• Interpretation of bit operators
• Interpretation of logical operators
• Operator priority
• Table of instruction encoding
4
About this manual
Copyright Statement
The copyright of this document belongs to Loongson Technology Corporation Limited. Without written
permission, no company or individualmay disclose, reproduce or otherwise distribute any part of this
document to third parties. Otherwise, they will be held legally responsible.
Disclaimer
This document provides only periodic information, and the contents contained may be updated at any time
without notice, depending on the actual situation of the product. Loongson Technology Corporation Limited
is not responsible for any direct or indirect damage aused by the improper use of the document.
Loongson Technology Corporation Limited
Building No.2, Loongson Industrial Park,
Zhongguancun Environmental Protection Park, Haidian District, Beijing
Tel: 010-62546668
Fax: 010-62600826
Reading Guide
This is the first volume of LoongArch Reference Manual, which describes the basic part of the LoongArch
architecture.
Translator’s Note
These documents were translated by Yanteng Si and Feiyang Chen.
This is the translation of https://github.com/loongson/LoongArch-Documentation/releases/latest/
download/LoongArch-Vol1-v1.00-CN.pdf.
Due to the limited knowledge of the translators, there are some inevitable errors and omissions existing in
this document, please feel free to correct.
License
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives
4.0
International License. To view a copy of this license, visit http://creativecommons.org/licenses/by-nc-nd/
4.0/ or send a letter to Creative Commons, PO Box 1866, Mountain View, CA 94042, USA.
Contributors
Since the release of the project, we have gotten several errata and content changes donated. Here are all
the people who have contributed to LoongArch Documentation as an open source project. Thank you
everyone for helping make this a better book for everyone.
The contributors are listed in alphabetical order.
Chao LI <lichao@loongson.cn>
5
Chenghua Xu <xuchenghua@loongson.cn>
Feiyang Chen <chenfeiyang@loongson.cn>
FreeFlyingSheep <fyang.168.hi@163.com>
Konstantin Romanov <konstantinsromanov@gmail.com>
LI Chao <lichao@loongson.cn>
limeidan <limeidan@loongson.cn>
liuzhensong <liuzhensong@loongson.cn>
mengqinggang <mengqinggang@loongson.cn>
Qi Hu <huqi@loongson.cn>
qmuntal <quimmuntal@gmail.com>
tangxiaolin <tangxiaolin@loongson.cn>
WANG Xuerui <git@xen0n.name>
wangguofeng <wangguofeng@loongson.cn>
Wu Xiaotian <wuxiaotian@loongson.cn>
Wu Xiaotian <yetist@gmail.com>
Xi Ruoyao <xry111@mengyan1223.wang>
Yang Yujie <yangyujie@alumni.sjtu.edu.cn>
Yang Yujie <yangyujie@loongson.cn>
Yanteng Si <siyanteng@loongson.cn>
6
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