|
|
|
FR[fd][31:0] = FP32convertToSint64(FR[fj][31:0], FCSR.Enables.I,
FCSR.RM)
FTINT.L.D:
FR[fd] = FP64convertToSint64(FR[fj], FCSR.Enables.I, FCSR.RM)
3.2.3.3. FTINT{RM/RP/RZ/RNE}.{W/L}.{S/D}
Instruction formats:
ftintrm.w.s
fd, fj
ftintrm.w.d
fd, fj
ftintrm.l.s
fd, fj
ftintrm.l.d
fd, fj
ftintrp.w.s
fd, fj
ftintrp.w.d
fd, fj
ftintrp.l.s
fd, fj
ftintrp.l.d
fd, fj
ftintrz.w.s
fd, fj
ftintrz.w.d
fd, fj
ftintrz.l.s
fd, fj
ftintrz.l.d
fd, fj
ftintrne.w.s
fd, fj
ftintrne.w.d
fd, fj
ftintrne.l.s
fd, fj
ftintrne.l.d
fd, fj
These instructions convert floating-point numbers to fixed-point numbers with the specified rounding
pattern. FTINTRM.{W/L}.{S/D} instruction selects the single-precision/double-precision floating-point
number in the floating-point register fj and converts it to integer-type long integer-type fixed point number,
and the resulting integer-type/long integer-type fixed point number is written to the floating-point register
fd, using the “round to negative infinity” mode.
FTINTRM.W.S:
FR[fd][31:0] = FP32convertToSint32(FR[fj][31:0], FCSR.Enables.I, 3)
FTINTRM.W.D:
FR[fd] = FP64convertToSint32(FR[fj], FCSR.Enables.I, 3)
FTINTRM.L.S:
FR[fd][31:0] = FP32convertToSint64(FR[fj][31:0], FCSR.Enables.I, 3)
FTINTRM.L.D:
FR[fd] = FP64convertToSint64(FR[fj], FCSR.Enables.I, 3)
82
FTINTRP.{W/L}.{S/D} instruction selects the single-precision/double-precision floating-point number in
the floating-point register fj, converts it to integer/long-integer fixed point number, and writes the
integer/long-integer fixed point number into the floating-point register fd, using the "rounding to positive
infinity" method.
FTINTRP.W.S:
FR[fd][31:0] = FP32convertToSint32(FR[fj][31:0], FCSR.Enables.I, 2)
FTINTRP.W.D:
FR[fd] = FP64convertToSint32(FR[fj], FCSR.Enables.I, 2)
FTINTRP.L.S:
FR[fd][31:0] = FP32convertToSint64(FR[fj][31:0], FCSR.Enables.I, 2)
FTINTRP.L.D:
FR[fd] = FP64convertToSint64(FR[fj], FCSR.Enables.I, 2)
FTINTRZ.{W/L}.{S/D} instruction selects the single-degree/double-precision floating-point number in
floating-point register fj, converts it to integer/long-integer fixed-point number, and writes the obtained
integer/long-integer fixed-point number to floating-point register fd, using the "rounding to zero" method.
FTINTRZ.W.S:
FR[fd][31:0] = FP32convertToSint32(FR[fj][31:0], FCSR.Enables.I, 1)
FTINTRZ.W.D:
FR[fd] = FP64convertToSint32(FR[fj], FCSR.Enables.I, 1)
FTINTRZ.L.S:
FR[fd][31:0] = FP32convertToSint64(FR[fj][31:0], FCSR.Enables.I, 1)
FTINTRZ.L.D:
FR[fd] = FP64convertToSint64(FR[fj], FCSR.Enables.I, 1)
FTINTRNE.{W/L}{S/D} instruction selects the single-precision/double-precision floating-point number in
floating-point register fj, converts it to integer long integer fixed point number, and writes the obtained
integer/long-integer fixed point number to floating-point register fd, using the "rounding to the nearest even
number" method.
FTINTRNE.W.S:
FR[fd][31:0] = FP32convertToSint32(FR[fj][31:0], FCSR.Enables.I, 0)
FTINTRNE.W.D:
FR[fd] = FP64convertToSint32(FR[fj], FCSR.Enables.I, 0)
FTINTRNE.L.S:
83
FR[fd][31:0] = FP32convertToSint64(FR[fj][31:0], FCSR.Enables.I, 0)
FTINTRNE.L.D:
FR[fd] = FP64convertToSint64(FR[fj], FCSR.Enables.I, 0)
The operations in the IEEE 754-2008 standard that the above four floating-point format conversion
operations follow are shown in the following table.
Table 11. Standard for floating-point conversion
Instruction name
Whether to report
IEEE 754-2008 Function
floating-point
imprecision exceptions
Yes
FTINTRNE.{W/L}.{S/D
convertToIntegerExactTiesToEven(x)
}
FTINTRZ.{W/L}.{S/D}
convertToIntegerExactTowardZero(x)
FTINTRP.{W/L}.{S/D}
convertToIntegerExactTowardPositive(x)
FTINTRM.{W/L}{S/D}
convertToIntegerExactTowardNegative(x)
No
FTINTRNE.{W/L}.{S/D
convertToIntegerTiesToEven(x)
}
FTINTRZ.{W/L}.{S/D}
convertToIntegerTowardZero(x)
FTINTRP{W/L}.{S/D}
convertToIntegerTowardPositive(x)
FTINTRM.{W/L}.{S/D}
convertToIntegerTowardNegative(x)
3.2.3.4. FRINT.{S/D}
Instruction formats:
frint.s
fd, fj
frint.d
fd, fj
The FRINT.{S/D} instruction selects the single-precision/double-precision floating-point number in the
floating-point register fj and converts it to a single-precision/double-precision floating-point number with
integer value, and the resulting single-precision/double-precision floating-point number is written to the
floating-point register fd. According to the different states in FCSR, this floating-point format conversion
operation follows the operation in IEEE 7542008 standard as shown in the following table.
Table 12. Standard for rounding to integer
84
Rounding mode
Whether to report
IEEE 754-2008 Function
floating-point
imprecision exceptions
Round to the nearest
Yes
roundToIntegralExact(x)
even number
Round towards zero
Round towards positive
infinity
Round towards negative
infinity
Round to the nearest
No
roundToIntegerTiesToEven(x)
even number
Round towards zero
roundToIntegerTowardZero(x)
Round towards positive
roundToIntegerTowardPositive(x)
infinity
Round towards negative
roundToInteger TowardNegative(x)
infinity
FRINT.S:
FR[fd][31:0] = FP32_roundToInteger(FR[fj], FCSR.Enables.I, FCSR.RM)
FRINT.D:
FR[fd] = FP64_roundToInteger(FR[fj], FCSR.Enables.I, FCSR.RM)
3.2.4. Floating-Point Move Instructions
3.2.4.1. FMOV.{S/D}
Instruction formats:
fmov.s
fd, fj
fmov.d
fd, fj
FMOV{S/D} writes the value of the floating-point register fj into the floating-point register fd in the single-
precision/double-precision floating-point number format. If the value of fj is not in the single-
precision/double-precision floating-point number format, the result is uncertain.
FMOV.S:
FR[fd][31:0] = FR[fj][31:0]
FMOV.D:
FR[fd] = FR[fj]
The above instruction operations are non-arithmetic and will not cause IEEE 754 exceptions, nor will they
modify the Cause and Flags fields of the floating-point control and status register.
85
3.2.4.2. FSEL
Instruction formats:
fsel
fd, fj, fk, ca
The FSEL instruction performs conditional assignment operations.
When FSEL is executed, if the value of the condition flag register ca is equal to 0, the value of the floating-
point register fj is written into the floating-point register fd, otherwise the value of the floating-point
register fk is written into the floating-point register fd.
FSEL:
FR[fd] = CFR[ca] ? FR[fk] : FR[fj]
3.2.4.3. MOVGR2FR.{W/D}, MOVGR2FRH.W
Instruction formats:
movgr2fr.w
fd, rj
movgr2fr.d
fd, rj
movgr2frh.w
fd, rj
MOVGR2FR.W writes the low 32-bit value of the general register rj into the low 32-bit of the floating-point
register fd. If the length of the floating-point register is 64 bits, the high 32-bit value of fd is uncertain.
MOVGR2FR.W:
FR[fd][31:0] = GR[rj][31:0]
MOVGR2FRH.W writes the low 32-bit value of the general register rj into the high 32-bit of the floating-point
register fd, and the low 32-bit value of the floating-point register fd remains unchanged.
MOVGR2FRH.W:
FR[fd][63:32] = GR[rj][31:0]
FR[fd][31: 0] = FR[fd][31:0]
MOVGR2FR.D writes the 64-bit value of general register rj into floating-point register fd.
MOVGR2FR.D:
FR[fd] = GR[rj]
86
3.2.4.4. MOVFR2GR.{S/D}, MOVFRH2GR.S
Instruction formats:
movfr2gr.s
rd, fj
movfr2gr.d
rd, fj
movfrh2gr.s
rd, fj
MOVFR2GRMOVFRH2GR.S sign extensions the low/high 32-bit value of the floating-point register fj and
writes it into the general register rd.
MOVFR2GR.S:
GR[rd] = SignExtend(FR[fj][31: 0], GRLEN)
MOVFRH2GR.S:
GR[rd] = SignExtend(FR[fj][63:32], GRLEN)
MOVFR2GR.D writes the 64-bit value of the floating-point register fj into the general register rd.
MOVFR2GR.D:
GR[rd] = FR[fj]
3.2.4.5. MOVGR2FCSR, MOVFCSR2GR
Instruction formats:
movgr2fcsr
fcsr, rj
movfcsr2gr
rd,
fcsr
MOVGR2FCSR modifies the value of the software writable field corresponding to the floating-point control
and status register indicated by fcsr according to the value of the lower 32 bits of the general register rj. If
the MOVGR2FCSR instruction modifies FCSR0 so that the bits of the Cause field and the corresponding
Enables bit are both 1, or modify the Enables field of FCSR1 and the Cause field of FCSR2 so that the Cause
bit and the corresponding Enables bit are both 1, the M0VGR2FCSR instruction itself No floating-point
exception will be triggered.
MOVGR2FCSR:
FCSR[fcsr] = GR[rd][31:0]
MOVFCSR2GR sign extensions the 32-bit value of the floating-point control and status register indicated by
fcsr and writes it into the general register rd.
MOVFCSR2GR:
87
GR[rd] = SignExtend(FCSR[fcsr], GRLEN)
If the floating-point control and status register indicated by fcsr in the above instruction does not exist, the
result is uncertain.
3.2.4.6. MOVFR2CF, MOVCF2FR
Instruction formats:
movfr2cf
cd, fj
movcf2fr
fd, cj
MOVFR2CF writes the value of the lowest bit of the floating-point register fj into the condition flag register
cd.
MOVFR2CF:
CFR[cd] = FR[fj][0]
MOVCF2FR writes the value of the condition flag register cj into the lowest bit of the floating-point register
fd.
MOVCF2FR:
FR[fd][0] = CFR[cj]
3.2.4.7. MOVGR2CF, MOVCF2GR
Instruction formats:
movgr2cf
cd, rj
movcf2gr
rd, cj
MOVGR2CF writes the value of the lowest bit of the general register rj into the condition flag register cd.
MOVGR2CF:
CFR[cd] = GR[rj][0]
MOVCF2GR writes the value of the condition flag register cj into the lowest bit of the general register rd
and clears the other bits.
MOVCF2GR:
GR[rd][0] = CFR[cj]
88
3.2.5. Floating-Point Branch Instructions
3.2.5.1. BCEQZ, BCNEZ
Instruction formats:
bceqz
cj, offs21
bcnez
cj, offs21
BCEQZ judges the value of the condition flag register cj, if it is equal to 0, jump to the target address,
otherwise it does not jump. BCNEZ judges the value of the condition flag register cj, if it is not equal to 0,
jump to the target address, otherwise it does not jump. The jump target address of the above two branch
instructions is to logically shift the 21-bit immediate offs21 in the instruction code to the left by 2 bits and
then sign extension, and the resulting offset value plus the PC of the branch instruction.
BCEQZ:
if CFR[cj] == 0:
PC = PC + SignExtend({offs21, 2'b0}, GRLEN)
BCNEZ:
if CFR[cj] != 0:
PC = PC + SignExtend({offs21, 2'b0}, GRLEN)
When writing assembly, you need to fill in the immediate field with the real offset value in
TIP
bytes, i.e. (offs21<<2).
3.2.6. Floating-Point Common Memory Access Instructions
3.2.6.1. FLD.{S/D}, FST.{S/D}
Instruction formats:
flds
fd, rj, si12
fld.d
fd, rj, si12
fst.s
fd, rj, si12
fst.d
fd, rj, si12
FLD.S retrieves a word of data from the internal memory and writes it into the lower 32 bits of the floating-
point register fd. If the length of the floating-point register is 64 bits, the high 32-bit value of fd is uncertain.
FLD.D retrieves a double word from the internal memory and writes it into the floating-point register fd.
FST.S writes the low 32-bit word data in the floating-point register fd into the memory.
FST.D writes double-word data in the floating-point register fd into the memory.
89
The access address of the above instruction is calculated by summing the value in the general register rj
with the symbolically expanded 12-bit immediate number si12.
FLD.{S/D} and FST.{S/D} instructions, regardless of the hardware implementation and environment
configuration, as long as the access address is naturally aligned, the non-alignment exception will not be
triggered; when the access address is not naturally aligned, if the hardware implementation supports non-
aligned access and the current computing environment is configured to allow non-aligned access, then the
non-alignment exception will not be triggered; otherwise, the non-alignment exception will be triggered.
Otherwise, the non-alignment exception will be triggered.
FLD.S:
vaddr = GR[rj] + SignExtend(si12, GRLEN)
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
word = MemoryLoad(paddr, WORD)
FR[fd][31:0] = word
FLD.D:
vaddr = GR[rj] + SignExtend(si12, GRLEN)
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
doubleword = MemoryLoad(paddr, DOUBLEWORD)
FR[fd] = doubleword
FST.S:
vaddr = GR[rj] + SignExtend(si12, GRLEN)
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
MemoryStore(FR[fd][31:0], paddr, WORD)
FST.D:
vaddr = GR[rj] + SignExtend(si12, GRLEN)
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
MemoryStore(FR[fd][63:0], paddr, DOUBLEWORD)
3.2.6.2. FLDX.{S/D}, FSTX.{S/D}
Instruction formats:
fldx.s fd, rj, rk
fldx.d fd, rj, rk
fstx.s fd, rj, rk
fstx.d fd, rj, rk
90
FLDX.S retrieves a word of data from the memory and writes it into the lower 32 bits of the floating-point
register fd. If the length of the floating-point register is 64 bits, the high 32-bit value of fd is uncertain.
FLDX.D retrieves a double word of data from the memory and writes it into the floating-point register fd.
FSTX.S writes the low 32-bit word data in the floating-point register fd into the memory.
FSTX.D writes the double word data in the floating-point register fd into the memory.
The memory access address calculation method of the above instruction is to add sum the value in the
general register rj and the value in the general register rk.
For FLDX.{S/D} and FSTX.{S/D} instructions, no matter what kind of hardware implementation and
environmental configuration, as long as the memory access address is naturally aligned, the non-aligned
exception will not be triggered; When the memory address is not naturally aligned, if the hardware
implementation supports unaligned memory access and the current computing environment is configured
to allow unaligned memory access, then the unaligned exception will not be triggered, otherwise it will
trigger the unaligned exception.
FLDX.S:
vaddr = GR[rj] + GR[rk]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
word = MemoryLoad(paddr, WORD)
FR[fd][31:0] = word
FLDX.D:
vaddr = GR[rj] + GR[rk]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
doubleword = MemoryLoad(paddr, DOUBLEWORD)
FR[fd] = doubleword
FSTX.S:
vaddr = GR[rj] + GR[rk]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
MemoryStore(FR[fd][31:0], paddr, WORD)
FSTX.D:
vaddr = GR[rj] + GR[rk]
AddressCompli anceCheck(vaddr)
paddr = AddressTranslation(vaddr)
MemoryStore(FR[fd][63:0], paddr, DOUBLEWORD)
91
3.2.7. Floating-Point Bound Check Memory Access Instructions
3.2.7.1. FLD{GT/LE}.{S/D}, FST{GT/LE}.{S/D}
Instruction formats:
fldgt.s
fd, rj, rk
fldgt.d
fd, rj, rk
fldle.s
fd, rj, rk
fldle.d
fd, rj, rk
fstgt.s
fd, rj, rk
fstgt.d
fd, rj, rk
fstle.s
fd, rj, rk
fstle.d
fd, rj, rk
FLD{GT/LE}.{S/D} determines if the valid address is out of bounds and writes the value from memory to
the floating-point register.
FLD{GT/LE}.S checks if the value in general register rj is greater/less than/equal to the value in general
register rk, and if the condition is met, fetches a word of data from memory and writes it to the lower 32
bits of floating-point register fd. If the floating-point register is 64 bits wide, the high 32-bit value of fd is
not determined.
FLD{GT/LE}.D checks if the value in general register rj is greater than/less than/equal to the value in
general register rk, and if the condition is met, fetches a double word of data from memory and writes it to
floating-point register fd.
FST{GT/LE}.{S/D} determines if the valid address is out of bounds, and writes the value of the floating-
point register to memory.
FST{GT/LE}.S checks if the value in general register rj is greater/less than/equal to the value in general
register rk, and if the condition is met, writes the low 32-bit word data in floating-point register fd to
memory.
FST{GT/LE}.D checks if the value in general register rj is greater than/less than or equal to the value in
general register rk, and if the condition is satisfied, writes the double word data in floating-point register fd
to memory.
The access address of the above instruction comes directly from the value in general register rj. The
access addresses of the above instructions are required to be naturally aligned, otherwise a non-alignment
exception will be triggered. The above instruction terminates the access operation and triggers the bound
check exception if the check condition is not satisfied.
FLDGT.S:
vaddr = GR[rj]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
if GR[rj] > GR[rk]:
word = MemoryLoad(paddr, WORD)
92
FR[fd][31:0] = word
else:
RaiseException(BCE)
# Bound Check Exception
FLDGT.D:
vaddr = GR [rj]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
if GR[rj] > GR[rk]:
FR[fd] = MemoryLoad(paddr, DOUBLEWORD)
else:
RaiseException(BCE)
# Bound Check Exception
FLDLE.S:
vaddr = GR[rj]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
if GR[rj] <= GR[rk]:
word = MemoryLoad(paddr, WORD)
FR[fd][31:0] = word
else:
RaiseException(BCE)
# Bound Check Exception
FLDLE.D:
vaddr = GR[rj]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
if GR[rj] <= GR[rk]:
FR[fd] = MemoryLoad(paddr, DOUBLEWORD)
else:
RaiseException(BCE)
# Bound Check Exception
FSTGT.S:
vaddr = GR[rj]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
if GR[rj] > GR[rk]:
MemoryStore(FR[fd][31:0], paddr, WORD)
else:
RaiseException(BCE)
# Bound Check Exception
FSTGT.D:
vaddr = GR[rij]
AddressComplianceCheck(vaddr)
93
paddr = AddressTranslation(vaddr)
if GR[rj] > GR[rk]:
MemoryStore(FR[fd][63:0], paddr, DOUBLEWORD)
else:
RaiseException(BCE)
# Bound Check Exception
FSTLE.S:
vaddr = GR[rj]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
if GR[rj] <= GR[rk]:
MemoryStore(FR[fd][31:0], paddr, WORD)
else:
RaiseException(BCE)
# Bound Check Exception
FSTLE.D:
vaddr = GR[rj]
AddressComplianceCheck(vaddr)
paddr = AddressTranslation(vaddr)
if GR[rj] <= GR[rk]:
MemoryStore(FR[fd][63:0], paddr, DOUBLEWORD)
else:
RaiseException(BCE)
# Bound Check Exception
94
Chapter 4. Overview of Privileged Resources
4.1. Privilege Levels
The processor cores are divided into four privilege levels (PLV0 to PLV3), which are uniquely determined by
the value of the PLV field in CSR.CRMD.
Among all privilege levels, PLV0 is the privilege level with the highest privilege and is the only privilege level
that can use privileged instructions and access all privileged resources. The three privilege levels, PLV1 to
PLV3, cannot execute privileged instructions to access privileged resources, but the three privilege levels
have different access rights under the MMU’s mapped address translation mode.
For Linux systems, only the PLV0 level can correspond to the kernel state in the architecture, while the
PLV3 level is recommended for the user state.
4.2. Overview of Privilege Instructions
All privileged instructions are accessible only at the PLV0 privilege level. The only exception is that when
the RPERF1/RPERF2/RPERF3 in CSR.MISC is configured to 1, the CSRRD instruction can be executed at
PLV1/PLV2/PLV3 privilege level to read the performance counter.
4.2.1. CSR Access Instructions
Instruction formats:
csrrd
rd, csr_num
csrwr
rd, csr_num
csrxchg
rd, rj, csr_num
The CSRRD, CSRWR, and CSRXCHG instructions are used to access the CSRs in software. The CSRRD
instruction writes the value of the specified CSR to the general register rd. The CSRWR instruction writes the
old value of the general register rd to the specified CSR and updates the old value of the specified CSR to
the general register rd. The CSRXCHG instruction writes the old value of the general register rd to the bits
of the specified CSR corresponding to the write mask 1 according to the write mask information stored in
the general register rj. The CSRXCHG instruction writes the old value of the general register rd to the bits
of the specified CSR corresponding to the write mask of 1 according to the write mask information stored
in the general register rj. The rest of the bits in the CSR remain unchanged, and the old value of the CSR is
updated to the general register rd.
All CSRs are addressed independently. The addressable value of the CSRs in the above instruction is
derived from the 14-bit immediate csr_num in the instruction. csr_num for CSR 0 is 0, csr_num for CSR 1
is 1, and so on.
The length of all CSR registers is either 32 bits or equal to the length of GR in the architecture, so CSR
access instructions do not distinguish between lengths. In LA32, all CSRs are naturally 32 bits wide. In
LA64, CSRs with a fixed 32-bit length in the definition are always written to the general purpose register rd
after symbolic expansion.
When a CSR access instruction accesses a CSR that is not defined in the architecture or not implemented
in hardware, the read operation returns an all 0 values and the write operation does not modify any
software-visible state of the processor.
95
4.2.2. IOCSR Access Instructions
4.2.2.1. IOCSR{RD/WR}.{B/H/W/D}
Instruction formats:
iocsrrd.b
rd, rj
iocsrrd.h
rd, rj
iocsrrd.w
rd, rj
iocsrrd.d
rd, rj
iocsrwr.b
rd, rj
iocsrwr.h
rd, rj
iocsrwr.w
rd, rj
iocsrwr.d
rd, rj
I0CSR{RD/WR}.{B/H/W/D} instructions are used to access the IOCSR.
All IOCSR registers use independent addressing space, and the basic unit of addressing is byte. All data is
stored in the IOCSR space in a little-endian storing {B/H/W/D} instruction’s IOCSR address is from the
general register rj.
The IOCSRRD.{B/H/W/D} instruction fetches byte/half-word/word/double-word length data from the
specified address in the IOCSR space, and writes it to the general register rd after symbolic expansion.
The IOCSRWR.{B/H/W/D} instruction writes the [7:0]/[15:0]/[31:0]/[63:0] bits of data in the
general register rd to the beginning of the specified address in the IOCSR space.
The IOCSRRD.D and IOCSRWR.D instructions appear only in LA64.
IOCSR registers can typically be accessed by multiple processor cores simultaneously. The execution of
IOCSR access instructions on multiple processor cores satisfies the sequential consistency condition.
4.2.3. Cache Maintenance Instructions
4.2.3.1. CACOP
Instruction formats:
cacop
op, rj, si12
The CACOP instruction is mainly used for Cache initialization and cache-consistency maintenance.
The value of the general register rj, plus the sign-extended 12-bit immediate number si12, gives the
virtual address VA used by the CACOP instruction, which is used to indicate the location of the Cache line
being operated on.
Which Cache is accessed by the CACOP instruction and what Cache operation is performed is determined
by the 5-bit op in the instruction. op[2:0] indicates the Cache object to be operated on, and op[4:3]
indicates the type of operation.
96
|
|