Intel 64 and IA-32 Architectures. Software Developer’s Manual (2026) - page 76

 

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Intel 64 and IA-32 Architectures. Software Developer’s Manual (2026) - page 76

 

 

MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
3:0
PKG_C_STATE_LIMIT
Specifies the lowest processor-specific C-state code name
(consuming the least power) for the package.
The default is set as factory-configured package C-state limit.
The following C-state code name encodings may be supported:
0000b: C0/C1 (no package C-state support)
0001b: C2
0010b: C3
0011b: C6
0100b: C7
0101b: C7s
0110b: C8
0111b: C9
1000b: C10
7:4
MAX_CORE_C_STATE
Possible values are: 0000-reserved; 0001-C1; 0010-C3,
0011-C6.
9:8
Reserved.
10
IO_MWAIT_REDIRECTION_ENABLE
When set, will map IO_read instructions sent to IO registers
PMG_IO_BASE_ADDR.PMB0+0/1/2 to MWAIT(C2,3,4) instructions;
applies to deepc4 too.
14:11
Reserved.
15
CFG_LOCK
When set, locks bits 15:0 of this register for further writes, until
the next reset occurs.
24:16
Reserved.
25
C3_STATE_AUTO_DEMOTION_ENABLE
When set, processor will conditionally demote C6/C7 requests to
C3 based on uncore auto-demote information.
26
C1_STATE_AUTO_DEMOTION_ENABLE
When set, processor will conditionally demote C3/C6/C7 requests
to C1 based on uncore auto-demote information.
27
ENABLE_C3_UNDEMOTION
Enable Un-Demotion from Demoted C3.
28
ENABLE_C1_UNDEMOTION
Enable Un-Demotion from Demoted C1.
29
ENABLE_PKGC_AUTODEMOTION
Enable Package C-State Auto-Demotion. It enables use of the
history of past package C-state depth and residence, as a factor in
determining C-State depth.
2-442 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
30
ENABLE_PKGC_UNDEMOTION
Enable Package C-State Un-Demotion. It enables considering
cases where demotion was the incorrect decision in determining
C-State depth.
31
TIMED_MWAIT_ENABLE
When set, enables Timed MWAIT feature. MWAIT would #GP on
attempts to do setup MWAIT timer if this bit is not set.
63:32
Reserved.
Register Address: E4H, 228
MSR_IO_CAPTURE_BASE
IO Capture Base (R/W)
Core
Power Management IO Redirection in C-state. See http://biosbits.org.
15:0
LVL_2_BASE_ADDRESS
Specifies the base address visible to software for IO redirection. If
MSR_PKG_CST_CONFIG_CONTROL.IO_MWAIT_REDIRECTION_ENA
BLE, reads to this address will be consumed by the power
management logic and decoded to MWAIT instructions. When IO
port address redirection is enabled, this is the IO port address
reported to the OS/software.
18:16
CST_RANGE
Specifies the encoding value of the maximum C-State code name
to be included when IO read to MWAIT redirection is enabled by
MSR_PKG_CST_CONFIG_CONTROL.IO_MWAIT_REDIRECTION_ENA
BLE:
000b-C3 is the max C-State to include.
001b-C6 is the max C-State to include.
010b-C7 is the max C-State to include.
63:19
Reserved.
Register Address: 13CH, 316
MSR_FEATURE_CONFIG
AES Feature Configuration (R/W)
Core
0
AESNI_LOCK
Once this bit is set, writes to this register will not be allowed.
1
AESNI_DISABLE
This bit disables Advanced Encryption Standard feature on this
processor core. To disable AES, BIOS will write '11 to this MSR on
every core.
63:2
Reserved.
Register Address: 140H, 320
MSR_FEATURE_ENABLES
Feature Enable (R/W)
Thread
Miscellaneous enables for thread specific features.
0
CPUID_GP_ON_CPL_GT_0
Causes CPUID to #GP if CPL greater than 0 and not in SMM.
63:1
Reserved.
Vol. 4
2-443
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 1A2H, 418
MSR_TEMPERATURE_TARGET
Temperature Target (R/W)
Package
Legacy register holding temperature related constants for Platform use.
6:0
TCC Offset Time Window
Describes the RATL averaging time window.
7
TCC Offset Clamping Bit
When enabled will allow RATL throttling below P1.
15:8
Temperature Control Offset
Fan Temperature Target Offset (a.k.a. T-Control) indicates the
relative offset from the Thermal Monitor Trip Temperature at
which fans should be engaged.
23:16
TCC Activation Temperature
The minimum temperature at which PROCHOT# will be asserted.
The value is degrees C.
30:24
TCC Activation Offset
Specifies a temperature offset in degrees C from the temperature
target (bits 23:16). PROCHOT# will assert at the offset target
temperature. Write is permitted only if
MSR_PLATFORM_INFO[30] is set.
31
LOCKED
When set, this entire register becomes read-only.
63:2
Reserved.
Register Address: 1A4H, 420
MSR_PREFETCH_CONTROL
PREFETCH Control (R/W)
Thread
Prefetch disable bits.
0
L2_HARDWARE_PREFETCHER_DISABLE
If 1, disables the L2 hardware prefetcher, which fetches
additional lines of code or data into the L2 cache.
1
L2_ADJACENT_CACHE_LINE_PREFETCHER_DISABLE
If 1, disables the adjacent cache line prefetcher, which fetches the
cache line that comprises a cache line pair (128 bytes).
2
DCU_HARDWARE_PREFETCHER_DISABLE
If 1, disables the L1 data cache prefetcher, which fetches the next
cache line into L1 data cache.
3
DCU_IP_PREFETCHER_DISABLE
If 1, disables the L1 data cache IP prefetcher, which uses
sequential load history (based on instruction pointer of previous
loads) to determine whether to prefetch additional lines.
4
DCU_NEXT_PAGE_PREFETCH_DISABLE
If 1, disables Next Page prefetcher.
5
AMP_PREFETCH_DISABLE
If 1, disables L2 Adaptive Multipath Probability (AMP) prefetcher.
2-444 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
6
LLC_PAGE_PREFETCH_DISABLE
If 1, disables the LLC Page prefetcher.
7
AOP_PREFETCH_DISABLE
8
STREAM_PREFETCH_CODE_FETCH_DISABLE
63:9
Reserved.
Register Address: 1A6H, 422
MSR_OFFCORE_RSP_0
OFFCORE_RSP_0 (R/W)
Thread
Offcore Response Event Select Register
0
TRUE_DEMAND_CACHE_LOAD
Demand Data Rd = DCU reads (includes partials) that is not tagged
homeless.
1
DEMAND_RFO
Demand Instruction fetch = IFU Fetches. ItoM or RFO that is not
tagged homeless.
2
DEMAND_CODE_READ
Demand Instruction fetch = IFU Fetches. CRd or CRd_UC.
3
CORE_MODIFIED_WRITEBACK
WBMtoI or WBMtoE.
4
HW_PREFETCH_MLC_LOAD
L2 prefetcher requests triggered by reads from MEC (except
those triggered by I-side).
5
HW_PREFETCH_MLC_RFO
L2 prefetcher requests triggered by RFOs.
6
HW_PREFETCH_MLC_CODE
L2 prefetcher requests triggered by I-side requests.
7
HW_PREFETCH_LLC_LOAD
LLC prefetch requests triggered by DRd.
8
HW_PREFETCH_LLC_RFO
LLC prefetch requests triggered by RFO.
9
HW_PREFETCH_LLC_CODE
LLC prefetch requests triggered by CRd.
10
L1_HWPREFETCH
Covers Hardware PFRFO, PFNEAR, PFMED, PFFAR, PFHW, PFNTA,
PFNPP, PFIPP including the homeless versions.
11
ALL_STREAMING_STORE
Write Combining. WCiL or WCiLF.
12
CORE_NON_MODIFIED_WB
WBEFtoI or WBEFtoE.
13
LLC_PREFETCH
LLC prefetch of load/code/RFO.
Vol. 4
2-445
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
14
L1_SWPREFETCH
Covers Software PFRFO, PFNEAR, PFMED, PFFAR, PFHW, PFNTA,
PFNPP, PFIPP including the homeless versions.
15
OTHER
Includes CLFlush, CLFlushOPT, CLDemote, CLWB, Enqueue
SetMonitor, PortIn, IntA, Lock, SplitLock, Unlock, SpCyc, ClrMonitor,
PortOut, IntPriUp, IntLog, IntPhy, EOI, RdCurr, WbStoI, LLCWBInv,
LLCInv, NOP, PCOMMIT.
16
ANY_RESP
Match on any response.
17
SUPPLIER_NONE
No Supplier Details. DATA_PRE [6:3] = 0.
18
LLC_HIT_M_STATE
LLC/L3, M-state, DATA_PRE [6:3] = 2.
19
LLC_HIT_E_STATE
LLC/L3, E-state, DATA_PRE [6:3] = 4.
20
LLC_HIT_S_STATE
LLC/L3, S-state, DATA_PRE [6:3] = 6.
21
LLC_HIT_F_STATE
LLC/L3, F-state, DATA_PRE [6:3] = 8.
22
FAR_MEM_LOCAL
Far Memory, Local, DATA_PRE [6:3] = 1.
23
FAR_MEM_REMOTE_0_HOP
Far Memory, Remote 0-hop, DATA_PRE [6:3] = 3.
24
FAR_MEM_REMOTE_1_HOP
Far Memory, Remote 1-hop, DATA_PRE [6:3] = 5.
25
FAR_MEM_REMOTE_2_PLUS_HOP
Far Memory, Rem 2+ hop, DATA_PRE [6:3] = 7.
26
NEAR_MEM_MISS_LOCAL_NODE
LLC Miss Local Node. Near Memory, Local DATA_PRE [6:3] = E.
27
NEAR_MEM_REMOTE_0_HOP
Near Memory, Remote 0-hop, DATA_PRE [6:3] = B
28
NEAR_MEM_REMOTE_1_HOP
Near Memory, Remote 1-hop, DATA_PRE [6:3] = D.
29
NEAR_MEM_REMOTE_2_PLUS_HOP
Near Memory, Remote 2+ hop, DATA_PRE [6:3] = F.
30
SPL_HIT
Snoop Info: SPL-hit, DATA_PRE [2:0] = 6.
31
SNOOP_NONE
No details as to Snoop-related info. Snoop Info: None, DATA_PRE
[2:0] = 0.
2-446 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
32
NOT_NEEDED
No snoop was needed to satisfy the request. Snoop Info: Not
needed, DATA_PRE [2:0] = 1.
33
MISS
No snoop was needed to satisfy the request. Snoop Info: Miss,
DATA_PRE [2:0] = 2.
34
HIT_NO_FWD
A snoop was needed and it Hits in at least one snooped cache. Hit
denotes a cache-line was valid before snoop effect. Snoop Info:
Hit No Fwd, DATA_PRE [2:0] = 3.
35
HIT_EF_WITH_FWD
A snoop was needed and data was Forwarded from a remote
socket. Snoop Info: Hit EF w/Fwd, DATA_PRE [2:0] = 4.
36
HITM
A snoop was needed and it HitMed in local or remote cache. HitM
denotes a cache-line was modified before snoop effect. Snoop
Info: HitM, DATA_PRE [2:0] = 5.
37
NON_DRAM
Target was non-DRAM system address. Snoop Info: HitM,
DATA_PRE [2:0] = 5.
38
GO_ERR
GO-ERR, RspData[3:0] = 0100.
39
GO_NO_GO
GO-NoGO, RspData[3:0] = 0111.
40
INPKG_MEM_LOCAL
In-package Memory, Local, DATA_PRE [6:3] = 9.
41
INPKG_MEM_NONLOCAL
In-package Memory, Non-Local, DATA_PRE [6:3] = C.
43:42
Reserved.
44
UC_LOAD
PRd or UCRdF.
45
UC_STORE
WiL.
46
PARTIAL_STREAMING_STORES
WCiL.
47
FULL_STREAMING_STORES
WCiLF.
48
L1_MODIFIED_WB
EVICTION EXTTYPE from MEC.
49
L2_MODIFIED_WB
WBMtoI or WBMtoE.
Vol. 4
2-447
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
50
PSMI
MemPushWr_NS (PSMI only).
51
ITOM
ItoM.
63:52
Reserved.
Register Address: 1A7H, 423
MSR_OFFCORE_RSP_1
OFFCORE_RSP_1 (R/W)
Thread
Offcore Response Event Select Register. See MSR_OFFCORE_RSP_0 (at1A6H).
Register Address: 1AAH, 426
MSR_MISC_PWR_MGMT
Miscellaneous Power Management Control (R/W)
Package
Various model-specific features enumeration. See http://biosbits.org.
0
Reserved.
1
ENABLE_HWP_VOTING_RIGHT
When set (1), The CPU will take into account thread HWP requests
for threads that have voting rights only (ignores thread requests
if they do not have voting rights). When reset(0), The CPU will
take into account all thread HWP requests, even for threads that
don't have voting rights. Setting this bit will cause the HWP Base
feature bit to be reported in CPUID as present; clearing will cause
it to be reported as non-present.
5:2
Reserved.
6
ENABLE_HWP
Setting this bit will cause the HWP Base feature bit to report as
present in CPUID; clearing this bit will cause CPUID to report the
feature as non-present.
7
ENABLE_HWP_INTERRUPT
Setting this bit will cause the HWP Interrupt feature
CPUID.06H:EAX[8] bit to report as present; clearing will report as
non-present.
8
ENABLE_OUT_OF_BAND_AUTONOMOUS
Setting this bit will cause the HWP Autonomous feature bit to
report as present; clearing will report as non-present.
11:9
Reserved.
12
ENABLE_HWP_EPP
Enable HWP EPP. Setting this bit (1) will cause the HWP
CPUID.06H:EAX[10] Energy Performance Preference bit to report
as present (1); clearing will report as non-present (0).
13
LOCK
Setting this bit will prevent the BIOS specific bits from changing
until the next reset. i.e., only Bits [0,22] which are meant for OS
use can be changed once the LOCK bit is set.
63:14
Reserved.
Register Address: 1ADH, 429
MSR_PRIMARY_TURBO_RATIO_LIMIT
2-448 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Primary Maximum Turbo Ratio Limit (R/W)
Package
Software can configure these limits when MSR_PLATFORM_INFO[28] = 1. Specifies Maximum Ratio Limit for each
group. Maximum ratio for groups with more cores must decrease monotonically.
7:0
MAX_TURBO_GROUP_0:
Maximum turbo ratio limit with 1 core active.
15:8
MAX_TURBO_GROUP_1:
Maximum turbo ratio limit with 2 cores active.
23:16
MAX_TURBO_GROUP_2:
Maximum turbo ratio limit with 3 cores active.
31:24
MAX_TURBO_GROUP_3:
Maximum turbo ratio limit with 4 cores active.
39:32
MAX_TURBO_GROUP_4:
Maximum turbo ratio limit with 5 cores active.
47:40
MAX_TURBO_GROUP_5:
Maximum turbo ratio limit with 6 cores active.
55:48
MAX_TURBO_GROUP_6:
Maximum turbo ratio limit with 7 cores active.
63:56
MAX_TURBO_GROUP_7:
Maximum turbo ratio limit with 8 cores active.
Register Address: 1F1H, 497
MSR_CRASHLOG_CONTROL
Crash Log Control (R/W)
Thread
Write data to a Crash Log configuration.
0
CDDIS
CrashDump_Disable: If set, indicates that Crash Dump is disabled.
1
EN_GPRS
Collect GPRs on a crash dump. Only meaningful when CDDIS is
zero.
2
EN_GPRS_IN_SMM
Collect GPRs in SMM on a crash dump. Only meaningful when
CDDIS is zero. EN_GPRS will override this control,
3
TRIPLE_FAULT_SHUTDOWN
Collect a crash log on a triple fault shutdown. Only meaningful
when CDDIS is zero.
63:4
Reserved.
Register Address: 1F5H, 501
MSR_PRMRR_PHYS_MASK
Processor Reserved Memory Range Register - Physical Mask (R/W)
Core
9:0
Reserved.
10
LOCK
Once set, this bit prevents software from modifying the PRMRR.
Vol. 4
2-449
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
11
VALID
This bit serves as the enable for the PRMRR; the PRMRR must be
LOCKed before it can be enabled.
19:12
Reserved.
45:20
MASK
PRMRR Address Mask.
63:46
Reserved.
Register Address: 1FCH, 508
MSR_POWER_CTL
Power Control Register (R/W)
Package
See http://biosbits.org.
0
ENABLE_BIDIR_PROCHOT
Used to enable or disable the response to PROCHOT# input.
When set/enabled, the platform can force the CPU to throttle to a
lower power condition such as Pn/Pm by asserting prochot#.
When clear/disabled (default), the CPU ignores the status of the
prochot input signal.
1
C1E_ENABLE
When set to '1', will enable the CPU to switch to the Minimum
Enhanced Intel SpeedStep Technology operating point when all
execution cores enter MWAIT (C1).
2
SAPM_IMC_C2_POLICY
This bit determines if self-refresh activation is allowed when
entering Package C2 State. If it is set to 0b, PCODE will keep the
FORCE_SR_OFF bit asserted in Package C2 State and allow its
negation according to the defined latency negotiations with the
PCH and Display Engine in Package C3 and deeper states.
Otherwise, self-refresh is allowed in Package C2 State.
3
FAST_BRK_SNP_EN
This bit controls the VID swing rate for the OTHER_SNP_WAKE
events that are detected by the iMPH. This is the event that is
detected by the iMPH when a non-DMI snoopable request is
observed while UCLK domain is not functional.
0b: Use slow VID swing rate.
1b: Use fast VID swing rate.
17:4
Reserved.
18
PWR_PERF_PLTFRM_OVR
Power performance platform override.
2-450 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
19
EE_TURBO_DISABLE
Setting this bit disables the P-States energy efficiency
optimization. Default value is 0. Disable/enable the energy
efficiency optimization in P-State legacy mode (when
IA32_PM_ENABLE[HWP_ENABLE] = 0), has an effect only in the
turbo range or into PERF_MIN_CTL value if it is not zero set. In
HWP mode (IA32_PM_ENABLE[HWP_ENABLE] == 1), has an
effect between the OS desired or OS maximize to the OS minimize
performance setting.
20
RTH_DISABLE
Setting this bit disables the Race to Halt optimization and avoids
this optimization limitation to execute below the most efficient
frequency ratio. Default value is 0 for processors that support
Race to Halt optimization.
21
DIS_PROCHOT_OUT
Prochot output disable.
22
PROCHOT_RESPONSE
Prochhot configurable response enable.
23
VR_THERM_ALERT_DISABLE_LOCK
When set to 1, locks PROCHOT related bits of this MSR. Once set,
a reset is required to clear this bit.
24
VR_THERM_ALERT_DISABLE
When set to 1, disables the VR_THERMAL_ALERT signaling.
25
DISABLE_RING_EE
Disable Ring EE.
26
DISABLE_SA_OPTIMIZATION
Disable SA optimization.
27
DISABLE_OOK
Disable OOK.
28
DISABLE_AUTONOMOUS
Disable HWP autonomous mode.
29
Reserved.
30
CSTATE_PREWAKE_DISABLE
C-state pre-wake disable.
63:31
Reserved.
Register Address: 2A0H, 672
MSR_PRMRR_BASE_0
Processor Reserved Memory Range Register - Physical Base Control Register (R/W)
Core
2:0
MEMTYPE
Memory type for PRMRR accesses.
3
CONFIGURED
PRMRR base configured.
19:4
Reserved.
Vol. 4
2-451
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
45:20
BASE
PRMRR base address.
63:46
Reserved.
Register Address: 474H, 1140
IA32_MC29_CTL
MC29_CTL. See Table 2-2.
Package
Register Address: 475H, 1141
IA32_MC29_STATUS
MC29_STATUS. See Table 2-2.
Package
Register Address: 476H, 1142
IA32_MC29_ADDR
MC29_ADDR. See Table 2-2.
Package
Register Address: 477H, 1143
IA32_MC29_MISC
MC29_MISC. See Table 2-2.
Package
Register Address: 478H, 1144
IA32_MC30_CTL
MC30_CTL. See Table 2-2.
Package
Register Address: 479H, 1145
IA32_MC30_STATUS
MC30_STATUS. See Table 2-2.
Package
Register Address: 47AH, 1146
IA32_MC30_ADDR
MC30_ADDR. See Table 2-2.
Package
Register Address: 47BH, 1147
IA32_MC30_MISC
MC30_MISC. See Table 2-2.
Package
Register Address: 47CH, 1148
IA32_MC31_CTL
MC31_CTL. See Table 2-2.
Package
Register Address: 47DH, 1149
IA32_MC31_STATUS
MC31_STATUS. See Table 2-2.
Package
Register Address: 47EH, 1150
IA32_MC31_ADDR
MC31_ADDR. See Table 2-2.
Package
Register Address: 47FH, 1151
IA32_MC31_MISC
MC31_MISC. See Table 2-2.
Package
Register Address: 4E0H, 1248
MSR_SMM_FEATURE_CONTROL
Enhanced SMM Feature Control (R/W)
Package
Reports SMM capability enhancement.
0
LOCK
When set, locks this register from further changes.
1
SMM_CPU_SAVE_EN
If 0, SMI/RSM will save/restore state in SMRAM
If 1, SMI/RSM will save/restore state from SRAM.
2-452 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
2
SMM_CODE_CHK_EN
When clear (default) none of the logical processors are prevented
from executing SMM code outside the ranges defined by the
SMRR. When set, any logical processor in the package that
attempts to execute SMM code not within the ranges defined by
the SMRR will assert an unrecoverable MCE.
63:3
Reserved.
Register Address: 601H, 1537
MSR_VR_CURRENT_CONFIG
Power Limit 4 (PL4) (R/W)
Package
Package-level maximum power limit (in Watts). It is a proactive, instantaneous limit.
15:0
CURRENT_LIMIT
PL4 Value in 0.125 A increments. This field is locked by
MSR_VR_CURRENT_CONFIG.LOCK. When the LOCK bit is set to 1,
this field becomes Read Only.
30:16
Reserved.
31
LOCK
This bit will lock the CURRENT_LIMIT settings in this register and
will also lock this setting. This means that once set to 1, the
CURRENT_LIMIT setting and this bit become Read Only until the
next Warm Reset.
63:32
Reserved.
Register Address: 620H, 1568
MSR_UNCORE_RATIO_LIMIT
Uncore Ratio Limit (R/W)
Package
Min/Max Ratio Limits for Uncore LLC and Ring.
6:0
MAX_CLR_RATIO
Maximum allowed ratio for the Ring and Last Level Cache (LLC).
7
Reserved.
14:8
MIN_CLR_RATIO
Minimum allowed ratio for the Ring and Last Level Cache (LLC).
63:15
Reserved.
Register Address: 638H, 1592
MSR_PP0_POWER_LIMIT
MSR_PP0_POWER_LIMIT (R/W)
Package
PP0 RAPL power unit control.
14:0
IA_PP_PWR_LIM
This is the power limitation on the IA cores power plane.
The unit of measurement is defined in
PACKAGE_POWER_SKU_UNIT_MSR[PWR_UNIT].
15
PWR_LIM_CTRL_EN
This bit must be set in order to limit the power of the IA cores
power plane.
0b: IA cores power plane power limitation is disabled.
1b: IA cores power plane power limitation is enabled.
Vol. 4
2-453
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
16
PP_CLAMP_LIM
Power Plane Clamping limitation; allow going below P1.
0b: PBM is limited between P1 and P0.
1b: PBM can go below P1.
23:17
CTRL_TIME_WIN
x = CTRL_TIME_WIN[23:22]
y = CTRL_TIME_WIN[21:17]
The timing interval window is Floating Point number given by 1.x
* power(2,y).
The unit of measurement is defined in
PACKAGE_POWER_SKU_UNIT_MSR[TIME_UNIT].
The maximal time window is bounded by
PACKAGE_POWER_SKU_MSR[PKG_MAX_WIN]. The minimum time
window is 1 unit of measurement (as defined above).
30:24
Reserved.
31
PP_PWR_LIM_LOCK
When set, all settings in this register are locked and are treated as
Read Only.
63:32
Reserved.
Register Address: 64FH, 1615
MSR_CORE_PERF_LIMIT_REASONS
Core Performance Limit Reasons
Package
Indicator of Frequency Clipping in Processor Cores. (Frequency refers to processor core frequency.)
0
PROCHOT (R/O)
PROCHOT Status. When set, frequency is reduced below the
operating system request due to assertion of external PROCHOT.
1
THERMAL (R/O)
Thermal Status. When set, frequency is reduced below the
operating system request due to a thermal event.
3:2
Reserved.
4
RSR_LIMIT (R/O)
Residency State Regulation Status. When set, frequency is
reduced below the operating system request due to residency
state regulation limit.
5
RATL (R/O)
Running Average Thermal Limit Status. When set, frequency is
reduced below the operating system request due to Running
Average Thermal Limit (RATL).
6
VR_THERMALERT (R/O)
VR Therm Alert Status. When set, frequency is reduced below the
operating system request due to a thermal alert from a processor
Voltage Regulator (VR).
2-454 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
7
VR_TDC (R/O)
VR Therm Design Current Status. When set, frequency is reduced
below the operating system request due to VR thermal design
current limit.
8
OTHER (R/O)
Other Status. When set, frequency is reduced below the operating
system request due to electrical or other constraints.
9
Reserved.
10
PBM_PL1 (R/O)
Package/Platform-Level Power Limiting PL1 Status. When set,
frequency is reduced below the operating system request due to
package/platform-level power limiting PL1.
11
PBM_PL2 (R/O)
Package/Platform-Level PL2 Power Limiting Status. When set,
frequency is reduced below the operating system request due to
package/platform-level power limiting PL2/PL3.
12
MAX_TURBO_LIMIT (R/O)
Max Turbo Limit Status. When set, frequency is reduced below
the operating system request due to multi-core turbo limits.
13
TURBO_ATTEN (R/O)
Turbo Transition Attenuation Status. When set, frequency is
reduced below the operating system request due to Turbo
transition attenuation. This prevents performance degradation
due to frequent operating ratio changes.
15:14
Reserved.
16
PROCHOT_LOG (R/W)
PROCHOT Log. When set, indicates that the PROCHOT Status bit
has asserted since the log bit was last cleared. This log bit will
remain set until cleared by software writing 0.
17
THERMAL_LOG (R/W)
Thermal Log When set, indicates that the Thermal Status bit has
asserted since the log bit was last cleared. This log bit will remain
set until cleared by software writing 0.
19:18
Reserved.
20
RSR_LIMIT_LOG (R/W)
Residency State Regulation Log. When set, indicates that the
Residency State Regulation Status bit has asserted since the log
bit was last cleared. This log bit will remain set until cleared by
software writing 0.
21
RATL_LOG (R/W)
Running average thermal limit Log, RW, When set by PCODE
indicates that Running average thermal limit has cause IA
frequency clipping. Software should write to this bit to clear the
status in this bit.
Vol. 4
2-455
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
22
VR_THERMALERT_LOG (R/W)
VR Therm Alert Log. When set, indicates that the VR Therm Alert
Status bit has asserted since the log bit was last cleared. This log
bit will remain set until cleared by software writing 0.
23
VR_TDC_LOG (R/W)
VR Thermal Design Current Log. When set, indicates that the VR
TDC Status bit has asserted since the log bit was last cleared. This
log bit will remain set until cleared by software writing 0.
24
OTHER_LOG (R/W)
Other Log. When set, indicates that the Other Status bit has
asserted since the log bit was last cleared. This log bit will remain
set until cleared by software writing 0.
25
Reserved.
26
PBM_PL1_LOG (R/W)
Package/Platform-Level PL1 Power Limiting Log. When set,
indicates that the Package or Platform Level PL1 Power Limiting
Status bit has asserted since the log bit was last cleared. This log
bit will remain set until cleared by software writing 0.
27
PBM_PL2_LOG (R/W)
Package/Platform-Level PL2 Power Limiting Log. When set,
indicates that the Package or Platform Level PL2/PL3 Power
Limiting Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
28
MAX_TURBO_LIMIT_LOG (R/W)
Max Turbo Limit Log. When set, indicates that the Max Turbo Limit
Status bit has asserted since the log bit was last cleared. This log
bit will remain set until cleared by software writing 0.
29
TURBO_ATTEN_LOG (R/W)
Turbo Transition Attenuation Log. When set, indicates that the
Turbo Transition Attenuation Status bit has asserted since the log
bit was last cleared. This log bit will remain set until cleared by
software writing 0.
63:30
Reserved.
Register Address: 650H, 1616
MSR_SECONDARY_TURBO_RATIO_LIMIT
Secondary Maximum Turbo Ratio Limit (R/W)
Package
Software can configure these limits when MSR_PLATFORM_INFO[28] = 1.
Specifies Maximum Ratio Limit for each group. Maximum ratio for groups with more cores must decrease
monotonically.
7:0
MAX_TURBO_GROUP_0:
Maximum turbo ratio limit with 1 core active.
15:8
MAX_TURBO_GROUP_1:
Maximum turbo ratio limit with 2 cores active.
23:16
MAX_TURBO_GROUP_2:
Maximum turbo ratio limit with 3 cores active.
2-456 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
31:24
MAX_TURBO_GROUP_3:
Maximum turbo ratio limit with 4 cores active.
39:32
MAX_TURBO_GROUP_4:
Maximum turbo ratio limit with 5 cores active.
47:40
MAX_TURBO_GROUP_5:
Maximum turbo ratio limit with 6 cores active.
55:48
MAX_TURBO_GROUP_6:
Maximum turbo ratio limit with 7 cores active.
63:56
MAX_TURBO_GROUP_7:
Maximum turbo ratio limit with 8 cores active.
Register Address: 65CH, 1628
MSR_PLATFORM_POWER_LIMIT
Platform Power Limit Control (R/W)
Package
Allows platform BIOS to limit power consumption of the platform devices to the specified values. The Long Duration
power consumption is specified via Platform_Power_Limit_1 and Platform_Power_Limit_1_Time. The Short Duration
power consumption limit is specified via the Platform_Power_Limit_2 with duration chosen by the processor. The
processor implements an exponential-weighted algorithm in the placement of the time windows.
14:0
POWER_LIMIT_1
Average Power limit value which the platform must not exceed
over a time window as specified by Power_Limit_1_TIME field.
The default value is the Thermal Design Power (a.k.a TDP) and
varies with product skus. The unit is specified in
MSR_RAPLPOWER_UNIT.
15
POWER_LIMIT_1_EN
When set, enables the processor to apply control policy such that
the platform power does not exceed Platform Power limit 1 over
the time window specified by Power Limit 1 Time Window.
16
CRITICAL_POWER_CLAMP_1
When set, allows the processor to go below the OS requested P
states in order to maintain the power below specified Platform
Power Limit 1 value.
23:17
POWER_LIMIT_1_TIME
Specifies the duration of the time window over which Platform
Power Limit 1 value should be maintained for sustained long
duration. This field is made up of two numbers from the following
equation:
Time Window = (float) ((1+(X/4))*(2^Y)), where:
X = POWER_LIMIT_1_TIME[23:22]
Y = POWER_LIMIT_1_TIME[21:17]
The maximum allowed value in this field is defined in
MSR_PKG_POWER_INFO[PKG_MAX_WIN].
The default value is 0DH, The unit is specified in
MSR_RAPLPOWER_UNIT[Time Unit]
31:24
Reserved.
Vol. 4
2-457
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
46:32
POWER_LIMIT_2
Average Power limit value which the platform must not exceed
over the Short Duration time window chosen by the processor.
The recommended default value is 1.25 times the Long Duration
Power Limit (i.e., Platform Power Limit 1).
47
POWER_LIMIT_2_EN
When set, enables the processor to apply control policy such that
the platform power does not exceed Platform Power limit 2 over
the Short Duration time window.
48
CRITICAL_POWER_CLAMP_2
When set, allows the processor to go below the OS requested P
states in order to maintain the power below specified Platform
Power Limit 2 value.
62:49
Reserved.
63
LOCK
Setting this bit will lock all other bits of this MSR until system
RESET.
Register Address: 6BOH, 1712
MSR_GRAPHICS_PERF_LIMIT_REASONS
MSR_GRAPHICS_PERF_LIMIT_REASONS
Package
Indicator of Frequency Clipping in the Processor Graphics. (Frequency refers to processor graphics frequency.)
0
PROCHOT (R/O)
PROCHOT Status. When set, frequency is reduced due to
assertion of external PROCHOT.
1
THERMAL (R/O)
Thermal Status. When set, frequency is reduced due to a thermal
event.
4:2
Reserved.
5
RATL (R/O)
Running Average Thermal Limit Status. When set, frequency is
reduced due to running average thermal limit.
6
VR_THERMALERT (R/O)
VR Therm Alert Status. When set, frequency is reduced due to a
thermal alert from a processor Voltage Regulator.
7
VR_TDC (R/O)
VR Thermal Design Current Status. When set, frequency is
reduced due to VR TDC limit.
8
OTHER (R/O)
Other Status. When set, frequency is reduced due to electrical or
other constraints.
9
Reserved.
2-458 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
10
PBM_PL1 (R/O)
Package/Platform-Level Power Limiting PL1 Status. When set,
frequency is reduced due to package/platform-level power
limiting PL1.
11
PBM_PL2 (R/O)
Package/Platform-Level PL2 Power Limiting Status. When set,
frequency is reduced due to package/platform-level power
limiting PL2/PL3.
12
INEFFICIENT_OPERATION (R/O)
Inefficient Operation Status. When set, processor graphics
frequency is operating below target frequency.
15:13
Reserved.
16
PROCHOT_LOG (R/W)
PROCHOT Log. When set, indicates that the PROCHOT Status bit
has asserted since the log bit was last cleared. This log bit will
remain set until cleared by software writing 0.
17
THERMAL_LOG (R/W)
Thermal Log. When set, indicates that the Thermal Status bit has
asserted since the log bit was last cleared. This log bit will remain
set until cleared by software writing 0.
20:18
Reserved.
21
RATL_LOG (R/W)
Running Average Thermal Limit Log. When set, indicates that the
RATL Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
22
VR_THERMALERT_LOG (R/W)
VR Therm Alert Log. When set, indicates that the VR Therm Alert
Status bit has asserted since the log bit was last cleared. This log
bit will remain set until cleared by software writing 0.
23
VR_TDC_LOG (R/W)
VR Thermal Design Current Log. When set, indicates that the VR
Therm Alert Status bit has asserted since the log bit was last
cleared. This log bit will remain set until cleared by software
writing 0.
24
OTHER_LOG (R/W)
Other Log. When set, indicates that the OTHER Status bit has
asserted since the log bit was last cleared. This log bit will remain
set until cleared by software writing 0.
25
Reserved.
26
PBM_PL1_LOG (R/W)
Package/Platform-Level PL1 Power Limiting Log. When set,
indicates that the Package/Platform Level PL1 Power Limiting
Status bit has asserted since the log bit was last cleared. This log
bit will remain set until cleared by software writing 0.
Vol. 4
2-459
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
27
PBM_PL2_LOG (R/W)
Package/Platform-Level PL2 Power Limiting Log. When set,
indicates that the Package/Platform Level PL2 Power Limiting
Status bit has asserted since the log bit was last cleared. This log
bit will remain set until cleared by software writing 0.
28
INEFFICIENT_OPERATION_LOG (R/W)
Inefficient Operation Log. When set, indicates that the Inefficient
Operation Status bit has asserted since the log bit was last
cleared. This log bit will remain set until cleared by software
writing 0.
63:29
Reserved.
Register Address: 6B1H, 1713
MSR_RING_PERF_LIMIT_REASONS
MSR_RING_PERF_LIMIT_REASONS
Package
Indicator of Frequency Clipping in the Ring Interconnect. (Frequency refers to ring interconnect in the uncore.)
0
PROCHOT (R/O)
PROCHOT Status. When set, frequency is reduced due to
assertion of external PROCHOT.
1
THERMAL (R/O)
Thermal Status. When set, frequency is reduced due to a thermal
event.
4:2
Reserved.
5
RATL (R/O)
Running Average Thermal Limit Status. When set, frequency is
reduced due to running average thermal limit.
6
VR_THERMALERT (R/O)
VR Therm Alert Status. When set, frequency is reduced due to a
thermal alert from a processor Voltage Regulator.
7
VR_TDC (R/O)
VR Thermal Design Current Status. When set, frequency is
reduced due to VR TDC limit.
8
OTHER (R/O)
Other Status. When set, frequency is reduced due to electrical or
other constraints.
9
Reserved.
10
PBM_PL1 (R/O)
Package/Platform-Level Power Limiting PL1 Status. When set,
frequency is reduced due to package/platform-level power
limiting PL1.
11
PBM_PL2 (R/O)
Package/Platform-Level PL2 Power Limiting Status. When set,
frequency is reduced due to package/platform-level power
limiting PL2/PL3.
15:12
Reserved.
2-460 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
16
PROCHOT_LOG (R/W)
PROCHOT Log. When set, indicates that the PROCHOT Status bit
has asserted since the log bit was last cleared. This log bit will
remain set until cleared by software writing 0.
17
THERMAL_LOG (R/W)
Thermal Log. When set, indicates that the Thermal Status bit has
asserted since the log bit was last cleared. This log bit will remain
set until cleared by software writing 0.
20:18
Reserved.
21
RATL_LOG (R/W)
Running Average Thermal Limit Log. When set, indicates that the
RATL Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
22
VR_THERMALERT_LOG (R/W)
VR Therm Alert Log. When set, indicates that the VR Therm Alert
Status bit has asserted since the log bit was last cleared. This log
bit will remain set until cleared by software writing 0.
23
VR_TDC_LOG (R/W)
VR Thermal Design Current Log. When set, indicates that the VR
Therm Alert Status bit has asserted since the log bit was last
cleared. This log bit will remain set until cleared by software
writing 0.
24
OTHER_LOG (R/W)
Other Log. When set, indicates that the OTHER Status bit has
asserted since the log bit was last cleared. This log bit will remain
set until cleared by software writing 0.
25
Reserved.
26
PBM_PL1_LOG (R/W)
Package/Platform-Level PL1 Power Limiting Log. When set,
indicates that the Package/Platform Level PL1 Power Limiting
Status bit has asserted since the log bit was last cleared. This log
bit will remain set until cleared by software writing 0.
27
PBM_PL2_LOG (R/W)
Package/Platform-Level PL2 Power Limiting Log. When set,
indicates that the Package/Platform Level PL2 Power Limiting
Status bit has asserted since the log bit was last cleared. This log
bit will remain set until cleared by software writing 0.
63:28
Reserved.
Register Address: 9FBH, 2555
IA32_TME_CLEAR_SAVED_KEY
IA32_TME_CLEAR_SAVED_KEY (R/W)
Package
See Table 2-2.
Register Address: 9FFH, 2559
MSR_CORE_MKTME_ACTIVATE
MSR_CORE_MKTME_ACTIVATE (R/O)
Core
MSR to read TME_ACTIVATE[MK_TME_KEYID_BITS].
Vol. 4
2-461
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
31:0
Reserved.
35:32
READ_MK_TME_KEYID_BITS
This value will be returned on a RDMSR, but must be zero on a
WRMSR.
39:36
TDX_RESERVED_KEYID_BITS (read only)
The number of key identifier bits allocated to TDX usage.
This is a read-only field and must be zero on a WRMSR.
63:40
Reserved.
The MSRs listed in Table 2-54 are unique to the Intel Core Ultra 7 processor P-core. These MSRs are not supported
on the processor E-core.
Table 2-54. MSRs Supported by the Intel® Core™ Ultra 7 Processor P-core
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 30CH, 780
IA32_FIXED_CTR3
Fixed-Function Performance Counter 3 (R/W)
Thread
47:0
FIXED_COUNTER
Top-down Microarchitecture Analysis unhalted number of available
slots counter.
63:48
Reserved.
Register Address: 329H, 809
MSR_PERF_METRICS
Performance Metrics (R/W)
Thread
This register provides built-in support for Top-down Micro-architecture Analysis (TMA) metrics. It exposes the four
TMA Level 1 metrics where the lower 32 bits are divided into four 8 bit fields, each of which is an integer percentage
of the total TOPDOWN.SLOTS (as reported by fixed counter 3).
7:0
RETIRING
Percent of utilized by uops that eventually retire (commit).
15:8
BAD_SPECULATION
Percent of Wasted due to incorrect speculation, covering Utilized by
uops that do not retire, or Recovery Bubbles (unutilized slots).
23:16
FRONTEND_BOUND
Percent of Unutilized slots where Front-end did not deliver a uop
while Back-end is ready.
31:24
BACKEND_BOUND
Percent of Unutilized slots where a uop was not delivered to Back-
end due to lack of Back-end resources.
39:32
MULTI_UOPS
Frontend bound.
47:40
BRANCH_MISPREDICTS
Frontend bound.
2-462 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-54. MSRs Supported by the Intel® Core™ Ultra 7 Processor P-core (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
55:48
FRONTEND_LATENCY
Frontend bound.
63:56
MEMORY_BOUND
Frontend bound.
Register Address: 540H, 1344
MSR_THREAD_UARCH_CTL
Thread Microarchitectural Control (R/W)
Thread
See Table 2-47.
Register Address: 541H, 1345
MSR_CORE_UARCH_CTL
Core Microarchitecture Control MSR (R/W)
Core
See Table 2-44.
The MSRs listed in Table 2-48 are unique to the Intel Core Ultra 7 processor E-core. These MSRs are not supported
on the processor P-core.
Table 2-55. MSRs Supported by the Intel® Core™ Ultra 7 Processor E-core
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 4F0H, 1264
MSR_SAF_CTRL
SAF Control (W/O)
Package
Extension to SAF.
0
INVALIDATE_CURRENT_STRIDE
Invalidate all chunks in current stride.
63:1
Reserved.
Register Address: D18H-D1FH, 3352-3359
IA32_L2_MASK_[8-15]
IA32_L2_MASK_[8-15] (R/W)
Module
If CPUID.10H.01H:EDX.CAT_MAX_CLOS[15:0] ≥ 0.
Controls MLC (L2) Intel RDT allocation. For more details on CAT/RDT, see Chapter 20, “Debug, Branch Profile, TSC, and
Intel® Resource Director Technology (Intel® RDT) Features.”
15:0
WAY_MASK
Capacity Bit Mask. Available ways vectors for class of service of
IA core. '1 in bit indicates allocation to the way is allowed. '0
indicates allocation to the way is not allowed.
31:16
Reserved.
Register Address: 1309H-130BH, 4873-4875
MSR_RELOAD_FIXED_CTRx
Reload value for IA32_FIXED_CTRx (R/W)
Thread
47:0
Value loaded into IA32_FIXED_CTRx when a PEBS record is
generated while PEBS_EN_FIXEDx = 1 and PEBS_OUTPUT =
01B in IA32_PEBS_ENABLE, and FIXED_CTRx is overflowed.
63:48
Reserved.
Register Address: 14C1H-14C8H, 5313 -5320
MSR_RELOAD_PMCx
Reload value for IA32_PMCx (R/W)
Thread
Vol. 4
2-463
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-55. MSRs Supported by the Intel® Core™ Ultra 7 Processor E-core (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
47:0
Value loaded into IA32_PMCx when a PEBS record is generated
while PEBS_EN_PMCx = 1 and PEBS_OUTPUT = 01B in
IA32_PEBS_ENABLE, and PMCx is overflowed.
63:48
Reserved.
Register Address: 1A8EH, 6798
MSR_STLB_FILL_TRANSLATION
STLB Fill Translation (W/O)
Core
STLB QoS MSR to fill translations into STLB.
3:0
CLOS
Class of service to use for the fill.
9:4
Reserved.
10
X
Set to 1 when LA is to an executable page.
11
RW
Set to 1 when LA is to a writeable page.
63:12
LA
Logical address to use for fill.
2.17.10 MSRs Introduced in the Intel® Xeon® 6 P-Core Processors
Table 2-56 lists additional MSRs for the Intel Xeon 6 P-core processors. Intel Xeon 6 P-core processors have a
CPUID Signature DisplayFamily_DisplayModel value of 06_ADH or 06_AEH.
For an MSR listed in Table 2-56 that also appears in the model-specific tables of prior generations, Table 2-56
supersedes prior generation tables.
Table 2-56. Additional MSRs Supported by the Intel® Xeon® 6 P-Core Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 33H, 51
MSR_MEMORY_CONTROL
MSR_MEMORY_CONTROL (R/W)
Core
Disables split locks, which are locked instructions that split a cache line.
26:0
Reserved.
27
UC_STORE_THROTTLE
If set to 1, when enabled, the processor allows one in-progress,
post-retirement UC stores at a time.
28
UC_LOCK_DISABLE
If set to 1, a UC load lock will trigger a fault. If clear to 0, UC load
locks proceed normally.
29
SPLIT_LOCK_DISABLE
If set to 1, a split lock will trigger an #AC fault. If clear to 0, split
locks proceed normally
63:30
Reserved.
Register Address: 34H, 52
MSR_SMI_COUNT
2-464 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Additional MSRs Supported by the Intel® Xeon® 6 P-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
SMI Counter (R/W)
Thread
31:0
SMI_COUNT
Running count of SMI events since the last reset.
63:32
Reserved.
Register Address: 39H, 57
MSR_SOCKET_ID
Socket ID (R/W)
Package
Reassigns the package-specific portions of the APIC ID. This MSR is used on scalable DP and high-end MP platforms to
resolve legacy-mode APIC ID conflicts.
10:0
PACKAGE_ID:
Holds package ID. This reflects the upper bits of the APIC ID.
63:11
Reserved.
Register Address: 7AH, 122
IA32_FEATURE_ACTIVATION
IA32_FEATURE_ACTIVATION (R/W)
Thread
Implements Feature Activation command. WRMSR to this address activates all 'activatable' features on this thread.
See Table 2-2.
Register Address: 7BH, 123
IA32_MCU_ENUMERATION
IA32_MCU_ENUMERATION (R/O)
Package
Enumeration of architectural features. See Table 2-2.
Register Address: 7CH, 124
IA32_MCU_STATUS
IA32_MCU_STATUS (R/O)
Package
Communicates results from the previous patch loads. See Table 2-2.
Register Address: 82H, 130
IA32_FZM_RANGE_INDEX
IA32_FZM_RANGE_INDEX (R/W)
Thread
Index and Domain handle for a valid FZM region. Programmed by SW and used by other FRM MSRs FZM Range Index
register to R/W Domain Index. See Table 2-2.
Register Address: 83H, 131
IA32_FZM_DOMAIN_CONFIG
IA32_FZM_DOMAIN_CONFIG (R/O)
Thread
Bit mask of valid regions within the domain identified by FZM_RANGE_INDEX. See Table 2-2.
Register Address: 84H, 132
IA32_FZM_RANGE_STARTADDR
IA32_FZM_RANGE_STARTADDR (R/O)
Thread
Start address of the FZM range pointed to by FZM_RANGE_INDEX. See Table 2-2.
Register Address: 85H, 133
IA32_FZM_RANGE_ENDADDR
IA32_FZM_RANGE_ENDADDR (R/O)
Thread
End address of the specified domain in FZM_RANGE_INDEX. See Table 2-2.
Register Address: 86H, 134
IA32_FZM_RANGE_WRITESTATUS
IA32_FZM_RANGE_WRITESTATUS (R/O)
Thread
Write status of the FZM range pointed to by FZM_RANGE_INDEX. See Table 2-2.
Register Address: 87H, 135
IA32_MKTME_KEYID_PARTITIONING
MKTME KEY ID Partitioning (R/O)
Package
Enumerates the number of activated KeyIDs for Intel TME-MK and Intel TDX. See Table 2-2.
Vol. 4
2-465
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Additional MSRs Supported by the Intel® Xeon® 6 P-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 90H, 144
IA32_SGXLEPUBKEYHASH4
IA32_SGXLEPUBKEYHASH4 (R/W)
Thread
See Table 2-2.
Register Address: 91H, 145
IA32_SGXLEPUBKEYHASH5
IA32_SGXLEPUBKEYHASH5 (R/W)
Thread
See Table 2-2.
Register Address: 98H, 152
MSR_SEAM_WBINVDP
SEAM WBINVDP (R/W)
Thread
Allows software to WBINVD sections of the LLC.
63:0
HANDLE
Caches sub-block to invalidate.
Register Address: 99H, 153
MSR_SEAM_WBNOINVDP
SEAM WBNOINVDP (R/W)
Thread
Allows software to WBNOINVD sections of the LLC.
63:0
HANDLE
Caches sub-block to invalidate.
Register Address: 9AH, 154
MSR_SEAM_INTR_PENDING
SEAM Interrupt Pending (R/O)
Thread
Report out some event pending bits.
0
INTR
Interrupt is pending.
1
NMI
NMI is pending.
2
SMI
SMI is pending.
4:3
OTHER_EVENTS
Other events pending.
63:5
Reserved.
Register Address: 9BH, 155
IA32_SMM_MONITOR_CTL
SMM Monitor Control (R/W)
Thread
The SMM Monitor Configuration involves SMM code specifying the MSEG location and enabling dual-monitor treatment
by writing to the corresponding MSR. See Table 2-2.
Register Address: CFH, 207
IA32_CORE_CAPABILITIES
IA32 Core Capabilities Register (R/W)
Core
If CPUID.07H.00H:EDX[30] = 1.
This MSR provides an architectural enumeration function for model-specific behavior.
0
STLB_QOS
When set to 1, processor supports STLB QoS.
1
Reserved.
2-466 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Additional MSRs Supported by the Intel® Xeon® 6 P-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
2
INTEGRITY_SUPPORTED
When set to 1, processor supports Functional Safety. Specific
FUSA capabilities are enumerated in MSR_FUSA_CAPABILITIES.
3
RSM_IN_CPL0_ONLY
Intel System Resources Defense: When set to 1, RSM will only be
allowed in CPL0 and will #GP for all non-CPL0 privilege levels.
4
UC_LOCK_DISABLE
When set to 1, processor supports UC load lock disable.
5
SPLIT_LOCK_DISABLE
When set to 1, processor supports #AC on split locks.
6
SNP_FILTER_QOS
When set to 1, processor supports Snoop Filter Quality of Service
MSRs.
7
UC_STORE_THROTTLING
When set to 1, processor supports UC store throttling through
MSR_MEMORY_CTRL[UC_STORE_THROTTLE].
63:8
Reserved.
Register Address: E7H, 231
IA32_MPERF
Maximum Performance Frequency Clock Count (R/W)
Thread
See Table 2-2.
Register Address: E8H, 232
IA32_APERF
Actual Performance Frequency Clock Count (R/W)
Thread
See Table 2-2.
Register Address: FEH, 254
IA32_MTRRCAP
Memory Type Range Register (R/O)
Core
See Table 2-2.
Register Address: 105H, 261
MSR_ARRAY_BIST
MSR_ARRAY_BIST (R/W)
Core
Triggered by writing and reading an MSR that can be written by Ring 0 software.
Vol. 4
2-467
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Additional MSRs Supported by the Intel® Xeon® 6 P-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
31:0
ARRAY_LIST:
Bit map which indicates which arrays to run MarchC- BIST
• Bit[0] MLC Data
• Bit[1] MLC Tag
• Bit[2] C6SRAM Data (NOP for WRMSR - used for reporting
error only)
• Bit[3] PMA BIST (NOP for WRMSR - used for reporting error
only)
• Bit[4] STLB Data
• Bit[5] IFU Data
• Bit[6] STLB Tag
• Bit[7] DCU Data
• Bit[8] DSB Data
• Bit[9] TMUL Data
• Bit[10] UROM pointer0
• Bit[11] UROM pointer1-3
• Bit[12] UROM pointer4-7
• Bit[13] UROM unique0
• Bit[14] UROM unique1/2
The WRMSR will run PBIST on all the arrays indicated in the
bitmap, starting from the LSB.
NOTE2: C6SRAM[Bit 2] and PMA[Bit 3] are only for reporting and
do not execute BIST (done by EDX[15:0]uCode during Fusa-
Reset).
46:32
Reserved.
62:47
Reserved.
63
SIGNAL_MCE:
Signal MCERR upon BIST failure.
Register Address: 105H, 261
MSR_ARRAY_BIST_STATUS
MSR_ARRAY_BIST_STATUS (R/O)
Core
31:0
ARRAY_COMPLETION _MASK
Bitmap indicating which arrays from the
ARRAY_BIST.ARRAY_LIST was not processed.
1 means not tested and 0 means tested.
62:32
Reserved. Returns all 0s.
63
PASS_FAIL:
0 means Pass on all arrays in the
WRMSR(ARRAY_BIST.ARRAY_LIST)
1 means Fail on the LSB array in the
RDMSR(ARRAY_BIST_STATUS.ARRAY_COMPLETION_MASK).
Register Address: 122H, 290
IA32_TSX_CTRL
IA32_TSX_CTRL (R/W)
Thread
See Table 2-2.
Register Address: 140H, 320
MSR_FEATURE_ENABLES
Miscellaneous enables for thread-specific features. (R/W)
Thread
0
2-468 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Additional MSRs Supported by the Intel® Xeon® 6 P-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
63:1
Reserved.
Register Address: 1E0H, 480
IA32_LER_INFO
IA32_LER_INFO (R/W)
Thread
Last Event Record Destination IP Register. See Table 2-2.
Register Address: 1F9H, 505
IA32_CPU_DCA_CAP
IA32_CPU_DCA_CAP (R/O)
Thread
See Table 2-2.
Register Address: 2A1H, 673
MSR_PRMRR_BASE_1
MSR_PRMRR_BASE_1 (R/W)
Core
Processor Reserved Memory Range Register - Physical Base Control Register.
2:0
MEMTYPE
Memory Type for PRMRR accesses.
3
CONFIGURED
PRMRR base configured.
19:4
Reserved.
51:20
BASE
PRMRR Base address.
63:52
Reserved.
Register Address: 2A2H, 674
MSR_PRMRR_BASE_2
MSR_PRMRR_BASE_2 (R/W)
Core
Processor Reserved Memory Range Register - Physical Base Control Register.
See MSR_PRMRR_BASE_1 (2A1H) for reference; similar format.
Register Address: 2A3H, 675
MSR_PRMRR_BASE_3
MSR_PRMRR_BASE_3 (R/W)
Core
Processor Reserved Memory Range Register - Physical Base Control Register.
See MSR_PRMRR_BASE_1 (2A1H) for reference; similar format.
Register Address: 2A4H, 676
MSR_PRMRR_BASE_4
MSR_PRMRR_BASE_4 (R/W)
Core
Processor Reserved Memory Range Register - Physical Base Control Register.
See MSR_PRMRR_BASE_1 (2A1H) for reference; similar format.
Register Address: 2A5H, 677
MSR_PRMRR_BASE_5
MSR_PRMRR_BASE_5 (R/W)
Core
Processor Reserved Memory Range Register - Physical Base Control Register.
See MSR_PRMRR_BASE_1 (2A1H) for reference; similar format.
Register Address: 2A6H, 678
MSR_PRMRR_BASE_6
MSR_PRMRR_BASE_6 (R/W)
Core
Processor Reserved Memory Range Register - Physical Base Control Register.
See MSR_PRMRR_BASE_1 (2A1H) for reference; similar format.
Register Address: 2A7H, 679
MSR_PRMRR_BASE_7
Vol. 4
2-469
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Additional MSRs Supported by the Intel® Xeon® 6 P-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
MSR_PRMRR_BASE_7 (R/W)
Core
Processor Reserved Memory Range Register - Physical Base Control Register.
See MSR_PRMRR_BASE_1 (2A1H) for reference; similar format.
Register Address: 2B8H, 696
MSR_COPY_SBFT_HASHES
MSR_COPY_SBFT_HASHES (W/O)
Module
63:0
SBFT_PROGRAM_SOURCE_ADDR
EDX:EAX contains the linear address base of the SBFT Binary
loaded into memory.
Register Address: 2B9H, 697
MSR_SBFT_HASHES_STATUS
MSR_COPY_SBFT_HASHES (R/O)
Core
15:0
CHUNK_SIZE
EAX[15:0] - Chunk size of the test in KB.
31:16
TOTAL_NUM_CHUNKS
EAX[31:16] - Total number of chunks.
39:32
ERROR_CODE - EDX[7:0]
The error code refers to the LP that runs WRMSR(2B8H).
• 0x0: Reserved.
• 0x1: Attempt to copy SBFT-hashes when copy already in
progress.
• 0x2: Secure Memory not set up correctly.
• 0x3: Scan-Image Header Image_info.ProgramID does not match
MSR_INTEGRITY_CAPABILITIES[31:24], or scan-image header
Processor-Signature doesn't match F/M/S, or scan-image
header Processor-Flags doesn't match PlatformID.
• 0x4: Reserved.
• 0x5: Integrity check failed.
• 0x6: WRMSR(0x2B8) (ACTIVATE_SBAF) Reinstall of SBFT test
image attempted when current SBFT test image is in use by
other LPs.
• 0x7: Aborted due to #PF (Page Fault).
• 0x8: Unable to generate a Random Value.
48:40
NUM_CHUNKS_IN_STRIDE
EDX[16:8] - Number of Chunks in stride. This is the number of
chunks that are installed. 0 in this field means that the CPU does
not support strides, otherwise, stride value must be >= 1.
50:49
Reserved.
EDX[18:17] - Set to all zeros.
62:51
MAX_CORE_LIMIT
EDX[30:19] - Maximum Number of Cores that can run
SBFTAFSBAF simultaneously -1.
0 means 1 core at a time.
63
Valid.
EDX[31] - Valid bit is set when COPY_SBFT_HASHES completed
successfully.
Register Address: 2BAH, 698
MSR_AUTHENTICATE_AND_COPY_SBFT_CHUNK
2-470 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Additional MSRs Supported by the Intel® Xeon® 6 P-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
MSR_AUTHENTICATE_AND_COPY_SBFT_CHUNK (W/O)
Core
63:0
BASE_CHUNK_TABLE_ADDR
EDX:EAX[63:0] - Linear Address pointing to the CHUNK TABLE
(TABLE_BASE).
Register Address: 2BBH, 699
MSR_SBFT_CHUNKS_AUTHENTICATION_STATUS
MSR_SBFT_CHUNKS_AUTHENTICATION_STATUS (R/O)
Core
15:0
NUM_VALID_CHUNKS
EAX[15:0] - Total number of Valid (authenticated) chunks.
31:16
NUM_CHUNKS_IN_STRIDE
EAX[31:16] - Number of Chunks in Stride.
39:32
ERROR_CODE
EDX[7:0]
• 0x0 - No error reported.
• 0x1 - Attempt to authenticate a CHUNK already marked as
authentic or is currently being installed by another core.
• 0x2 - CHUNK authentication error. HASH of chunk did not
match expected value.
• 0x3 - Aborted due to #PF.
• 0x4 - Chunk Outside the current Stride.
• 0x5 - Interrupted.
47:40
Reserved.
EDX[15:8] - Set to all zeros.
63:48
CURRENT_MAX_BUNDLE_INDX
EDX[31:16] - Maximum Bundle Index in current stride.
Register Address: 2BCH, 700
MSR_ACTIVATE_SBFT
MSR_ACTIVATE_SBFT (W/O)
Core
13:0
SBFT_BUNDLE_INDEX
EAX[13:0] - Indicates SBFT Bundle Index to start from.
15:14
SBFT_PRGM_INDEX
EAX[15:14] - Indicates what SBFT Program index to run.
31:16
Reserved. Set to all zeros.
62:32
THREAD_WAIT_DELAY
EDX[30:0] - TSC-based delay to allow threads to rendezvous.
63
Reserved.
EDX[31] - Must be set to 0. #GP fault otherwise.
Register Address: 2BDH, 701
MSR_SBFT_STATUS
MSR_SBFT_STATUS (R/O)
Core
13:0
SBFT_BUNDLE_INDEX
EAX[13:0] - SBFT Bundle that was executed.
Vol. 4
2-471
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Additional MSRs Supported by the Intel® Xeon® 6 P-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
15:14
SBFT_PGM_INDEX
EAX[15:14] - Indicates what SBFT Program index that was last
ran. Maps to same field in WRMSR(ACTIVATE_SBFT).
On a test pass this field will be 2'b00.
31:16
Reserved.
EAX[31:16] - Return all zeros.
39:32
ERROR_CODE
EDX[7:0]
• 0x0 - No Error.
• 0x1 - SBFT operation did not start. Other thread could not join.
• 0x2 - SBFT operation did not start. Interrupt occurred prior to
SBFT coordination.
• 0x3 - Reserved.
• 0x4 - SBFT operation did not start. Non-valid SBFT BUNDLES in
the SBFT_BUNDLE_INDEX.
• 0x5 - SBFT operation did not start. Mismatch in arguments
between threads T0/T1.
• 0x6 - SBFT operation did not start. Core is not capable of
performing SBFT currently.
• 0x7 - Reserved.
• 0x8 - SBFT operation did not start. Exceeded number of Logical
Processors (LP) allowed to run SBFT-At-Field concurrently.
• 0x9 - SBFT operation did not start. Interrupt occurred or timer
about to expire.
• 0xA - SBFT operation did not start. SBFT_PGM_INDEX is not
valid.
• 0xB - SBFT operation aborted due to corrupted chunk.
• 0xC - SBFT operation did not start. TAP Data error.
• 0xD - SBFT operation did not start. SBFT program is not valid.
All other error codes are reserved.
60:40
Reserved.
EDX[28:8] - Return all zeros.
61
TEST_FAIL
EDX[29:29] - Architectural Signature failed. Last thread executed
HLT and completed SBFT and EBX != 0xACED.
63:62
SBFT_STATUS
EDX[31:30] - SBFT status (result of running SBAF).
•
00 - PASS.
•
10 - INTERRUPTED.
•
01 - FAILED SIGNATURE CHECK.
•
11 - FAILED.
Register Address: 2BEH, 702
MSR_SBFT_MODULE_ID
MSR_SBFT_MODULE_ID (R/O)
Module
31:0
SBFT-AT-FIELD_REVID
EAX[31:0] - Maps to Revision field in external header (offset 4).
40:32
CURRENT_STRIDE_INDEX
EDX[8:0] - Stride Index.
2-472 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Additional MSRs Supported by the Intel® Xeon® 6 P-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
63:41
Reserved.
EDX[31:9] - Return all zeros.
Register Address: 2BFH, 703
MSR_SBFTAF_LAST_WP
MSR_SBFTAF_LAST_WP (R/O)
Module
31:0
LAST_WP
EAX[31:0] - Provides information about the core when the last
WRMSR(ACTIVATE_SBFT) was executed. Available only if
enumerated in INTEGRITY_CAPABILITIES[10:9].
39:32
Reserved.
63:40
Reserved.
EDX[31:8] - Return all zeros.
Register Address: 2C2H, 706
MSR_COPY_SCAN_HASHES
MSR_COPY_SCAN_HASHES (W/O)
Module
63:0
SCAN_HASH-ADDR
EDX:EAX contains the linear address of the SCAN Test HASH
Binary loaded into memory
Register Address: 2C3H, 707
MSR_SCAN_HASHES_STATUS
MSR_SCAN_HASHES_STATUS (R/O)
Core
15:0
CHUNK_SIZE
EAX[15:0] - Chunk size of the test in KB.
31:16
TOTAL_NUM_CHUNKS
EAX[31:16] - Total number of chunks.
39:32
ERROR_CODE
EDX[7:0] - The error code refers to the LP that runs
WRMSR(2C2H).
• 0x0 - Reserved.
• 0x1 - Attempt to copy scan-hashes when copy already in
progress.
• 0x2 - Secure Memory not set up correctly.
• 0x3 - Scan-Image Header Image_info.ProgramID does not
match MSR_INTEGRITY_CAPABILITIES[31:24], or scan-image
header Processor-Signature doesn't match F/M/S, or scan-
image header Processor-Flags doesn't match PlatformID.
• 0x4 - Reserved.
• 0x5 - Integrity check failed.
• 0x6 - WRMSR(0x2C6) Re-install of scan test image attempted
when current scan test image is in use by other LPs.
• 0x7 - Aborted due to #PF (Page Fault).
• 0x8 - Unable to generate a Random Value.
48:40
NUM_CHUNKS_IN_STRIDE
EDX[16:8] - Number of Chunks in stride. This is the number of
chunks that are installed. 0 in this field means that the CPU does
not support strides, otherwise, the stride value must be >= 1.
50:49
Reserved.
EDX[18:17] - Set to all zeros.
Vol. 4
2-473
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Additional MSRs Supported by the Intel® Xeon® 6 P-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
62:51
NAME
EDX[30:19] - Maximum Number of cores that can run Intel® In-
field Scan simultaneously minus 1.
0 means 1 core at a time.
63
VALID
EDX[31] - Valid bit is set when COPY_SCAN_HASHES completed.
Register Address: 2C4H, 708
MSR_AUTHENTICATE_AND_COPY_CHUNK
MSR_AUTHENTICATE_AND_COPY_CHUNK (R/O)
Core
63:0
BASE_CHUNK_TABLE_ADDR
EDX:EAX[63:0] - Linear Address pointing to the CHUNK TABLE
(TABLE_BASE).
Register Address: 2C5H, 709
MSR_CHUNKS_AUTHENTICATION_STATUS
MSR_CHUNKS_AUTHENTICATION_STATUS (R/O)
Core
15:0
VALID_CHUNKS
EAX[15:0] - Total number of Valid (authenticated) chunks.
31:16
NUM_CHUNKS_IN_STRIDE
EAX[31:16] - Number of Chunks in Stride.
39:32
ERROR_CODE
EDX[7:0]
• 0x0 - No-error reported.
• 0x1 - Attempt to authenticate a CHUNK which is already.
marked as authentic or is currently being installed by another
core.
• 0x2 - CHUNK authentication error. HASH of chunk did not
match expected value.
• 0x3 - Aborted due to #PF (Page Fault).
• 0x4 - Chunk Outside the current Stride.
63:40
Reserved.
EDX[31:8] - Set to all zeros.
Register Address: 2C6H, 710
MSR_ACTIVATE_SCAN
MSR_ACTIVATE_SCAN (W/O)
Core
15:0
CHUNK_START_INDEX
EAX[15:0] - Indicates Chunk Index from which to start.
31:16
CHUNK_STOP_INDEX
EAX[31:16] - Indicates what chunk index to stop at (inclusive).
62:32
THREAD_WAIT_DELAY
EDX[30:0] - TSC based delay to allow threads to rendezvous.
63
SIGNAL_MCE
EDX[31]
• If 1: On scan-error log MC in MC4_STATUS and signal MCE if
machine check signaling enabled in MC4_CTL[0].
• If 0: Don't no-logging/no-signaling.
Register Address: 2C7H, 711
MSR_SCAN_STATUS
2-474 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Additional MSRs Supported by the Intel® Xeon® 6 P-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
MSR_SCAN_STATUS (R/O)
Core
15:0
CHUNK_NUM
EAX[15:0] - SCAN Chunk that was reached.
31:16
CHUNK_STOP_INDEX
EAX[31:16]
• Indicates what chunk index to stop at (inclusive).
• Maps to same field in WRMSR(ACTIVATE_SCAN).
39:32
ERROR_CODE
EDX[7:0]
• 0x0 - No Error.
• 0x1 - SCAN operation did not start. Other thread could not join.
• 0x2 - SCAN operation did not start. Interrupt occurred prior to
SCAN coordination.
• 0x3 - SCAN operation did not start. Power Management
conditions are inadequate to run SAF.
• 0x4 - SCAN operation did not start. Non valid chunks in the
range CHUNK_STOP_INDEX : CHUNK_START_INDEX.
• 0x5 - SCAN operation did not start. Mismatch in arguments
between threads T0/T1.
• 0x6 - SCAN operation did not start. Core not capable of
performing SCAN currently.
• 0x7 - Debug Mode. Scan-At-Field results not to be trusted.
• 0x8 - SCAN operation did not start. Exceeded number of
Logical Processors (LP) allowed to run Scan-At-Field
concurrently. MAX_CORE_LIMIT exceeded.
• 0x9 - Interrupt occurred. Scan operation aborted prematurely,
not all chunks requested have been executed.
• 0xB - Scan operation aborted due to corrupted chunk.
• 0xC - Scan operation did not start.
All other error codes are reserved.
61:40
Reserved.
EDX[29:8] - Return all zeros.
62
SCAN_CONTROL_ERROR
EDX[30]
• SCAN error in the Scan-At-Field controller.
• Non ECC error.
63
SCAN_SIGNATURE_ERROR
EDX[31]
• SCAN SIGNATURE error in the SCAN pattern fetched from main
memory.
• Non ECC error.
Register Address: 2C8H, 712
MSR_SCAN_MODULE_ID
MSR_SCAN_MODULE_ID (R/O)
Module
31:0
SCAN-AT-FIELD_REVID
EAX[31:0] - Maps to Revision field in external header (offset 4).
40:32
CURRENT_STRIDE_INDEX
EDX[8:0] - Stride Index.
Vol. 4
2-475
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Additional MSRs Supported by the Intel® Xeon® 6 P-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
63:41
Reserved.
EDX[31:9] - Return all zeros.
Register Address: 2C9H, 713
MSR_LAST_SAF_WP
MSR_LAST_SAF_WP (R/O)
Module
31:0
LAST_WP
EAX[31:0]
• Provides information about the core when the last
WRMSR(ACTIVATE_SCAN) was executed.
• Available only if enumerated in
INTEGRITY_CAPABILITIES[10:9].
39:32
Reserved.
EDX[7:0]
63:40
Reserved.
EDX[31:8] - Return all zeros.
Register Address: 2D9H, 729
MSR_INTEGRITY_CAPABILITIES
MSR_INTEGRITY_CAPABILITIES (R/O)
Thread
Enumerates features supported in Functional Safety.
0
STARTUP_SCAN_BIST
When set to 1, processor supports Startup SCAN BIST.
1
STARTUP_MEM_BIST
When set to 1, processor supports Startup MEM BIST.
2
PERIODIC_MEM_BIST
When set to 1, processor supports Periodic MEM BIST.
3
LOCKSTEP
When set to 1, processor supports Lock Step Mode.
4
PERIODIC_SCAN_BIST
When set to 1, processor supports Periodic SCAN BIST.
5
PLL_LOSS_DETECT
When set to 1, processor supports PLL LOSS detection.
6
PWR_LOSS_DETECT
When set to 1, processor supports Power Loss detection.
7
PERRINJ
When set to 1, processor supports FUSA PERRINJ.
8
SBFT_AT_FIELD
When set to 1, processor supports SBFT-At-Field.
10:9
SAF_GEN_REV
00 = REV1; 01 = REV2; 10 = REV3; 11 = REV4.
14:11
Reserved.
15
PRESERVE_MEMORY_NEEDED
When set to 1, processor supports FUSARR_BASE/MASK MSRs.
2-476 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Additional MSRs Supported by the Intel® Xeon® 6 P-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
20:16
TID_BIT_SHIFT
Number of bits to shift right on x2APICID to get a unique topology
ID of all logical processors that share a scan test engine.
21
ALL_LP_JOIN_NEEDED
All logical processors that share scan test engine need to be
tested together and must join using MSR_ACTIVATE_SCAN.
23:22
Reserved.
31:24
PATTERN_ID
Processor scan pattern ID. ID of the startup and periodic scan
programs supported for this part.
63:32
Reserved.
Register Address: 30CH, 780
IA32_FIXED_CTR3
Fixed-Function Performance Counter 3 (R/W)
Thread
See Table 2-2.
Register Address: 4D0H, 1232
IA32_MCG_EXT_CTL
IA32_MCG_EXT_CTL (R/W)
Thread
See Table 2-2.
Register Address: 4F0H, 1264
MSR_SAF_CTRL
MSR_SAF_CTRL (W/O)
Core
0
INVALIDATE_CURRENT_STRIDE
EAX[0]
• Write of 1 invalidates the currently installed stride.
• Clears only the VALID_CHUNKS field on a
RDMSR(CHUNKS_AUTHENTICATION_STATUS).
63:1
Reserved.
Register Address: 4F8H, 1272
MSR_SBFT_CTRL
MSR_SBFT_CTRL (W/O)
Module
0
INVALIDATE_CURRENT_STRIDE
EAX[0] - Write of 1 invalidates the currently installed stride.
63:1
Reserved.
EDX[31:0],EAX[31:1]
Register Address: 540H, 1344
MSR_THREAD_UARCH_CTL
Thread Microarchitectural Control (R/W)
Thread
0
WB_MEM_STRM_LD_DISABLE
Disable streaming behavior for MOVNTDQA loads to WB memory
type. If set, these accesses will be treated like regular cacheable
loads (Data will be cached).
63:1
Reserved.
Register Address: 541H, 1345
MSR_CORE_UARCH_CTL
Core Microarchitecture Control MSR (R/W)
Core
Vol. 4
2-477
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Additional MSRs Supported by the Intel® Xeon® 6 P-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
0
SCRUB_DIS
L1 scrubbing disable.
63:1
Reserved.
Register Address: 664H, 1636
MSR_MC6_RESIDENCY
MSR_MC6_RESIDENCY (R/O)
Module
Time spent in the Module C6-State. Provided in units compatible to P1 clock frequency (Guaranteed / Maximum Core
Non-Turbo Frequency).
63:0
RESIDENCY
Time that this module is in module-specific C6 states since last
reset.
Register Address: 6E1H, 1761
IA32_PKRS
IA32_PKRS (R/W)
Thread
Specifies the PK permissions associated with each protection domain for supervisor pages. See Table 2-2.
Register Address: 7A3H, 1955
IA32_MCU_EXT_SERVICE
MCU Extended Service MSR (R/O)
Module
If IA32_ARCH_CAPABILITIES[22] = 1. See Table 2-2.
Register Address: 7A4H, 1956
IA32_MCU_ROLLBACK_MIN_ID
Minimal MCU Revision ID for Rollback (R/O)
Module
See Table 2-2.
Register Address: 7B0H, 1968
IA32_ROLLBACK_SIGN_ID_0
Rollback ID 0 (R/O)
Module
See Table 2-2.
Register Address: 7B1H, 1969
IA32_ROLLBACK_SIGN_ID_1
Rollback ID 1 (R/O)
Module
See Table 2-2.
Register Address: 7B2H, 1970
IA32_ROLLBACK_SIGN_ID_2
Rollback ID 2 (R/O)
Module
See Table 2-2.
Register Address: 7B3H, 1971
IA32_ROLLBACK_SIGN_ID_3
Rollback ID 3 (R/O)
Module
See Table 2-2.
Register Address: 7B4H, 1972
IA32_ROLLBACK_SIGN_ID_4
Rollback ID 4 (R/O)
Module
See Table 2-2.
Register Address: 7B5H, 1973
IA32_ROLLBACK_SIGN_ID_5
Rollback ID 5 (R/O)
Module
See Table 2-2.
Register Address: 7B6H, 1974
IA32_ROLLBACK_SIGN_ID_6
Rollback ID 6 (R/O)
Module
See Table 2-2.
2-478 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Additional MSRs Supported by the Intel® Xeon® 6 P-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 7B7H, 1975
IA32_ROLLBACK_SIGN_ID_7
Rollback ID 7 (R/O)
Module
See Table 2-2.
Register Address: 7B8H, 1976
IA32_ROLLBACK_SIGN_ID_8
Rollback ID 8 (R/O)
Module
See Table 2-2.
Register Address: 7B9H, 1977
IA32_ROLLBACK_SIGN_ID_9
Rollback ID 9 (R/O)
Module
See Table 2-2.
Register Address: 7BAH, 1978
IA32_ROLLBACK_SIGN_ID_10
Rollback ID 10 (R/O)
Module
See Table 2-2.
Register Address: 7BBH, 1979
IA32_ROLLBACK_SIGN_ID_11
Rollback ID 11 (R/O)
Module
See Table 2-2.
Register Address: 7BCH, 1980
IA32_ROLLBACK_SIGN_ID_12
Rollback ID 12 (R/O)
Module
See Table 2-2.
Register Address: 7BDH, 1981
IA32_ROLLBACK_SIGN_ID_13
Rollback ID 13 (R/O)
Module
See Table 2-2.
Register Address: 7BEH, 1982
IA32_ROLLBACK_SIGN_ID_14
Rollback ID 14 (R/O)
Module
See Table 2-2.
Register Address: 7BFH, 1983
IA32_ROLLBACK_SIGN_ID_15
Rollback ID 15 (R/O)
Module
See Table 2-2.
Register Address: 981H, 2433
IA32_TME_CAPABILITY
IA32_TME_CAPABILITY (R/O)
Package
See Table 2-2.
Register Address: 982H, 2434
IA32_TME_ACTIVATE
IA32_TME_ACTIVATE (R/W)
Package
See Table 2-2.
Register Address: 983H, 2435
IA32_TME_EXCLUDE_MASK
Intel TME Exclude Mask (R/W)
Package
See Table 2-2.
Register Address: 984H, 2436
IA32_TME_EXCLUDE_BASE
Intel TME Exclude Base (R/W)
Package
See Table 2-2.
Vol. 4
2-479
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Additional MSRs Supported by the Intel® Xeon® 6 P-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 985H, 2437
IA32_UINTR_RR
User Interrupt Request Register (R/W)
Thread
See Table 2-2.
Register Address: 986H, 2438
IA32_UINTR_HANDLER
User Interrupt Handler Address (R/W)
Thread
See Table 2-2.
Register Address: 987H, 2439
IA32_UINTR_STACKADJUST
User Interrupt Stack Adjustment (R/W)
Thread
See Table 2-2.
Register Address: 988H, 2440
IA32_UINTR_NV
User-Interrupt Size and Notification Vector (R/W)
Thread
See Table 2-2.
Register Address: 989H, 2441
IA32_UINTR_PD
User Interrupt PID Address (R/W)
Thread
See Table 2-2.
Register Address: 98AH, 2442
IA32_UINTR_TT
User-Interrupt Target Table (R/W)
Thread
See Table 2-2.
Register Address: 990H, 2448
IA32_COPY_STATUS
IA32_COPY_STATUS (R/O)
Thread
See Table 2-2.
Register Address: 991H, 2449
IA32_IWKEYBACKUP_STATUS
IA32_IWKEYBACKUP_STATUS (R/O)
Package
See Table 2-2.
Register Address: 9FBH, 2555
IA32_TME_CLEAR_SAVED_KEY
IA32_TME_CLEAR_SAVED_KEY (R/W)
Package
See Table 2-2.
Register Address: 9FFH, 2559
MSR_CORE_MKTME_ACTIVATE
MSR to read TME_ACTIVATE[MK_TME_KEYID_BITS] (R/O)
Core
31:0
Reserved.
35:32
READ_MK_TME_KEYID_BITS
This value will be returned on a RDMSR, but must be zero on a
WRMSR.
39:36
TDX_RESERVED_KEYID_BITS (read only)
The number of key identifier bits allocated to TDX usage.
This is a read-only field. #GP on a non-zero write.
63:40
Reserved.
Register Address: C84H, 3204
MSR_MBA_CFG
Memory Bandwidth Allocation (MBA) Configuration (R/W)
Package
2-480 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Additional MSRs Supported by the Intel® Xeon® 6 P-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
1:0
Reserved.
2
RAMBAE
Resource Aware MBA Enable.
63:3
Reserved.
Register Address: CA0H, 3232
MSR_RMID_SNC_CONFIG
RMID_SNC_CONFIG (R/W)
Package
0
RMID_LOCALIZED_DISTRIBUTION_MODE_ENABLE
If set, Localized RMID distribution mode is enabled. If Clear, RMID
Sharing mode is enabled.
63:1
Reserved.
Register Address: D50H, 3408
IA32_L2_QOS_EXT_BW_THRTL_0
Memory Bandwidth Enforcement for COS0 (R/W)
Package
See Table 2-2.
Register Address: D51H, 3409
IA32_L2_QOS_EXT_BW_THRTL_1
Memory Bandwidth Enforcement for COS1 (R/W)
Package
See Table 2-2.
Register Address: D52H, 3410
IA32_L2_QOS_EXT_BW_THRTL_2
Memory Bandwidth Enforcement for COS2 (R/W)
Package
See Table 2-2.
Register Address: D53H, 3411
IA32_L2_QOS_EXT_BW_THRTL_3
Memory Bandwidth Enforcement for COS3 (R/W)
Package
See Table 2-2.
Register Address: D54H, 3412
IA32_L2_QOS_EXT_BW_THRTL_4
Memory Bandwidth Enforcement for COS4 (R/W)
Package
See Table 2-2.
Register Address: D55H, 3413
IA32_L2_QOS_EXT_BW_THRTL_5
Memory Bandwidth Enforcement for COS5 (R/W)
Package
See Table 2-2.
Register Address: D56H, 3414
IA32_L2_QOS_EXT_BW_THRTL_6
Memory Bandwidth Enforcement for COS6 (R/W)
Package
See Table 2-2.
Register Address: D57H, 3415
IA32_L2_QOS_EXT_BW_THRTL_7
Memory Bandwidth Enforcement for COS7 (R/W)
Package
See Table 2-2.
Register Address: D58H, 3416
IA32_L2_QOS_EXT_BW_THRTL_8
Memory Bandwidth Enforcement for COS8 (R/W)
Package
See Table 2-2.
Register Address: D59H, 3417
IA32_L2_QOS_EXT_BW_THRTL_9
Vol. 4
2-481
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Additional MSRs Supported by the Intel® Xeon® 6 P-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Memory Bandwidth Enforcement for COS9 (R/W)
Package
See Table 2-2.
Register Address: D5AH, 3418
IA32_L2_QOS_EXT_BW_THRTL_10
Memory Bandwidth Enforcement for COS10 (R/W)
Package
See Table 2-2.
Register Address: D5BH, 3419
IA32_L2_QOS_EXT_BW_THRTL_11
Memory Bandwidth Enforcement for COS11 (R/W)
Package
See Table 2-2.
Register Address: D5CH, 3420
IA32_L2_QOS_EXT_BW_THRTL_12
Memory Bandwidth Enforcement for COS12 (R/W)
Package
See Table 2-2.
Register Address: D5DH, 3421
IA32_L2_QOS_EXT_BW_THRTL_13
Memory Bandwidth Enforcement for COS13 (R/W)
Package
See Table 2-2.
Register Address: D5EH, 3422
IA32_L2_QOS_EXT_BW_THRTL_14
Memory Bandwidth Enforcement for COS14 (R/W)
Package
See Table 2-2.
Register Address: D91H, 3473
IA32_COPY_LOCAL_TO_PLATFORM
See Table 2-2.
Thread
Register Address: D92H, 3474
IA32_COPY_PLATFORM_TO_LOCAL
See Table 2-2.
Thread
Register Address: D93H, 3475
IA32_PASID
See Table 2-2.
Thread
Register Address: 1400H, 5120
IA32_SEAMRR_BASE
SEAM Memory Range Register for TDx - Base Address (R/W)
Core
See Table 2-2.
Register Address: 1401H, 5121
IA32_SEAMRR_MASK
SEAM Memory Range Register for TDX (R/W)
Core
See Table 2-2.
Register Address: 1A8FH, 6799
MSR_STLB_QOS_INFO
STLB_QOS_INFO (R/O)
Core
STLB QoS MASK configuration.
5:0
NCLOS
Number of CLOS supported for STLB resource using minus-1
notation.
15:6
Reserved.
19:16
4K_2M_CBM
Length of capacity bitmask for 4K and 2M pages using minus-1
notation.
2-482 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Additional MSRs Supported by the Intel® Xeon® 6 P-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
28:20
Reserved.
29
STLB_FILL_TRANSLATION_MSR_SUPPORTED
MSR interface to fill STLB translations supported.
30
4K_2M_ALIAS
Indicates that 4K/2M pages alias into the same structure.
63:31
Reserved.
Register Address: 1B01H, 6913
IA32_UARCH_MISC_CTL
IA32_UARCH_MISC_CTL (R/W)
Thread
See Table 2-2.
2.17.11 MSRs Introduced in the Intel® Xeon® 6 E-Core Processors
Table 2-57 lists additional MSRs for the Intel Xeon 6 E-core processors. Intel Xeon 6 E-core processors have a
CPUID Signature DisplayFamily_DisplayModel value of 06_AFH.
For an MSR listed in Table 2-57 that also appears in the model-specific tables of prior generations, Table 2-57
supersedes prior generation tables.
Table 2-57. Additional MSRs Supported by the Intel® Xeon® 6 E-Core Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 2FH, 47
IA32_BARRIER
BARRIER (R/O)
Core
The IA32_BARRIER MSR ensures ordered execution by acting like LFENCE, controlling the sequencing of subsequent
MSR reads after prior MSR reads and instructions.
See Table 2-2.
Register Address: 33H, 51
MSR_MEMORY_CONTROL
Memory Control (R/W)
Core
Disables split locks, which are locked instructions that split a cache line.
26:0
Reserved.
27
UC_STORE_THROTTLE
If set to 1, when enabled, the processor allows one in-progress,
post-retirement UC stores at a time.
28
UC_LOCK_DISABLE
If set to 1, a UC load lock will trigger a fault. If clear to 0, UC load
locks proceed normally.
29
SPLIT_LOCK_DISABLE
If set to 1, a split lock will trigger an #AC fault. If clear to 0, split
locks proceed normally.
63:30
Reserved.
Register Address: 34H, 52
MSR_SMI_COUNT
SMI Counter (R/W)
Thread
Vol. 4
2-483
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-57. Additional MSRs Supported by the Intel® Xeon® 6 E-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
31:0
SMI_COUNT
Running count of SMI events since the last reset.
63:32
Reserved.
Register Address: 39H, 57
MSR_SOCKET_ID
Socket ID (R/W)
Package
Reassigns the package-specific portions of the APIC ID. This MSR is used on scalable DP and high-end MP platforms to
resolve legacy-mode APIC ID conflicts.
10:0
PACKAGE_ID
Holds package ID. This reflects the upper bits of the APIC ID.
63:11
Reserved.
Register Address: 7BH, 123
IA32_MCU_ENUMERATION
Enumeration of Architectural Features (R/O)
Package
See Table 2-2.
Register Address: 7CH, 124
IA32_MCU_STATUS
MCU Status (R/O)
Package
Communicates results from the previous patch loads. See Table 2-2.
Register Address: 87H, 135
IA32_MKTME_KEYID_PARTITIONING
MKTME KEY ID Partitioning (R/O)
Package
Enumerates the number of activated KeyIDs for Intel TME-MK and Intel TDX. See Table 2-2.
Register Address: 98H, 152
MSR_SEAM_WBINVDP
SEAM WBINVDP (R/W)
Thread
Allows software to WBINVD sections of the LLC.
63:0
HANDLE
Caches sub-block to invalidate.
Register Address: 99H, 153
MSR_SEAM_WBNOINVDP
SEAM WBNOINVDP (R/W)
Thread
Allows software to WBNOINVD sections of the LLC.
63:0
HANDLE
Caches sub-block to invalidate.
Register Address: 9AH, 154
MSR_SEAM_INTR_PENDING
SEAM Interrupt Pending (R/O)
Thread
Report out some event pending bits.
0
INTR
Interrupt is pending.
1
NMI
NMI is pending.
2
SMI
SMI is pending.
4:3
OTHER_EVENTS
Other events pending.
2-484 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-57. Additional MSRs Supported by the Intel® Xeon® 6 E-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
63:5
Reserved.
Register Address: 9BH, 155
IA32_SMM_MONITOR_CTL
SMM Monitor Control (R/W)
Thread
The SMM Monitor Configuration involves SMM code specifying the MSEG location and enabling dual-monitor treatment
by writing to the corresponding MSR. See Table 2-2.
Register Address: CEH, 206
MSR_PLATFORM_INFO
Platform Information (R/O)
Package
Contains power management and other model specific features enumeration. See http://biosbits.org.
15:8
MAX_NON_TURBO_LIM_RATIO
This is the ratio of the frequency that invariant TSC runs at.
Frequency = ratio * 100 MHz.
25:16
Reserved.
26
DCU_16K_MODE_AVAIL
0b: Indicates that the part does not support the 16K DCU mode.
1b: Indicates that the part supports 16K DCU mode.
27
Reserved.
28
PRG_TURBO_RATIO_EN
Programmable Turbo Ratios per number of Active Cores.
0 = Programming Not Allowed.
1 = Programming Allowed.
34:29
Reserved.
35
BIOS_GUARD_ENABLE
Indicates whether the BIOS Guard feature is enabled in the CPU.
36
PEG2DMIDIS_EN
0 = PEG2DMIDIS is disabled.
1 = PEG2DMIDIS is enabled.
39:37
Reserved.
47:40
MAX_EFFICIENCY_RATIO
Maximum Efficiency Ratio. This is given in units of 100 MHz.
58:48
Reserved.
59
SMM_SUPOVR_STATE_LOCK_ENABLE
When set, indicates that the CPU supports MSR
SMM_SUPOVR_STATE_LOCK and the Hardware Shield feature.
63:60
Reserved.
Register Address: CFH, 207
IA32_CORE_CAPABILITIES
IA32 Core Capabilities Register (R/W)
Core
If CPUID.07H.00H:EDX[30] = 1.
This MSR provides an architectural enumeration function for model-specific behavior.
0
STLB_QOS
When set to 1, processor supports STLB QoS.
Vol. 4
2-485
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-57. Additional MSRs Supported by the Intel® Xeon® 6 E-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
1
Reserved.
2
INTEGRITY_SUPPORTED
When set to 1, processor supports Functional Safety. Specific
FUSA capabilities are enumerated in MSR_FUSA_CAPABILITIES.
3
RSM_IN_CPL0_ONLY
Intel System Resources Defense: When set to 1, RSM will only be
allowed in CPL0 and will #GP for all non-CPL0 privilege levels.
4
UC_LOCK_DISABLE
When set to 1, processor supports UC load lock disable.
5
SPLIT_LOCK_DISABLE
When set to 1, processor supports #AC on split locks.
6
SNP_FILTER_QOS
When set to 1, processor supports Snoop Filter Quality of Service
MSRs.
7
UC_STORE_THROTTLING
When set to 1, processor supports UC store throttling through
MSR_MEMORY_CTRL[UC_STORE_THROTTLE].
63:8
Reserved.
Register Address: E7H, 231
IA32_MPERF
Maximum Performance Frequency Clock Count (R/W)
Thread
See Table 2-2.
Register Address: E8H, 232
IA32_APERF
Actual Performance Frequency Clock Count (R/W)
Thread
See Table 2-2.
Register Address: FEH, 254
IA32_MTRRCAP
Memory Type Range Register (R/O)
Core
See Table 2-2.
Register Address: 140H, 320
MSR_FEATURE_ENABLES
Miscellaneous Enables for Thread-Specific Features (R/W)
Thread
0
63:1
Reserved.
Register Address: 1B0H, 432
IA32_ENERGY_PERF_BIAS
IA32_ENERGY_PERF_BIAS (R/W)
Thread
See Table 2-2.
Register Address: 1B1H, 433
IA32_PACKAGE_THERM_STATUS
IA32_PACKAGE_THERM_STATUS
Package
See Table 2-2.
Register Address: 1B2H, 434
IA32_PACKAGE_THERM_INTERRUPT
IA32_PACKAGE_THERM_INTERRUPT (R/W)
Package
See Table 2-2.
2-486 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-57. Additional MSRs Supported by the Intel® Xeon® 6 E-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 2A1H, 673
MSR_PRMRR_BASE_1
Processor Reserved Memory Range Register - Physical Base Control Register (R/W)
Core
2:0
MEMTYPE
Memory Type for PRMRR accesses.
3
CONFIGURED
PRMRR base configured.
11:4
Reserved.
51:12
BASE
PRMRR Base address.
63:52
Reserved.
Register Address: 2A2H, 674
MSR_PRMRR_BASE_2
Processor Reserved Memory Range Register - Physical Base Control Register (R/W)
Core
2:0
MEMTYPE
Memory Type for PRMRR accesses.
3
CONFIGURED
PRMRR base configured.
11:4
Reserved.
51:12
BASE
PRMRR Base address.
63:52
Reserved.
Register Address: 2A3H, 675
MSR_PRMRR_BASE_3
Processor Reserved Memory Range Register - Physical Base Control Register (R/W)
Core
2:0
MEMTYPE
Memory Type for PRMRR accesses.
3
CONFIGURED
PRMRR base configured.
11:4
Reserved.
51:12
BASE
PRMRR Base address.
63:52
Reserved.
Register Address: 2C2H, 706
MSR_COPY_SCAN_HASHES
MSR_COPY_SCAN_HASHES (W/O)
Module
63:0
SCAN_HASH-ADDR
EDX:EAX contains the linear address of the SCAN Test HASH
Binary loaded into memory
Register Address: 2C3H, 707
MSR_SCAN_HASHES_STATUS
MSR_SCAN_HASHES_STATUS (R/O)
Core
15:0
CHUNK_SIZE
EAX[15:0] - Chunk size of the test in KB.
Vol. 4
2-487
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-57. Additional MSRs Supported by the Intel® Xeon® 6 E-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
31:16
TOTAL_NUM_CHUNKS
EAX[31:16] - Total number of chunks.
39:32
ERROR_CODE
EDX[7:0] - The error code refers to the LP that runs
WRMSR(2C2H).
• 0x0 - Reserved.
• 0x1 - Attempt to copy scan-hashes when copy already in
progress.
• 0x2 - Secure Memory not set up correctly.
• 0x3 - Scan-Image Header Image_info.ProgramID does not
match MSR_INTEGRITY_CAPABILITIES[31:24], or scan-image
header Processor-Signature doesn't match F/M/S, or scan-
image header Processor-Flags doesn't match PlatformID.
• 0x4 - Reserved.
• 0x5 - Integrity check failed.
• 0x6 - WRMSR(0x2C6) Re-install of scan test image attempted
when current scan test image is in use by other LPs.
• 0x7 - Aborted due to #PF (Page Fault).
• 0x8 - Unable to generate a Random Value.
48:40
NUM_CHUNKS_IN_STRIDE
EDX[16:8] - Number of Chunks in stride. This is the number of
chunks that are installed. 0 in this field means that the CPU does
not support strides, otherwise, the stride value must be >= 1
50:49
Reserved.
EDX[18:17] - Set to all zeros.
62:51
NAME
EDX[30:19] - Maximum Number of cores that can run Intel® In-
field Scan simultaneously minus 1.
0 means 1 core at a time.
63
VALID
EDX[31] - Valid bit is set when COPY_SCAN_HASHES completed.
Register Address: 2C4H, 708
MSR_AUTHENTICATE_AND_COPY_CHUNK
MSR_AUTHENTICATE_AND_COPY_CHUNK(R/O)
Core
63:0
BASE_CHUNK_TABLE_ADDR
EDX:EAX[63:0] - Linear Address pointing to the CHUNK TABLE
(TABLE_BASE).
Register Address: 2C5H, 709
MSR_CHUNKS_AUTHENTICATION_STATUS
MSR_CHUNKS_AUTHENTICATION_STATUS (R/O)
Core
15:0
VALID_CHUNKS
EAX[15:0] - Total number of Valid (authenticated) chunks.
31:16
NUM_CHUNKS_IN_STRIDE
EAX[31:16] - Number of Chunks in Stride.
2-488 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-57. Additional MSRs Supported by the Intel® Xeon® 6 E-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
39:32
ERROR_CODE
EDX[7:0]
• 0x0 - No-error reported.
• 0x1 - Attempt to authenticate a CHUNK which is already
marked as authentic or is currently being installed by another
core.
• 0x2 - CHUNK authentication error. HASH of chunk did not
match expected value.
• 0x3 - Aborted due to #PF (Page Fault).
• 0x4 - Chunk Outside the current Stride.
63:40
Reserved.
EDX[31:8] - Set to all zeros.
Register Address: 2C6H, 710
MSR_ACTIVATE_SCAN
MSR_ACTIVATE_SCAN (W/O)
Core
15:0
CHUNK_START_INDEX
EAX[15:0] - Indicates Chunk Index from which to start.
31:16
CHUNK_STOP_INDEX
EAX[31:16] - Indicates what chunk index to stop at (inclusive).
62:32
THREAD_WAIT_DELAY
EDX[30:0] - TSC based delay to allow threads to rendezvous.
63
SIGNAL_MCE
EDX[31]
• If 1: On scan-error log MC in MC4_STATUS and signal MCE if
machine check signaling enabled in MC4_CTL[0].
• If 0: Don't no-logging/no-signaling.
Register Address: 2C7H, 711
MSR_SCAN_STATUS
MSR_SCAN_STATUS (R/O)
Core
15:0
CHUNK_NUM
EAX[15:0] - SCAN Chunk that was reached.
31:16
CHUNK_STOP_INDEX
EAX[31:16]
• Indicates what chunk index to stop at (inclusive).
• Maps to same field in WRMSR(ACTIVATE_SCAN).
Vol. 4
2-489
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-57. Additional MSRs Supported by the Intel® Xeon® 6 E-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
39:32
ERROR_CODE
EDX[7:0]
• 0x0 - No Error.
• 0x1 - SCAN operation did not start. Other thread could not join.
• 0x2 - SCAN operation did not start. Interrupt occurred prior to
SCAN coordination.
• 0x3 - SCAN operation did not start. Power Management
conditions are inadequate to run SAF.
• 0x4 - SCAN operation did not start. Non valid chunks in the
range CHUNK_STOP_INDEX : CHUNK_START_INDEX.
• 0x5 - SCAN operation did not start. Mismatch in arguments
between threads T0/T1.
• 0x6 - SCAN operation did not start. Core not capable of
performing SCAN currently.
• 0x7 - Debug Mode. Scan-At-Field results not to be trusted.
• 0x8 - SCAN operation did not start. Exceeded number of
Logical Processors (LP) allowed to run Scan-At-Field
concurrently. MAX_CORE_LIMIT exceeded.
• 0x9 - Interrupt occurred. Scan operation aborted prematurely,
not all chunks requested have been executed.
• 0xB - Scan operation aborted due to corrupted chunk.
• 0xC - Scan operation did not start.
All other error codes are reserved.
61:40
Reserved.
EDX[29:8] - Return all zeros.
62
SCAN_CONTROL_ERROR
EDX[30]
• SCAN error in the Scan-At-Field controller.
• Non ECC error.
63
SCAN_SIGNATURE_ERROR
EDX[31]
• SCAN SIGNATURE error in the SCAN pattern fetched from main
memory.
• Non ECC error.
Register Address: 2C8H, 712
MSR_SCAN_MODULE_ID
MSR_SCAN_MODULE_ID (R/O)
Module
31:0
SCAN-AT-FIELD_REVID
EAX[31:0] - Maps to Revision field in external header (offset 4).
40:32
CURRENT_STRIDE_INDEX
EDX[8:0] - Stride Index.
63:41
Reserved.
EDX[31:9] - Return all zeros.
Register Address: 2C9H, 713
MSR_LAST_SAF_WP
MSR_LAST_SAF_WP (R/O)
Module
2-490 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-57. Additional MSRs Supported by the Intel® Xeon® 6 E-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
31:0
LAST_WP
EAX[31:0]
• Provides information about the core when the last
WRMSR(ACTIVATE_SCAN) was executed.
• Available only if enumerated in
INTEGRITY_CAPABILITIES[10:9].
39:32
Reserved.
EDX[7:0]
63:40
Reserved.
EDX[31:8] - Return all zeros.
Register Address: 2D6H, 726
MSR_TRIGGER_PERIODIC_MEM_BIST
MSR_TRIGGER_PERIODIC_MEM_BIST (W/O)
Core
0
SIGNAL_MCE
EAX[0] - If 1, then signal MCE on fail if machine check signaling
enabled in the corresponding MCi_CTL. If 0 then don't signal
machine checks.
7:1
ARRAY_BANK
EAX[7:1] - Reserved.
15:8
TST_STEP_PARAM
EAX[15:8]
0: Test All Arrays, or Test Arrays in STEPs of NUM_STEPS.
31:16
Reserved.
EAX[31:16]
63:32
Reserved.
EAX[31:0]
Register Address: 2D7H, 727
MSR_PERIODIC_MEM_BIST_STATUS
MSR_PERIODIC_MEM_BIST_STATUS (R/O)
Core
0
MEM_BIST_STATUS
0: PASS.
1: FAIL.
63:1
Reserved.
Register Address: 2D9H, 729
MSR_INTEGRITY_CAPABILITIES
MSR_INTEGRITY_CAPABILITIES (R/O)
Thread
Enumerates features supported in Functional Safety.
0
STARTUP_SCAN_BIST
When set to 1, processor supports Startup SCAN BIST.
1
STARTUP_MEM_BIST
When set to 1, processor supports Startup MEM BIST.
2
PERIODIC_MEM_BIST
When set to 1, processor supports Periodic MEM BIST.
Vol. 4
2-491
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-57. Additional MSRs Supported by the Intel® Xeon® 6 E-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
3
LOCKSTEP
When set to 1, processor supports Lock Step Mode.
4
PERIODIC_SCAN_BIST
When set to 1, processor supports Periodic SCAN BIST.
5
PLL_LOSS_DETECT
When set to 1, processor supports PLL LOSS detection.
6
PWR_LOSS_DETECT
When set to 1, processor supports Power Loss detection.
7
PERRINJ
When set to 1, processor supports FUSA PERRINJ.
8
SBFT_AT_FIELD
When set to 1, processor supports SBFT-At-Field.
10:9
SAF_GEN_REV
00 = REV1; 01 = REV2; 10 = REV3; 11 = REV4.
14:11
Reserved.
15
PRESERVE_MEMORY_NEEDED
When set to 1, processor supports FUSARR_BASE/MASK MSRs.
20:16
TID_BIT_SHIFT
Number of bits to shift right on x2APICID to get a unique topology
ID of all logical processors that share a scan test engine.
21
ALL_LP_JOIN_NEEDED
All logical processors that share scan test engine need to be
tested together and must join using MSR_ACTIVATE_SCAN.
23:22
Reserved.
31:24
PATTERN_ID
Processor scan pattern ID. ID of the startup and periodic scan
programs supported for this part.
63:32
Reserved.
Register Address: 2DCH, 732
IA32_INTEGRITY_STATUS
IA32_INTEGRITY_STATUS (R/O)
Thread
Provides status information for integrity features. See Table 2-2.
Register Address: 3F9H, 1017
MSR_PKG_C6_RESIDENCY
MSR_PKG_C6_RESIDENCY (R/O)
Package
63:0
Package C6 Residency Counter
Register Address: 3FAH, 1018
MSR_PKG_C7_RESIDENCY
MSR_PKG_C7_RESIDENCY (R/O)
Package
63:0
Package C7 Residency Counter
Register Address: 3FCH, 1020
MSR_CORE_C3_RESIDENCY
2-492 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-57. Additional MSRs Supported by the Intel® Xeon® 6 E-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
MSR_CORE_C3_RESIDENCY (R/O)
Core
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
63:0
CORE C3 Residency Counter
Time spent in the Core C-State. Provided in units compatible to P1
clock frequency (Guaranteed / Maximum Core Non-Turbo
Frequency).
Register Address: 3FDH, 1021
MSR_CORE_C6_RESIDENCY
MSR_CORE_C6_RESIDENCY (R/O)
Core
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
63:0
CORE C6 Residency Counter
Time spent in the Core C-State. Provided in units compatible to P1
clock frequency (Guaranteed / Maximum Core Non-Turbo
Frequency).
Register Address: 3FEH, 1022
MSR_CORE_C7_RESIDENCY
MSR_CORE_C7_RESIDENCY (R/O)
Core
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
63:0
CORE C7 Residency Counter
Time spent in the Core C-State. Provided in units compatible to P1
clock frequency (Guaranteed / Maximum Core Non-Turbo
Frequency).
Register Address: 4F0H, 1264
MSR_SAF_CTRL
MSR_SAF_CTRL (W/O)
Core
0
INVALIDATE_CURRENT_STRIDE
EAX[0]
• Write of 1 invalidates the currently installed stride.
• Clears only the VALID_CHUNKS field on a
RDMSR(CHUNKS_AUTHENTICATION_STATUS).
63:1
Reserved.
Register Address: 664H, 1636
MSR_MC6_RESIDENCY
MSR_MC6_RESIDENCY (R/O)
Module
Time spent in the Module C6-State. Provided in units compatible to P1 clock frequency (Guaranteed / Maximum Core
Non-Turbo Frequency).
63:0
RESIDENCY
Time that this module is in module-specific C6 states since last
reset.
Register Address: 6E0H, 1760
IA32_TSC_DEADLINE
TSC Target of Local APIC’s TSC Deadline Mode (R/W)
Thread
See Table 2-2.
Register Address: 7A3H, 1955
IA32_MCU_EXT_SERVICE
Vol. 4
2-493
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-57. Additional MSRs Supported by the Intel® Xeon® 6 E-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
MCU Extended Service (R/W)
Module
See Table 2-2.
Register Address: 7A4H, 1956
IA32_MCU_ROLLBACK_MIN_ID
Minimal MCU Revision ID (R/O)
Module
See Table 2-2.
Register Address: 7A5H, 1957
IA32_MCU_STAGING_MBOX_ADDR
IA32_MCU_STAGING_MBOX_ADDR (R/O)
Package
See Table 2-2.
Register Address: 7BOH, 1968
IA32_ROLLBACK_SIGN_ID_0
Rollback ID 0 (R/O)
Module
See Table 2-2.
Register Address: 7B1H, 1969
IA32_ROLLBACK_SIGN_ID_1
Rollback ID 1 (R/O)
Module
See Table 2-2.
Register Address: 7B2H, 1970
IA32_ROLLBACK_SIGN_ID_2
Rollback ID 2 (R/O)
Module
See Table 2-2.
Register Address: 7B3H, 1971
IA32_ROLLBACK_SIGN_ID_3
Rollback ID 3 (R/O)
Module
See Table 2-2.
Register Address: 7B4H, 1972
IA32_ROLLBACK_SIGN_ID_4
Rollback ID 4 (R/O)
Module
See Table 2-2.
Register Address: 7B5H, 1973
IA32_ROLLBACK_SIGN_ID_5
Rollback ID 5 (R/O)
Module
See Table 2-2.
Register Address: 7B6H, 1974
IA32_ROLLBACK_SIGN_ID_6
Rollback ID 6 (R/O)
Module
See Table 2-2.
Register Address: 7B7H, 1975
IA32_ROLLBACK_SIGN_ID_7
Rollback ID 7 (R/O)
Module
See Table 2-2.
Register Address: 7B8H, 1976
IA32_ROLLBACK_SIGN_ID_8
Rollback ID 8 (R/O)
Module
See Table 2-2.
Register Address: 7B9H, 1977
IA32_ROLLBACK_SIGN_ID_9
Rollback ID 9 (R/O)
Module
See Table 2-2.
Register Address: 7BAH, 1978
IA32_ROLLBACK_SIGN_ID_10
2-494 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-57. Additional MSRs Supported by the Intel® Xeon® 6 E-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Rollback ID 10 (R/O)
Module
See Table 2-2.
Register Address: 7BBH, 1979
IA32_ROLLBACK_SIGN_ID_11
Rollback ID 11 (R/O)
Module
See Table 2-2.
Register Address: 7BCH, 1980
IA32_ROLLBACK_SIGN_ID_12
Rollback ID 12 (R/O)
Module
See Table 2-2.
Register Address: 7BDH, 1981
IA32_ROLLBACK_SIGN_ID_13
Rollback ID 13 (R/O)
Module
See Table 2-2.
Register Address: 7BEH, 1982
IA32_ROLLBACK_SIGN_ID_14
Rollback ID 14 (R/O)
Module
See Table 2-2.
Register Address: 7BFH, 1983
IA32_ROLLBACK_SIGN_ID_15
Rollback ID 15 (R/O)
Module
See Table 2-2.
Register Address: 988H, 2440
IA32_UINTR_NV
User Interrupt Size and Notification Vector (R/W)
Thread
See Table 2-2.
Register Address: 9FBH, 2555
IA32_TME_CLEAR_SAVED_KEY
IA32_TME_CLEAR_SAVED_KEY (R/W)
Package
See Table 2-2.
Register Address: 9FFH, 2559
MSR_CORE_MKTME_ACTIVATE
MSR_CORE_MKTME_ACTIVATE (R/O)
Core
MSR to read TME_ACTIVATE[MK_TME_KEYID_BITS].
31:0
Reserved.
35:32
READ_MK_TME_KEYID_BITS
This value will be returned on a RDMSR, but must be zero on a
WRMSR.
39:36
TDX_RESERVED_KEYID_BITS (read only)
The number of key identifier bits allocated to TDX usage.
This is a read-only field. #GP on a non-zero write.
63:40
Reserved.
Register Address: C84H, 3204
MSR_MBA_CFG
Memory Bandwidth Allocation (MBA) Configuration (R/W)
Package
1:0
Reserved.
2
RAMBAE
Resource Aware MBA Enable.
Vol. 4
2-495
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-57. Additional MSRs Supported by the Intel® Xeon® 6 E-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
63:3
Reserved.
Register Address: CA0H, 3232
MSR_RMID_SNC_CONFIG
MSR_RMID_SNC_CONFIG (R/W)
Package
0
RMID_LOCALIZED_DISTRIBUTION_MODE_ENABLE
If set, Localized RMID distribution mode is enabled. If Clear, RMID
Sharing mode is enabled.
63:1
Reserved.
Register Address: D50H, 3408
IA32_L2_QOS_EXT_BW_THRTL_0
Memory Bandwidth Enforcement for COS0 (R/W)
Package
See Table 2-2.
Register Address: D51H, 3409
IA32_L2_QOS_EXT_BW_THRTL_1
Memory Bandwidth Enforcement for COS1 (R/W)
Package
See Table 2-2.
Register Address: D52H, 3410
IA32_L2_QOS_EXT_BW_THRTL_2
Memory Bandwidth Enforcement for COS2 (R/W)
Package
See Table 2-2.
Register Address: D53H, 3411
IA32_L2_QOS_EXT_BW_THRTL_3
Memory Bandwidth Enforcement for COS3 (R/W)
Package
See Table 2-2.
Register Address: D54H, 3412
IA32_L2_QOS_EXT_BW_THRTL_4
Memory Bandwidth Enforcement for COS4 (R/W)
Package
See Table 2-2.
Register Address: D55H, 3413
IA32_L2_QOS_EXT_BW_THRTL_5
Memory Bandwidth Enforcement for COS5 (R/W)
Package
See Table 2-2.
Register Address: D56H, 3414
IA32_L2_QOS_EXT_BW_THRTL_6
Memory Bandwidth Enforcement for COS6 (R/W)
Package
See Table 2-2.
Register Address: D57H, 3415
IA32_L2_QOS_EXT_BW_THRTL_7
Memory Bandwidth Enforcement for COS7 (R/W)
Package
See Table 2-2.
Register Address: D58H, 3416
IA32_L2_QOS_EXT_BW_THRTL_8
Memory Bandwidth Enforcement for COS8 (R/W)
Package
See Table 2-2.
Register Address: D59H, 3417
IA32_L2_QOS_EXT_BW_THRTL_9
Memory Bandwidth Enforcement for COS9 (R/W)
Package
See Table 2-2.
Register Address: D5AH, 3418
IA32_L2_QOS_EXT_BW_THRTL_10
2-496 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-57. Additional MSRs Supported by the Intel® Xeon® 6 E-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Memory Bandwidth Enforcement for COS10 (R/W)
Package
See Table 2-2.
Register Address: D5BH, 3419
IA32_L2_QOS_EXT_BW_THRTL_11
Memory Bandwidth Enforcement for COS11 (R/W)
Package
See Table 2-2.
Register Address: D5CH, 3420
IA32_L2_QOS_EXT_BW_THRTL_12
Memory Bandwidth Enforcement for COS12 (R/W)
Package
See Table 2-2.
Register Address: D5DH, 3421
IA32_L2_QOS_EXT_BW_THRTL_13
Memory Bandwidth Enforcement for COS13 (R/W)
Package
See Table 2-2.
Register Address: D5EH, 3422
IA32_L2_QOS_EXT_BW_THRTL_14
Memory Bandwidth Enforcement for COS14 (R/W)
Package
See Table 2-2.
Register Address: E00H, 3584
IA32_QOS_CORE_BW_THRTL_0
CBA Levels Based on COS for Bandwidth Throttling (R/W)
Thread
See Table 2-2.
Register Address: E01H, 3585
IA32_QOS_CORE_BW_THRTL_1
CBA Levels Based on COS for Bandwidth Throttling (R/W)
Thread
See Table 2-2.
Register Address: 1400H, 5120
IA32_SEAMRR_BASE
SEAM Memory Range Register for TDX - Base Address (R/W)
Core
See Table 2-2.
Register Address: 1401H, 5121
IA32_SEAMRR_MASK
SEAM Memory Range Register for TDX (R/W)
Core
See Table 2-2.
Register Address: 1A8FH, 6799
MSR_STLB_QOS_INFO
STLB_QOS_INFO (R/O)
Core
STLB QoS MASK configuration.
5:0
NCLOS
Number of CLOS supported for STLB resource using minus-1
notation.
15:6
Reserved.
19:16
4K_2M_CBM
Length of capacity bitmask for 4K and 2M pages using minus-1
notation.
28:20
Reserved.
29
STLB_FILL_TRANSLATION_MSR_SUPPORTED
MSR interface to fill STLB translations supported.
Vol. 4
2-497
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-57. Additional MSRs Supported by the Intel® Xeon® 6 E-Core Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
30
4K_2M_ALIAS
Indicates that 4K/2M pages alias into the same structure.
63:31
Reserved.
2.17.12 MSRs Introduced in the Intel® Series 2 Core™ Ultra Processor Supporting Performance
Hybrid Architecture
Table 2-58 lists additional MSRs for the Intel Series 2 Core Ultra processor with a CPUID Signature
DisplayFamily_DisplayModel value of 06_BDH. Table 2-59 lists the MSRs unique to the processor P-core. Table 2-60
lists the MSRs unique to the processor E-core.
For an MSR listed in Table 2-58, Table 2-59, or Table 2-60 that also appears in the model-specific tables of prior
generations, Table 2-58, Table 2-59, and Table 2-60 supersede prior generation tables.
Table 2-58. Additional MSRs Supported by the Intel® Series 2 Core™ Ultra Processors Supporting Performance
Hybrid Architecture
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 8BH, 139
IA32_BIOS_SIGN_ID
BIOS Update Signature ID (R/W)
Thread
See Table 2-2.
Register Address: 19AH, 410
IA32_CLOCK_MODULATION
Clock Modulation (R/W)
Thread
See Table 2-2.
Register Address: 601H, 1537
MSR_PKG_POWER_LIMIT_4
Package Power Limit 4 (R/W)
Package
Package-level maximum power limit (in Watts).
15:0
POWER_LIMIT_4
PL4 Value in 0.125 W increments. This field is locked by
PKG_POWER_LIMIT_4.LOCK. When the LOCK bit is set to 1, this
field becomes Read Only.
If the value is 0, PL4 limit is disabled.
30:16
Reserved.
31
LOCK
This bit will lock the POWER_LIMIT_4 settings in this register and
will also lock this setting. This means that once set to 1, the
POWER_LIMIT_4 setting and this bit become Read Only until the
next Warm Reset.
63:32
Reserved.
Register Address: 630H, 1584
MSR_PKG_C8_RESIDENCY
MSR_PKG_C8_RESIDENCY (R/O)
Package
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
2-498 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-58. Additional MSRs Supported by the Intel® Series 2 Core™ Ultra Processors Supporting Performance
Hybrid Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
59:0
Package C8 Residency Counter
Value since last reset that this package is in processor-specific C8
states. Count at the same frequency as the TSC.
63:60
Reserved.
Register Address: 631H, 1585
MSR_PKG_C9_RESIDENCY
MSR_PKG_C9_RESIDENCY (R/O)
Package
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
59:0
Package C9 Residency Counter
Value since last reset that this package is in processor-specific C9
states. Count at the same frequency as the TSC.
63:60
Reserved.
Register Address: 632H, 1586
MSR_PKG_C10_RESIDENCY
MSR_PKG_C10_RESIDENCY (R/O)
Package
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
59:0
Package C10 Residency Counter
Value since last reset that this package is in processor-specific
C10 states. Count at the same frequency as the TSC.
63:60
Reserved.
Register Address: 651H, 1617
MSR_SECONDARY_TURBO_RATIO_LIMIT_CORES
SECONDARY_TURBO_RATIO_LIMIT_CORES (R/W)
Package
This register defines the active core ranges for each frequency point.
•
NUMCORE[0:7] must be populated in ascending order.
•
NUMCORE[i+1] must be greater than NUMCORE[i].
•
Entries with NUMCORE[i] == 0 will be ignored.
•
The last valid entry must have NUMCORE >= the number of cores in the SKU.
If any of the rules above are broken, we will silently reject the configuration.
7:0
CORE_COUNT_0
Defines the active core ranges for each frequency point.
15:8
CORE_COUNT_1
Defines the active core ranges for each frequency point.
23:16
CORE_COUNT_2
Defines the active core ranges for each frequency point.
31:24
CORE_COUNT_3
Defines the active core ranges for each frequency point.
39:32
CORE_COUNT_4
Defines the active core ranges for each frequency point.
47:40
CORE_COUNT_5
Defines the active core ranges for each frequency point.
55:48
CORE_COUNT_6
Defines the active core ranges for each frequency point.
Vol. 4
2-499
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-58. Additional MSRs Supported by the Intel® Series 2 Core™ Ultra Processors Supporting Performance
Hybrid Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
63:56
CORE_COUNT_7
Defines the active core ranges for each frequency point.
Register Address: 658H, 1624
MSR_WEIGHTED_CORE_C0
Core-Count Weighted C0 Residency (R/O)
Package
63:0
DATA
Increment at the same rate as the TSC. The increment each cycle
is weighted by the number of processor cores in the package that
reside in C0. If N cores are simultaneously in C0, then each cycle
the counter increments by N.
Register Address: 659H, 1625
MSR_ANY_CORE_C0
Any Core C0 Residency (R/O)
Package
63:0
DATA
Increment at the same rate as the TSC. The increment each cycle
is weighted by the number of processor cores in the package that
reside in C0. If N cores are simultaneously in C0, then each cycle
the counter increments by N.
Register Address: 65AH, 1626
MSR_ANY_GFXE_C0
Any Graphics Engine C0 Residency (R/O)
Package
63:0
DATA
Increment at the same rate as the TSC. The increment each cycle
is one if any processor graphic device's compute engines are in
C0.
Register Address: 65BH, 1627
MSR_CORE_GFXE_OVERLAP_C0
Core and Graphics Engine Overlapped C0 Residency (R/O)
Package
63:0
DATA
Increment at the same rate as the TSC. The increment each cycle
is one if at least one compute engine of the processor graphics is
in C0 and at least one processor core in the package is also in C0.
Register Address: C88H, 3208
IA32_RESOURCE_PRIORITY
Thread scope Resource Priority Enable (R/W)
Thread
See Table 2-2.
Register Address: C89H, 3209
IA32_RESOURCE_PRIORITY_PKG
IA32_RESOURCE_PRIORITY_PKG (R/W)
Package
See Table 2-2.
Register Address: 1900H, 6400
IA32_PMC_GP0_CTR
Full Width Writable General Performance Counter 0 (R/W)
Thread
See Table 2-2.
Register Address: 1901H, 6401
IA32_PMC_GP0_CFG_A
IA32_PMC_GP0_CFG_A (R/W)
Thread
Performance Event Select Register used to control the operation of the General Performance Counter 0.
See Table 2-2.
2-500 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-58. Additional MSRs Supported by the Intel® Series 2 Core™ Ultra Processors Supporting Performance
Hybrid Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 1904H, 6404
IA32_PMC_GP1_CTR
Full Width Writable General Performance Counter 1 (R/W)
Thread
See Table 2-2.
Register Address: 1905H, 6405
IA32_PMC_GP1_CFG_A
IA32_PMC_GP1_CFG_A (R/W)
Thread
Performance Event Select Register used to control the operation of the General Performance Counter 1.
See Table 2-2.
Register Address: 1908H, 6408
IA32_PMC_GP2_CTR
Full Width Writable General Performance Counter 2 (R/W)
Thread
See Table 2-2.
Register Address: 1909H, 6409
IA32_PMC_GP2_CFG_A
IA32_PMC_GP2_CFG_A (R/W)
Thread
Performance Event Select Register used to control the operation of the General Performance Counter 2.
See Table 2-2.
Register Address: 190CH, 6412
IA32_PMC_GP3_CTR
Full Width Writable General Performance Counter 3 (R/W)
Thread
See Table 2-2.
Register Address: 190DH, 6413
IA32_PMC_GP3_CFG_A
IA32_PMC_GP3_CFG_A (R/W)
Thread
Performance Event Select Register used to control the operation of the General Performance Counter 3.
See Table 2-2.
Register Address: 1910H, 6416
IA32_PMC_GP4_CTR
Full Width Writable General Performance Counter 4 (R/W)
Thread
See Table 2-2.
Register Address: 1911H, 6417
IA32_PMC_GP4_CFG_A
IA32_PMC_GP4_CFG_A (R/W)
Thread
Performance Event Select Register used to control the operation of the General Performance Counter 4.
See Table 2-2.
Register Address: 1914H, 6420
IA32_PMC_GP5_CTR
Full Width Writable General Performance Counter 5 (R/W)
Thread
See Table 2-2.
Register Address: 1915H, 6421
IA32_PMC_GP5_CFG_A
IA32_PMC_GP5_CFG_A (R/W)
Thread
Performance Event Select Register used to control the operation of the General Performance Counter 5.
See Table 2-2.
Register Address: 1918H, 6424
IA32_PMC_GP6_CTR
Full Width Writable General Performance Counter 6 (R/W)
Thread
See Table 2-2.
Register Address: 1919H, 6425
IA32_PMC_GP6_CFG_A
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-58. Additional MSRs Supported by the Intel® Series 2 Core™ Ultra Processors Supporting Performance
Hybrid Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
IA32_PMC_GP6_CFG_A (R/W)
Thread
Performance Event Select Register used to control the operation of the General Performance Counter 6.
See Table 2-2.
Register Address: 191CH, 6428
IA32_PMC_GP7_CTR
Full Width Writable General Performance Counter 7 (R/W)
Thread
See Table 2-2.
Register Address: 191DH, 6429
IA32_PMC_GP7_CFG_A
IA32_PMC_GP7_CFG_A (R/W)
Thread
Performance Event Select Register used to control the operation of the General Performance Counter 7.
See Table 2-2.
Register Address: 1980H, 6528
IA32_PMC_FX0_CTR
IA32_PMC_FX0_CTR (R/W)
Thread
Fixed-Function Performance Counter 0 - Instructions Retired. See Table 2-2.
Register Address: 1984H, 6532
IA32_PMC_FX1_CTR
IA32_PMC_FX1_CTR (R/W)
Thread
Fixed-Function Performance Counter 1 - Unhalted core clock cycles. See Table 2-2.
Register Address: 1988H, 6536
IA32_PMC_FX2_CTR
IA32_PMC_FX2_CTR (R/W)
Thread
Fixed-Function Performance Counter 2 - Unhalted core reference cycles. See Table 2-2.
The MSRs listed in Table 2-59 are unique to the Intel Series 2 Core Ultra processor P-core. These MSRs are not
supported on the processor E-core.
Table 2-59. MSRs Supported by the Intel® Series 2 Core™ Ultra Processor P-core
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: C9H, 201
IA32_PMC8
General Performance Counter 8 (R/W)
Thread
See Table 2-2.
Register Address: CAH, 202
IA32_PMC9
General Performance Counter 9 (R/W)
Thread
See Table 2-2.
Register Address: 18EH, 398
IA32_PERFEVTSEL8
Performance Event Select Register 8 (R/W)
Thread
See Table 2-2.
Register Address: 18FH, 399
IA32_PERFEVTSEL9
Performance Event Select Register 9 (R/W)
Thread
See Table 2-2.
Register Address: 30CH, 780
IA32_FIXED_CTR3
2-502 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-59. MSRs Supported by the Intel® Series 2 Core™ Ultra Processor P-core (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Fixed-Function Performance Counter 3 (R/W)
Thread
See Table 2-2.
Register Address: 329H, 809
MSR_PERF_METRICS
MSR_PERF_METRICS (R/W)
Thread
This register provides built-in support for Top-down Micro-architecture Analysis (TMA) metrics. It exposes the four
TMA Level 1 metrics where the lower 32 bits are divided into four 8 bit fields, each of which is an integer percentage
of the total TOPDOWN.SLOTS (as reported by fixed-function counter 3).
7:0
RETIRING
Percent of utilized by uops that eventually retire (commit).
15:8
BAD_SPECULATION
Percent of Wasted due to incorrect speculation, covering Utilized by
uops that do not retire, or Recovery Bubbles (unutilized slots).
23:16
FRONTEND_BOUND
Percent of Unutilized slots where Front-end did not deliver a uop
while Back-end is ready.
31:24
BACKEND_BOUND
Percent of Unutilized slots where a uop was not delivered to Back-
end due to lack of Back-end resources.
39:32
MULTI_UOPS
Frontend bound.
47:40
BRANCH_MISPREDICTS
Frontend bound.
55:48
FRONTEND_LATENCY
Frontend bound.
63:56
MEMORY_BOUND
Frontend bound.
Register Address: 4C9H, 1225
IA32_A_PMC8
Full Width Writable IA32_PMC8 Alias (R/W)
Thread
See Table 2-2.
Register Address: 4CAH, 1226
IA32_A_PMC9
Full Width Writable IA32_PMC9 Alias (R/W)
Thread
See Table 2-2.
Register Address: 540H, 1344
MSR_THREAD_UARCH_CTL
Thread Uarch Control (R/W)
Thread
0
WB_MEM_STRM_LD_DISABLE
Disable streaming behavior for MOVNTDQA loads to WB memory
type. If set, these accesses will be treated like regular cacheable
loads (Data will be cached).
63:1
Reserved.
Register Address: 540H, 1344
MSR_CORE_UARCH_CTL
Core Uarch Control (R/W)
Core
Vol. 4
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-59. MSRs Supported by the Intel® Series 2 Core™ Ultra Processor P-core (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
0
SCRUB_DIS
L1 scrubbing disable.
63:1
Reserved.
Register Address: 1920H, 6432
IA32_PMC_GP8_CTR
Full Width Writable General Performance Counter 8 (R/W)
Thread
See Table 2-2.
Register Address: 1921H, 6433
IA32_PMC_GP8_CFG_A
IA32_PMC_GP8_CFG_A (R/W)
Thread
Performance Event Select Register used to control the operation of the General Performance Counter 8.
See Table 2-2.
Register Address: 1924H, 6436
IA32_PMC_GP9_CTR
Full Width Writable General Performance Counter 9 (R/W)
Thread
See Table 2-2.
Register Address: 1925H, 6437
IA32_PMC_GP9_CFG_A
IA32_PMC_GP9_CFG_A (R/W)
Thread
Performance Event Select Register used to control the operation of the General Performance Counter 9.
See Table 2-2.
Register Address: 198CH, 6540
IA32_PMC_FX3_CTR
IA32_PMC_FX3_CTR (R/W)
Thread
See Table 2-2.
The MSRs listed in Table 2-60 are unique to the Intel Series 2 Core Ultra processor E-core. These MSRs are not
supported on the processor P-core.
Table 2-60. MSRs Supported by the Intel® Series 2 Core™ Ultra Processor E-core
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 2DCH, 732
IA32_INTEGRITY_STATUS
Status Information for Integrity Features (R/O)
Thread
See Table 2-2.
Register Address: 30DH, 781
IA32_FIXED_CTR4
Fixed-Function Performance Counter 4 - Top-down Bad Speculation (R/W)
Thread
See Table 2-2.
Register Address: 30EH, 782
IA32_FIXED_CTR5
Fixed-Function Performance Counter 5 - Top-down Frontend Bound (R/W)
Thread
See Table 2-2.
Register Address: 30FH, 783
IA32_FIXED_CTR6
Fixed-Function Performance Counter 6 - Top-down Retiring (R/W)
Thread
See Table 2-2.
Register Address: D18H, 3352
IA32_L2_MASK_8
2-504 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-60. MSRs Supported by the Intel® Series 2 Core™ Ultra Processor E-core (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
L2 CAT Mask for COS8 (R/W)
Module
See Table 2-2.
Register Address: D19H, 3353
IA32_L2_MASK_9
L2 CAT Mask for COS9 (R/W)
Module
See Table 2-2.
Register Address: D1AH, 3354
IA32_L2_MASK_10
L2 CAT Mask for COS10 (R/W)
Module
See Table 2-2.
Register Address: D1BH, 3355
IA32_L2_MASK_11
L2 CAT Mask for COS11 (R/W)
Module
See Table 2-2.
Register Address: D1CH, 3356
IA32_L2_MASK_12
L2 CAT Mask for COS12 (R/W)
Module
See Table 2-2.
Register Address: D1DH, 3357
IA32_L2_MASK_13
L2 CAT Mask for COS13 (R/W)
Module
See Table 2-2.
Register Address: D1EH, 3358
IA32_L2_MASK_14
L2 CAT Mask for COS14 (R/W)
Module
See Table 2-2.
Register Address: D1FH, 3359
IA32_L2_MASK_15
L2 CAT Mask for COS15 (R/W)
Module
See Table 2-2.
Register Address: 1878H, 6264
MSR_WORK_CONSERVING_CLOS
Work Conserving CLOS (R/W)
Module
0
WC_VALID
WC Valid Bit that indicates WC MSR has been setup. This bit must
be set for the WC algorithm to be enabled.
7:1
Reserved.
11:8
CLOS_START_PRI1
Starting CLOS range for priority 1.
15:12
CLOS_END_PRI1
Ending CLOS range for priority 1.
19:16
CLOS_START_PRI2
Starting CLOS range for priority 2.
23:20
CLOS_END_PRI2
Ending CLOS range for priority 2.
27:24
CLOS_START_PRI3
Starting CLOS range for priority 3.
Vol. 4
2-505
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-60. MSRs Supported by the Intel® Series 2 Core™ Ultra Processor E-core (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
31:28
CLOS_END_PRI3
Ending CLOS range for priority 3.
63:32
Reserved.
Register Address: 1903H, 6403
IA32_PMC_GP0_CFG_C
IA32_PMC_GP0_CFG_C (R/W)
Thread
See Table 2-2.
Register Address: 1907H, 6407
IA32_PMC_GP1_CFG_C
IA32_PMC_GP1_CFG_C (R/W)
Thread
See Table 2-2.
Register Address: 190AH, 6410
IA32_PMC_GP2_CFG_B
IA32_PMC_GP2_CFG_B (R/W)
Thread
See Table 2-2.
Register Address: 190BH, 6411
IA32_PMC_GP2_CFG_C
IA32_PMC_GP2_CFG_C (R/W)
Thread
See Table 2-2.
Register Address: 190EH, 6414
IA32_PMC_GP3_CFG_B
IA32_PMC_GP3_CFG_B (R/W)
Thread
See Table 2-2.
Register Address: 190FH, 6415
IA32_PMC_GP3_CFG_C
IA32_PMC_GP3_CFG_C (R/W)
Thread
See Table 2-2.
Register Address: 1912H, 6418
IA32_PMC_GP4_CFG_B
IA32_PMC_GP4_CFG_B (R/W)
Thread
See Table 2-2.
Register Address: 1913H, 6419
IA32_PMC_GP4_CFG_C
IA32_PMC_GP4_CFG_C (R/W)
Thread
See Table 2-2.
Register Address: 1916H, 6422
IA32_PMC_GP5_CFG_B
IA32_PMC_GP5_CFG_B (R/W)
Thread
See Table 2-2.
Register Address: 1917H, 6423
IA32_PMC_GP5_CFG_C
IA32_PMC_GP5_CFG_C (R/W)
Thread
See Table 2-2.
Register Address: 191AH, 6426
IA32_PMC_GP6_CFG_B
IA32_PMC_GP6_CFG_B (R/W)
Thread
See Table 2-2.
Register Address: 191BH, 6427
IA32_PMC_GP6_CFG_C
IA32_PMC_GP6_CFG_C (R/W)
Thread
See Table 2-2.
2-506 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-60. MSRs Supported by the Intel® Series 2 Core™ Ultra Processor E-core (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 191EH, 6430
IA32_PMC_GP7_CFG_B
IA32_PMC_GP7_CFG_B (R/W)
Thread
See Table 2-2.
Register Address: 191FH, 6431
IA32_PMC_GP7_CFG_C
IA32_PMC_GP7_CFG_C (R/W)
Thread
See Table 2-2.
Register Address: 1982H, 6530
IA32_PMC_FX0_CFG_B
Fixed-Function Counter Reload Configuration Register (R/W)
Thread
See Table 2-2.
Register Address: 1983H, 6531
IA32_PMC_FX0_CFG_C
Extended Perf Event Selector for Fixed-Function Counter 0 (R/W)
Thread
See Table 2-2.
Register Address: 1986H, 6534
IA32_PMC_FX1_CFG_B
Fixed-Function Counter Reload Configuration Register (R/W)
Thread
See Table 2-2.
Register Address: 1987H, 6535
IA32_PMC_FX1_CFG_C
Extended Perf Event Selector for Fixed-Function Counter 1 (R/W)
Thread
See Table 2-2.
Register Address: 198BH, 6539
IA32_PMC_FX2_CFG_C
Extended Perf Event Selector for Fixed-Function Counter 2 (R/W)
Thread
See Table 2-2.
Register Address: 1990H, 6544
IA32_PMC_FX4_CTR
Fixed-Function Performance Counter 4 - Top-down Bad Speculation (R/W)
Thread
See Table 2-2.
Register Address: 1993H, 6547
IA32_PMC_FX4_CFG_C
Extended Perf Event Selector for Fixed-Function Counter 4 (R/W)
Thread
See Table 2-2.
Register Address: 1994H, 6548
IA32_PMC_FX5_CTR
Fixed-Function Performance Counter 5 - Top-down Frontend Bound (R/W)
Thread
See Table 2-2.
Register Address: 1997H, 6551
IA32_PMC_FX5_CFG_C
Extended Perf Event Selector for Fixed-Function Counter 5 (R/W)
Thread
See Table 2-2.
Register Address: 1998H, 6552
IA32_PMC_FX6_CTR
Fixed-Function Performance Counter 5 - Top-down Bad Retiring (R/W)
Thread
See Table 2-2.
Register Address: 199BH, 6555
IA32_PMC_FX6_CFG_C
Extended Perf Event Selector for Fixed-Function Counter 6 (R/W)
Thread
See Table 2-2.
Vol. 4
2-507
MODEL-SPECIFIC REGISTERS (MSRS)
2.18
MSRS IN THE INTEL® XEON PHI™ PROCESSOR 3200/5200/7200 SERIES
AND THE INTEL® XEON PHI™ PROCESSOR 7215/7285/7295 SERIES
The Intel® Xeon Phi™ processor 3200, 5200, 7200 series, with a CPUID Signature DisplayFamily_DisplayModel
value of 06_57H, supports the MSR interfaces listed in Table 2-61. These processors are based on the Knights
Landing microarchitecture. The Intel® Xeon Phi™ processor 7215, 7285, 7295 series, with a CPUID Signature
DisplayFamily_DisplayModel value of 06_85H, supports the MSR interfaces listed in Table 2-61 and Table 2-62.
These processors are based on the Knights Mill microarchitecture. Some MSRs are shared between a pair of
processor cores, and the scope is marked as module.
Table 2-61. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 0H, 0
IA32_P5_MC_ADDR
See Section 2.23, “MSRs in Pentium Processors.”
Module
Register Address: 1H, 1
IA32_P5_MC_TYPE
See Section 2.23, “MSRs in Pentium Processors.”
Module
Register Address: 6H, 6
IA32_MONITOR_FILTER_SIZE
See Section 11.10.5, “Monitor/Mwait Address Range Determination.” See Table 2-2.
Thread
Register Address: 10H, 16
IA32_TIME_STAMP_COUNTER
See Section 20.17, “Time-Stamp Counter,” and Table 2-2.
Thread
Register Address: 17H, 23
IA32_PLATFORM_ID
Platform ID (R)
Package
See Table 2-2.
Register Address: 1BH, 27
IA32_APIC_BASE
See Section 13.4.4, “Local APIC Status and Location,” and Table 2-2.
Thread
Register Address: 34H, 52
MSR_SMI_COUNT
SMI Counter (R/O)
Thread
31:0
SMI Count (R/O)
63:32
Reserved.
Register Address: 3AH, 58
IA32_FEATURE_CONTROL
Control Features in Intel 64Processor (R/W)
Thread
See Table 2-2.
0
Lock. (R/WL)
1
Reserved.
2
Enable VMX outside SMX operation. (R/WL)
Register Address: 3BH, 59
IA32_TSC_ADJUST
Per-Logical-Processor TSC ADJUST (R/W)
Thread
See Table 2-2.
Register Address: 4EH, 78
IA32_PPIN_CTL (MSR_PPIN_CTL)
Protected Processor Inventory Number Enable Control (R/W)
Package
0
LockOut (R/WO)
See Table 2-2.
2-508 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-61. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
1
Enable_PPIN (R/W)
See Table 2-2.
63:2
Reserved
Register Address: 4FH, 79
IA32_PPIN (MSR_PPIN)
Protected Processor Inventory Number (R/O)
Package
63:0
Protected Processor Inventory Number (R/O)
See Table 2-2.
Register Address: 79H, 121
IA32_BIOS_UPDT_TRIG
BIOS Update Trigger Register (W)
Core
See Table 2-2.
Register Address: 8BH, 139
IA32_BIOS_SIGN_ID
BIOS Update Signature ID (R/W)
Thread
See Table 2-2.
Register Address: C1H, 193
IA32_PMC0
Performance Counter Register
Thread
See Table 2-2.
Register Address: C2H, 194
IA32_PMC1
Performance Counter Register
Thread
See Table 2-2.
Register Address: CEH, 206
MSR_PLATFORM_INFO
Platform Information
Package
Contains power management and other model specific features enumeration. See http://biosbits.org.
7:0
Reserved.
15:8
Maximum Non-Turbo Ratio (R/O)
Package
This is the ratio of the frequency that invariant TSC runs at. Frequency
= ratio * 100 MHz.
27:16
Reserved.
28
Programmable Ratio Limit for Turbo Mode (R/O)
Package
When set to 1, indicates that Programmable Ratio Limit for Turbo mode
is enabled. When set to 0, indicates Programmable Ratio Limit for Turbo
mode is disabled.
29
Programmable TDP Limit for Turbo Mode (R/O)
Package
When set to 1, indicates that TDP Limit for Turbo mode is
programmable. When set to 0, indicates TDP Limit for Turbo mode is
not programmable.
39:30
Reserved.
47:40
Maximum Efficiency Ratio (R/O)
Package
This is the minimum ratio (maximum efficiency) that the processor can
operate, in units of 100MHz.
63:48
Reserved.
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