Intel 64 and IA-32 Architectures. Software Developer’s Manual (2026)

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors,

1st-5th Generation Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors,

8th Generation Intel® Core™ i3 Processors, Intel® Xeon® E Processors, Intel® Xeon® 6 E-Core Processors,

Intel® Xeon® 6 P-Core Processors, and Intel® Series 2 Core™ Ultra Processors (Contd.)

Bit Description

Scope

Platform Clamping Limitation #1

When set, allows the processor to go below the OS requested P states in

order to maintain the power below specified Platform Power Limit #1

value.

This bit is writeable only when CPUID.06H:EAX[4] is set.

23:17

Time Window for Platform Power Limit #1

Specifies the duration of the time window over which Platform Power

Limit 1 value should be maintained for sustained long duration. This field is

made up of two numbers from the following equation:

Time Window = (float) ((1+(X/4))*(2^Y)), where:

X = POWER_LIMIT_1_TIME[23:22]

Y = POWER_LIMIT_1_TIME[21:17]

The maximum allowed value in this field is defined in

MSR_PKG_POWER_INFO[PKG_MAX_WIN].

The default value is 0DH, and the unit is specified in

MSR_RAPL_POWER_UNIT[Time Unit].

31:24

Reserved.

46:32

Platform Power Limit #2

Average Power limit value which the platform must not exceed over the

Short Duration time window chosen by the processor.

The recommended default value is 1.25 times the Long Duration Power

Limit (i.e., Platform Power Limit # 1).

Enable Platform Power Limit #2

When set, enables the processor to apply control policy such that the

platform power does not exceed Platform Power limit #2 over the Short

Duration time window.

Platform Clamping Limitation #2

When set, allows the processor to go below the OS requested P states in

order to maintain the power below specified Platform Power Limit #2

value.

62:49

Reserved.

Lock. Setting this bit will lock all other bits of this MSR until system RESET.

MSR_LASTBRANCH_16_FROM_IP

Last Branch Record 16 From IP (R/W)

Thread

One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains

pointers to the source instruction. See also:

• Last Branch Record Stack TOS at 1C9H.

• Section 20.12.

MSR_LASTBRANCH_17_FROM_IP

Last Branch Record 17 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_18_FROM_IP

2-372 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors,

1st-5th Generation Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors,

8th Generation Intel® Core™ i3 Processors, Intel® Xeon® E Processors, Intel® Xeon® 6 E-Core Processors,

Intel® Xeon® 6 P-Core Processors, and Intel® Series 2 Core™ Ultra Processors (Contd.)

Bit Description

Scope

Last Branch Record 18 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_19_FROM_IP

Last Branch Record 19From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_20_FROM_IP

Last Branch Record 20 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_21_FROM_IP

Last Branch Record 21 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_22_FROM_IP

Last Branch Record 22 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_23_FROM_IP

Last Branch Record 23 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_24_FROM_IP

Last Branch Record 24 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_25_FROM_IP

Last Branch Record 25 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_26_FROM_IP

Last Branch Record 26 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_27_FROM_IP

Last Branch Record 27 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_28_FROM_IP

Last Branch Record 28 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_29_FROM_IP

Last Branch Record 29 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_30_FROM_IP

Vol. 4

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors,

1st-5th Generation Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors,

8th Generation Intel® Core™ i3 Processors, Intel® Xeon® E Processors, Intel® Xeon® 6 E-Core Processors,

Intel® Xeon® 6 P-Core Processors, and Intel® Series 2 Core™ Ultra Processors (Contd.)

Bit Description

Scope

Last Branch Record 30 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_31_FROM_IP

Last Branch Record 31 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_GRAPHICS_PERF_LIMIT_REASONS

Indicator of Frequency Clipping in the Processor Graphics (R/W)

Package

(Frequency refers to processor graphics frequency.)

PROCHOT Status (R0)

When set, frequency is reduced due to assertion of external PROCHOT.

Thermal Status (R0)

When set, frequency is reduced due to a thermal event.

4:2

Reserved.

Running Average Thermal Limit Status (R0)

When set, frequency is reduced due to running average thermal limit.

VR Therm Alert Status (R0)

When set, frequency is reduced due to a thermal alert from a processor

Voltage Regulator.

VR Thermal Design Current Status (R0)

When set, frequency is reduced due to VR TDC limit.

Other Status (R0)

When set, frequency is reduced due to electrical or other constraints.

Reserved.

Package/Platform-Level Power Limiting PL1 Status (R0)

When set, frequency is reduced due to package/platform-level power

limiting PL1.

Package/Platform-Level PL2 Power Limiting Status (R0)

When set, frequency is reduced due to package/platform-level power

limiting PL2/PL3.

Inefficient Operation Status (R0)

When set, processor graphics frequency is operating below target

frequency.

15:13

Reserved.

PROCHOT Log

When set, indicates that the PROCHOT Status bit has asserted since the

log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

2-374 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors,

1st-5th Generation Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors,

8th Generation Intel® Core™ i3 Processors, Intel® Xeon® E Processors, Intel® Xeon® 6 E-Core Processors,

Intel® Xeon® 6 P-Core Processors, and Intel® Series 2 Core™ Ultra Processors (Contd.)

Bit Description

Scope

Thermal Log

When set, indicates that the Thermal Status bit has asserted since the log

bit was last cleared.

This log bit will remain set until cleared by software writing 0.

20:18

Reserved.

Running Average Thermal Limit Log

When set, indicates that the RATL Status bit has asserted since the log bit

was last cleared.

This log bit will remain set until cleared by software writing 0.

VR Therm Alert Log

When set, indicates that the VR Therm Alert Status bit has asserted since

the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

VR Thermal Design Current Log

When set, indicates that the VR Therm Alert Status bit has asserted since

the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Other Log

When set, indicates that the OTHER Status bit has asserted since the log

bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Reserved.

Package/Platform-Level PL1 Power Limiting Log

When set, indicates that the Package/Platform Level PL1 Power Limiting

Status bit has asserted since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Package/Platform-Level PL2 Power Limiting Log

When set, indicates that the Package/Platform Level PL2 Power Limiting

Status bit has asserted since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Inefficient Operation Log

When set, indicates that the Inefficient Operation Status bit has asserted

since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

63:29

Reserved.

MSR_RING_PERF_LIMIT_REASONS

Indicator of Frequency Clipping in the Ring Interconnect (R/W)

Package

(Frequency refers to ring interconnect in the uncore.)

PROCHOT Status (R0)

When set, frequency is reduced due to assertion of external PROCHOT.

Vol. 4

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors,

1st-5th Generation Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors,

8th Generation Intel® Core™ i3 Processors, Intel® Xeon® E Processors, Intel® Xeon® 6 E-Core Processors,

Intel® Xeon® 6 P-Core Processors, and Intel® Series 2 Core™ Ultra Processors (Contd.)

Bit Description

Scope

Thermal Status (R0)

When set, frequency is reduced due to a thermal event.

4:2

Reserved.

Running Average Thermal Limit Status (R0)

When set, frequency is reduced due to running average thermal limit.

VR Therm Alert Status (R0)

When set, frequency is reduced due to a thermal alert from a processor

Voltage Regulator.

VR Thermal Design Current Status (R0)

When set, frequency is reduced due to VR TDC limit.

Other Status (R0)

When set, frequency is reduced due to electrical or other constraints.

Reserved.

Package/Platform-Level Power Limiting PL1 Status (R0)

When set, frequency is reduced due to package/Platform-level power

limiting PL1.

Package/Platform-Level PL2 Power Limiting Status (R0)

When set, frequency is reduced due to package/Platform-level power

limiting PL2/PL3.

15:12

Reserved

PROCHOT Log

When set, indicates that the PROCHOT Status bit has asserted since the

log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Thermal Log

When set, indicates that the Thermal Status bit has asserted since the log

bit was last cleared.

This log bit will remain set until cleared by software writing 0.

20:18

Reserved.

Running Average Thermal Limit Log

When set, indicates that the RATL Status bit has asserted since the log bit

was last cleared.

This log bit will remain set until cleared by software writing 0.

VR Therm Alert Log

When set, indicates that the VR Therm Alert Status bit has asserted since

the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

2-376 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors,

1st-5th Generation Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors,

8th Generation Intel® Core™ i3 Processors, Intel® Xeon® E Processors, Intel® Xeon® 6 E-Core Processors,

Intel® Xeon® 6 P-Core Processors, and Intel® Series 2 Core™ Ultra Processors (Contd.)

Bit Description

Scope

VR Thermal Design Current Log

When set, indicates that the VR Therm Alert Status bit has asserted since

the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Other Log

When set, indicates that the OTHER Status bit has asserted since the log

bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Reserved.

Package/Platform-Level PL1 Power Limiting Log

When set, indicates that the Package/Platform Level PL1 Power Limiting

Status bit has asserted since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Package/Platform-Level PL2 Power Limiting Log

When set, indicates that the Package/Platform Level PL2 Power Limiting

Status bit has asserted since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

63:28

Reserved.

MSR_LASTBRANCH_16_TO_IP

Last Branch Record 16 To IP (R/W)

Thread

One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains

pointers to the destination instruction. See also:

• Last Branch Record Stack TOS at 1C9H.

• Section 20.12.

MSR_LASTBRANCH_17_TO_IP

Last Branch Record 17 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_18_TO_IP

Last Branch Record 18 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_19_TO_IP

Last Branch Record 19To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_20_TO_IP

Last Branch Record 20 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_21_TO_IP

Last Branch Record 21 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

Vol. 4

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors,

1st-5th Generation Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors,

8th Generation Intel® Core™ i3 Processors, Intel® Xeon® E Processors, Intel® Xeon® 6 E-Core Processors,

Intel® Xeon® 6 P-Core Processors, and Intel® Series 2 Core™ Ultra Processors (Contd.)

Bit Description

Scope

MSR_LASTBRANCH_22_TO_IP

Last Branch Record 22 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_23_TO_IP

Last Branch Record 23 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_24_TO_IP

Last Branch Record 24 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_25_TO_IP

Last Branch Record 25 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_26_TO_IP

Last Branch Record 26 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_27_TO_IP

Last Branch Record 27 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_28_TO_IP

Last Branch Record 28 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_29_TO_IP

Last Branch Record 29 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_30_TO_IP

Last Branch Record 30 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_31_TO_IP

Last Branch Record 31 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

IA32_PM_ENABLE

See Section 17.4.2, “Enabling HWP.”

Package

IA32_HWP_CAPABILITIES

See Section 17.4.3, “HWP Performance Range and Dynamic Capabilities.”

Thread

IA32_HWP_REQUEST_PKG

See Section 17.4.4, “Managing HWP.”

Package

2-378 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors,

1st-5th Generation Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors,

8th Generation Intel® Core™ i3 Processors, Intel® Xeon® E Processors, Intel® Xeon® 6 E-Core Processors,

Intel® Xeon® 6 P-Core Processors, and Intel® Series 2 Core™ Ultra Processors (Contd.)

Bit Description

Scope

IA32_HWP_INTERRUPT

See Section 17.4.6, “HWP Notifications.”

Thread

IA32_HWP_REQUEST

See Section 17.4.4, “Managing HWP.”

Thread

7:0

Minimum Performance (R/W)

15:8

Maximum Performance (R/W)

23:16

Desired Performance (R/W)

31:24

Energy/Performance Preference (R/W)

41:32

Activity Window (R/W)

Package Control (R/W)

63:43

Reserved.

IA32_HWP_STATUS

See Section 17.4.5, “HWP Feedback.”

Thread

IA32_BNDCFGS

See Table 2-2.

Thread

IA32_XSS

See Table 2-2.

Thread

IA32_PKG_HDC_CTL

See Section 17.5.2, “Package level Enabling HDC.”

Package

IA32_PM_CTL1

See Section 17.5.3, “Logical-Processor Level HDC Control.”

Thread

IA32_THREAD_STALL

See Section 17.5.4.1, “IA32_THREAD_STALL.”

Thread

MSR_LBR_INFO_0

Last Branch Record 0 Additional Information (R/W)

Thread

One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag,

TSX-related and elapsed cycle information. See also:

• Last Branch Record Stack TOS at 1C9H.

• Section 20.9.1, “LBR Stack.”

MSR_LBR_INFO_1

Last Branch Record 1 Additional Information (R/W)

Thread

See description of MSR_LBR_INFO_0.

MSR_LBR_INFO_2

Last Branch Record 2 Additional Information (R/W)

Thread

See description of MSR_LBR_INFO_0.

MSR_LBR_INFO_3

Vol. 4

2-379

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors,

1st-5th Generation Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors,

8th Generation Intel® Core™ i3 Processors, Intel® Xeon® E Processors, Intel® Xeon® 6 E-Core Processors,

Intel® Xeon® 6 P-Core Processors, and Intel® Series 2 Core™ Ultra Processors (Contd.)

Bit Description

Scope

Last Branch Record 3 Additional Information (R/W)

Thread

See description of MSR_LBR_INFO_0.

MSR_LBR_INFO_4

Last Branch Record 4 Additional Information (R/W)

Thread

See description of MSR_LBR_INFO_0.

MSR_LBR_INFO_5

Last Branch Record 5 Additional Information (R/W)

Thread

See description of MSR_LBR_INFO_0.

MSR_LBR_INFO_6

Last Branch Record 6 Additional Information (R/W)

Thread

See description of MSR_LBR_INFO_0.

MSR_LBR_INFO_7

Last Branch Record 7 Additional Information (R/W)

Thread

See description of MSR_LBR_INFO_0.

MSR_LBR_INFO_8

Last Branch Record 8 Additional Information (R/W)

Thread

See description of MSR_LBR_INFO_0.

MSR_LBR_INFO_9

Last Branch Record 9 Additional Information (R/W)

Thread

See description of MSR_LBR_INFO_0.

MSR_LBR_INFO_10

Last Branch Record 10 Additional Information (R/W)

Thread

See description of MSR_LBR_INFO_0.

MSR_LBR_INFO_11

Last Branch Record 11 Additional Information (R/W)

Thread

See description of MSR_LBR_INFO_0.

MSR_LBR_INFO_12

Last Branch Record 12 Additional Information (R/W)

Thread

See description of MSR_LBR_INFO_0.

MSR_LBR_INFO_13

Last Branch Record 13 Additional Information (R/W)

Thread

See description of MSR_LBR_INFO_0.

MSR_LBR_INFO_14

Last Branch Record 14 Additional Information (R/W)

Thread

See description of MSR_LBR_INFO_0.

MSR_LBR_INFO_15

2-380 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors,

1st-5th Generation Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors,

8th Generation Intel® Core™ i3 Processors, Intel® Xeon® E Processors, Intel® Xeon® 6 E-Core Processors,

Intel® Xeon® 6 P-Core Processors, and Intel® Series 2 Core™ Ultra Processors (Contd.)

Bit Description

Scope

Last Branch Record 15 Additional Information (R/W)

Thread

See description of MSR_LBR_INFO_0.

MSR_LBR_INFO_16

Last Branch Record 16 Additional Information (R/W)

Thread

See description of MSR_LBR_INFO_0.

MSR_LBR_INFO_17

Last Branch Record 17 Additional Information (R/W)

Thread

See description of MSR_LBR_INFO_0.

MSR_LBR_INFO_18

Last Branch Record 18 Additional Information (R/W)

Thread

See description of MSR_LBR_INFO_0.

MSR_LBR_INFO_19

Last Branch Record 19 Additional Information (R/W)

Thread

See description of MSR_LBR_INFO_0.

MSR_LBR_INFO_20

Last Branch Record 20 Additional Information (R/W)

Thread

See description of MSR_LBR_INFO_0.

MSR_LBR_INFO_21

Last Branch Record 21 Additional Information (R/W)

Thread

See description of MSR_LBR_INFO_0.

MSR_LBR_INFO_22

Last Branch Record 22 Additional Information (R/W)

Thread

See description of MSR_LBR_INFO_0.

MSR_LBR_INFO_23

Last Branch Record 23 Additional Information (R/W)

Thread

See description of MSR_LBR_INFO_0.

MSR_LBR_INFO_24

Last Branch Record 24 Additional Information (R/W)

Thread

See description of MSR_LBR_INFO_0.

MSR_LBR_INFO_25

Last Branch Record 25 Additional Information (R/W)

Thread

See description of MSR_LBR_INFO_0.

MSR_LBR_INFO_26

Last Branch Record 26 Additional Information (R/W)

Thread

See description of MSR_LBR_INFO_0.

MSR_LBR_INFO_27

Vol. 4

2-381

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors,

1st-5th Generation Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors,

8th Generation Intel® Core™ i3 Processors, Intel® Xeon® E Processors, Intel® Xeon® 6 E-Core Processors,

Intel® Xeon® 6 P-Core Processors, and Intel® Series 2 Core™ Ultra Processors (Contd.)

Bit Description

Scope

Last Branch Record 27 Additional Information (R/W)

Thread

See description of MSR_LBR_INFO_0.

MSR_LBR_INFO_28

Last Branch Record 28 Additional Information (R/W)

Thread

See description of MSR_LBR_INFO_0.

MSR_LBR_INFO_29

Last Branch Record 29 Additional Information (R/W)

Thread

See description of MSR_LBR_INFO_0.

MSR_LBR_INFO_30

Last Branch Record 30 Additional Information (R/W)

Thread

See description of MSR_LBR_INFO_0.

MSR_LBR_INFO_31

Last Branch Record 31 Additional Information (R/W)

Thread

See description of MSR_LBR_INFO_0.

Table 2-40 lists the MSRs of uncore PMU for Intel processors with a CPUID Signature DisplayFamily_DisplayModel

value of 06_4EH, 06_5EH, 06_8EH, 06_9EH, or 06_66H.

Table 2-40. Uncore PMU MSRs Supported by 6th Generation, 7th Generation, and 8th Generation Intel® Core™

Processors, and 8th generation Intel® Core™ i3 Processors

Bit Description

Scope

MSR_UNC_PERF_FIXED_CTRL

Uncore Fixed Counter Control (R/W)

Package

19:0

Reserved.

Enable overflow propagation.

Reserved.

Enable counting.

63:23

Reserved.

MSR_UNC_PERF_FIXED_CTR

Uncore Fixed Counter

Package

43:0

Current count.

63:44

Reserved.

MSR_UNC_CBO_CONFIG

Uncore C-Box Configuration Information (R/O)

Package

3:0

Specifies the number of C-Box units with programmable counters

(including processor cores and processor graphics).

63:4

Reserved.

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-40. Uncore PMU MSRs Supported by 6th Generation, 7th Generation, and 8th Generation Intel® Core™

Processors, and 8th generation Intel® Core™ i3 Processors

Bit Description

Scope

MSR_UNC_ARB_PERFCTR0

Uncore Arb Unit, Performance Counter 0

Package

MSR_UNC_ARB_PERFCTR1

Uncore Arb Unit, Performance Counter 1

Package

MSR_UNC_ARB_PERFEVTSEL0

Uncore Arb Unit, Counter 0 Event Select MSR

Package

MSR_UNC_ARB_PERFEVTSEL1

Uncore Arb Unit, Counter 1 Event Select MSR

Package

MSR_UNC_CBO_0_PERFEVTSEL0

Uncore C-Box 0, Counter 0 Event Select MSR

Package

MSR_UNC_CBO_0_PERFEVTSEL1

Uncore C-Box 0, Counter 1 Event Select MSR

Package

MSR_UNC_CBO_0_PERFCTR0

Uncore C-Box 0, Performance Counter 0

Package

MSR_UNC_CBO_0_PERFCTR1

Uncore C-Box 0, Performance Counter 1

Package

MSR_UNC_CBO_1_PERFEVTSEL0

Uncore C-Box 1, Counter 0 Event Select MSR

Package

MSR_UNC_CBO_1_PERFEVTSEL1

Uncore C-Box 1, Counter 1 Event Select MSR

Package

MSR_UNC_CBO_1_PERFCTR0

Uncore C-Box 1, Performance Counter 0

Package

MSR_UNC_CBO_1_PERFCTR1

Uncore C-Box 1, Performance Counter 1

Package

MSR_UNC_CBO_2_PERFEVTSEL0

Uncore C-Box 2, Counter 0 Event Select MSR

Package

MSR_UNC_CBO_2_PERFEVTSEL1

Uncore C-Box 2, Counter 1 Event Select MSR

Package

MSR_UNC_CBO_2_PERFCTR0

Uncore C-Box 2, Performance Counter 0

Package

MSR_UNC_CBO_2_PERFCTR1

Uncore C-Box 2, Performance Counter 1

Package

MSR_UNC_CBO_3_PERFEVTSEL0

Uncore C-Box 3, Counter 0 Event Select MSR

Package

MSR_UNC_CBO_3_PERFEVTSEL1

Uncore C-Box 3, Counter 1 Event Select MSR

Package

MSR_UNC_CBO_3_PERFCTR0

Vol. 4

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-40. Uncore PMU MSRs Supported by 6th Generation, 7th Generation, and 8th Generation Intel® Core™

Processors, and 8th generation Intel® Core™ i3 Processors

Bit Description

Scope

Uncore C-Box 3, Performance Counter 0

Package

MSR_UNC_CBO_3_PERFCTR1

Uncore C-Box 3, Performance Counter 1

Package

MSR_UNC_PERF_GLOBAL_CTRL

Uncore PMU Global Control

Package

Slice 0 select.

Slice 1 select.

Slice 2 select.

Slice 3 select.

Slice 4select.

18:5

Reserved.

Enable all uncore counters.

Enable wake on PMI.

Enable Freezing counter when overflow.

63:32

Reserved.

MSR_UNC_PERF_GLOBAL_STATUS

Uncore PMU Main Status

Package

Fixed counter overflowed.

An ARB counter overflowed.

Reserved.

A CBox counter overflowed (on any slice).

63:4

Reserved.

2.17.1 MSRs Introduced in 7th Generation and 8th Generation Intel® Core™ Processors Based

on Kaby Lake Microarchitecture and Coffee Lake Microarchitecture

Table 2-41 lists additional MSRs for 7th generation and 8th generation Intel Core processors with a CPUID Signa-

ture DisplayFamily_DisplayModel value of 06_8EH or 06_9EH. For an MSR listed in Table 2-41 that also appears in

the model-specific tables of prior generations, Table 2-41 supersedes prior generation tables.

Table 2-41. Additional MSRs Supported by the 7th Generation and 8th Generation Intel® Core™ Processors Based

on Kaby Lake Microarchitecture and Coffee Lake Microarchitecture

Bit Description

Scope

MSR_TRACE_HUB_STH_ACPIBAR_BASE

NPK Address Used by AET Messages (R/W)

Package

Lock Bit

If set, this MSR cannot be re-written anymore. Lock bit has to be set in

order for the AET packets to be directed to NPK MMIO.

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-41. Additional MSRs Supported by the 7th Generation and 8th Generation Intel® Core™ Processors Based

on Kaby Lake Microarchitecture and Coffee Lake Microarchitecture (Contd.)

Bit Description

Scope

17:1

Reserved.

63:18

ACPIBAR_BASE_ADDRESS

AET target address in NPK MMIO space.

MSR_PRMRR_PHYS_BASE

Processor Reserved Memory Range Register - Physical Base Control Register (R/W)

Core

2:0

MemType

PRMRR BASE MemType.

11:3

Reserved.

45:12

Base

PRMRR Base Address.

63:46

Reserved.

MSR_PRMRR_PHYS_MASK

Processor Reserved Memory Range Register - Physical Mask Control Register (R/W)

Core

9:0

Reserved.

Lock

Lock bit for the PRMRR.

VLD

Enable bit for the PRMRR.

45:12

Mask

PRMRR MASK bits.

63:46

Reserved.

MSR_PRMRR_VALID_CONFIG

Valid PRMRR Configurations (R/W)

Core

1M supported MEE size.

4:1

Reserved.

32M supported MEE size.

64M supported MEE size.

128M supported MEE size.

31:8

Reserved.

MSR_UNCORE_PRMRR_PHYS_BASE¹

(R/W)

Package

The PRMRR range is used to protect the processor reserved memory from unauthorized reads and writes. Any IO

access to this range is aborted. This register controls the location of the PRMRR range by indicating its starting

address. It functions in tandem with the PRMRR mask register.

11:0

Reserved.

PAWIDTH-1:12

Range Base

This field corresponds to bits PAWIDTH-1:12 of the base address memory

range which is allocated to PRMRR memory.

63:PAWIDTH

Reserved.

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Table 2-41. Additional MSRs Supported by the 7th Generation and 8th Generation Intel® Core™ Processors Based

on Kaby Lake Microarchitecture and Coffee Lake Microarchitecture (Contd.)

Bit Description

Scope

MSR_UNCORE_PRMRR_PHYS_MASK¹

(R/W)

Package

This register controls the size of the PRMRR range by indicating which address bits must match the PRMRR base

9:0

Reserved.

Lock

Setting this bit locks all writeable settings in this register, including itself.

Range_En

Indicates whether the PRMRR range is enabled and valid.

38:12

Range_Mask

This field indicates which address bits must match PRMRR base in order

to qualify as an PRMRR access.

63:39

Reserved.

MSR_RING_RATIO_LIMIT

Ring Ratio Limit (R/W)

Package

This register provides Min/Max Ratio Limits for the LLC and Ring.

6:0

MAX_Ratio

This field is used to limit the max ratio of the LLC/Ring.

Reserved.

14:8

MIN_Ratio

Writing to this field controls the minimum possible ratio of the LLC/Ring.

63:15

Reserved.

NOTES:

1. This MSR is specific to 7th generation and 8th generation Intel® Core™ processors.

2.17.2 MSRs Specific to 8th Generation Intel® Core™ i3 Processors

Table 2-42 lists additional MSRs for 8th generation Intel Core i3 processors with a CPUID Signature

DisplayFamily_DisplayModel value of 06_66H. For an MSR listed in Table 2-42 that also appears in the model-

specific tables of prior generations, Table 2-42 supersedes prior generation tables.

Table 2-42. Additional MSRs Supported by the 8th Generation Intel® Core™ i3 Processors

Based on Cannon Lake Microarchitecture

Bit Description

Scope

IA32_FEATURE_CONTROL

Control Features in Intel 64 Processor (R/W)

Thread

See Table 2-2.

Lock (R/WL)

Enable VMX Inside SMX Operation (R/WL)

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-42. Additional MSRs Supported by the 8th Generation Intel® Core™ i3 Processors

Based on Cannon Lake Microarchitecture (Contd.)

Bit Description

Scope

Enable VMX Outside SMX Operation (R/WL)

14:8

SENTER Local Functions Enables (R/WL)

SENTER Global Functions Enable (R/WL)

SGX Launch Control Enable (R/WL)

This bit must be set to enable runtime reconfiguration of SGX Launch

Control via IA32_SGXLEPUBKEYHASHn MSR.

Available only if CPUID.07H.00H:ECX[30] = 1.

SGX Global Functions Enable (R/WL)

63:21

Reserved.

MSR_BR_DETECT_CTRL

Branch Monitoring Global Control (R/W)

EnMonitoring

Global enable for branch monitoring.

EnExcept

Enable branch monitoring event signaling on threshold trip.

The branch monitoring event handler is signaled via the existing PMI

signaling mechanism as programmed from the corresponding local APIC

LVT entry.

EnLBRFrz

Enable LBR freeze on threshold trip. This will cause the LBR frozen bit

58 to be set in IA32_PERF_GLOBAL_STATUS when a triggering

condition occurs and this bit is enabled.

DisableInGuest

When set to ‘1’, branch monitoring, event triggering and LBR freeze

actions are disabled when operating at VMX non-root operation.

7:4

Reserved.

17:8

WindowSize

Window size defined by WindowCntSel. Values 0 - 1023 are supported.

Once the Window counter reaches the WindowSize count both the

Window Counter and all Branch Monitoring Counters are cleared.

23:18

Reserved.

25:24

WindowCntSel

Window event count select:

‘00 = Instructions retired.

‘01 = Branch instructions retired

‘10 = Return instructions retired.

‘11 = Indirect branch instructions retired.

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-42. Additional MSRs Supported by the 8th Generation Intel® Core™ i3 Processors

Based on Cannon Lake Microarchitecture (Contd.)

Bit Description

Scope

CntAndMode

When set to ‘1’, the overall branch monitoring event triggering

condition is true only if all enabled counters’ threshold conditions are

true.

When ‘0’, the threshold tripping condition is true if any enabled

counters’ threshold is true.

63:27

Reserved.

MSR_BR_DETECT_STATUS

Branch Monitoring Global Status (R/W)

Branch Monitoring Event Signaled

When set to '1', Branch Monitoring event signaling is blocked until this

bit is cleared by software.

LBRsValid

This status bit is set to ‘1’ if the LBR state is considered valid for

sampling by branch monitoring software.

7:2

Reserved.

CntrHit0

Branch monitoring counter #0 threshold hit. This status bit is sticky

and once set requires clearing by software. Counter operation

continues independent of the state of the bit.

CntrHit1

Branch monitoring counter #1 threshold hit. This status bit is sticky

and once set requires clearing by software. Counter operation

continues independent of the state of the bit.

15:10

Reserved.

Reserved for additional branch monitoring counters threshold hit

status.

25:16

CountWindow

The current value of the window counter. The count value is frozen on

a valid branch monitoring triggering condition. This is a 10-bit unsigned

value.

31:26

Reserved.

Reserved for future extension of CountWindow.

39:32

Count0

The current value of counter 0 updated after each occurrence of the

event being counted. The count value is frozen on a valid branch

monitoring triggering condition (in which case CntrHit0 will also be set).

This is an 8-bit signed value (2’s complement).

Heuristic events which only increment will saturate and freeze at

maximum value 0xFF (256).

RET-CALL event counter saturate at maximum value 0x7F (+127) and

minimum value 0x80 (-128).

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-42. Additional MSRs Supported by the 8th Generation Intel® Core™ i3 Processors

Based on Cannon Lake Microarchitecture (Contd.)

Bit Description

Scope

47:40

Count1

The current value of counter 1 updated after each occurrence of the

event being counted. The count value is frozen on a valid branch

monitoring triggering condition (in which case CntrHit1 will also be set).

This is an 8-bit signed value (2’s complement).

Heuristic events which only increment will saturate and freeze at

maximum value 0xFF (256).

RET-CALL event counter saturate at maximum value 0x7F (+127) and

minimum value 0x80 (-128).

63:48

Reserved.

MSR_BR_DETECT_COUNTER_CONFIG_i

Branch Monitoring Detect Counter Configuration (R/W)

CntrEn

Enable counter.

7:1

CntrEvSel

Event select (other values #GP)

‘0000000 = RETs.

‘0000001 = RET-CALL bias.

‘0000010 = RET mispredicts.

‘0000011 = Branch (all) mispredicts.

‘0000100 = Indirect branch mispredicts.

‘0000101 = Far branch instructions.

14:8

CntrThreshold

Threshold (an unsigned value of 0 to 127 supported). The value 0 of

counter threshold will result in event signaled after every instruction.

#GP if threshold is < 2.

MispredEventCnt

Mispredict events counting behavior:

‘0 = Mispredict events are counted in a window.

‘1 = Mispredict events are counted based on a consecutive occurrence.

CntrThreshold is treated as # of consecutive mispredicts. This control

bit only applies to events specified by CntrEvSel that involve a

prediction (0000010, 0000011, 0000100). Setting this bit for other

events is ignored.

63:16

Reserved.

MSR_PKG_C3_RESIDENCY

Package C3 Residency Counter (R/O)

Package

63:0

Note: C-state values are processor specific C-state code names,

unrelated to MWAIT extension C-state parameters or ACPI C-states.

MSR_RING_RATIO_LIMIT

Ring Ratio Limit (R/W)

Package

This register provides Min/Max Ratio Limits for the LLC and Ring.

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-42. Additional MSRs Supported by the 8th Generation Intel® Core™ i3 Processors

Based on Cannon Lake Microarchitecture (Contd.)

Bit Description

Scope

6:0

MAX_Ratio

This field is used to limit the max ratio of the LLC/Ring.

Reserved.

14:8

MIN_Ratio

Writing to this field controls the minimum possible ratio of the

LLC/Ring.

63:15

Reserved.

MSR_CORE_C1_RESIDENCY

Core C1 Residency Counter (R/O)

Core

63:0

Value since last reset for the Core C1 residency. Counter rate is the

Max Non-Turbo frequency (same as TSC). This counter counts in case

both of the core's threads are in an idle state and at least one of the

core's thread residency is in a C1 state or in one of its sub states. The

counter is updated only after a core C state exit. Note: Always reads 0

if core C1 is unsupported. A value of zero indicates that this processor

does not support core C1 or never entered core C1 level state.

MSR_CORE_C3_RESIDENCY

Core C3 Residency Counter (R/O)

Core

63:0

Will always return 0.

Table 2-43 lists the MSRs of uncore PMU for Intel processors with a CPUID Signature DisplayFamily_DisplayModel

value of 06_66H.

Table 2-43. Uncore PMU MSRs Supported by Intel® Core™ Processors Based on Cannon Lake Microarchitecture

Bit Description

Scope

MSR_UNC_PERF_FIXED_CTRL

Uncore Fixed Counter Control (R/W)

Package

19:0

Reserved.

Enable overflow propagation.

Reserved

Enable counting.

63:23

Reserved.

MSR_UNC_PERF_FIXED_CTR

Uncore Fixed Counter

Package

47:0

Current count.

63:48

Reserved.

MSR_UNC_CBO_CONFIG

Uncore C-Box Configuration Information (R/O)

Package

3:0

Report the number of C-Box units with performance counters, including

processor cores and processor graphics.

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-43. Uncore PMU MSRs Supported by Intel® Core™ Processors Based on Cannon Lake Microarchitecture

Bit Description

Scope

63:4

Reserved.

MSR_UNC_ARB_PERFCTR0

Uncore Arb Unit, Performance Counter 0

Package

MSR_UNC_ARB_PERFCTR1

Uncore Arb Unit, Performance Counter 1

Package

MSR_UNC_ARB_PERFEVTSEL0

Uncore Arb Unit, Counter 0 Event Select MSR

Package

MSR_UNC_ARB_PERFEVTSEL1

Uncore Arb unit, Counter 1 Event Select MSR

Package

MSR_UNC_CBO_0_PERFEVTSEL0

Uncore C-Box 0, Counter 0 Event Select MSR

Package

MSR_UNC_CBO_0_PERFEVTSEL1

Uncore C-Box 0, Counter 1 Event Select MSR

Package

MSR_UNC_CBO_0_PERFCTR0

Uncore C-Box 0, Performance Counter 0

Package

MSR_UNC_CBO_0_PERFCTR1

Uncore C-Box 0, Performance Counter 1

Package

MSR_UNC_CBO_1_PERFEVTSEL0

Uncore C-Box 1, Counter 0 Event Select MSR

Package

MSR_UNC_CBO_1_PERFEVTSEL1

Uncore C-Box 1, Counter 1 Event Select MSR

Package

MSR_UNC_CBO_1_PERFCTR0

Uncore C-Box 1, Performance Counter 0

Package

MSR_UNC_CBO_1_PERFCTR1

Uncore C-Box 1, Performance Counter 1

Package

MSR_UNC_CBO_2_PERFEVTSEL0

Uncore C-Box 2, Counter 0 Event Select MSR

Package

MSR_UNC_CBO_2_PERFEVTSEL1

Uncore C-Box 2, Counter 1 Event Select MSR

Package

MSR_UNC_CBO_2_PERFCTR0

Uncore C-Box 2, Performance Counter 0

Package

MSR_UNC_CBO_2_PERFCTR1

Uncore C-Box 2, Performance Counter 1

Package

MSR_UNC_CBO_3_PERFEVTSEL0

Uncore C-Box 3, Counter 0 Event Select MSR

Package

MSR_UNC_CBO_3_PERFEVTSEL1

Uncore C-Box 3, Counter 1 Event Select MSR

Package

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-43. Uncore PMU MSRs Supported by Intel® Core™ Processors Based on Cannon Lake Microarchitecture

Bit Description

Scope

MSR_UNC_CBO_3_PERFCTR0

Uncore C-Box 3, Performance Counter 0

Package

MSR_UNC_CBO_3_PERFCTR1

Uncore C-Box 3, Performance Counter 1

Package

MSR_UNC_CBO_4_PERFEVTSEL0

Uncore C-Box 4, Counter 0 Event Select MSR

Package

MSR_UNC_CBO_4_PERFEVTSEL1

Uncore C-Box 4, Counter 1 Event Select MSR

Package

MSR_UNC_CBO_4_PERFCTR0

Uncore C-Box 4, Performance Counter 0

Package

MSR_UNC_CBO_4_PERFCTR1

Uncore C-Box 4, Performance Counter 1

Package

MSR_UNC_CBO_5_PERFEVTSEL0

Uncore C-Box 5, Counter 0 Event Select MSR

Package

MSR_UNC_CBO_5_PERFEVTSEL1

Uncore C-Box 5, Counter 1 Event Select MSR

Package

MSR_UNC_CBO_5_PERFCTR0

Uncore C-Box 5, Performance Counter 0

Package

MSR_UNC_CBO_5_PERFCTR1

Uncore C-Box 5, Performance Counter 1

Package

MSR_UNC_CBO_6_PERFEVTSEL0

Uncore C-Box 6, Counter 0 Event Select MSR

Package

MSR_UNC_CBO_6_PERFEVTSEL1

Uncore C-Box 6, Counter 1 Event Select MSR

Package

MSR_UNC_CBO_6_PERFCTR0

Uncore C-Box 6, Performance Counter 0

Package

MSR_UNC_CBO_6_PERFCTR1

Uncore C-Box 6, Performance Counter 1

Package

MSR_UNC_CBO_7_PERFEVTSEL0

Uncore C-Box 7, Counter 0 Event Select MSR

Package

MSR_UNC_CBO_7_PERFEVTSEL1

Uncore C-Box 7, Counter 1 Event Select MSR

Package

MSR_UNC_CBO_7_PERFCTR0

Uncore C-Box 7, Performance Counter 0

Package

MSR_UNC_CBO_7_PERFCTR1

Uncore C-Box 7, Performance Counter 1

Package

MSR_UNC_PERF_GLOBAL_CTRL

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Table 2-43. Uncore PMU MSRs Supported by Intel® Core™ Processors Based on Cannon Lake Microarchitecture

Bit Description

Scope

Uncore PMU Global Control

Package

Slice 0 select.

Slice 1 select.

Slice 2 select.

Slice 3 select.

Slice 4select.

18:5

Reserved.

Enable all uncore counters.

Enable wake on PMI.

Enable Freezing counter when overflow.

63:32

Reserved.

MSR_UNC_PERF_GLOBAL_STATUS

Uncore PMU Main Status

Package

Fixed counter overflowed.

An ARB counter overflowed.

Reserved.

A CBox counter overflowed (on any slice).

63:4

Reserved.

2.17.3 MSRs Introduced in 10th Generation Intel® Core™ Processors

Table 2-44 lists additional MSRs for 10th generation Intel Core processors with a CPUID Signature

DisplayFamily_DisplayModel value of 06_7EH. For an MSR listed in Table 2-44 that also appears in the model-

specific tables of prior generations, Table 2-44 supersedes prior generation tables.

Table 2-44. MSRs Supported by the 10th Generation Intel® Core™ Processors (Ice Lake Microarchitecture)

Bit Description

Scope

MSR_MEMORY_CTRL

Memory Control Register

Core

28:0

Reserved.

SPLIT_LOCK_DISABLE

If set to 1, a split lock will cause an #AC(0) exception.

See Section 11.1.2.3, “Features to Disable Bus Locks.”

Reserved.

IA32_SPEC_CTRL

See Table 2-2.

Core

IA32_PREDICT_CMD

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Table 2-44. MSRs Supported by the 10th Generation Intel® Core™ Processors (Ice Lake Microarchitecture) (Contd.)

Bit Description

Scope

See Table 2-2.

Thread

IA32_SGXLEPUBKEYHASH0

See Table 2-2.

Thread

IA32_SGXLEPUBKEYHASH1

See Table 2-2.

Thread

IA32_SGXLEPUBKEYHASH2

See Table 2-2.

Thread

IA32_SGXLEPUBKEYHASH3

See Table 2-2.

Thread

MSR_BIOS_MCU_ERRORCODE

BIOS MCU ERRORCODE (R/O)

Package

This MSR indicates if WRMSR 0x79 failed to configure PRM memory and gives a hint to debug BIOS.

15:0

Error Codes (R/O)

Package

30:16

Reserved.

MCU Partial Success (R/O)

Thread

When set to 1, WRMSR 0x79 skipped part of the functionality during

BIOS.

MSR_FIT_BIOS_ERROR

FIT BIOS ERROR (R/W)

Thread

Report error codes for debug in case the processor failed to parse the Firmware Table in BIOS.

Can also be used to log BIOS information.

7:0

Error Codes (R/W)

Error codes for debug.

15:8

Entry Type (R/W)

Failed FIT entry type.

FIT MCU Entry (R/W)

FIT contains MCU entry.

62:17

Reserved.

LOCK (R/W)

When set to 1, writes to this MSR will be skipped.

IA32_FLUSH_CMD

See Table 2-2.

Thread

MSR_BIOS_DONE

BIOS Done (R/WO)

Thread

BIOS Done Indication (R/WO)

Thread

Set by BIOS when it finishes programming the processor and wants to

lock the memory configuration from changes by software that is running

on this thread.

Writes to the bit will be ignored if EAX[0] is 0.

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-44. MSRs Supported by the 10th Generation Intel® Core™ Processors (Ice Lake Microarchitecture) (Contd.)

Bit Description

Scope

Package BIOS Done Indication (R/O)

Package

When set to 1, all threads in the package have bit 0 of this MSR set.

31:2

Reserved.

MSR_CRASHLOG_CONTROL

Write Data to a Crash Log Configuration

Thread

CDDIS: CrashDump_Disable

If set, indicates that Crash Dump is disabled.

63:1

Reserved.

MSR_PRMRR_BASE_0

Processor Reserved Memory Range Register - Physical Base Control Register (R/W)

Core

2:0

MEMTYPE: PRMRR BASE Memory Type.

CONFIGURED: PRMRR BASE Configured.

11:4

Reserved.

51:12

BASE: PRMRR Base Address.

63:52

Reserved.

IA32_FIXED_CTR3

Fixed-Function Performance Counter Register 3 (R/W)

Thread

Bit definitions are the same as found in IA32_FIXED_CTR0, offset 309H. See Table 2-2.

MSR_PERF_METRICS

Performance Metrics (R/W)

Thread

Reports metrics directly. Software can check (and/or expose to its guests) the availability of PERF_METRICS feature

using IA32_PERF_CAPABILITIES.PERF_METRICS_AVAILABLE (bit 15).

7:0

Retiring. Percent of utilized slots by uops that eventually retire (commit).

15:8

Bad Speculation. Percent of wasted slots due to incorrect speculation,

covering utilized by uops that do not retire, or recovery bubbles

(unutilized slots).

23:16

Frontend Bound. Percent of unutilized slots where front-end did not

deliver a uop while back-end is ready.

31:24

Backend Bound. Percent of unutilized slots where a uop was not delivered

to back-end due to lack of back-end resources.

63:32

Reserved.

MSR_PEBS_DATA_CFG

PEBS Data Configuration (R/W)

Thread

Provides software the capability to select data groups of interest and thus reduce the record size in memory and

record generation latency. Hence, a PEBS record's size and layout vary based on the selected groups. The MSR also

allows software to select LBR depth for branch data records.

Memory Info.

Setting this bit will capture memory information such as the linear

address, data source and latency of the memory access in the PEBS

record.

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Table 2-44. MSRs Supported by the 10th Generation Intel® Core™ Processors (Ice Lake Microarchitecture) (Contd.)

Bit Description

Scope

GPRs.

Setting this bit will capture the contents of the General Purpose registers

in the PEBS record.

XMMs.

Setting this bit will capture the contents of the XMM registers in the PEBS

record.

LBRs.

Setting this bit will capture LBR TO, FROM, and INFO in the PEBS record.

23:4

Reserved.

31:24

LBR Entries.

Set the field to the desired number of entries - 1. For example, if the

LBR_entries field is 0, a single entry will be included in the record. To

include 32 LBR entries, set the LBR_entries field to 31 (0x1F). To ensure

all PEBS records are 16-byte aligned, software can use LBR_entries that

is multiple of 3.

MSR_CORE_UARCH_CTL

Core Microarchitecture Control MSR (R/W)

Core

L1 Scrubbing Enable

When set to 1, enable L1 scrubbing.

31:1

Reserved.

MSR_FAST_UNCORE_MSRS_CTL

Fast WRMSR/RDMSR Control MSR (R/W)

Thread

3:0

FAST_ACCESS_ENABLE:

Bit 0: When set to '1', provides a hint for the hardware to enable fast

access mode for the IA32_HWP_REQUEST MSR.

This bit is sticky and is cleaned by the hardware only during reset time.

This bit is valid only if FAST_UNCORE_MSRS_CAPABILITY[0] is set. Setting

this bit will cause CPUID.06H:EAX[18] to be set.

31:4

Reserved.

MSR_FAST_UNCORE_MSRS_STATUS

Indication of Uncore MSRs, Post Write Activates

Thread

Indicates whether the CPU is still in the middle of writing

IA32_HWP_REQUEST MSR, even after the WRMSR instruction has retired.

A value of 1 indicates the last write of IA32_HWP_REQUEST is still

ongoing.

A value of 0 indicates the last write of IA32_HWP_REQUEST is visible

outside the logical processor.

Software can use the status of this bit to avoid overwriting

IA32_HWP_REQUEST.

31:1

Reserved.

MSR_FAST_UNCORE_MSRS_CAPABILITY

Fast WRMSR/RDMSR Enumeration MSR (R/O)

Thread

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Table 2-44. MSRs Supported by the 10th Generation Intel® Core™ Processors (Ice Lake Microarchitecture) (Contd.)

Bit Description

Scope

3:0

MSRS_CAPABILITY:

Bit 0: If set to ‘1’, hardware supports the fast access mode for the

IA32_HWP_REQUEST MSR.

31:4

Reserved.

IA32_HWP_REQUEST_PKG

See Table 2-2.

Package

IA32_PECI_HWP_REQUEST_INFO

See Table 2-2.

Package

IA32_HWP_STATUS

See Table 2-2.

Thread

2.17.4 MSRs Introduced in the 11th Generation Intel® Core™ Processors based on Tiger Lake

Microarchitecture

Table 2-45 lists additional MSRs for 11th generation Intel Core processors with a CPUID Signature

DisplayFamily_DisplayModel value of 06_8CH or 06_8DH. The MSRs listed in Table 2-44 are also supported by

these processors. For an MSR listed in Table 2-45 that also appears in the model-specific tables of prior genera-

tions, Table 2-45 supersedes prior generation tables.

Table 2-45. Additional MSRs Supported by the 11th Generation Intel® Core™ Processors Based on Tiger Lake

Microarchitecture

Bit Description

Scope

MSR_BIOS_MCU_ERRORCODE

BIOS MCU ERRORCODE (R/O)

Package

15:0

Error Codes

31:16

Reserved.

MSR_BIOS_DEBUG

BIOS DEBUG (R/O)

Thread

This MSR indicates if WRMSR 79H failed to configure PRM memory and gives a hint to debug BIOS.

30:0

Reserved.

MCU Partial Success

When set to 1, WRMSR 79H skipped part of the functionality during

BIOS.

63:32

Reserved.

IA32_CORE_CAPABILITIES

IA32 Core Capabilities Register (R/O)

Package

If CPUID.07H.00H:EDX[30] = 1.

This MSR provides an architectural enumeration function for model-specific behavior.

1:0

Reserved.

FUSA_SUPPORTED

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2-397

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-45. Additional MSRs Supported by the 11th Generation Intel® Core™ Processors Based on Tiger Lake

Microarchitecture (Contd.)

Bit Description

Scope

RSM_IN_CPL0_ONLY

When set to 1, the RSM instruction is only allowed in CPL0 (#GP

triggered in any CPL != 0).

When set to 0, then any CPL may execute the RSM instruction.

Reserved.

SPLIT_LOCK_DISABLE_SUPPORTED

When read as 1, software can set bit 29 of MSR_MEMORY_CTRL

(MSR address 33H).

31:6

Reserved.

IA32_VMX_PROCBASED_CTLS3

Core

This MSR enumerates the allowed 1-settings of the third set of processor-based controls. Specifically, VM entry

allows bit X of the tertiary processor-based VM-execution controls to be 1 if and only if bit X of the MSR is set to 1.

If bit X of the MSR is cleared to 0, VM entry fails if control X and the “activate tertiary controls” primary processor-

based VM-execution control are both 1.

LOADIWKEY

This control determines whether executions of LOADIWKEY cause VM

exits.

63:1

Reserved.

MSR_VR_CURRENT_CONFIG

Power Limit 4 (PL4)

Package

Package-level maximum power limit (in Watts). It is a proactive, instantaneous limit.

12:0

PL4 Value

PL4 value in 0.125 A increments. This field is locked by

VR_CURRENT_CONFIG[LOCK]. When the LOCK bit is set to 1b, this

field becomes Read Only.

30:13

Reserved.

Lock Indication (LOCK)

This bit will lock the CURRENT_LIMIT settings in this register and will

also lock this setting. This means that once set to 1b, the

CURRENT_LIMIT setting and this bit become Read Only until the next

Warm Reset.

62:32

Not in use.

Reserved.

IA32_U_CET

Configure User Mode CET (R/W)

See Table 2-2.

IA32_S_CET

Configure Supervisor Mode CET (R/W)

See Table 2-2.

IA32_PL0_SSP

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-45. Additional MSRs Supported by the 11th Generation Intel® Core™ Processors Based on Tiger Lake

Microarchitecture (Contd.)

Bit Description

Scope

Linear address to be loaded into SSP on transition to privilege level 0. (R/W)

See Table 2-2.

IA32_PL1_SSP

Linear address to be loaded into SSP on transition to privilege level 1. (R/W)

See Table 2-2.

IA32_PL2_SSP

Linear address to be loaded into SSP on transition to privilege level 2. (R/W)

See Table 2-2.

IA32_PL3_SSP

Linear address to be loaded into SSP on transition to privilege level 3. (R/W)

See Table 2-2.

IA32_INTERRUPT_SSP_TABLE_ADDR

Linear address of a table of seven shadow stack pointers that are selected in IA-32e mode using the IST index (when

not 0) from the interrupt gate descriptor. (R/W)

See Table 2-2.

IA32_TME_CAPABILITY

See Table 2-2.

IA32_TME_ACTIVATE

See Table 2-2.

IA32_TME_EXCLUDE_MASK

See Table 2-2.

IA32_TME_EXCLUDE_BASE

See Table 2-2.

IA32_COPY_STATUS¹

See Table 2-2.

Thread

IA32_IWKEYBACKUP_STATUS¹

See Table 2-2.

Platform

IA32_L2_QOS_CFG

IA32_CR_L2_QOS_CFG

Core

This MSR provides software an enumeration of the parameters that L2 QoS (Intel RDT) support in any particular

implementation.

CDP_ENABLE

When set to 1, it will enable the code and data prioritization for the

L2 CAT/Intel RDT feature.

When set to 0, code and data prioritization is disabled for L2 CAT/Intel

RDT. See Chapter 20, “Debug, Branch Profile, TSC, and Intel® Resource

Director Technology (Intel® RDT) Features‚” for further details on CDP.

31:1

Reserved.

IA32_L2_QOS_MASK_[0-7]

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2-399

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-45. Additional MSRs Supported by the 11th Generation Intel® Core™ Processors Based on Tiger Lake

Microarchitecture (Contd.)

Bit Description

Scope

IA32_CR_L2_QOS_MASK_[0-7]

Package

Controls MLC (L2) Intel RDT allocation. For more details on CAT/RDT, see Chapter 20, “Debug, Branch Profile, TSC, and

Intel® Resource Director Technology (Intel® RDT) Features.”

19:0

WAYS_MASK

Setting a 1 in this bit X allows threads with CLOS <n> (where N is [0-

7]) to allocate to way X in the MLC. Ones are only allowed to be

written to ways that physically exist in the MLC

(CPUID.04H.02H:EBX[31:22] will indicate this).

Writing a 1 to a value beyond the highest way or a non-contiguous

set of 1s will cause a #GP on the WRMSR to this MSR.

31:20

Reserved.

IA32_COPY_LOCAL_TO_PLATFORM¹

See Table 2-2.

Thread

IA32_COPY_PLATFORM_TO_LOCAL¹

See Table 2-2.

Thread

NOTES:

1. Further details on Key Locker and usage of this MSR can be found here:

https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html.

2.17.5 MSRs Introduced in the 12th and 13th Generation Intel® Core™ Processors Supporting

Performance Hybrid Architecture

Table 2-46 lists additional MSRs for 12th and 13th generation Intel Core processors with a CPUID Signature

DisplayFamily_DisplayModel value of 06_97H, 06_9AH, 06_BAH, 06_B7H, or 06_BFH. Table 2-47 lists the MSRs

unique to the processor P-core. Table 2-48 lists the MSRs unique to the processor E-core.

The MSRs listed in Table 2-44¹ and Table 2-45 are also supported by these processors. For an MSR listed in Table

2-46, Table 2-47, or Table 2-48 that also appears in the model-specific tables of prior generations, Table 2-46, Table

2-47, and Table 2-48 supersede prior generation tables.

Table 2-46. Additional MSRs Supported by the 12th and 13th Generation Intel® Core™ Processors Supporting

Performance Hybrid Architecture

Bit Description

Scope

MSR_MEMORY_CTRL

Memory Control Register

Core

26:0

Reserved.

UC_STORE_THROTTLE

If set to 1, when enabled, the processor will only allow one in-

progress UC store at a time.

1. MSRs at the following addresses are not supported in the 12th and 13th generation Intel Core processor E-core: 30CH, 329H, 541H,

and 657H. The MSR at address 657H is not supported in the 12th and 13th generation Intel Core processor P-core.

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-46. Additional MSRs Supported by the 12th and 13th Generation Intel® Core™ Processors Supporting

Performance Hybrid Architecture (Contd.)

Bit Description

Scope

UC_LOCK_DISABLE

If set to 1, a UC lock will cause a #GP(0) exception.

See Section 11.1.2.3, “Features to Disable Bus Locks.”

SPLIT_LOCK_DISABLE

If set to 1, a split lock will cause an #AC(0) exception.

See Section 11.1.2.3, “Features to Disable Bus Locks.”

Reserved.

IA32_MISC_PACKAGE_CTLS

Power Filtering Control (R/W)

Package

IA32_ARCH_CAPABILITIES[bit 10] enumerates support for this MSR.

See Table 2-2.

IA32_PMC6

General Performance Counter 6 (R/W)

Core

See Table 2-2.

IA32_PMC7

General Performance Counter 7 (R/W)

Core

See Table 2-2.

IA32_CORE_CAPABILITIES

IA32 Core Capabilities Register (R/O)

Package

If CPUID.07H.00H:EDX[30] = 1.

This MSR provides an architectural enumeration function for model-specific behavior.

STLB_QOS_SUPPORTED

When set to 1, the STLB QoS feature is supported and the STLB

QoS MSRs (1A8FH -1A97H) are accessible. When set to 0, access

to these MSRs will #GP.

Reserved.

FUSA_SUPPORTED

RSM_IN_CPL0_ONLY

When set to 1, the RSM instruction is only allowed in CPL0 (#GP

triggered in any CPL != 0).

When set to 0, then any CPL may execute the RSM instruction.

UC_LOCK_DISABLE_SUPPORTED

When read as 1, software can set bit 28 of MSR_MEMORY_CTRL

(MSR address 33H).

SPLIT_LOCK_DISABLE_SUPPORTED

When read as 1, software can set bit 29 of MSR_MEMORY_CTRL.

SNOOP_FILTER_QOS_SUPPORTED

When set to 1, the Snoop Filter Qos Mask MSRs are supported.

When set to 0, access to these MSRs will #GP.

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-46. Additional MSRs Supported by the 12th and 13th Generation Intel® Core™ Processors Supporting

Performance Hybrid Architecture (Contd.)

Bit Description

Scope

UC_STORE_THROTTLING_SUPPORTED

When set 1, UC Store throttle capability exist through

MSR_MEMORY_CTRL (33H) bit 27.

31:8

Reserved.

IA32_UMWAIT_CONTROL

UMWAIT Control (R/W)

See Table 2-2.

IA32_ARCH_CAPABILITIES

Enumeration of Architectural Features (R/O)

See Table 2-2.

IA32_PERFEVTSEL6

See Table 2-20.

Core

IA32_PERFEVTSEL7

See Table 2-20.

Core

IA32_OVERCLOCKING_STATUS

Overclocking Status (R/O)

Package

IA32_ARCH_CAPABILITIES[bit 23] enumerates support for this MSR. See Table 2-2.

MSR_PRIMARY_TURBO_RATIO_LIMIT

Primary Maximum Turbo Ratio Limit (R/W)

Package

Software can configure these limits when MSR_PLATFORM_INFO[28] = 1. Specifies Maximum Ratio Limit for each

group. Maximum ratio for groups with more cores must decrease monotonically.

7:0

MAX_TURBO_GROUP_0:

Maximum turbo ratio limit with 1 core active.

15:8

MAX_TURBO_GROUP_1:

Maximum turbo ratio limit with 2 cores active.