Intel 64 and IA-32 Architectures. Software Developer’s Manual (2026) - page 74

 

  Index      Manuals     Intel 64 and IA-32 Architectures. Software Developer’s Manual (2026)

 

Search            copyright infringement  

 

   

 

    

 

Content      ..     72      73      74      75     ..

 

 

 

Intel 64 and IA-32 Architectures. Software Developer’s Manual (2026) - page 74

 

 

MODEL-SPECIFIC REGISTERS (MSRS)
2.13.2 Additional Residency MSRs Supported in 4th Generation Intel® Core™ Processors
The 4th generation Intel® Core™ processor family (based on Haswell microarchitecture) with a CPUID Signature
DisplayFamily_DisplayModel value of 06_45H supports the MSR interfaces listed in Table 2-20, Table 2-21, Table
2-29, Table 2-30, and Table 2-31.
Table 2-31. Additional Residency MSRs Supported by 4th Generation Intel® Core™ Processors with a
CPUID Signature DisplayFamily_DisplayModel Value of 06_45H
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: E2H, 226
MSR_PKG_CST_CONFIG_CONTROL
C-State Configuration Control (R/W)
Core
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-states. See http://biosbits.org.
3:0
Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code name (consuming the
least power) for the package. The default is set as factory-configured
package C-state limit.
The following C-state code name encodings are supported:
0000b: C0/C1 (no package C-state support)
0001b: C2
0010b: C3
0011b: C6
0100b: C7
0101b: C7s
0110b: C8
0111b: C9
1000b: C10
9:4
Reserved.
10
I/O MWAIT Redirection Enable (R/W)
14:11
Reserved.
15
CFG Lock (R/WO)
24:16
Reserved.
25
C3 State Auto Demotion Enable (R/W)
26
C1 State Auto Demotion Enable (R/W)
27
Enable C3 Undemotion (R/W)
28
Enable C1 Undemotion (R/W)
63:29
Reserved.
Register Address: 630H, 1584
MSR_PKG_C8_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
Package
ACPI C-States.
59:0
Package C8 Residency Counter (R/O)
Value since last reset that this package is in processor-specific C8 states.
Count at the same frequency as the TSC.
63:60
Reserved.
Register Address: 631H, 1585
MSR_PKG_C9_RESIDENCY
2-304 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-31. Additional Residency MSRs Supported by 4th Generation Intel® Core™ Processors with a
CPUID Signature DisplayFamily_DisplayModel Value of 06_45H
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
Package
ACPI C-States.
59:0
Package C9 Residency Counter (R/O)
Value since last reset that this package is in processor-specific C9 states.
Count at the same frequency as the TSC.
63:60
Reserved.
Register Address: 632H, 1586
MSR_PKG_C10_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
Package
ACPI C-States.
59:0
Package C10 Residency Counter (R/O)
Value since last reset that this package is in processor-specific C10 states.
Count at the same frequency as the TSC.
63:60
Reserved.
See Table 2-20, Table 2-21, Table 2-22, Table 2-29, and Table 2-30 for other MSR definitions applicable to processors with a CPUID
Signature DisplayFamily_DisplayModel value of 06_45H.
2.14
MSRS IN THE INTEL® XEON® PROCESSOR E5 V3 AND E7 V3 PRODUCT
FAMILY
The Intel® Xeon® processor E5 v3 family and the Intel® Xeon® processor E7 v3 family are based on Haswell-E
microarchitecture (CPUID Signature DisplayFamily_DisplayModel value of 06_3F). These processors support the
MSR interfaces listed in Table 2-20, Table 2-29, and Table 2-32.
Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
Register Address: 35H, 53
MSR_CORE_THREAD_COUNT
Configured State of Enabled Processor Core Count and Logical Processor Count (R/O)
Package
• After a Power-On RESET, enumerates factory configuration of the number of processor cores and logical
processors in the physical package.
• Following the sequence of (i) BIOS modified a Configuration Mask which selects a subset of processor cores to be
active post RESET and (ii) a RESET event after the modification, enumerates the current configuration of enabled
processor core count and logical processor count in the physical package.
15:0
THREAD_COUNT (R/O)
The number of logical processors that are currently enabled (by either
factory configuration or BIOS configuration) in the physical package.
31:16
Core_COUNT (R/O)
The number of processor cores that are currently enabled (by either factory
configuration or BIOS configuration) in the physical package.
63:32
Reserved.
Register Address: 53H, 83
MSR_THREAD_ID_INFO
A Hardware Assigned ID for the Logical Processor (R/O)
Thread
Vol. 4
2-305
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
7:0
Logical_Processor_ID (R/O)
An implementation-specific numerical value physically assigned to each
logical processor. This ID is not related to Initial APIC ID or x2APIC ID, it is
unique within a physical package.
63:8
Reserved.
Register Address: E2H, 226
MSR_PKG_CST_CONFIG_CONTROL
C-State Configuration Control (R/W)
Core
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-states.
See http://biosbits.org.
2:0
Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code name (consuming the
least power) for the package. The default is set as factory-configured
package C-state limit.
The following C-state code name encodings are supported:
000b: C0/C1 (no package C-state support)
001b: C2
010b: C6 (non-retention)
011b: C6 (retention)
111b: No Package C state limits. All C states supported by the processor are
available.
9:3
Reserved.
10
I/O MWAIT Redirection Enable (R/W)
14:11
Reserved.
15
CFG Lock (R/WO)
24:16
Reserved.
25
C3 State Auto Demotion Enable (R/W)
26
C1 State Auto Demotion Enable (R/W)
27
Enable C3 Undemotion (R/W)
28
Enable C1 Undemotion (R/W)
29
Package C State Demotion Enable (R/W)
30
Package C State Undemotion Enable (R/W)
63:31
Reserved.
Register Address: 179H, 377
IA32_MCG_CAP
Global Machine Check Capability (R/O)
Thread
7:0
Count
8
MCG_CTL_P
9
MCG_EXT_P
10
MCP_CMCI_P
11
MCG_TES_P
15:12
Reserved.
2-306 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
23:16
MCG_EXT_CNT
24
MCG_SER_P
25
MCG_EM_P
26
MCG_ELOG_P
63:27
Reserved.
Register Address: 17DH, 381
MSR_SMM_MCA_CAP
Enhanced SMM Capabilities (SMM-RO)
Thread
Reports SMM capability Enhancement. Accessible only while in SMM.
57:0
Reserved.
58
SMM_Code_Access_Chk (SMM-RO)
If set to 1, indicates that the SMM code access restriction is supported and a
host-space interface available to SMM handler.
59
Long_Flow_Indication (SMM-RO)
If set to 1, indicates that the SMM long flow indicator is supported and a
host-space interface available to SMM handler.
63:60
Reserved.
Register Address: 17FH, 383
MSR_ERROR_CONTROL
MC Bank Error Configuration (R/W)
Package
0
Reserved.
1
MemError Log Enable (R/W)
When set, enables IMC status bank to log additional info in bits 36:32.
63:2
Reserved.
Register Address: 1ADH, 429
MSR_TURBO_RATIO_LIMIT
Maximum Ratio Limit of Turbo Mode
Package
R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1.
7:0
Maximum Ratio Limit for 1C
Package
Maximum turbo ratio limit of 1 core active.
15:8
Maximum Ratio Limit for 2C
Package
Maximum turbo ratio limit of 2 core active.
23:16
Maximum Ratio Limit for 3C
Package
Maximum turbo ratio limit of 3 core active.
31:24
Maximum Ratio Limit for 4C
Package
Maximum turbo ratio limit of 4 core active.
39:32
Maximum Ratio Limit for 5C
Package
Maximum turbo ratio limit of 5 core active.
47:40
Maximum Ratio Limit for 6C
Package
Maximum turbo ratio limit of 6 core active.
55:48
Maximum Ratio Limit for 7C
Package
Maximum turbo ratio limit of 7 core active.
Vol. 4
2-307
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
63:56
Maximum Ratio Limit for 8C
Package
Maximum turbo ratio limit of 8 core active.
Register Address: 1AEH, 430
MSR_TURBO_RATIO_LIMIT1
Maximum Ratio Limit of Turbo Mode
Package
R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1.
7:0
Maximum Ratio Limit for 9C
Package
Maximum turbo ratio limit of 9 core active.
15:8
Maximum Ratio Limit for 10C
Package
Maximum turbo ratio limit of 10 core active.
23:16
Maximum Ratio Limit for 11C
Package
Maximum turbo ratio limit of 11 core active.
31:24
Maximum Ratio Limit for 12C
Package
Maximum turbo ratio limit of 12 core active.
39:32
Maximum Ratio Limit for 13C
Package
Maximum turbo ratio limit of 13 core active.
47:40
Maximum Ratio Limit for 14C
Package
Maximum turbo ratio limit of 14 core active.
55:48
Maximum Ratio Limit for 15C
Package
Maximum turbo ratio limit of 15 core active.
63:56
Maximum Ratio Limit for16C
Package
Maximum turbo ratio limit of 16 core active.
Register Address: 1AFH, 431
MSR_TURBO_RATIO_LIMIT2
Maximum Ratio Limit of Turbo Mode
Package
R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1.
7:0
Maximum Ratio Limit for 17C
Package
Maximum turbo ratio limit of 17 core active.
15:8
Maximum Ratio Limit for 18C
Package
Maximum turbo ratio limit of 18 core active.
62:16
Reserved.
Package
63
Semaphore for Turbo Ratio Limit Configuration
Package
If 1, the processor uses override configuration1 specified in
MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1, and
MSR_TURBO_RATIO_LIMIT2.
If 0, the processor uses factory-set configuration (Default).
Register Address: 414H, 1044
IA32_MC5_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC5 reports MC errors from the Intel QPI 0 module.
Register Address: 415H, 1045
IA32_MC5_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC5 reports MC errors from the Intel QPI 0 module.
2-308 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
Register Address: 416H, 1046
IA32_MC5_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC5 reports MC errors from the Intel QPI 0 module.
Register Address: 417H, 1047
IA32_MC5_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC5 reports MC errors from the Intel QPI 0 module.
Register Address: 418H, 1048
IA32_MC6_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC6 reports MC errors from the integrated I/O module.
Register Address: 419H, 1049
IA32_MC6_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC6 reports MC errors from the integrated I/O module.
Register Address: 41AH, 1050
IA32_MC6_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC6 reports MC errors from the integrated I/O module.
Register Address: 41BH, 1051
IA32_MC6_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC6 reports MC errors from the integrated I/O module.
Register Address: 41CH, 1052
IA32_MC7_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC7 reports MC errors from the home agent HA 0.
Register Address: 41DH, 1053
IA32_MC7_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC7 reports MC errors from the home agent HA 0.
Register Address: 41EH, 1054
IA32_MC7_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC7 reports MC errors from the home agent HA 0.
Register Address: 41FH, 1055
IA32_MC7_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC7 reports MC errors from the home agent HA 0.
Register Address: 420H, 1056
IA32_MC8_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC8 reports MC errors from the home agent HA 1.
Register Address: 421H, 1057
IA32_MC8_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC8 reports MC errors from the home agent HA 1.
Register Address: 422H, 1058
IA32_MC8_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC8 reports MC errors from the home agent HA 1.
Vol. 4
2-309
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
Register Address: 423H, 1059
IA32_MC8_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC8 reports MC errors from the home agent HA 1.
Register Address: 424H, 1060
IA32_MC9_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 425H, 1061
IA32_MC9_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 426H, 1062
IA32_MC9_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 427H, 1063
IA32_MC9_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 428H, 1064
IA32_MC10_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 429H, 1065
IA32_MC10_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 42AH, 1066
IA32_MC10_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 42BH, 1067
IA32_MC10_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 42CH, 1068
IA32_MC11_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 42DH, 1069
IA32_MC11_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 42EH, 1070
IA32_MC11_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 42FH, 1071
IA32_MC11_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
2-310 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
Register Address: 430H, 1072
IA32_MC12_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 431H, 1073
IA32_MC12_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 432H, 1074
IA32_MC12_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 433H, 1075
IA32_MC12_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 434H, 1076
IA32_MC13_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 435H, 1077
IA32_MC13_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 436H, 1078
IA32_MC13_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 437H, 1079
IA32_MC13_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 438H, 1080
IA32_MC14_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 439H, 1081
IA32_MC14_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 43AH, 1082
IA32_MC14_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 43BH, 1083
IA32_MC14_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 43CH, 1084
IA32_MC15_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Vol. 4
2-311
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
Register Address: 43DH, 1085
IA32_MC15_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 43EH, 1086
IA32_MC15_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 43FH, 1087
IA32_MC15_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 440H, 1088
IA32_MC16_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 441H, 1089
IA32_MC16_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 442H, 1090
IA32_MC16_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 443H, 1091
IA32_MC16_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 444H, 1092
IA32_MC17_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Register Address: 445H, 1093
IA32_MC17_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Register Address: 446H, 1094
IA32_MC17_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Register Address: 447H, 1095
IA32_MC17_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Register Address: 448H, 1096
IA32_MC18_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
2-312 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
Register Address: 449H, 1097
IA32_MC18_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
Register Address: 44AH, 1098
IA32_MC18_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
Register Address: 44BH, 1099
IA32_MC18_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
Register Address: 44CH, 1100
IA32_MC19_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
Register Address: 44DH, 1101
IA32_MC19_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
Register Address: 44EH, 1102
IA32_MC19_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
Register Address: 44FH, 1103
IA32_MC19_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
Register Address: 450H, 1104
IA32_MC20_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC20 reports MC errors from the Intel QPI 1 module.
Register Address: 451H, 1105
IA32_MC20_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC20 reports MC errors from the Intel QPI 1 module.
Register Address: 452H, 1106
IA32_MC20_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC20 reports MC errors from the Intel QPI 1 module.
Register Address: 453H, 1107
IA32_MC20_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC20 reports MC errors from the Intel QPI 1 module.
Register Address: 454H, 1108
IA32_MC21_CTL
Vol. 4
2-313
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC21 reports MC errors from the Intel QPI 2 module.
Register Address: 455H, 1109
IA32_MC21_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC21 reports MC errors from the Intel QPI 2 module.
Register Address: 456H, 1110
IA32_MC21_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC21 reports MC errors from the Intel QPI 2 module.
Register Address: 457H, 1111
IA32_MC21_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC21 reports MC errors from the Intel QPI 2 module.
Register Address: 606H, 1542
MSR_RAPL_POWER_UNIT
Unit Multipliers Used in RAPL Interfaces (R/O)
Package
3:0
Power Units
Package
See Section 17.10.1, “RAPL Interfaces.”
7:4
Reserved.
Package
12:8
Energy Status Units
Package
Energy related information (in Joules) is based on the multiplier, 1/2^ESU;
where ESU is an unsigned integer represented by bits 12:8. Default value is
0EH (or 61 micro-joules).
15:13
Reserved.
Package
19:16
Time Units
Package
See Section 17.10.1, “RAPL Interfaces.”
63:20
Reserved.
Register Address: 618H, 1560
MSR_DRAM_POWER_LIMIT
DRAM RAPL Power Limit Control (R/W)
Package
See Section 17.10.5, “DRAM RAPL Domain.”
Register Address: 619H, 1561
MSR_DRAM_ENERGY_STATUS
DRAM Energy Status (R/O)
Package
Energy Consumed by DRAM devices.
31:0
Energy in 15.3 micro-joules. Requires BIOS configuration to enable DRAM
RAPL mode 0 (Direct VR).
63:32
Reserved.
Register Address: 61BH, 1563
MSR_DRAM_PERF_STATUS
DRAM Performance Throttling Status (R/O)
Package
See Section 17.10.5, “DRAM RAPL Domain.”
Register Address: 61CH, 1564
MSR_DRAM_POWER_INFO
DRAM RAPL Parameters (R/W)
Package
See Section 17.10.5, “DRAM RAPL Domain.”
Register Address: 61EH, 1566
MSR_PCIE_PLL_RATIO
2-314 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
Configuration of PCIE PLL Relative to BCLK(R/W)
Package
1:0
PCIE Ratio (R/W)
Package
00b: Use 5:5 mapping for100MHz operation (default).
01b: Use 5:4 mapping for125MHz operation.
10b: Use 5:3 mapping for166MHz operation.
11b: Use 5:2 mapping for250MHz operation.
2
LPLL Select (R/W)
Package
If 1, use configured setting of PCIE Ratio.
3
LONG RESET (R/W)
Package
If 1, wait an additional time-out before re-locking Gen2/Gen3 PLLs.
63:4
Reserved.
Register Address: 620H, 1568
MSR_UNCORE_RATIO_LIMIT
Uncore Ratio Limit (R/W)
Package
Out of reset, the min_ratio and max_ratio fields represent the widest possible range of uncore frequencies. Writing to
these fields allows software to control the minimum and the maximum frequency that hardware will select.
6:0
MAX_RATIO
This field is used to limit the max ratio of the LLC/Ring.
7
Reserved.
14:8
MIN_RATIO
Writing to this field controls the minimum possible ratio of the LLC/Ring.
63:15
Reserved.
Register Address: 639H, 1593
MSR_PP0_ENERGY_STATUS
Reserved (R/O)
Package
Reads return 0.
Register Address: 690H, 1680
MSR_CORE_PERF_LIMIT_REASONS
Indicator of Frequency Clipping in Processor Cores (R/W)
Package
(Frequency refers to processor core frequency.)
0
PROCHOT Status (R0)
When set, processor core frequency is reduced below the operating system
request due to assertion of external PROCHOT.
1
Thermal Status (R0)
When set, frequency is reduced below the operating system request due to
a thermal event.
2
Power Budget Management Status (R0)
When set, frequency is reduced below the operating system request due to
PBM limit
3
Platform Configuration Services Status (R0)
When set, frequency is reduced below the operating system request due to
PCS limit
4
Reserved.
Vol. 4
2-315
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
5
Autonomous Utilization-Based Frequency Control Status (R0)
When set, frequency is reduced below the operating system request
because the processor has detected that utilization is low.
6
VR Therm Alert Status (R0)
When set, frequency is reduced below the operating system request due to
a thermal alert from the Voltage Regulator.
7
Reserved.
8
Electrical Design Point Status (R0)
When set, frequency is reduced below the operating system request due to
electrical design point constraints (e.g., maximum electrical current
consumption).
9
Reserved.
10
Multi-Core Turbo Status (R0)
When set, frequency is reduced below the operating system request due to
Multi-Core Turbo limits.
12:11
Reserved.
13
Core Frequency P1 Status (R0)
When set, frequency is reduced below max non-turbo P1.
14
Core Max N-Core Turbo Frequency Limiting Status (R0)
When set, frequency is reduced below max n-core turbo frequency.
15
Core Frequency Limiting Status (R0)
When set, frequency is reduced below the operating system request.
16
PROCHOT Log
When set, indicates that the PROCHOT Status bit has asserted since the log
bit was last cleared.
This log bit will remain set until cleared by software writing 0.
17
Thermal Log
When set, indicates that the Thermal Status bit has asserted since the log
bit was last cleared.
This log bit will remain set until cleared by software writing 0.
18
Power Budget Management Log
When set, indicates that the PBM Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software writing 0.
19
Platform Configuration Services Log
When set, indicates that the PCS Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software writing 0.
20
Reserved.
21
Autonomous Utilization-Based Frequency Control Log
When set, indicates that the AUBFC Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software writing 0.
2-316 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
22
VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
23
Reserved.
24
Electrical Design Point Log
When set, indicates that the EDP Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software writing 0.
25
Reserved.
26
Multi-Core Turbo Log
When set, indicates that the Multi-Core Turbo Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
28:27
Reserved.
29
Core Frequency P1 Log
When set, indicates that the Core Frequency P1 Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
30
Core Max N-Core Turbo Frequency Limiting Log
When set, indicates that the Core Max n-core Turbo Frequency Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
31
Core Frequency Limiting Log
When set, indicates that the Core Frequency Limiting Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
63:32
Reserved.
Register Address: C8DH, 3213
IA32_QM_EVTSEL
Monitoring Event Select Register (R/W)
Thread
If CPUID.07H.00H:EBX.RDT_M[12] = 1.
7:0
EventID (R/W)
Event encoding:
0x0: No monitoring.
0x1: L3 occupancy monitoring.
All other encoding reserved.
31:8
Reserved.
41:32
RMID (R/W)
63:42
Reserved.
Register Address: C8EH, 3214
IA32_QM_CTR
Monitoring Counter Register (R/O)
Thread
If CPUID.07H.00H:EBX.RDT_M[12] = 1.
Vol. 4
2-317
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
61:0
Resource Monitored Data
62
Unavailable: If 1, indicates data for this RMID is not available or not
monitored for this resource or RMID.
63
Error: If 1, indicates an unsupported RMID or event type was written to
IA32_PQR_QM_EVTSEL.
Register Address: C8FH, 3215
IA32_PQR_ASSOC
Resource Association Register (R/W)
Thread
9:0
RMID
63: 10
Reserved.
See Table 2-20 and Table 2-29 for other MSR definitions applicable to processors with a CPUID Signature DisplayFamily_DisplayModel
value of 06_3FH.
NOTES:
1. An override configuration lower than the factory-set configuration is always supported. An override configuration higher than the fac-
tory-set configuration is dependent on features specific to the processor and the platform.
2.14.1 Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family
The Intel Xeon Processor E5 v3 and E7 v3 families are based on Haswell-E microarchitecture. The MSR-based
uncore PMU interfaces are listed in Table 2-33. For complete details of the uncore PMU, refer to the Intel Xeon
Processor E5 v3 Product Family Uncore Performance Monitoring Guide. These processors have a CPUID Signature
DisplayFamily_DisplayModel value of 06_3FH.
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 700H, 1792
MSR_PMON_GLOBAL_CTL
Uncore PerfMon Per-Socket Global Control
Package
Register Address: 701H, 1793
MSR_PMON_GLOBAL_STATUS
Uncore PerfMon Per-Socket Global Status
Package
Register Address: 702H, 1794
MSR_PMON_GLOBAL_CONFIG
Uncore PerfMon Per-Socket Global Configuration
Package
Register Address: 703H, 1795
MSR_U_PMON_UCLK_FIXED_CTL
Uncore U-Box UCLK Fixed Counter Control
Package
Register Address: 704H, 1796
MSR_U_PMON_UCLK_FIXED_CTR
Uncore U-Box UCLK Fixed Counter
Package
Register Address: 705H, 1797
MSR_U_PMON_EVNTSEL0
Uncore U-Box PerfMon Event Select for U-Box Counter 0
Package
Register Address: 706H, 1798
MSR_U_PMON_EVNTSEL1
Uncore U-Box PerfMon Event Select for U-Box Counter 1
Package
Register Address: 708H, 1800
MSR_U_PMON_BOX_STATUS
2-318 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Uncore U-Box PerfMon U-Box Wide Status
Package
Register Address: 709H, 1801
MSR_U_PMON_CTR0
Uncore U-Box PerfMon Counter 0
Package
Register Address: 70AH, 1802
MSR_U_PMON_CTR1
Uncore U-Box PerfMon Counter 1
Package
Register Address: 710H, 1808
MSR_PCU_PMON_BOX_CTL
Uncore PCU PerfMon for PCU-Box-Wide Control
Package
Register Address: 711H, 1809
MSR_PCU_PMON_EVNTSEL0
Uncore PCU PerfMon Event Select for PCU Counter 0
Package
Register Address: 712H, 1810
MSR_PCU_PMON_EVNTSEL1
Uncore PCU PerfMon Event Select for PCU Counter 1
Package
Register Address: 713H, 1811
MSR_PCU_PMON_EVNTSEL2
Uncore PCU PerfMon Event Select for PCU Counter 2
Package
Register Address: 714H, 1812
MSR_PCU_PMON_EVNTSEL3
Uncore PCU PerfMon Event Select for PCU Counter 3
Package
Register Address: 715H, 1813
MSR_PCU_PMON_BOX_FILTER
Uncore PCU PerfMon Box-Wide Filter
Package
Register Address: 716H, 1814
MSR_PCU_PMON_BOX_STATUS
Uncore PCU PerfMon Box Wide Status
Package
Register Address: 717H, 1815
MSR_PCU_PMON_CTR0
Uncore PCU PerfMon Counter 0
Package
Register Address: 718H, 1816
MSR_PCU_PMON_CTR1
Uncore PCU PerfMon Counter 1
Package
Register Address: 719H, 1817
MSR_PCU_PMON_CTR2
Uncore PCU PerfMon Counter 2
Package
Register Address: 71AH, 1818
MSR_PCU_PMON_CTR3
Uncore PCU PerfMon Counter 3
Package
Register Address: 720H, 1824
MSR_S0_PMON_BOX_CTL
Uncore SBo 0 PerfMon for SBo 0 Box-Wide Control
Package
Register Address: 721H, 1825
MSR_S0_PMON_EVNTSEL0
Uncore SBo 0 PerfMon Event Select for SBo 0 Counter 0
Package
Register Address: 722H, 1826
MSR_S0_PMON_EVNTSEL1
Uncore SBo 0 PerfMon Event Select for SBo 0 Counter 1
Package
Register Address: 723H, 1827
MSR_S0_PMON_EVNTSEL2
Uncore SBo 0 PerfMon Event Select for SBo 0 Counter 2
Package
Register Address: 724H, 1828
MSR_S0_PMON_EVNTSEL3
Uncore SBo 0 PerfMon Event Select for SBo 0 Counter 3
Package
Vol. 4
2-319
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 725H, 1829
MSR_S0_PMON_BOX_FILTER
Uncore SBo 0 PerfMon Box-Wide Filter
Package
Register Address: 726H, 1830
MSR_S0_PMON_CTR0
Uncore SBo 0 PerfMon Counter 0
Package
Register Address: 727H, 1831
MSR_S0_PMON_CTR1
Uncore SBo 0 PerfMon Counter 1
Package
Register Address: 728H, 1832
MSR_S0_PMON_CTR2
Uncore SBo 0 PerfMon Counter 2
Package
Register Address: 729H, 1833
MSR_S0_PMON_CTR3
Uncore SBo 0 PerfMon Counter 3
Package
Register Address: 72AH, 1834
MSR_S1_PMON_BOX_CTL
Uncore SBo 1 PerfMon for SBo 1 Box-Wide Control
Package
Register Address: 72BH, 1835
MSR_S1_PMON_EVNTSEL0
Uncore SBo 1 PerfMon Event Select for SBo 1 Counter 0
Package
Register Address: 72CH, 1836
MSR_S1_PMON_EVNTSEL1
Uncore SBo 1 PerfMon Event Select for SBo 1 Counter 1
Package
Register Address: 72DH, 1837
MSR_S1_PMON_EVNTSEL2
Uncore SBo 1 PerfMon Event Select for SBo 1 Counter 2
Package
Register Address: 72EH, 1838
MSR_S1_PMON_EVNTSEL3
Uncore SBo 1 PerfMon Event Select for SBo 1 Counter 3
Package
Register Address: 72FH, 1839
MSR_S1_PMON_BOX_FILTER
Uncore SBo 1 PerfMon Box-Wide Filter
Package
Register Address: 730H, 1840
MSR_S1_PMON_CTR0
Uncore SBo 1 PerfMon Counter 0
Package
Register Address: 731H, 1841
MSR_S1_PMON_CTR1
Uncore SBo 1 PerfMon Counter 1
Package
Register Address: 732H, 1842
MSR_S1_PMON_CTR2
Uncore SBo 1 PerfMon Counter 2
Package
Register Address: 733H, 1843
MSR_S1_PMON_CTR3
Uncore SBo 1 PerfMon Counter 3
Package
Register Address: 734H, 1844
MSR_S2_PMON_BOX_CTL
Uncore SBo 2 PerfMon for SBo 2 Box-Wide Control
Package
Register Address: 735H, 1845
MSR_S2_PMON_EVNTSEL0
Uncore SBo 2 PerfMon Event Select for SBo 2 Counter 0
Package
Register Address: 736H, 1846
MSR_S2_PMON_EVNTSEL1
Uncore SBo 2 PerfMon Event Select for SBo 2 Counter 1
Package
Register Address: 737H, 1847
MSR_S2_PMON_EVNTSEL2
2-320 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Uncore SBo 2 PerfMon Event Select for SBo 2 Counter 2
Package
Register Address: 738H, 1848
MSR_S2_PMON_EVNTSEL3
Uncore SBo 2 PerfMon Event Select for SBo 2 Counter 3
Package
Register Address: 739H, 1849
MSR_S2_PMON_BOX_FILTER
Uncore SBo 2 PerfMon Box-Wide Filter
Package
Register Address: 73AH, 1850
MSR_S2_PMON_CTR0
Uncore SBo 2 PerfMon Counter 0
Package
Register Address: 73BH, 1851
MSR_S2_PMON_CTR1
Uncore SBo 2 PerfMon Counter 1
Package
Register Address: 73CH, 1852
MSR_S2_PMON_CTR2
Uncore SBo 2 PerfMon Counter 2
Package
Register Address: 73DH, 1853
MSR_S2_PMON_CTR3
Uncore SBo 2 PerfMon Counter 3
Package
Register Address: 73EH, 1854
MSR_S3_PMON_BOX_CTL
Uncore SBo 3 PerfMon for SBo 3 Box-Wide Control
Package
Register Address: 73FH, 1855
MSR_S3_PMON_EVNTSEL0
Uncore SBo 3 PerfMon Event Select for SBo 3 Counter 0
Package
Register Address: 740H, 1856
MSR_S3_PMON_EVNTSEL1
Uncore SBo 3 PerfMon Event Select for SBo 3 Counter 1
Package
Register Address: 741H, 1857
MSR_S3_PMON_EVNTSEL2
Uncore SBo 3 PerfMon Event Select for SBo 3 Counter 2
Package
Register Address: 742H, 1858
MSR_S3_PMON_EVNTSEL3
Uncore SBo 3 PerfMon Event Select for SBo 3 Counter 3
Package
Register Address: 743H, 1859
MSR_S3_PMON_BOX_FILTER
Uncore SBo 3 PerfMon Box-Wide Filter
Package
Register Address: 744H, 1860
MSR_S3_PMON_CTR0
Uncore SBo 3 PerfMon Counter 0
Package
Register Address: 745H, 1861
MSR_S3_PMON_CTR1
Uncore SBo 3 PerfMon Counter 1
Package
Register Address: 746H, 1862
MSR_S3_PMON_CTR2
Uncore SBo 3 PerfMon Counter 2
Package
Register Address: 747H, 1863
MSR_S3_PMON_CTR3
Uncore SBo 3 PerfMon Counter 3
Package
Register Address: E00H, 3584
MSR_C0_PMON_BOX_CTL
Uncore C-Box 0 PerfMon for Box-Wide Control
Package
Register Address: E01H, 3585
MSR_C0_PMON_EVNTSEL0
Uncore C-Box 0 PerfMon Event Select for C-Box 0 Counter 0
Package
Vol. 4
2-321
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: E02H, 3586
MSR_C0_PMON_EVNTSEL1
Uncore C-Box 0 PerfMon Event Select for C-Box 0 Counter 1
Package
Register Address: E03H, 3587
MSR_C0_PMON_EVNTSEL2
Uncore C-Box 0 PerfMon Event Select for C-Box 0 Counter 2
Package
Register Address: E04H, 3588
MSR_C0_PMON_EVNTSEL3
Uncore C-Box 0 PerfMon Event Select for C-Box 0 Counter 3
Package
Register Address: E05H, 3589
MSR_C0_PMON_BOX_FILTER0
Uncore C-Box 0 PerfMon Box Wide Filter 0
Package
Register Address: E06H, 3590
MSR_C0_PMON_BOX_FILTER1
Uncore C-Box 0 PerfMon Box Wide Filter 1
Package
Register Address: E07H, 3591
MSR_C0_PMON_BOX_STATUS
Uncore C-Box 0 PerfMon Box Wide Status
Package
Register Address: E08H, 3592
MSR_C0_PMON_CTR0
Uncore C-Box 0 PerfMon Counter 0
Package
Register Address: E09H, 3593
MSR_C0_PMON_CTR1
Uncore C-Box 0 PerfMon Counter 1
Package
Register Address: E0AH, 3594
MSR_C0_PMON_CTR2
Uncore C-Box 0 PerfMon Counter 2
Package
Register Address: E0BH, 3595
MSR_C0_PMON_CTR3
Uncore C-Box 0 PerfMon Counter 3
Package
Register Address: E10H, 3600
MSR_C1_PMON_BOX_CTL
Uncore C-Box 1 PerfMon for Box-Wide Control
Package
Register Address: E11H, 3601
MSR_C1_PMON_EVNTSEL0
Uncore C-Box 1 PerfMon Event Select for C-Box 1 Counter 0
Package
Register Address: E12H, 3602
MSR_C1_PMON_EVNTSEL1
Uncore C-Box 1 PerfMon Event Select for C-Box 1 Counter 1
Package
Register Address: E13H, 3603
MSR_C1_PMON_EVNTSEL2
Uncore C-Box 1 PerfMon Event Select for C-Box 1 Counter 2
Package
Register Address: E14H, 3604
MSR_C1_PMON_EVNTSEL3
Uncore C-Box 1 PerfMon Event Select for C-Box 1 Counter 3
Package
Register Address: E15H, 3605
MSR_C1_PMON_BOX_FILTER0
Uncore C-Box 1 PerfMon Box Wide Filter 0
Package
Register Address: E16H, 3606
MSR_C1_PMON_BOX_FILTER1
Uncore C-Box 1 PerfMon Box Wide Filter1
Package
Register Address: E17H, 3607
MSR_C1_PMON_BOX_STATUS
Uncore C-Box 1 PerfMon Box Wide Status
Package
Register Address: E18H, 3608
MSR_C1_PMON_CTR0
2-322 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Uncore C-Box 1 PerfMon Counter 0
Package
Register Address: E19H, 3609
MSR_C1_PMON_CTR1
Uncore C-Box 1 PerfMon Counter 1
Package
Register Address: E1AH, 3610
MSR_C1_PMON_CTR2
Uncore C-Box 1 PerfMon Counter 2
Package
Register Address: E1BH, 3611
MSR_C1_PMON_CTR3
Uncore C-Box 1 PerfMon Counter 3
Package
Register Address: E20H, 3616
MSR_C2_PMON_BOX_CTL
Uncore C-Box 2 PerfMon for Box-Wide Control
Package
Register Address: E21H, 3617
MSR_C2_PMON_EVNTSEL0
Uncore C-Box 2 PerfMon Event Select for C-Box 2 Counter 0
Package
Register Address: E22H, 3618
MSR_C2_PMON_EVNTSEL1
Uncore C-Box 2 PerfMon Event Select for C-Box 2 Counter 1
Package
Register Address: E23H, 3619
MSR_C2_PMON_EVNTSEL2
Uncore C-Box 2 PerfMon Event Select for C-Box 2 Counter 2
Package
Register Address: E24H, 3620
MSR_C2_PMON_EVNTSEL3
Uncore C-Box 2 PerfMon Event select for C-Box 2 Counter 3
Package
Register Address: E25H, 3621
MSR_C2_PMON_BOX_FILTER0
Uncore C-Box 2 PerfMon Box Wide Filter 0
Package
Register Address: E26H, 3622
MSR_C2_PMON_BOX_FILTER1
Uncore C-Box 2 PerfMon Box Wide Filter1
Package
Register Address: E27H, 3623
MSR_C2_PMON_BOX_STATUS
Uncore C-Box 2 PerfMon Box Wide Status
Package
Register Address: E28H, 3624
MSR_C2_PMON_CTR0
Uncore C-Box 2 PerfMon Counter 0
Package
Register Address: E29H, 3625
MSR_C2_PMON_CTR1
Uncore C-Box 2 PerfMon Counter 1
Package
Register Address: E2AH, 3626
MSR_C2_PMON_CTR2
Uncore C-Box 2 PerfMon Counter 2
Package
Register Address: E2BH, 3627
MSR_C2_PMON_CTR3
Uncore C-Box 2 PerfMon Counter 3
Package
Register Address: E30H, 3632
MSR_C3_PMON_BOX_CTL
Uncore C-Box 3 PerfMon for Box-Wide Control
Package
Register Address: E31H, 3633
MSR_C3_PMON_EVNTSEL0
Uncore C-Box 3 PerfMon Event Select for C-Box 3 Counter 0
Package
Register Address: E32H, 3634
MSR_C3_PMON_EVNTSEL1
Uncore C-Box 3 PerfMon Event Select for C-Box 3 Counter 1
Package
Vol. 4
2-323
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: E33H, 3635
MSR_C3_PMON_EVNTSEL2
Uncore C-Box 3 PerfMon Event Select for C-Box 3 Counter 2
Package
Register Address: E34H, 3636
MSR_C3_PMON_EVNTSEL3
Uncore C-Box 3 PerfMon Event Select for C-Box 3 Counter 3
Package
Register Address: E35H, 3637
MSR_C3_PMON_BOX_FILTER0
Uncore C-Box 3 PerfMon Box Wide Filter 0
Package
Register Address: E36H, 3638
MSR_C3_PMON_BOX_FILTER1
Uncore C-Box 3 PerfMon Box Wide Filter1
Package
Register Address: E37H, 3639
MSR_C3_PMON_BOX_STATUS
Uncore C-Box 3 PerfMon Box Wide Status
Package
Register Address: E38H, 3640
MSR_C3_PMON_CTR0
Uncore C-Box 3 PerfMon Counter 0
Package
Register Address: E39H, 3641
MSR_C3_PMON_CTR1
Uncore C-Box 3 PerfMon Counter 1
Package
Register Address: E3AH, 3642
MSR_C3_PMON_CTR2
Uncore C-Box 3 PerfMon Counter 2
Package
Register Address: E3BH, 3643
MSR_C3_PMON_CTR3
Uncore C-Box 3 PerfMon Counter 3
Package
Register Address: E40H, 3648
MSR_C4_PMON_BOX_CTL
Uncore C-Box 4 PerfMon for Box-Wide Control
Package
Register Address: E41H, 3649
MSR_C4_PMON_EVNTSEL0
Uncore C-Box 4 PerfMon Event Select for C-Box 4 Counter 0
Package
Register Address: E42H, 3650
MSR_C4_PMON_EVNTSEL1
Uncore C-Box 4 PerfMon Event Select for C-Box 4 Counter 1
Package
Register Address: E43H, 3651
MSR_C4_PMON_EVNTSEL2
Uncore C-Box 4 PerfMon Event Select for C-Box 4 Counter 2
Package
Register Address: E44H, 3652
MSR_C4_PMON_EVNTSEL3
Uncore C-Box 4 PerfMon Event Select for C-Box 4 Counter 3
Package
Register Address: E45H, 3653
MSR_C4_PMON_BOX_FILTER0
Uncore C-Box 4 PerfMon Box Wide Filter 0
Package
Register Address: E46H, 3654
MSR_C4_PMON_BOX_FILTER1
Uncore C-Box 4 PerfMon Box Wide Filter1
Package
Register Address: E47H, 3655
MSR_C4_PMON_BOX_STATUS
Uncore C-Box 4 PerfMon Box Wide Status
Package
Register Address: E48H, 3656
MSR_C4_PMON_CTR0
Uncore C-Box 4 PerfMon Counter 0
Package
Register Address: E49H, 3657
MSR_C4_PMON_CTR1
2-324 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Uncore C-Box 4 PerfMon Counter 1
Package
Register Address: E4AH, 3658
MSR_C4_PMON_CTR2
Uncore C-Box 4 PerfMon Counter 2
Package
Register Address: E4BH, 3659
MSR_C4_PMON_CTR3
Uncore C-Box 4 PerfMon Counter 3
Package
Register Address: E50H, 3664
MSR_C5_PMON_BOX_CTL
Uncore C-Box 5 PerfMon for Box-Wide Control
Package
Register Address: E51H, 3665
MSR_C5_PMON_EVNTSEL0
Uncore C-Box 5 PerfMon Event Select for C-Box 5 Counter 0
Package
Register Address: E52H, 3666
MSR_C5_PMON_EVNTSEL1
Uncore C-Box 5 PerfMon Event Select for C-Box 5 Counter 1
Package
Register Address: E53H, 3667
MSR_C5_PMON_EVNTSEL2
Uncore C-Box 5 PerfMon Event Select for C-Box 5 Counter 2
Package
Register Address: E54H, 3668
MSR_C5_PMON_EVNTSEL3
Uncore C-Box 5 PerfMon Event Select for C-Box 5 Counter 3
Package
Register Address: E55H, 3669
MSR_C5_PMON_BOX_FILTER0
Uncore C-Box 5 PerfMon Box Wide Filter 0
Package
Register Address: E56H, 3670
MSR_C5_PMON_BOX_FILTER1
Uncore C-Box 5 PerfMon Box Wide Filter 1
Package
Register Address: E57H, 3671
MSR_C5_PMON_BOX_STATUS
Uncore C-Box 5 PerfMon Box Wide Status
Package
Register Address: E58H, 3672
MSR_C5_PMON_CTR0
Uncore C-Box 5 PerfMon Counter 0
Package
Register Address: E59H, 3673
MSR_C5_PMON_CTR1
Uncore C-Box 5 PerfMon Counter 1
Package
Register Address: E5AH, 3674
MSR_C5_PMON_CTR2
Uncore C-Box 5 PerfMon Counter 2
Package
Register Address: E5BH, 3675
MSR_C5_PMON_CTR3
Uncore C-Box 5 PerfMon Counter 3
Package
Register Address: E60H, 3680
MSR_C6_PMON_BOX_CTL
Uncore C-Box 6 PerfMon for Box-Wide Control
Package
Register Address: E61H, 3681
MSR_C6_PMON_EVNTSEL0
Uncore C-Box 6 PerfMon Event Select for C-Box 6 Counter 0
Package
Register Address: E62H, 3682
MSR_C6_PMON_EVNTSEL1
Uncore C-Box 6 PerfMon Event Select for C-Box 6 Counter 1
Package
Register Address: E63H, 3683
MSR_C6_PMON_EVNTSEL2
Uncore C-Box 6 PerfMon Event Select for C-Box 6 Counter 2
Package
Vol. 4
2-325
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: E64H, 3684
MSR_C6_PMON_EVNTSEL3
Uncore C-Box 6 PerfMon Event Select for C-Box 6 Counter 3
Package
Register Address: E65H, 3685
MSR_C6_PMON_BOX_FILTER0
Uncore C-Box 6 PerfMon Box Wide Filter 0
Package
Register Address: E66H, 3686
MSR_C6_PMON_BOX_FILTER1
Uncore C-Box 6 PerfMon Box Wide Filter 1
Package
Register Address: E67H, 3687
MSR_C6_PMON_BOX_STATUS
Uncore C-Box 6 PerfMon Box Wide Status
Package
Register Address: E68H, 3688
MSR_C6_PMON_CTR0
Uncore C-Box 6 PerfMon Counter 0
Package
Register Address: E69H, 3689
MSR_C6_PMON_CTR1
Uncore C-Box 6 PerfMon Counter 1
Package
Register Address: E6AH, 3690
MSR_C6_PMON_CTR2
Uncore C-Box 6 PerfMon Counter 2
Package
Register Address: E6BH, 3691
MSR_C6_PMON_CTR3
Uncore C-Box 6 PerfMon Counter 3
Package
Register Address: E70H, 3696
MSR_C7_PMON_BOX_CTL
Uncore C-Box 7 PerfMon for Box-Wide Control
Package
Register Address: E71H, 3697
MSR_C7_PMON_EVNTSEL0
Uncore C-Box 7 PerfMon Event Select for C-Box 7 Counter 0
Package
Register Address: E72H, 3698
MSR_C7_PMON_EVNTSEL1
Uncore C-Box 7 PerfMon Event Select for C-Box 7 Counter 1
Package
Register Address: E73H, 3699
MSR_C7_PMON_EVNTSEL2
Uncore C-Box 7 PerfMon Event Select for C-Box 7 Counter 2
Package
Register Address: E74H, 3700
MSR_C7_PMON_EVNTSEL3
Uncore C-Box 7 PerfMon Event Select for C-Box 7 Counter 3
Package
Register Address: E75H, 3701
MSR_C7_PMON_BOX_FILTER0
Uncore C-Box 7 PerfMon Box Wide Filter 0
Package
Register Address: E76H, 3702
MSR_C7_PMON_BOX_FILTER1
Uncore C-Box 7 PerfMon Box Wide Filter 1
Package
Register Address: E77H, 3703
MSR_C7_PMON_BOX_STATUS
Uncore C-Box 7 PerfMon Box Wide Status
Package
Register Address: E78H, 3704
MSR_C7_PMON_CTR0
Uncore C-Box 7 PerfMon Counter 0
Package
Register Address: E79H, 3705
MSR_C7_PMON_CTR1
Uncore C-Box 7 PerfMon Counter 1
Package
Register Address: E7AH, 3706
MSR_C7_PMON_CTR2
2-326 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Uncore C-Box 7 PerfMon Counter 2
Package
Register Address: E7BH, 3707
MSR_C7_PMON_CTR3
Uncore C-Box 7 PerfMon Counter 3
Package
Register Address: E80H, 3712
MSR_C8_PMON_BOX_CTL
Uncore C-Box 8 PerfMon Local Box Wide Control
Package
Register Address: E81H, 3713
MSR_C8_PMON_EVNTSEL0
Uncore C-Box 8 PerfMon Event Select for C-Box 8 Counter 0
Package
Register Address: E82H, 3714
MSR_C8_PMON_EVNTSEL1
Uncore C-Box 8 PerfMon Event Select for C-Box 8 Counter 1
Package
Register Address: E83H, 3715
MSR_C8_PMON_EVNTSEL2
Uncore C-Box 8 PerfMon Event Select for C-Box 8 Counter 2
Package
Register Address: E84H, 3716
MSR_C8_PMON_EVNTSEL3
Uncore C-Box 8 PerfMon Event Select for C-Box 8 Counter 3
Package
Register Address: E85H, 3717
MSR_C8_PMON_BOX_FILTER0
Uncore C-Box 8 PerfMon Box Wide Filter 0
Package
Register Address: E86H, 3718
MSR_C8_PMON_BOX_FILTER1
Uncore C-Box 8 PerfMon Box Wide Filter 1
Package
Register Address: E87H, 3719
MSR_C8_PMON_BOX_STATUS
Uncore C-Box 8 PerfMon Box Wide Status
Package
Register Address: E88H, 3720
MSR_C8_PMON_CTR0
Uncore C-Box 8 PerfMon Counter 0
Package
Register Address: E89H, 3721
MSR_C8_PMON_CTR1
Uncore C-Box 8 PerfMon Counter 1
Package
Register Address: E8AH, 3722
MSR_C8_PMON_CTR2
Uncore C-Box 8 PerfMon Counter 2
Package
Register Address: E8BH, 3723
MSR_C8_PMON_CTR3
Uncore C-Box 8 PerfMon Counter 3
Package
Register Address: E90H, 3728
MSR_C9_PMON_BOX_CTL
Uncore C-Box 9 PerfMon Local Box Wide Control
Package
Register Address: E91H, 3729
MSR_C9_PMON_EVNTSEL0
Uncore C-Box 9 PerfMon Event Select for C-Box 9 Counter 0
Package
Register Address: E92H, 3730
MSR_C9_PMON_EVNTSEL1
Uncore C-Box 9 PerfMon Event Select for C-Box 9 Counter 1
Package
Register Address: E93H, 3731
MSR_C9_PMON_EVNTSEL2
Uncore C-Box 9 PerfMon Event Select for C-Box 9 Counter 2
Package
Register Address: E94H, 3732
MSR_C9_PMON_EVNTSEL3
Uncore C-Box 9 PerfMon Event Select for C-Box 9 Counter 3
Package
Vol. 4
2-327
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: E95H, 3733
MSR_C9_PMON_BOX_FILTER0
Uncore C-Box 9 PerfMon Box Wide Filter 0
Package
Register Address: E96H, 3734
MSR_C9_PMON_BOX_FILTER1
Uncore C-Box 9 PerfMon Box Wide Filter 1
Package
Register Address: E97H, 3735
MSR_C9_PMON_BOX_STATUS
Uncore C-Box 9 PerfMon Box Wide Status
Package
Register Address: E98H, 3736
MSR_C9_PMON_CTR0
Uncore C-Box 9 PerfMon Counter 0
Package
Register Address: E99H, 3737
MSR_C9_PMON_CTR1
Uncore C-Box 9 PerfMon Counter 1
Package
Register Address: E9AH, 3738
MSR_C9_PMON_CTR2
Uncore C-Box 9 PerfMon Counter 2
Package
Register Address: E9BH, 3739
MSR_C9_PMON_CTR3
Uncore C-Box 9 PerfMon Counter 3
Package
Register Address: EA0H, 3744
MSR_C10_PMON_BOX_CTL
Uncore C-Box 10 PerfMon Local Box Wide Control
Package
Register Address: EA1H, 3745
MSR_C10_PMON_EVNTSEL0
Uncore C-Box 10 PerfMon Event Select for C-Box 10 Counter 0
Package
Register Address: EA2H, 3746
MSR_C10_PMON_EVNTSEL1
Uncore C-Box 10 PerfMon Event Select for C-Box 10 Counter 1
Package
Register Address: EA3H, 3747
MSR_C10_PMON_EVNTSEL2
Uncore C-Box 10 PerfMon Event Select for C-Box 10 Counter 2
Package
Register Address: EA4H, 3748
MSR_C10_PMON_EVNTSEL3
Uncore C-Box 10 PerfMon Event Select for C-Box 10 Counter 3
Package
Register Address: EA5H, 3749
MSR_C10_PMON_BOX_FILTER0
Uncore C-Box 10 PerfMon Box Wide Filter 0
Package
Register Address: EA6H, 3750
MSR_C10_PMON_BOX_FILTER1
Uncore C-Box 10 PerfMon Box Wide Filter 1
Package
Register Address: EA7H, 3751
MSR_C10_PMON_BOX_STATUS
Uncore C-Box 10 PerfMon Box Wide Status
Package
Register Address: EA8H, 3752
MSR_C10_PMON_CTR0
Uncore C-Box 10 PerfMon Counter 0
Package
Register Address: EA9H, 3753
MSR_C10_PMON_CTR1
Uncore C-Box 10 PerfMon Counter 1
Package
Register Address: EAAH, 3754
MSR_C10_PMON_CTR2
Uncore C-Box 10 PerfMon Counter 2
Package
Register Address: EABH, 3755
MSR_C10_PMON_CTR3
2-328 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Uncore C-Box 10 PerfMon Counter 3
Package
Register Address: EB0H, 3760
MSR_C11_PMON_BOX_CTL
Uncore C-Box 11 PerfMon Local Box Wide Control
Package
Register Address: EB1H, 3761
MSR_C11_PMON_EVNTSEL0
Uncore C-Box 11 PerfMon Event Select for C-Box 11 Counter 0
Package
Register Address: EB2H, 3762
MSR_C11_PMON_EVNTSEL1
Uncore C-Box 11 PerfMon Event Select for C-Box 11 Counter 1
Package
Register Address: EB3H, 3763
MSR_C11_PMON_EVNTSEL2
Uncore C-Box 11 PerfMon Event Select for C-Box 11 Counter 2
Package
Register Address: EB4H, 3764
MSR_C11_PMON_EVNTSEL3
Uncore C-box 11 PerfMon Event Select for C-Box 11 Counter 3
Package
Register Address: EB5H, 3765
MSR_C11_PMON_BOX_FILTER0
Uncore C-Box 11 PerfMon Box Wide Filter 0
Package
Register Address: EB6H, 3766
MSR_C11_PMON_BOX_FILTER1
Uncore C-Box 11 PerfMon Box Wide Filter 1
Package
Register Address: EB7H, 3767
MSR_C11_PMON_BOX_STATUS
Uncore C-Box 11 PerfMon Box Wide Status
Package
Register Address: EB8H, 3768
MSR_C11_PMON_CTR0
Uncore C-Box 11 PerfMon Counter 0
Package
Register Address: EB9H, 3769
MSR_C11_PMON_CTR1
Uncore C-Box 11 PerfMon Counter 1
Package
Register Address: EBAH, 3770
MSR_C11_PMON_CTR2
Uncore C-Box 11 PerfMon Counter 2
Package
Register Address: EBBH, 3771
MSR_C11_PMON_CTR3
Uncore C-Box 11 PerfMon Counter 3
Package
Register Address: EC0H, 3776
MSR_C12_PMON_BOX_CTL
Uncore C-Box 12 PerfMon Local Box Wide Control
Package
Register Address: EC1H, 3777
MSR_C12_PMON_EVNTSEL0
Uncore C-Box 12 PerfMon Event Select for C-Box 12 Counter 0
Package
Register Address: EC2H, 3778
MSR_C12_PMON_EVNTSEL1
Uncore C-Box 12 PerfMon Event Select for C-Box 12 Counter 1
Package
Register Address: EC3H, 3779
MSR_C12_PMON_EVNTSEL2
Uncore C-Box 12 PerfMon Event Select for C-Box 12 Counter 2
Package
Register Address: EC4H, 3780
MSR_C12_PMON_EVNTSEL3
Uncore C-Box 12 PerfMon Event Select for C-Box 12 Counter 3
Package
Register Address: EC5H, 3781
MSR_C12_PMON_BOX_FILTER0
Uncore C-Box 12 PerfMon Box Wide Filter 0
Package
Vol. 4
2-329
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: EC6H, 3782
MSR_C12_PMON_BOX_FILTER1
Uncore C-Box 12 PerfMon Box Wide Filter 1
Package
Register Address: EC7H, 3783
MSR_C12_PMON_BOX_STATUS
Uncore C-Box 12 PerfMon Box Wide Status
Package
Register Address: EC8H, 3784
MSR_C12_PMON_CTR0
Uncore C-Box 12 PerfMon Counter 0
Package
Register Address: EC9H, 3785
MSR_C12_PMON_CTR1
Uncore C-Box 12 PerfMon Counter 1
Package
Register Address: ECAH, 3786
MSR_C12_PMON_CTR2
Uncore C-Box 12 PerfMon Counter 2
Package
Register Address: ECBH, 3787
MSR_C12_PMON_CTR3
Uncore C-Box 12 PerfMon Counter 3
Package
Register Address: ED0H, 3792
MSR_C13_PMON_BOX_CTL
Uncore C-Box 13 PerfMon local box wide control.
Package
Register Address: ED1H, 3793
MSR_C13_PMON_EVNTSEL0
Uncore C-Box 13 PerfMon Event Select for C-Box 13 Counter 0
Package
Register Address: ED2H, 3794
MSR_C13_PMON_EVNTSEL1
Uncore C-Box 13 PerfMon Event Select for C-Box 13 Counter 1
Package
Register Address: ED3H, 3795
MSR_C13_PMON_EVNTSEL2
Uncore C-Box 13 PerfMon Event Select for C-Box 13 Counter 2
Package
Register Address: ED4H, 3796
MSR_C13_PMON_EVNTSEL3
Uncore C-Box 13 PerfMon Event Select for C-Box 13 Counter 3
Package
Register Address: ED5H, 3797
MSR_C13_PMON_BOX_FILTER0
Uncore C-Box 13 PerfMon Box Wide Filter 0
Package
Register Address: ED6H, 3798
MSR_C13_PMON_BOX_FILTER1
Uncore C-Box 13 PerfMon Box Wide Filter 1
Package
Register Address: ED7H, 3799
MSR_C13_PMON_BOX_STATUS
Uncore C-Box 13 PerfMon Box Wide Status
Package
Register Address: ED8H, 3800
MSR_C13_PMON_CTR0
Uncore C-Box 13 PerfMon Counter 0
Package
Register Address: ED9H, 3801
MSR_C13_PMON_CTR1
Uncore C-Box 13 PerfMon Counter 1
Package
Register Address: EDAH, 3802
MSR_C13_PMON_CTR2
Uncore C-Box 13 PerfMon Counter 2
Package
Register Address: EDBH, 3803
MSR_C13_PMON_CTR3
Uncore C-Box 13 PerfMon Counter 3
Package
Register Address: EE0H, 3808
MSR_C14_PMON_BOX_CTL
2-330 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Uncore C-Box 14 PerfMon Local Box Wide Control
Package
Register Address: EE1H, 3809
MSR_C14_PMON_EVNTSEL0
Uncore C-Box 14 PerfMon Event Select for C-Box 14 Counter 0
Package
Register Address: EE2H, 3810
MSR_C14_PMON_EVNTSEL1
Uncore C-Box 14 PerfMon Event Select for C-Box 14 Counter 1
Package
Register Address: EE3H, 3811
MSR_C14_PMON_EVNTSEL2
Uncore C-Box 14 PerfMon Event Select for C-Box 14 Counter 2
Package
Register Address: EE4H, 3812
MSR_C14_PMON_EVNTSEL3
Uncore C-Box 14 PerfMon Event Select for C-Box 14 Counter 3
Package
Register Address: EE5H, 3813
MSR_C14_PMON_BOX_FILTER
Uncore C-Box 14 PerfMon Box Wide Filter 0
Package
Register Address: EE6H, 3814
MSR_C14_PMON_BOX_FILTER1
Uncore C-Box 14 PerfMon Box Wide Filter 1
Package
Register Address: EE7H, 3815
MSR_C14_PMON_BOX_STATUS
Uncore C-Box 14 PerfMon Box Wide Status
Package
Register Address: EE8H, 3816
MSR_C14_PMON_CTR0
Uncore C-Box 14 PerfMon Counter 0
Package
Register Address: EE9H, 3817
MSR_C14_PMON_CTR1
Uncore C-Box 14 PerfMon Counter 1
Package
Register Address: EEAH, 3818
MSR_C14_PMON_CTR2
Uncore C-Box 14 PerfMon Counter 2
Package
Register Address: EEBH, 3819
MSR_C14_PMON_CTR3
Uncore C-Box 14 PerfMon Counter 3
Package
Register Address: EF0H, 3824
MSR_C15_PMON_BOX_CTL
Uncore C-Box 15 PerfMon Local Box Wide Control
Package
Register Address: EF1H, 3825
MSR_C15_PMON_EVNTSEL0
Uncore C-Box 15 PerfMon Event Select for C-Box 15 Counter 0
Package
Register Address: EF2H, 3826
MSR_C15_PMON_EVNTSEL1
Uncore C-Box 15 PerfMon Event Select for C-Box 15 Counter 1
Package
Register Address: EF3H, 3827
MSR_C15_PMON_EVNTSEL2
Uncore C-Box 15 PerfMon Event Select for C-Box 15 Counter 2
Package
Register Address: EF4H, 3828
MSR_C15_PMON_EVNTSEL3
Uncore C-Box 15 PerfMon Event Select for C-Box 15 Counter 3
Package
Register Address: EF5H, 3829
MSR_C15_PMON_BOX_FILTER0
Uncore C-Box 15 PerfMon Box Wide Filter 0
Package
Register Address: EF6H, 3830
MSR_C15_PMON_BOX_FILTER1
Uncore C-Box 15 PerfMon Box Wide Filter 1
Package
Vol. 4
2-331
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: EF7H, 3831
MSR_C15_PMON_BOX_STATUS
Uncore C-Box 15 PerfMon Box Wide Status
Package
Register Address: EF8H, 3832
MSR_C15_PMON_CTR0
Uncore C-Box 15 PerfMon Counter 0
Package
Register Address: EF9H, 3833
MSR_C15_PMON_CTR1
Uncore C-Box 15 PerfMon Counter 1
Package
Register Address: EFAH, 3834
MSR_C15_PMON_CTR2
Uncore C-Box 15 PerfMon Counter 2
Package
Register Address: EFBH, 3835
MSR_C15_PMON_CTR3
Uncore C-Box 15 PerfMon Counter 3
Package
Register Address: F00H, 3840
MSR_C16_PMON_BOX_CTL
Uncore C-Box 16 PerfMon for Box-Wide Control
Package
Register Address: F01H, 3841
MSR_C16_PMON_EVNTSEL0
Uncore C-Box 16 PerfMon Event Select for C-Box 16 Counter 0
Package
Register Address: F02H, 3842
MSR_C16_PMON_EVNTSEL1
Uncore C-Box 16 PerfMon Event Select for C-Box 16 Counter 1
Package
Register Address: F03H, 3843
MSR_C16_PMON_EVNTSEL2
Uncore C-Box 16 PerfMon Event Select for C-Box 16 Counter 2
Package
Register Address: F04H, 3844
MSR_C16_PMON_EVNTSEL3
Uncore C-Box 16 PerfMon Event Select for C-Box 16 Counter 3
Package
Register Address: F05H, 3845
MSR_C16_PMON_BOX_FILTER0
Uncore C-Box 16 PerfMon Box Wide Filter 0
Package
Register Address: F06H, 3846
MSR_C16_PMON_BOX_FILTER1
Uncore C-Box 16 PerfMon Box Wide Filter 1
Package
Register Address: F07H, 3847
MSR_C16_PMON_BOX_STATUS
Uncore C-Box 16 PerfMon Box Wide Status
Package
Register Address: F08H, 3848
MSR_C16_PMON_CTR0
Uncore C-Box 16 PerfMon Counter 0
Package
Register Address: F09H, 3849
MSR_C16_PMON_CTR1
Uncore C-Box 16 PerfMon Counter 1
Package
Register Address: F0AH, 3850
MSR_C16_PMON_CTR2
Uncore C-Box 16 PerfMon Counter 2
Package
Register Address: F0BH, 3851
MSR_C16_PMON_CTR3
Uncore C-Box 16 PerfMon Counter 3
Package
Register Address: F10H, 3856
MSR_C17_PMON_BOX_CTL
Uncore C-Box 17 PerfMon for Box-Wide Control
Package
Register Address: F11H, 3857
MSR_C17_PMON_EVNTSEL0
2-332 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Uncore C-Box 17 PerfMon Event Select for C-Box 17 Counter 0
Package
Register Address: F12H, 3858
MSR_C17_PMON_EVNTSEL1
Uncore C-Box 17 PerfMon Event Select for C-Box 17 Counter 1
Package
Register Address: F13H, 3859
MSR_C17_PMON_EVNTSEL2
Uncore C-Box 17 PerfMon Event Select for C-Box 17 Counter 2
Package
Register Address: F14H, 3860
MSR_C17_PMON_EVNTSEL3
Uncore C-Box 17 PerfMon Event Select for C-Box 17 Counter 3
Package
Register Address: F15H, 3861
MSR_C17_PMON_BOX_FILTER0
Uncore C-Box 17 PerfMon Box Wide Filter 0
Package
Register Address: F16H, 3862
MSR_C17_PMON_BOX_FILTER1
Uncore C-Box 17 PerfMon Box Wide Filter1
Package
Register Address: F17H, 3863
MSR_C17_PMON_BOX_STATUS
Uncore C-Box 17 PerfMon Box Wide Status
Package
Register Address: F18H, 3864
MSR_C17_PMON_CTR0
Uncore C-Box 17 PerfMon Counter 0
Package
Register Address: F19H, 3865
MSR_C17_PMON_CTR1
Uncore C-Box 17 PerfMon Counter 1
Package
Register Address: F1AH, 3866
MSR_C17_PMON_CTR2
Uncore C-Box 17 PerfMon Counter 2
Package
Register Address: F1BH, 3867
MSR_C17_PMON_CTR3
Uncore C-Box 17 PerfMon Counter 3
Package
2.15
MSRS IN THE INTEL® CORE™ M PROCESSORS AND THE 5TH GENERATION
INTEL® CORE™ PROCESSORS
The Intel® Core™ M-5xxx processors, 5th generation Intel® Core™ Processors, and the Intel® Xeon® Processor
E3-1200 v4 family are based on Broadwell microarchitecture. The Intel® Core™ M-5xxx processors and 5th gener-
ation Intel® Core™ Processors have a CPUID Signature DisplayFamily_DisplayModel value of 06_3DH. The Intel®
Xeon® Processor E3-1200 v4 family and 5th generation Intel® Core™ Processors have a CPUID Signature
DisplayFamily_DisplayModel value of 06_47H. Processors with a CPUID Signature DisplayFamily_DisplayModel
value of 06_3DH or 06_47H support the MSR interfaces listed in Table 2-20, Table 2-21, Table 2-22, Table 2-25,
Table 2-29, Table 2-30, Table 2-34, and Table 2-35. For an MSR listed in Table 2-35 that also appears in the model-
specific tables of prior generations, Table 2-35 supersedes prior generation tables.
Table 2-34 lists MSRs that are common to processors based on the Broadwell microarchitectures (including CPUID
Signature DisplayFamily_DisplayModel values of 06_3DH, 06_47H, 06_4FH, and 06_56H).
Table 2-34. Additional MSRs Common to Processors Based on Broadwell Microarchitectures
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 38EH, 910
IA32_PERF_GLOBAL_STATUS
Vol. 4
2-333
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-34. Additional MSRs Common to Processors Based on Broadwell Microarchitectures
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
See Table 2-2 and Section 22.6.2.2, “Global Counter Control Facilities.”
Thread
0
Ovf_PMC0
1
Ovf_PMC1
2
Ovf_PMC2
3
Ovf_PMC3
31:4
Reserved
32
Ovf_FixedCtr0
33
Ovf_FixedCtr1
34
Ovf_FixedCtr2
54:35
Reserved.
55
Trace_ToPA_PMI
See Section 36.2.7.2, “Table of Physical Addresses (ToPA).”
60:56
Reserved.
61
Ovf_Uncore
62
Ovf_BufDSSAVE
63
CondChgd
Register Address: 390H, 912
IA32_PERF_GLOBAL_OVF_CTRL
See Table 2-2 and Section 22.6.2.2, “Global Counter Control Facilities.”
Thread
0
Set 1 to clear Ovf_PMC0.
1
Set 1 to clear Ovf_PMC1.
2
Set 1 to clear Ovf_PMC2.
3
Set 1 to clear Ovf_PMC3.
31:4
Reserved.
32
Set 1 to clear Ovf_FixedCtr0.
33
Set 1 to clear Ovf_FixedCtr1.
34
Set 1 to clear Ovf_FixedCtr2
54:35
Reserved.
55
Set 1 to clear Trace_ToPA_PMI. See Section 36.2.7.2, “Table of Physical
Addresses (ToPA).”
60:56
Reserved.
61
Set 1 to clear Ovf_Uncore.
62
Set 1 to clear Ovf_BufDSSAVE.
63
Set 1 to clear CondChgd.
Register Address: 560H, 1376
IA32_RTIT_OUTPUT_BASE
Trace Output Base Register (R/W)
Thread
6:0
Reserved.
M-1:7
Base physical address. M is the value enumerated by
CPUID.80000008H:EAX[7:0].
2-334 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-34. Additional MSRs Common to Processors Based on Broadwell Microarchitectures
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
63:M
Reserved.
Register Address: 561H, 1377
IA32_RTIT_OUTPUT_MASK_PTRS
Trace Output Mask Pointers Register (R/W)
Thread
6:0
Reserved.
31:7
MaskOrTableOffset
63:32
Output Offset.
Register Address: 570H, 1392
IA32_RTIT_CTL
Trace Control Register (R/W)
Thread
0
TraceEn
1
Reserved, must be zero.
2
OS
3
User
6:4
Reserved, must be zero.
7
CR3Filter
8
ToPA
Writing 0 will #GP if also setting TraceEn.
9
Reserved, must be zero.
10
TSCEn
11
DisRETC
12
Reserved, must be zero.
13
Reserved; writing 0 will #GP if also setting TraceEn.
63:14
Reserved, must be zero.
Register Address: 571H, 1393
IA32_RTIT_STATUS
Tracing Status Register (R/W)
Thread
0
Reserved, writes ignored.
1
ContexEn, writes ignored.
2
TriggerEn, writes ignored.
3
Reserved
4
Error (R/W)
5
Stopped
63:6
Reserved, must be zero.
Register Address: 572H, 1394
IA32_RTIT_CR3_MATCH
Trace Filter CR3 Match Register (R/W)
Thread
4:0
Reserved.
63:5
CR3[63:5] value to match.
Register Address: 620H, 1568
MSR_UNCORE_RATIO_LIMIT
Vol. 4
2-335
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-34. Additional MSRs Common to Processors Based on Broadwell Microarchitectures
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Uncore Ratio Limit (R/W)
Package
Out of reset, the min_ratio and max_ratio fields represent the widest possible range of uncore frequencies. Writing to
these fields allows software to control the minimum and the maximum frequency that hardware will select.
6:0
MAX_RATIO
This field is used to limit the max ratio of the LLC/Ring.
7
Reserved.
14:8
MIN_RATIO
Writing to this field controls the minimum possible ratio of the LLC/Ring.
63:15
Reserved.
Table 2-35 lists MSRs that are specific to Intel Core M processors and 5th Generation Intel Core Processors.
Table 2-35. Additional MSRs Supported by Intel® Core™ M Processors and 5th Generation Intel® Core™ Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: E2H, 226
MSR_PKG_CST_CONFIG_CONTROL
C-State Configuration Control (R/W)
Core
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-states. See http://biosbits.org.
3:0
Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code name (consuming the
least power) for the package. The default is set as factory-configured
package C-state limit.
The following C-state code name encodings are supported:
0000b: C0/C1 (no package C-state support)
0001b: C2
0010b: C3
0011b: C6
0100b: C7
0101b: C7s
0110b: C8
0111b: C9
1000b: C10
9:4
Reserved.
10
I/O MWAIT Redirection Enable (R/W)
14:11
Reserved.
15
CFG Lock (R/WO)
24:16
Reserved.
25
C3 State Auto Demotion Enable (R/W)
26
C1 State Auto Demotion Enable (R/W)
2-336 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-35. Additional MSRs Supported by Intel® Core™ M Processors and 5th Generation Intel® Core™ Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
27
Enable C3 Undemotion (R/W)
28
Enable C1 Undemotion (R/W)
29
Enable Package C-State Auto-Demotion (R/W)
30
Enable Package C-State Undemotion (R/W)
63:31
Reserved.
Register Address: 1ADH, 429
MSR_TURBO_RATIO_LIMIT
Maximum Ratio Limit of Turbo Mode
Package
R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1.
7:0
Maximum Ratio Limit for 1C
Package
Maximum turbo ratio limit of 1 core active.
15:8
Maximum Ratio Limit for 2C
Package
Maximum turbo ratio limit of 2 core active.
23:16
Maximum Ratio Limit for 3C
Package
Maximum turbo ratio limit of 3 core active.
31:24
Maximum Ratio Limit for 4C
Package
Maximum turbo ratio limit of 4 core active.
39:32
Maximum Ratio Limit for 5C
Package
Maximum turbo ratio limit of 5core active.
47:40
Maximum Ratio Limit for 6C
Package
Maximum turbo ratio limit of 6core active.
63:48
Reserved.
Register Address: 639H, 1593
MSR_PP0_ENERGY_STATUS
PP0 Energy Status (R/O)
Package
See Section 17.10.4, “PP0/PP1 RAPL Domains.”
See Table 2-20, Table 2-21, Table 2-22, Table 2-25, Table 2-29, Table 2-30, and Table 2-34 for other MSR definitions applicable to
processors with a CPUID Signature DisplayFamily_DisplayModel value of 06_3DH.
2.16
MSRS IN THE INTEL® XEON® PROCESSOR E5 V4 FAMILY
The MSRs listed in Table 2-36 are available and common to the Intel® Xeon® Processor D Product Family (CPUID
Signature DisplayFamily_DisplayModel value of 06_56H) and to the Intel Xeon processors E5 v4 and E7 v4 families
(CPUID Signature DisplayFamily_DisplayModel value of 06_4FH). These processors are based on Broadwell
microarchitecture.
See Section 2.16.1 for lists of tables of MSRs that are supported by the Intel® Xeon® Processor D Family.
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family
Based on Broadwell Microarchitecture
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
Register Address: 4EH, 78
IA32_PPIN_CTL (MSR_PPIN_CTL)
Vol. 4
2-337
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family
Based on Broadwell Microarchitecture (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
Protected Processor Inventory Number Enable Control (R/W)
Package
0
LockOut (R/WO)
See Table 2-2.
1
Enable_PPIN (R/W)
See Table 2-2.
63:2
Reserved
Register Address: 4FH, 79
IA32_PPIN (MSR_PPIN)
Protected Processor Inventory Number (R/O)
Package
63:0
Protected Processor Inventory Number (R/O)
See Table 2-2.
Register Address: CEH, 206
MSR_PLATFORM_INFO
Platform Information
Package
Contains power management and other model specific features enumeration. See http://biosbits.org.
7:0
Reserved.
15:8
Maximum Non-Turbo Ratio (R/O)
Package
See Table 2-26.
22:16
Reserved.
23
PPIN_CAP (R/O)
Package
See Table 2-26.
27:24
Reserved.
28
Programmable Ratio Limit for Turbo Mode (R/O)
Package
See Table 2-26.
29
Programmable TDP Limit for Turbo Mode (R/O)
Package
See Table 2-26.
30
Programmable TJ OFFSET (R/O)
Package
See Table 2-26.
39:31
Reserved.
47:40
Maximum Efficiency Ratio (R/O)
Package
See Table 2-26.
63:48
Reserved.
Register Address: E2H, 226
MSR_PKG_CST_CONFIG_CONTROL
C-State Configuration Control (R/W)
Core
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-states. See http://biosbits.org.
2-338 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family
Based on Broadwell Microarchitecture (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
2:0
Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code name (consuming the
least power) for the package. The default is set as factory-configured
package C-state limit.
The following C-state code name encodings are supported:
000b: C0/C1 (no package C-state support)
001b: C2
010b: C6 (non-retention)
011b: C6 (retention)
111b: No Package C state limits. All C states supported by the processor
are available.
9:3
Reserved.
10
I/O MWAIT Redirection Enable (R/W)
14:11
Reserved.
15
CFG Lock (R/WO)
16
Automatic C-State Conversion Enable (R/W)
If 1, the processor will convert HALT or MWAT(C1) to MWAIT(C6).
24:17
Reserved.
25
C3 State Auto Demotion Enable (R/W)
26
C1 State Auto Demotion Enable (R/W)
27
Enable C3 Undemotion (R/W)
28
Enable C1 Undemotion (R/W)
29
Package C State Demotion Enable (R/W)
30
Package C State Undemotion Enable (R/W)
63:31
Reserved.
Register Address: 179H, 377
IA32_MCG_CAP
Global Machine Check Capability (R/O)
Thread
7:0
Count
8
MCG_CTL_P
9
MCG_EXT_P
10
MCP_CMCI_P
11
MCG_TES_P
15:12
Reserved
23:16
MCG_EXT_CNT
24
MCG_SER_P
25
MCG_EM_P
26
MCG_ELOG_P
63:27
Reserved.
Register Address: 17DH, 381
MSR_SMM_MCA_CAP
Vol. 4
2-339
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family
Based on Broadwell Microarchitecture (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
Enhanced SMM Capabilities (SMM-RO)
Thread
Reports SMM capability Enhancement. Accessible only while in SMM.
57:0
Reserved.
58
SMM_Code_Access_Chk (SMM-RO)
If set to 1, indicates that the SMM code access restriction is supported and
a host-space interface available to SMM handler.
59
Long_Flow_Indication (SMM-RO)
If set to 1, indicates that the SMM long flow indicator is supported and a
host-space interface available to SMM handler.
63:60
Reserved.
Register Address: 19CH, 412
IA32_THERM_STATUS
Thermal Monitor Status (R/W)
Core
See Table 2-2.
0
Thermal Status (R/O)
See Table 2-2.
1
Thermal Status Log (R/WC0)
See Table 2-2.
2
PROTCHOT # or FORCEPR# Status (R/O)
See Table 2-2.
3
PROTCHOT # or FORCEPR# Log (R/WC0)
See Table 2-2.
4
Critical Temperature Status (R/O)
See Table 2-2.
5
Critical Temperature Status Log (R/WC0)
See Table 2-2.
6
Thermal Threshold #1 Status (R/O)
See Table 2-2.
7
Thermal Threshold #1 Log (R/WC0)
See Table 2-2.
8
Thermal Threshold #2 Status (R/O)
See Table 2-2.
9
Thermal Threshold #2 Log (R/WC0)
See Table 2-2.
10
Power Limitation Status (R/O)
See Table 2-2.
11
Power Limitation Log (R/WC0)
See Table 2-2.
12
Current Limit Status (R/O)
See Table 2-2.
2-340 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family
Based on Broadwell Microarchitecture (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
13
Current Limit Log (R/WC0)
See Table 2-2.
14
Cross Domain Limit Status (R/O)
See Table 2-2.
15
Cross Domain Limit Log (R/WC0)
See Table 2-2.
22:16
Digital Readout (R/O)
See Table 2-2.
26:23
Reserved.
30:27
Resolution in Degrees Celsius (R/O)
See Table 2-2.
31
Reading Valid (R/O)
See Table 2-2.
63:32
Reserved.
Register Address: 1A2H, 418
MSR_TEMPERATURE_TARGET
Temperature Target
Package
15:0
Reserved.
23:16
Temperature Target (R/O)
See Table 2-26.
27:24
TCC Activation Offset (R/W)
See Table 2-26.
63:28
Reserved.
Register Address: 1ADH, 429
MSR_TURBO_RATIO_LIMIT
Maximum Ratio Limit of Turbo Mode
Package
R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1.
7:0
Maximum Ratio Limit for 1C
Package
15:8
Maximum Ratio Limit for 2C
Package
23:16
Maximum Ratio Limit for 3C
Package
31:24
Maximum Ratio Limit for 4C
Package
39:32
Maximum Ratio Limit for 5C
Package
47:40
Maximum Ratio Limit for 6C
Package
55:48
Maximum Ratio Limit for 7C
Package
63:56
Maximum Ratio Limit for 8C
Package
Register Address: 1AEH, 430
MSR_TURBO_RATIO_LIMIT1
Maximum Ratio Limit of Turbo Mode
Package
R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1.
7:0
Maximum Ratio Limit for 9C
Package
15:8
Maximum Ratio Limit for 10C
Package
Vol. 4
2-341
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family
Based on Broadwell Microarchitecture (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
23:16
Maximum Ratio Limit for 11C
Package
31:24
Maximum Ratio Limit for 12C
Package
39:32
Maximum Ratio Limit for 13C
Package
47:40
Maximum Ratio Limit for 14C
Package
55:48
Maximum Ratio Limit for 15C
Package
63:56
Maximum Ratio Limit for 16C
Package
Register Address: 606H, 1542
MSR_RAPL_POWER_UNIT
Unit Multipliers Used in RAPL Interfaces (R/O)
Package
3:0
Power Units
Package
See Section 17.10.1, “RAPL Interfaces.”
7:4
Reserved.
Package
12:8
Energy Status Units
Package
Energy related information (in Joules) is based on the multiplier, 1/2^ESU;
where ESU is an unsigned integer represented by bits 12:8. Default value
is 0EH (or 61 micro-joules).
15:13
Reserved.
Package
19:16
Time Units
Package
See Section 17.10.1, “RAPL Interfaces.”
63:20
Reserved.
Register Address: 618H, 1560
MSR_DRAM_POWER_LIMIT
DRAM RAPL Power Limit Control (R/W)
Package
See Section 17.10.5, “DRAM RAPL Domain.”
Register Address: 619H, 1561
MSR_DRAM_ENERGY_STATUS
DRAM Energy Status (R/O)
Package
Energy consumed by DRAM devices.
31:0
Energy in 15.3 micro-joules. Requires BIOS configuration to enable DRAM
RAPL mode 0 (Direct VR).
63:32
Reserved.
Register Address: 61BH, 1563
MSR_DRAM_PERF_STATUS
DRAM Performance Throttling Status (R/O)
Package
See Section 17.10.5, “DRAM RAPL Domain.”
Register Address: 61CH, 1564
MSR_DRAM_POWER_INFO
DRAM RAPL Parameters (R/W)
Package
See Section 17.10.5, “DRAM RAPL Domain.”
Register Address: 620H, 1568
MSR_UNCORE_RATIO_LIMIT
Uncore Ratio Limit (R/W)
Package
Out of reset, the min_ratio and max_ratio fields represent the widest possible range of uncore frequencies. Writing
to these fields allows software to control the minimum and the maximum frequency that hardware will select.
63:15
Reserved.
2-342 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family
Based on Broadwell Microarchitecture (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
14:8
MIN_RATIO
Writing to this field controls the minimum possible ratio of the LLC/Ring.
7
Reserved.
6:0
MAX_RATIO
This field is used to limit the max ratio of the LLC/Ring.
Register Address: 639H, 1593
MSR_PP0_ENERGY_STATUS
Reserved (R/O)
Package
Reads return 0.
Register Address: 690H, 1680
MSR_CORE_PERF_LIMIT_REASONS
Indicator of Frequency Clipping in Processor Cores (R/W)
Package
(Frequency refers to processor core frequency.)
0
PROCHOT Status (R0)
When set, processor core frequency is reduced below the operating
system request due to assertion of external PROCHOT.
1
Thermal Status (R0)
When set, frequency is reduced below the operating system request due
to a thermal event.
2
Power Budget Management Status (R0)
When set, frequency is reduced below the operating system request due
to PBM limit.
3
Platform Configuration Services Status (R0)
When set, frequency is reduced below the operating system request due
to PCS limit.
4
Reserved.
5
Autonomous Utilization-Based Frequency Control Status (R0)
When set, frequency is reduced below the operating system request
because the processor has detected that utilization is low.
6
VR Therm Alert Status (R0)
When set, frequency is reduced below the operating system request due
to a thermal alert from the Voltage Regulator.
7
Reserved.
8
Electrical Design Point Status (R0)
When set, frequency is reduced below the operating system request due
to electrical design point constraints (e.g., maximum electrical current
consumption).
9
Reserved.
10
Multi-Core Turbo Status (R0)
When set, frequency is reduced below the operating system request due
to Multi-Core Turbo limits.
12:11
Reserved.
Vol. 4
2-343
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family
Based on Broadwell Microarchitecture (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
13
Core Frequency P1 Status (R0)
When set, frequency is reduced below max non-turbo P1.
14
Core Max N-Core Turbo Frequency Limiting Status (R0)
When set, frequency is reduced below max n-core turbo frequency.
15
Core Frequency Limiting Status (R0)
When set, frequency is reduced below the operating system request.
16
PROCHOT Log
When set, indicates that the PROCHOT Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
17
Thermal Log
When set, indicates that the Thermal Status bit has asserted since the log
bit was last cleared.
This log bit will remain set until cleared by software writing 0.
18
Power Budget Management Log
When set, indicates that the PBM Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software writing 0.
19
Platform Configuration Services Log
When set, indicates that the PCS Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software writing 0.
20
Reserved.
21
Autonomous Utilization-Based Frequency Control Log
When set, indicates that the AUBFC Status bit has asserted since the log
bit was last cleared.
This log bit will remain set until cleared by software writing 0.
22
VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
23
Reserved.
24
Electrical Design Point Log
When set, indicates that the EDP Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software writing 0.
25
Reserved.
26
Multi-Core Turbo Log
When set, indicates that the Multi-Core Turbo Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
28:27
Reserved.
2-344 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family
Based on Broadwell Microarchitecture (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
29
Core Frequency P1 Log
When set, indicates that the Core Frequency P1 Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
30
Core Max N-Core Turbo Frequency Limiting Log
When set, indicates that the Core Max n-core Turbo Frequency Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
31
Core Frequency Limiting Log
When set, indicates that the Core Frequency Limiting Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
63:32
Reserved.
Register Address: 770H, 1904
IA32_PM_ENABLE
See Section 17.4.2, “Enabling HWP.”
Package
Register Address: 771H, 1905
IA32_HWP_CAPABILITIES
See Section 17.4.3, “HWP Performance Range and Dynamic Capabilities.”
Thread
Register Address: 774H, 1908
IA32_HWP_REQUEST
See Section 17.4.4, “Managing HWP.”
Thread
7:0
Minimum Performance (R/W)
15:8
Maximum Performance (R/W)
23:16
Desired Performance (R/W)
63:24
Reserved.
Register Address: 777H, 1911
IA32_HWP_STATUS
See Section 17.4.5, “HWP Feedback.”
Thread
1:0
Reserved.
2
Excursion to Minimum (R/O)
63:3
Reserved.
Register Address: C8DH, 3213
IA32_QM_EVTSEL
Monitoring Event Select Register (R/W)
Thread
If CPUID.07H.00H:EBX.RDT_M[12] = 1.
7:0
EventID (R/W)
Event encoding:
0x00: No monitoring.
0x01: L3 occupancy monitoring.
0x02: Total memory bandwidth monitoring.
0x03: Local memory bandwidth monitoring.
All other encoding reserved.
31:8
Reserved.
Vol. 4
2-345
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family
Based on Broadwell Microarchitecture (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
41:32
RMID (R/W)
63:42
Reserved.
Register Address: C8FH, 3215
IA32_PQR_ASSOC
Resource Association Register (R/W)
Thread
9:0
RMID
31:10
Reserved.
51:32
CLOS (R/W)
63: 52
Reserved.
Register Address: C90H, 3216
IA32_L3_QOS_MASK_0
L3 Class Of Service Mask - CLOS 0 (R/W)
Package
If CPUID.10H.01H:EDX.CAT_MAX_CLOS[15:0] >= 0.
0:19
CBM: Bit vector of available L3 ways for CLOS 0 enforcement.
63:20
Reserved.
Register Address: C91H, 3217
IA32_L3_QOS_MASK_1
L3 Class Of Service Mask - CLOS 1 (R/W)
Package
If CPUID.10H.01H:EDX.CAT_MAX_CLOS[15:0] >= 1.
0:19
CBM: Bit vector of available L3 ways for CLOS 1 enforcement.
63:20
Reserved.
Register Address: C92H, 3218
IA32_L3_QOS_MASK_2
L3 Class Of Service Mask - CLOS 2 (R/W)
Package
If CPUID.10H.01H:EDX.CAT_MAX_CLOS[15:0] >= 2.
0:19
CBM: Bit vector of available L3 ways for CLOS 2 enforcement.
63:20
Reserved.
Register Address: C93H, 3219
IA32_L3_QOS_MASK_3
L3 Class Of Service Mask - CLOS 3 (R/W)
Package
If CPUID.10H.01H:EDX.CAT_MAX_CLOS[15:0] >= 3.
0:19
CBM: Bit vector of available L3 ways for CLOS 3 enforcement.
63:20
Reserved.
Register Address: C94H, 3220
IA32_L3_QOS_MASK_4
L3 Class Of Service Mask - CLOS 4 (R/W)
Package
If CPUID.10H.01H:EDX.CAT_MAX_CLOS[15:0] >= 4.
0:19
CBM: Bit vector of available L3 ways for CLOS 4 enforcement.
63:20
Reserved.
Register Address: C95H, 3221
IA32_L3_QOS_MASK_5
L3 Class Of Service Mask - CLOS 5 (R/W)
Package
If CPUID.10H.01H:EDX.CAT_MAX_CLOS[15:0] >= 5.
0:19
CBM: Bit vector of available L3 ways for CLOS 5 enforcement.
2-346 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family
Based on Broadwell Microarchitecture (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
63:20
Reserved.
Register Address: C96H, 3222
IA32_L3_QOS_MASK_6
L3 Class Of Service Mask - CLOS 6 (R/W)
Package
If CPUID.10H.01H:EDX.CAT_MAX_CLOS[15:0] >= 6.
0:19
CBM: Bit vector of available L3 ways for CLOS 6 enforcement.
63:20
Reserved.
Register Address: C97H, 3223
IA32_L3_QOS_MASK_7
L3 Class Of Service Mask - CLOS 7 (R/W)
Package
If CPUID.10H.01H:EDX.CAT_MAX_CLOS[15:0] >= 7.
0:19
CBM: Bit vector of available L3 ways for CLOS 7 enforcement.
63:20
Reserved.
Register Address: C98H, 3224
IA32_L3_QOS_MASK_8
L3 Class Of Service Mask - CLOS 8 (R/W)
Package
If CPUID.10H.01H:EDX.CAT_MAX_CLOS[15:0] >= 8.
0:19
CBM: Bit vector of available L3 ways for CLOS 8 enforcement.
63:20
Reserved.
Register Address: C99H, 3225
IA32_L3_QOS_MASK_9
L3 Class Of Service Mask - CLOS 9 (R/W)
Package
If CPUID.10H.01H:EDX.CAT_MAX_CLOS[15:0] >= 9.
0:19
CBM: Bit vector of available L3 ways for CLOS 9 enforcement.
63:20
Reserved.
Register Address: C9AH, 3226
IA32_L3_QOS_MASK_10
L3 Class Of Service Mask - CLOS 10 (R/W)
Package
If CPUID.10H.01H:EDX.CAT_MAX_CLOS[15:0] >= 10.
0:19
CBM: Bit vector of available L3 ways for CLOS 10 enforcement.
63:20
Reserved.
Register Address: C9BH, 3227
IA32_L3_QOS_MASK_11
L3 Class Of Service Mask - CLOS 11 (R/W)
Package
If CPUID.10H.01H:EDX.CAT_MAX_CLOS[15:0] >= 11.
0:19
CBM: Bit vector of available L3 ways for CLOS 11 enforcement.
63:20
Reserved.
Register Address: C9CH, 3228
IA32_L3_QOS_MASK_12
L3 Class Of Service Mask - CLOS 12 (R/W)
Package
If CPUID.10H.01H:EDX.CAT_MAX_CLOS[15:0] >= 12.
0:19
CBM: Bit vector of available L3 ways for CLOS 12 enforcement.
63:20
Reserved.
Register Address: C9DH, 3229
IA32_L3_QOS_MASK_13
Vol. 4
2-347
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family
Based on Broadwell Microarchitecture (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
L3 Class Of Service Mask - CLOS 13 (R/W)
Package
If CPUID.10H.01H:EDX.CAT_MAX_CLOS[15:0] >= 13.
0:19
CBM: Bit vector of available L3 ways for CLOS 13 enforcement.
63:20
Reserved.
Register Address: C9EH, 3230
IA32_L3_QOS_MASK_14
L3 Class Of Service Mask - CLOS 14 (R/W)
Package
If CPUID.10H.01H:EDX.CAT_MAX_CLOS[15:0] >= 14.
0:19
CBM: Bit vector of available L3 ways for CLOS 14 enforcement.
63:20
Reserved.
Register Address: C9FH, 3231
IA32_L3_QOS_MASK_15
L3 Class Of Service Mask - CLOS 15 (R/W)
Package
If CPUID.10H.01H:EDX.CAT_MAX_CLOS[15:0] >= 15.
0:19
CBM: Bit vector of available L3 ways for CLOS 15 enforcement.
63:20
Reserved.
2.16.1 Additional MSRs Supported in the Intel® Xeon® Processor D Product Family
The MSRs listed in Table 2-37 are available to Intel® Xeon® Processor D Product Family (CPUID Signature
DisplayFamily_DisplayModel value of 06_56H). The Intel® Xeon® processor D product family is based on Broadwell
microarchitecture and supports the MSR interfaces listed in Table 2-20, Table 2-29, Table 2-34, Table 2-36, and
Table 2-37.
Table 2-37. Additional MSRs Supported by Intel® Xeon® Processor D with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_56H
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 1ACH, 428
MSR_TURBO_RATIO_LIMIT3
Config Ratio Limit of Turbo Mode
Package
R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1.
62:0
Reserved.
Package
63
Semaphore for Turbo Ratio Limit Configuration
Package
If 1, the processor uses override configuration1 specified in
MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1.
If 0, the processor uses factory-set configuration (Default).
Register Address: 286H, 646
IA32_MC6_CTL2
See Table 2-2.
Package
Register Address: 287H, 647
IA32_MC7_CTL2
See Table 2-2.
Package
Register Address: 289H, 649
IA32_MC9_CTL2
See Table 2-2.
Package
2-348 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-37. Additional MSRs Supported by Intel® Xeon® Processor D with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_56H
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 28AH, 650
IA32_MC10_CTL2
See Table 2-2.
Package
Register Address: 291H, 657
IA32_MC17_CTL2
See Table 2-2.
Package
Register Address: 292H, 658
IA32_MC18_CTL2
See Table 2-2.
Package
Register Address: 293H, 659
IA32_MC19_CTL2
See Table 2-2.
Package
Register Address: 418H, 1048
IA32_MC6_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC6 reports MC errors from the integrated I/O module.
Register Address: 419H, 1049
IA32_MC6_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC6 reports MC errors from the integrated I/O module.
Register Address: 41AH, 1050
IA32_MC6_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC6 reports MC errors from the integrated I/O module.
Register Address: 41BH, 1051
IA32_MC6_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC6 reports MC errors from the integrated I/O module.
Register Address: 41CH, 1052
IA32_MC7_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC7 reports MC errors from the home agent HA 0.
Register Address: 41DH, 1053
IA32_MC7_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC7 reports MC errors from the home agent HA 0.
Register Address: 41EH, 1054
IA32_MC7_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC7 reports MC errors from the home agent HA 0.
Register Address: 41FH, 1055
IA32_MC7_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC7 reports MC errors from the home agent HA 0.
Register Address: 424H, 1060
IA32_MC9_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 10 report MC errors from each channel of the integrated memory controllers.
Register Address: 425H, 1061
IA32_MC9_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 10 report MC errors from each channel of the integrated memory controllers.
Vol. 4
2-349
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-37. Additional MSRs Supported by Intel® Xeon® Processor D with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_56H
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 426H, 1062
IA32_MC9_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 10 report MC errors from each channel of the integrated memory controllers.
Register Address: 427H, 1063
IA32_MC9_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 10 report MC errors from each channel of the integrated memory controllers.
Register Address: 428H, 1064
IA32_MC10_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 10 report MC errors from each channel of the integrated memory controllers.
Register Address: 429H, 1065
IA32_MC10_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 10 report MC errors from each channel of the integrated memory controllers.
Register Address: 42AH, 1066
IA32_MC10_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 10 report MC errors from each channel of the integrated memory controllers.
Register Address: 42BH, 1067
IA32_MC10_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 10 report MC errors from each channel of the integrated memory controllers.
Register Address: 444H, 1092
IA32_MC17_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Register Address: 445H, 1093
IA32_MC17_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Register Address: 446H, 1094
IA32_MC17_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Register Address: 447H, 1095
IA32_MC17_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Register Address: 448H, 1096
IA32_MC18_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
Register Address: 449H, 1097
IA32_MC18_STATUS
2-350 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-37. Additional MSRs Supported by Intel® Xeon® Processor D with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_56H
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
Register Address: 44AH, 1098
IA32_MC18_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
Register Address: 44BH, 1099
IA32_MC18_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
Register Address: 44CH, 1100
IA32_MC19_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
Register Address: 44DH, 1101
IA32_MC19_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
Register Address: 44EH, 1102
IA32_MC19_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
Register Address: 44FH, 1103
IA32_MC19_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
See Table 2-20, Table 2-29, Table 2-34, and Table 2-36 for other MSR definitions applicable to processors with a CPUID Signature
DisplayFamily_DisplayModel value of 06_56H.
NOTES:
1. An override configuration lower than the factory-set configuration is always supported. An override configuration higher than the
factory-set configuration is dependent on features specific to the processor and the platform.
2.16.2 Additional MSRs Supported in Intel® Xeon® Processors E5 v4 and E7 v4 Families
The MSRs listed in Table 2-37 are available to the Intel® Xeon® Processor E5 v4 and E7 v4 Families (CPUID
Signature DisplayFamily_DisplayModel value of 06_4FH). The Intel® Xeon® processor E5 v4 family is based on
Broadwell microarchitecture and supports the MSR interfaces listed in Table 2-20, Table 2-21, Table 2-29, Table
2-34, Table 2-36, and Table 2-38.
Vol. 4
2-351
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-38. Additional MSRs Supported by Intel® Xeon® Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_4FH
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 1ACH, 428
MSR_TURBO_RATIO_LIMIT3
Config Ratio Limit of Turbo Mode
Package
R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1.
62:0
Reserved.
Package
63
Semaphore for Turbo Ratio Limit Configuration
Package
If 1, the processor uses override configuration1 specified in
MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1, and
MSR_TURBO_RATIO_LIMIT2.
If 0, the processor uses factory-set configuration (Default).
Register Address: 285H, 645
IA32_MC5_CTL2
See Table 2-2.
Package
Register Address: 286H, 646
IA32_MC6_CTL2
See Table 2-2.
Package
Register Address: 287H, 647
IA32_MC7_CTL2
See Table 2-2.
Package
Register Address: 288H, 648
IA32_MC8_CTL2
See Table 2-2.
Package
Register Address: 289H, 649
IA32_MC9_CTL2
See Table 2-2.
Package
Register Address: 28AH, 650
IA32_MC10_CTL2
See Table 2-2.
Package
Register Address: 28BH, 651
IA32_MC11_CTL2
See Table 2-2.
Package
Register Address: 28CH, 652
IA32_MC12_CTL2
See Table 2-2.
Package
Register Address: 28DH, 653
IA32_MC13_CTL2
See Table 2-2.
Package
Register Address: 28EH, 654
IA32_MC14_CTL2
See Table 2-2.
Package
Register Address: 28FH, 655
IA32_MC15_CTL2
See Table 2-2.
Package
Register Address: 290H, 656
IA32_MC16_CTL2
See Table 2-2.
Package
Register Address: 291H, 657
IA32_MC17_CTL2
See Table 2-2.
Package
Register Address: 292H, 658
IA32_MC18_CTL2
See Table 2-2.
Package
2-352 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-38. Additional MSRs Supported by Intel® Xeon® Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_4FH
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 293H, 659
IA32_MC19_CTL2
See Table 2-2.
Package
Register Address: 294H, 660
IA32_MC20_CTL2
See Table 2-2.
Package
Register Address: 295H, 661
IA32_MC21_CTL2
See Table 2-2.
Package
Register Address: 414H, 1044
IA32_MC5_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC5 reports MC errors from the Intel QPI 0 module.
Register Address: 415H, 1045
IA32_MC5_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC5 reports MC errors from the Intel QPI 0 module.
Register Address: 416H, 1046
IA32_MC5_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC5 reports MC errors from the Intel QPI 0 module.
Register Address: 417H, 1047
IA32_MC5_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC5 reports MC errors from the Intel QPI 0 module.
Register Address: 418H, 1048
IA32_MC6_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC6 reports MC errors from the integrated I/O module.
Register Address: 419H, 1049
IA32_MC6_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC6 reports MC errors from the integrated I/O module.
Register Address: 41AH, 1050
IA32_MC6_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC6 reports MC errors from the integrated I/O module.
Register Address: 41BH, 1051
IA32_MC6_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC6 reports MC errors from the integrated I/O module.
Register Address: 41CH, 1052
IA32_MC7_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC7 reports MC errors from the home agent HA 0.
Register Address: 41DH, 1053
IA32_MC7_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC7 reports MC errors from the home agent HA 0.
Register Address: 41EH, 1054
IA32_MC7_ADDR
Vol. 4
2-353
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-38. Additional MSRs Supported by Intel® Xeon® Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_4FH
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC7 reports MC errors from the home agent HA 0.
Register Address: 41FH, 1055
IA32_MC7_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC7 reports MC errors from the home agent HA 0.
Register Address: 420H, 1056
IA32_MC8_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC8 reports MC errors from the home agent HA 1.
Register Address: 421H, 1057
IA32_MC8_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC8 reports MC errors from the home agent HA 1.
Register Address: 422H, 1058
IA32_MC8_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC8 reports MC errors from the home agent HA 1.
Register Address: 423H, 1059
IA32_MC8_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC8 reports MC errors from the home agent HA 1.
Register Address: 424H, 1060
IA32_MC9_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 425H, 1061
IA32_MC9_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 426H, 1062
IA32_MC9_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 427H, 1063
IA32_MC9_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 428H, 1064
IA32_MC10_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 429H, 1065
IA32_MC10_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 42AH, 1066
IA32_MC10_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
2-354 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-38. Additional MSRs Supported by Intel® Xeon® Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_4FH
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 42BH, 1067
IA32_MC10_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 42CH, 1068
IA32_MC11_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 42DH, 1069
IA32_MC11_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 42EH, 1070
IA32_MC11_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 42FH, 1071
IA32_MC11_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 430H, 1072
IA32_MC12_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 431H, 1073
IA32_MC12_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 432H, 1074
IA32_MC12_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 433H, 1075
IA32_MC12_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 434H, 1076
IA32_MC13_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 435H, 1077
IA32_MC13_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 436H, 1078
IA32_MC13_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 437H, 1079
IA32_MC13_MISC
Vol. 4
2-355
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-38. Additional MSRs Supported by Intel® Xeon® Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_4FH
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 438H, 1080
IA32_MC14_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 439H, 1081
IA32_MC14_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 43AH, 1082
IA32_MC14_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 43BH, 1083
IA32_MC14_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 43CH, 1084
IA32_MC15_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 43DH, 1085
IA32_MC15_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 43EH, 1086
IA32_MC15_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 43FH, 1087
IA32_MC15_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 440H, 1088
IA32_MC16_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 441H, 1089
IA32_MC16_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 442H, 1090
IA32_MC16_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 443H, 1091
IA32_MC16_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
2-356 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-38. Additional MSRs Supported by Intel® Xeon® Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_4FH
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 444H, 1092
IA32_MC17_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Register Address: 445H, 1093
IA32_MC17_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Register Address: 446H, 1094
IA32_MC17_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Register Address: 447H, 1095
IA32_MC17_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Register Address: 448H, 1096
IA32_MC18_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
Register Address: 449H, 1097
IA32_MC18_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
Register Address: 44AH, 1098
IA32_MC18_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
Register Address: 44BH, 1099
IA32_MC18_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
Register Address: 44CH, 1100
IA32_MC19_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
Register Address: 44DH, 1101
IA32_MC19_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
Register Address: 44EH, 1102
IA32_MC19_ADDR
Vol. 4
2-357
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-38. Additional MSRs Supported by Intel® Xeon® Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_4FH
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
Register Address: 44FH, 1103
IA32_MC19_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
Register Address: 450H, 1104
IA32_MC20_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC20 reports MC errors from the Intel QPI 1 module.
Register Address: 451H, 1105
IA32_MC20_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC20 reports MC errors from the Intel QPI 1 module.
Register Address: 452H, 1106
IA32_MC20_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC20 reports MC errors from the Intel QPI 1 module.
Register Address: 453H, 1107
IA32_MC20_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC20 reports MC errors from the Intel QPI 1 module.
Register Address: 454H, 1108
IA32_MC21_CTL
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC21 reports MC errors from the Intel QPI 2 module.
Register Address: 455H, 1109
IA32_MC21_STATUS
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC21 reports MC errors from the Intel QPI 2 module.
Register Address: 456H, 1110
IA32_MC21_ADDR
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC21 reports MC errors from the Intel QPI 2 module.
Register Address: 457H, 1111
IA32_MC21_MISC
See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC21 reports MC errors from the Intel QPI 2 module.
Register Address: C81H, 3201
IA32_L3_QOS_CFG
Cache Allocation Technology Configuration (R/W)
Package
0
CAT Enable. Set 1 to enable Cache Allocation Technology.
63:1
Reserved.
See Table 2-20, Table 2-21, Table 2-29, and Table 2-30 for other MSR definitions applicable to processors with a CPUID Signature
DisplayFamily_DisplayModel value of 06_45H.
2-358 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
NOTES:
1. An override configuration lower than the factory-set configuration is always supported. An override configuration higher than the fac-
tory-set configuration is dependent on features specific to the processor and the platform.
2.17
MSRS IN THE 6TH-13TH GENERATION INTEL® CORE™ PROCESSORS,
1ST-5TH GENERATION INTEL® XEON® SCALABLE PROCESSOR FAMILIES,
INTEL® CORE™ ULTRA 7 PROCESSORS, 8TH GENERATION INTEL® CORE™ I3
PROCESSORS, INTEL® XEON® E PROCESSORS, INTEL® XEON® 6 P-CORE
PROCESSORS, INTEL® XEON® 6 E-CORE PROCESSORS, AND INTEL® SERIES 2
CORE™ ULTRA PROCESSORS
6th generation Intel® Core™ processors are based on Skylake microarchitecture and have a CPUID Signature
DisplayFamily_DisplayModel value of 06_4EH or 06_5EH.
The Intel® Xeon® Scalable Processor Family based on the Skylake microarchitecture, the 2nd generation Intel®
Xeon® Scalable Processor Family based on the Cascade Lake product, and the 3rd generation Intel® Xeon® Scal-
able Processor Family based on the Cooper Lake product all have a CPUID Signature DisplayFamily_DisplayModel
value of 06_55H.
7th generation Intel® Core™ processors are based on the Kaby Lake microarchitecture, 8th generation and 9th
generation Intel® Core™ processors, and Intel® Xeon® E processors are based on Coffee Lake microarchitecture;
these processors have a CPUID Signature DisplayFamily_DisplayModel value of 06_8EH or 06_9EH.
8th generation Intel® Core™ i3 processors are based on Cannon Lake microarchitecture and have a CPUID Signa-
ture DisplayFamily_DisplayModel value of 06_66H.
10th generation Intel® Core™ processors are based on Comet Lake microarchitecture (with a CPUID Signature
DisplayFamily_DisplayModel value of 06_A5H or 06_A6H) and Ice Lake microarchitecture (with a CPUID Signature
DisplayFamily_DisplayModel value of 06_7EH).
11th generation Intel® Core™ processors are based on Tiger Lake microarchitecture and have a CPUID Signature
DisplayFamily_DisplayModel value of 06_8CH or 06_8DH.
The 3rd generation Intel® Xeon® Scalable Processor Family is based on Ice Lake microarchitecture and has a
CPUID Signature DisplayFamily_DisplayModel value of 06_6AH or 06_6CH.
12th generation Intel® Core™ processors supporting the Alder Lake performance hybrid architecture have a CPUID
Signature DisplayFamily_DisplayModel value of 06_97H or 06_9AH.
13th generation Intel® Core™ processors supporting the Raptor Lake performance hybrid architecture have a
CPUID Signature DisplayFamily_DisplayModel value of 06_BAH, 06_B7H, or 06_BFH.
The 4th generation Intel® Xeon® Scalable Processor Family is based on Sapphire Rapids microarchitecture and has
a CPUID Signature DisplayFamily_DisplayModel value of 06_8FH.
The 5th generation Intel® Xeon® Scalable Processor Family is based on Emerald Rapids microarchitecture and has
a CPUID Signature DisplayFamily_DisplayModel value of 06_CFH.
The Intel® Core™ Ultra 7 processors supporting the Meteor Lake hybrid architecture have a CPUID Signature
DisplayFamily_DisplayModel value of 06_AAH.
The Intel® Xeon® 6 P-core processor is based on the Granite Rapids microarchitecture and has a CPUID Signature
DisplayFamily_DisplayModel value of 06_ADH or 06_AEH.
The Intel® Xeon® 6 E-core processor is based on the Sierra Forest microarchitecture and has a CPUID Signature
DisplayFamily_DisplayModel value of 06_AFH.
The Intel® Series 2 Core™ Ultra processors supporting the Lunar Lake performance hybrid architecture have a
CPUID Signature DisplayFamily_DisplayModel value of 06_BDH.
Vol. 4
2-359
MODEL-SPECIFIC REGISTERS (MSRS)
These processors support the MSR interfaces listed in Table 2-20, Table 2-21, Table 2-25, Table 2-29, Table 2-35,
and Table 2-391. For an MSR listed in Table 2-39 that also appears in the model-specific tables of prior generations,
Table 2-39 supersedes prior generation tables.
Tables 2-40 through 2-60 list additional supported MSR interfaces introduced in specific processors; see each table
for additional details.
The notation of “Platform” in the Scope column (with respect to MSR_PLATFORM_ENERGY_COUNTER and
MSR_PLATFORM_POWER_LIMIT) is limited to the power-delivery domain and the specifics of the power delivery
integration may vary by platform vendor’s implementation.
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors,
1st-5th Generation Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors,
8th Generation Intel® Core™ i3 Processors, Intel® Xeon® E Processors, Intel® Xeon® 6 E-Core Processors,
Intel® Xeon® 6 P-Core Processors, and Intel® Series 2 Core™ Ultra Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 3AH, 58
IA32_FEATURE_CONTROL
Control Features in Intel 64 Processor (R/W)
Thread
See Table 2-2.
Register Address: FEH, 254
IA32_MTRRCAP
MTRR Capability (R/O, Architectural)
Thread
See Table 2-2
Register Address: 19CH, 412
IA32_THERM_STATUS
Thermal Monitor Status (R/W)
Core
See Table 2-2.
0
Thermal Status (R/O)
See Table 2-2.
1
Thermal Status Log (R/WC0)
See Table 2-2.
2
PROTCHOT # or FORCEPR# Status (R/O)
See Table 2-2.
3
PROTCHOT # or FORCEPR# Log (R/WC0)
See Table 2-2.
4
Critical Temperature Status (R/O)
See Table 2-2.
5
Critical Temperature Status Log (R/WC0)
See Table 2-2.
6
Thermal threshold #1 Status (R/O)
See Table 2-2.
7
Thermal threshold #1 Log (R/WC0)
See Table 2-2.
8
Thermal Threshold #2 Status (R/O)
See Table 2-2.
1. MSRs at the following addresses are not supported in the 12th generation Intel Core processor E-core: 3F7H. MSRs at the following
addresses are not supported in the 12th generation Intel Core processor E-core or P-core: 652H, 653H, 655H, 656H, DB0H, DB1H,
DB2H, and D90H.
2-360 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors,
1st-5th Generation Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors,
8th Generation Intel® Core™ i3 Processors, Intel® Xeon® E Processors, Intel® Xeon® 6 E-Core Processors,
Intel® Xeon® 6 P-Core Processors, and Intel® Series 2 Core™ Ultra Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
9
Thermal Threshold #2 Log (R/WC0)
See Table 2-2.
10
Power Limitation Status (R/O)
See Table 2-2.
11
Power Limitation Log (R/WC0)
See Table 2-2.
12
Current Limit Status (R/O)
See Table 2-2.
13
Current Limit Log (R/WC0)
See Table 2-2.
14
Cross Domain Limit Status (R/O)
See Table 2-2.
15
Cross Domain Limit Log (R/WC0)
See Table 2-2.
22:16
Digital Readout (R/O)
See Table 2-2.
26:23
Reserved.
30:27
Resolution in Degrees Celsius (R/O)
See Table 2-2.
31
Reading Valid (R/O)
See Table 2-2.
63:32
Reserved.
Register Address: 1ADH, 429
MSR_TURBO_RATIO_LIMIT
Maximum Ratio Limit of Turbo Mode
Package
R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1
7:0
Maximum Ratio Limit for 1C
Package
Maximum turbo ratio limit of 1 core active.
15:8
Maximum Ratio Limit for 2C
Package
Maximum turbo ratio limit of 2 core active.
23:16
Maximum Ratio Limit for 3C
Package
Maximum turbo ratio limit of 3 core active.
31:24
Maximum Ratio Limit for 4C
Package
Maximum turbo ratio limit of 4 core active.
63:32
Reserved.
Register Address: 1C9H, 457
MSR_LASTBRANCH_TOS
Last Branch Record Stack TOS (R/W)
Thread
Contains an index (bits 0-4) that points to the MSR containing the most recent branch record.
Vol. 4
2-361
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors,
1st-5th Generation Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors,
8th Generation Intel® Core™ i3 Processors, Intel® Xeon® E Processors, Intel® Xeon® 6 E-Core Processors,
Intel® Xeon® 6 P-Core Processors, and Intel® Series 2 Core™ Ultra Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 1FCH, 508
MSR_POWER_CTL
Power Control Register
Core
See http://biosbits.org.
0
Reserved.
1
C1E Enable (R/W)
Package
When set to ‘1’, will enable the CPU to switch to the Minimum Enhanced
Intel SpeedStep Technology operating point when all execution cores enter
MWAIT (C1).
18:2
Reserved.
19
Disable Energy Efficiency Optimization (R/W)
Setting this bit disables the P-States energy efficiency optimization.
Default value is 0. Disable/enable the energy efficiency optimization in P-
State legacy mode (when IA32_PM_ENABLE[HWP_ENABLE] = 0), has an
effect only in the turbo range or into PERF_MIN_CTL value if it is not zero
set. In HWP mode (IA32_PM_ENABLE[HWP_ENABLE] == 1), has an effect
between the OS desired or OS maximize to the OS minimize performance
setting.
20
Disable Race to Halt Optimization (R/W)
Setting this bit disables the Race to Halt optimization and avoids this
optimization limitation to execute below the most efficient frequency ratio.
Default value is 0 for processors that support Race to Halt optimization.
63:21
Reserved.
Register Address: 300H, 768
MSR_SGXOWNEREPOCH0
Lower 64 Bit CR_SGXOWNEREPOCH (W)
Package
Writes do not update CR_SGXOWNEREPOCH if CPUID.12H.00H:EAX.SGX1 is 1 on any thread in the package.
63:0
Lower 64 bits of an 128-bit external entropy value for key derivation of an
enclave.
Register Address: 301H, 769
MSR_SGXOWNEREPOCH1
Upper 64 Bit CR_SGXOWNEREPOCH (W)
Package
Writes do not update CR_SGXOWNEREPOCH if CPUID.12H.00H:EAX.SGX1 is 1 on any thread in the package.
63:0
Upper 64 bits of an 128-bit external entropy value for key derivation of an
enclave.
Register Address: 38EH, 910
IA32_PERF_GLOBAL_STATUS
See Table 2-2 and Section 22.2.4, “Architectural Performance Monitoring Version 4.”
0
Ovf_PMC0
Thread
1
Ovf_PMC1
Thread
2
Ovf_PMC2
Thread
3
Ovf_PMC3
Thread
4
Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4)
Thread
5
Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5)
Thread
2-362 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors,
1st-5th Generation Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors,
8th Generation Intel® Core™ i3 Processors, Intel® Xeon® E Processors, Intel® Xeon® 6 E-Core Processors,
Intel® Xeon® 6 P-Core Processors, and Intel® Series 2 Core™ Ultra Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
6
Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6)
Thread
7
Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7)
Thread
31:8
Reserved.
32
Ovf_FixedCtr0
Thread
33
Ovf_FixedCtr1
Thread
34
Ovf_FixedCtr2
Thread
54:35
Reserved
55
Trace_ToPA_PMI
Thread
57:56
Reserved.
58
LBR_Frz
Thread
59
CTR_Frz
Thread
60
ASCI
Thread
61
Ovf_Uncore
Thread
62
Ovf_BufDSSAVE
Thread
63
CondChgd
Thread
Register Address: 390H, 912
IA32_PERF_GLOBAL_STATUS_RESET
See Table 2-2 and Section 22.2.4, “Architectural Performance Monitoring Version 4.”
0
Set 1 to clear Ovf_PMC0.
Thread
1
Set 1 to clear Ovf_PMC1.
Thread
2
Set 1 to clear Ovf_PMC2.
Thread
3
Set 1 to clear Ovf_PMC3.
Thread
4
Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
Thread
5
Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
Thread
6
Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
Thread
7
Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
Thread
31:8
Reserved.
32
Set 1 to clear Ovf_FixedCtr0.
Thread
33
Set 1 to clear Ovf_FixedCtr1.
Thread
34
Set 1 to clear Ovf_FixedCtr2.
Thread
54:35
Reserved.
55
Set 1 to clear Trace_ToPA_PMI.
Thread
57:56
Reserved.
58
Set 1 to clear LBR_Frz.
Thread
59
Set 1 to clear CTR_Frz.
Thread
60
Set 1 to clear ASCI.
Thread
Vol. 4
2-363
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors,
1st-5th Generation Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors,
8th Generation Intel® Core™ i3 Processors, Intel® Xeon® E Processors, Intel® Xeon® 6 E-Core Processors,
Intel® Xeon® 6 P-Core Processors, and Intel® Series 2 Core™ Ultra Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
61
Set 1 to clear Ovf_Uncore.
Thread
62
Set 1 to clear Ovf_BufDSSAVE.
Thread
63
Set 1 to clear CondChgd.
Thread
Register Address: 391H, 913
IA32_PERF_GLOBAL_STATUS_SET
See Table 2-2 and Section 22.2.4, “Architectural Performance Monitoring Version 4.”
0
Set 1 to cause Ovf_PMC0 = 1.
Thread
1
Set 1 to cause Ovf_PMC1 = 1.
Thread
2
Set 1 to cause Ovf_PMC2 = 1.
Thread
3
Set 1 to cause Ovf_PMC3 = 1.
Thread
4
Set 1 to cause Ovf_PMC4 =1 (if CPUID.0AH:EAX[15:8] > 4).
Thread
5
Set 1 to cause Ovf_PMC5 =1 (if CPUID.0AH:EAX[15:8] > 5).
Thread
6
Set 1 to cause Ovf_PMC6 =1 (if CPUID.0AH:EAX[15:8] > 6).
Thread
7
Set 1 to cause Ovf_PMC7 =1 (if CPUID.0AH:EAX[15:8] > 7).
Thread
31:8
Reserved.
32
Set 1 to cause Ovf_FixedCtr0 = 1.
Thread
33
Set 1 to cause Ovf_FixedCtr1 = 1.
Thread
34
Set 1 to cause Ovf_FixedCtr2 = 1.
Thread
54:35
Reserved.
55
Set 1 to cause Trace_ToPA_PMI = 1.
Thread
57:56
Reserved.
58
Set 1 to cause LBR_Frz = 1.
Thread
59
Set 1 to cause CTR_Frz = 1.
Thread
60
Set 1 to cause ASCI = 1.
Thread
61
Set 1 to cause Ovf_Uncore.
Thread
62
Set 1 to cause Ovf_BufDSSAVE.
Thread
63
Reserved.
Register Address: 392H, 914
IA32_PERF_GLOBAL_INUSE
See Table 2-2.
Thread
Register Address: 3F7H, 1015
MSR_PEBS_FRONTEND
FrontEnd Precise Event Condition Select (R/W)
Thread
2:0
Event Code Select
3
Reserved
4
Event Code Select High
7:5
Reserved.
19:8
IDQ_Bubble_Length Specifier
2-364 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors,
1st-5th Generation Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors,
8th Generation Intel® Core™ i3 Processors, Intel® Xeon® E Processors, Intel® Xeon® 6 E-Core Processors,
Intel® Xeon® 6 P-Core Processors, and Intel® Series 2 Core™ Ultra Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
22:20
IDQ_Bubble_Width Specifier
63:23
Reserved.
Register Address: 500H, 1280
IA32_SGX_SVN_STATUS
Status and SVN Threshold of SGX Support for ACM (R/O)
Thread
0
Lock
See Section 42.11.3, “Interactions with Authenticated Code Modules
(ACMs).”
15:1
Reserved.
23:16
SGX_SVN_SINIT
See Section 42.11.3, “Interactions with Authenticated Code Modules
(ACMs).”
63:24
Reserved.
Register Address: 560H, 1376
IA32_RTIT_OUTPUT_BASE
Trace Output Base Register (R/W)
Thread
See Table 2-2.
Register Address: 561H, 1377
IA32_RTIT_OUTPUT_MASK_PTRS
Trace Output Mask Pointers Register (R/W)
Thread
See Table 2-2.
Register Address: 570H, 1392
IA32_RTIT_CTL
Trace Control Register (R/W)
Thread
0
TraceEn
1
CYCEn
2
OS
3
User
6:4
Reserved, must be zero.
7
CR3Filter
8
ToPA
Writing 0 will #GP if also setting TraceEn.
9
MTCEn
10
TSCEn
11
DisRETC
12
Reserved, must be zero.
13
BranchEn
17:14
MTCFreq
18
Reserved, must be zero.
22:19
CycThresh
Vol. 4
2-365
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors,
1st-5th Generation Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors,
8th Generation Intel® Core™ i3 Processors, Intel® Xeon® E Processors, Intel® Xeon® 6 E-Core Processors,
Intel® Xeon® 6 P-Core Processors, and Intel® Series 2 Core™ Ultra Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
23
Reserved, must be zero.
27:24
PSBFreq
31:28
Reserved, must be zero.
35:32
ADDR0_CFG
39:36
ADDR1_CFG
63:40
Reserved, must be zero.
Register Address: 571H, 1393
IA32_RTIT_STATUS
Tracing Status Register (R/W)
Thread
0
FilterEn, writes ignored.
1
ContexEn, writes ignored.
2
TriggerEn, writes ignored.
3
Reserved
4
Error (R/W)
5
Stopped
31:6
Reserved, must be zero.
48:32
PacketByteCnt
63:49
Reserved, must be zero.
Register Address: 572H, 1394
IA32_RTIT_CR3_MATCH
Trace Filter CR3 Match Register (R/W)
Thread
4:0
Reserved
63:5
CR3[63:5] value to match
Register Address: 580H, 1408
IA32_RTIT_ADDR0_A
Region 0 Start Address (R/W)
Thread
63:0
See Table 2-2.
Register Address: 581H, 1409
IA32_RTIT_ADDR0_B
Region 0 End Address (R/W)
Thread
63:0
See Table 2-2.
Register Address: 582H, 1410
IA32_RTIT_ADDR1_A
Region 1 Start Address (R/W)
Thread
63:0
See Table 2-2.
Register Address: 583H, 1411
IA32_RTIT_ADDR1_B
Region 1 End Address (R/W)
Thread
63:0
See Table 2-2.
Register Address: 639H, 1593
MSR_PP0_ENERGY_STATUS
2-366 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors,
1st-5th Generation Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors,
8th Generation Intel® Core™ i3 Processors, Intel® Xeon® E Processors, Intel® Xeon® 6 E-Core Processors,
Intel® Xeon® 6 P-Core Processors, and Intel® Series 2 Core™ Ultra Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
PP0 Energy Status (R/O)
Package
See Section 17.10.4, “PP0/PP1 RAPL Domains.”
Register Address: 64DH, 1613
MSR_PLATFORM_ENERGY_COUNTER
Platform Energy Counter (R/O)
Platform
This MSR is valid only if both platform vendor hardware implementation and BIOS enablement support it. This MSR
will read 0 if not valid.
31:0
Total energy consumed by all devices in the platform that receive power
from integrated power delivery mechanism, included platform devices are
processor cores, SOC, memory, add-on or peripheral devices that get
powered directly from the platform power delivery means. The energy
units are specified in the MSR_RAPL_POWER_UNIT.Enery_Status_Unit.
63:32
Reserved.
Register Address: 64EH, 1614
MSR_PPERF
Productive Performance Count (R/O)
Thread
63:0
Hardware’s view of workload scalability. See Section 17.4.5.1.
Register Address: 64FH, 1615
MSR_CORE_PERF_LIMIT_REASONS
Indicator of Frequency Clipping in Processor Cores (R/W)
Package
(Frequency refers to processor core frequency.)
0
PROCHOT Status (R0)
When set, frequency is reduced below the operating system request due
to assertion of external PROCHOT.
1
Thermal Status (R0)
When set, frequency is reduced below the operating system request due
to a thermal event.
3:2
Reserved.
4
Residency State Regulation Status (R0)
When set, frequency is reduced below the operating system request due
to residency state regulation limit.
5
Running Average Thermal Limit Status (R0)
When set, frequency is reduced below the operating system request due
to Running Average Thermal Limit (RATL).
6
VR Therm Alert Status (R0)
When set, frequency is reduced below the operating system request due
to a thermal alert from a processor Voltage Regulator (VR).
7
VR Therm Design Current Status (R0)
When set, frequency is reduced below the operating system request due
to VR thermal design current limit.
8
Other Status (R0)
When set, frequency is reduced below the operating system request due
to electrical or other constraints.
Vol. 4
2-367
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors,
1st-5th Generation Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors,
8th Generation Intel® Core™ i3 Processors, Intel® Xeon® E Processors, Intel® Xeon® 6 E-Core Processors,
Intel® Xeon® 6 P-Core Processors, and Intel® Series 2 Core™ Ultra Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
9
Reserved.
10
Package/Platform-Level Power Limiting PL1 Status (R0)
When set, frequency is reduced below the operating system request due
to package/platform-level power limiting PL1.
11
Package/Platform-Level PL2 Power Limiting Status (R0)
When set, frequency is reduced below the operating system request due
to package/platform-level power limiting PL2/PL3.
12
Max Turbo Limit Status (R0)
When set, frequency is reduced below the operating system request due
to multi-core turbo limits.
13
Turbo Transition Attenuation Status (R0)
When set, frequency is reduced below the operating system request due
to Turbo transition attenuation. This prevents performance degradation
due to frequent operating ratio changes.
15:14
Reserved.
16
PROCHOT Log
When set, indicates that the PROCHOT Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
17
Thermal Log
When set, indicates that the Thermal Status bit has asserted since the log
bit was last cleared.
This log bit will remain set until cleared by software writing 0.
19:18
Reserved.
20
Residency State Regulation Log
When set, indicates that the Residency State Regulation Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
21
Running Average Thermal Limit Log
When set, indicates that the RATL Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software writing 0.
22
VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
23
VR Thermal Design Current Log
When set, indicates that the VR TDC Status bit has asserted since the log
bit was last cleared.
This log bit will remain set until cleared by software writing 0.
2-368 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors,
1st-5th Generation Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors,
8th Generation Intel® Core™ i3 Processors, Intel® Xeon® E Processors, Intel® Xeon® 6 E-Core Processors,
Intel® Xeon® 6 P-Core Processors, and Intel® Series 2 Core™ Ultra Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
24
Other Log
When set, indicates that the Other Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software writing 0.
25
Reserved.
26
Package/Platform-Level PL1 Power Limiting Log
When set, indicates that the Package or Platform Level PL1 Power Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
27
Package/Platform-Level PL2 Power Limiting Log
When set, indicates that the Package or Platform Level PL2/PL3 Power
Limiting Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
28
Max Turbo Limit Log
When set, indicates that the Max Turbo Limit Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
29
Turbo Transition Attenuation Log
When set, indicates that the Turbo Transition Attenuation Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
63:30
Reserved.
Register Address: 652H, 1618
MSR_PKG_HDC_CONFIG
HDC Configuration (R/W)
Package
2:0
PKG_Cx_Monitor
Configures Package Cx state threshold for
MSR_PKG_HDC_DEEP_RESIDENCY.
63: 3
Reserved.
Register Address: 653H, 1619
MSR_CORE_HDC_RESIDENCY
Core HDC Idle Residency (R/O)
Core
63:0
Core_Cx_Duty_Cycle_Cnt
Register Address: 655H, 1621
MSR_PKG_HDC_SHALLOW_RESIDENCY
Accumulate the cycles the package was in C2 state and at least one logical processor was in forced idle (R/O)
Package
63:0
Pkg_C2_Duty_Cycle_Cnt
Register Address: 656H, 1622
MSR_PKG_HDC_DEEP_RESIDENCY
Package Cx HDC Idle Residency (R/O)
Package
63:0
Pkg_Cx_Duty_Cycle_Cnt
Register Address: 658H, 1624
MSR_WEIGHTED_CORE_C0
Vol. 4
2-369
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors,
1st-5th Generation Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors,
8th Generation Intel® Core™ i3 Processors, Intel® Xeon® E Processors, Intel® Xeon® 6 E-Core Processors,
Intel® Xeon® 6 P-Core Processors, and Intel® Series 2 Core™ Ultra Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Core-count Weighted C0 Residency (R/O)
Package
63:0
Increment at the same rate as the TSC. The increment each cycle is
weighted by the number of processor cores in the package that reside in
C0. If N cores are simultaneously in C0, then each cycle the counter
increments by N.
Register Address: 659H, 1625
MSR_ANY_CORE_C0
Any Core C0 Residency (R/O)
Package
63:0
Increment at the same rate as the TSC. The increment each cycle is one if
any processor core in the package is in C0.
Register Address: 65AH, 1626
MSR_ANY_GFXE_C0
Any Graphics Engine C0 Residency (R/O)
Package
63:0
Increment at the same rate as the TSC. The increment each cycle is one if
any processor graphic device’s compute engines are in C0.
Register Address: 65BH, 1627
MSR_CORE_GFXE_OVERLAP_C0
Core and Graphics Engine Overlapped C0 Residency (R/O)
Package
63:0
Increment at the same rate as the TSC. The increment each cycle is one if
at least one compute engine of the processor graphics is in C0 and at least
one processor core in the package is also in C0.
Register Address: 65CH, 1628
MSR_PLATFORM_POWER_LIMIT
Platform Power Limit Control (R/W-L)
Platform
Allows platform BIOS to limit power consumption of the platform devices to the specified values. The Long Duration
power consumption is specified via Platform_Power_Limit_1 and Platform_Power_Limit_1_Time. The Short Duration
power consumption limit is specified via the Platform_Power_Limit_2 with duration chosen by the processor.
The processor implements an exponential-weighted algorithm in the placement of the time windows.
Note that the bit field widths differ depending on the platform.
MSR_PLATFORM_POWER_LIMIT for 4th and 5th generation Intel® Xeon® Scalable Processor Families, Intel® Xeon® 6 E-
Core Processors, and Intel® Xeon 6 P-core Processors
16:0
Platform Power Limit #1
Average Power limit value which the platform must not exceed over a time
window as specified by Power_Limit_1_TIME field.
The default value is the Thermal Design Power (TDP) and varies with
product skus. The unit is specified in MSR_RAPLPOWER_UNIT.
17
Enable Platform Power Limit #1
When set, enables the processor to apply control policy such that the
platform power does not exceed Platform Power limit #1 over the time
window specified by Power Limit #1 Time Window.
18
Platform Clamping Limitation #1
When set, allows the processor to go below the OS requested P states in
order to maintain the power below specified Platform Power Limit #1
value.
This bit is writeable only when CPUID.06H:EAX[4] is set.
2-370 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors,
1st-5th Generation Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors,
8th Generation Intel® Core™ i3 Processors, Intel® Xeon® E Processors, Intel® Xeon® 6 E-Core Processors,
Intel® Xeon® 6 P-Core Processors, and Intel® Series 2 Core™ Ultra Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
25:19
Time Window for Platform Power Limit #1
Specifies the duration of the time window over which Platform Power
Limit 1 value should be maintained for sustained long duration. This field is
made up of two numbers from the following equation:
Time Window = (float) ((1+(X/4))*(2^Y)), where:
X = POWER_LIMIT_1_TIME[25:24]
Y = POWER_LIMIT_1_TIME[23:19]
The maximum allowed value in this field is defined in
MSR_PKG_POWER_INFO[PKG_MAX_WIN].
The default value is 0DH, and the unit is specified in
MSR_RAPL_POWER_UNIT[Time Unit].
31:26
Reserved.
48:32
Platform Power Limit #2
Average Power limit value which the platform must not exceed over the
Short Duration time window chosen by the processor.
The recommended default value is 1.25 times the Long Duration Power
Limit (i.e., Platform Power Limit # 1).
49
Enable Platform Power Limit #2
When set, enables the processor to apply control policy such that the
platform power does not exceed Platform Power limit #2 over the Short
Duration time window.
50
Platform Clamping Limitation #2
When set, allows the processor to go below the OS requested P states in
order to maintain the power below specified Platform Power Limit #2
value.
62:51
Reserved.
63
Lock. Setting this bit will lock all other bits of this MSR until system RESET.
MSR_PLATFORM_POWER_LIMIT for 6th-13th Generation Intel® Core™ Processors, 1st-3rd Generation Intel® Xeon®
Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors, Intel® Xeon® E
Processors, and Intel® Series 2 Core™ Ultra Processors
14:0
Platform Power Limit #1
Average Power limit value which the platform must not exceed over a time
window as specified by Power_Limit_1_TIME field.
The default value is the Thermal Design Power (TDP) and varies with
product skus. The unit is specified in MSR_RAPLPOWER_UNIT.
15
Enable Platform Power Limit #1
When set, enables the processor to apply control policy such that the
platform power does not exceed Platform Power limit #1 over the time
window specified by Power Limit #1 Time Window.
Vol. 4
2-371

 

 

 

 

 

 

 

Content      ..     72      73      74      75     ..