Content      ..     70      71      72      73     ..

Intel 64 and IA-32 Architectures. Software Developer’s Manual (2026) - page 72

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Last Branch Record 17 To IP (R/W)

Core

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6D2H, 1746

MSR_LASTBRANCH_18_TO_IP

Last Branch Record 18 To IP (R/W)

Core

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6D3H, 1747

MSR_LASTBRANCH_19_TO_IP

Last Branch Record 19To IP (R/W)

Core

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6D4H, 1748

MSR_LASTBRANCH_20_TO_IP

Last Branch Record 20 To IP (R/W)

Core

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6D5H, 1749

MSR_LASTBRANCH_21_TO_IP

Last Branch Record 21 To IP (R/W)

Core

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6D6H, 1750

MSR_LASTBRANCH_22_TO_IP

Last Branch Record 22 To IP (R/W)

Core

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6D7H, 1751

MSR_LASTBRANCH_23_TO_IP

Last Branch Record 23 To IP (R/W)

Core

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6D8H, 1752

MSR_LASTBRANCH_24_TO_IP

Last Branch Record 24 To IP (R/W)

Core

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6D9H, 1753

MSR_LASTBRANCH_25_TO_IP

Last Branch Record 25 To IP (R/W)

Core

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6DAH, 1754

MSR_LASTBRANCH_26_TO_IP

Last Branch Record 26 To IP (R/W)

Core

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6DBH, 1755

MSR_LASTBRANCH_27_TO_IP

Last Branch Record 27 To IP (R/W)

Core

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6DCH, 1756

MSR_LASTBRANCH_28_TO_IP

Last Branch Record 28 To IP (R/W)

Core

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6DDH, 1757

MSR_LASTBRANCH_29_TO_IP

Last Branch Record 29 To IP (R/W)

Core

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6DEH, 1758

MSR_LASTBRANCH_30_TO_IP

2-166 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Register Address: D13H, 3347

IA32_L2_QOS_MASK_3

L2 Class Of Service Mask - CLOS 3 (R/W)

Package

If CPUID.10H.01H:EDX.CAT_MAX_CLOS[15:0] >= 3.

0:19

CBM: Bit vector of available L2 ways for CLOS 3 enforcement.

63:20

Reserved.

Register Address: D90H, 3472

IA32_BNDCFGS

See Table 2-2.

Core

Register Address: DA0H, 3488

IA32_XSS

See Table 2-2.

Core

See Table 2-6, and Table 2-12 for MSR definitions applicable to processors with a CPUID Signature DisplayFamily_DisplayModel value

of 06_5CH.

2.6

MSRS IN INTEL ATOM® PROCESSORS BASED ON GOLDMONT PLUS

MICROARCHITECTURE

Intel Atom processors based on the Goldmont Plus microarchitecture support MSRs listed in Table 2-6, Table 2-12,

and Table 2-13. These processors have a CPUID Signature DisplayFamily_DisplayModel value of 06_7AH; see Table

2-1. For an MSR listed in Table 2-13 that also appears in the model-specific tables of prior generations, Table 2-13

supersedes prior generation tables.

In the Goldmont Plus microarchitecture, the scope column indicates the following: “Core” means each processor

core has a separate MSR, or a bit field not shared with another processor core. “Module” means the MSR or the bit

field is shared by a subset of the processor cores in the physical package. The number of processor cores in this

subset is model specific and may differ between different processors. For all processors based on Goldmont Plus

microarchitecture, the L2 cache is also shared between cores in a module and thus CPUID.04H enumeration can be

used to figure out which processors are in the same module. “Package” means all processor cores in the physical

package share the same MSR or bit interface.

Table 2-13. MSRs in Intel Atom® Processors Based on Goldmont Plus Microarchitecture

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Register Address: 3AH, 58

IA32_FEATURE_CONTROL

Control Features in Intel 64Processor (R/W)

Core

See Table 2-2.

0

Lock (R/WL)

1

Enable VMX inside SMX operation (R/WL)

2

Enable VMX outside SMX operation (R/WL)

14:8

SENTER local functions enables (R/WL)

15

SENTER global functions enable (R/WL)

17

SGX Launch Control Enable (R/WL)

This bit must be set to enable runtime reconfiguration of SGX Launch

Control via IA32_SGXLEPUBKEYHASHn MSR.

Valid if CPUID.07H.00H:ECX[30] = 1.

2-170 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-13. MSRs in Intel Atom® Processors Based on Goldmont Plus Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

18

SGX global functions enable (R/WL)

63:19

Reserved.

Register Address: 8CH, 140

IA32_SGXLEPUBKEYHASH0

See Table 2-2.

Core

Register Address: 8DH, 141

IA32_SGXLEPUBKEYHASH1

See Table 2-2.

Core

Register Address: 8EH, 142

IA32_SGXLEPUBKEYHASH2

See Table 2-2.

Core

Register Address: 8FH, 143

IA32_SGXLEPUBKEYHASH3

See Table 2-2.

Core

Register Address: 3F1H, 1009

IA32_PEBS_ENABLE (MSR_PEBS_ENABLE)

(R/W) See Table 2-2. See Section 22.6.2.4, “Processor Event Based Sampling (PEBS).”

Core

0

Enable PEBS trigger and recording for the programmed event (precise or

otherwise) on IA32_PMC0.

1

Enable PEBS trigger and recording for the programmed event (precise or

otherwise) on IA32_PMC1.

2

Enable PEBS trigger and recording for the programmed event (precise or

otherwise) on IA32_PMC2.

3

Enable PEBS trigger and recording for the programmed event (precise or

otherwise) on IA32_PMC3.

31:4

Reserved.

32

Enable PEBS trigger and recording for IA32_FIXED_CTR0.

33

Enable PEBS trigger and recording for IA32_FIXED_CTR1.

34

Enable PEBS trigger and recording for IA32_FIXED_CTR2.

63:35

Reserved.

Register Address: 570H, 1392

IA32_RTIT_CTL

Trace Control Register (R/W)

Core

0

TraceEn

1

CYCEn

2

OS

3

User

4

PwrEvtEn

5

FUPonPTW

6

FabricEn

7

CR3Filter

8

ToPA

Writing 0 will #GP if also setting TraceEn.

9

MTCEn

10

TSCEn

Vol. 4

2-171

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-13. MSRs in Intel Atom® Processors Based on Goldmont Plus Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

11

DisRETC

12

PTWEn

13

BranchEn

17:14

MTCFreq

18

Reserved, must be zero.

22:19

CycThresh

23

Reserved, must be zero.

27:24

PSBFreq

31:28

Reserved, must be zero.

35:32

ADDR0_CFG

39:36

ADDR1_CFG

63:40

Reserved, must be zero.

Register Address: 680H, 1664

MSR_LASTBRANCH_0_FROM_IP

Last Branch Record 0 From IP (R/W)

Core

One of the three MSRs that make up the first entry of the 32-entry LBR stack. The From_IP part of the stack contains

pointers to the source instruction. See also:

• Last Branch Record Stack TOS at 1C9H.

• Section 20.7, “Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Goldmont Plus

Microarchitecture.”

Register Address: 681H-69FH, 1665-

MSR_LASTBRANCH_i_FROM_IP

1695

Last Branch Record i From IP (R/W)

Core

See description of MSR_LASTBRANCH_0_FROM_IP; i = 1-31.

Register Address: 6C0H, 1728

MSR_LASTBRANCH_0_TO_IP

Last Branch Record 0 To IP (R/W)

Core

One of the three MSRs that make up the first entry of the 32-entry LBR stack. The To_IP part of the stack contains

pointers to the Destination instruction. See also:

• Section 20.7, “Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Goldmont Plus

Microarchitecture.”

Register Address: 6C1H-6DFH, 1729-

MSR_LASTBRANCH_i_TO_IP

1759

Last Branch Record i To IP (R/W)

Core

See description of MSR_LASTBRANCH_0_TO_IP; i = 1-31.

Register Address: DC0H, 3520

MSR_LASTBRANCH_INFO_0

Last Branch Record 0 Additional Information (R/W)

Core

One of the three MSRs that make up the first entry of the 32-entry LBR stack. This part of the stack contains flag and

elapsed cycle information. See also:

• Last Branch Record Stack TOS at 1C9H.

• Section 20.9.1, “LBR Stack.”

Register Address: DC1H, 3521

MSR_LASTBRANCH_INFO_1

Last Branch Record 1 Additional Information (R/W)

Core

See description of MSR_LASTBRANCH_INFO_0.

2-172 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-13. MSRs in Intel Atom® Processors Based on Goldmont Plus Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Register Address: DC2H, 3522

MSR_LASTBRANCH_INFO_2

Last Branch Record 2 Additional Information (R/W)

Core

See description of MSR_LASTBRANCH_INFO_0.

Register Address: DC3H, 3523

MSR_LASTBRANCH_INFO_3

Last Branch Record 3 Additional Information (R/W)

Core

See description of MSR_LASTBRANCH_INFO_0.

Register Address: DC4H, 3524

MSR_LASTBRANCH_INFO_4

Last Branch Record 4 Additional Information (R/W)

Core

See description of MSR_LASTBRANCH_INFO_0.

Register Address: DC5H, 3525

MSR_LASTBRANCH_INFO_5

Last Branch Record 5 Additional Information (R/W)

Core

See description of MSR_LASTBRANCH_INFO_0.

Register Address: DC6H, 3526

MSR_LASTBRANCH_INFO_6

Last Branch Record 6 Additional Information (R/W)

Core

See description of MSR_LASTBRANCH_INFO_0.

Register Address: DC7H, 3527

MSR_LASTBRANCH_INFO_7

Last Branch Record 7 Additional Information (R/W)

Core

See description of MSR_LASTBRANCH_INFO_0.

Register Address: DC8H, 3528

MSR_LASTBRANCH_INFO_8

Last Branch Record 8 Additional Information (R/W)

Core

See description of MSR_LASTBRANCH_INFO_0.

Register Address: DC9H, 3529

MSR_LASTBRANCH_INFO_9

Last Branch Record 9 Additional Information (R/W)

Core

See description of MSR_LASTBRANCH_INFO_0.

Register Address: DCAH, 3530

MSR_LASTBRANCH_INFO_10

Last Branch Record 10 Additional Information (R/W)

Core

See description of MSR_LASTBRANCH_INFO_0.

Register Address: DCBH, 3531

MSR_LASTBRANCH_INFO_11

Last Branch Record 11 Additional Information (R/W)

Core

See description of MSR_LASTBRANCH_INFO_0.

Register Address: DCCH, 3532

MSR_LASTBRANCH_INFO_12

Last Branch Record 12 Additional Information (R/W)

Core

See description of MSR_LASTBRANCH_INFO_0.

Register Address: DCDH, 3533

MSR_LASTBRANCH_INFO_13

Last Branch Record 13 Additional Information (R/W)

Core

See description of MSR_LASTBRANCH_INFO_0.

Register Address: DCEH, 3534

MSR_LASTBRANCH_INFO_14

Last Branch Record 14 Additional Information (R/W)

Core

See description of MSR_LASTBRANCH_INFO_0.

Vol. 4

2-173

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-13. MSRs in Intel Atom® Processors Based on Goldmont Plus Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Register Address: DCFH, 3535

MSR_LASTBRANCH_INFO_15

Last Branch Record 15 Additional Information (R/W)

Core

See description of MSR_LASTBRANCH_INFO_0.

Register Address: DD0H, 3536

MSR_LASTBRANCH_INFO_16

Last Branch Record 16 Additional Information (R/W)

Core

See description of MSR_LASTBRANCH_INFO_0.

Register Address: DD1H, 3537

MSR_LASTBRANCH_INFO_17

Last Branch Record 17 Additional Information (R/W)

Core

See description of MSR_LASTBRANCH_INFO_0.

Register Address: DD2H, 3538

MSR_LASTBRANCH_INFO_18

Last Branch Record 18 Additional Information (R/W)

Core

See description of MSR_LASTBRANCH_INFO_0.

Register Address: DD3H, 3539

MSR_LASTBRANCH_INFO_19

Last Branch Record 19 Additional Information (R/W)

Core

See description of MSR_LASTBRANCH_INFO_0.

Register Address: DD4H, 3520

MSR_LASTBRANCH_INFO_20

Last Branch Record 20 Additional Information (R/W)

Core

See description of MSR_LASTBRANCH_INFO_0.

Register Address: DD5H, 3521

MSR_LASTBRANCH_INFO_21

Last Branch Record 21 Additional Information (R/W)

Core

See description of MSR_LASTBRANCH_INFO_0.

Register Address: DD6H, 3522

MSR_LASTBRANCH_INFO_22

Last Branch Record 22 Additional Information (R/W)

Core

See description of MSR_LASTBRANCH_INFO_0.

Register Address: DD7H, 3523

MSR_LASTBRANCH_INFO_23

Last Branch Record 23 Additional Information (R/W)

Core

See description of MSR_LASTBRANCH_INFO_0.

Register Address: DD8H, 3524

MSR_LASTBRANCH_INFO_24

Last Branch Record 24 Additional Information (R/W)

Core

See description of MSR_LASTBRANCH_INFO_0.

Register Address: DD9H, 3525

MSR_LASTBRANCH_INFO_25

Last Branch Record 25 Additional Information (R/W)

Core

See description of MSR_LASTBRANCH_INFO_0.

Register Address: DDAH, 3526

MSR_LASTBRANCH_INFO_26

Last Branch Record 26 Additional Information (R/W)

Core

See description of MSR_LASTBRANCH_INFO_0.

Register Address: DDBH, 3527

MSR_LASTBRANCH_INFO_27

Last Branch Record 27 Additional Information (R/W)

Core

See description of MSR_LASTBRANCH_INFO_0.

2-174 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-13. MSRs in Intel Atom® Processors Based on Goldmont Plus Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Register Address: DDCH, 3528

MSR_LASTBRANCH_INFO_28

Last Branch Record 28 Additional Information (R/W)

Core

See description of MSR_LASTBRANCH_INFO_0.

Register Address: DDDH, 3529

MSR_LASTBRANCH_INFO_29

Last Branch Record 29 Additional Information (R/W)

Core

See description of MSR_LASTBRANCH_INFO_0.

Register Address: DDEH, 3530

MSR_LASTBRANCH_INFO_30

Last Branch Record 30 Additional Information (R/W)

Core

See description of MSR_LASTBRANCH_INFO_0.

Register Address: DDFH, 3531

MSR_LASTBRANCH_INFO_31

Last Branch Record 31 Additional Information (R/W)

Core

See description of MSR_LASTBRANCH_INFO_0.

See Table 2-6, Table 2-12, and Table 2-13 for MSR definitions applicable to processors with a CPUID Signature

DisplayFamily_DisplayModel value of 06_7AH.

2.7

MSRS IN INTEL ATOM® PROCESSORS BASED ON TREMONT

MICROARCHITECTURE

Processors based on the Tremont microarchitecture support MSRs listed in Table 2-6, Table 2-12, Table 2-13, and

Table 2-14. These processors have a CPUID Signature DisplayFamily_DisplayModel value of 06_86H, 06_96H, or

06_9CH; see Table 2-1. For an MSR listed in Table 2-14 that also appears in the model-specific tables of prior

generations, Table 2-14 supersedes prior generation tables.

In the Tremont microarchitecture, the scope column indicates the following: “Core” means each processor core has

a separate MSR, or a bit field not shared with another processor core. “Module” means the MSR or the bit field is

shared by a subset of the processor cores in the physical package. The number of processor cores in this subset is

model specific and may differ between different processors. For all processors based on Tremont microarchitecture,

the L2 cache is also shared between cores in a module and thus CPUID.04H enumeration can be used to figure out

which processors are in the same module. “Package” means all processor cores in the physical package share the

same MSR or bit interface.

Table 2-14. MSRs in Intel Atom® Processors Based on Tremont Microarchitecture

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Register Address: 33H, 51

MSR_MEMORY_CTRL

Memory Control Register

Core

28:0

Reserved.

29

SPLIT_LOCK_DISABLE

If set to 1, a split lock will cause an #AC(0) exception.

See Section 11.1.2.3, “Features to Disable Bus Locks.”

30

Reserved.

31

Reserved.

Register Address: CFH, 207

IA32_CORE_CAPABILITIES

Vol. 4

2-175

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-14. MSRs in Intel Atom® Processors Based on Tremont Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

IA32 Core Capabilities Register

Core

If CPUID.07H.00H:EDX[30] = 1.

4:0

Reserved.

5

SPLIT_LOCK_DISABLE_SUPPORTED

When read as 1, software can set bit 29 of MSR_MEMORY_CTRL (MSR

address 33H).

63:6

Reserved.

Register Address: 2A0H, 672

MSR_PRMRR_BASE_0

Processor Reserved Memory Range Register - Physical Base Control Register (R/W)

Core

2:0

MEMTYPE: PRMRR BASE Memory Type.

3

CONFIGURED: PRMRR BASE Configured.

11:4

Reserved.

51:12

BASE: PRMRR Base Address.

63:52

Reserved.

Register Address: 3F1H, 1009

IA32_PEBS_ENABLE (MSR_PEBS_ENABLE)

(R/W) See Table 2-2. See Section 22.6.2.4, “Processor Event Based Sampling (PEBS).”

Core

n:0

Enable PEBS trigger and recording for the programmed event (precise or

otherwise) on IA32_PMCx. The maximum value n can be determined from

CPUID.0AH:EAX[15:8].

31:n+1

Reserved.

32+m:32

Enable PEBS trigger and recording for IA32_FIXED_CTRx. The maximum

value m can be determined from CPUID.0AH:EDX[4:0].

59:33+m

Reserved.

60

Pend a PerfMon Interrupt (PMI) after each PEBS event.

62:61

Specifies PEBS output destination. Encodings:

00B: DS Save Area.

01B: Intel PT trace output. Supported if

IA32_PERF_CAPABILITIES.PEBS_OUTPUT_PT_AVAIL[16] and

CPUID.07H.00H:EBX[25] are set.

10B: Reserved.

11B: Reserved.

63

Reserved.

Register Address: 1309H-130BH,

MSR_RELOAD_FIXED_CTRx

4873-4875

Reload value for IA32_FIXED_CTRx (R/W)

47:0

Value loaded into IA32_FIXED_CTRx when a PEBS record is generated

while PEBS_EN_FIXEDx = 1 and PEBS_OUTPUT = 01B in

IA32_PEBS_ENABLE, and FIXED_CTRx is overflowed.

63:48

Reserved.

Register Address: 14C1H-14C4H,

MSR_RELOAD_PMCx

5313-5316

2-176 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-14. MSRs in Intel Atom® Processors Based on Tremont Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Reload value for IA32_PMCx (R/W)

Core

47:0

Value loaded into IA32_PMCx when a PEBS record is generated while

PEBS_EN_PMCx = 1 and PEBS_OUTPUT = 01B in IA32_PEBS_ENABLE,

and PMCx is overflowed.

63:48

Reserved.

See Table 2-6, Table 2-12, Table 2-13, and Table 2-14 for MSR definitions applicable to processors with a CPUID Signature

DisplayFamily_DisplayModel value of 06_86H.

2.8

MSRS IN PROCESSORS BASED ON NEHALEM MICROARCHITECTURE

Table 2-15 lists model-specific registers (MSRs) that are common for Nehalem microarchitecture. These include the

Intel Core i7 and i5 processor family. These processors have a CPUID Signature DisplayFamily_DisplayModel value

of 06_1AH, 06_1EH, 06_1FH, or 06_2EH; see Table 2-1. Additional MSRs specific to processors with a CPUID

Signature DisplayFamily_DisplayModel value of 06_1AH, 06_1EH, or 06_1FH are listed in Table 2-16. Some MSRs

listed in these tables are used by BIOS. More information about these MSR can be found at http://biosbits.org.

The column “Scope” represents the package/core/thread scope of individual bit field of an MSR. “Thread” means

this bit field must be programmed on each logical processor independently. “Core” means the bit field must be

programmed on each processor core independently, logical processors in the same core will be affected by change

of this bit on the other logical processor in the same core. “Package” means the bit field must be programmed once

for each physical package. Change of a bit filed with a package scope will affect all logical processors in that phys-

ical package.

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Register Address: 0H, 0

IA32_P5_MC_ADDR

See Section 2.23, “MSRs in Pentium Processors.”

Thread

Register Address: 1H, 1

IA32_P5_MC_TYPE

See Section 2.23, “MSRs in Pentium Processors.”

Thread

Register Address: 6H, 6

IA32_MONITOR_FILTER_SIZE

See Section 11.10.5, “Monitor/Mwait Address Range Determination,” and Table 2-2.

Thread

Register Address: 10H, 16

IA32_TIME_STAMP_COUNTER

See Section 20.17, “Time-Stamp Counter,” and Table 2-2.

Thread

Register Address: 17H, 23

IA32_PLATFORM_ID

Platform ID (R)

Package

See Table 2-2.

Register Address: 17H, 23

MSR_PLATFORM_ID

Model Specific Platform ID (R)

Package

49:0

Reserved.

52:50

See Table 2-2.

63:53

Reserved.

Register Address: 1BH, 27

IA32_APIC_BASE

Vol. 4

2-177

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

See Section 13.4.4, “Local APIC Status and Location,” and Table 2-2.

Thread

Register Address: 34H, 52

MSR_SMI_COUNT

SMI Counter (R/O)

Thread

31:0

SMI Count (R/O)

Running count of SMI events since last RESET.

63:32

Reserved.

Register Address: 3AH, 58

IA32_FEATURE_CONTROL

Control Features in Intel 64Processor (R/W)

Thread

See Table 2-2.

Register Address: 79H, 121

IA32_BIOS_UPDT_TRIG

BIOS Update Trigger Register (W)

Core

See Table 2-2.

Register Address: 8BH, 139

IA32_BIOS_SIGN_ID

BIOS Update Signature ID (R/W)

Thread

See Table 2-2.

Register Address: C1H, 193

IA32_PMC0

Performance Counter Register

Thread

See Table 2-2.

Register Address: C2H, 194

IA32_PMC1

Performance Counter Register

Thread

See Table 2-2.

Register Address: C3H, 195

IA32_PMC2

Performance Counter Register

Thread

See Table 2-2.

Register Address: C4H, 196

IA32_PMC3

Performance Counter Register

Thread

See Table 2-2.

Register Address: CEH, 206

MSR_PLATFORM_INFO

Platform Information

Package

Contains power management and other model specific features enumeration. See http://biosbits.org.

7:0

Reserved.

15:8

Maximum Non-Turbo Ratio (R/O)

Package

This is the ratio of the frequency that invariant TSC runs at. The invariant

TSC frequency can be computed by multiplying this ratio by 133.33 MHz.

27:16

Reserved.

28

Programmable Ratio Limit for Turbo Mode (R/O)

Package

When set to 1, indicates that Programmable Ratio Limit for Turbo mode is

enabled. When set to 0, indicates Programmable Ratio Limit for Turbo

mode is disabled.

2-178 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

29

Programmable TDC-TDP Limit for Turbo Mode (R/O)

Package

When set to 1, indicates that TDC and TDP Limits for Turbo mode are

programmable. When set to 0, indicates TDC and TDP Limits for Turbo

mode are not programmable.

39:30

Reserved.

47:40

Maximum Efficiency Ratio (R/O)

Package

This is the minimum ratio (maximum efficiency) that the processor can

operate, in units of 133.33MHz.

63:48

Reserved.

Register Address: E2H, 226

MSR_PKG_CST_CONFIG_CONTROL

C-State Configuration Control (R/W)

Core

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

ACPI C-States. See http://biosbits.org.

2:0

Package C-State Limit (R/W)

Specifies the lowest processor-specific C-state code name (consuming the

least power) for the package. The default is set as factory-configured

package C-state limit.

The following C-state code name encodings are supported:

000b: C0 (no package C-sate support)

001b: C1 (Behavior is the same as 000b)

010b: C3

011b: C6

100b: C7

101b and 110b: Reserved

111: No package C-state limit.

Note: This field cannot be used to limit package C-state to C3.

9:3

Reserved.

10

I/O MWAIT Redirection Enable (R/W)

When set, will map IO_read instructions sent to IO register specified by

MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.

14:11

Reserved.

15

CFG Lock (R/WO)

When set, locks bits 15:0 of this register until next reset.

23:16

Reserved.

24

Interrupt filtering enable (R/W)

When set, processor cores in a deep C-State will wake only when the event

message is destined for that core. When 0, all processor cores in a deep C-

State will wake for an event message.

25

C3 state auto demotion enable (R/W)

When set, the processor will conditionally demote C6/C7 requests to C3

based on uncore auto-demote information.

Vol. 4

2-179

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

26

C1 state auto demotion enable (R/W)

When set, the processor will conditionally demote C3/C6/C7 requests to C1

based on uncore auto-demote information.

27

Enable C3 Undemotion (R/W)

28

Enable C1 Undemotion (R/W)

29

Package C State Demotion Enable (R/W)

30

Package C State Undemotion Enable (R/W)

63:31

Reserved.

Register Address: E4H, 228

MSR_PMG_IO_CAPTURE_BASE

Power Management IO Redirection in C-state (R/W)

Core

See http://biosbits.org.

15:0

LVL_2 Base Address (R/W)

Specifies the base address visible to software for IO redirection. If IO

MWAIT Redirection is enabled, reads to this address will be consumed by

the power management logic and decoded to MWAIT instructions. When IO

port address redirection is enabled, this is the IO port address reported to

the OS/software.

18:16

C-state Range (R/W)

Specifies the encoding value of the maximum C-State code name to be

included when IO read to MWAIT redirection is enabled by

MSR_PKG_CST_CONFIG_CONTROL[bit 10]:

000b - C3 is the max C-State to include.

001b - C6 is the max C-State to include.

010b - C7 is the max C-State to include.

63:19

Reserved.

Register Address: E7H, 231

IA32_MPERF

Maximum Performance Frequency Clock Count (R/W)

Thread

See Table 2-2.

Register Address: E8H, 232

IA32_APERF

Actual Performance Frequency Clock Count (R/W)

Thread

See Table 2-2.

Register Address: FEH, 254

IA32_MTRRCAP

See Table 2-2.

Thread

Register Address: 174H, 372

IA32_SYSENTER_CS

See Table 2-2.

Thread

Register Address: 175H, 373

IA32_SYSENTER_ESP

See Table 2-2.

Thread

Register Address: 176H, 374

IA32_SYSENTER_EIP

See Table 2-2.

Thread

Register Address: 179H, 377

IA32_MCG_CAP

See Table 2-2.

Thread

2-180 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Register Address: 17AH, 378

IA32_MCG_STATUS

Global Machine Check Status

Thread

0

RIPV

When set, bit indicates that the instruction addressed by the instruction

pointer pushed on the stack (when the machine check was generated) can

be used to restart the program. If cleared, the program cannot be reliably

restarted.

1

EIPV

When set, bit indicates that the instruction addressed by the instruction

pointer pushed on the stack (when the machine check was generated) is

directly associated with the error.

2

MCIP

When set, bit indicates that a machine check has been generated. If a

second machine check is detected while this bit is still set, the processor

enters a shutdown state. Software should write this bit to 0 after

processing a machine check exception.

63:3

Reserved.

Register Address: 186H, 390

IA32_PERFEVTSEL0

See Table 2-2.

Thread

7:0

Event Select

15:8

UMask

16

USR

17

OS

18

Edge

19

PC

20

INT

21

AnyThread

22

EN

23

INV

31:24

CMASK

63:32

Reserved.

Register Address: 187H, 391

IA32_PERFEVTSEL1

See Table 2-2.

Thread

Register Address: 188H, 392

IA32_PERFEVTSEL2

See Table 2-2.

Thread

Register Address: 189H, 393

IA32_PERFEVTSEL3

See Table 2-2.

Thread

Register Address: 198H, 408

IA32_PERF_STATUS

See Table 2-2.

Core

15:0

Current Performance State Value.

Vol. 4

2-181

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

63:16

Reserved.

Register Address: 199H, 409

IA32_PERF_CTL

See Table 2-2.

Thread

Register Address: 19AH, 410

IA32_CLOCK_MODULATION

Clock Modulation (R/W)

Thread

See Table 2-2.

IA32_CLOCK_MODULATION MSR was originally named IA32_THERM_CONTROL MSR.

0

Reserved.

3:1

On demand Clock Modulation Duty Cycle (R/W)

4

On demand Clock Modulation Enable (R/W)

63:5

Reserved.

Register Address: 19BH, 411

IA32_THERM_INTERRUPT

Thermal Interrupt Control (R/W)

Core

See Table 2-2.

Register Address: 19CH, 412

IA32_THERM_STATUS

Thermal Monitor Status (R/W)

Core

See Table 2-2.

Register Address: 1A0H, 416

IA32_MISC_ENABLE

Enable Misc. Processor Features (R/W)

Allows a variety of processor functions to be enabled and disabled.

0

Fast-Strings Enable

Thread

See Table 2-2.

2:1

Reserved.

3

Automatic Thermal Control Circuit Enable (R/W)

Thread

See Table 2-2. Default value is 1.

6:4

Reserved.

7

Performance Monitoring Available (R)

Thread

See Table 2-2.

10:8

Reserved.

11

Branch Trace Storage Unavailable (R/O)

Thread

See Table 2-2.

12

Processor Event Based Sampling Unavailable (R/O)

Thread

See Table 2-2.

15:13

Reserved.

16

Enhanced Intel SpeedStep Technology Enable (R/W)

Package

See Table 2-2.

18

ENABLE MONITOR FSM. (R/W) See Table 2-2.

Thread

21:19

Reserved.

2-182 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

22

Limit CPUID Maxval (R/W)

Thread

See Table 2-2.

23

xTPR Message Disable (R/W)

Thread

See Table 2-2.

33:24

Reserved.

34

XD Bit Disable (R/W)

Thread

See Table 2-3.

37:35

Reserved.

38

Turbo Mode Disable (R/W)

Package

When set to 1 on processors that support Intel Turbo Boost Technology,

the turbo mode feature is disabled and the IDA_Enable feature flag will be

clear (CPUID.06H:EAX[1] =0).

When set to a 0 on processors that support IDA, CPUID.06H:EAX[1] reports

the processor’s support of turbo mode is enabled.

Note: The power-on default value is used by BIOS to detect hardware

support of turbo mode. If the power-on default value is 1, turbo mode is

available in the processor. If the power-on default value is 0, turbo mode is

not available.

63:39

Reserved.

Register Address: 1A2H, 418

MSR_TEMPERATURE_TARGET

Temperature Target

Thread

15:0

Reserved.

23:16

Temperature Target (R)

The minimum temperature at which PROCHOT# will be asserted. The value

is degrees C.

63:24

Reserved.

Register Address: 1A4H, 420

MSR_MISC_FEATURE_CONTROL

Miscellaneous Feature Control (R/W)

0

L2 Hardware Prefetcher Disable (R/W)

Core

If 1, disables the L2 hardware prefetcher, which fetches additional lines of

code or data into the L2 cache.

1

L2 Adjacent Cache Line Prefetcher Disable (R/W)

Core

If 1, disables the adjacent cache line prefetcher, which fetches the cache

line that comprises a cache line pair (128 bytes).

2

DCU Hardware Prefetcher Disable (R/W)

Core

If 1, disables the L1 data cache prefetcher, which fetches the next cache

line into L1 data cache.

3

DCU IP Prefetcher Disable (R/W)

Core

If 1, disables the L1 data cache IP prefetcher, which uses sequential load

history (based on instruction pointer of previous loads) to determine

whether to prefetch additional lines.

63:4

Reserved.

Register Address: 1A6H, 422

MSR_OFFCORE_RSP_0

Vol. 4

2-183

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Offcore Response Event Select Register (R/W)

Thread

Register Address: 1AAH, 426

MSR_MISC_PWR_MGMT

Miscellaneous Power Management Control

Various model specific features enumeration. See http://biosbits.org.

0

EIST Hardware Coordination Disable (R/W)

Package

When 0, enables hardware coordination of Enhanced Intel Speedstep

Technology request from processor cores. When 1, disables hardware

coordination of Enhanced Intel Speedstep Technology requests.

1

Energy/Performance Bias Enable (R/W)

Thread

This bit makes the IA32_ENERGY_PERF_BIAS register (MSR 1B0h) visible

to software with Ring 0 privileges. This bit’s status (1 or 0) is also reflected

by CPUID.06H:ECX[3].

63:2

Reserved.

Register Address: 1ACH, 428

MSR_TURBO_POWER_CURRENT_LIMIT

See http://biosbits.org.

14:0

TDP Limit (R/W)

Package

TDP limit in 1/8 Watt granularity.

15

TDP Limit Override Enable (R/W)

Package

A value = 0 indicates override is not active; a value = 1 indicates override is

active.

30:16

TDC Limit (R/W)

Package

TDC limit in 1/8 Amp granularity.

31

TDC Limit Override Enable (R/W)

Package

A value = 0 indicates override is not active; a value = 1 indicates override is

active.

63:32

Reserved.

Register Address: 1ADH, 429

MSR_TURBO_RATIO_LIMIT

Maximum Ratio Limit of Turbo Mode

Package

R/O if MSR_PLATFORM_INFO.[28] = 0.

R/W if MSR_PLATFORM_INFO.[28] = 1.

7:0

Maximum Ratio Limit for 1C

Package

Maximum turbo ratio limit of 1 core active.

15:8

Maximum Ratio Limit for 2C

Package

Maximum turbo ratio limit of 2 core active.

23:16

Maximum Ratio Limit for 3C

Package

Maximum turbo ratio limit of 3 core active.

31:24

Maximum Ratio Limit for 4C

Package

Maximum turbo ratio limit of 4 core active.

63:32

Reserved.

Register Address: 1C8H, 456

MSR_LBR_SELECT

2-184 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Last Branch Record Filtering Select Register (R/W)

Core

See Section 20.9.2, “Filtering of Last Branch Records.”

0

CPL_EQ_0

1

CPL_NEQ_0

2

JCC

3

NEAR_REL_CALL

4

NEAR_IND_CALL

5

NEAR_RET

6

NEAR_IND_JMP

7

NEAR_REL_JMP

8

FAR_BRANCH

63:9

Reserved.

Register Address: 1C9H, 457

MSR_LASTBRANCH_TOS

Last Branch Record Stack TOS (R/W)

Thread

Contains an index (bits 0-3) that points to the MSR containing the most recent branch record.

See MSR_LASTBRANCH_0_FROM_IP (at 680H).

Register Address: 1D9H, 473

IA32_DEBUGCTL

Debug Control (R/W)

Thread

See Table 2-2.

Register Address: 1DDH, 477

MSR_LER_FROM_LIP

Last Exception Record From Linear IP (R)

Thread

Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was

generated or the last interrupt that was handled.

Register Address: 1DEH, 478

MSR_LER_TO_LIP

Last Exception Record To Linear IP (R)

Thread

This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last

exception that was generated or the last interrupt that was handled.

Register Address: 1F2H, 498

IA32_SMRR_PHYSBASE

See Table 2-2.

Core

Register Address: 1F3H, 499

IA32_SMRR_PHYSMASK

See Table 2-2.

Core

Register Address: 1FCH, 508

MSR_POWER_CTL

Power Control Register

Core

See http://biosbits.org.

0

Reserved.

1

C1E Enable (R/W)

Package

When set to ‘1’, will enable the CPU to switch to the Minimum Enhanced

Intel SpeedStep Technology operating point when all execution cores enter

MWAIT (C1).

63:2

Reserved.

Vol. 4

2-185

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Register Address: 285H, 645

IA32_MC5_CTL2

See Table 2-2.

Core

Register Address: 286H, 646

IA32_MC6_CTL2

See Table 2-2.

Package

Register Address: 287H, 647

IA32_MC7_CTL2

See Table 2-2.

Package

Register Address: 288H, 648

IA32_MC8_CTL2

See Table 2-2.

Package

Register Address: 2FFH, 767

IA32_MTRR_DEF_TYPE

Default Memory Types (R/W)

Thread

See Table 2-2.

Register Address: 309H, 777

IA32_FIXED_CTR0

Fixed-Function Performance Counter Register 0 (R/W)

Thread

See Table 2-2.

Register Address: 30AH, 778

IA32_FIXED_CTR1

Fixed-Function Performance Counter Register 1 (R/W)

Thread

See Table 2-2.

Register Address: 30BH, 779

IA32_FIXED_CTR2

Fixed-Function Performance Counter Register 2 (R/W)

Thread

See Table 2-2.

Register Address: 345H, 837

IA32_PERF_CAPABILITIES

See Table 2-2. See Section 20.4.1, “IA32_DEBUGCTL MSR.”

Thread

5:0

LBR Format

See Table 2-2.

6

PEBS Record Format

7

PEBSSaveArchRegs

See Table 2-2.

11:8

PEBS_REC_FORMAT

See Table 2-2.

12

SMM_FREEZE

See Table 2-2.

63:13

Reserved.

Register Address: 38DH, 909

IA32_FIXED_CTR_CTRL

Fixed-Function-Counter Control Register (R/W)

Thread

See Table 2-2.

Register Address: 38EH, 910

IA32_PERF_GLOBAL_STATUS

See Table 2-2. See Section 22.6.2.2, “Global Counter Control Facilities.”

Thread

Register Address: 38EH, 910

MSR_PERF_GLOBAL_STATUS

Provides single-bit status used by software to query the overflow condition of each performance counter. (R/O)

Thread

2-188 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

61

UNC_Ovf

Uncore overflowed if 1.

Register Address: 38FH, 911

IA32_PERF_GLOBAL_CTRL

See Table 2-2. See Section 22.6.2.2, “Global Counter Control Facilities.”

Thread

Register Address: 390H, 912

IA32_PERF_GLOBAL_OVF_CTRL

See Table 2-2. See Section 22.6.2.2, “Global Counter Control Facilities.” Allows software to clear counter overflow

Thread

conditions on any combination of fixed-function PMCs (IA32_FIXED_CTRx) or general-purpose PMCs via a single

WRMSR.

Register Address: 390H, 912

MSR_PERF_GLOBAL_OVF_CTRL

(R/W)

Thread

61

CLR_UNC_Ovf

Set 1 to clear UNC_Ovf.

Register Address: 3F1H, 1009

IA32_PEBS_ENABLE (MSR_PEBS_ENABLE)

See Section 22.3.1.1.1, “Processor Event Based Sampling (PEBS).”

Thread

0

Enable PEBS on IA32_PMC0 (R/W)

1

Enable PEBS on IA32_PMC1 (R/W)

2

Enable PEBS on IA32_PMC2 (R/W)

3

Enable PEBS on IA32_PMC3 (R/W)

31:4

Reserved.

32

Enable Load Latency on IA32_PMC0 (R/W)

33

Enable Load Latency on IA32_PMC1 (R/W)

34

Enable Load Latency on IA32_PMC2 (R/W)

35

Enable Load Latency on IA32_PMC3 (R/W)

63:36

Reserved.

Register Address: 3F6H, 1014

MSR_PEBS_LD_LAT

See Section 22.3.1.1.2, “Load Latency Performance Monitoring Facility.”

Thread

15:0

Minimum threshold latency value of tagged load operation that will be

counted. (R/W)

63:36

Reserved.

Register Address: 3F8H, 1016

MSR_PKG_C3_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

Package

ACPI C-States.

63:0

Package C3 Residency Counter (R/O)

Value since last reset that this package is in processor-specific C3 states.

Count at the same frequency as the TSC.

Register Address: 3F9H, 1017

MSR_PKG_C6_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

Package

ACPI C-States.

Vol. 4

2-189

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

63:0

Package C6 Residency Counter (R/O)

Value since last reset that this package is in processor-specific C6 states.

Count at the same frequency as the TSC.

Register Address: 3FAH, 1018

MSR_PKG_C7_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

Package

ACPI C-States.

63:0

Package C7 Residency Counter (R/O)

Value since last reset that this package is in processor-specific C7 states.

Count at the same frequency as the TSC.

Register Address: 3FCH, 1020

MSR_CORE_C3_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

Core

ACPI C-States.

63:0

CORE C3 Residency Counter (R/O)

Value since last reset that this core is in processor-specific C3 states. Count

at the same frequency as the TSC.

Register Address: 3FDH, 1021

MSR_CORE_C6_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

Core

ACPI C-States.

63:0

CORE C6 Residency Counter (R/O)

Value since last reset that this core is in processor-specific C6 states. Count

at the same frequency as the TSC.

Register Address: 400H, 1024

IA32_MC0_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Package

Register Address: 401H, 1025

IA32_MC0_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

Package

Register Address: 402H, 1026

IA32_MC0_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

Package

The IA32_MC0_ADDR register is either not implemented or contains no address if the ADDRV flag in the

IA32_MC0_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

Register Address: 403H, 1027

IA32_MC0_MISC

See Section 18.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Register Address: 404H, 1028

IA32_MC1_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Package

Register Address: 405H, 1029

IA32_MC1_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

Package

Register Address: 406H, 1030

IA32_MC1_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

Package

The IA32_MC1_ADDR register is either not implemented or contains no address if the ADDRV flag in the

IA32_MC1_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

2-190 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Register Address: 407H, 1031

IA32_MC1_MISC

See Section 18.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Register Address: 408H, 1032

IA32_MC2_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Core

Register Address: 409H, 1033

IA32_MC2_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

Core

Register Address: 40AH, 1034

IA32_MC2_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

Core

The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in the

IA32_MC2_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

Register Address: 40BH, 1035

IA32_MC2_MISC

See Section 18.3.2.4, “IA32_MCi_MISC MSRs.”

Core

Register Address: 40CH, 1036

IA32_MC3_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Core

Register Address: 40DH, 1037

IA32_MC3_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

Core

Register Address: 40EH, 1038

IA32_MC3_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

Core

The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the

MSR_MC4_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

Register Address: 40FH, 1039

IA32_MC3_MISC

See Section 18.3.2.4, “IA32_MCi_MISC MSRs.”

Core

Register Address: 410H, 1040

IA32_MC4_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Core

Register Address: 411H, 1041

IA32_MC4_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

Core

Register Address: 412H, 1042

IA32_MC4_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

Core

The MSR_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in the

MSR_MC3_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

Register Address: 413H, 1043

IA32_MC4_MISC

See Section 18.3.2.4, “IA32_MCi_MISC MSRs.”

Core

Register Address: 414H, 1044

IA32_MC5_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Core

Register Address: 415H, 1045

IA32_MC5_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

Core

Vol. 4

2-191

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Capability Reporting Register of VM-Exit Controls (R/O)

Thread

See Table 2-2 and Appendix A.4, “VM-Exit Controls.”

Register Address: 484H, 1156

IA32_VMX_ENTRY_CTLS

Capability Reporting Register of VM-Entry Controls (R/O)

Thread

See Table 2-2 and Appendix A.5, “VM-Entry Controls.”

Register Address: 485H, 1157

IA32_VMX_MISC

Reporting Register of Miscellaneous VMX Capabilities (R/O)

Thread

See Table 2-2 and Appendix A.6, “Miscellaneous Data.”

Register Address: 486H, 1158

IA32_VMX_CR0_FIXED0

Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)

Thread

See Table 2-2 and Appendix A.7, “VMX-Fixed Bits in CR0.”

Register Address: 487H, 1159

IA32_VMX_CR0_FIXED1

Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)

Thread

See Table 2-2 and Appendix A.7, “VMX-Fixed Bits in CR0.”

Register Address: 488H, 1160

IA32_VMX_CR4_FIXED0

Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)

Thread

See Table 2-2 and Appendix A.8, “VMX-Fixed Bits in CR4.”

Register Address: 489H, 1161

IA32_VMX_CR4_FIXED1

Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)

Thread

See Table 2-2 and Appendix A.8, “VMX-Fixed Bits in CR4.”

Register Address: 48AH, 1162

IA32_VMX_VMCS_ENUM

Capability Reporting Register of VMCS Field Enumeration (R/O)

Thread

See Table 2-2 and Appendix A.9, “VMCS Enumeration.”

Register Address: 48BH, 1163

IA32_VMX_PROCBASED_CTLS2

Capability Reporting Register of Secondary Processor-Based VM-Execution Controls (R/O)

Thread

See Appendix A.3, “VM-Execution Controls.”

Register Address: 600H, 1536

IA32_DS_AREA

DS Save Area (R/W)

Thread

See Table 2-2 and Section 22.6.3.4, “Debug Store (DS) Mechanism.”

Register Address: 680H, 1664

MSR_LASTBRANCH_0_FROM_IP

Last Branch Record 0 From IP (R/W)

Thread

One of sixteen pairs of last branch record registers on the last branch record stack. The From_IP part of the stack

contains pointers to the source instruction. See also:

• Last Branch Record Stack TOS at 1C9H.

• See Section 20.9.1 and record format in Section 20.4.8.1.

Register Address: 681H, 1665

MSR_LASTBRANCH_1_FROM_IP

Last Branch Record 1 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

Register Address: 682H, 1666

MSR_LASTBRANCH_2_FROM_IP

Vol. 4

2-193

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Last Branch Record 2 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

Register Address: 683H, 1667

MSR_LASTBRANCH_3_FROM_IP

Last Branch Record 3 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

Register Address: 684H, 1668

MSR_LASTBRANCH_4_FROM_IP

Last Branch Record 4 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

Register Address: 685H, 1669

MSR_LASTBRANCH_5_FROM_IP

Last Branch Record 5 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

Register Address: 686H, 1670

MSR_LASTBRANCH_6_FROM_IP

Last Branch Record 6 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

Register Address: 687H, 1671

MSR_LASTBRANCH_7_FROM_IP

Last Branch Record 7 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

Register Address: 688H, 1672

MSR_LASTBRANCH_8_FROM_IP

Last Branch Record 8 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

Register Address: 689H, 1673

MSR_LASTBRANCH_9_FROM_IP

Last Branch Record 9 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

Register Address: 68AH, 1674

MSR_LASTBRANCH_10_FROM_IP

Last Branch Record 10 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

Register Address: 68BH, 1675

MSR_LASTBRANCH_11_FROM_IP

Last Branch Record 11 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

Register Address: 68CH, 1676

MSR_LASTBRANCH_12_FROM_IP

Last Branch Record 12 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

Register Address: 68DH, 1677

MSR_LASTBRANCH_13_FROM_IP

Last Branch Record 13 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

Register Address: 68EH, 1678

MSR_LASTBRANCH_14_FROM_IP

Last Branch Record 14 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

Register Address: 68FH, 1679

MSR_LASTBRANCH_15_FROM_IP

2-194 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Last Branch Record 15 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

Register Address: 6C0H, 1728

MSR_LASTBRANCH_0_TO_IP

Last Branch Record 0 To IP (R/W)

Thread

One of sixteen pairs of last branch record registers on the last branch record stack. This part of the stack contains

pointers to the destination instruction.

Register Address: 6C1H, 1729

MSR_LASTBRANCH_1_TO_IP

Last Branch Record 1 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6C2H, 1730

MSR_LASTBRANCH_2_TO_IP

Last Branch Record 2 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6C3H, 1731

MSR_LASTBRANCH_3_TO_IP

Last Branch Record 3 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6C4H, 1732

MSR_LASTBRANCH_4_TO_IP

Last Branch Record 4 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6C5H, 1733

MSR_LASTBRANCH_5_TO_IP

Last Branch Record 5 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6C6H, 1734

MSR_LASTBRANCH_6_TO_IP

Last Branch Record 6 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6C7H, 1735

MSR_LASTBRANCH_7_TO_IP

Last Branch Record 7 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6C8H, 1736

MSR_LASTBRANCH_8_TO_IP

Last Branch Record 8 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6C9H, 1737

MSR_LASTBRANCH_9_TO_IP

Last Branch Record 9 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6CAH, 1738

MSR_LASTBRANCH_10_TO_IP

Last Branch Record 10 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6CBH, 1739

MSR_LASTBRANCH_11_TO_IP

Last Branch Record 11 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

Vol. 4

2-195

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Map of BASE Address of FS (R/W)

Thread

See Table 2-2.

Register Address: C000_0101H

IA32_GS_BASE

Map of BASE Address of GS (R/W)

Thread

See Table 2-2.

Register Address: C000_0102H

IA32_KERNEL_GS_BASE

Swap Target of BASE Address of GS (R/W)

Thread

See Table 2-2.

Register Address: C000_0103H

IA32_TSC_AUX

AUXILIARY TSC Signature (R/W)

Thread

See Table 2-2 and Section 20.17.2, “IA32_TSC_AUX Register and RDTSCP Support.”

2.8.1

Additional MSRs in the Intel® Xeon® Processor 5500 and 3400 Series

The Intel Xeon Processor 5500 and 3400 series supports additional model-specific registers listed in Table 2-16.

These MSRs also apply to the Intel Core i7 and i5 processor family with a CPUID Signature

DisplayFamily_DisplayModel value of 06_1AH, 06_1EH, or 06_1FH; see Table 2-1.

Table 2-16. Additional MSRs in the Intel® Xeon® Processor 5500 and 3400 Series

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Register Address: 1ADH, 429

MSR_TURBO_RATIO_LIMIT

Actual maximum turbo frequency is multiplied by 133.33MHz.

Package

(Not available in model 06_2EH.)

7:0

Maximum Turbo Ratio Limit 1C (R/O)

Maximum Turbo mode ratio limit with 1 core active.

15:8

Maximum Turbo Ratio Limit 2C (R/O)

Maximum Turbo mode ratio limit with 2 cores active.

23:16

Maximum Turbo Ratio Limit 3C (R/O)

Maximum Turbo mode ratio limit with 3 cores active.

31:24

Maximum Turbo Ratio Limit 4C (R/O)

Maximum Turbo mode ratio limit with 4 cores active.

63:32

Reserved.

Register Address: 301H, 769

MSR_GQ_SNOOP_MESF

MSR_GQ_SNOOP_MESF

Package

0

From M to S (R/W)

1

From E to S (R/W)

2

From S to S (R/W)

3

From F to S (R/W)

4

From M to I (R/W)

Vol. 4

2-199

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-16. Additional MSRs in the Intel® Xeon® Processor 5500 and 3400 Series (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

See Section 22.3.1.2.2, “Uncore Performance Event Configuration Facility.”

Package

Register Address: 3C3H, 947

MSR_UNCORE_PERFEVTSEL3

See Section 22.3.1.2.2, “Uncore Performance Event Configuration Facility.”

Package

Register Address: 3C4H, 948

MSR_UNCORE_PERFEVTSEL4

See Section 22.3.1.2.2, “Uncore Performance Event Configuration Facility.”

Package

Register Address: 3C5H, 949

MSR_UNCORE_PERFEVTSEL5

See Section 22.3.1.2.2, “Uncore Performance Event Configuration Facility.”

Package

Register Address: 3C6H, 950

MSR_UNCORE_PERFEVTSEL6

See Section 22.3.1.2.2, “Uncore Performance Event Configuration Facility.”

Package

Register Address: 3C7H, 951

MSR_UNCORE_PERFEVTSEL7

See Section 22.3.1.2.2, “Uncore Performance Event Configuration Facility.”

Package

2.8.2

Additional MSRs in the Intel® Xeon® Processor 7500 Series

The Intel Xeon Processor 7500 series supports MSRs listed in Table 2-15 (except MSR address 1ADH) and addi-

tional model-specific registers listed in Table 2-17. These processors have a CPUID Signature

DisplayFamily_DisplayModel value of 06_2EH.

Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Register Address: 1ADH, 429

MSR_TURBO_RATIO_LIMIT

Reserved. Attempt to read/write will cause #UD.

Package

Register Address: 289H, 649

IA32_MC9_CTL2

See Table 2-2.

Package

Register Address: 28AH, 650

IA32_MC10_CTL2

See Table 2-2.

Package

Register Address: 28BH, 651

IA32_MC11_CTL2

See Table 2-2.

Package

Register Address: 28CH, 652

IA32_MC12_CTL2

See Table 2-2.

Package

Register Address: 28DH, 653

IA32_MC13_CTL2

See Table 2-2.

Package

Register Address: 28EH, 654

IA32_MC14_CTL2

See Table 2-2.

Package

Register Address: 28FH, 655

IA32_MC15_CTL2

See Table 2-2.

Package

Register Address: 290H, 656

IA32_MC16_CTL2

See Table 2-2.

Package

Vol. 4

2-201