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Intel 64 and IA-32 Architectures. Software Developer’s Manual (2026) - page 70

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

63

MISPRED

Reset Value: 0

The recorded branch taken/not-taken resolution (for conditional

branches) or target (for any indirect branch, including RETs) was

mispredicted.

Register Address: 1F2H, 498

IA32_SMRR_PHYSBASE

SMRR Base Address (Writeable only in SMM)

If IA32_MTRRCAP.SMRR[11] = 1

Base address of SMM memory range.

7:0

Type. Specifies memory type of the range.

11:8

Reserved.

31:12

PhysBase

SMRR physical Base Address.

63:32

Reserved.

Register Address: 1F3H, 499

IA32_SMRR_PHYSMASK

SMRR Range Mask (Writeable only in SMM)

If IA32_MTRRCAP[SMRR] = 1

Range Mask of SMM memory range.

10:0

Reserved.

11

Valid

Enable range mask.

31:12

PhysMask

SMRR address range mask.

63:32

Reserved.

Register Address: 1F8H, 504

IA32_PLATFORM_DCA_CAP

DCA Capability (R)

If CPUID.01H:ECX[18] = 1

Register Address: 1F9H, 505

IA32_CPU_DCA_CAP

If set, CPU supports Prefetch-Hint type.

If CPUID.01H:ECX[18] = 1

Register Address: 1FAH, 506

IA32_DCA_0_CAP

DCA type 0 Status and Control register.

If CPUID.01H:ECX[18] = 1

0

DCA_ACTIVE: Set by HW when DCA is fuse-enabled and no defeatures

are set.

2:1

TRANSACTION

6:3

DCA_TYPE

10:7

DCA_QUEUE_SIZE

12:11

Reserved.

16:13

DCA_DELAY: Writes will update the register but have no HW side-effect.

23:17

Reserved.

24

SW_BLOCK: SW can request DCA block by setting this bit.

25

Reserved.

26

HW_BLOCK: Set when DCA is blocked by HW (e.g., CR0.CD = 1).

31:27

Reserved.

2-28 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

MTRRphysBase9

If IA32_MTRRCAP[7:0] > 9

Register Address: 213H, 531

IA32_MTRR_PHYSMASK9

MTRRphysMask9

If IA32_MTRRCAP[7:0] > 9

Register Address: 250H, 592

IA32_MTRR_FIX64K_00000

MTRRfix64K_00000

If CPUID.01H:EDX.MTRR[12] = 1

Register Address: 258H, 600

IA32_MTRR_FIX16K_80000

MTRRfix16K_80000

If CPUID.01H:EDX.MTRR[12] = 1

Register Address: 259H, 601

IA32_MTRR_FIX16K_A0000

MTRRfix16K_A0000

If CPUID.01H:EDX.MTRR[12] = 1

Register Address: 268H, 616

IA32_MTRR_FIX4K_C0000 (MTRRfix4K_C0000)

See Section 14.11.2.2, “Fixed Range MTRRs.”

If CPUID.01H:EDX.MTRR[12] = 1

Register Address: 269H, 617

IA32_MTRR_FIX4K_C8000

MTRRfix4K_C8000

If CPUID.01H:EDX.MTRR[12] = 1

Register Address: 26AH, 618

IA32_MTRR_FIX4K_D0000

MTRRfix4K_D0000

If CPUID.01H:EDX.MTRR[12] = 1

Register Address: 26BH, 619

IA32_MTRR_FIX4K_D8000

MTRRfix4K_D8000

If CPUID.01H:EDX.MTRR[12] = 1

Register Address: 26CH, 620

IA32_MTRR_FIX4K_E0000

MTRRfix4K_E0000

If CPUID.01H:EDX.MTRR[12] = 1

Register Address: 26DH, 621

IA32_MTRR_FIX4K_E8000

MTRRfix4K_E8000

If CPUID.01H:EDX.MTRR[12] = 1

Register Address: 26EH, 622

IA32_MTRR_FIX4K_F0000

MTRRfix4K_F0000

If CPUID.01H:EDX.MTRR[12] = 1

Register Address: 26FH, 623

IA32_MTRR_FIX4K_F8000

MTRRfix4K_F8000.

If CPUID.01H:EDX.MTRR[12] = 1

Register Address: 277H, 631

IA32_PAT

IA32_PAT (R/W)

If CPUID.01H:EDX.PAT[16] = 1

2:0

PA0

7:3

Reserved.

10:8

PA1

15:11

Reserved.

18:16

PA2

23:19

Reserved.

26:24

PA3

31:27

Reserved.

34:32

PA4

39:35

Reserved.

2-30 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

42:40

PA5

47:43

Reserved.

50:48

PA6

55:51

Reserved.

58:56

PA7

63:59

Reserved.

Register Address: 280H, 640

IA32_MC0_CTL2

MSR to enable/disable CMCI capability for bank 0. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 0

See Section 18.3.2.5, “IA32_MCi_CTL2 MSRs.”

14:0

Corrected error count threshold.

29:15

Reserved.

30

CMCI_EN

63:31

Reserved.

Register Address: 281H, 641

IA32_MC1_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 1

Register Address: 282H, 642

IA32_MC2_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 2

Register Address: 283H, 643

IA32_MC3_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 3

Register Address: 284H, 644

IA32_MC4_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 4

Register Address: 285H, 645

IA32_MC5_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 5

Register Address: 286H, 646

IA32_MC6_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 6

Register Address: 287H, 647

IA32_MC7_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 7

Register Address: 288H, 648

IA32_MC8_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 8

Register Address: 289H, 649

IA32_MC9_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 9

Vol. 4

2-31

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

Register Address: 28AH, 650

IA32_MC10_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 10

Register Address: 28BH, 651

IA32_MC11_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 11

Register Address: 28CH, 652

IA32_MC12_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 12

Register Address: 28DH, 653

IA32_MC13_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 13

Register Address: 28EH, 654

IA32_MC14_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 14

Register Address: 28FH, 655

IA32_MC15_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 15

Register Address: 290H, 656

IA32_MC16_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 16

Register Address: 291H, 657

IA32_MC17_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 17

Register Address: 292H, 658

IA32_MC18_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 18

Register Address: 293H, 659

IA32_MC19_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 19

Register Address: 294H, 660

IA32_MC20_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 20

Register Address: 295H, 661

IA32_MC21_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 21

Register Address: 296H, 662

IA32_MC22_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 22

Register Address: 297H, 663

IA32_MC23_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 23

2-32 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

Register Address: 298H, 664

IA32_MC24_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 24

Register Address: 299H, 665

IA32_MC25_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 25

Register Address: 29AH, 666

IA32_MC26_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 26

Register Address: 29BH, 667

IA32_MC27_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 27

Register Address: 29CH, 668

IA32_MC28_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 28

Register Address: 29DH, 669

IA32_MC29_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 29

Register Address: 29EH, 670

IA32_MC30_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 30

Register Address: 29FH, 671

IA32_MC31_CTL2

Same fields as IA32_MC0_CTL2. (R/W)

If IA32_MCG_CAP[10] = 1 &&

IA32_MCG_CAP[7:0] > 31

Register Address: 2DCH, 732

IA32_INTEGRITY_STATUS

IA32_INTEGRITY_STATUS (R/O)

If any one enumeration condition

Provides status information for integrity features.

for defined bit field holds.

0

STATIC_LOCKSTEP

If CPUID.07H.01H:EDX[24] = 1

0: Static Lockstep Mode is not active on this logical processor.

1: Static Lockstep Mode is active on this logical processor.

63:1

Reserved.

Register Address: 2FFH, 767

IA32_MTRR_DEF_TYPE

MTRRdefType (R/W)

If CPUID.01H:EDX.MTRR[12] = 1

2:0

Default Memory Type

9:3

Reserved.

10

Fixed Range MTRR Enable

11

MTRR Enable

63:12

Reserved.

Register Address: 309H, 777

IA32_FIXED_CTR0

Vol. 4

2-33

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any.

If CPUID.0AH:EDX[4:0] > 0 ||

CPUID.0AH:ECX[0] = 1 ||

CPUID.23H.01H:EBX[0] = 1

Register Address: 30AH, 778

IA32_FIXED_CTR1

Fixed-Function Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core.

If CPUID.0AH:EDX[4:0] > 1 ||

CPUID.0AH:ECX[1] = 1 ||

CPUID.23H.01H:EBX[1] = 1

Register Address: 30BH, 779

IA32_FIXED_CTR2

Fixed-Function Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref.

If CPUID.0AH:EDX[4:0] > 2 ||

CPUID.0AH:ECX[2] = 1 ||

CPUID.23H.01H:EBX[2] = 1

Register Address: 30CH, 780

IA32_FIXED_CTR3

Fixed-Function Performance Counter 3 (R/W): Top-down Microarchitecture Analysis unhalted

If CPUID.0AH:EDX[4:0] > 3 ||

number of available slots.

CPUID.0AH:ECX[3] = 1 ||

CPUID.23H.01H:EBX[3] = 1

Register Address: 30DH, 781

IA32_FIXED_CTR4

Fixed-Function Performance Counter 4 (R/W): Top-down bad speculation.

If CPUID.0AH:EDX[4:0] > 4 ||

CPUID.0AH:ECX[4] = 1 ||

CPUID.23H.01H:EBX[4] = 1

47:0

FIXED_COUNTER

Top-down bad speculation counter.

63:46

Reserved.

Register Address: 30EH, 782

IA32_FIXED_CTR5

Fixed-Function Performance Counter 5 (R/W): Top-down Frontend Bound.

If CPUID.0AH:EDX[4:0] > 5 ||

CPUID.0AH:ECX[5] = 1 ||

CPUID.23H.01H:EBX[5] = 1

47:0

FIXED_COUNTER

Top-down Frontend Bound counter.

63:46

Reserved.

Register Address: 30FH, 783

IA32_FIXED_CTR6

Fixed-Function Performance Counter 6 (R/W): Top-down retiring.

If CPUID.0AH:EDX[4:0] > 6 ||

CPUID.0AH:ECX[6] = 1 ||

CPUID.23H.01H:EBX[6] = 1

47:0

FIXED_COUNTER

Top-down Retiring counter.

63:46

Reserved.

Register Address: 345H, 837

IA32_PERF_CAPABILITIES

Read Only MSR that enumerates the existence of performance monitoring features. (R/O)

If CPUID.01H:ECX[15] = 1

5:0

LBR format

6

PEBS Trap

7

PEBSSaveArchRegs

11:8

PEBS Record Format

2-34 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

12

1: Freeze while SMM is supported.

13

1: Full width of counter writable via IA32_A_PMCx.

14

PEBS_BASELINE

15

1: Performance metrics available.

16

1: PEBS output will be written into the Intel PT trace stream.

If CPUID.07H.00H:EBX[25] = 1

17

1: Indicates support for PEBS Retire Latency output.

18

TSX_ADDRESS

19

RDPMC_METRICS_CLEAR

63:20

Reserved.

Register Address: 38DH, 909

IA32_FIXED_CTR_CTRL

Fixed-Function Performance Counter Control (R/W)

If CPUID.0AH:EAX[7:0] > 1

Counter increments while the results of ANDing respective enable bit in

IA32_PERF_GLOBAL_CTRL with the corresponding OS or USR bits in this MSR is true.

0

EN0_OS: Enable Fixed Counter 0 to count while CPL = 0.

1

EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0.

2

AnyThr0: When set to 1, it enables counting the associated event

If CPUID.0AH:EAX[7:0] > 2 &&

conditions occurring across all logical processors sharing a processor

CPUID.0AH:EDX[15] = 0

core. When set to 0, the counter only increments the associated event

conditions occurring in the logical processor which programmed the MSR.

3

EN0_PMI: Enable PMI when fixed counter 0 overflows.

4

EN1_OS: Enable Fixed Counter 1to count while CPL = 0.

5

EN1_Usr: Enable Fixed Counter 1to count while CPL > 0.

6

AnyThr1: When set to 1, it enables counting the associated event

If CPUID.0AH:EAX[7:0] > 2 &&

conditions occurring across all logical processors sharing a processor

CPUID.0AH:EDX[15] = 0

core. When set to 0, the counter only increments the associated event

conditions occurring in the logical processor which programmed the MSR.

7

EN1_PMI: Enable PMI when fixed counter 1 overflows.

8

EN2_OS: Enable Fixed Counter 2 to count while CPL = 0.

9

EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0.

10

AnyThr2: When set to 1, it enables counting the associated event

If CPUID.0AH:EAX[7:0] > 2 &&

conditions occurring across all logical processors sharing a processor

CPUID.0AH:EDX[15] = 0

core. When set to 0, the counter only increments the associated event

conditions occurring in the logical processor which programmed the MSR.

11

EN2_PMI: Enable PMI when fixed counter 2 overflows.

12

EN3_OS: Enable Fixed Counter 3 to count while CPL = 0.

13

EN3_Usr: Enable Fixed Counter 3 to count while CPL > 0.

14

Reserved.

15

EN3_PMI: Enable PMI when fixed counter 3 overflows.

63:16

Reserved.

Register Address: 38EH, 910

IA32_PERF_GLOBAL_STATUS

Vol. 4

2-35

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

Global Performance Counter Status (R/O)

If CPUID.0AH:EAX[7:0] > 0 II

(CPUID.07H.00H:EBX[25] = 1 &&

CPUID.14H.00H:ECX[0] = 1)

0

Ovf_PMC0: Overflow status of IA32_PMC0.

If CPUID.0AH:EAX[15:8] > 0

1

Ovf_PMC1: Overflow status of IA32_PMC1.

If CPUID.0AH:EAX[15:8] > 1

2

Ovf_PMC2: Overflow status of IA32_PMC2.

If CPUID.0AH:EAX[15:8] > 2

3

Ovf_PMC3: Overflow status of IA32_PMC3.

If CPUID.0AH:EAX[15:8] > 3

n

Ovf_PMCn: Overflow status of IA32_PMCn.

If CPUID.0AH:EAX[15:8] > n

31:n+1

Reserved.

32

Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0.

If CPUID.0AH:EAX[7:0] > 1

33

Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1.

If CPUID.0AH:EAX[7:0] > 1

34

Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2.

If CPUID.0AH:EAX[7:0] > 1

32+m

Ovf_FixedCtrm: Overflow status of IA32_FIXED_CTRm.

If CPUID.0AH:ECX[m] == 1 ||

CPUID.0AH:EDX[4:0] > m

47:33+m

Reserved.

48

OVF_PERF_METRICS: If this bit is set, it indicates that PERF_METRIC

counter has overflowed and a PMI is triggered; however, an overflow of

fixed counter 3 should normally happen first. If this bit is clear no

overflow occurred.

54:49

Reserved.

55

Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory buffer

If CPUID.07H.00H:EBX[25] = 1 &&

that was completely filled.

CPUID.14H.00H:ECX[0] = 1

57:56

Reserved.

58

LBR_Frz. LBRs are frozen due to:

If CPUID.0AH:EAX[7:0] > 3

• IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1.

• The LBR stack overflowed.

59

CTR_Frz. Performance counters in the core PMU are frozen due to:

If CPUID.0AH:EAX[7:0] > 3

• IA32_DEBUGCTL.FREEZE_PERFMON_ON_PMI=1.

• One or more core PMU counters overflowed.

60

ASCI: Data in the performance counters in the core PMU may include

If the processor supports Intel®

contributions from the direct or indirect operation Intel SGX to protect an

SGX.

enclave.

61

Ovf_Uncore: Uncore counter overflow status.

If CPUID.0AH:EAX[7:0] > 2

62

OvfBuf: DS SAVE area Buffer overflow status.

If CPUID.0AH:EAX[7:0] > 0

63

CondChgd: Status bits of this register have changed.

If CPUID.0AH:EAX[7:0] > 0

Register Address: 38FH, 911

IA32_PERF_GLOBAL_CTRL

Global Performance Counter Control (R/W)

If CPUID.0AH:EAX[7:0] > 0

Counter increments while the result of ANDing the respective enable bit in this MSR with the

corresponding OS or USR bits in the general-purpose or fixed counter control MSR is true.

0

EN_PMC0

If CPUID.0AH:EAX[15:8] > 0

1

EN_PMC1

If CPUID.0AH:EAX[15:8] > 1

2

EN_PMC2

If CPUID.0AH:EAX[15:8] > 2

2-36 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

n

EN_PMCn

If CPUID.0AH:EAX[15:8] > n

31:n+1

Reserved.

32

EN_FIXED_CTR0

If CPUID.0AH:EDX[4:0] > 0

33

EN_FIXED_CTR1

If CPUID.0AH:EDX[4:0] > 1

34

EN_FIXED_CTR2

If CPUID.0AH:EDX[4:0] > 2

32+m

EN_FIXED_CTRm

If CPUID.0AH:ECX[m] == 1 ||

CPUID.0AH:EDX[4:0] > m

47:33+m

Reserved.

48

EN_PERF_METRICS: If this bit is set and fixed counter 3 is effectively

enabled, built-in performance metrics are enabled.

63:49

Reserved.

Register Address: 390H, 912

IA32_PERF_GLOBAL_STATUS_RESET

Global Performance Counter Overflow Reset Control (R/W)

If CPUID.0AH:EAX[7:0] > 3 II

(CPUID.07H.00H:EBX[25] = 1 &&

CPUID.14H.00H:ECX[0] = 1)

0

Set 1 to Clear Ovf_PMC0 bit.

If CPUID.0AH:EAX[15:8] > 0

1

Set 1 to Clear Ovf_PMC1 bit.

If CPUID.0AH:EAX[15:8] > 1

2

Set 1 to Clear Ovf_PMC2 bit.

If CPUID.0AH:EAX[15:8] > 2

n

Set 1 to Clear Ovf_PMCn bit.

If CPUID.0AH:EAX[15:8] > n

31:n

Reserved.

32

Set 1 to Clear Ovf_FIXED_CTR0 bit.

If CPUID.0AH:EDX[4:0] > 0

33

Set 1 to Clear Ovf_FIXED_CTR1 bit.

If CPUID.0AH:EDX[4:0] > 1

34

Set 1 to Clear Ovf_FIXED_CTR2 bit.

If CPUID.0AH:EDX[4:0] > 2

32+m

Set 1 to Clear Ovf_FIXED_CTRm bit.

If CPUID.0AH:ECX[m] == 1 ||

CPUID.0AH:EDX[4:0] > m

47:33+m

Reserved.

48

RESET_OVF_PERF_METRICS: If this bit is set, it will clear the status bit in

the IA32_PERF_GLOBAL_STATUS register for the PERF_METRICS

counters.

54:49

Reserved.

55

Set 1 to Clear Trace_ToPA_PMI bit.

If CPUID.07H.00H:EBX[25] = 1 &&

CPUID.14H.00H:ECX[0] = 1

57:56

Reserved.

58

Set 1 to Clear LBR_Frz bit.

If CPUID.0AH:EAX[7:0] > 3

59

Set 1 to Clear CTR_Frz bit.

If CPUID.0AH:EAX[7:0] > 3

60

Set 1 to Clear ASCI bit.

If the processor supports Intel®

SGX.

61

Set 1 to Clear Ovf_Uncore bit.

06_2EH

62

Set 1 to Clear OvfBuf bit.

If CPUID.0AH:EAX[7:0] > 0

63

Set 1 to clear CondChgd bit.

If CPUID.0AH:EAX[7:0] > 0

Vol. 4

2-37

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

Register Address: 391H, 913

IA32_PERF_GLOBAL_STATUS_SET

Global Performance Counter Overflow Set Control (R/W)

If CPUID.0AH:EAX[7:0] > 3 II

(CPUID.07H.00H:EBX[25] = 1 &&

CPUID.14H.00H:ECX[0] = 1)

0

Set 1 to cause Ovf_PMC0 = 1.

If CPUID.0AH:EAX[7:0] > 3

1

Set 1 to cause Ovf_PMC1 = 1.

If CPUID.0AH:EAX[15:8] > 1

2

Set 1 to cause Ovf_PMC2 = 1.

If CPUID.0AH:EAX[15:8] > 2

n

Set 1 to cause Ovf_PMCn = 1.

If CPUID.0AH:EAX[15:8] > n

31:n

Reserved.

32

Set 1 to cause Ovf_FIXED_CTR0 = 1.

If CPUID.0AH:EAX[7:0] > 3

33

Set 1 to cause Ovf_FIXED_CTR1 = 1.

If CPUID.0AH:EAX[7:0] > 3

34

Set 1 to cause Ovf_FIXED_CTR2 = 1.

If CPUID.0AH:EAX[7:0] > 3

32+m

Set 1 to cause Ovf_FIXED_CTRm = 1.

If CPUID.0AH:ECX[m] == 1 ||

CPUID.0AH:EDX[4:0] > m

47:33+m

Reserved.

48

SET_OVF_PERF_METRICS: If this bit is set, it will set the status bit in the

IA32_PERF_GLOBAL_STATUS register for the PERF_METRICS counters.

54:49

Reserved.

55

Set 1 to cause Trace_ToPA_PMI = 1.

If CPUID.07H.00H:EBX[25] = 1 &&

CPUID.14H.00H:ECX[0] = 1

57:56

Reserved.

58

Set 1 to cause LBR_Frz = 1.

If CPUID.0AH:EAX[7:0] > 3

59

Set 1 to cause CTR_Frz = 1.

If CPUID.0AH:EAX[7:0] > 3

60

Set 1 to cause ASCI = 1.

If the processor supports Intel®

SGX.

61

Set 1 to cause Ovf_Uncore = 1.

If CPUID.0AH:EAX[7:0] > 3

62

Set 1 to cause OvfBuf = 1.

If CPUID.0AH:EAX[7:0] > 3

63

Reserved.

Register Address: 392H, 914

IA32_PERF_GLOBAL_INUSE

Indicator that core PerfMon interface is in use. (R/O)

If CPUID.0AH:EAX[7:0] > 3

0

IA32_PERFEVTSEL0 in use.

1

IA32_PERFEVTSEL1 in use.

If CPUID.0AH:EAX[15:8] > 1

2

IA32_PERFEVTSEL2 in use.

If CPUID.0AH:EAX[15:8] > 2

n

IA32_PERFEVTSELn in use.

If CPUID.0AH:EAX[15:8] > n

31:n+1

Reserved.

32

IA32_FIXED_CTR0 in use.

33

IA32_FIXED_CTR1 in use.

34

IA32_FIXED_CTR2 in use.

32+m

IA32_FIXED_CTRm in use.

2-38 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

62:33+m

Reserved or model specific.

63

PMI in use.

Register Address: 3F1H, 1009

IA32_PEBS_ENABLE

PEBS Control (R/W)

0

Enable PEBS on IA32_PMC0.

06_0FH

3:1

Reserved or model specific.

31:4

Reserved.

35:32

Reserved or model specific.

63:36

Reserved.

Register Address: 3F4H, 1012

IA32_PEBS_BASE

Architectural PEBS Output Buffer Base Register (R/W)

CPUID.23H.00H:EAX[5]=1

Holds basic structural controls for Architectural PEBS.

This MSR is initialized to all zeros on reset.

3:0

SIZE (R/W)

Size options for the PEBS output buffer (actual size is power-of-2

multiples of 4KB, that is, Buffer Size = 4KB * 2^SIZE).

11:4

Reserved.

MAXPHYADDR - 1:12

PHYS_ADDR (R/W)

Start of the PEBS output buffer (4KB-aligned physical address, excluding

the 12b page offset).

63:MAXPHYADDR

Reserved.

Register Address: 3F5H, 1013

IA32_PEBS_INDEX

Arch PEBS Output Buffer Index Register (R/W)

CPUID.23H.00H:EAX[5]=1

Holds status and additional controls for Architectural PEBS.

This MSR is initialized to all zeros on reset.

3:0

Reserved.

26:4

WR_OFFSET (R/W)

Next-byte-to-write offset from IA32_PEBS_BASE.PHYS_ADDR.

30:27

Reserved.

31

FULL (R/W)

The buffer is full, and no further records will be generated.

32

THRESH_EN (R/W)

Enable PMI on PEBS buffer Threshold checks.

35:33

Reserved.

58:36

THRESH_OFFSET (R/W)

The threshold for the PEBS buffer (specified as offset in bytes from

IA32_PEBS_BASE.PHYS_ADDR).

63:59

Reserved.

Register Address: 400H, 1024

IA32_MC0_CTL

MC0_CTL

If IA32_MCG_CAP.CNT > 0

Vol. 4

2-39

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

Register Address: 482H, 1154

IA32_VMX_PROCBASED_CTLS

Capability Reporting Register of Primary Processor-Based VM-Execution Controls (R/O)

If CPUID.01H:ECX[5] = 1

See Appendix A.3.2, “Primary Processor-Based VM-Execution Controls.”

Register Address: 483H, 1155

IA32_VMX_EXIT_CTLS

Capability Reporting Register of Primary VM-Exit Controls (R/O)

If CPUID.01H:ECX[5] = 1

See Appendix A.4.1, “Primary VM-Exit Controls.”

Register Address: 484H, 1156

IA32_VMX_ENTRY_CTLS

Capability Reporting Register of VM-Entry Controls (R/O)

If CPUID.01H:ECX[5] = 1

See Appendix A.5, “VM-Entry Controls.”

Register Address: 485H, 1157

IA32_VMX_MISC

Reporting Register of Miscellaneous VMX Capabilities (R/O)

If CPUID.01H:ECX[5] = 1

See Appendix A.6, “Miscellaneous Data.”

Register Address: 486H, 1158

IA32_VMX_CR0_FIXED0

Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)

If CPUID.01H:ECX[5] = 1

See Appendix A.7, “VMX-Fixed Bits in CR0.”

Register Address: 487H, 1159

IA32_VMX_CR0_FIXED1

Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)

If CPUID.01H:ECX[5] = 1

See Appendix A.7, “VMX-Fixed Bits in CR0.”

Register Address: 488H, 1160

IA32_VMX_CR4_FIXED0

Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)

If CPUID.01H:ECX[5] = 1

See Appendix A.8, “VMX-Fixed Bits in CR4.”

Register Address: 489H, 1161

IA32_VMX_CR4_FIXED1

Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)

If CPUID.01H:ECX[5] = 1

See Appendix A.8, “VMX-Fixed Bits in CR4.”

Register Address: 48AH, 1162

IA32_VMX_VMCS_ENUM

Capability Reporting Register of VMCS Field Enumeration (R/O)

If CPUID.01H:ECX[5] = 1

See Appendix A.9, “VMCS Enumeration.”

Register Address: 48BH, 1163

IA32_VMX_PROCBASED_CTLS2

Capability Reporting Register of Secondary Processor-Based VM-Execution Controls (R/O)

If ( CPUID.01H:ECX[5] &&

IA32_VMX_PROCBASED_CTLS[63

See Appendix A.3.3, “Secondary Processor-Based VM-Execution Controls.”

])

Register Address: 48CH, 1164

IA32_VMX_EPT_VPID_CAP

Capability Reporting Register of EPT and VPID (R/O)

If ( CPUID.01H:ECX[5] &&

IA32_VMX_PROCBASED_CTLS[63

See Appendix A.10, “VPID and EPT Capabilities.”

] && (

IA32_VMX_PROCBASED_CTLS2[3

3] ||

IA32_VMX_PROCBASED_CTLS2[3

7]) )

Register Address: 48DH, 1165

IA32_VMX_TRUE_PINBASED_CTLS

Vol. 4

2-47

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

Capability Reporting Register of Pin-Based VM-Execution Flex Controls (R/O)

If ( CPUID.01H:ECX[5] &&

IA32_VMX_BASIC[55] )

See Appendix A.3.1, “Pin-Based VM-Execution Controls.”

Register Address: 48EH, 1166

IA32_VMX_TRUE_PROCBASED_CTLS

Capability Reporting Register of Primary Processor-Based VM-Execution Flex Controls (R/O)

If( CPUID.01H:ECX[5] &&

IA32_VMX_BASIC[55] )

See Appendix A.3.2, “Primary Processor-Based VM-Execution Controls.”

Register Address: 48FH, 1167

IA32_VMX_TRUE_EXIT_CTLS

Capability Reporting Register of VM-Exit Flex Controls (R/O)

If( CPUID.01H:ECX[5] &&

IA32_VMX_BASIC[55] )

See Appendix A.4, “VM-Exit Controls.”

Register Address: 490H, 1168

IA32_VMX_TRUE_ENTRY_CTLS

Capability Reporting Register of VM-Entry Flex Controls (R/O)

If( CPUID.01H:ECX[5] &&

See Appendix A.5, “VM-Entry Controls.”

IA32_VMX_BASIC[55] )

Register Address: 491H, 1169

IA32_VMX_VMFUNC

Capability Reporting Register of VM-Function Controls (R/O)

If( CPUID.01H:ECX[5] &&

IA32_VMX_PROCBASED_CTLS[63

] &&

IA32_VMX_PROCBASED_CTLS2[4

5])

Register Address: 492H, 1170

IA32_VMX_PROCBASED_CTLS3

Capability Reporting Register of Tertiary Processor-Based VM-Execution Controls (R/O)

If ( CPUID.01H:ECX[5] &&

IA32_VMX_PROCBASED_CTLS[49

See Appendix A.3.4, “Tertiary Processor-Based VM-Execution Controls.”

])

Register Address: 493H, 1171

IA32_VMX_EXIT_CTLS2

Capability Reporting Register of Secondary VM-Exit Controls (R/O)

If ( CPUID.01H:ECX[5] &&

IA32_VMX_EXIT_CTLS[63])

See Appendix A.4.2, “Secondary VM-Exit Controls.”

Register Address: 4C1H, 1217

IA32_A_PMC0

Full Width Writable IA32_PMC0 Alias (R/W)

If (CPUID.0AH:EAX[15:8] > 0) &&

IA32_PERF_CAPABILITIES[13] =

1) || CPUID.23H.01H:EAX[0] = 1

Register Address: 4C2H, 1218

IA32_A_PMC1

Full Width Writable IA32_PMC1 Alias (R/W)

If (CPUID.0AH:EAX[15:8] > 1) &&

IA32_PERF_CAPABILITIES[13] =

1) || CPUID.23H.01H:EAX[1] = 1

Register Address: 4C3H, 1219

IA32_A_PMC2

Full Width Writable IA32_PMC2 Alias (R/W)

If (CPUID.0AH:EAX[15:8] > 2) &&

IA32_PERF_CAPABILITIES[13] =

1) || CPUID.23H.01H:EAX[2] = 1

Register Address: 4C4H, 1220

IA32_A_PMC3

Full Width Writable IA32_PMC3 Alias (R/W)

If (CPUID.0AH:EAX[15:8] > 3) &&

IA32_PERF_CAPABILITIES[13] =

1) || CPUID.23H.01H:EAX[3] = 1

Register Address: 4C5H, 1221

IA32_A_PMC4

2-48 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

Full Width Writable IA32_PMC4 Alias (R/W)

If (CPUID.0AH:EAX[15:8] > 4) &&

IA32_PERF_CAPABILITIES[13] =

1) || CPUID.23H.01H:EAX[4] = 1

Register Address: 4C6H, 1222

IA32_A_PMC5

Full Width Writable IA32_PMC5 Alias (R/W)

If (CPUID.0AH:EAX[15:8] > 5) &&

IA32_PERF_CAPABILITIES[13] =

1) || CPUID.23H.01H:EAX[5] = 1

Register Address: 4C7H, 1223

IA32_A_PMC6

Full Width Writable IA32_PMC6 Alias (R/W)

If (CPUID.0AH:EAX[15:8] > 6) &&

IA32_PERF_CAPABILITIES[13] =

1) || CPUID.23H.01H:EAX[6] = 1

Register Address: 4C8H, 1224

IA32_A_PMC7

Full Width Writable IA32_PMC7 Alias (R/W)

If (CPUID.0AH:EAX[15:8] > 7) &&

IA32_PERF_CAPABILITIES[13] =

1) || CPUID.23H.01H:EAX[7] = 1

Register Address: 4C9H, 1225

IA32_A_PMC8

Full Width Writable IA32_PMC8 Alias (R/W)

If (CPUID.0AH:EAX[15:8] > 8) &&

IA32_PERF_CAPABILITIES[13] =

1) || CPUID.23H.01H:EAX[8] = 1

Register Address: 4CAH, 1226

IA32_A_PMC9

Full Width Writable IA32_PMC9 Alias (R/W)

If (CPUID.0AH:EAX[15:8] > 9) &&

IA32_PERF_CAPABILITIES[13] =

1) || CPUID.23H.01H:EAX[9] = 1

Register Address: 4D0H, 1232

IA32_MCG_EXT_CTL

Allows software to signal some MCEs to only a single logical processor in the system. (R/W)

If IA32_MCG_CAP.LMCE_P = 1

See Section 18.3.1.4, “IA32_MCG_EXT_CTL MSR.”

0

LMCE_EN

Enable / Disable local machine check exception.

63:1

Reserved.

Register Address: 500H, 1280

IA32_SGX_SVN_STATUS

Status and SVN Threshold of SGX Support for ACM (R/O)

If CPUID.07H.00H:EBX[2] = 1

0

Lock.

See Section 42.11.3, “Interactions

with Authenticated Code Modules

(ACMs).”

15:1

Reserved.

23:16

SGX_SVN_SINIT

See Section 42.11.3, “Interactions

with Authenticated Code Modules

(ACMs).”

63:24

Reserved.

Register Address: 560H, 1376

IA32_RTIT_OUTPUT_BASE

Trace Output Base Register (R/W)

If ((CPUID.07H.00H:EBX[25] = 1)

&& ( (CPUID.14H.00H:ECX[0] = 1) ||

(CPUID.14H.00H:ECX[2] = 1) ) )

Vol. 4

2-49

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

6:0

Reserved.

M-1:7

Base physical address.

M is the value enumerated by

CPUID.80000008H:EAX[7:0].

63:M

Reserved.

Register Address: 561H, 1377

IA32_RTIT_OUTPUT_MASK_PTRS

Trace Output Mask Pointers Register (R/W)

If ((CPUID.07H.00H:EBX[25] = 1)

&& ( (CPUID.14H.00H:ECX[0] = 1) ||

(CPUID.14H.00H:ECX[2] = 1) ) )

6:0

Reserved.

31:7

MaskOrTableOffset.

63:32

Output Offset.

Register Address: 568H, 1384

IA32_RTIT_TRIGGER0_CFG

Trace Trigger 0 Configuration Register (R/W)

Thread

6:0

Input0 (R/W)

Selects the event used as a trigger input for trigger unit 0. The following

encoding values are supported:

• 0H...7H: PMC[0...7] Event Increment.

•

20H...27H: PMC[0...7] Overflow.

•

40H...43H: DR[0...3] Breakpoint Match.

All other values are reserved. Reset value: 0.

11:7

Reserved.

15:12

Action0 (R/W)

Bitmap field that selects the actions to be taken on a trigger event. The

following bit encodings are supported:

• Bit 12: TRACE_RESUME-Trace Resume.

• Bit 13: TRACE_PAUSE-Trace Pause.

• Bit 14: EN_ICNT-Enable ICNT.

• Bit 15: EN-Trigger Unit Enable.

22:16

Input1 (R/W)

Same definition as Input0, but for trigger unit 1.

27:23

Reserved.

31:28

Action1 (R/W)

Same definition as Action0, but for trigger unit 1.

38:32

Input2 (R/W)

Same definition as Input0, but for trigger unit 2.

43:39

Reserved.

47:44

Action2 (R/W)

Same definition as Action0, but for trigger unit 2.

54:48

Input3 (R/W)

Same definition as Input0, but for trigger unit 3.

59:55

Reserved.

63:32

Action3 (R/W)

Same definition as Action0, but for trigger unit 3.

Register Address: 569H, 1385

IA32_RTIT_TRIGGER1_CFG

2-50 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

Trace Trigger 1 Configuration Register (R/W)

Register Address: 56AH, 1386

IA32_RTIT_TRIGGER2_CFG

Trace Trigger 2 Configuration Register (R/W)

Register Address: 56BH, 1387

IA32_RTIT_TRIGGER3_CFG

Trace Trigger 3 Configuration Register (R/W)

Register Address: 56CH, 1388

IA32_RTIT_TRIGGER4_CFG

Trace Trigger 4 Configuration Register (R/W)

Register Address: 56DH, 1389

IA32_RTIT_TRIGGER5_CFG

Trace Trigger 5 Configuration Register (R/W)

Register Address: 56EH, 1390

IA32_RTIT_TRIGGER6_CFG

Trace Trigger 6 Configuration Register (R/W)

Register Address: 56FH, 1391

IA32_RTIT_TRIGGER7_CFG

Trace Trigger 7 Configuration Register (R/W)

Register Address: 570H, 1392

IA32_RTIT_CTL

Trace Control Register (R/W)

If (CPUID.07H.00H:EBX[25] = 1)

0

TraceEn

1

CYCEn

If (CPUID.07H.00H:EBX[1] = 1)

2

OS

3

User

4

PwrEvtEn

If (CPUID.07H.01H:EBX[5] = 1)

5

FUPonPTW

If (CPUID.07H.01H:EBX[4] = 1)

6

FabricEn

If (CPUID.07H.00H:ECX[3] = 1)

7

CR3Filter

If (CPUID.14H.00H:EBX[0] = 1)

8

ToPA

9

MTCEn

If (CPUID.07H.00H:EBX[3] = 1)

10

TSCEn

11

DisRETC

12

PTWEn

If (CPUID.07H.01H:EBX[4] = 1)

13

BranchEn

17:14

MTCFreq.

If (CPUID.07H.00H:EBX[3] = 1)

18

Reserved, must be zero.

22:19

CycThresh

If (CPUID.07H.00H:EBX[1] = 1)

23

Reserved, must be zero.

27:24

PSBFreq

If (CPUID.07H.00H:EBX[1] = 1)

30:28

Reserved, must be zero.

31

EventEn

If (CPUID.14H.00H:EBX[7] = 1)

35:32

ADDR0_CFG

If (CPUID.07H.01H:EAX[2:0] > 0)

Vol. 4

2-51

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

39:36

ADDR1_CFG

If (CPUID.07H.01H:EAX[2:0] > 1)

43:40

ADDR2_CFG

If (CPUID.07H.01H:EAX[2:0] > 2)

47:44

ADDR3_CFG

If (CPUID.07H.01H:EAX[2:0] > 3)

54:48

Reserved, must be zero.

55

DisTNT

If (CPUID.14H.00H:EBX[8] = 1)

56

InjectPsbPmiOnEnable

If (CPUID.07H.01H:EBX[6] = 1)

63:57

Reserved, must be zero.

Register Address: 571H, 1393

IA32_RTIT_STATUS

Tracing Status Register (R/W)

If (CPUID.07H.00H:EBX[25] = 1)

0

FilterEn (writes ignored).

If (CPUID.07H.00H:EBX[2] = 1)

1

ContexEn (writes ignored).

2

TriggerEn (writes ignored).

3

Reserved.

4

Error.

5

Stopped.

6

PendPSB.

If (CPUID.07H.00H:EBX[6] = 1)

7

PendToPAPMI.

If (CPUID.07H.00H:EBX[6] = 1)

8

Paused.

If (CPUID.14H.00H:EBX[9] = 1)

31:9

Reserved, must be zero.

48:32

PacketByteCnt.

If (CPUID.07H.00H:EBX[1] > 3)

63:49

Reserved.

Register Address: 572H, 1394

IA32_RTIT_CR3_MATCH

Trace Filter CR3 Match Register (R/W)

If (CPUID.07H.00H:EBX[25] = 1)

4:0

Reserved.

63:5

CR3[63:5] value to match.

Register Address: 580H, 1408

IA32_RTIT_ADDR0_A

Region 0 Start Address (R/W)

If (CPUID.07H.01H:EAX[2:0] > 0)

47:0

Virtual Address.

63:48

SignExt_VA

Register Address: 581H, 1409

IA32_RTIT_ADDR0_B

Region 0 End Address (R/W)

If (CPUID.07H.01H:EAX[2:0] > 0)

47:0

Virtual Address.

63:48

SignExt_VA

Register Address: 582H, 1410

IA32_RTIT_ADDR1_A

Region 1 Start Address (R/W)

If (CPUID.07H.01H:EAX[2:0] > 1)

47:0

Virtual Address.

63:48

SignExt_VA

2-52 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

Register Address: 583H, 1411

IA32_RTIT_ADDR1_B

Region 1 End Address (R/W)

If (CPUID.07H.01H:EAX[2:0] > 1)

47:0

Virtual Address.

63:48

SignExt_VA

Register Address: 584H, 1412

IA32_RTIT_ADDR2_A

Region 2 Start Address (R/W)

If (CPUID.07H.01H:EAX[2:0] > 2)

47:0

Virtual Address.

63:48

SignExt_VA

Register Address: 585H, 1413

IA32_RTIT_ADDR2_B

Region 2 End Address (R/W)

If (CPUID.07H.01H:EAX[2:0] > 2)

47:0

Virtual Address.

63:48

SignExt_VA

Register Address: 586H, 1414

IA32_RTIT_ADDR3_A

Region 3 Start Address (R/W)

If (CPUID.07H.01H:EAX[2:0] > 3)

47:0

Virtual Address.

63:48

SignExt_VA

Register Address: 587H, 1415

IA32_RTIT_ADDR3_B

Region 3 End Address (R/W)

If (CPUID.07H.01H:EAX[2:0] > 3)

47:0

Virtual Address.

63:48

SignExt_VA

Register Address: 600H, 1536

IA32_DS_AREA

DS Save Area (R/W)

If( CPUID.01H:EDX.DS[21] = 1

Points to the linear address of the first byte of the DS buffer management area, which is used to

manage the BTS and PEBS buffers.

See Section 22.6.3.4, “Debug Store (DS) Mechanism.”

63:0

The linear address of the first byte of the DS buffer management area, if

IA-32e mode is active.

31:0

The linear address of the first byte of the DS buffer management area, if

not in IA-32e mode.

63:32

Reserved if not in IA-32e mode.

Register Address: 6A0H, 1696

IA32_U_CET

Configure User Mode CET (R/W)

Bits 1:0 are defined if

CPUID.07H.00H:ECX.CET_SS[7] =

1.

Bits 5:2 and bits 63:10 are defined

if

CPUID.07H.00H:EDX.CET_IBT[20]

= 1.

0

SH_STK_EN: When set to 1, enable shadow stacks at CPL3.

1

WR_SHSTK_EN: When set to 1, enables the WRSSD/WRSSQ instructions.

Vol. 4

2-53

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

2

ENDBR_EN: When set to 1, enables indirect branch tracking.

3

LEG_IW_EN: Enable legacy compatibility treatment for indirect branch

tracking.

4

NO_TRACK_EN: When set to 1, enables use of no-track prefix for indirect

branch tracking.

5

SUPPRESS_DIS: When set to 1, disables suppression of CET indirect

branch tracking on legacy compatibility.

9:6

Reserved; must be zero.

10

SUPPRESS: When set to 1, indirect branch tracking is suppressed. This bit

can be written to 1 only if TRACKER is written as IDLE.

11

TRACKER: Value of the indirect branch tracking state machine. Values:

IDLE (0), WAIT_FOR_ENDBRANCH(1).

63:12

EB_LEG_BITMAP_BASE: Linear address bits 63:12 of a legacy code page

bitmap used for legacy compatibility when indirect branch tracking is

enabled.

If the processor does not support Intel 64 architecture, these fields have

only 32 bits; bits 63:32 of the MSRs are reserved. On processors that

support Intel 64 architecture this value cannot represent a non-canonical

address. In protected mode, only 31:0 are used.

Register Address: 6A2H, 1698

IA32_S_CET

Configure Supervisor Mode CET (R/W)

See IA32_U_CET (6A0H) for

reference; similar format.

Register Address: 6A4H, 1700

IA32_PL0_SSP (also called IA32_FRED_SSP0)

Linear address to be loaded into SSP on transition to privilege level 0. (R/W)

If CPUID.07H.00H:ECX.CET_SS[7]

= 1

If the processor does not support Intel 64 architecture, these fields have only 32 bits; bits 63:32

of the MSRs are reserved. On processors that support Intel 64 architecture this value cannot

represent a non-canonical address. In protected mode, only 31:0 are loaded. Bits 1:0 of the MSR

must be 0. Transitions to privilege level 0 will check that bit 2 is also 0.

FRED event delivery uses this MSR as IA32_FRED_SSP0: if FRED event delivery causes a

transition from CPL 3, SSP is loaded from this MSR.

Register Address: 6A5H, 1701

IA32_PL1_SSP

Linear address to be loaded into SSP on transition to privilege level 1. (R/W)

If CPUID.07H.00H:ECX.CET_SS[7]

= 1

If the processor does not support Intel 64 architecture, these fields have only 32 bits; bits 63:32

of the MSRs are reserved. On processors that support Intel 64 architecture this value cannot

represent a non-canonical address. In protected mode, only 31:0 are loaded. Bits 1:0 of the MSR

must be 0. Transitions to privilege level 1 from a higher privilege level will check that bit 2 is also

0.

Register Address: 6A6H, 1702

IA32_PL2_SSP

Linear address to be loaded into SSP on transition to privilege level 2. (R/W)

If CPUID.07H.00H:ECX.CET_SS[7]

= 1

If the processor does not support Intel 64 architecture, these fields have only 32 bits; bits 63:32

of the MSRs are reserved. On processors that support Intel 64 architecture this value cannot

represent a non-canonical address. In protected mode, only 31:0 are loaded. Bits 1:0 of the MSR

must be 0. Transitions to privilege level 2 from a higher privilege level will check that bit 2 is also

0.

Register Address: 6A7H, 1703

IA32_PL3_SSP

2-54 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

Linear address to be loaded into SSP on transition to privilege level 3. (R/W)

If CPUID.07H.00H:ECX.CET_SS[7]

= 1

If the processor does not support Intel 64 architecture, these fields have only 32 bits; bits 63:32

of the MSRs are reserved. On processors that support Intel 64 architecture this value cannot

represent a non-canonical address. In protected mode, only 31:0 are loaded. Bits 1:0 of the MSR

must be 0.

Register Address: 6A8H, 1704

IA32_INTERRUPT_SSP_TABLE_ADDR

Linear address of a table of seven shadow stack pointers that are selected in IA-32e mode using

If CPUID.07H.00H:ECX.CET_SS[7]

the IST index (when not 0) from the interrupt gate descriptor. (R/W)

= 1

This MSR is not present on processors that do not support Intel 64 architecture. This field cannot

represent a non-canonical address.

Register Address: 6E0H, 1760

IA32_TSC_DEADLINE

TSC Target of Local APIC’s TSC Deadline Mode (R/W)

If CPUID.01H:ECX[24] = 1

63:0

REGISTER_VALUE

TSC-deadline value.

Register Address: 6E1H, 1761

IA32_PKRS

Specifies the PK permissions associated with each protection domain for supervisor pages (R/W)

If CPUID.07H.00H:ECX.PKS[31] = 1

31:0

For domain i (i between 0 and 15), bits 2i and 2i+1 contain the AD and

WD permissions, respectively.

63:32

Reserved.

Register Address: 770H, 1904

IA32_PM_ENABLE

Enable/disable HWP (R/W)

If CPUID.06H:EAX[7] = 1

0

HWP_ENABLE (R/W)

If CPUID.06H:EAX[7] = 1

Note this bit can only be enabled once from the default value. Once set,

writes to the HWP_ENABLE bit are ignored. Only RESET will clear this bit.

Default = 0. See Section 17.4.2, “Enabling HWP.”

63:1

Reserved.

Register Address: 771H, 1905

IA32_HWP_CAPABILITIES

HWP Performance Range Enumeration (R/O)

If CPUID.06H:EAX[7] = 1

7:0

Highest_Performance

If CPUID.06H:EAX[7] = 1

See Section 17.4.3, “HWP Performance Range and Dynamic Capabilities.”

15:8

Guaranteed_Performance

If CPUID.06H:EAX[7] = 1

See Section 17.4.3, “HWP Performance Range and Dynamic Capabilities.”

23:16

Most_Efficient_Performance

If CPUID.06H:EAX[7] = 1

See Section 17.4.3, “HWP Performance Range and Dynamic Capabilities”.

31:24

Lowest_Performance

If CPUID.06H:EAX[7] = 1

See Section 17.4.3, “HWP Performance Range and Dynamic Capabilities.”

63:32

Reserved.

Register Address: 772H, 1906

IA32_HWP_REQUEST_PKG

Power Management Control Hints for All Logical Processors in a Package (R/W)

If CPUID.06H:EAX[11] = 1

7:0

Minimum_Performance

If CPUID.06H:EAX[11] = 1

See Section 17.4.4, “Managing HWP.”

Vol. 4

2-55

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

15:8

Maximum_Performance

If CPUID.06H:EAX[11] = 1

See Section 17.4.4, “Managing HWP.”

23:16

Desired_Performance

If CPUID.06H:EAX[11] = 1

See Section 17.4.4, “Managing HWP.”

31:24

Energy_Performance_Preference

If CPUID.06H:EAX[11] = 1 &&

See Section 17.4.4, “Managing HWP.”

CPUID.06H:EAX[10] = 1

41:32

Activity_Window

If CPUID.06H:EAX[11] = 1 &&

See Section 17.4.4, “Managing HWP.”

CPUID.06H:EAX[9] = 1

63:42

Reserved.

Register Address: 773H, 1907

IA32_HWP_INTERRUPT

Control HWP Native Interrupts (R/W)

If CPUID.06H:EAX[8] = 1

0

EN_Guaranteed_Performance_Change

If CPUID.06H:EAX[8] = 1

See Section 17.4.6, “HWP Notifications.”

1

EN_Excursion_Minimum

If CPUID.06H:EAX[8] = 1

See Section 17.4.6, “HWP Notifications.”

63:2

Reserved.

Register Address: 774H, 1908

IA32_HWP_REQUEST

Power Management Control Hints to a Logical Processor (R/W)

If CPUID.06H:EAX[7] = 1

7:0

Minimum_Performance

If CPUID.06H:EAX[7] = 1

See Section 17.4.4, “Managing HWP.”

15:8

Maximum_Performance

If CPUID.06H:EAX[7] = 1

See Section 17.4.4, “Managing HWP.”

23:16

Desired_Performance

If CPUID.06H:EAX[7] = 1

See Section 17.4.4, “Managing HWP.”

31:24

Energy_Performance_Preference

If CPUID.06H:EAX[7] = 1 &&

CPUID.06H:EAX[10] = 1

See Section 17.4.4, “Managing HWP.”

41:32

Activity_Window

If CPUID.06H:EAX[7] = 1 &&

CPUID.06H:EAX[9] = 1

See Section 17.4.4, “Managing HWP.”

42

Package_Control

If CPUID.06H:EAX[7] = 1 &&

CPUID.06H:EAX[11] = 1

See Section 17.4.4, “Managing HWP.”

63:43

Reserved.

Register Address: 775H, 1909

IA32_PECI_HWP_REQUEST_INFO

IA32_PECI_HWP_REQUEST_INFO

7:0

Minimum Performance (MINIMUM_PERFORMANCE): Used by OS to read

the latest value of PECI minimum performance input. Default value is 0.

15:8

Maximum Performance (MAXIMUM_PERFORMANCE): Used by OS to read

the latest value of PECI maximum performance input. Default value is 0.

23:16

Reserved.

2-56 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

31:24

Energy Performance Preference

(ENERGY_PERFORMANCE_PREFERENCE): Used by OS to read the latest

value of PECI Energy Performance Preference input. Default value is 0.

59:32

Reserved.

60

EPP PECI Override (EPP_PECI_OVERRIDE):

Indicates whether PECI is currently overriding the Energy Performance

Preference input. If set to ‘1’, PECI is overriding the Energy Performance

Preference input. If clear (0), OS has control over Energy Performance

Preference input. Default value is 0.

61

Reserved.

62

Max PECI Override (MAX_PECI_OVERRIDE):

Indicates whether PECI is currently overriding the Maximum

Performance input. If set to ‘1’, PECI is overriding the Maximum

Performance input. If clear (0), OS has control over Maximum

Performance input. Default value is 0.

63

Min PECI Override (MIN_PECI_OVERRIDE):

Indicates whether PECI is currently overriding the Minimum Performance

input. If set to ‘1’, PECI is overriding the Minimum Performance input. If

clear (0), OS has control over Minimum Performance input. Default value

is 0.

Register Address: 776H, 1910

IA32_HWP_CTL

IA32_HWP_CTL

If CPUID.06H:EAX[22] = 1

0

PKG_CTL_POLARITY

If CPUID.06H:EAX[22] = 1

Defines which HWP Request MSR is used whether Thread level or

package level. When package MSR is used, the thread MSR valid bits

define which thread MSR fields override the package.

Default value is 0.

63:1

Reserved.

Register Address: 777H, 1911

IA32_HWP_STATUS

Log bits indicating changes to Guaranteed & excursions to Minimum (R/W)

If CPUID.06H:EAX[7] = 1

0

Guaranteed_Performance_Change (R/WC0)

If CPUID.06H:EAX[7] = 1

See Section 17.4.5, “HWP Feedback.”

1

Reserved.

2

Excursion_To_Minimum (R/WC0)

If CPUID.06H:EAX[7] = 1

See Section 17.4.5, “HWP Feedback.”

63:3

Reserved.

Register Address: 7A3H, 1955

IA32_MCU_EXT_SERVICE

MCU Extended Service (R/O)

If IA32_ARCH_CAPABILITIES[22] =

1

3:0

ALLOWED_PERIODS

Value indicates the allowed periods for extended servicing. Value x

means that all extended servicing periods are allowed till period x.

63:4

Reserved.

Vol. 4

2-57

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

Register Address: 7A4H, 1956

IA32_MCU_ROLLBACK_MIN_ID

Minimal MCU Revision ID (R/O)

If IA32_MCU_ENUMERATION[3] =

1

Minimal MCU Revision ID that software can rollback to per boot.

31:0

REVISION_ID

Minimal MCU revision ID for rollback.

63:32

Reserved for future use.

Register Address: 7A5H, 1957

IA32_MCU_STAGING_MBOX_ADDR

IA32_MCU_STAGING_MBOX_ADDR (R/O)

Reports MMIO address of MCU staging DOE mailbox.

63:0

ADDR

MMIO address base of MCU staging DOE mailbox.

Register Address: 7B0H, 1968

IA32_ROLLBACK_SIGN_ID_0

Rollback ID 0 (R/O)

If IA32_MCU_ENUMERATION[3] =

1

Holds the Revision ID and SVN of a supported rollback target or 0 if none.

31:0

MCU_ROLLBACK_ID

MCU supported Rollback ID.

47:32

ROLLBACK_MCU_SVN

MCU SVN corresponding to the reported MCU Rollback ID.

63:48

Reserved.

Register Address: 7B1H, 1969

IA32_ROLLBACK_SIGN_ID_1

Rollback ID 1 (R/O)

If IA32_MCU_ENUMERATION[3] =

Holds the Revision ID and SVN of a supported rollback target or 0 if none.

1

31:0

MCU_ROLLBACK_ID

MCU supported Rollback ID.

47:32

ROLLBACK_MCU_SVN

MCU SVN corresponding to the reported MCU Rollback ID.

63:48

Reserved.

Register Address: 7B2H, 1970

IA32_ROLLBACK_SIGN_ID_2

Rollback ID 2 (R/O)

If IA32_MCU_ENUMERATION[3] =

1

Holds the Revision ID and SVN of a supported rollback target or 0 if none.

31:0

MCU_ROLLBACK_ID

MCU supported Rollback ID.

47:32

ROLLBACK_MCU_SVN

MCU SVN corresponding to the reported MCU Rollback ID.

63:48

Reserved.

Register Address: 7B3H, 1971

IA32_ROLLBACK_SIGN_ID_3

Rollback ID 3 (R/O)

If IA32_MCU_ENUMERATION[3] =

1

Holds the Revision ID and SVN of a supported rollback target or 0 if none.

2-58 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

31:0

MCU_ROLLBACK_ID

MCU supported Rollback ID.

47:32

ROLLBACK_MCU_SVN

MCU SVN corresponding to the reported MCU Rollback ID.

63:48

Reserved.

Register Address: 7B4H, 1972

IA32_ROLLBACK_SIGN_ID_4

Rollback ID 4 (R/O)

If IA32_MCU_ENUMERATION[3] =

1

Holds the Revision ID and SVN of a supported rollback target or 0 if none.

31:0

MCU_ROLLBACK_ID

MCU supported Rollback ID.

47:32

ROLLBACK_MCU_SVN

MCU SVN corresponding to the reported MCU Rollback ID.

63:48

Reserved.

Register Address: 7B5H, 1973

IA32_ROLLBACK_SIGN_ID_5

Rollback ID 5 (R/O)

If IA32_MCU_ENUMERATION[3] =

1

Holds the Revision ID and SVN of a supported rollback target or 0 if none.

31:0

MCU_ROLLBACK_ID

MCU supported Rollback ID.

47:32

ROLLBACK_MCU_SVN

MCU SVN corresponding to the reported MCU Rollback ID.

63:48

Reserved.

Register Address: 7B6H, 1974

IA32_ROLLBACK_SIGN_ID_6

Rollback ID 6 (R/O)

If IA32_MCU_ENUMERATION[3] =

Holds the Revision ID and SVN of a supported rollback target or 0 if none.

1

31:0

MCU_ROLLBACK_ID

MCU supported Rollback ID.

47:32

ROLLBACK_MCU_SVN

MCU SVN corresponding to the reported MCU Rollback ID.

63:48

Reserved.

Register Address: 7B7H, 1975

IA32_ROLLBACK_SIGN_ID_7

Rollback ID 7 (R/O)

If IA32_MCU_ENUMERATION[3] =

1

Holds the Revision ID and SVN of a supported rollback target or 0 if none.

31:0

MCU_ROLLBACK_ID

MCU supported Rollback ID.

47:32

ROLLBACK_MCU_SVN

MCU SVN corresponding to the reported MCU Rollback ID.

63:48

Reserved.

Register Address: 7B8H, 1976

IA32_ROLLBACK_SIGN_ID_8

Vol. 4

2-59

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

Rollback ID 8 (R/O)

If IA32_MCU_ENUMERATION[3] =

1

Holds the Revision ID and SVN of a supported rollback target or 0 if none.

31:0

MCU_ROLLBACK_ID

MCU supported Rollback ID.

47:32

ROLLBACK_MCU_SVN

MCU SVN corresponding to the reported MCU Rollback ID.

63:48

Reserved.

Register Address: 7B9H, 1977

IA32_ROLLBACK_SIGN_ID_9

Rollback ID 9 (R/O)

If IA32_MCU_ENUMERATION[3] =

1

Holds the Revision ID and SVN of a supported rollback target or 0 if none.

31:0

MCU_ROLLBACK_ID

MCU supported Rollback ID.

47:32

ROLLBACK_MCU_SVN

MCU SVN corresponding to the reported MCU Rollback ID.

63:48

Reserved.

Register Address: 7BAH, 1978

IA32_ROLLBACK_SIGN_ID_10

Rollback ID 10 (R/O)

If IA32_MCU_ENUMERATION[3] =

1

Holds the Revision ID and SVN of a supported rollback target or 0 if none.

31:0

MCU_ROLLBACK_ID

MCU supported Rollback ID.

47:32

ROLLBACK_MCU_SVN

MCU SVN corresponding to the reported MCU Rollback ID.

63:48

Reserved.

Register Address: 7BBH, 1979

IA32_ROLLBACK_SIGN_ID_11

Rollback ID 11 (R/O)

If IA32_MCU_ENUMERATION[3] =

Holds the Revision ID and SVN of a supported rollback target or 0 if none.

1

31:0

MCU_ROLLBACK_ID

MCU supported Rollback ID.

47:32

ROLLBACK_MCU_SVN

MCU SVN corresponding to the reported MCU Rollback ID.

63:48

Reserved.

Register Address: 7BCH, 1980

IA32_ROLLBACK_SIGN_ID_12

Rollback ID 12 (R/O)

If IA32_MCU_ENUMERATION[3] =

1

Holds the Revision ID and SVN of a supported rollback target or 0 if none.

31:0

MCU_ROLLBACK_ID

MCU supported Rollback ID.

47:32

ROLLBACK_MCU_SVN

MCU SVN corresponding to the reported MCU Rollback ID.

63:48

Reserved.

2-60 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

Register Address: 7BDH, 1981

IA32_ROLLBACK_SIGN_ID_13

Rollback ID 13 (R/O)

If IA32_MCU_ENUMERATION[3] =

1

Holds the Revision ID and SVN of a supported rollback target or 0 if none.

31:0

MCU_ROLLBACK_ID

MCU supported Rollback ID.

47:32

ROLLBACK_MCU_SVN

MCU SVN corresponding to the reported MCU Rollback ID.

63:48

Reserved.

Register Address: 7BEH, 1982

IA32_ROLLBACK_SIGN_ID_14

Rollback ID 14 (R/O)

If IA32_MCU_ENUMERATION[3] =

Holds the Revision ID and SVN of a supported rollback target or 0 if none.

1

31:0

MCU_ROLLBACK_ID

MCU supported Rollback ID.

47:32

ROLLBACK_MCU_SVN

MCU SVN corresponding to the reported MCU Rollback ID.

63:48

Reserved.

Register Address: 7BFH, 1983

IA32_ROLLBACK_SIGN_ID_15

Rollback ID 15 (R/O)

If IA32_MCU_ENUMERATION[3] =

1

Holds the Revision ID and SVN of a supported rollback target or 0 if none.

31:0

MCU_ROLLBACK_ID

MCU supported Rollback ID.

47:32

ROLLBACK_MCU_SVN

MCU SVN corresponding to the reported MCU Rollback ID.

63:48

Reserved.

Register Address: 802H, 2050

IA32_X2APIC_APICID

x2APIC ID Register (R/O)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 803H, 2051

IA32_X2APIC_VERSION

x2APIC Version Register (R/O)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 808H, 2056

IA32_X2APIC_TPR

x2APIC Task Priority Register (R/W)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 80AH, 2058

IA32_X2APIC_PPR

x2APIC Processor Priority Register (R/O)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 80BH, 2059

IA32_X2APIC_EOI

x2APIC EOI Register (W/O)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 80DH, 2061

IA32_X2APIC_LDR

Vol. 4

2-61

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

x2APIC Logical Destination Register (R/O)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 80FH, 2063

IA32_X2APIC_SIVR

x2APIC Spurious Interrupt Vector Register (R/W)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 810H, 2064

IA32_X2APIC_ISR0

x2APIC In-Service Register Bits 31:0 (R/O)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 811H, 2065

IA32_X2APIC_ISR1

x2APIC In-Service Register Bits 63:32 (R/O)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 812H, 2066

IA32_X2APIC_ISR2

x2APIC In-Service Register Bits 95:64 (R/O)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 813H, 2067

IA32_X2APIC_ISR3

x2APIC In-Service Register Bits 127:96 (R/O)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 814H, 2068

IA32_X2APIC_ISR4

x2APIC In-Service Register Bits 159:128 (R/O)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 815H, 2069

IA32_X2APIC_ISR5

x2APIC In-Service Register Bits 191:160 (R/O)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 816H, 2070

IA32_X2APIC_ISR6

x2APIC In-Service Register Bits 223:192 (R/O)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 817H, 2071

IA32_X2APIC_ISR7

x2APIC In-Service Register Bits 255:224 (R/O)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 818H, 2072

IA32_X2APIC_TMR0

x2APIC Trigger Mode Register Bits 31:0 (R/O)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 819H, 2073

IA32_X2APIC_TMR1

x2APIC Trigger Mode Register Bits 63:32 (R/O)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 81AH, 2074

IA32_X2APIC_TMR2

x2APIC Trigger Mode Register Bits 95:64 (R/O)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 81BH, 2075

IA32_X2APIC_TMR3

x2APIC Trigger Mode Register Bits 127:96 (R/O)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 81CH, 2076

IA32_X2APIC_TMR4

2-62 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

x2APIC Trigger Mode Register Bits 159:128 (R/O)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 81DH, 2077

IA32_X2APIC_TMR5

x2APIC Trigger Mode Register Bits 191:160 (R/O)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 81EH, 2078

IA32_X2APIC_TMR6

x2APIC Trigger Mode Register Bits 223:192 (R/O)

If ( CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1)

Register Address: 81FH, 2079

IA32_X2APIC_TMR7

x2APIC Trigger Mode Register Bits 255:224 (R/O)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 820H, 2080

IA32_X2APIC_IRR0

x2APIC Interrupt Request Register Bits 31:0 (R/O)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 821H, 2081

IA32_X2APIC_IRR1

x2APIC Interrupt Request Register Bits 63:32 (R/O)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 822H, 2082

IA32_X2APIC_IRR2

x2APIC Interrupt Request Register Bits 95:64 (R/O)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 823H, 2083

IA32_X2APIC_IRR3

x2APIC Interrupt Request Register Bits 127:96 (R/O)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 824H, 2084

IA32_X2APIC_IRR4

x2APIC Interrupt Request Register Bits 159:128 (R/O)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 825H, 2085

IA32_X2APIC_IRR5

x2APIC Interrupt Request Register Bits 191:160 (R/O)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 826H, 2086

IA32_X2APIC_IRR6

x2APIC Interrupt Request Register Bits 223:192 (R/O)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 827H, 2087

IA32_X2APIC_IRR7

x2APIC Interrupt Request Register Bits 255:224 (R/O)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 828H, 2088

IA32_X2APIC_ESR

x2APIC Error Status Register (R/W)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 82FH, 2095

IA32_X2APIC_LVT_CMCI

x2APIC LVT Corrected Machine Check Interrupt Register (R/W)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 830H, 2096

IA32_X2APIC_ICR

Vol. 4

2-63

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

x2APIC Interrupt Command Register (R/W)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 832H, 2098

IA32_X2APIC_LVT_TIMER

x2APIC LVT Timer Interrupt Register (R/W)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 833H, 2099

IA32_X2APIC_LVT_THERMAL

x2APIC LVT Thermal Sensor Interrupt Register (R/W)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 834H, 2100

IA32_X2APIC_LVT_PMI

x2APIC LVT Performance Monitor Interrupt Register (R/W)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 835H, 2101

IA32_X2APIC_LVT_LINT0

x2APIC LVT LINT0 Register (R/W)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 836H, 2102

IA32_X2APIC_LVT_LINT1

x2APIC LVT LINT1 Register (R/W)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 837H, 2103

IA32_X2APIC_LVT_ERROR

x2APIC LVT Error Register (R/W)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 838H, 2104

IA32_X2APIC_INIT_COUNT

x2APIC Initial Count Register (R/W)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 839H, 2105

IA32_X2APIC_CUR_COUNT

x2APIC Current Count Register (R/O)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 83EH, 2110

IA32_X2APIC_DIV_CONF

x2APIC Divide Configuration Register (R/W)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 83FH, 2111

IA32_X2APIC_SELF_IPI

x2APIC Self IPI Register (W/O)

If CPUID.01H:ECX[21] = 1 &&

IA32_APIC_BASE.[10] = 1

Register Address: 981H, 2433

IA32_TME_CAPABILITY

Memory Encryption Capability MSR

If CPUID.07H.00H:ECX[13] = 1

0

Support for AES-XTS 128-bit encryption algorithm.

(NIST standard)

1

Support for AES-XTS 128-bit encryption with integrity algorithm.

2

Support for AES-XTS 256-bit encryption algorithm.

3

Support for AES-XTS 256-bit encryption with integrity algorithm.

27:4

Reserved.

2-64 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

28

Non-zero KeyIDs must be SEAM-private.

If set, any write to

IA32_TME_ACTIVATE must write

identical values to

MK_TME_KEYID_BITS and

TDX_RESERVED_KEYID_BITS.

29

Reserved.

30

SUPPORT_IA32_TME_CLEAR_SAVED_KEY

Support for the IA32_TME_CLEAR_SAVED_KEY MSR.

31

TME encryption bypass supported.

35:32

MK_TME_MAX_KEYID_BITS

Number of bits which can be allocated for usage as key identifiers for

multi-key memory encryption.

4 bits allow for a maximum value of 15, which could address 32K keys.

Zero if TME-MK is not supported.

50:36

MK_TME_MAX_KEYS

Indicates the maximum number of keys which are available for usage.

This value may not be a power of 2.

KeyID 0 is specially reserved and is not accounted for in this field.

63:51

Reserved.

Register Address: 982H, 2434

IA32_TME_ACTIVATE

Memory Encryption Activation MSR

If CPUID.07H.00H:ECX[13] = 1

This MSR is used to lock the MSRs listed below. Any write to the following MSRs will be ignored

after they are locked. The lock is reset when CPU is reset.

• IA32_TME_ACTIVATE

• IA32_TME_EXCLUDE_MASK

• IA32_TME_EXCLUDE_BASE

Note that IA32_TME_EXCLUDE_MASK and IA32_TME_EXCLUDE_BASE must be configured before

IA32_TME_ACTIVATE.

0

Lock R/O - Will be set upon successful WRMSR (or first SMI); written

value ignored.

1

Hardware Encryption Enable

This bit also enables TME-MK; TME-MK cannot be enabled without

enabling encryption hardware.

TME is enabled depending on the TME Encryption Bypass Enable bit (bit

31).

2

Key Select

0: Create a new TME key (expected cold/warm boot).

1: Restore the TME key from storage (expected when resume from

standby).

3

Save TME Key for Standby

Save key into storage to be used when resume from standby.

Note: This may not be supported in all processors.

Vol. 4

2-65

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

7:4

TME Policy/Encryption Algorithm

Only algorithms enumerated in IA32_TME_CAPABILITY MSR are allowed.

Any other values are invalid and will result in #GP.

Additionally, any algorithm that supports integrity checking is not

allowed to be used for TME even if it is listed as allowed in the

IA32_TME_CAPABILITY MSR and will result in #GP.

30:8

Reserved.

31

TME Encryption Bypass Enable

When encryption hardware is enabled:

• Total Memory Encryption is enabled using a CPU generated ephemeral

key based on a hardware random number generator when this bit is

set to 0.

• Total Memory Encryption is bypassed (no encryption/decryption for

KeyID0) when this bit is set to 1. On some processors, bypassing TME

encryption can provide performance benefits to accesses made with

KeyID 0 by avoiding the latency of decryption or encryption and

decryption.

Software must inspect Hardware Encryption Enable (bit 1) and TME

Encryption Bypass Enable (bit 31) to determine if TME encryption is

enabled.

35:32

MK_TME_KEYID_BITS

Reserved if TME-MK is not enumerated, otherwise:

The number of key identifier bits to allocate to TME-MK usage. Similar to

enumeration, this is an encoded value.

Writing a value greater than MK_TME_MAX_KEYID_BITS will result in

#GP.

Writing a non-zero value to this field will #GP if bit 1 of EAX (Hardware

Encryption Enable) is not also set to 1, as encryption hardware must be

enabled to use TME-MK.

Example: To support 255 keys, this field would be set to a value of 8.

39:36

TDX_RESERVED_KEYID_BITS

If IA32_TME_CAPABILITY[28] = 1,

this value must be the same as

The number of key identifier bits to allocate to TDX usage, which are

that of MK_TME_KEYID_BITS.

allocated from the most significant bit downward.

Writing a value greater than MK_TME_KEYID_BITS will result in a #GP.

Note: These bits are a subset of the overall KeyID bits which are declared

by MK_TME_MAX_KEYID_BITS.

47:40

Reserved.

63:48

MK_TME_CRYPTO_ALGS

Reserved if TME-MK is not enumerated, otherwise:

Bit 48: AES-XTS 128.

Bit 49: AES-XTS 128 with integrity.

Bit 50: AES-XTS 256.

Bit 51: AES-XTS-256 with integrity.

Bit 63:52: Reserved (#GP)

Bitmask for BIOS to set which encryption algorithms are allowed for

TME-MK, would be later enforced by the key loading ISA (‘1 = allowed).

Register Address: 983H, 2435

IA32_TME_EXCLUDE_MASK

2-66 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

Memory Encryption Exclude Mask

If CPUID.07H.00H:ECX[13] = 1

The IA32_TME_EXCLUDE_MASK MSR must define a contiguous region. WRMSR will #GP if the

TMEEMASK field does not specify a contiguous region.

This MSRs is locked by the IA32_TME_ACTIVATE MSR. If lock=1, then WRMSR to

IA32_TME_EXCLUDE_MASK/IA32_TME_EXCLUDE_BASE MSRs will result in #GP.

10:0

Reserved.

11

Enable: When set to ‘1’, then TME_EXCLUDE_BASE and

TME_EXCLUDE_MASK are used to define an exclusion region for

TME/TME-MK (for KeyID=0).

MAXPHYADDR-1:12

TMEEMASK: This field indicates the bits that must match TMEEBASE in

order to qualify as a TME/TME-MK (for KeyID=0) exclusion memory range

access.

63:MAXPHYADDR

Reserved; must be zero.

Register Address: 984H, 2436

IA32_TME_EXCLUDE_BASE

Memory Encryption Exclude Base

IF CPUID.07H.00H:ECX[13] = 1

Note: Writing ‘1’ into bits greater than the max supported physical size will result in #GP.

This MSRs is locked by the IA32_TME_ACTIVATE MSR. If lock=1, then WRMSR to

IA32_TME_EXCLUDE_MASK/IA32_TME_EXCLUDE_BASE MSRs will result in #GP.

11:0

Reserved.

MAXPHYADDR-1:12

TMEEBASE: Base physical address to be excluded for TME/TME-MK (for

KeyID=0) encryption.

63:MAXPHYADDR

Reserved; must be zero.

Register Address: 985H, 2437

IA32_UINTR_RR

User Interrupt Request Register (R/W)

IF CPUID.07H.01H:EDX[13] = 1

63:0

UIRR

Bitmap of requested user interrupt vectors.

Register Address: 986H, 2438

IA32_UINTR_HANDLER

User Interrupt Handler Address (R/W)

IF CPUID.07H.01H:EDX[13] = 1

63:0

UIHANDLER

User interrupt handler linear address.

Register Address: 987H, 2439

IA32_UINTR_STACKADJUST

User Interrupt Stack Adjustment (R/W)

IF CPUID.07H.01H:EDX[13] = 1

0

LOAD_RSP

User interrupt stack mode.

2:1

Reserved.

63:3

STACK_ADJUST

Stack adjust value.

Register Address: 988H, 2440

IA32_UINTR_MISC

User-Interrupt Target-Table Size and Notification Vector (R/W)

If CPUID.07H.01H:EDX[13] = 1

Vol. 4

2-67

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

31:0

UITTSZ

The highest index of a valid entry in the user-interrupt target table. Valid

entries are indices 0..UITTSZ (inclusive).

39:32

UINV

User-interrupt notification vector.

63:40

Reserved.

Register Address: 989H, 2441

IA32_UINTR_PD

User Interrupt PID Address (R/W)

If CPUID.07H.01H:EDX[13] = 1

5:0

Reserved.

63:6

UPIDADDR

User-interrupt notification processing accesses a UPID at this linear

address.

Register Address: 98AH, 2442

IA32_UINTR_TT

User-Interrupt Target Table (R/W)

If CPUID.07H.01H:EDX[13] = 1

0

SENDUIPI_ENABLE

User-interrupt target table is valid.

3:1

Reserved.

63:4

UITTADDR

User-interrupt target table base linear address.

Register Address: 990H, 2448

IA32_COPY_STATUS⁴

Status of Most Recent Platform to Local or Local to Platform Copies (R/O)

If ((CPUID.19H:EBX[4] = 1) &&

(CPUID.07H.00H:ECX[23] = 1))

0

IWKEY_COPY_SUCCESSFUL

If ((CPUID.19H:EBX[4] = 1) &&

Status of most recent copy to or from IWKeyBackup.

(CPUID.07H.00H:ECX[23] = 1))

63:1

Reserved.

Register Address: 991H, 2449

IA32_IWKEYBACKUP_STATUS⁵

Information about IWKeyBackup Register (R/O)

If ((CPUID.19H:EBX[4] = 1) &&

(CPUID.07H.00H:ECX[23] = 1))

0

Backup/Restore Valid

IF ((CPUID.19H:EBX[4] = 1) &&

(CPUID.07H.00H:ECX[23] = 1))

Cleared when a write to IWKeyBackup is initiated, and then set when the

latest write of IWKeyBackup has been written to storage that persists

across S3/S4 sleep state. If S3/S4 is entered between when an

IWKeyBackup write occurs and when this bit is set, then IWKeyBackup

may not be recovered after S3/S4 exit. During S3/S4 sleep state exit

(system wake up), this bit is cleared. It is set again when IWKeyBackup is

restored from persistent storage and thus available to be copied to

IWKey using IA32_COPY_PLATFORM_TO_LOCAL MSR. Another write to

IWKeyBackup (via IA32_COPY_LOCAL_TO_PLATFORM MSR) may fail if a

previous write has not yet set this bit.

1

Reserved.

2

Backup Key Storage Read/Write Error

IF ((CPUID.19H:EBX[4] = 1) &&

(CPUID.07H.00H:ECX[23] = 1))

Updated prior to backup/restore valid being set. Set when an error is

encountered while backing up or restoring a key to persistent storage.

2-68 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

3

IWKeyBackup Consumed

IF ((CPUID.19H:EBX[4] = 1) &&

(CPUID.07H.00H:ECX[23] = 1))

Set after the previous backup operation has been consumed by the

platform. This does not indicate that the system is ready for a second

IWKeyBackup write as the previous IWKeyBackup write may still need to

set Backup/restore valid.

63:4

Reserved.

Register Address: 9F1H, 2545

IA32_TSE_CAPABILITY

IA32_TSE_CAPABILITY

If CPUID.07H.01H:EBX.PBNDKB[1]

= 1

15:0

Supported encryption algorithms.

23:16

TSE engine key sources supported.

35:24

Reserved.

50:36

TSE_MAX_KEYS. Indicates the maximum number of keys available.

63:51

Reserved.

Register Address: 9FBH, 2555

IA32_TME_CLEAR_SAVED_KEY

IA32_TME_CLEAR_SAVED_KEY (W/O)

0

TME_CLEAR_SAVED_KEY

Clear saved TME keys.

63:1

Reserved.

Register Address: C80H, 3200

IA32_DEBUG_INTERFACE

Silicon Debug Feature Control (R/W)

If CPUID.01H:ECX[11] = 1

0

Enable (R/W)

If CPUID.01H:ECX[11] = 1

BIOS set 1 to enable Silicon debug features. Default is 0.

29:1

Reserved.

30

Lock (R/W): If 1, locks any further change to the MSR. The lock bit is set

If CPUID.01H:ECX[11] = 1

automatically on the first SMI assertion even if not explicitly set by BIOS.

Default is 0.

31

Debug Occurred (R/O): This “sticky bit” is set by hardware to indicate the

If CPUID.01H:ECX[11] = 1

status of bit 0. Default is 0.

63:32

Reserved.

Register Address: C81H, 3201

IA32_L3_QOS_CFG

L3 QOS Configuration (R/W)

If (CPUID.10H.01H:ECX[2] = 1)

0

Enable (R/W)

Set 1 to enable L3 CAT masks and CLOS to operate in Code and Data

Prioritization (CDP) mode.

63:1

Reserved. Attempts to write to reserved bits result in a #GP(0).

Register Address: C82H, 3202

IA32_L2_QOS_CFG

L2 QOS Configuration (R/W)

If (CPUID.10H.02H:ECX[2] = 1)

0

Enable (R/W)

Set 1 to enable L2 CAT masks and CLOS to operate in Code and Data

Prioritization (CDP) mode.

Vol. 4

2-69

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

63:1

Reserved. Attempts to write to reserved bits result in a #GP(0).

Register Address: C83H, 3203

IA32_L3_IO_QOS_CFG

L3 I/O QOS Configuration (R/W)

If (CPUID.0FH.01H:EAX[10:9] = 1)

This MSR is used to enable the I/O RDT features.

0

L3 I/O RDT Allocation Enable.

1

L3 I/O RDT Monitoring Enable.

63:2

Reserved.

Register Address: C88H, 3208

IA32_RESOURCE_PRIORITY

Thread Scope Resource Priority Enable (R/W)

If CPUID.10H.06H:EAX[0] = 1

Cleared at system reset.

0

ENABLE

When set for all logical processors, enables the Resource Priority

feature.

63:1

Reserved.

Register Address: C89H, 3209

IA32_RESOURCE_PRIORITY_PKG

Package Scope Resource Priority Enable (R/W)

If CPUID.10H.06H:EAX[1] = 1

Cleared at system reset.

0

ENABLE

When set for each package, enables Resource Priority feature.

63:1

Reserved.

Register Address: C8DH, 3213

IA32_QM_EVTSEL

Monitoring Event Select Register (R/W)

If (CPUID.07H.00H:EBX[12] = 1)

7:0

Event ID: ID of a supported monitoring event to report via IA32_QM_CTR.

31: 8

Reserved.

N+31:32

Resource Monitoring ID: ID for monitoring hardware to report monitored

N = Ceil (Log₂

data via IA32_QM_CTR.

(CPUID.0FH.00H:EBX[31:0] +1))

63:N+32

Reserved.

Register Address: C8EH, 3214

IA32_QM_CTR

Monitoring Counter Register (R/O)

If (CPUID.07H.00H:EBX[12] = 1)

61:0

Resource Monitored Data.

62

Unavailable: If 1, indicates data for this RMID is not available or not

monitored for this resource or RMID.

63

Error: If 1, indicates an unsupported RMID or event type was written to

IA32_PQR_QM_EVTSEL.

Register Address: C8FH, 3215

IA32_PQR_ASSOC

Resource Association Register (R/W)

If ((CPUID.07H.00H:EBX[12] = 1)

or (CPUID.07H.00H:EBX[15] = 1))

N-1:0

Resource Monitoring ID (R/W): ID for monitoring hardware to track

N = Ceil (Log₂

internal operation, e.g., memory access.

(CPUID.0FH.00H:EBX[31:0] +1))

31:N

Reserved.

2-70 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

M:32

CLOS (R/W): The class of service (CLOS) to enforce (on writes); returns

CLOS_MAX = max of all valid RDT

the current CLOS when read.

Allocation ResID.EDX[15:0] sub-

leaves

CLOS_WIDTH =

Ceil(Log2(CLOS_MAX +1))

M = (32 + CLOS_WIDTH -1)

63:M+1+32

Reserved.

Register Address: C90H-D8FH, 3216-3471

Reserved MSR Address Space for CAT Mask Registers

See Section 20.19.4.1, “Enumeration and Detection Support of Cache Allocation Technology.”

Register Address: C90H, 3216

IA32_L3_MASK_0

L3 CAT Mask for COS0 (R/W)

If (CPUID.10H.00H:EBX[1] != 0)

31:0

Capacity Bit Mask (R/W)

63:32

Reserved.

Register Address: C90H+n, 3216+n

IA32_L3_MASK_n

L3 CAT Mask for COSn (R/W)

n = CPUID.10H.01H:EDX[15:0]

31:0

Capacity Bit Mask (R/W)

63:32

Reserved.

Register Address: D10H-D4FH, 3344-3407

Reserved MSR Address Space for L2 CAT Mask Registers

See Section 20.19.4.1, “Enumeration and Detection Support of Cache Allocation Technology.”

Register Address: D10H, 3344

IA32_L2_MASK_0

L2 CAT Mask for COS0 (R/W)

If (CPUID.10H.00H:EBX[2] != 0)

31:0

Capacity Bit Mask (R/W)

63:32

Reserved.

Register Address: D10H+n, 3344+n

IA32_L2_MASK_n

L2 CAT Mask for COSn (R/W)

n = CPUID.10H.02H:EDX[15:0]

31:0

Capacity Bit Mask (R/W)

63:32

Reserved.

Register Address: D18H, 3352

IA32_L2_MASK_8

L2 CAT Mask for COS8 (R/W)

15:0

WAY_MASK

Capacity Bit Mask. Available ways vectors for class of service of IA core.

'1 in bit indicates allocation to the way is allowed. '0 indicates allocation

to the way is not allowed.

63:16

Reserved.

Register Address: D19H, 3353

IA32_L2_MASK_9

L2 CAT Mask for COS9 (R/W)

See IA32_L2_MASK_8 (D18H) for reference; similar format.

Register Address: D1AH, 3354

IA32_L2_MASK_10

Vol. 4

2-71

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

L2 CAT Mask for COS10 (R/W)

See IA32_L2_MASK_8 (D18H) for reference; similar format.

Register Address: D1BH, 3355

IA32_L2_MASK_11

L2 CAT Mask for COS11 (R/W)

See IA32_L2_MASK_8 (D18H) for reference; similar format.

Register Address: D1CH, 3356

IA32_L2_MASK_12

L2 CAT Mask for COS12 (R/W)

See IA32_L2_MASK_8 (D18H) for reference; similar format.

Register Address: D1DH, 3357

IA32_L2_MASK_13

L2 CAT Mask for COS13 (R/W)

See IA32_L2_MASK_8 (D18H) for reference; similar format.

Register Address: D1EH, 3358

IA32_L2_MASK_14

L2 CAT Mask for COS14 (R/W)

See IA32_L2_MASK_8 (D18H) for reference; similar format.

Register Address: D1FH, 3359

IA32_L2_MASK_15

L2 CAT Mask for COS15 (R/W)

See IA32_L2_MASK_8 (D18H) for reference; similar format.

Register Address: D50H, 3408

IA32_L2_QOS_EXT_BW_THRTL_0

IA32_L2_QOS_EXT_BW_THRTL_0 (R/W)

CPUID.10H.00H:EBX[3] and

Memory Bandwidth enforcement for COS0.

CPUID.10H.03H:EDX ≥ 0

6:0

RBE_ENFORCEMENT_VAL

Max Delay value cannot be greater than 90 percent - 0x5a.

63:7

Reserved.

Register Address: D51H, 3409

IA32_L2_QOS_EXT_BW_THRTL_1

IA32_L2_QOS_EXT_BW_THRTL_1 (R/W)

CPUID.10H.00H:EBX[3] and

CPUID.10H.03H:EDX ≥ 1

Memory Bandwidth enforcement for COS1.

6:0

RBE_ENFORCEMENT_VAL

Max Delay value cannot be greater than 90 percent - 0x5a.

63:7

Reserved.

Register Address: D52H, 3410

IA32_L2_QOS_EXT_BW_THRTL_2

IA32_L2_QOS_EXT_BW_THRTL_2 (R/W)

CPUID.10H.00H:EBX[3] and

CPUID.10H.03H:EDX ≥ 2

Memory Bandwidth enforcement for COS2.

6:0

RBE_ENFORCEMENT_VAL

Max Delay value cannot be greater than 90 percent - 0x5a.

63:7

Reserved.

Register Address: D53H, 3411

IA32_L2_QOS_EXT_BW_THRTL_3

IA32_L2_QOS_EXT_BW_THRTL_3 (R/W)

CPUID.10H.00H:EBX[3] and

Memory Bandwidth enforcement for COS3.

CPUID.10H.03H:EDX ≥ 3

2-72 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

6:0

RBE_ENFORCEMENT_VAL

Max Delay value cannot be greater than 90 percent - 0x5a.

63:7

Reserved.

Register Address: D54H, 3412

IA32_L2_QOS_EXT_BW_THRTL_4

IA32_L2_QOS_EXT_BW_THRTL_4 (R/W)

CPUID.10H.00H:EBX[3] and

CPUID.10H.03H:EDX ≥ 4

Memory Bandwidth enforcement for COS4.

6:0

RBE_ENFORCEMENT_VAL

Max Delay value cannot be greater than 90 percent - 0x5a.

63:7

Reserved.

Register Address: D55H, 3413

IA32_L2_QOS_EXT_BW_THRTL_5

IA32_L2_QOS_EXT_BW_THRTL_5 (R/W)

CPUID.10H.00H:EBX[3] and

CPUID.10H.03H:EDX ≥ 5

Memory Bandwidth enforcement for COS5.

6:0

RBE_ENFORCEMENT_VAL

Max Delay value cannot be greater than 90 percent - 0x5a.

63:7

Reserved.

Register Address: D56H, 3414

IA32_L2_QOS_EXT_BW_THRTL_6

IA32_L2_QOS_EXT_BW_THRTL_6 (R/W)

CPUID.10H.00H:EBX[3] and

Memory Bandwidth enforcement for COS6.

CPUID.10H.03H:EDX ≥ 6

6:0

RBE_ENFORCEMENT_VAL

Max Delay value cannot be greater than 90 percent - 0x5a.

63:7

Reserved.

Register Address: D57H, 3415

IA32_L2_QOS_EXT_BW_THRTL_7

IA32_L2_QOS_EXT_BW_THRTL_7 (R/W)

CPUID.10H.00H:EBX[3] and

CPUID.10H.03H:EDX ≥ 7

Memory Bandwidth enforcement for COS7.

6:0

RBE_ENFORCEMENT_VAL

Max Delay value cannot be greater than 90 percent - 0x5a.

63:7

Reserved.

Register Address: D58H, 3416

IA32_L2_QOS_EXT_BW_THRTL_8

IA32_L2_QOS_EXT_BW_THRTL_8 (R/W)

CPUID.10H.00H:EBX[3] and

CPUID.10H.03H:EDX ≥ 8

Memory Bandwidth enforcement for COS8.

6:0

RBE_ENFORCEMENT_VAL

Max Delay value cannot be greater than 90 percent - 0x5a.

63:7

Reserved.

Register Address: D59H, 3417

IA32_L2_QOS_EXT_BW_THRTL_9

IA32_L2_QOS_EXT_BW_THRTL_9 (R/W)

CPUID.10H.00H:EBX[3] and

Memory Bandwidth enforcement for COS9.

CPUID.10H.03H:EDX ≥ 9

6:0

RBE_ENFORCEMENT_VAL

Max Delay value cannot be greater than 90 percent - 0x5a.

63:7

Reserved.

Vol. 4

2-73

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

Register Address: D5AH, 3418

IA32_L2_QOS_EXT_BW_THRTL_10

IA32_L2_QOS_EXT_BW_THRTL_10 (R/W)

CPUID.10H.00H:EBX[3] and

CPUID.10H.03H:EDX ≥ 10

Memory Bandwidth enforcement for COS10.

6:0

RBE_ENFORCEMENT_VAL

Max Delay value cannot be greater than 90 percent - 0x5a.

63:7

Reserved.

Register Address: D5BH, 3419

IA32_L2_QOS_EXT_BW_THRTL_11

IA32_L2_QOS_EXT_BW_THRTL_11 (R/W)

CPUID.10H.00H:EBX[3] and

Memory Bandwidth enforcement for COS11.

CPUID.10H.03H:EDX ≥ 11

6:0

RBE_ENFORCEMENT_VAL

Max Delay value cannot be greater than 90 percent - 0x5a.

63:7

Reserved.

Register Address: D5CH, 3420

IA32_L2_QOS_EXT_BW_THRTL_12

IA32_L2_QOS_EXT_BW_THRTL_12 (R/W)

CPUID.10H.00H:EBX[3] and

CPUID.10H.03H:EDX ≥ 12

Memory Bandwidth enforcement for COS12.

6:0

RBE_ENFORCEMENT_VAL

Max Delay value cannot be greater than 90 percent - 0x5a.

63:7

Reserved.

Register Address: D5DH, 3421

IA32_L2_QOS_EXT_BW_THRTL_13

IA32_L2_QOS_EXT_BW_THRTL_13 (R/W)

CPUID.10H.00H:EBX[3] and

CPUID.10H.03H:EDX ≥ 13

Memory Bandwidth enforcement for COS13.

6:0

RBE_ENFORCEMENT_VAL

Max Delay value cannot be greater than 90 percent - 0x5a.

63:7

Reserved.

Register Address: D5EH, 3422

IA32_L2_QOS_EXT_BW_THRTL_14

IA32_L2_QOS_EXT_BW_THRTL_14 (R/W)

CPUID.10H.00H:EBX[3] and

Memory Bandwidth enforcement for COS14.

CPUID.10H.03H:EDX ≥ 14

6:0

RBE_ENFORCEMENT_VAL

Max Delay value cannot be greater than 90 percent - 0x5a.

63:7

Reserved.

Register Address: D90H, 3472

IA32_BNDCFGS

Supervisor State of MPX Configuration (R/W)

If (CPUID.07H.00H:EBX[14] = 1)

0

EN: Enable Intel MPX in supervisor mode.

1

BNDPRESERVE: Preserve the bounds registers for near branch

instructions in the absence of the BND prefix.

11:2

Reserved, must be zero.

63:12

Base Address of Bound Directory.

Register Address: D91H, 3473

IA32_COPY_LOCAL_TO_PLATFORM⁵

2-74 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

Copy Local State to Platform State (W)

IF ((CPUID.19H:EBX[4] = 1) &&

(CPUID.07H.00H:ECX[23] = 1))

0

IWKeyBackup

IF ((CPUID.19H:EBX[4] = 1) &&

(CPUID.07H.00H:ECX[23] = 1))

Copy IWKey to IWKeyBackup.

63:1

Reserved.

Register Address: D92H, 3474

IA32_COPY_PLATFORM_TO_LOCAL⁵

Copy Platform State to Local State (W)

IF ((CPUID.19H:EBX[4] = 1) &&

(CPUID.07H.00H:ECX[23] = 1))

0

IWKeyBackup

IF ((CPUID.19H:EBX[4] = 1) &&

(CPUID.07H.00H:ECX[23] = 1))

Copy IWKeyBackup to IWKey.

63:1

Reserved.

Register Address: D93H, 3475

IA32_PASID

Process Address Space Identifier. (R/W)

19:0

Process address space identifier (PASID). Specifies the PASID of the

currently running software thread.

30:20

Reserved.

31

Valid. Execution of ENQCMD causes a #GP if this bit is clear.

63:32

Reserved.

Register Address: DA0H, 3488

IA32_XSS

Extended Supervisor State Mask (R/W)

If( CPUID.0DH.01H:EAX[3] = 1

7:0

Reserved.

8

PT State (R/W)

9

Reserved.

10

PASID State (R/W)

11

CET_U State (R/W)

12

CET_S State (R/W)

13

HDC State (R/W)

14

UINTR State (R/W)

15

LBR State (R/W)

16

HWP State (R/W)

63:17

Reserved.

Register Address: DB0H, 3504

IA32_PKG_HDC_CTL

Package Level Enable/Disable HDC (R/W)

If CPUID.06H:EAX[13] = 1

0

HDC_Pkg_Enable (R/W)

If CPUID.06H:EAX[13] = 1

Force HDC idling or wake up HDC-idled logical processors in the package.

See Section 17.5.2, “Package level Enabling HDC.”

63:1

Reserved.

Register Address: DB1H, 3505

IA32_PM_CTL1

Enable/Disable the HDC Thread Level Activity (R/W)

If CPUID.06H:EAX[13] = 1

Vol. 4

2-75

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Register Address: Hex, Decimal

Architectural MSR Name (Former MSR Name)

Bit Fields

MSR/Bit Description

Comment

0

SDC_ALLOWED (R/W)

If CPUID.06H:EAX[13] = 1

Set this bit to allow this thread to be forced into HDC idle state. Clearing

this bit blocks HDC-enter (HW) request. Default value: 1. See Section

17.5.3.

63:1

Reserved.

Register Address: DB2H, 3506

IA32_THREAD_STALL

Per-Logical_Processor_ID HDC Idle Residency (R/0)

If CPUID.06H:EAX[13] = 1

63:0

Stall_Cycle_Cnt (R/W)

If CPUID.06H:EAX[13] = 1

Stalled cycles due to HDC forced idle on this logical processor. See

Section 17.5.4.1.

Register Address: E00H, 3584

IA32_QOS_CORE_BW_THRTL_0

CBA Levels Based on COS for Bandwidth Throttling (R/W)

CPUID.10H.00H:EBX[5] = 1

3:0

COS0_LEVEL

CBA Level for COS[0]. Levels are programmed from 0 to 15.

7:4

Reserved.

11:8

COS1_LEVEL

CBA Level for COS[1]. Levels are programmed from 0 to 15.

15:12

Reserved.

19:16

COS2_LEVEL

CBA Level for COS[2]. Levels are programmed from 0 to 15.

25:20

Reserved.

27:24

COS3_LEVEL

CBA Level for COS[3]. Levels are programmed from 0 to 15.

31:28

Reserved.

35:32

COS4_LEVEL

CBA Level for COS[4]. Levels are programmed from 0 to 15.

39:36

Reserved.

43:40

COS5_LEVEL

CBA Level for COS[5]. Levels are programmed from 0 to 15.

47:44

Reserved.

51:48

COS6_LEVEL

CBA Level for COS[6]. Levels are programmed from 0 to 15.

Register Address: E01H, 3585

IA32_QOS_CORE_BW_THRTL_1

CBA Levels Based on COS for Bandwidth Throttling (R/W)

CPUID.10H.00H:EBX[5] = 1

3:0

COS8_LEVEL

CBA Level for COS[8]. Levels are programmed from 0 to 15.

7:4

Reserved.

11:8

COS9_LEVEL

CBA Level for COS[9]. Levels are programmed from 0 to 15.

15:12

Reserved.

2-76 Vol. 4