Intel 64 and IA-32 Architectures. Software Developer’s Manual (2026)

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Shared/

Bit Description

Unique

Reserved.

1 MByte Power on Reset Vector (R/O)

1 = 1 MByte; 0 = 4 GBytes.

Reserved.

17:16

APIC Cluster ID (R/O)

N/2 Non-Integer Bus Ratio (R/O)

0 = Integer ratio; 1 = Non-integer ratio.

Reserved.

21: 20

Symmetric Arbitration ID (R/O)

26:22

Integer Bus Frequency Ratio (R/O)

MSR_FEATURE_CONTROL

Control Features in Intel 64 Processor (R/W)

Unique

See Table 2-2.

SMRR Enable (R/WL)

Unique

When this bit is set and the lock bit is set, this makes the SMRR_PHYS_BASE

and SMRR_PHYS_MASK registers read visible and writeable while in SMM.

MSR_LASTBRANCH_0_FROM_IP

Last Branch Record 0 From IP (R/W)

Unique

One of four pairs of last branch record registers on the last branch record stack. The From_IP part of the stack

contains pointers to the source instruction. See also:

• Last Branch Record Stack TOS at 1C9H.

• Section 20.5.

MSR_LASTBRANCH_1_FROM_IP

Last Branch Record 1 From IP (R/W)

Unique

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_2_FROM_IP

Last Branch Record 2 From IP (R/W)

Unique

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_3_FROM_IP

Last Branch Record 3 From IP (R/W)

Unique

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_0_TO_IP

Last Branch Record 0 To IP (R/W)

Unique

One of four pairs of last branch record registers on the last branch record stack. This To_IP part of the stack contains

pointers to the destination instruction.

MSR_LASTBRANCH_1_TO_IP

Last Branch Record 1 To IP (R/W)

Unique

See description of MSR_LASTBRANCH_0_TO_IP.

2-96 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Shared/

Bit Description

Unique

MSR_LASTBRANCH_2_TO_IP

Last Branch Record 2 To IP (R/W)

Unique

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_3_TO_IP

Last Branch Record 3 To IP (R/W)

Unique

See description of MSR_LASTBRANCH_0_TO_IP.

IA32_BIOS_UPDT_TRIG

BIOS Update Trigger Register (W)

Unique

See Table 2-2.

IA32_BIOS_SIGN_ID

BIOS Update Signature ID (R/W)

Unique

See Table 2-2.

MSR_SMRR_PHYSBASE

System Management Mode Base Address register (WO in SMM)

Unique

Model-specific implementation of SMRR-like interface, read visible and write only in SMM.

11:0

Reserved.

31:12

PhysBase: SMRR physical Base Address.

63:32

Reserved.

MSR_SMRR_PHYSMASK

System Management Mode Physical Address Mask register (WO in SMM)

Unique

Model-specific implementation of SMRR-like interface, read visible and write only in SMM.

10:0

Reserved.

Valid: Physical address base and range mask are valid.

31:12

PhysMask: SMRR physical address range mask.

63:32

Reserved.

IA32_PMC0

Performance Counter Register

Unique

See Table 2-2.

IA32_PMC1

Performance Counter Register

Unique

See Table 2-2.

MSR_FSB_FREQ

Scaleable Bus Speed (R/O)

Shared

This field indicates the intended scalable bus clock speed for processors based on Intel Core microarchitecture.

Vol. 4

2-97

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Shared/

Bit Description

Unique

2:0

•

101B: 100 MHz (FSB 400)

•

001B: 133 MHz (FSB 533)

•

011B: 167 MHz (FSB 667)

•

010B: 200 MHz (FSB 800)

•

000B: 267 MHz (FSB 1067)

•

100B: 333 MHz (FSB 1333)

133.33 MHz should be utilized if performing calculation with System Bus

Speed when encoding is 001B.

166.67 MHz should be utilized if performing calculation with System Bus

Speed when encoding is 011B.

266.67 MHz should be utilized if performing calculation with System Bus

Speed when encoding is 000B.

333.33 MHz should be utilized if performing calculation with System Bus

Speed when encoding is 100B.

63:3

Reserved.

MSR_FSB_FREQ

Scaleable Bus Speed (R/O)

Shared

This field indicates the intended scalable bus clock speed for processors based on Enhanced Intel Core

microarchitecture.

2:0

•

101B: 100 MHz (FSB 400)

•

001B: 133 MHz (FSB 533)

•

011B: 167 MHz (FSB 667)

•

010B: 200 MHz (FSB 800)

•

000B: 267 MHz (FSB 1067)

•

100B: 333 MHz (FSB 1333)

•

110B: 400 MHz (FSB 1600)

133.33 MHz should be utilized if performing calculation with System Bus

Speed when encoding is 001B.

166.67 MHz should be utilized if performing calculation with System Bus

Speed when encoding is 011B.

266.67 MHz should be utilized if performing calculation with System Bus

Speed when encoding is 110B.

333.33 MHz should be utilized if performing calculation with System Bus

Speed when encoding is 111B.

63:3

Reserved.

IA32_MPERF

Maximum Performance Frequency Clock Count (R/W)

Unique

See Table 2-2.

IA32_APERF

Actual Performance Frequency Clock Count (R/W)

Unique

See Table 2-2.

IA32_MTRRCAP

See Table 2-2.

Unique

SMRR Capability Using MSR 0A0H and 0A1H (R)

Unique

2-98 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Shared/

Bit Description

Unique

IA32_SYSENTER_CS

See Table 2-2.

Unique

IA32_SYSENTER_ESP

See Table 2-2.

Unique

IA32_SYSENTER_EIP

See Table 2-2.

Unique

IA32_MCG_CAP

See Table 2-2.

Unique

IA32_MCG_STATUS

Global Machine Check Status

Unique

RIPV

When set, bit indicates that the instruction addressed by the instruction

pointer pushed on the stack (when the machine check was generated) can be

used to restart the program. If cleared, the program cannot be reliably

restarted.

EIPV

When set, bit indicates that the instruction addressed by the instruction

pointer pushed on the stack (when the machine check was generated) is

directly associated with the error.

MCIP

When set, bit indicates that a machine check has been generated. If a second

machine check is detected while this bit is still set, the processor enters a

shutdown state. Software should write this bit to 0 after processing a

machine check exception.

63:3

Reserved.

IA32_PERFEVTSEL0

See Table 2-2.

Unique

IA32_PERFEVTSEL1

See Table 2-2.

Unique

IA32_PERF_STATUS

See Table 2-2.

Shared

MSR_PERF_STATUS

Current performance status. See Section 17.1.1, “Software Interface For Initiating Performance State Transitions.”

Shared

15:0

Current Performance State Value

30:16

Reserved.

XE Operation (R/O).

If set, XE operation is enabled. Default is cleared.

39:32

Reserved.

Vol. 4

2-99

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Shared/

Bit Description

Unique

44:40

Maximum Bus Ratio (R/O)

Indicates maximum bus ratio configured for the processor.

Reserved.

Non-Integer Bus Ratio (R/O)

Indicates non-integer bus ratio is enabled. Applies processors based on

Enhanced Intel Core microarchitecture.

63:47

Reserved.

IA32_PERF_CTL

See Table 2-2.

Unique

IA32_CLOCK_MODULATION

Clock Modulation (R/W)

Unique

See Table 2-2.

IA32_CLOCK_MODULATION MSR was originally named IA32_THERM_CONTROL MSR.

IA32_THERM_INTERRUPT

Thermal Interrupt Control (R/W)

Unique

See Table 2-2.

IA32_THERM_STATUS

Thermal Monitor Status (R/W)

Unique

See Table 2-2.

MSR_THERM2_CTL

Thermal Monitor 2 Control

Unique

15:0

Reserved.

TM_SELECT (R/W)

Mode of automatic thermal monitor:

0 = Thermal Monitor 1 (thermally-initiated on-die modulation of the stop-

clock duty cycle).

1 = Thermal Monitor 2 (thermally-initiated frequency transitions).

If bit 3 of the IA32_MISC_ENABLE register is cleared, TM_SELECT has no

effect. Neither TM1 nor TM2 are enabled.

63:16

Reserved.

IA32_MISC_ENABLE

Enable Misc. Processor Features (R/W)

Allows a variety of processor functions to be enabled and disabled.

Fast-Strings Enable

See Table 2-2.

2:1

Reserved.

Automatic Thermal Control Circuit Enable (R/W)

Unique

See Table 2-2.

2-100 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Shared/

Bit Description

Unique

6:4

Reserved.

Performance Monitoring Available (R)

Shared

See Table 2-2.

Reserved.

Hardware Prefetcher Disable (R/W)

When set, disables the hardware prefetcher operation on streams of data.

When clear (default), enables the prefetch queue.

Disabling of the hardware prefetcher may impact processor performance.

FERR# Multiplexing Enable (R/W)

Shared

1 = FERR# asserted by the processor to indicate a pending break event

within the processor.

0 = Indicates compatible FERR# signaling behavior.

This bit must be set to 1 to support XAPIC interrupt model usage.

Branch Trace Storage Unavailable (R/O)

Shared

See Table 2-2.

Processor Event Based Sampling Unavailable (R/O)

Shared

See Table 2-2.

TM2 Enable (R/W)

Shared

When this bit is set (1) and the thermal sensor indicates that the die

temperature is at the pre-determined threshold, the Thermal Monitor 2

mechanism is engaged. TM2 will reduce the bus to core ratio and voltage

according to the value last written to MSR_THERM2_CTL bits 15:0.

When this bit is clear (0, default), the processor does not change the VID

signals or the bus to core ratio when the processor enters a thermally

managed state.

The BIOS must enable this feature if the TM2 feature flag (CPUID.01H:ECX[8])

is set; if the TM2 feature flag is not set, this feature is not supported and

BIOS must not alter the contents of the TM2 bit location.

The processor is operating out of specification if both this bit and the TM1 bit

are set to 0.

15:14

Reserved.

Enhanced Intel SpeedStep Technology Enable (R/W)

Shared

See Table 2-2.

ENABLE MONITOR FSM (R/W)

Shared

See Table 2-2.

Vol. 4

2-101

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Shared/

Bit Description

Unique

Adjacent Cache Line Prefetch Disable (R/W)

Shared

When set to 1, the processor fetches the cache line that contains data

currently required by the processor. When set to 0, the processor fetches

cache lines that comprise a cache line pair (128 bytes).

Single processor platforms should not set this bit. Server platforms should set

or clear this bit based on platform performance observed in validation and

testing.

BIOS may contain a setup option that controls the setting of this bit.

Enhanced Intel SpeedStep Technology Select Lock (R/WO)

Shared

When set, this bit causes the following bits to become read-only:

• Enhanced Intel SpeedStep Technology Select Lock (this bit).

• Enhanced Intel SpeedStep Technology Enable bit.

The bit must be set before an Enhanced Intel SpeedStep Technology

transition is requested. This bit is cleared on reset.

Reserved.

Limit CPUID Maxval (R/W)

Shared

See Table 2-2.

xTPR Message Disable (R/W)

Shared

See Table 2-2.

33:24

Reserved.

XD Bit Disable (R/W)

Unique

When set to 1, the Execute Disable Bit feature (XD Bit) is disabled and the XD

Bit extended feature flag will be clear (CPUID.80000001H:EDX[20] =0).

When set to a 0 (default), the Execute Disable Bit feature (if available) allows

the OS to enable PAE paging and take advantage of data only pages.

BIOS must not alter the contents of this bit location if XD bit is not supported.

Writing this bit to 1 when the XD Bit extended feature flag is set to 0 may

generate a #GP exception.

36:35

Reserved.

DCU Prefetcher Disable (R/W)

Unique

When set to 1, the DCU L1 data cache prefetcher is disabled. The default

value after reset is 0. BIOS may write ‘1’ to disable this feature.

The DCU prefetcher is an L1 data cache prefetcher. When the DCU prefetcher

detects multiple loads from the same line done within a time limit, the DCU

prefetcher assumes the next line will be required. The next line is prefetched

in to the L1 data cache from memory or L2.

2-102 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Shared/

Bit Description

Unique

IDA Disable (R/W)

Shared

When set to 1 on processors that support IDA, the Intel Dynamic Acceleration

feature (IDA) is disabled and the IDA_Enable feature flag will be cleared

(CPUID.06H:EAX[1] =0).

When set to a 0 on processors that support IDA, CPUID.06H:EAX[1] reports

the processor’s support of IDA is enabled.

Note: The power-on default value is used by BIOS to detect hardware support

of IDA. If the power-on default value is 1, IDA is available in the processor. If

the power-on default value is 0, IDA is not available.

IP Prefetcher Disable (R/W)

Unique

When set to 1, the IP prefetcher is disabled. The default value after reset is 0.

BIOS may write ‘1’ to disable this feature.

The IP prefetcher is an L1 data cache prefetcher. The IP prefetcher looks for

sequential load history to determine whether to prefetch the next expected

data into the L1 cache from memory or L2.

63:40

Reserved.

MSR_LASTBRANCH_TOS

Last Branch Record Stack TOS (R/W)

Unique

Contains an index (bits 0-3) that points to the MSR containing the most recent branch record.

See MSR_LASTBRANCH_0_FROM_IP (at 40H).

IA32_DEBUGCTL

Debug Control (R/W)

Unique

See Table 2-2.

MSR_LER_FROM_LIP

Last Exception Record From Linear IP (R/W)

Unique

Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was

generated or the last interrupt that was handled.

MSR_LER_TO_LIP

Last Exception Record To Linear IP (R/W)

Unique

This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last

exception that was generated or the last interrupt that was handled.

IA32_MTRR_PHYSBASE0

See Table 2-2.

Unique

IA32_MTRR_PHYSMASK0

See Table 2-2.

Unique

IA32_MTRR_PHYSBASE1

See Table 2-2.

Unique

IA32_MTRR_PHYSMASK1

See Table 2-2.

Unique

IA32_MTRR_PHYSBASE2

Vol. 4

2-103

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Shared/

Bit Description

Unique

See Table 2-2.

Unique

IA32_MTRR_PHYSMASK2

See Table 2-2.

Unique

IA32_MTRR_PHYSBASE3

See Table 2-2.

Unique

IA32_MTRR_PHYSMASK3

See Table 2-2.

Unique

IA32_MTRR_PHYSBASE4

See Table 2-2.

Unique

IA32_MTRR_PHYSMASK4

See Table 2-2.

Unique

IA32_MTRR_PHYSBASE5

See Table 2-2.

Unique

IA32_MTRR_PHYSMASK5

See Table 2-2.

Unique

IA32_MTRR_PHYSBASE6

See Table 2-2.

Unique

IA32_MTRR_PHYSMASK6

See Table 2-2.

Unique

IA32_MTRR_PHYSBASE7

See Table 2-2.

Unique

IA32_MTRR_PHYSMASK7

See Table 2-2.

Unique

IA32_MTRR_FIX64K_00000

See Table 2-2.

Unique

IA32_MTRR_FIX16K_80000

See Table 2-2.

Unique

IA32_MTRR_FIX16K_A0000

See Table 2-2.

Unique

IA32_MTRR_FIX4K_C0000

See Table 2-2.

Unique

IA32_MTRR_FIX4K_C8000

See Table 2-2.

Unique

IA32_MTRR_FIX4K_D0000

See Table 2-2.

Unique

2-104 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Shared/

Bit Description

Unique

IA32_MTRR_FIX4K_D8000

See Table 2-2.

Unique

IA32_MTRR_FIX4K_E0000

See Table 2-2.

Unique

IA32_MTRR_FIX4K_E8000

See Table 2-2.

Unique

IA32_MTRR_FIX4K_F0000

See Table 2-2.

Unique

IA32_MTRR_FIX4K_F8000

See Table 2-2.

Unique

IA32_PAT

See Table 2-2.

Unique

IA32_MTRR_DEF_TYPE

Default Memory Types (R/W)

Unique

See Table 2-2.

IA32_FIXED_CTR0

Fixed-Function Performance Counter Register 0 (R/W)

Unique

See Table 2-2.

IA32_FIXED_CTR1

Fixed-Function Performance Counter Register 1 (R/W)

Unique

See Table 2-2.

IA32_FIXED_CTR2

Fixed-Function Performance Counter Register 2 (R/W)

Unique

See Table 2-2.

IA32_PERF_CAPABILITIES

See Table 2-2. See Section 20.4.1, “IA32_DEBUGCTL MSR.”

Unique

MSR_PERF_CAPABILITIES

R/O. This applies to processors that do not support architectural PerfMon version 2.

Unique

5:0

LBR Format. See Table 2-2.

PEBS Record Format.

PEBSSaveArchRegs. See Table 2-2.

63:8

Reserved.

IA32_FIXED_CTR_CTRL

Fixed-Function-Counter Control Register (R/W)

Unique

See Table 2-2.

IA32_PERF_GLOBAL_STATUS

Vol. 4

2-105

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Shared/

Bit Description

Unique

See Table 2-2. See Section 22.6.2.2, “Global Counter Control Facilities.”

Unique

MSR_PERF_GLOBAL_STATUS

See Section 22.6.2.2, “Global Counter Control Facilities.”

Unique

IA32_PERF_GLOBAL_CTRL

See Table 2-2. See Section 22.6.2.2, “Global Counter Control Facilities.”

Unique

MSR_PERF_GLOBAL_CTRL

See Section 22.6.2.2, “Global Counter Control Facilities.”

Unique

IA32_PERF_GLOBAL_OVF_CTRL

See Table 2-2. See Section 22.6.2.2, “Global Counter Control Facilities.”

Unique

MSR_PERF_GLOBAL_OVF_CTRL

See Section 22.6.2.2, “Global Counter Control Facilities.”

Unique

IA32_PEBS_ENABLE (MSR_PEBS_ENABLE)

See Table 2-2. See Section 22.6.2.4, “Processor Event Based Sampling (PEBS).”

Unique

Enable PEBS on IA32_PMC0. (R/W)

IA32_MC0_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Unique

IA32_MC0_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

Unique

IA32_MC0_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

Unique

The IA32_MC0_ADDR register is either not implemented or contains no address if the ADDRV flag in the

IA32_MC0_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

IA32_MC1_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Unique

IA32_MC1_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

Unique

IA32_MC1_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

Unique

The IA32_MC1_ADDR register is either not implemented or contains no address if the ADDRV flag in the

IA32_MC1_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

IA32_MC2_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Unique

IA32_MC2_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

Unique

2-106 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Shared/

Bit Description

Unique

IA32_MC2_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

Unique

The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in the

IA32_MC2_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

IA32_MC4_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Unique

IA32_MC4_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

Unique

IA32_MC4_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

Unique

The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the

MSR_MC4_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

IA32_MC3_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

IA32_MC3_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

IA32_MC3_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

Unique

The MSR_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in the

MSR_MC3_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

IA32_MC3_MISC

Machine Check Error Reporting Register: Contains additional information describing the machine-check error if the

Unique

MISCV flag in the IA32_MCi_STATUS register is set.

IA32_MC5_CTL

Machine Check Error Reporting Register: Controls signaling of #MC for errors produced by a particular hardware unit

Unique

(or group of hardware units).

IA32_MC5_STATUS

Machine Check Error Reporting Register: Contains information related to a machine-check error if its VAL (valid) flag is

Unique

set. Software is responsible for clearing IA32_MCi_STATUS MSRs by explicitly writing 0s to them; writing 1s to them

causes a general-protection exception.

IA32_MC5_ADDR

Machine Check Error Reporting Register: Contains the address of the code or data memory location that produced the

Unique

machine-check error if the ADDRV flag in the IA32_MCi_STATUS register is set.

IA32_MC5_MISC

Machine Check Error Reporting Register: Contains additional information describing the machine-check error if the

Unique

MISCV flag in the IA32_MCi_STATUS register is set.

Vol. 4

2-107

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Shared/

Bit Description

Unique

IA32_MC6_STATUS

Applies to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 18.3.2.2,

Unique

“IA32_MCi_STATUS MSRS,” and Chapter 26.

IA32_VMX_BASIC

Reporting Register of Basic VMX Capabilities (R/O)

Unique

See Table 2-2. See Appendix A.1, “Basic VMX Information.”

IA32_VMX_PINBASED_CTLS

Capability Reporting Register of Pin-Based VM-Execution Controls (R/O)

Unique

See Table 2-2. See Appendix A.3, “VM-Execution Controls.”

IA32_VMX_PROCBASED_CTLS

Capability Reporting Register of Primary Processor-Based VM-Execution Controls (R/O)

Unique

See Appendix A.3, “VM-Execution Controls.”

IA32_VMX_EXIT_CTLS

Capability Reporting Register of VM-Exit Controls (R/O)

Unique

See Table 2-2. See Appendix A.4, “VM-Exit Controls.”

IA32_VMX_ENTRY_CTLS

Capability Reporting Register of VM-Entry Controls (R/O)

Unique

See Table 2-2. See Appendix A.5, “VM-Entry Controls.”

IA32_VMX_MISC

Reporting Register of Miscellaneous VMX Capabilities (R/O)

Unique

See Table 2-2. See Appendix A.6, “Miscellaneous Data.”

IA32_VMX_CR0_FIXED0

Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)

Unique

See Table 2-2. See Appendix A.7, “VMX-Fixed Bits in CR0.”

IA32_VMX_CR0_FIXED1

Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)

Unique

See Table 2-2. See Appendix A.7, “VMX-Fixed Bits in CR0.”

IA32_VMX_CR4_FIXED0

Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)

Unique

See Table 2-2. See Appendix A.8, “VMX-Fixed Bits in CR4.”

IA32_VMX_CR4_FIXED1

Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)

Unique

See Table 2-2. See Appendix A.8, “VMX-Fixed Bits in CR4.”

IA32_VMX_VMCS_ENUM

Capability Reporting Register of VMCS Field Enumeration (R/O)

Unique

See Table 2-2. See Appendix A.9, “VMCS Enumeration.”

IA32_VMX_PROCBASED_CTLS2

2-108 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Shared/

Bit Description

Unique

Capability Reporting Register of Secondary Processor-Based VM-Execution Controls (R/O)

Unique

See Appendix A.3, “VM-Execution Controls.”

IA32_DS_AREA

DS Save Area (R/W)

Unique

See Table 2-2. See Section 22.6.3.4, “Debug Store (DS) Mechanism.”

MSR_EMON_L3_CTR_CTL0

GBUSQ Event Control/Counter Register (R/W)

Unique

Applies to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 20.2.2.

MSR_EMON_L3_CTR_CTL1

GBUSQ Event Control/Counter Register (R/W)

Unique

Applies to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 20.2.2.

MSR_EMON_L3_CTR_CTL2

GSNPQ Event Control/Counter Register (R/W)

Unique

Applies to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 20.2.2.

MSR_EMON_L3_CTR_CTL3

GSNPQ Event Control/Counter Register (R/W)

Unique

Applies to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 20.2.2.

MSR_EMON_L3_CTR_CTL4

FSB Event Control/Counter Register (R/W)

Unique

Applies to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 20.2.2.

MSR_EMON_L3_CTR_CTL5

FSB Event Control/Counter Register (R/W)

Unique

Applies to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 20.2.2.

MSR_EMON_L3_CTR_CTL6

FSB Event Control/Counter Register (R/W)

Unique

Applies to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 20.2.2.

MSR_EMON_L3_CTR_CTL7

FSB Event Control/Counter Register (R/W)

Unique

Applies to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 20.2.2.

MSR_EMON_L3_GL_CTL

L3/FSB Common Control Register (R/W)

Unique

Applies to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 20.2.2.

IA32_EFER

Extended Feature Enables

Unique

See Table 2-2.

IA32_STAR

Vol. 4

2-109

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Shared/

Bit Description

Unique

System Call Target Address (R/W)

Unique

See Table 2-2.

IA32_LSTAR

IA-32e Mode System Call Target Address (R/W)

Unique

See Table 2-2.

IA32_FMASK

System Call Flag Mask (R/W)

Unique

See Table 2-2.

IA32_FS_BASE

Map of BASE Address of FS (R/W)

Unique

See Table 2-2.

IA32_GS_BASE

Map of BASE Address of GS (R/W)

Unique

See Table 2-2.

IA32_KERNEL_GS_BASE

Swap Target of BASE Address of GS (R/W)

Unique

See Table 2-2.

2.3

MSRS IN THE 45 NM AND 32 NM INTEL ATOM® PROCESSOR FAMILY

Table 2-4 lists model-specific registers (MSRs) for 45 nm and 32 nm Intel Atom processors, architectural MSR

addresses are also included in Table 2-4. These processors have a CPUID Signature DisplayFamily_DisplayModel

value of 06_1CH, 06_26H, 06_27H, 06_35H, or 06_36H; see Table 2-1.

The column “Shared/Unique” applies to logical processors sharing the same core in processors based on the Intel

Atom microarchitecture. “Unique” means each logical processor has a separate MSR, or a bit field in an MSR

governs only a logical processor. “Shared” means the MSR or the bit field in an MSR address governs the operation

of both logical processors in the same core.

Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family

Shared/

Bit Description

Unique

IA32_P5_MC_ADDR

See Section 2.23, “MSRs in Pentium Processors.”

Shared

IA32_P5_MC_TYPE

See Section 2.23, “MSRs in Pentium Processors.”

Shared

IA32_MONITOR_FILTER_SIZE

See Section 11.10.5, “Monitor/Mwait Address Range Determination,” and Table 2-2.

Unique

2-110 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)

Shared/

Bit Description

Unique

IA32_TIME_STAMP_COUNTER

See Section 20.17, “Time-Stamp Counter,” and see Table 2-2.

Unique

IA32_PLATFORM_ID

Platform ID (R)

Shared

See Table 2-2.

MSR_PLATFORM_ID

Model Specific Platform ID (R)

Shared

7:0

Reserved.

12:8

Maximum Qualified Ratio (R)

The maximum allowed bus ratio.

63:13

Reserved.

IA32_APIC_BASE

See Section 13.4.4, “Local APIC Status and Location,” and Table 2-2.

Unique

MSR_EBL_CR_POWERON

Processor Hard Power-On Configuration (R/W)

Shared

Enables and disables processor features; (R) indicates current processor configuration.

Reserved.

Data Error Checking Enable (R/W)

1 = Enabled; 0 = Disabled.

Always 0.

Response Error Checking Enable (R/W)

1 = Enabled; 0 = Disabled.

Always 0.

AERR# Drive Enable (R/W)

1 = Enabled; 0 = Disabled.

Always 0.

BERR# Enable for initiator bus requests (R/W)

1 = Enabled; 0 = Disabled.

Always 0.

Reserved.

BINIT# Driver Enable (R/W)

1 = Enabled; 0 = Disabled.

Always 0.

Reserved.

Execute BIST (R/O)

1 = Enabled; 0 = Disabled.

AERR# Observation Enabled (R/O)

1 = Enabled; 0 = Disabled.

Always 0.

Vol. 4

2-111

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)

Shared/

Bit Description

Unique

Reserved.

BINIT# Observation Enabled (R/O)

1 = Enabled; 0 = Disabled.

Always 0.

Reserved.

1 MByte Power on Reset Vector (R/O)

1 = 1 MByte; 0 = 4 GBytes.

Reserved.

17:16

APIC Cluster ID (R/O)

Always 00B.

19: 18

Reserved.

21: 20

Symmetric Arbitration ID (R/O)

Always 00B.

26:22

Integer Bus Frequency Ratio (R/O)

IA32_FEATURE_CONTROL

Control Features in Intel 64Processor (R/W)

Unique

See Table 2-2.

MSR_LASTBRANCH_0_FROM_IP

Last Branch Record 0 From IP (R/W)

Unique

One of eight pairs of last branch record registers on the last branch record stack. The From_IP part of the stack

contains pointers to the source instruction. See also:

• Last Branch Record Stack TOS at 1C9H.

• Section 20.5.

MSR_LASTBRANCH_1_FROM_IP

Last Branch Record 1 From IP (R/W)

Unique

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_2_FROM_IP

Last Branch Record 2 From IP (R/W)

Unique

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_3_FROM_IP

Last Branch Record 3 From IP (R/W)

Unique

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_4_FROM_IP

Last Branch Record 4 From IP (R/W)

Unique

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_5_FROM_IP

Last Branch Record 5 From IP (R/W)

Unique

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_6_FROM_IP

2-112 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)

Shared/

Bit Description

Unique

Last Branch Record 6 From IP (R/W)

Unique

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_7_FROM_IP

Last Branch Record 7 From IP (R/W)

Unique

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_0_TO_IP

Last Branch Record 0 To IP (R/W)

Unique

One of eight pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains

pointers to the destination instruction.

MSR_LASTBRANCH_1_TO_IP

Last Branch Record 1 To IP (R/W)

Unique

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_2_TO_IP

Last Branch Record 2 To IP (R/W)

Unique

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_3_TO_IP

Last Branch Record 3 To IP (R/W)

Unique

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_4_TO_IP

Last Branch Record 4 To IP (R/W)

Unique

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_5_TO_IP

Last Branch Record 5 To IP (R/W)

Unique

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_6_TO_IP

Last Branch Record 6 To IP (R/W)

Unique

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_7_TO_IP

Last Branch Record 7 To IP (R/W)

Unique

See description of MSR_LASTBRANCH_0_TO_IP.

IA32_BIOS_UPDT_TRIG

BIOS Update Trigger Register (W)

Shared

See Table 2-2.

IA32_BIOS_SIGN_ID

BIOS Update Signature ID (R/W)

Unique

See Table 2-2.

IA32_PMC0

Performance counter register

Unique

See Table 2-2.

Vol. 4

2-113

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)

Shared/

Bit Description

Unique

IA32_PMC1

Performance Counter Register

Unique

See Table 2-2.

MSR_FSB_FREQ

Scaleable Bus Speed (R/O)

Shared

This field indicates the intended scalable bus clock speed for processors based on Intel Atom microarchitecture.

2:0

•

111B: 083 MHz (FSB 333)

•

101B: 100 MHz (FSB 400)

•

001B: 133 MHz (FSB 533)

•

011B: 167 MHz (FSB 667)

133.33 MHz should be utilized if performing calculation with System Bus

Speed when encoding is 001B.

166.67 MHz should be utilized if performing calculation with System Bus

Speed when encoding is 011B.

63:3

Reserved.

IA32_MPERF

Maximum Performance Frequency Clock Count (R/W)

Unique

See Table 2-2.

IA32_APERF

Actual Performance Frequency Clock Count (R/W)

Unique

See Table 2-2.

IA32_MTRRCAP

Memory Type Range Register (R)

Shared

See Table 2-2.

MSR_BBL_CR_CTL3

Control Register 3

Shared

Used to configure the L2 Cache.

L2 Hardware Enabled (R/O)

1 = Indicates the L2 is hardware-enabled.

0 = Indicates the L2 is hardware-disabled.

7:1

Reserved.

L2 Enabled (R/W)

1 = L2 cache has been initialized.

0 = Disabled (default).

Until this bit is set, the processor will not respond to the WBINVD instruction

or the assertion of the FLUSH# input.

22:9

Reserved.

L2 Not Present (R/O)

0 = L2 Present.

1 = L2 Not Present.

63:24

Reserved.

2-114 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)

Shared/

Bit Description

Unique

IA32_SYSENTER_CS

See Table 2-2.

Unique

IA32_SYSENTER_ESP

See Table 2-2.

Unique

IA32_SYSENTER_EIP

See Table 2-2.

Unique

IA32_MCG_CAP

See Table 2-2.

Unique

IA32_MCG_STATUS

Global Machine Check Status

Unique

RIPV

When set, bit indicates that the instruction addressed by the instruction

pointer pushed on the stack (when the machine check was generated) can be

used to restart the program. If cleared, the program cannot be reliably

restarted.

EIPV

When set, bit indicates that the instruction addressed by the instruction

pointer pushed on the stack (when the machine check was generated) is

directly associated with the error.

MCIP

When set, bit indicates that a machine check has been generated. If a second

machine check is detected while this bit is still set, the processor enters a

shutdown state. Software should write this bit to 0 after processing a

machine check exception.

63:3

Reserved.

IA32_PERFEVTSEL0

See Table 2-2.

Unique

IA32_PERFEVTSEL1

See Table 2-2.

Unique

IA32_PERF_STATUS

See Table 2-2.

Shared

MSR_PERF_STATUS

Performance Status

Shared

15:0

Current Performance State Value.

39:16

Reserved.

44:40

Maximum Bus Ratio (R/O)

Indicates maximum bus ratio configured for the processor.

63:45

Reserved.

IA32_PERF_CTL

See Table 2-2.

Unique

Vol. 4

2-115

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)

Shared/

Bit Description

Unique

IA32_CLOCK_MODULATION

Clock Modulation (R/W)

Unique

See Table 2-2.

IA32_CLOCK_MODULATION MSR was originally named IA32_THERM_CONTROL MSR.

IA32_THERM_INTERRUPT

Thermal Interrupt Control (R/W)

Unique

See Table 2-2.

IA32_THERM_STATUS

Thermal Monitor Status (R/W)

Unique

See Table 2-2.

MSR_THERM2_CTL

Thermal Monitor 2 Control

Shared

15:0

Reserved.

TM_SELECT (R/W)

Mode of automatic thermal monitor:

0 = Thermal Monitor 1 (thermally-initiated on-die modulation of the stop-

clock duty cycle).

1 = Thermal Monitor 2 (thermally-initiated frequency transitions).

If bit 3 of the IA32_MISC_ENABLE register is cleared, TM_SELECT has no

effect. Neither TM1 nor TM2 are enabled.

63:17

Reserved.

IA32_MISC_ENABLE

Enable Misc. Processor Features (R/W)

Unique

Allows a variety of processor functions to be enabled and disabled.

Fast-Strings Enable

See Table 2-2.

2:1

Reserved.

Automatic Thermal Control Circuit Enable (R/W)

Unique

See Table 2-2. Default value is 0.

6:4

Reserved.

Performance Monitoring Available (R)

Shared

See Table 2-2.

Reserved.

FERR# Multiplexing Enable (R/W)

Shared

1 = FERR# asserted by the processor to indicate a pending break event

within the processor.

0 = Indicates compatible FERR# signaling behavior.

This bit must be set to 1 to support XAPIC interrupt model usage.

2-116 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)

Shared/

Bit Description

Unique

Branch Trace Storage Unavailable (R/O)

Shared

See Table 2-2.

Processor Event Based Sampling Unavailable (R/O)

Shared

See Table 2-2.

TM2 Enable (R/W)

Shared

When this bit is set (1) and the thermal sensor indicates that the die

temperature is at the pre-determined threshold, the Thermal Monitor 2

mechanism is engaged. TM2 will reduce the bus to core ratio and voltage

according to the value last written to MSR_THERM2_CTL bits 15:0.

When this bit is cleared (0, default), the processor does not change the VID

signals or the bus to core ratio when the processor enters a thermally

managed state.

The BIOS must enable this feature if the TM2 feature flag (CPUID.01H:ECX[8])

is set; if the TM2 feature flag is not set, this feature is not supported and BIOS

must not alter the contents of the TM2 bit location.

The processor is operating out of specification if both this bit and the TM1 bit

are set to 0.

15:14

Reserved.

Enhanced Intel SpeedStep Technology Enable (R/W)

Shared

See Table 2-2.

ENABLE MONITOR FSM (R/W)

Shared

See Table 2-2.

Reserved.

Enhanced Intel SpeedStep Technology Select Lock (R/WO)

Shared

When set, this bit causes the following bits to become read-only:

• Enhanced Intel SpeedStep Technology Select Lock (this bit).

• Enhanced Intel SpeedStep Technology Enable bit.

The bit must be set before an Enhanced Intel SpeedStep Technology transition

is requested. This bit is cleared on reset.

Reserved.

Limit CPUID Maxval (R/W)

Unique

See Table 2-2.

xTPR Message Disable (R/W)

Shared

See Table 2-2.

33:24

Reserved.

XD Bit Disable (R/W)

Unique

See Table 2-3.

63:35

Reserved.

MSR_LASTBRANCH_TOS

Last Branch Record Stack TOS (R/W)

Unique

Contains an index (bits 0-2) that points to the MSR containing the most recent branch record.

See MSR_LASTBRANCH_0_FROM_IP (at 40H).

Vol. 4

2-117

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)

Shared/

Bit Description

Unique

IA32_DEBUGCTL

Debug Control (R/W)

Unique

See Table 2-2.

MSR_LER_FROM_LIP

Last Exception Record From Linear IP (R)

Unique

Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was

generated or the last interrupt that was handled.

MSR_LER_TO_LIP

Last Exception Record To Linear IP (R)

Unique

This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last

exception that was generated or the last interrupt that was handled.

IA32_MTRR_PHYSBASE0

See Table 2-2.

Shared

IA32_MTRR_PHYSMASK0

See Table 2-2.

Shared

IA32_MTRR_PHYSBASE1

See Table 2-2.

Shared

IA32_MTRR_PHYSMASK1

See Table 2-2.

Shared

IA32_MTRR_PHYSBASE2

See Table 2-2.

Shared

IA32_MTRR_PHYSMASK2

See Table 2-2.

Shared

IA32_MTRR_PHYSBASE3

See Table 2-2.

Shared

IA32_MTRR_PHYSMASK3

See Table 2-2.

Shared

IA32_MTRR_PHYSBASE4

See Table 2-2.

Shared

IA32_MTRR_PHYSMASK4

See Table 2-2.

Shared

IA32_MTRR_PHYSBASE5

See Table 2-2.

Shared

IA32_MTRR_PHYSMASK5

See Table 2-2.

Shared

IA32_MTRR_PHYSBASE6

See Table 2-2.

Shared

IA32_MTRR_PHYSMASK6

2-118 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)

Shared/

Bit Description

Unique

See Table 2-2.

Shared

IA32_MTRR_PHYSBASE7

See Table 2-2.

Shared

IA32_MTRR_PHYSMASK7

See Table 2-2.

Shared

IA32_MTRR_FIX64K_00000

See Table 2-2.

Shared

IA32_MTRR_FIX16K_80000

See Table 2-2.

Shared

IA32_MTRR_FIX16K_A0000

See Table 2-2.

Shared

IA32_MTRR_FIX4K_C0000

See Table 2-2.

Shared

IA32_MTRR_FIX4K_C8000

See Table 2-2.

Shared

IA32_MTRR_FIX4K_D0000

See Table 2-2.

Shared

IA32_MTRR_FIX4K_D8000

See Table 2-2.

Shared

IA32_MTRR_FIX4K_E0000

See Table 2-2.

Shared

IA32_MTRR_FIX4K_E8000

See Table 2-2.

Shared

IA32_MTRR_FIX4K_F0000

See Table 2-2.

Shared

IA32_MTRR_FIX4K_F8000

See Table 2-2.

Shared

IA32_PAT

See Table 2-2.

Unique

IA32_FIXED_CTR0

Fixed-Function Performance Counter Register 0 (R/W)

Unique

See Table 2-2.

IA32_FIXED_CTR1

Fixed-Function Performance Counter Register 1 (R/W)

Unique

See Table 2-2.

IA32_FIXED_CTR2

Vol. 4

2-119

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)

Shared/

Bit Description

Unique

Fixed-Function Performance Counter Register 2 (R/W)

Unique

See Table 2-2.

IA32_PERF_CAPABILITIES

See Table 2-2. See Section 20.4.1, “IA32_DEBUGCTL MSR.”

Shared

IA32_FIXED_CTR_CTRL

Fixed-Function-Counter Control Register (R/W)

Unique

See Table 2-2.

IA32_PERF_GLOBAL_STATUS

See Table 2-2. See Section 22.6.2.2, “Global Counter Control Facilities.”

Unique

IA32_PERF_GLOBAL_CTRL

See Table 2-2. See Section 22.6.2.2, “Global Counter Control Facilities.”

Unique

IA32_PERF_GLOBAL_OVF_CTRL

See Table 2-2. See Section 22.6.2.2, “Global Counter Control Facilities.”

Unique

IA32_PEBS_ENABLE (MSR_PEBS_ENABLE)

See Table 2-2. See Section 22.6.2.4, “Processor Event Based Sampling (PEBS).”

Unique

Enable PEBS on IA32_PMC0 (R/W)

IA32_MC0_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Shared

IA32_MC0_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

Shared

IA32_MC0_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

Shared

The IA32_MC0_ADDR register is either not implemented or contains no address if the ADDRV flag in the

IA32_MC0_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

IA32_MC1_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Shared

IA32_MC1_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

Shared

IA32_MC2_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Shared

IA32_MC2_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

Shared

IA32_MC2_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

Shared

The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in the

IA32_MC2_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

2-120 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)

Shared/

Bit Description

Unique

IA32_MC3_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Shared

IA32_MC3_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

Shared

IA32_MC3_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

Shared

The MSR_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in the

MSR_MC3_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

IA32_MC4_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Shared

IA32_MC4_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

Shared

IA32_MC4_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

Shared

The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the

MSR_MC4_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

IA32_VMX_BASIC

Reporting Register of Basic VMX Capabilities (R/O)

Unique

See Table 2-2. See Appendix A.1, “Basic VMX Information.”

IA32_VMX_PINBASED_CTLS

Capability Reporting Register of Pin-Based VM-Execution Controls (R/O)

Unique

See Table 2-2. See Appendix A.3, “VM-Execution Controls.”

IA32_VMX_PROCBASED_CTLS

Capability Reporting Register of Primary Processor-Based VM-Execution Controls (R/O)

Unique

See Appendix A.3, “VM-Execution Controls.”

IA32_VMX_EXIT_CTLS

Capability Reporting Register of VM-Exit Controls (R/O)

Unique

See Table 2-2. See Appendix A.4, “VM-Exit Controls.”

IA32_VMX_ENTRY_CTLS

Capability Reporting Register of VM-Entry Controls (R/O)

Unique

See Table 2-2. See Appendix A.5, “VM-Entry Controls.”

IA32_VMX_MISC

Reporting Register of Miscellaneous VMX Capabilities (R/O)

Unique

See Table 2-2. See Appendix A.6, “Miscellaneous Data.”

IA32_VMX_CR0_FIXED0

Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)

Unique

See Table 2-2. See Appendix A.7, “VMX-Fixed Bits in CR0.”

Vol. 4

2-121

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)

Shared/

Bit Description

Unique

IA32_VMX_CR0_FIXED1

Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)

Unique

See Table 2-2. See Appendix A.7, “VMX-Fixed Bits in CR0.”

IA32_VMX_CR4_FIXED0

Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)

Unique

See Table 2-2. See Appendix A.8, “VMX-Fixed Bits in CR4.”

IA32_VMX_CR4_FIXED1

Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)

Unique

See Table 2-2. See Appendix A.8, “VMX-Fixed Bits in CR4.”

IA32_VMX_VMCS_ENUM

Capability Reporting Register of VMCS Field Enumeration (R/O)

Unique

See Table 2-2. See Appendix A.9, “VMCS Enumeration.”

IA32_VMX_PROCBASED_CTLS2

Capability Reporting Register of Secondary Processor-Based VM-Execution Controls (R/O)

Unique

See Appendix A.3, “VM-Execution Controls.”

IA32_DS_AREA

DS Save Area (R/W)

Unique

See Table 2-2. See Section 22.6.3.4, “Debug Store (DS) Mechanism.”

IA32_EFER

Extended Feature Enables

Unique

See Table 2-2.

IA32_STAR

System Call Target Address (R/W)

Unique

See Table 2-2.

IA32_LSTAR

IA-32e Mode System Call Target Address (R/W)

Unique

See Table 2-2.

IA32_FMASK

System Call Flag Mask (R/W)

Unique

See Table 2-2.

IA32_FS_BASE

Map of BASE Address of FS (R/W)

Unique

See Table 2-2.

IA32_GS_BASE

Map of BASE Address of GS (R/W)

Unique

See Table 2-2.

IA32_KERNEL_GS_BASE

2-122 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)

Shared/

Bit Description

Unique

Swap Target of BASE Address of GS (R/W)

Unique

See Table 2-2.

Table 2-5 lists model-specific registers (MSRs) that are specific to Intel Atom^® processor with a CPUID Signature

DisplayFamily_DisplayModel value of 06_27H.

Table 2-5. MSRs Supported by Intel Atom® Processors with a CPUID Signature DisplayFamily_DisplayModel

Value of 06_27H

Bit Description

Scope

MSR_PKG_C2_RESIDENCY

Package C2 Residency

Package

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

ACPI C-States.

63:0

Package C2 Residency Counter (R/O)

Package

Time that this package is in processor-specific C2 states since last reset.

Counts at 1 Mhz frequency.

MSR_PKG_C4_RESIDENCY

Package C4 Residency

Package

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

ACPI C-States.

63:0

Package C4 Residency Counter. (R/O)

Package

Time that this package is in processor-specific C4 states since last reset.

Counts at 1 Mhz frequency.

MSR_PKG_C6_RESIDENCY

Package C6 Residency

Package

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

ACPI C-States.

63:0

Package C6 Residency Counter. (R/O)

Package

Time that this package is in processor-specific C6 states since last reset.

Counts at 1 Mhz frequency.

2.4

MSRS IN INTEL PROCESSORS BASED ON SILVERMONT

MICROARCHITECTURE

Table 2-6 lists model-specific registers (MSRs) common to Intel processors based on the Silvermont microarchitec-

ture. These processors have a CPUID Signature DisplayFamily_DisplayModel value of 06_37H, 06_4AH, 06_4DH,

06_5AH, or 06_5DH; see Table 2-1. The MSRs listed in Table 2-6 are also common to processors based on the

Airmont microarchitecture and newer microarchitectures for next generation Intel Atom processors.

Table 2-7 lists MSRs common to processors based on the Silvermont and Airmont microarchitectures, but not

newer microarchitectures.

Table 2-8, Table 2-9, and Table 2-10 lists MSRs that are model-specific across processors based on the Silvermont

microarchitecture.

Vol. 4

2-123

MODEL-SPECIFIC REGISTERS (MSRS)

In the Silvermont microarchitecture, the scope column indicates the following: “Core” means each processor core

has a separate MSR, or a bit field not shared with another processor core. “Module” means the MSR or the bit field

is shared by a subset of the processor cores in the physical package. The number of processor cores in this subset

is model specific and may differ between different processors. For all processors based on Silvermont microarchi-

tecture, the L2 cache is also shared between cores in a module and thus CPUID.04H enumeration can be used to

figure out which processors are in the same module. “Package” means all processor cores in the physical package

share the same MSR or bit interface.

Table 2-6. MSRs Common to Intel Atom® Processors (Silvermont and Newer Microarchitectures)

Bit Description

Scope

IA32_P5_MC_ADDR

See Section 2.23, “MSRs in Pentium Processors.”

Module

IA32_P5_MC_TYPE

See Section 2.23, “MSRs in Pentium Processors.”

Module

IA32_MONITOR_FILTER_SIZE

See Section 11.10.5, “Monitor/Mwait Address Range Determination,” and Table 2-2.

Core

IA32_TIME_STAMP_COUNTER

See Section 20.17, “Time-Stamp Counter,” and Table 2-2.

Core

IA32_APIC_BASE

See Section 13.4.4, “Local APIC Status and Location,” and Table 2-2.

Core

MSR_EBL_CR_POWERON

Processor Hard Power-On Configuration (R/W)

Module

Writes ignored.

63:0

Reserved.

MSR_SMI_COUNT

SMI Counter (R/O)

Core

31:0

SMI Count (R/O)

Running count of SMI events since last RESET.

63:32

Reserved.

IA32_BIOS_UPDT_TRIG

BIOS Update Trigger Register (W)

Core

See Table 2-2.

IA32_BIOS_SIGN_ID

BIOS Update Signature ID (R/W)

Core

See Table 2-2.

IA32_PMC0

Performance Counter Register

Core

See Table 2-2.

IA32_PMC1

Performance Counter Register

Core

See Table 2-2.

MSR_PMG_IO_CAPTURE_BASE

2-124 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-6. MSRs Common to Intel Atom® Processors (Silvermont and Newer Microarchitectures) (Contd.)

Bit Description

Scope

Power Management IO Redirection in C-state (R/W)

Module

See http://biosbits.org.

15:0

LVL_2 Base Address (R/W)

Specifies the base address visible to software for IO redirection. If IO MWAIT

Redirection is enabled, reads to this address will be consumed by the power

management logic and decoded to MWAIT instructions. When IO port

address redirection is enabled, this is the IO port address reported to the

OS/software.

18:16

C-state Range (R/W)

Specifies the encoding value of the maximum C-State code name to be

included when IO read to MWAIT redirection is enabled by

MSR_PKG_CST_CONFIG_CONTROL[bit 10]:

100b - C4 is the max C-State to include

110b - C6 is the max C-State to include

111b - C7 is the max C-State to include

63:19

Reserved.

IA32_MPERF

Maximum Performance Frequency Clock Count (R/W)

Core

See Table 2-2.

IA32_APERF

Actual Performance Frequency Clock Count (R/W)

Core

See Table 2-2.

IA32_MTRRCAP

Memory Type Range Register (R)

Core

See Table 2-2.

MSR_FEATURE_CONFIG

AES Configuration (RW-L)

Core

Privileged post-BIOS agent must provide a #GP handler to handle unsuccessful read of this MSR.

1:0

AES Configuration (RW-L)

Upon a successful read of this MSR, the configuration of AES instruction

sets availability is as follows:

11b: AES instructions are not available until next RESET.

Otherwise, AES instructions are available.

Note: AES instruction set is not available if read is unsuccessful. If the

configuration is not 01b, AES instructions can be mis-configured if a

privileged agent unintentionally writes 11b.

63:2

Reserved.

IA32_SYSENTER_CS

See Table 2-2.

Core

IA32_SYSENTER_ESP

See Table 2-2.

Core

IA32_SYSENTER_EIP

Vol. 4

2-125

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-6. MSRs Common to Intel Atom® Processors (Silvermont and Newer Microarchitectures) (Contd.)

Bit Description

Scope

See Table 2-2.

Core

IA32_MCG_CAP

See Table 2-2.

Core

IA32_MCG_STATUS

Global Machine Check Status

Core

RIPV

When set, bit indicates that the instruction addressed by the instruction

pointer pushed on the stack (when the machine check was generated) can

be used to restart the program. If cleared, the program cannot be reliably

restarted.

EIPV

When set, bit indicates that the instruction addressed by the instruction

pointer pushed on the stack (when the machine check was generated) is

directly associated with the error.

MCIP

When set, bit indicates that a machine check has been generated. If a

second machine check is detected while this bit is still set, the processor

enters a shutdown state. Software should write this bit to 0 after

processing a machine check exception.

63:3

Reserved.

IA32_PERFEVTSEL0

See Table 2-2.

Core

7:0

Event Select

15:8

UMask

USR

Edge

INT

Reserved.

INV

31:24

CMASK

63:32

Reserved.

IA32_PERFEVTSEL1

See Table 2-2.

Core

IA32_PERF_STATUS

See Table 2-2.

Module

IA32_PERF_CTL

See Table 2-2.

Core

2-126 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-6. MSRs Common to Intel Atom® Processors (Silvermont and Newer Microarchitectures) (Contd.)

Bit Description

Scope

IA32_CLOCK_MODULATION

Clock Modulation (R/W)

Core

See Table 2-2.

IA32_CLOCK_MODULATION MSR was originally named IA32_THERM_CONTROL MSR.

IA32_THERM_INTERRUPT

Thermal Interrupt Control (R/W)

Core

See Table 2-2.

IA32_THERM_STATUS

Thermal Monitor Status (R/W)

Core

See Table 2-2.

MSR_TEMPERATURE_TARGET

Temperature Target

Package

15:0

Reserved.

23:16

Temperature Target (R)

The default thermal throttling or PROCHOT# activation temperature in

degrees C. The effective temperature for thermal throttling or PROCHOT#

activation is “Temperature Target” + “Target Offset”.

29:24

Target Offset (R/W)

Specifies an offset in degrees C to adjust the throttling and PROCHOT#

activation temperature from the default target specified in

TEMPERATURE_TARGET (bits 23:16).

63:30

Reserved.

MSR_OFFCORE_RSP_0

Offcore Response Event Select Register (R/W)

Module

MSR_OFFCORE_RSP_1

Offcore Response Event Select Register (R/W)

Module

IA32_ENERGY_PERF_BIAS

See Table 2-2.

Core

IA32_DEBUGCTL

Debug Control (R/W)

Core

See Table 2-2.

MSR_LER_FROM_LIP

Last Exception Record From Linear IP (R/W)

Core

Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was

generated or the last interrupt that was handled.

MSR_LER_TO_LIP

Last Exception Record To Linear IP (R/W)

Core

This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last

exception that was generated or the last interrupt that was handled.

IA32_SMRR_PHYSBASE

Vol. 4

2-127

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-6. MSRs Common to Intel Atom® Processors (Silvermont and Newer Microarchitectures) (Contd.)

Bit Description

Scope

See Table 2-2.

Core

IA32_SMRR_PHYSMASK

See Table 2-2.

Core

IA32_MTRR_PHYSBASE0

See Table 2-2.

Core

IA32_MTRR_PHYSMASK0

See Table 2-2.

Core

IA32_MTRR_PHYSBASE1

See Table 2-2.

Core

IA32_MTRR_PHYSMASK1

See Table 2-2.

Core

IA32_MTRR_PHYSBASE2

See Table 2-2.

Core

IA32_MTRR_PHYSMASK2

See Table 2-2.

Core

IA32_MTRR_PHYSBASE3

See Table 2-2.

Core

IA32_MTRR_PHYSMASK3

See Table 2-2.

Core

IA32_MTRR_PHYSBASE4

See Table 2-2.

Core

IA32_MTRR_PHYSMASK4

See Table 2-2.

Core

IA32_MTRR_PHYSBASE5

See Table 2-2.

Core

IA32_MTRR_PHYSMASK5

See Table 2-2.

Core

IA32_MTRR_PHYSBASE6

See Table 2-2.

Core

IA32_MTRR_PHYSMASK6

See Table 2-2.

Core

IA32_MTRR_PHYSBASE7

See Table 2-2.

Core

IA32_MTRR_PHYSMASK7

See Table 2-2.

Core

IA32_MTRR_FIX64K_00000

See Table 2-2.

Core

2-128 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-6. MSRs Common to Intel Atom® Processors (Silvermont and Newer Microarchitectures) (Contd.)

Bit Description

Scope

IA32_MTRR_FIX16K_80000

See Table 2-2.

Core

IA32_MTRR_FIX16K_A0000

See Table 2-2.

Core

IA32_MTRR_FIX4K_C0000

See Table 2-2.

Core

IA32_MTRR_FIX4K_C8000

See Table 2-2.

Core

IA32_MTRR_FIX4K_D0000

See Table 2-2.

Core

IA32_MTRR_FIX4K_D8000

See Table 2-2.

Core

IA32_MTRR_FIX4K_E0000

See Table 2-2.

Core

IA32_MTRR_FIX4K_E8000

See Table 2-2.

Core

IA32_MTRR_FIX4K_F0000

See Table 2-2.

Core

IA32_MTRR_FIX4K_F8000

See Table 2-2.

Core

IA32_PAT

See Table 2-2.

Core

IA32_MTRR_DEF_TYPE

Default Memory Types (R/W)

Core

See Table 2-2.

IA32_FIXED_CTR0

Fixed-Function Performance Counter Register 0 (R/W)

Core

See Table 2-2.

IA32_FIXED_CTR1

Fixed-Function Performance Counter Register 1 (R/W)

Core

See Table 2-2.

IA32_FIXED_CTR2

Fixed-Function Performance Counter Register 2 (R/W)

Core

See Table 2-2.

IA32_PERF_CAPABILITIES

See Table 2-2. See Section 20.4.1, “IA32_DEBUGCTL MSR.”

Core

IA32_FIXED_CTR_CTRL

Vol. 4

2-129

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-6. MSRs Common to Intel Atom® Processors (Silvermont and Newer Microarchitectures) (Contd.)

Bit Description

Scope

Fixed-Function-Counter Control Register (R/W)

Core

See Table 2-2.

IA32_PERF_GLOBAL_CTRL

See Table 2-2. See Section 22.6.2.2, “Global Counter Control Facilities.”

Core

MSR_CORE_C6_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

Core

ACPI C-States.

63:0

CORE C6 Residency Counter (R/O)

Value since last reset that this core is in processor-specific C6 states.

Counts at the TSC Frequency.

IA32_MC0_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Module

IA32_MC0_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

Module

IA32_MC0_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

Module

The IA32_MC0_ADDR register is either not implemented or contains no address if the ADDRV flag in the

IA32_MC0_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

IA32_MC1_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Module

IA32_MC1_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

Module

IA32_MC2_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Module

IA32_MC2_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

Module

IA32_MC2_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

Module

The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in the

IA32_MC2_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

IA32_MC3_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Core

IA32_MC3_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

Core

IA32_MC3_ADDR

2-130 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-6. MSRs Common to Intel Atom® Processors (Silvermont and Newer Microarchitectures) (Contd.)

Bit Description

Scope

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

Core

The MSR_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in the

MSR_MC3_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

IA32_MC4_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Core

IA32_MC4_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

Core

IA32_MC4_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

Core

The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the

MSR_MC4_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

IA32_MC5_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Package

IA32_MC5_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

Package

IA32_MC5_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

Package

The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the

MSR_MC4_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

IA32_VMX_BASIC

Reporting Register of Basic VMX Capabilities (R/O)

Core

See Table 2-2.

See Appendix A.1, “Basic VMX Information.”

IA32_VMX_PINBASED_CTLS

Capability Reporting Register of Pin-Based VM-Execution Controls (R/O)

Core

See Table 2-2.

See Appendix A.3, “VM-Execution Controls.”

IA32_VMX_PROCBASED_CTLS

Capability Reporting Register of Primary Processor-Based VM-Execution Controls (R/O)

Core

See Appendix A.3, “VM-Execution Controls.”

IA32_VMX_EXIT_CTLS

Capability Reporting Register of VM-Exit Controls (R/O)

Core

See Table 2-2.

See Appendix A.4, “VM-Exit Controls.”

IA32_VMX_ENTRY_CTLS

Vol. 4

2-131

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-6. MSRs Common to Intel Atom® Processors (Silvermont and Newer Microarchitectures) (Contd.)

Bit Description

Scope

Capability Reporting Register of VM-Entry Controls (R/O)

Core

See Table 2-2.

See Appendix A.5, “VM-Entry Controls.”

IA32_VMX_MISC

Reporting Register of Miscellaneous VMX Capabilities (R/O)

Core

See Table 2-2.

See Appendix A.6, “Miscellaneous Data.”

IA32_VMX_CR0_FIXED0

Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)

Core

See Table 2-2.

See Appendix A.7, “VMX-Fixed Bits in CR0.”

IA32_VMX_CR0_FIXED1

Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)

Core

See Table 2-2.

See Appendix A.7, “VMX-Fixed Bits in CR0.”

IA32_VMX_CR4_FIXED0

Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)

Core

See Table 2-2.

See Appendix A.8, “VMX-Fixed Bits in CR4.”

IA32_VMX_CR4_FIXED1

Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)

Core

See Table 2-2.

See Appendix A.8, “VMX-Fixed Bits in CR4.”

IA32_VMX_VMCS_ENUM

Capability Reporting Register of VMCS Field Enumeration (R/O)

Core

See Table 2-2.

See Appendix A.9, “VMCS Enumeration.”

IA32_VMX_PROCBASED_CTLS2

Capability Reporting Register of Secondary Processor-Based VM-Execution Controls (R/O)

Core

See Appendix A.3, “VM-Execution Controls.”

IA32_VMX_EPT_VPID_ENUM

Capability Reporting Register of EPT and VPID (R/O)

Core

See Table 2-2.

IA32_VMX_TRUE_PINBASED_CTLS

Capability Reporting Register of Pin-Based VM-Execution Flex Controls (R/O)

Core

See Table 2-2.

IA32_VMX_TRUE_PROCBASED_CTLS

Capability Reporting Register of Primary Processor-based VM-Execution Flex Controls (R/O)

Core

See Table 2-2.

IA32_VMX_TRUE_EXIT_CTLS

2-132 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-6. MSRs Common to Intel Atom® Processors (Silvermont and Newer Microarchitectures) (Contd.)

Bit Description

Scope

Capability Reporting Register of VM-Exit Flex Controls (R/O)

Core

See Table 2-2.

IA32_VMX_TRUE_ENTRY_CTLS

Capability Reporting Register of VM-Entry Flex Controls (R/O)

Core

See Table 2-2.

IA32_VMX_FMFUNC

Capability Reporting Register of VM-Function Controls (R/O)

Core

See Table 2-2.

IA32_A_PMC0

See Table 2-2.

Core

IA32_A_PMC1

See Table 2-2.

Core

IA32_DS_AREA

DS Save Area (R/W)

Core

See Table 2-2 and Section 22.6.3.4, “Debug Store (DS) Mechanism.”

MSR_CORE_C1_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

Core

ACPI C-States.

63:0

CORE C1 Residency Counter. (R/O)

Value since last reset that this core is in processor-specific C1 states.

Counts at the TSC frequency.

IA32_TSC_DEADLINE

TSC Target of Local APIC’s TSC Deadline Mode (R/W)

Core

See Table 2-2.

IA32_EFER

Extended Feature Enables

Core

See Table 2-2.

IA32_STAR

System Call Target Address (R/W)

Core

See Table 2-2.

IA32_LSTAR

IA-32e Mode System Call Target Address (R/W)

Core

See Table 2-2.

IA32_FMASK

System Call Flag Mask (R/W)

Core

See Table 2-2.

IA32_FS_BASE

Map of BASE Address of FS (R/W)

Core

See Table 2-2.

Vol. 4

2-133

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-6. MSRs Common to Intel Atom® Processors (Silvermont and Newer Microarchitectures) (Contd.)

Bit Description

Scope

IA32_GS_BASE

Map of BASE Address of GS (R/W)

Core

See Table 2-2.

IA32_KERNEL_GS_BASE

Swap Target of BASE Address of GS (R/W)

Core

See Table 2-2.

IA32_TSC_AUX

AUXILIARY TSC Signature (R/W)

Core

See Table 2-2.

Table 2-7 lists model-specific registers (MSRs) that are common to Intel Atom^® processors based on the Silver-

mont and Airmont microarchitectures but not newer microarchitectures.

Table 2-7. MSRs Common to the Silvermont and Airmont Microarchitectures

Bit Description

Scope

MSR_PLATFORM_ID

Model Specific Platform ID (R)

Module

7:0

Reserved.

13:8

Maximum Qualified Ratio (R)

The maximum allowed bus ratio.

49:13

Reserved.

52:50

See Table 2-2.

63:33

Reserved.

IA32_FEATURE_CONTROL

Control Features in Intel 64Processor (R/W)

Core

See Table 2-2.

Lock (R/WL)

Reserved.

Enable VMX outside SMX operation (R/WL)

MSR_LASTBRANCH_0_FROM_IP

Last Branch Record 0 From IP (R/W)

Core

One of eight pairs of last branch record registers on the last branch record stack. The From_IP part of the stack

contains pointers to the source instruction. See also:

• Last Branch Record Stack TOS at 1C9H.

• Section 20.5 and record format in Section 20.4.8.1.

MSR_LASTBRANCH_1_FROM_IP

Last Branch Record 1 From IP (R/W)

Core

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_2_FROM_IP

2-134 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-7. MSRs Common to the Silvermont and Airmont Microarchitectures (Contd.)

Bit Description

Scope

Last Branch Record 2 From IP (R/W)

Core

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_3_FROM_IP

Last Branch Record 3 From IP (R/W)

Core

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_4_FROM_IP

Last Branch Record 4 From IP (R/W)

Core

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_5_FROM_IP

Last Branch Record 5 From IP (R/W)

Core

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_6_FROM_IP

Last Branch Record 6 From IP (R/W)

Core

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_7_FROM_IP

Last Branch Record 7 From IP (R/W)

Core

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_0_TO_IP

Last Branch Record 0 To IP (R/W)

Core

One of eight pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains

pointers to the destination instruction.

MSR_LASTBRANCH_1_TO_IP

Last Branch Record 1 To IP (R/W)

Core

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_2_TO_IP

Last Branch Record 2 To IP (R/W)

Core

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_3_TO_IP

Last Branch Record 3 To IP (R/W)

Core

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_4_TO_IP

Last Branch Record 4 To IP (R/W)

Core

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_5_TO_IP

Last Branch Record 5 To IP (R/W)

Core

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_6_TO_IP

Last Branch Record 6 To IP (R/W)

Core

See description of MSR_LASTBRANCH_0_TO_IP.

Vol. 4

2-135

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-7. MSRs Common to the Silvermont and Airmont Microarchitectures (Contd.)

Bit Description

Scope

MSR_LASTBRANCH_7_TO_IP

Last Branch Record 7 To IP (R/W)

Core

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_PLATFORM_INFO

Platform Information: Contains power management and other model specific features enumeration. See

Package

http://biosbits.org.

7:0

Reserved.

15:8

Maximum Non-Turbo Ratio (R/O)

Package

This is the ratio of the maximum frequency that does not require turbo.

Frequency = ratio * Scalable Bus Frequency.

63:16

Reserved.

MSR_PKG_CST_CONFIG_CONTROL

C-State Configuration Control (R/W)

Module

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

ACPI C-States.

See http://biosbits.org.

2:0

Package C-State Limit (R/W)

Specifies the lowest processor-specific C-state code name (consuming the

least power) for the package. The default is set as factory-configured

package C-state limit.

The following C-state code name encodings are supported:

000b: C0 (no package C-sate support)

001b: C1 (Behavior is the same as 000b)

100b: C4

110b: C6

111b: C7 (Silvermont only)

9:3

Reserved.

I/O MWAIT Redirection Enable (R/W)

When set, will map IO_read instructions sent to IO register specified by

MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.

14:11

Reserved.

CFG Lock (R/WO)

When set, locks bits 15:0 of this register until next reset.

63:16

Reserved.

MSR_BBL_CR_CTL3

Control Register 3

Module

Used to configure the L2 Cache.

L2 Hardware Enabled (R/O)

1 = If the L2 is hardware-enabled.

0 = Indicates if the L2 is hardware-disabled.

7:1

Reserved.

2-136 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-7. MSRs Common to the Silvermont and Airmont Microarchitectures (Contd.)

Bit Description

Scope

L2 Enabled (R/W)

1 = L2 cache has been initialized.

0 = Disabled (default).

Until this bit is set the processor will not respond to the WBINVD instruction

or the assertion of the FLUSH# input.

22:9

Reserved.

L2 Not Present (R/O)

0 = L2 Present.

1 = L2 Not Present.

63:24

Reserved.

IA32_MISC_ENABLE

Enable Misc. Processor Features (R/W)

Allows a variety of processor functions to be enabled and disabled.

Fast-Strings Enable

Core

See Table 2-2.

2:1

Reserved.

Automatic Thermal Control Circuit Enable (R/W)

Module

See Table 2-2. Default value is 0.

6:4

Reserved.

Performance Monitoring Available (R)

Core

See Table 2-2.

10:8

Reserved.

Branch Trace Storage Unavailable (R/O)

Core

See Table 2-2.

Processor Event Based Sampling Unavailable (R/O)

Core

See Table 2-2.

15:13

Reserved.

Enhanced Intel SpeedStep Technology Enable (R/W)

Module

See Table 2-2.

ENABLE MONITOR FSM (R/W)

Core

See Table 2-2.

21:19

Reserved.

Limit CPUID Maxval (R/W)

Core

See Table 2-2.

xTPR Message Disable (R/W)

Module

See Table 2-2.

33:24

Reserved.

XD Bit Disable (R/W)

Core

See Table 2-3.

37:35

Reserved.

Vol. 4

2-137

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-7. MSRs Common to the Silvermont and Airmont Microarchitectures (Contd.)

Bit Description

Scope

Turbo Mode Disable (R/W)

Module

When set to 1 on processors that support Intel Turbo Boost Technology, the

turbo mode feature is disabled and the IDA_Enable feature flag will be

cleared (CPUID.06H:EAX[1] =0).

When set to a 0 on processors that support IDA, CPUID.06H:EAX[1] reports

the processor’s support of turbo mode is enabled.

Note: The power-on default value is used by BIOS to detect hardware

support of turbo mode. If the power-on default value is 1, turbo mode is

available in the processor. If the power-on default value is 0, turbo mode is

not available.

63:39

Reserved.

MSR_LBR_SELECT

Last Branch Record Filtering Select Register (R/W)

Core

See Section 20.9.2, “Filtering of Last Branch Records.”

CPL_EQ_0

CPL_NEQ_0

JCC

NEAR_REL_CALL

NEAR_IND_CALL

NEAR_RET

NEAR_IND_JMP

NEAR_REL_JMP

FAR_BRANCH

63:9

Reserved.

MSR_LASTBRANCH_TOS

Last Branch Record Stack TOS (R/W)

Core

Contains an index (bits 0-2) that points to the MSR containing the most recent branch record.

See MSR_LASTBRANCH_0_FROM_IP.

IA32_PERF_GLOBAL_STATUS

See Table 2-2. See Section 22.6.2.2, “Global Counter Control Facilities.”

Core

IA32_PERF_GLOBAL_OVF_CTRL

See Table 2-2. See Section 22.6.2.2, “Global Counter Control Facilities.”

Core

IA32_PEBS_ENABLE (MSR_PEBS_ENABLE)

See Table 2-2. See Section 22.6.2.4, “Processor Event Based Sampling (PEBS).”

Core

Enable PEBS for precise event on IA32_PMC0 (R/W)

MSR_PKG_C6_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

Package

ACPI C-States.

63:0

Package C6 Residency Counter (R/O)

Value since last reset that this package is in processor-specific C6 states.

Counts at the TSC Frequency.

2-138 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-7. MSRs Common to the Silvermont and Airmont Microarchitectures (Contd.)

Bit Description

Scope

MSR_MC6_RESIDENCY_COUNTER

Module C6 Residency Counter (R/0)

Module

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

ACPI C-States.

63:0

Time that this module is in module-specific C6 states since last reset. Counts

at 1 Mhz frequency.

2.4.1

MSRs with Model-Specific Behavior in the Silvermont Microarchitecture

Table 2-8 lists MSRs that are specific to the Intel Atom^® processor E3000 Series (CPUID Signature

DisplayFamily_DisplayModel value of 06_37H) and Intel Atom processors (CPUID Signature

DisplayFamily_DisplayModel value of 06_4AH, 06_5AH, or 06_5DH).

Table 2-8. Specific MSRs Supported by Intel Atom® Processors with a CPUID Signature DisplayFamily_DisplayModel

Value of 06_37H, 06_4AH, 06_5AH, or 06_5DH

Bit Description

Scope

MSR_FSB_FREQ

Scaleable Bus Speed (R/O)

Module

This field indicates the intended scalable bus clock speed for processors based on Silvermont microarchitecture.

2:0

•

100B: 080.0 MHz

•

000B: 083.3 MHz

•

001B: 100.0 MHz

•

010B: 133.3 MHz

•

011B: 116.7 MHz

63:3

Reserved.

MSR_RAPL_POWER_UNIT

Unit Multipliers used in RAPL Interfaces (R/O)

Package

See Section 17.10.1, “RAPL Interfaces.”

3:0

Power Units

Power related information (in milliWatts) is based on the multiplier,

2^PU;

where PU is an unsigned integer represented by bits 3:0. Default value is

0101b, indicating power unit is in 32 milliWatts increment.

7:4

Reserved.

12:8

Energy Status Units

Energy related information (in microJoules) is based on the multiplier, 2^ESU;

where ESU is an unsigned integer represented by bits 12:8. Default value is

00101b, indicating energy unit is in 32 microJoules increment.

15:13

Reserved.

19:16

Time Unit

The value is 0000b, indicating time unit is in one second.

63:20

Reserved.

MSR_PKG_POWER_LIMIT

PKG RAPL Power Limit Control (R/W)

Package

Vol. 4

2-139

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-8. Specific MSRs Supported by Intel Atom® Processors with a CPUID Signature DisplayFamily_DisplayModel

Value of 06_37H, 06_4AH, 06_5AH, or 06_5DH (Contd.)

Bit Description

Scope

14:0

Package Power Limit #1 (R/W)

See Section 17.10.3, “Package RAPL Domain,” and MSR_RAPL_POWER_UNIT

in Table 2-8.

Enable Power Limit #1 (R/W)

See Section 17.10.3, “Package RAPL Domain.”

Package Clamping Limitation #1 (R/W)

See Section 17.10.3, “Package RAPL Domain.”

23:17

Time Window for Power Limit #1 (R/W)

In unit of second. If 0 is specified in bits [23:17], defaults to 1 second

window.

63:24

Reserved.

MSR_PKG_ENERGY_STATUS

PKG Energy Status (R/O)

Package

See Section 17.10.3, “Package RAPL Domain,” and MSR_RAPL_POWER_UNIT in Table 2-8.

MSR_PP0_ENERGY_STATUS

PP0 Energy Status (R/O)

Package

See Section 17.10.4, “PP0/PP1 RAPL Domains,” and MSR_RAPL_POWER_UNIT in Table 2-8.

Table 2-9 lists model-specific registers (MSRs) that are specific to the Intel Atom^® processor E3000 Series (CPUID

Signature DisplayFamily_DisplayModel value of 06_37H).

Table 2-9. Specific MSRs Supported by the Intel Atom® Processor E3000 Series with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_37H

Bit Description

Scope

MSR_CC6_DEMOTION_POLICY_CONFIG

Core C6 Demotion Policy Config MSR

Package

63:0

Controls per-core C6 demotion policy. Writing a value of 0 disables core

level HW demotion policy.

MSR_MC6_DEMOTION_POLICY_CONFIG

Module C6 Demotion Policy Config MSR

Package

63:0

Controls module (i.e., two cores sharing the second-level cache) C6

demotion policy. Writing a value of 0 disables module level HW demotion

policy.

MSR_MC6_RESIDENCY_COUNTER

Module C6 Residency Counter (R/0)

Module

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

ACPI C-States.

63:0

Time that this module is in module-specific C6 states since last reset.

Counts at 1 Mhz frequency.

2-140 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-10 lists model-specific registers (MSRs) that are specific to Intel Atom^® processor C2000 Series (CPUID

Signature DisplayFamily_DisplayModel value of 06_4DH).

Table 2-10. Specific MSRs Supported by Intel Atom® Processor C2000 Series with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_4DH

Bit Description

Scope

MSR_MISC_FEATURE_CONTROL

Miscellaneous Feature Control (R/W)

L2 Hardware Prefetcher Disable (R/W)

Core

If 1, disables the L2 hardware prefetcher, which fetches additional lines of

code or data into the L2 cache.

Reserved.

DCU Hardware Prefetcher Disable (R/W)

Core

If 1, disables the L1 data cache prefetcher, which fetches the next cache

line into L1 data cache.

63:3

Reserved.

MSR_TURBO_RATIO_LIMIT

Maximum Ratio Limit of Turbo Mode (R/W)

Package

7:0

Maximum Ratio Limit for 1C

Package

Maximum turbo ratio limit of 1 core active.

15:8

Maximum Ratio Limit for 2C

Package

Maximum turbo ratio limit of 2 core active.