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Intel 64 and IA-32 Architectures. Software Developer’s Manual (2026) - page 73

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

9

BTS_OFF_OS

10

BTS_OFF_USER

11

FREEZE_LBR_ON_PMI

12

FREEZE_PERFMON_ON_PMI

13

ENABLE_UNCORE_PMI

14

FREEZE_WHILE_SMM

63:15

Reserved.

Register Address: 1DDH, 477

MSR_LER_FROM_LIP

Last Exception Record From Linear IP (R/W)

Thread

Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was

generated or the last interrupt that was handled.

Register Address: 1DEH, 478

MSR_LER_TO_LIP

Last Exception Record To Linear IP (R/W)

Thread

This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last

exception that was generated or the last interrupt that was handled.

Register Address: 1F2H, 498

IA32_SMRR_PHYSBASE

See Table 2-2.

Core

Register Address: 1F3H, 499

IA32_SMRR_PHYSMASK

See Table 2-2.

Core

Register Address: 1FCH, 508

MSR_POWER_CTL

See http://biosbits.org.

Core

Register Address: 200H, 512

IA32_MTRR_PHYSBASE0

See Table 2-2.

Thread

Register Address: 201H, 513

IA32_MTRR_PHYSMASK0

See Table 2-2.

Thread

Register Address: 202H, 514

IA32_MTRR_PHYSBASE1

See Table 2-2.

Thread

Register Address: 203H, 515

IA32_MTRR_PHYSMASK1

See Table 2-2.

Thread

Register Address: 204H, 516

IA32_MTRR_PHYSBASE2

See Table 2-2.

Thread

Register Address: 205H, 517

IA32_MTRR_PHYSMASK2

See Table 2-2.

Thread

Register Address: 206H, 518

IA32_MTRR_PHYSBASE3

See Table 2-2.

Thread

Register Address: 207H, 519

IA32_MTRR_PHYSMASK3

See Table 2-2.

Thread

Register Address: 208H, 520

IA32_MTRR_PHYSBASE4

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Register Address: 26CH, 620

IA32_MTRR_FIX4K_E0000

See Table 2-2.

Thread

Register Address: 26DH, 621

IA32_MTRR_FIX4K_E8000

See Table 2-2.

Thread

Register Address: 26EH, 622

IA32_MTRR_FIX4K_F0000

See Table 2-2.

Thread

Register Address: 26FH, 623

IA32_MTRR_FIX4K_F8000

See Table 2-2.

Thread

Register Address: 277H, 631

IA32_PAT

See Table 2-2.

Thread

Register Address: 280H, 640

IA32_MC0_CTL2

See Table 2-2.

Core

Register Address: 281H, 641

IA32_MC1_CTL2

See Table 2-2.

Core

Register Address: 282H, 642

IA32_MC2_CTL2

See Table 2-2.

Core

Register Address: 283H, 643

IA32_MC3_CTL2

See Table 2-2.

Core

Register Address: 284H, 644

IA32_MC4_CTL2

Always 0 (CMCI not supported).

Package

Register Address: 2FFH, 767

IA32_MTRR_DEF_TYPE

Default Memory Types (R/W)

Thread

See Table 2-2.

Register Address: 309H, 777

IA32_FIXED_CTR0

Fixed-Function Performance Counter Register 0 (R/W)

Thread

See Table 2-2.

Register Address: 30AH, 778

IA32_FIXED_CTR1

Fixed-Function Performance Counter Register 1 (R/W)

Thread

See Table 2-2.

Register Address: 30BH, 779

IA32_FIXED_CTR2

Fixed-Function Performance Counter Register 2 (R/W)

Thread

See Table 2-2.

Register Address: 345H, 837

IA32_PERF_CAPABILITIES

See Table 2-2 and Section 20.4.1, “IA32_DEBUGCTL MSR.”

Thread

5:0

LBR Format

See Table 2-2.

6

PEBS Record Format.

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

7

PEBSSaveArchRegs

See Table 2-2.

11:8

PEBS_REC_FORMAT

See Table 2-2.

12

SMM_FREEZE

See Table 2-2.

63:13

Reserved.

Register Address: 38DH, 909

IA32_FIXED_CTR_CTRL

Fixed-Function-Counter Control Register (R/W)

Thread

See Table 2-2.

Register Address: 38EH, 910

IA32_PERF_GLOBAL_STATUS

See Table 2-2 and Section 22.6.2.2, “Global Counter Control Facilities.”

0

Ovf_PMC0

Thread

1

Ovf_PMC1

Thread

2

Ovf_PMC2

Thread

3

Ovf_PMC3

Thread

4

Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4)

Core

5

Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5)

Core

6

Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6)

Core

7

Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7)

Core

31:8

Reserved.

32

Ovf_FixedCtr0

Thread

33

Ovf_FixedCtr1

Thread

34

Ovf_FixedCtr2

Thread

60:35

Reserved.

61

Ovf_Uncore

Thread

62

Ovf_BufDSSAVE

Thread

63

CondChgd

Thread

Register Address: 38FH, 911

IA32_PERF_GLOBAL_CTRL

See Table 2-2 and Section 22.6.2.2, “Global Counter Control Facilities.”

Thread

0

Set 1 to enable PMC0 to count.

Thread

1

Set 1 to enable PMC1 to count.

Thread

2

Set 1 to enable PMC2 to count.

Thread

3

Set 1 to enable PMC3 to count.

Thread

4

Set 1 to enable PMC4 to count (if CPUID.0AH:EAX[15:8] > 4).

Core

5

Set 1 to enable PMC5 to count (if CPUID.0AH:EAX[15:8] > 5).

Core

6

Set 1 to enable PMC6 to count (if CPUID.0AH:EAX[15:8] > 6).

Core

7

Set 1 to enable PMC7 to count (if CPUID.0AH:EAX[15:8] > 7).

Core

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

31:8

Reserved.

32

Set 1 to enable FixedCtr0 to count.

Thread

33

Set 1 to enable FixedCtr1 to count.

Thread

34

Set 1 to enable FixedCtr2 to count.

Thread

63:35

Reserved.

Register Address: 390H, 912

IA32_PERF_GLOBAL_OVF_CTRL

See Table 2-2 and Section 22.6.2.2, “Global Counter Control Facilities.”

0

Set 1 to clear Ovf_PMC0.

Thread

1

Set 1 to clear Ovf_PMC1.

Thread

2

Set 1 to clear Ovf_PMC2.

Thread

3

Set 1 to clear Ovf_PMC3.

Thread

4

Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).

Core

5

Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).

Core

6

Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).

Core

7

Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).

Core

31:8

Reserved.

32

Set 1 to clear Ovf_FixedCtr0.

Thread

33

Set 1 to clear Ovf_FixedCtr1.

Thread

34

Set 1 to clear Ovf_FixedCtr2.

Thread

60:35

Reserved.

61

Set 1 to clear Ovf_Uncore.

Thread

62

Set 1 to clear Ovf_BufDSSAVE.

Thread

63

Set 1 to clear CondChgd.

Thread

Register Address: 3F1H, 1009

IA32_PEBS_ENABLE (MSR_PEBS_ENABLE)

See Section 22.3.1.1.1, “Processor Event Based Sampling (PEBS).”

Thread

0

Enable PEBS on IA32_PMC0. (R/W)

1

Enable PEBS on IA32_PMC1. (R/W)

2

Enable PEBS on IA32_PMC2. (R/W)

3

Enable PEBS on IA32_PMC3. (R/W)

31:4

Reserved.

32

Enable Load Latency on IA32_PMC0. (R/W)

33

Enable Load Latency on IA32_PMC1. (R/W)

34

Enable Load Latency on IA32_PMC2. (R/W)

35

Enable Load Latency on IA32_PMC3. (R/W)

62:36

Reserved.

63

Enable Precise Store (R/W)

Register Address: 3F6H, 1014

MSR_PEBS_LD_LAT

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

See Section 22.3.1.1.2, “Load Latency Performance Monitoring Facility.”

Thread

15:0

Minimum threshold latency value of tagged load operation that will be

counted. (R/W)

63:36

Reserved.

Register Address: 3F8H, 1016

MSR_PKG_C3_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

Package

ACPI C-States.

63:0

Package C3 Residency Counter (R/O)

Value since last reset that this package is in processor-specific C3 states.

Count at the same frequency as the TSC.

Register Address: 3F9H, 1017

MSR_PKG_C6_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

Package

ACPI C-States.

63:0

Package C6 Residency Counter. (R/O)

Value since last reset that this package is in processor-specific C6 states.

Count at the same frequency as the TSC.

Register Address: 3FAH, 1018

MSR_PKG_C7_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

Package

ACPI C-States.

63:0

Package C7 Residency Counter (R/O)

Value since last reset that this package is in processor-specific C7 states.

Count at the same frequency as the TSC.

Register Address: 3FCH, 1020

MSR_CORE_C3_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

Core

ACPI C-States.

63:0

CORE C3 Residency Counter (R/O)

Value since last reset that this core is in processor-specific C3 states. Count

at the same frequency as the TSC.

Register Address: 3FDH, 1021

MSR_CORE_C6_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

Core

ACPI C-States.

63:0

CORE C6 Residency Counter (R/O)

Value since last reset that this core is in processor-specific C6 states. Count

at the same frequency as the TSC.

Register Address: 3FEH, 1022

MSR_CORE_C7_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

Core

ACPI C-States.

63:0

CORE C7 Residency Counter (R/O)

Value since last reset that this core is in processor-specific C7 states. Count

at the same frequency as the TSC.

Register Address: 400H, 1024

IA32_MC0_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Core

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

63:2

Reserved.

Register Address: 411H, 1041

IA32_MC4_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 19.

Core

Register Address: 480H, 1152

IA32_VMX_BASIC

Reporting Register of Basic VMX Capabilities (R/O)

Thread

See Table 2-2 and Appendix A.1, “Basic VMX Information.”

Register Address: 481H, 1153

IA32_VMX_PINBASED_CTLS

Capability Reporting Register of Pin-Based VM-Execution Controls (R/O)

Thread

See Table 2-2 and Appendix A.3, “VM-Execution Controls.”

Register Address: 482H, 1154

IA32_VMX_PROCBASED_CTLS

Capability Reporting Register of Primary Processor-Based VM-Execution Controls (R/O)

Thread

See Appendix A.3, “VM-Execution Controls.”

Register Address: 483H, 1155

IA32_VMX_EXIT_CTLS

Capability Reporting Register of VM-Exit Controls (R/O)

Thread

See Table 2-2 and Appendix A.4, “VM-Exit Controls.”

Register Address: 484H, 1156

IA32_VMX_ENTRY_CTLS

Capability Reporting Register of VM-Entry Controls (R/O)

Thread

See Table 2-2 and Appendix A.5, “VM-Entry Controls.”

Register Address: 485H, 1157

IA32_VMX_MISC

Reporting Register of Miscellaneous VMX Capabilities (R/O)

Thread

See Table 2-2 and Appendix A.6, “Miscellaneous Data.”

Register Address: 486H, 1158

IA32_VMX_CR0_FIXED0

Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)

Thread

See Table 2-2 and Appendix A.7, “VMX-Fixed Bits in CR0.”

Register Address: 487H, 1159

IA32_VMX_CR0_FIXED1

Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)

Thread

See Table 2-2 and Appendix A.7, “VMX-Fixed Bits in CR0.”

Register Address: 488H, 1160

IA32_VMX_CR4_FIXED0

Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)

Thread

See Table 2-2 and Appendix A.8, “VMX-Fixed Bits in CR4.”

Register Address: 489H, 1161

IA32_VMX_CR4_FIXED1

Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)

Thread

See Table 2-2 and Appendix A.8, “VMX-Fixed Bits in CR4.”

Register Address: 48AH, 1162

IA32_VMX_VMCS_ENUM

Capability Reporting Register of VMCS Field Enumeration (R/O)

Thread

See Table 2-2 and Appendix A.9, “VMCS Enumeration.”

Register Address: 48BH, 1163

IA32_VMX_PROCBASED_CTLS2

Capability Reporting Register of Secondary Processor-Based VM-Execution Controls (R/O)

Thread

See Appendix A.3, “VM-Execution Controls.”

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Register Address: 48CH, 1164

IA32_VMX_EPT_VPID_ENUM

Capability Reporting Register of EPT and VPID (R/O)

Thread

See Table 2-2

Register Address: 48DH, 1165

IA32_VMX_TRUE_PINBASED_CTLS

Capability Reporting Register of Pin-Based VM-Execution Flex Controls (R/O)

Thread

See Table 2-2

Register Address: 48EH, 1166

IA32_VMX_TRUE_PROCBASED_CTLS

Capability Reporting Register of Primary Processor-Based VM-Execution Flex Controls (R/O)

Thread

See Table 2-2

Register Address: 48FH, 1167

IA32_VMX_TRUE_EXIT_CTLS

Capability Reporting Register of VM-Exit Flex Controls (R/O)

Thread

See Table 2-2

Register Address: 490H, 1168

IA32_VMX_TRUE_ENTRY_CTLS

Capability Reporting Register of VM-Entry Flex Controls (R/O)

Thread

See Table 2-2

Register Address: 4C1H, 1217

IA32_A_PMC0

See Table 2-2.

Thread

Register Address: 4C2H, 1218

IA32_A_PMC1

See Table 2-2.

Thread

Register Address: 4C3H, 1219

IA32_A_PMC2

See Table 2-2.

Thread

Register Address: 4C4H, 1220

IA32_A_PMC3

See Table 2-2.

Thread

Register Address: 4C5H, 1221

IA32_A_PMC4

See Table 2-2.

Core

Register Address: 4C6H, 1222

IA32_A_PMC5

See Table 2-2.

Core

Register Address: 4C7H, 1223

IA32_A_PMC6

See Table 2-2.

Core

Register Address: 4C8H, 1224

IA32_A_PMC7

See Table 2-2.

Core

Register Address: 600H, 1536

IA32_DS_AREA

DS Save Area (R/W)

Thread

See Table 2-2 and Section 22.6.3.4, “Debug Store (DS) Mechanism.”

Register Address: 606H, 1542

MSR_RAPL_POWER_UNIT

Unit Multipliers used in RAPL Interfaces (R/O)

Package

See Section 17.10.1, “RAPL Interfaces.”

Register Address: 60AH, 1546

MSR_PKGC3_IRTL

2-242 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Package C3 Interrupt Response Limit (R/W)

Package

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

ACPI C-States.

9:0

Interrupt Response Time Limit (R/W)

Specifies the limit that should be used to decide if the package should be

put into a package C3 state.

12:10

Time Unit (R/W)

Specifies the encoding value of time unit of the interrupt response time

limit. The following time unit encodings are supported:

000b: 1 ns

001b: 32 ns

010b: 1024 ns

011b: 32768 ns

100b: 1048576 ns

101b: 33554432 ns

14:13

Reserved.

15

Valid (R/W)

Indicates whether the values in bits 12:0 are valid and can be used by the

processor for package C-sate management.

63:16

Reserved.

Register Address: 60BH, 1547

MSR_PKGC6_IRTL

Package C6 Interrupt Response Limit (R/W)

Package

This MSR defines the budget allocated for the package to exit from a C6 to a C0 state, where an interrupt request can

be delivered to the core and serviced. Additional core-exit latency may be applicable depending on the actual C-state

the core is in.

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

ACPI C-states.

9:0

Interrupt Response Time Limit (R/W)

Specifies the limit that should be used to decide if the package should be

put into a package C6 state.

12:10

Time Unit (R/W)

Specifies the encoding value of time unit of the interrupt response time

limit. The following time unit encodings are supported:

000b: 1 ns

001b: 32 ns

010b: 1024 ns

011b: 32768 ns

100b: 1048576 ns

101b: 33554432 ns

14:13

Reserved.

15

Valid (R/W)

Indicates whether the values in bits 12:0 are valid and can be used by the

processor for package C-sate management.

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Last Branch Record 2 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6C3H, 1731

MSR_LASTBRANCH_3_TO_IP

Last Branch Record 3 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6C4H, 1732

MSR_LASTBRANCH_4_TO_IP

Last Branch Record 4 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6C5H, 1733

MSR_LASTBRANCH_5_TO_IP

Last Branch Record 5 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6C6H, 1734

MSR_LASTBRANCH_6_TO_IP

Last Branch Record 6 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6C7H, 1735

MSR_LASTBRANCH_7_TO_IP

Last Branch Record 7 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6C8H, 1736

MSR_LASTBRANCH_8_TO_IP

Last Branch Record 8 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6C9H, 1737

MSR_LASTBRANCH_9_TO_IP

Last Branch Record 9 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6CAH, 1738

MSR_LASTBRANCH_10_TO_IP

Last Branch Record 10 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6CBH, 1739

MSR_LASTBRANCH_11_TO_IP

Last Branch Record 11 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6CCH, 1740

MSR_LASTBRANCH_12_TO_IP

Last Branch Record 12 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6CDH, 1741

MSR_LASTBRANCH_13_TO_IP

Last Branch Record 13 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6CEH, 1742

MSR_LASTBRANCH_14_TO_IP

Last Branch Record 14 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6CFH, 1743

MSR_LASTBRANCH_15_TO_IP

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Last Branch Record 15 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

Register Address: 6E0H, 1760

IA32_TSC_DEADLINE

See Table 2-2.

Thread

Register Address: 802H-83FH, 2050-

X2APIC MSRs

2111

See Table 2-2.

Thread

Register Address: C000_0080H

IA32_EFER

Extended Feature Enables

Thread

See Table 2-2.

Register Address: C000_0081H

IA32_STAR

System Call Target Address (R/W)

Thread

See Table 2-2.

Register Address: C000_0082H

IA32_LSTAR

IA-32e Mode System Call Target Address (R/W)

Thread

See Table 2-2.

Register Address: C000_0084H

IA32_FMASK

System Call Flag Mask (R/W)

Thread

See Table 2-2.

Register Address: C000_0100H

IA32_FS_BASE

Map of BASE Address of FS (R/W)

Thread

See Table 2-2.

Register Address: C000_0101H

IA32_GS_BASE

Map of BASE Address of GS (R/W)

Thread

See Table 2-2.

Register Address: C000_0102H

IA32_KERNEL_GS_BASE

Swap Target of BASE Address of GS (R/W)

Thread

See Table 2-2.

Register Address: C000_0103H

IA32_TSC_AUX

AUXILIARY TSC Signature (R/W)

Thread

See Table 2-2 and Section 20.17.2, “IA32_TSC_AUX Register and RDTSCP Support.”

2.11.1 MSRs in the 2nd Generation Intel® Core™ Processor Family Based on Sandy Bridge

Microarchitecture

Table 2-21 and Table 2-22 list model-specific registers (MSRs) that are specific to the 2nd generation Intel^® Core™

processor family based on the Sandy Bridge microarchitecture. These processors have a CPUID Signature

DisplayFamily_DisplayModel value of 06_2AH; see Table 2-1.

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-21. MSRs Supported by the 2nd Generation Intel® Core™ Processors (Sandy Bridge Microarchitecture)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Register Address: 1ADH, 429

MSR_TURBO_RATIO_LIMIT

Maximum Ratio Limit of Turbo Mode

Package

R/O if MSR_PLATFORM_INFO.[28] = 0.

R/W if MSR_PLATFORM_INFO.[28] = 1.

7:0

Maximum Ratio Limit for 1C

Package

Maximum turbo ratio limit of 1 core active.

15:8

Maximum Ratio Limit for 2C

Package

Maximum turbo ratio limit of 2 core active.

23:16

Maximum Ratio Limit for 3C

Package

Maximum turbo ratio limit of 3 core active.

31:24

Maximum Ratio Limit for 4C

Package

Maximum turbo ratio limit of 4 core active.

63:32

Reserved.

Register Address: 60CH, 1548

MSR_PKGC7_IRTL

Package C7 Interrupt Response Limit (R/W)

Package

This MSR defines the budget allocated for the package to exit from a C7 to a C0 state, where interrupt request can be

delivered to the core and serviced. Additional core-exit latency may be applicable depending on the actual C-state the

core is in.

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

ACPI C-states.

9:0

Interrupt Response Time Limit (R/W)

Specifies the limit that should be used to decide if the package should be

put into a package C7 state.

12:10

Time Unit (R/W)

Specifies the encoding value of time unit of the interrupt response time

limit. The following time unit encodings are supported:

000b: 1 ns

001b: 32 ns

010b: 1024 ns

011b: 32768 ns

100b: 1048576 ns

101b: 33554432 ns

14:13

Reserved.

15

Valid (R/W)

Indicates whether the values in bits 12:0 are valid and can be used by

the processor for package C-sate management.

63:16

Reserved.

Register Address: 639H, 1593

MSR_PP0_ENERGY_STATUS

PP0 Energy Status (R/O)

Package

See Section 17.10.4, “PP0/PP1 RAPL Domains.”

Register Address: 63AH, 1594

MSR_PP0_POLICY

2-248 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-21. MSRs Supported by the 2nd Generation Intel® Core™ Processors (Sandy Bridge Microarchitecture)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

PP0 Balance Policy (R/W)

Package

See Section 17.10.4, “PP0/PP1 RAPL Domains.”

Register Address: 640H, 1600

MSR_PP1_POWER_LIMIT

PP1 RAPL Power Limit Control (R/W)

Package

See Section 17.10.4, “PP0/PP1 RAPL Domains.”

Register Address: 641H, 1601

MSR_PP1_ENERGY_STATUS

PP1 Energy Status (R/O)

Package

See Section 17.10.4, “PP0/PP1 RAPL Domains.”

Register Address: 642H, 1602

MSR_PP1_POLICY

PP1 Balance Policy (R/W)

Package

See Section 17.10.4, “PP0/PP1 RAPL Domains.”

See Table 2-20, Table 2-21, and Table 2-22 for MSR definitions applicable to processors with a CPUID Signature

DisplayFamily_DisplayModel value of 06_2AH.

Table 2-22 lists the MSRs of uncore PMU for Intel processors with a CPUID Signature DisplayFamily_DisplayModel

value of 06_2AH.

Table 2-22. Uncore PMU MSRs Supported by 2nd Generation Intel® Core™ Processors

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Register Address: 391H, 913

MSR_UNC_PERF_GLOBAL_CTRL

Uncore PMU Global Control

Package

0

Slice 0 select.

1

Slice 1 select.

2

Slice 2 select.

3

Slice 3 select.

4

Slice 4 select.

18:5

Reserved.

29

Enable all uncore counters.

30

Enable wake on PMI.

31

Enable Freezing counter when overflow.

63:32

Reserved.

Register Address: 392H, 914

MSR_UNC_PERF_GLOBAL_STATUS

Uncore PMU Main Status

Package

0

Fixed counter overflowed.

1

An ARB counter overflowed.

2

Reserved.

3

A CBox counter overflowed (on any slice).

63:4

Reserved.

Vol. 4

2-249

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-22. Uncore PMU MSRs Supported by 2nd Generation Intel® Core™ Processors (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Register Address: 749H, 1865

MSR_UNC_CBO_4_PERFCTR3

Uncore C-Box 4, Performance Counter 3

Package

2.11.2 MSRs in the Intel® Xeon® Processor E5 Family Based on Sandy Bridge

Microarchitecture

Table 2-23 lists additional model-specific registers (MSRs) that are specific to the Intel^® Xeon^® Processor E5

Family based on Sandy Bridge microarchitecture. These processors have a CPUID Signature

DisplayFamily_DisplayModel value of 06_2DH, and also support MSRs listed in Table 2-20 and Table 2-24.

Table 2-23. Additional MSRs Supported by the Intel® Xeon® Processors E5 Family Based on Sandy Bridge

Microarchitecture

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Register Address: 17FH, 383

MSR_ERROR_CONTROL

MC Bank Error Configuration (R/W)

Package

0

Reserved.

1

MemError Log Enable (R/W)

When set, enables IMC status bank to log additional info in bits 36:32.

63:2

Reserved.

Register Address: 1ADH, 429

MSR_TURBO_RATIO_LIMIT

Maximum Ratio Limit of Turbo Mode

Package

R/O if MSR_PLATFORM_INFO.[28] = 0. R/W if MSR_PLATFORM_INFO.[28] = 1.

7:0

Maximum Ratio Limit for 1C

Package

Maximum turbo ratio limit of 1 core active.

15:8

Maximum Ratio Limit for 2C

Package

Maximum turbo ratio limit of 2 cores active.

23:16

Maximum Ratio Limit for 3C

Package

Maximum turbo ratio limit of 3 cores active.

31:24

Maximum Ratio Limit for 4C

Package

Maximum turbo ratio limit of 4 cores active.

39:32

Maximum Ratio Limit for 5C

Package

Maximum turbo ratio limit of 5 cores active.

47:40

Maximum Ratio Limit for 6C

Package

Maximum turbo ratio limit of 6 cores active.

55:48

Maximum Ratio Limit for 7C

Package

Maximum turbo ratio limit of 7 cores active.

63:56

Maximum Ratio Limit for 8C

Package

Maximum turbo ratio limit of 8 cores active.

Register Address: 285H, 645

IA32_MC5_CTL2

See Table 2-2.

Package

Vol. 4

2-253

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-23. Additional MSRs Supported by the Intel® Xeon® Processors E5 Family Based on Sandy Bridge

Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Register Address: 44DH, 1101

IA32_MC19_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 19.

Package

Register Address: 44EH, 1102

IA32_MC19_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

Package

Register Address: 44FH, 1103

IA32_MC19_MISC

See Section 18.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Register Address: 613H, 1555

MSR_PKG_PERF_STATUS

Package RAPL Perf Status (R/O)

Package

Register Address: 618H, 1560

MSR_DRAM_POWER_LIMIT

DRAM RAPL Power Limit Control (R/W)

Package

See Section 17.10.5, “DRAM RAPL Domain.”

Register Address: 619H, 1561

MSR_DRAM_ENERGY_STATUS

DRAM Energy Status (R/O)

Package

See Section 17.10.5, “DRAM RAPL Domain.”

Register Address: 61BH, 1563

MSR_DRAM_PERF_STATUS

DRAM Performance Throttling Status (R/O)

Package

See Section 17.10.5, “DRAM RAPL Domain.”

Register Address: 61CH, 1564

MSR_DRAM_POWER_INFO

DRAM RAPL Parameters (R/W)

Package

See Section 17.10.5, “DRAM RAPL Domain.”

Register Address: 639H, 1593

MSR_PP0_ENERGY_STATUS

PP0 Energy Status (R/O)

Package

See Section 17.10.4, “PP0/PP1 RAPL Domains.”

See Table 2-20, Table 2-23, and Table 2-24 for MSR definitions applicable to processors with a CPUID Signature

DisplayFamily_DisplayModel value of 06_2DH.

2.11.3 Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 Family

Intel Xeon Processor E5 family is based on the Sandy Bridge microarchitecture. The MSR-based uncore PMU inter-

faces are listed in Table 2-24. For complete details of the uncore PMU, refer to the Intel Xeon Processor E5 Product

Family Uncore Performance Monitoring Guide. These processors have a CPUID Signature

DisplayFamily_DisplayModel value of 06_2DH.

Table 2-24. Uncore PMU MSRs in Intel® Xeon® Processor E5 Family

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Register Address: C08H, 3080

MSR_U_PMON_UCLK_FIXED_CTL

Uncore U-box UCLK Fixed Counter Control

Package

Register Address: C09H, 3081

MSR_U_PMON_UCLK_FIXED_CTR

2-258 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-24. Uncore PMU MSRs in Intel® Xeon® Processor E5 Family (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Register Address: DF8H, 3576

MSR_C7_PMON_CTR2

Uncore C-box 7 PerfMon Counter 2

Package

Register Address: DF9H, 3577

MSR_C7_PMON_CTR3

Uncore C-box 7 PerfMon Counter 3

Package

2.12

MSRS IN THE 3RD GENERATION INTEL® CORE™ PROCESSOR FAMILY BASED

ON IVY BRIDGE MICROARCHITECTURE

The 3rd generation Intel^® Core™ processor family and the Intel^® Xeon^® processor E3-1200v2 product family

based on Ivy Bridge microarchitecture support the MSR interfaces listed in Table 2-20, Table 2-21, Table 2-22, and

Table 2-25. These processors have a CPUID Signature DisplayFamily_DisplayModel value of 06_3AH.

Table 2-25. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors Based on Ivy Bridge

Microarchitecture

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Register Address: CEH, 206

MSR_PLATFORM_INFO

Platform Information

Package

Contains power management and other model specific features enumeration. See http://biosbits.org.

7:0

Reserved.

15:8

Maximum Non-Turbo Ratio (R/O)

Package

This is the ratio of the frequency that invariant TSC runs at. Frequency =

ratio * 100 MHz.

27:16

Reserved.

28

Programmable Ratio Limit for Turbo Mode (R/O)

Package

When set to 1, indicates that Programmable Ratio Limit for Turbo mode is

enabled. When set to 0, indicates Programmable Ratio Limit for Turbo

mode is disabled.

29

Programmable TDP Limit for Turbo Mode (R/O)

Package

When set to 1, indicates that TDP Limit for Turbo mode is programmable.

When set to 0, indicates that TDP Limit for Turbo mode is not

programmable.

31:30

Reserved.

32

Low Power Mode Support (LPM) (R/O)

Package

When set to 1, indicates that LPM is supported. When set to 0, indicates

LPM is not supported.

34:33

Number of ConfigTDP Levels (R/O)

Package

00: Only Base TDP level available.

01: One additional TDP level available.

02: Two additional TDP level available.

03: Reserved

39:35

Reserved.

2-264 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-25. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors Based on Ivy Bridge

Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

47:40

Maximum Efficiency Ratio (R/O)

Package

This is the minimum ratio (maximum efficiency) that the processor can

operate, in units of 100MHz.

55:48

Minimum Operating Ratio (R/O)

Package

Contains the minimum supported operating ratio in units of 100 MHz.

63:56

Reserved.

Register Address: E2H, 226

MSR_PKG_CST_CONFIG_CONTROL

C-State Configuration Control (R/W)

Core

Note: C-state values are processor specific C-state code names, unrelated

to MWAIT extension C-state parameters or ACPI C-States.

See http://biosbits.org.

2:0

Package C-State Limit (R/W)

Specifies the lowest processor-specific C-state code name (consuming the

least power) for the package. The default is set as factory-configured

package C-state limit.

The following C-state code name encodings are supported:

000b: C0/C1 (no package C-sate support)

001b: C2

010b: C6 no retention

011b: C6 retention

100b: C7

101b: C7s

111: No package C-state limit.

Note: This field cannot be used to limit package C-state to C3.

9:3

Reserved.

10

I/O MWAIT Redirection Enable (R/W)

When set, will map IO_read instructions sent to IO register specified by

MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.

14:11

Reserved.

15

CFG Lock (R/WO)

When set, locks bits 15:0 of this register until next reset.

24:16

Reserved

25

C3 State Auto Demotion Enable (R/W)

When set, the processor will conditionally demote C6/C7 requests to C3

based on uncore auto-demote information.

26

C1 State Auto Demotion Enable (R/W)

When set, the processor will conditionally demote C3/C6/C7 requests to

C1 based on uncore auto-demote information.

27

Enable C3 Undemotion (R/W)

When set, enables undemotion from demoted C3.

Vol. 4

2-265

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-25. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors Based on Ivy Bridge

Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

28

Enable C1 Undemotion (R/W)

When set, enables undemotion from demoted C1.

63:29

Reserved.

Register Address: 639H, 1593

MSR_PP0_ENERGY_STATUS

PP0 Energy Status (R/O)

Package

See Section 17.10.4, “PP0/PP1 RAPL Domains.”

Register Address: 648H, 1608

MSR_CONFIG_TDP_NOMINAL

Base TDP Ratio (R/O)

Package

7:0

Config_TDP_Base

Base TDP level ratio to be used for this specific processor (in units of 100

MHz).

63:8

Reserved.

Register Address: 649H, 1609

MSR_CONFIG_TDP_LEVEL1

ConfigTDP Level 1 ratio and power level (R/O)

Package

14:0

PKG_TDP_LVL1

Power setting for ConfigTDP Level 1.

15

Reserved.

23:16

Config_TDP_LVL1_Ratio

ConfigTDP level 1 ratio to be used for this specific processor.

31:24

Reserved.

46:32

PKG_MAX_PWR_LVL1

Max Power setting allowed for ConfigTDP Level 1.

47

Reserved.

62:48

PKG_MIN_PWR_LVL1

MIN Power setting allowed for ConfigTDP Level 1.

63

Reserved.

Register Address: 64AH, 1610

MSR_CONFIG_TDP_LEVEL2

ConfigTDP Level 2 ratio and power level (R/O)

Package

14:0

PKG_TDP_LVL2

Power setting for ConfigTDP Level 2.

15

Reserved.

23:16

Config_TDP_LVL2_Ratio

ConfigTDP level 2 ratio to be used for this specific processor.

31:24

Reserved.

46:32

PKG_MAX_PWR_LVL2

Max Power setting allowed for ConfigTDP Level 2.

47

Reserved.

2-266 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-25. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors Based on Ivy Bridge

Microarchitecture (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

62:48

PKG_MIN_PWR_LVL2

MIN Power setting allowed for ConfigTDP Level 2.

63

Reserved.

Register Address: 64BH, 1611

MSR_CONFIG_TDP_CONTROL

ConfigTDP Control (R/W)

Package

1:0

TDP_LEVEL (RW/L)

System BIOS can program this field.

30:2

Reserved.

31

Config_TDP_Lock (RW/L)

When this bit is set, the content of this register is locked until a reset.

63:32

Reserved.

Register Address: 64CH, 1612

MSR_TURBO_ACTIVATION_RATIO

ConfigTDP Control (R/W)

Package

7:0

MAX_NON_TURBO_RATIO (RW/L)

System BIOS can program this field.

30:8

Reserved.

31

TURBO_ACTIVATION_RATIO_Lock (RW/L)

When this bit is set, the content of this register is locked until a reset.

63:32

Reserved.

See Table 2-20, Table 2-21, and Table 2-22 for other MSR definitions applicable to processors with a CPUID Signature

DisplayFamily_DisplayModel value of 06_3AH.

2.12.1 MSRs in the Intel® Xeon® Processor E5 v2 Product Family Based on Ivy Bridge-E

Microarchitecture

Table 2-26 lists model-specific registers (MSRs) that are specific to the Intel^® Xeon^® Processor E5 v2 Product

Family (based on Ivy Bridge-E microarchitecture). These processors have a CPUID Signature

DisplayFamily_DisplayModel value of 06_3EH; see Table 2-1. These processors supports the MSR interfaces listed

in Table 2-20 and Table 2-26.

Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Register Address: 4EH, 78

IA32_PPIN_CTL (MSR_PPIN_CTL)

Protected Processor Inventory Number Enable Control (R/W)

Package

0

LockOut (R/WO)

See Table 2-2.

1

Enable_PPIN (R/W)

See Table 2-2.

63:2

Reserved.

Vol. 4

2-267

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Register Address: 4FH, 79

IA32_PPIN (MSR_PPIN)

Protected Processor Inventory Number (R/O)

Package

63:0

Protected Processor Inventory Number (R/O)

See Table 2-2.

Register Address: CEH, 206

MSR_PLATFORM_INFO

Platform Information

Package

Contains power management and other model specific features enumeration. See http://biosbits.org.

7:0

Reserved.

15:8

Maximum Non-Turbo Ratio (R/O)

Package

This is the ratio of the frequency that invariant TSC runs at. Frequency =

ratio * 100 MHz.

22:16

Reserved.

23

PPIN_CAP (R/O)

Package

When set to 1, indicates that Protected Processor Inventory Number (PPIN)

capability can be enabled for a privileged system inventory agent to read

PPIN from MSR_PPIN.

When set to 0, PPIN capability is not supported. An attempt to access

MSR_PPIN_CTL or MSR_PPIN will cause #GP.

27:24

Reserved.

28

Programmable Ratio Limit for Turbo Mode (R/O)

Package

When set to 1, indicates that Programmable Ratio Limit for Turbo mode is

enabled. When set to 0, indicates Programmable Ratio Limit for Turbo mode

is disabled.

29

Programmable TDP Limit for Turbo Mode (R/O)

Package

When set to 1, indicates that TDP Limit for Turbo mode is programmable.

When set to 0, indicates TDP Limit for Turbo mode is not programmable.

30

Programmable TJ OFFSET (R/O)

Package

When set to 1, indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid

and writable to specify a temperature offset.

39:31

Reserved.

47:40

Maximum Efficiency Ratio (R/O)

Package

This is the minimum ratio (maximum efficiency) that the processor can

operate, in units of 100MHz.

63:48

Reserved.

Register Address: E2H, 226

MSR_PKG_CST_CONFIG_CONTROL

C-State Configuration Control (R/W)

Core

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

ACPI C-states. See http://biosbits.org.

2-268 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

2:0

Package C-State Limit (R/W)

Specifies the lowest processor-specific C-state code name (consuming the

least power) for the package. The default is set as factory-configured

package C-state limit.

The following C-state code name encodings are supported:

000b: C0/C1 (no package C-sate support)

001b: C2

010b: C6 no retention

011b: C6 retention

100b: C7

101b: C7s

111: No package C-state limit.

Note: This field cannot be used to limit package C-state to C3.

9:3

Reserved.

10

I/O MWAIT Redirection Enable (R/W)

When set, will map IO_read instructions sent to IO register specified by

MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.

14:11

Reserved.

15

CFG Lock (R/WO)

When set, locks bits 15:0 of this register until next reset.

63:16

Reserved.

Register Address: 179H, 377

IA32_MCG_CAP

Global Machine Check Capability (R/O)

Thread

7:0

Count

8

MCG_CTL_P

9

MCG_EXT_P

10

MCP_CMCI_P

11

MCG_TES_P

15:12

Reserved.

23:16

MCG_EXT_CNT

24

MCG_SER_P

25

Reserved.

26

MCG_ELOG_P

63:27

Reserved.

Register Address: 17FH, 383

MSR_ERROR_CONTROL

MC Bank Error Configuration (R/W)

Package

0

Reserved.

1

MemError Log Enable (R/W)

When set, enables IMC status bank to log additional info in bits 36:32.

63:2

Reserved.

Vol. 4

2-269

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Register Address: 1A2H, 418

MSR_TEMPERATURE_TARGET

Temperature Target

Package

15:0

Reserved.

23:16

Temperature Target (R/O)

The minimum temperature at which PROCHOT# will be asserted. The value

is degrees C.

27:24

TCC Activation Offset (R/W)

Specifies a temperature offset in degrees C from the temperature target

(bits 23:16). PROCHOT# will assert at the offset target temperature. Write

is permitted only if MSR_PLATFORM_INFO.[30] is set.

63:28

Reserved.

Register Address: 1AEH, 430

MSR_TURBO_RATIO_LIMIT1

Maximum Ratio Limit of Turbo Mode

Package

R/O if MSR_PLATFORM_INFO.[28] = 0. R/W if MSR_PLATFORM_INFO.[28] = 1.

7:0

Maximum Ratio Limit for 9C

Package

Maximum turbo ratio limit of 9 core active.

15:8

Maximum Ratio Limit for 10C

Package

Maximum turbo ratio limit of 10 core active.

23:16

Maximum Ratio Limit for 11C

Package

Maximum turbo ratio limit of 11 core active.

31:24

Maximum Ratio Limit for 12C

Package

Maximum turbo ratio limit of 12 core active.

63:32

Reserved.

Register Address: 285H, 645

IA32_MC5_CTL2

See Table 2-2.

Package

Register Address: 286H, 646

IA32_MC6_CTL2

See Table 2-2.

Package

Register Address: 287H, 647

IA32_MC7_CTL2

See Table 2-2.

Package

Register Address: 288H, 648

IA32_MC8_CTL2

See Table 2-2.

Package

Register Address: 289H, 649

IA32_MC9_CTL2

See Table 2-2.

Package

Register Address: 28AH, 650

IA32_MC10_CTL2

See Table 2-2.

Package

Register Address: 28BH, 651

IA32_MC11_CTL2

See Table 2-2.

Package

Register Address: 28CH, 652

IA32_MC12_CTL2

See Table 2-2.

Package

2-270 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Register Address: 471H, 1137

IA32_MC28_STATUS

See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC28 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

Register Address: 472H, 1138

IA32_MC28_ADDR

See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC28 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

Register Address: 473H, 1139

IA32_MC28_MISC

See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC28 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

Register Address: 613H, 1555

MSR_PKG_PERF_STATUS

Package RAPL Perf Status (R/O)

Package

Register Address: 618H, 1560

MSR_DRAM_POWER_LIMIT

DRAM RAPL Power Limit Control (R/W)

Package

See Section 17.10.5, “DRAM RAPL Domain.”

Register Address: 619H, 1561

MSR_DRAM_ENERGY_STATUS

DRAM Energy Status (R/O)

Package

See Section 17.10.5, “DRAM RAPL Domain.”

Register Address: 61BH, 1563

MSR_DRAM_PERF_STATUS

DRAM Performance Throttling Status (R/O)

Package

See Section 17.10.5, “DRAM RAPL Domain.”

Register Address: 61CH, 1564

MSR_DRAM_POWER_INFO

DRAM RAPL Parameters (R/W)

Package

See Section 17.10.5, “DRAM RAPL Domain.”

Register Address: 639H, 1593

MSR_PP0_ENERGY_STATUS

PP0 Energy Status (R/O)

Package

See Section 17.10.4, “PP0/PP1 RAPL Domains.”

See Table 2-20, for other MSR definitions applicable to Intel Xeon processor E5 v2 with a CPUID Signature

DisplayFamily_DisplayModel value of 06_3EH.

2.12.2 Additional MSRs Supported by the Intel® Xeon® Processor E7 v2 Family

The Intel^® Xeon^® processor E7 v2 family (based on Ivy Bridge-E microarchitecture) with a CPUID Signature

DisplayFamily_DisplayModel value of 06_3EH supports the MSR interfaces listed in Table 2-20, Table 2-26, and

Table 2-27.

Table 2-27. Additional MSRs Supported by the Intel® Xeon® Processor E7 v2 Family with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_3EH

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Register Address: 3AH, 58

IA32_FEATURE_CONTROL

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-27. Additional MSRs Supported by the Intel® Xeon® Processor E7 v2 Family with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_3EH (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Control Features in Intel 64 Processor (R/W)

Thread

See Table 2-2.

0

Lock (R/WL)

1

Enable VMX Inside SMX Operation (R/WL)

2

Enable VMX Outside SMX Operation (R/WL)

14:8

SENTER Local Functions Enables (R/WL)

15

SENTER Global Functions Enable (R/WL)

63:16

Reserved.

Register Address: 179H, 377

IA32_MCG_CAP

Global Machine Check Capability (R/O)

Thread

7:0

Count

8

MCG_CTL_P

9

MCG_EXT_P

10

MCP_CMCI_P

11

MCG_TES_P

15:12

Reserved.

23:16

MCG_EXT_CNT

24

MCG_SER_P

63:25

Reserved.

Register Address: 17AH, 378

IA32_MCG_STATUS

Global Machine Check Status (R/W)

Thread

0

RIPV

1

EIPV

2

MCIP

3

LMCE Signaled

63:4

Reserved.

Register Address: 1AEH, 430

MSR_TURBO_RATIO_LIMIT1

Maximum Ratio Limit of Turbo Mode

Package

R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1.

7:0

Maximum Ratio Limit for 9C

Package

Maximum turbo ratio limit of 9 core active.

15:8

Maximum Ratio Limit for 10C

Package

Maximum turbo ratio limit of 10core active.

23:16

Maximum Ratio Limit for 11C

Package

Maximum turbo ratio limit of 11 core active.

31:24

Maximum Ratio Limit for 12C

Package

Maximum turbo ratio limit of 12 core active.

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-27. Additional MSRs Supported by the Intel® Xeon® Processor E7 v2 Family with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_3EH (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

39:32

Maximum Ratio Limit for 13C

Package

Maximum turbo ratio limit of 13 core active.

47:40

Maximum Ratio Limit for 14C

Package

Maximum turbo ratio limit of 14 core active.

55:48

Maximum Ratio Limit for 15C

Package

Maximum turbo ratio limit of 15 core active.

62:56

Reserved.

63

Semaphore for Turbo Ratio Limit Configuration

Package

If 1, the processor uses override configuration¹ specified in

MSR_TURBO_RATIO_LIMIT and MSR_TURBO_RATIO_LIMIT1.

If 0, the processor uses factory-set configuration (Default).

Register Address: 29DH, 669

IA32_MC29_CTL2

See Table 2-2.

Package

Register Address: 29EH, 670

IA32_MC30_CTL2

See Table 2-2.

Package

Register Address: 29FH, 671

IA32_MC31_CTL2

See Table 2-2.

Package

Register Address: 3F1H, 1009

IA32_PEBS_ENABLE (MSR_PEBS_ENABLE)

See Section 22.3.1.1.1, “Processor Event Based Sampling (PEBS).”

Thread

n:0

Enable PEBS on IA32_PMCx. (R/W)

31:n+1

Reserved.

32+m:32

Enable Load Latency on IA32_PMCx. (R/W)

63:33+m

Reserved.

Register Address: 41BH, 1051

IA32_MC6_MISC

Misc MAC Information of Integrated I/O (R/O)

Package

See Section 18.3.2.4.

5:0

Recoverable Address LSB

8:6

Address Mode

15:9

Reserved.

31:16

PCI Express Requestor ID

39:32

PCI Express Segment Number

63:32

Reserved.

Register Address: 474H, 1140

IA32_MC29_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC29 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

Register Address: 475H, 1141

IA32_MC29_STATUS

See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC29 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

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2-281

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-27. Additional MSRs Supported by the Intel® Xeon® Processor E7 v2 Family with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_3EH (Contd.)

Register Address: Hex, Decimal

Register Name (Former Register Name)

Register Information / Bit Fields

Bit Description

Scope

Register Address: 476H, 1142

IA32_MC29_ADDR

See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC29 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

Register Address: 477H, 1143

IA32_MC29_MISC

See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC29 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

Register Address: 478H, 1144

IA32_MC30_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC30 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

Register Address: 479H, 1145

IA32_MC30_STATUS

See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC30 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

Register Address: 47AH, 1146

IA32_MC30_ADDR

See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC30 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

Register Address: 47BH, 1147

IA32_MC30_MISC

See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC30 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

Register Address: 47CH, 1148

IA32_MC31_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC31 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

Register Address: 47DH, 1149

IA32_MC31_STATUS

See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC31 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

Register Address: 47EH, 1150

IA32_MC31_ADDR

See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC31 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

Register Address: 47FH, 1147

IA32_MC31_MISC

See Section 18.3.2.1, “IA32_MCi_CTL MSRs,” through Section 18.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC31 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

See Table 2-20, Table 2-26 for other MSR definitions applicable to Intel Xeon processor E7 v2 with a CPUID Signature

DisplayFamily_DisplayModel value of 06_3AH.

NOTES:

1. An override configuration lower than the factory-set configuration is always supported. An override configuration higher than the

factory-set configuration is dependent on features specific to the processor and the platform.

2.12.3 Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families

Intel Xeon Processor E5 v2 and E7 v2 families are based on the Ivy Bridge-E microarchitecture. The MSR-based

uncore PMU interfaces are listed in Table 2-24 and Table 2-28. For complete detail of the uncore PMU, refer to Intel

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