Intel 64 and IA-32 Architectures. Software Developer’s Manual (2026)

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-61. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)

Bit Description

Scope

MSR_PKG_CST_CONFIG_CONTROL

C-State Configuration Control (R/W)

Package

2:0

Package C-State Limit (R/W)

Specifies the lowest C-state for the package. This feature does not limit

the processor core C-state. The power-on default value from bit[2:0] of

this register reports the deepest package C-state the processor is

capable to support when manufactured. It is recommended that BIOS

always read the power-on default value reported from this bit field to

determine the supported deepest C-state on the processor and leave it

as default without changing it.

000b - C0/C1 (No package C-state support)

001b - C2

010b - C6 (non retention)*

011b - C6 (Retention)*

100b - Reserved

101b - Reserved

110b - Reserved

111b - No package C-state limit. All C-States supported by the

processor are available.

Note: C6 retention mode provides more power saving than C6 non-

retention mode. Limiting the package to C6 non retention mode does

prevent the MSR_PKG_C6_RESIDENCY counter (MSR 3F9h) from being

incremented.

9:3

Reserved.

I/O MWAIT Redirection Enable (R/W)

When set, will map IO_read instructions sent to IO registers at

MSR_PMG_IO_CAPTURE_BASE[15:0] to MWAIT instructions.

14:11

Reserved.

CFG Lock (R/O)

When set, locks bits [15:0] of this register for further writes until the

next reset occurs.

Reserved.

C1 State Auto Demotion Enable (R/W)

When set, the processor will conditionally demote C3/C6/C7 requests

to C1 based on uncore auto-demote information.

Reserved.

C1 State Auto Undemotion Enable (R/W)

When set, enables Undemotion from Demoted C1.

PKG C-State Auto Demotion Enable (R/W)

When set, enables Package C state demotion.

63:30

Reserved.

MSR_PMG_IO_CAPTURE_BASE

Power Management IO Capture Base (R/W)

Tile

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-61. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)

Bit Description

Scope

15:0

LVL_2 Base Address (R/W)

Microcode will compare IO-read zone to this base address to determine

if an MWAIT(C2/3/4) needs to be issued instead of the IO-read. Should

be programmed to the chipset Plevel_2 IO address.

22:16

C-State Range (R/W)

The IO-port block size in which IO-redirection will be executed (0-127).

Should be programmed based on the number of LVLx registers existing

in the chipset.

63:23

Reserved.

IA32_MPERF

Maximum Performance Frequency Clock Count (R/W)

Thread

See Table 2-2.

IA32_APERF

Actual Performance Frequency Clock Count (R/W)

Thread

See Table 2-2.

IA32_MTRRCAP

Memory Type Range Register (R/O)

Core

See Table 2-2.

MSR_FEATURE_CONFIG

AES Configuration (RW-L)

Core

Privileged post-BIOS agent must provide a #GP handler to handle unsuccessful read of this MSR.

1:0

AES Configuration (RW-L)

Upon a successful read of this MSR, the configuration of AES

instruction set availability is as follows:

11b: AES instructions are not available until next RESET.

Otherwise, AES instructions are available.

Note, the AES instruction set is not available if read is unsuccessful. If

the configuration is not 01b, AES instructions can be mis-configured if a

privileged agent unintentionally writes 11b.

63:2

Reserved.

MISC_FEATURE_ENABLES

Thread

Reserved.

User Mode MONITOR and MWAIT (R/W)

If set to 1, the MONITOR and MWAIT instructions do not cause invalid-

opcode exceptions when executed with CPL > 0 or in virtual-8086

mode. If MWAIT is executed when CPL > 0 or in virtual-8086 mode, and

if EAX indicates a C-state other than C0 or C1, the instruction operates

as if EAX indicated the C-state C1.

63:2

Reserved.

IA32_SYSENTER_CS

See Table 2-2.

Thread

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2-511

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-61. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)

Bit Description

Scope

IA32_SYSENTER_ESP

See Table 2-2.

Thread

IA32_SYSENTER_EIP

See Table 2-2.

Thread

IA32_MCG_CAP

See Table 2-2.

Thread

IA32_MCG_STATUS

See Table 2-2.

Thread

MSR_SMM_MCA_CAP

Enhanced SMM Capabilities (SMM-RO)

Thread

Reports SMM capability Enhancement. Accessible only while in SMM.

31:0

Bank Support (SMM-RO)

One bit per MCA bank. If the bit is set, that bank supports Enhanced

MCA (Default all 0; does not support EMCA).

55:32

Reserved.

Targeted SMI (SMM-RO)

Set if targeted SMI is supported.

SMM_CPU_SVRSTR (SMM-RO)

Set if SMM SRAM save/restore feature is supported.

SMM_CODE_ACCESS_CHK (SMM-RO)

Set if SMM code access check feature is supported.

Long_Flow_Indication (SMM-RO)

If set to 1, indicates that the SMM long flow indicator is supported and a

host-space interface available to SMM handler.

63:60

Reserved.

IA32_PERFEVTSEL0

Performance Monitoring Event Select Register (R/W)

Thread

See Table 2-2.

7:0

Event Select.

15:8

UMask.

USR.

OS.

Edge.

PC.

INT.

AnyThread.

EN.

INV.

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-61. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)

Bit Description

Scope

31:24

CMASK.

63:32

Reserved.

IA32_PERFEVTSEL1

See Table 2-2.

Thread

IA32_PERF_STATUS

See Table 2-2.

Package

IA32_PERF_CTL

See Table 2-2.

Thread

IA32_CLOCK_MODULATION

Clock Modulation (R/W)

Thread

See Table 2-2.

IA32_THERM_INTERRUPT

Thermal Interrupt Control (R/W)

Module

See Table 2-2.

IA32_THERM_STATUS

Thermal Monitor Status (R/W)

Module

See Table 2-2.

Thermal Status (R/O)

Thermal Status Log (R/WC0)

PROTCHOT # or FORCEPR# Status (R/O)

PROTCHOT # or FORCEPR# Log (R/WC0)

Critical Temperature Status (R/O)

Critical Temperature Status Log (R/WC0)

Thermal Threshold #1 Status (R/O)

Thermal Threshold #1 Log (R/WC0)

Thermal Threshold #2 Status (R/O)

Thermal Threshold #2 Log (R/WC0)

Power Limitation Status (R/O)

Power Limitation Log (RWC0)

15:12

Reserved.

22:16

Digital Readout (R/O)

26:23

Reserved.

30:27

Resolution in Degrees Celsius (R/O)

Reading Valid (R/O)

63:32

Reserved.

IA32_MISC_ENABLE

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-61. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)

Bit Description

Scope

Enable Misc. Processor Features (R/W)

Thread

Allows a variety of processor functions to be enabled and disabled.

Fast-Strings Enable

2:1

Reserved.

Automatic Thermal Control Circuit Enable (R/W)

6:4

Reserved.

Performance Monitoring Available (R)

10:8

Reserved.

Branch Trace Storage Unavailable (R/O)

Processor Event Based Sampling Unavailable (R/O)

15:13

Reserved.

Enhanced Intel SpeedStep Technology Enable (R/W)

ENABLE MONITOR FSM (R/W)

21:19

Reserved.

Limit CPUID Maxval (R/W)

xTPR Message Disable (R/W)

33:24

Reserved.

XD Bit Disable (R/W)

See Table 2-3.

37:35

Reserved.

Turbo Mode Disable (R/W)

63:39

Reserved.

MSR_TEMPERATURE_TARGET

Temperature Target

Package

15:0

Reserved.

23:16

Temperature Target (R)

29:24

Target Offset (R/W)

63:30

Reserved.

MSR_MISC_FEATURE_CONTROL

Miscellaneous Feature Control (R/W)

DCU Hardware Prefetcher Disable (R/W)

Core

If 1, disables the L1 data cache prefetcher.

L2 Hardware Prefetcher Disable (R/W)

Core

If 1, disables the L2 hardware prefetcher.

63:2

Reserved.

MSR_OFFCORE_RSP_0

Offcore Response Event Select Register (R/W)

Shared

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-61. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)

Bit Description

Scope

MSR_OFFCORE_RSP_1

Offcore Response Event Select Register (R/W)

Shared

MSR_TURBO_RATIO_LIMIT

Maximum Ratio Limit of Turbo Mode for Groups of Cores (R/W)

Package

Reserved.

7:1

Maximum Number of Cores in Group 0

Package

Number active processor cores which operates under the maximum

ratio limit for group 0.

15:8

Maximum Ratio Limit for Group 0

Package

Maximum turbo ratio limit when the number of active cores are not

more than the group 0 maximum core count.

20:16

Number of Incremental Cores Added to Group 1

Package

Group 1, which includes the specified number of additional cores plus

the cores in group 0, operates under the group 1 turbo max ratio limit =

“group 0 Max ratio limit” - “group ratio delta for group 1”.

23:21

Group Ratio Delta for Group 1

Package

An unsigned integer specifying the ratio decrement relative to the Max

ratio limit to Group 0.

28:24

Number of Incremental Cores Added to Group 2

Package

Group 2, which includes the specified number of additional cores plus all

the cores in group 1, operates under the group 2 turbo max ratio limit =

“group 1 Max ratio limit” - “group ratio delta for group 2”.

31:29

Group Ratio Delta for Group 2

Package

An unsigned integer specifying the ratio decrement relative to the Max

ratio limit for Group 1.

36:32

Number of Incremental Cores Added to Group 3

Package

Group 3, which includes the specified number of additional cores plus all

the cores in group 2, operates under the group 3 turbo max ratio limit =

“group 2 Max ratio limit” - “group ratio delta for group 3”.

39:37

Group Ratio Delta for Group 3

Package

An unsigned integer specifying the ratio decrement relative to the Max

ratio limit for Group 2.

44:40

Number of Incremental Cores Added to Group 4

Package

Group 4, which includes the specified number of additional cores plus all

the cores in group 3, operates under the group 4 turbo max ratio limit =

“group 3 Max ratio limit” - “group ratio delta for group 4”.

47:45

Group Ratio Delta for Group 4

Package

An unsigned integer specifying the ratio decrement relative to the Max

ratio limit for Group 3.

52:48

Number of Incremental Cores Added to Group 5

Package

Group 5, which includes the specified number of additional cores plus all

the cores in group 4, operates under the group 5 turbo max ratio limit =

“group 4 Max ratio limit” - “group ratio delta for group 5”.

Vol. 4

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-61. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)

Bit Description

Scope

55:53

Group Ratio Delta for Group 5

Package

An unsigned integer specifying the ratio decrement relative to the Max

ratio limit for Group 4.

60:56

Number of Incremental Cores Added to Group 6

Package

Group 6, which includes the specified number of additional cores plus all

the cores in group 5, operates under the group 6 turbo max ratio limit =

“group 5 Max ratio limit” - “group ratio delta for group 6”.

63:61

Group Ratio Delta for Group 6

Package

An unsigned integer specifying the ratio decrement relative to the Max

ratio limit for Group 5.

IA32_ENERGY_PERF_BIAS

See Table 2-2.

Thread

IA32_PACKAGE_THERM_STATUS

See Table 2-2.

Package

IA32_PACKAGE_THERM_INTERRUPT

See Table 2-2.

Package

MSR_LBR_SELECT

Last Branch Record Filtering Select Register (R/W)

Thread

See Section 20.9.2, “Filtering of Last Branch Records.”

CPL_EQ_0

CPL_NEQ_0

JCC

NEAR_REL_CALL

NEAR_IND_CALL

NEAR_RET

NEAR_IND_JMP

NEAR_REL_JMP

FAR_BRANCH

63:9

Reserved.

MSR_LASTBRANCH_TOS

Last Branch Record Stack TOS (R/W)

Thread

Contains an index (bits 0-2) that points to the MSR containing the most recent branch record.

See MSR_LASTBRANCH_0_FROM_IP.

IA32_DEBUGCTL

Debug Control (R/W)

Thread

LBR

Setting this bit to 1 enables the processor to record a running trace of

the most recent branches taken by the processor in the LBR stack.

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-61. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)

Bit Description

Scope

BTF

Setting this bit to 1 enables the processor to treat EFLAGS.TF as single-

step on branches instead of single-step on instructions.

5:2

Reserved.

Setting this bit to 1 enables branch trace messages to be sent.

BTS

Setting this bit enables branch trace messages (BTMs) to be logged in a

BTS buffer.

BTINT

When clear, BTMs are logged in a BTS buffer in circular fashion. When

this bit is set, an interrupt is generated by the BTS facility when the

BTS buffer is full.

BTS_OFF_OS

When set, BTS or BTM is skipped if CPL = 0.

BTS_OFF_USR

When set, BTS or BTM is skipped if CPL > 0.

FREEZE_LBRS_ON_PMI

When set, the LBR stack is frozen on a PMI request.

FREEZE_PERFMON_ON_PMI

When set, each ENABLE bit of the global counter control MSR are frozen

(address 3BFH) on a PMI request.

Reserved.

FREEZE_WHILE_SMM

When set, freezes PerfMon and trace messages while in SMM.

31:15

Reserved.

MSR_LER_FROM_LIP

Last Exception Record from Linear IP (R)

Thread

MSR_LER_TO_LIP

Last Exception Record to Linear IP (R)

Thread

IA32_SMRR_PHYSBASE

See Table 2-2.

Core

IA32_SMRR_PHYSMASK

See Table 2-2.

Core

IA32_MTRR_PHYSBASE0

See Table 2-2.

Core

IA32_MTRR_PHYSMASK0

See Table 2-2.

Core

IA32_MTRR_PHYSBASE1

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-61. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)

Bit Description

Scope

See Table 2-2.

Core

IA32_MTRR_PHYSMASK1

See Table 2-2.

Core

IA32_MTRR_PHYSBASE2

See Table 2-2.

Core

IA32_MTRR_PHYSMASK2

See Table 2-2.

Core

IA32_MTRR_PHYSBASE3

See Table 2-2.

Core

IA32_MTRR_PHYSMASK3

See Table 2-2.

Core

IA32_MTRR_PHYSBASE4

See Table 2-2.

Core

IA32_MTRR_PHYSMASK4

See Table 2-2.

Core

IA32_MTRR_PHYSBASE5

See Table 2-2.

Core

IA32_MTRR_PHYSMASK5

See Table 2-2.

Core

IA32_MTRR_PHYSBASE6

See Table 2-2.

Core

IA32_MTRR_PHYSMASK6

See Table 2-2.

Core

IA32_MTRR_PHYSBASE7

See Table 2-2.

Core

IA32_MTRR_PHYSMASK7

See Table 2-2.

Core

IA32_MTRR_FIX64K_00000

See Table 2-2.

Core

IA32_MTRR_FIX16K_80000

See Table 2-2.

Core

IA32_MTRR_FIX16K_A0000

See Table 2-2.

Core

IA32_MTRR_FIX4K_C0000

See Table 2-2.

Core

IA32_MTRR_FIX4K_C8000

See Table 2-2.

Core

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-61. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)

Bit Description

Scope

IA32_MTRR_FIX4K_D0000

See Table 2-2.

Core

IA32_MTRR_FIX4K_D8000

See Table 2-2.

Core

IA32_MTRR_FIX4K_E0000

See Table 2-2.

Core

IA32_MTRR_FIX4K_E8000

See Table 2-2.

Core

IA32_MTRR_FIX4K_F0000

See Table 2-2.

Core

IA32_MTRR_FIX4K_F8000

See Table 2-2.

Core

IA32_PAT

See Table 2-2.

Core

IA32_MTRR_DEF_TYPE

Default Memory Types (R/W)

Core

See Table 2-2.

IA32_FIXED_CTR0

Fixed-Function Performance Counter Register 0 (R/W)

Thread

See Table 2-2.

IA32_FIXED_CTR1

Fixed-Function Performance Counter Register 1 (R/W)

Thread

See Table 2-2.

IA32_FIXED_CTR2

Fixed-Function Performance Counter Register 2 (R/W)

Thread

See Table 2-2.

IA32_PERF_CAPABILITIES

See Table 2-2. See Section 20.4.1, “IA32_DEBUGCTL MSR.”

Package

IA32_FIXED_CTR_CTRL

Fixed-Function-Counter Control Register (R/W)

Thread

See Table 2-2.

IA32_PERF_GLOBAL_STATUS

See Table 2-2.

Thread

IA32_PERF_GLOBAL_CTRL

See Table 2-2.

Thread

IA32_PERF_GLOBAL_OVF_CTRL

See Table 2-2.

Thread

Vol. 4

2-519

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-61. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)

Bit Description

Scope

IA32_PEBS_ENABLE (MSR_PEBS_ENABLE)

See Table 2-2.

Thread

MSR_PKG_C3_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state

Package

parameters or ACPI C-states.

63:0

Package C3 Residency Counter (R/O)

MSR_PKG_C6_RESIDENCY

63:0

Package C6 Residency Counter (R/O)

Package

MSR_PKG_C7_RESIDENCY

63:0

Package C7 Residency Counter (R/O)

Package

MSR_MC0_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state

Module

parameters or ACPI C-states.

63:0

Module C0 Residency Counter (R/O)

MSR_MC6_RESIDENCY

63:0

Module C6 Residency Counter (R/O)

Module

MSR_CORE_C6_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state

Core

parameters or ACPI C-states.

63:0

CORE C6 Residency Counter (R/O)

IA32_MC0_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Core

IA32_MC0_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

Core

IA32_MC0_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

Core

IA32_MC1_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Core

IA32_MC1_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

Core

IA32_MC2_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Core

IA32_MC2_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

Core

IA32_MC2_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

Core

IA32_MC3_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Core

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-61. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)

Bit Description

Scope

IA32_MC3_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

Core

IA32_MC3_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

Core

IA32_MC4_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Core

IA32_MC4_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

Core

IA32_MC4_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

Core

The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the

MSR_MC4_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-protection

exception.

IA32_MC5_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Package

IA32_MC5_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

Package

IA32_MC5_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

Package

IA32_A_PMC0

See Table 2-2.

Thread

IA32_A_PMC1

See Table 2-2.

Thread

IA32_DS_AREA

DS Save Area (R/W)

Thread

See Table 2-2.

MSR_RAPL_POWER_UNIT

Unit Multipliers Used in RAPL Interfaces (R/O)

Package

3:0

Power Units

Package

See Section 17.10.1, “RAPL Interfaces.”

7:4

Reserved.

Package

12:8

Energy Status Units

Package

Energy related information (in Joules) is based on the multiplier,

1/2^ESU; where ESU is an unsigned integer represented by bits 12:8.

Default value is 0EH (or 61 micro-joules).

15:13

Reserved.

Package

19:16

Time Units

Package

See Section 17.10.1, “RAPL Interfaces.”

Vol. 4

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-61. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)

Bit Description

Scope

63:20

Reserved.

MSR_PKG_C2_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state

Package

parameters or ACPI C-states.

63:0

Package C2 Residency Counter (R/O)

MSR_PKG_POWER_LIMIT

PKG RAPL Power Limit Control (R/W)

Package

See Section 17.10.3, “Package RAPL Domain.”

MSR_PKG_ENERGY_STATUS

PKG Energy Status (R/O)

Package

See Section 17.10.3, “Package RAPL Domain.”

MSR_PKG_PERF_STATUS

PKG Perf Status (R/O)

Package

See Section 17.10.3, “Package RAPL Domain.”

MSR_PKG_POWER_INFO

PKG RAPL Parameters (R/W)

Package

See Section 17.10.3, “Package RAPL Domain.”

MSR_DRAM_POWER_LIMIT

DRAM RAPL Power Limit Control (R/W)

Package

See Section 17.10.5, “DRAM RAPL Domain.”

MSR_DRAM_ENERGY_STATUS

DRAM Energy Status (R/O)

Package

See Section 17.10.5, “DRAM RAPL Domain.”

MSR_DRAM_PERF_STATUS

DRAM Performance Throttling Status (R/O)

Package

See Section 17.10.5, “DRAM RAPL Domain.”

MSR_DRAM_POWER_INFO

DRAM RAPL Parameters (R/W)

Package

See Section 17.10.5, “DRAM RAPL Domain.”

MSR_PP0_POWER_LIMIT

PP0 RAPL Power Limit Control (R/W)

Package

See Section 17.10.4, “PP0/PP1 RAPL Domains.”

MSR_PP0_ENERGY_STATUS

PP0 Energy Status (R/O)

Package

See Section 17.10.4, “PP0/PP1 RAPL Domains.”

MSR_CONFIG_TDP_NOMINAL

Base TDP Ratio (R/O)

Package

See Table 2-25.

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Table 2-61. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)

Bit Description

Scope

MSR_CONFIG_TDP_LEVEL1

ConfigTDP Level 1 ratio and power level (R/O)

Package

See Table 2-25.

MSR_CONFIG_TDP_LEVEL2

ConfigTDP Level 2 ratio and power level (R/O)

Package

See Table 2-25.

MSR_CONFIG_TDP_CONTROL

ConfigTDP Control (R/W)

Package

See Table 2-25.

MSR_TURBO_ACTIVATION_RATIO

ConfigTDP Control (R/W)

Package

See Table 2-25.

MSR_CORE_PERF_LIMIT_REASONS

Indicator of Frequency Clipping in Processor Cores (R/W)

Package

(Frequency refers to processor core frequency.)

PROCHOT Status (R0)

Thermal Status (R0)

5:2

Reserved.

VR Therm Alert Status (R0)

Reserved.

Electrical Design Point Status (R0)

63:9

Reserved.

IA32_TSC_DEADLINE

TSC Target of Local APIC’s TSC Deadline Mode (R/W)

Core

See Table 2-2.

IA32_X2APIC_APICID

x2APIC ID Register (R/O)

Thread

IA32_X2APIC_VERSION

x2APIC Version Register (R/O)

Thread

IA32_X2APIC_TPR

x2APIC Task Priority Register (R/W)

Thread

IA32_X2APIC_PPR

x2APIC Processor Priority Register (R/O)

Thread

IA32_X2APIC_EOI

x2APIC EOI Register (W/O)

Thread

IA32_X2APIC_LDR

x2APIC Logical Destination Register (R/O)

Thread

Vol. 4

2-523

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-61. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)

Bit Description

Scope

IA32_X2APIC_SIVR

x2APIC Spurious Interrupt Vector Register (R/W)

Thread

IA32_X2APIC_ISR0

x2APIC In-Service Register Bits [31:0] (R/O)

Thread

IA32_X2APIC_ISR1

x2APIC In-Service Register Bits [63:32] (R/O)

Thread

IA32_X2APIC_ISR2

x2APIC In-Service Register Bits [95:64] (R/O)

Thread

IA32_X2APIC_ISR3

x2APIC In-Service Register Bits [127:96] (R/O)

Thread

IA32_X2APIC_ISR4

x2APIC In-Service Register Bits [159:128] (R/O)

Thread

IA32_X2APIC_ISR5

x2APIC In-Service Register Bits [191:160] (R/O)

Thread

IA32_X2APIC_ISR6

x2APIC In-Service Register Bits [223:192] (R/O)

Thread

IA32_X2APIC_ISR7

x2APIC In-Service Register Bits [255:224] (R/O)

Thread

IA32_X2APIC_TMR0

x2APIC Trigger Mode Register Bits [31:0] (R/O)

Thread

IA32_X2APIC_TMR1

x2APIC Trigger Mode Register Bits [63:32] (R/O)

Thread

IA32_X2APIC_TMR2

x2APIC Trigger Mode Register Bits [95:64] (R/O)

Thread

IA32_X2APIC_TMR3

x2APIC Trigger Mode Register Bits [127:96] (R/O)

Thread

IA32_X2APIC_TMR4

x2APIC Trigger Mode Register Bits [159:128] (R/O)

Thread

IA32_X2APIC_TMR5

x2APIC Trigger Mode Register Bits [191:160] (R/O)

Thread

IA32_X2APIC_TMR6

x2APIC Trigger Mode Register Bits [223:192] (R/O)

Thread

IA32_X2APIC_TMR7

x2APIC Trigger Mode Register Bits [255:224] (R/O)

Thread

IA32_X2APIC_IRR0

x2APIC Interrupt Request Register Bits [31:0] (R/O)

Thread

IA32_X2APIC_IRR1

2-524 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-61. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)

Bit Description

Scope

x2APIC Interrupt Request Register Bits [63:32] (R/O)

Thread

IA32_X2APIC_IRR2

x2APIC Interrupt Request Register Bits [95:64] (R/O)

Thread

IA32_X2APIC_IRR3

x2APIC Interrupt Request Register Bits [127:96] (R/O)

Thread

IA32_X2APIC_IRR4

x2APIC Interrupt Request Register Bits [159:128] (R/O)

Thread

IA32_X2APIC_IRR5

x2APIC Interrupt Request Register Bits [191:160] (R/O)

Thread

IA32_X2APIC_IRR6

x2APIC Interrupt Request Register Bits [223:192] (R/O)

Thread

IA32_X2APIC_IRR7

x2APIC Interrupt Request Register Bits [255:224] (R/O)

Thread

IA32_X2APIC_ESR

x2APIC Error Status Register (R/W)

Thread

IA32_X2APIC_LVT_CMCI

x2APIC LVT Corrected Machine Check Interrupt Register (R/W)

Thread

IA32_X2APIC_ICR

x2APIC Interrupt Command Register (R/W)

Thread

IA32_X2APIC_LVT_TIMER

x2APIC LVT Timer Interrupt Register (R/W)

Thread

IA32_X2APIC_LVT_THERMAL

x2APIC LVT Thermal Sensor Interrupt Register (R/W)

Thread

IA32_X2APIC_LVT_PMI

x2APIC LVT Performance Monitor Register (R/W)

Thread

IA32_X2APIC_LVT_LINT0

x2APIC LVT LINT0 Register (R/W)

Thread

IA32_X2APIC_LVT_LINT1

x2APIC LVT LINT1 Register (R/W)

Thread

IA32_X2APIC_LVT_ERROR

x2APIC LVT Error Register (R/W)

Thread

IA32_X2APIC_INIT_COUNT

x2APIC Initial Count Register (R/W)

Thread

IA32_X2APIC_CUR_COUNT

x2APIC Current Count Register (R/O)

Thread

IA32_X2APIC_DIV_CONF

x2APIC Divide Configuration Register (R/W)

Thread

Vol. 4

2-525

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-61. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)

Bit Description

Scope

IA32_X2APIC_SELF_IPI

x2APIC Self IPI Register (W/O)

Thread

IA32_EFER

Extended Feature Enables

Thread

See Table 2-2.

IA32_STAR

System Call Target Address (R/W)

Thread

See Table 2-2.

IA32_LSTAR

IA-32e Mode System Call Target Address (R/W)

Thread

See Table 2-2.

IA32_FMASK

System Call Flag Mask (R/W)

Thread

See Table 2-2.

IA32_FS_BASE

Map of BASE Address of FS (R/W)

Thread

See Table 2-2.

IA32_GS_BASE

Map of BASE Address of GS (R/W)

Thread

See Table 2-2.

IA32_KERNEL_GS_BASE

Swap Target of BASE Address of GS (R/W)

Thread

See Table 2-2.

IA32_TSC_AUX

AUXILIARY TSC Signature (R/W)

Thread

See Table 2-2

Table 2-62 lists model-specific registers that are supported by the Intel^® Xeon Phi™ processor 7215, 7285, 7295

series based on the Knights Mill microarchitecture.

Table 2-62. Additional MSRs Supported by the Intel® Xeon Phi™ Processor 7215, 7285, 7295 Series

with a CPUID Signature DisplayFamily_DisplayModel Value of 06_85H

Bit Description

Scope

IA32_SMM_MONITOR_CTL

SMM Monitor Configuration (R/W)

Core

This MSR is readable only if VMX is enabled, and writeable only if VMX is enabled and in SMM mode, and is used to

configure the VMX MSEG base address. See Table 2-2.

IA32_VMX_BASIC

2-526 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-62. Additional MSRs Supported by the Intel® Xeon Phi™ Processor 7215, 7285, 7295 Series

with a CPUID Signature DisplayFamily_DisplayModel Value of 06_85H (Contd.)

Bit Description

Scope

Reporting Register of Basic VMX Capabilities (R/O)

Core

See Table 2-2.

IA32_VMX_PINBASED_CTLS

Capability Reporting Register of Pin-based VM-execution Controls (R/O)

Core

See Table 2-2.

IA32_VMX_PROCBASED_CTLS

Capability Reporting Register of Primary Processor-based VM-execution Controls (R/O)

Core

IA32_VMX_EXIT_CTLS

Capability Reporting Register of VM-exit Controls (R/O)

Core

See Table 2-2.

IA32_VMX_ENTRY_CTLS

Capability Reporting Register of VM-entry Controls (R/O)

Core

See Table 2-2.

IA32_VMX_MISC

Reporting Register of Miscellaneous VMX Capabilities (R/O)

Core

See Table 2-2.

IA32_VMX_CR0_FIXED0

Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)

Core

See Table 2-2.

IA32_VMX_CR0_FIXED1

Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)

Core

See Table 2-2.

IA32_VMX_CR4_FIXED0

Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)

Core

See Table 2-2.

IA32_VMX_CR4_FIXED1

Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)

Core

See Table 2-2.

IA32_VMX_VMCS_ENUM

Capability Reporting Register of VMCS Field Enumeration (R/O)

Core

See Table 2-2.

IA32_VMX_PROCBASED_CTLS2

Capability Reporting Register of Secondary Processor-Based VM-Execution Controls (R/O)

Core

See Table 2-2.

IA32_VMX_EPT_VPID_ENUM

Capability Reporting Register of EPT and VPID (R/O)

Core

See Table 2-2.

IA32_VMX_TRUE_PINBASED_CTLS

Vol. 4

2-527

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-62. Additional MSRs Supported by the Intel® Xeon Phi™ Processor 7215, 7285, 7295 Series

with a CPUID Signature DisplayFamily_DisplayModel Value of 06_85H (Contd.)

Bit Description

Scope

Capability Reporting Register of Pin-Based VM-Execution Flex Controls (R/O)

Core

See Table 2-2.

IA32_VMX_TRUE_PROCBASED_CTLS

Capability Reporting Register of Primary Processor-Based VM-Execution Flex Controls (R/O)

Core

See Table 2-2.

IA32_VMX_TRUE_EXIT_CTLS

Capability Reporting Register of VM-Exit Flex Controls (R/O)

Core

See Table 2-2.

IA32_VMX_TRUE_ENTRY_CTLS

Capability Reporting Register of VM-Entry Flex Controls (R/O)

Core

See Table 2-2.

IA32_VMX_FMFUNC

Capability Reporting Register of VM-Function Controls (R/O)

Core

See Table 2-2.

2.19

MSRS IN THE PENTIUM® 4 AND INTEL® XEON® PROCESSORS

Table 2-63 lists MSRs (architectural and model-specific) that are defined across processor generations based on

Intel NetBurst microarchitecture. The processor can be identified by its CPUID signatures of DisplayFamily

encoding of 0FH, see Table 2-1.

• MSRs with an “IA32_” prefix are designated as “architectural.” This means that the functions of these MSRs and

their addresses remain the same for succeeding families of IA-32 processors.

• MSRs with an “MSR_” prefix are model specific with respect to address functionalities. The column “Model Avail-

ability” lists the model encoding value(s) within the Pentium 4 and Intel Xeon processor family at the specified

Identification” in Chapter 3 of the Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.

Table 2-63. MSRs in the Pentium® 4 and Intel® Xeon® Processors

Model

Shared/

Bit Description

Availability

Unique¹

IA32_P5_MC_ADDR

See Section 2.23, “MSRs in Pentium Processors.”

0, 1, 2, 3, 4, 6

Shared

IA32_P5_MC_TYPE

See Section 2.23, “MSRs in Pentium Processors.”

0, 1, 2, 3, 4, 6

Shared

IA32_MONITOR_FILTER_LINE_SIZE

See Section 11.10.5, “Monitor/Mwait Address Range Determination.”

3, 4, 6

Shared

IA32_TIME_STAMP_COUNTER

Time Stamp Counter

0, 1, 2, 3, 4, 6

Unique

See Table 2-2.

2-528 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-63. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

On earlier processors, only the lower 32 bits are writable. On any write to the lower 32 bits, the upper

32 bits are cleared. For processor family 0FH, models 3 and 4: all 64 bits are writable.

IA32_PLATFORM_ID

Platform ID (R)

0, 1, 2, 3, 4, 6

Shared

See Table 2-2.

The operating system can use this MSR to determine “slot” information for the processor and the

proper microcode update to load.

IA32_APIC_BASE

APIC Location and Status (R/W)

0, 1, 2, 3, 4, 6

Unique

See Table 2-2. See Section 13.4.4, “Local APIC Status and Location.”

MSR_EBC_HARD_POWERON

Processor Hard Power-On Configuration

0, 1, 2, 3, 4, 6

Shared

(R/W) Enables and disables processor features.

(R) Indicates current processor configuration.

Output Tri-state Enabled (R)

Indicates whether tri-state output is enabled (1) or disabled (0) as

set by the strapping of SMI#. The value in this bit is written on

the deassertion of RESET#; the bit is set to 1 when the address

bus signal is asserted.

Execute BIST (R)

Indicates whether the execution of the BIST is enabled (1) or

disabled (0) as set by the strapping of INIT#. The value in this bit

is written on the deassertion of RESET#; the bit is set to 1 when

the address bus signal is asserted.

In Order Queue Depth (R)

Indicates whether the in order queue depth for the system bus is

1 (1) or up to 12 (0) as set by the strapping of A7#. The value in

this bit is written on the deassertion of RESET#; the bit is set to

1 when the address bus signal is asserted.

MCERR# Observation Disabled (R)

Indicates whether MCERR# observation is enabled (0) or disabled

(1) as determined by the strapping of A9#. The value in this bit is

written on the deassertion of RESET#; the bit is set to 1 when

the address bus signal is asserted.

BINIT# Observation Enabled (R)

Indicates whether BINIT# observation is enabled (0) or disabled

(1) as determined by the strapping of A10#. The value in this bit

is written on the deassertion of RESET#; the bit is set to 1 when

the address bus signal is asserted.

6:5

APIC Cluster ID (R)

Contains the logical APIC cluster ID value as set by the strapping

of A12# and A11#. The logical cluster ID value is written into the

field on the deassertion of RESET#; the field is set to 1 when the

address bus signal is asserted.

Vol. 4

2-529

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-63. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

Bus Park Disable (R)

Indicates whether bus park is enabled (0) or disabled (1) as set by

the strapping of A15#. The value in this bit is written on the

deassertion of RESET#; the bit is set to 1 when the address bus

signal is asserted.

11:8

Reserved.

13:12

Agent ID (R)

Contains the logical agent ID value as set by the strapping of

BR[3:0]. The logical ID value is written into the field on the

deassertion of RESET#; the field is set to 1 when the address bus

signal is asserted.

63:14

Reserved.

MSR_EBC_SOFT_POWERON

Processor Soft Power-On Configuration (R/W)

0, 1, 2, 3, 4, 6

Shared

Enables and disables processor features.

RCNT/SCNT On Request Encoding Enable (R/W)

Controls the driving of RCNT/SCNT on the request encoding. Set

to enable (1); clear to disabled (0, default).

Data Error Checking Disable (R/W)

Set to disable system data bus parity checking; clear to enable

parity checking.

Response Error Checking Disable (R/W)

Set to disable (default); clear to enable.

Address/Request Error Checking Disable (R/W)

Set to disable (default); clear to enable.

Initiator MCERR# Disable (R/W)

Set to disable MCERR# driving for initiator bus requests (default);

clear to enable.

Internal MCERR# Disable (R/W)

Set to disable MCERR# driving for initiator internal errors

(default); clear to enable.

BINIT# Driver Disable (R/W)

Set to disable BINIT# driver (default); clear to enable driver.

63:7

Reserved.

MSR_EBC_FREQUENCY_ID

Processor Frequency Configuration

2,3, 4, 6

Shared

The bit field layout of this MSR varies according to the MODEL value in the CPUID version information.

The following bit field layout applies to Pentium 4 and Xeon Processors with MODEL encoding equal or

greater than 2.

(R) The field Indicates the current processor frequency configuration.

15:0

Reserved.

2-530 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-63. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

18:16

Scalable Bus Speed (R/W)

Indicates the intended scalable bus speed:

EncodingScalable Bus Speed

000B

100 MHz (Model 2)

000B

266 MHz (Model 3 or 4)

001B

133 MHz

010B

200 MHz

011B

166 MHz

100B

333 MHz (Model 6)

133.33 MHz should be utilized if performing calculation with

System Bus Speed when encoding is 001B.

166.67 MHz should be utilized if performing calculation with

System Bus Speed when encoding is 011B.

266.67 MHz should be utilized if performing calculation with

System Bus Speed when encoding is 000B and model encoding =

3 or 4.

333.33 MHz should be utilized if performing calculation with

System Bus Speed when encoding is 100B and model encoding =

All other values are reserved.

23:19

Reserved.

31:24

Core Clock Frequency to System Bus Frequency Ratio (R)

The processor core clock frequency to system bus frequency

ratio observed at the deassertion of the reset pin.

63:32

Reserved.

MSR_EBC_FREQUENCY_ID

Processor Frequency Configuration (R)

0, 1

Shared

The bit field layout of this MSR varies according to the MODEL value of the CPUID version information.

This bit field layout applies to Pentium 4 and Xeon Processors with MODEL encoding less than 2.

Indicates current processor frequency configuration.

20:0

Reserved.

23:21

Scalable Bus Speed (R/W)

Indicates the intended scalable bus speed:

Encoding Scalable Bus Speed

000B

100 MHz

All others values reserved.

63:24

Reserved.

IA32_FEATURE_CONTROL

Control Features in IA-32 Processor (R/W)

3, 4, 6

Unique

See Table 2-2.

(If CPUID.01H:ECX[5])

IA32_BIOS_UPDT_TRIG

Vol. 4

2-531

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-63. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

BIOS Update Trigger Register (W)

0, 1, 2, 3, 4, 6

Shared

See Table 2-2.

IA32_BIOS_SIGN_ID

BIOS Update Signature ID (R/W)

0, 1, 2, 3, 4, 6

Unique

See Table 2-2.

IA32_SMM_MONITOR_CTL

SMM Monitor Configuration (R/W)

3, 4, 6

Unique

See Table 2-2.

IA32_MTRRCAP

MTRR Information

0, 1, 2, 3, 4, 6

Unique

See Section 14.11.1, “MTRR Feature Identification.”

IA32_SYSENTER_CS

CS Register Target for CPL 0 Code (R/W)

0, 1, 2, 3, 4, 6

Unique

See Table 2-2 and Section 6.8.7, “Performing Fast Calls to System Procedures with the SYSENTER and

SYSEXIT Instructions.”

IA32_SYSENTER_ESP

Stack Pointer for CPL 0 Stack (R/W)

0, 1, 2, 3, 4, 6

Unique

See Table 2-2 and Section 6.8.7, “Performing Fast Calls to System Procedures with the SYSENTER and

SYSEXIT Instructions.”

IA32_SYSENTER_EIP

CPL 0 Code Entry Point (R/W)

0, 1, 2, 3, 4, 6

Unique

See Table 2-2 and Section 6.8.7, “Performing Fast Calls to System Procedures with the SYSENTER and

SYSEXIT Instructions.”

IA32_MCG_CAP

Machine Check Capabilities (R)

0, 1, 2, 3, 4, 6

Unique

See Table 2-2 and Section 18.3.1.1, “IA32_MCG_CAP MSR.”

IA32_MCG_STATUS

Machine Check Status (R)

0, 1, 2, 3, 4, 6

Unique

See Table 2-2 and Section 18.3.1.2, “IA32_MCG_STATUS MSR.”

IA32_MCG_CTL

Machine Check Feature Enable (R/W)

See Table 2-2 and Section 18.3.1.3, “IA32_MCG_CTL MSR.”

MSR_MCG_RAX

Machine Check EAX/RAX Save State

0, 1, 2, 3, 4, 6

Unique

See Section 18.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”

63:0

Contains register state at time of machine check error. When in

non-64-bit modes at the time of the error, bits 63-32 do not

contain valid data.

MSR_MCG_RBX

2-532 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-63. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

Machine Check EBX/RBX Save State

0, 1, 2, 3, 4, 6

Unique

See Section 18.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”

63:0

Contains register state at time of machine check error. When in

non-64-bit modes at the time of the error, bits 63-32 do not

contain valid data.

MSR_MCG_RCX

Machine Check ECX/RCX Save State

0, 1, 2, 3, 4, 6

Unique

See Section 18.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”

63:0

Contains register state at time of machine check error. When in

non-64-bit modes at the time of the error, bits 63-32 do not

contain valid data.

MSR_MCG_RDX

Machine Check EDX/RDX Save State

0, 1, 2, 3, 4, 6

Unique

See Section 18.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”

63:0

Contains register state at time of machine check error. When in

non-64-bit modes at the time of the error, bits 63-32 do not

contain valid data.

MSR_MCG_RSI

Machine Check ESI/RSI Save State

0, 1, 2, 3, 4, 6

Unique

See Section 18.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”

63:0

Contains register state at time of machine check error. When in

non-64-bit modes at the time of the error, bits 63-32 do not

contain valid data.

MSR_MCG_RDI

Machine Check EDI/RDI Save State

0, 1, 2, 3, 4, 6

Unique

See Section 18.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”

63:0

Contains register state at time of machine check error. When in

non-64-bit modes at the time of the error, bits 63-32 do not

contain valid data.

MSR_MCG_RBP

Machine Check EBP/RBP Save State

0, 1, 2, 3, 4, 6

Unique

See Section 18.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”

63:0

Contains register state at time of machine check error. When in

non-64-bit modes at the time of the error, bits 63-32 do not

contain valid data.

MSR_MCG_RSP

Machine Check ESP/RSP Save State

0, 1, 2, 3, 4, 6

Unique

See Section 18.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”

63:0

Contains register state at time of machine check error. When in

non-64-bit modes at the time of the error, bits 63-32 do not

contain valid data.

MSR_MCG_RFLAGS

Vol. 4

2-533

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-63. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

Machine Check EFLAGS/RFLAG Save State

0, 1, 2, 3, 4, 6

Unique

See Section 18.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”

63:0

Contains register state at time of machine check error. When in

non-64-bit modes at the time of the error, bits 63-32 do not

contain valid data.

MSR_MCG_RIP

Machine Check EIP/RIP Save State

0, 1, 2, 3, 4, 6

Unique

See Section 18.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”

63:0

Contains register state at time of machine check error. When in

non-64-bit modes at the time of the error, bits 63-32 do not

contain valid data.

MSR_MCG_MISC

Machine Check Miscellaneous

0, 1, 2, 3, 4, 6

Unique

See Section 18.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”

When set, the bit indicates that a page assist or page fault

occurred during DS normal operation. The processors response is

to shut down.

The bit is used as an aid for debugging DS handling code. It is the

responsibility of the user (BIOS or operating system) to clear this

bit for normal operation.

63:1

Reserved.

MSR_MCG_RESERVED1-MSR_MCG_RESERVED5

395-399

Reserved.

MSR_MCG_R8

Machine Check R8

0, 1, 2, 3, 4, 6

Unique

See Section 18.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”

63:0

Registers R8-15 (and the associated state-save MSRs) exist only

in Intel 64 processors. These registers contain valid information

only when the processor is operating in 64-bit mode at the time

of the error.

MSR_MCG_R9

Machine Check R9D/R9

0, 1, 2, 3, 4, 6

Unique

See Section 18.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”

63:0

Registers R8-15 (and the associated state-save MSRs) exist only

in Intel 64 processors. These registers contain valid information

only when the processor is operating in 64-bit mode at the time

of the error.

MSR_MCG_R10

Machine Check R10

0, 1, 2, 3, 4, 6

Unique

See Section 18.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”

2-534 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-63. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

63:0

Registers R8-15 (and the associated state-save MSRs) exist only

in Intel 64 processors. These registers contain valid information

only when the processor is operating in 64-bit mode at the time

of the error.

MSR_MCG_R11

Machine Check R11

0, 1, 2, 3, 4, 6

Unique

See Section 18.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”

63:0

Registers R8-15 (and the associated state-save MSRs) exist only

in Intel 64 processors. These registers contain valid information

only when the processor is operating in 64-bit mode at the time

of the error.

MSR_MCG_R12

Machine Check R12

0, 1, 2, 3, 4, 6

Unique

See Section 18.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”

63:0

Registers R8-15 (and the associated state-save MSRs) exist only

in Intel 64 processors. These registers contain valid information

only when the processor is operating in 64-bit mode at the time

of the error.

MSR_MCG_R13

Machine Check R13

0, 1, 2, 3, 4, 6

Unique

See Section 18.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”

63:0

Registers R8-15 (and the associated state-save MSRs) exist only

in Intel 64 processors. These registers contain valid information

only when the processor is operating in 64-bit mode at the time

of the error.

MSR_MCG_R14

Machine Check R14

0, 1, 2, 3, 4, 6

Unique

See Section 18.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”

63:0

Registers R8-15 (and the associated state-save MSRs) exist only

in Intel 64 processors. These registers contain valid information

only when the processor is operating in 64-bit mode at the time

of the error.

MSR_MCG_R15

Machine Check R15

0, 1, 2, 3, 4, 6

Unique

See Section 18.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”

63:0

Registers R8-15 (and the associated state-save MSRs) exist only

in Intel 64 processors. These registers contain valid information

only when the processor is operating in 64-bit mode at the time

of the error.

IA32_PERF_STATUS

See Table 2-2. See Section 17.1, “Enhanced Intel Speedstep® Technology.”

3, 4, 6

Unique

IA32_PERF_CTL

See Table 2-2. See Section 17.1, “Enhanced Intel Speedstep® Technology.”

3, 4, 6

Unique

Vol. 4

2-535

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-63. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

IA32_CLOCK_MODULATION

Thermal Monitor Control (R/W)

0, 1, 2, 3, 4, 6

Unique

See Table 2-2 and Section 17.8.3, “Software Controlled Clock Modulation.”

IA32_THERM_INTERRUPT

Thermal Interrupt Control (R/W)

0, 1, 2, 3, 4, 6

Unique

See Section 17.8.2, “Thermal Monitor,” and Table 2-2.

IA32_THERM_STATUS

Thermal Monitor Status (R/W)

0, 1, 2, 3, 4, 6

Shared

See Section 17.8.2, “Thermal Monitor,” and Table 2-2.

MSR_THERM2_CTL

Thermal Monitor 2 Control

For Family F, Model 3 processors: When read, specifies the value of the target TM2 transition last

Shared

written. When set, it sets the next target value for TM2 transition.

For Family F, Model 4 and Model 6 processors: When read, specifies the value of the target TM2

4, 6

Shared

transition last written. Writes may cause #GP exceptions.

IA32_MISC_ENABLE

Enable Miscellaneous Processor Features (R/W)

0, 1, 2, 3, 4, 6

Shared

Fast-Strings Enable. See Table 2-2.

Reserved.

x87 FPU Fopcode Compatibility Mode Enable

Thermal Monitor 1 Enable

See Section 17.8.2, “Thermal Monitor,” and Table 2-2.

Split-Lock Disable

When set, the bit causes an #AC exception to be issued instead

of a split-lock cycle. Operating systems that set this bit must align

system structures to avoid split-lock scenarios.

When the bit is clear (default), normal split-locks are issued to the

bus.

This debug feature is specific to the Pentium 4 processor.

Reserved.

Third-Level Cache Disable (R/W)

When set, the third-level cache is disabled; when clear (default)

the third-level cache is enabled. This flag is reserved for

processors that do not have a third-level cache.

Note that the bit controls only the third-level cache; and only if

overall caching is enabled through the CD flag of control register

CR0, the page-level cache controls, and/or the MTRRs.

See Section 14.5.4, “Disabling and Enabling the L3 Cache.”

Performance Monitoring Available (R)

See Table 2-2.

2-536 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-63. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

Suppress Lock Enable

When set, assertion of LOCK on the bus is suppressed during a

Split Lock access. When clear (default), LOCK is not suppressed.

Prefetch Queue Disable

When set, disables the prefetch queue. When clear (default),

enables the prefetch queue.

FERR# Interrupt Reporting Enable (R/W)

When set, interrupt reporting through the FERR# pin is enabled;

when clear, this interrupt reporting function is disabled.

When this flag is set and the processor is in the stop-clock state

(STPCLK# is asserted), asserting the FERR# pin signals to the

processor that an interrupt (such as, INIT#, BINIT#, INTR, NMI,

SMI#, or RESET#) is pending and that the processor should return

to normal operation to handle the interrupt.

This flag does not affect the normal operation of the FERR# pin

(to indicate an unmasked floating-point error) when the STPCLK#

pin is not asserted.

Branch Trace Storage Unavailable (BTS_UNAVILABLE) (R)

See Table 2-2.

When set, the processor does not support branch trace storage

(BTS); when clear, BTS is supported.

PEBS_UNAVILABLE: Processor Event Based Sampling Unavailable

(R)

See Table 2-2.

When set, the processor does not support processor event-based

sampling (PEBS); when clear, PEBS is supported.

TM2 Enable (R/W)

When this bit is set (1) and the thermal sensor indicates that the

die temperature is at the pre-determined threshold, the Thermal

Monitor 2 mechanism is engaged. TM2 will reduce the bus to core

ratio and voltage according to the value last written to

MSR_THERM2_CTL bits 15:0.

When this bit is clear (0, default), the processor does not change

the VID signals or the bus to core ratio when the processor

enters a thermal managed state.

If the TM2 feature flag (ECX[8]) is not set to 1 after executing

CPUID with EAX = 1, then this feature is not supported and BIOS

must not alter the contents of this bit location. The processor is

operating out of spec if both this bit and the TM1 bit are set to

disabled states.

17:14

Reserved.

ENABLE MONITOR FSM (R/W)

3, 4, 6

See Table 2-2.

Vol. 4

2-537

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-63. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

Adjacent Cache Line Prefetch Disable (R/W)

When set to 1, the processor fetches the cache line of the 128-

byte sector containing currently required data. When set to 0, the

processor fetches both cache lines in the sector.

Single processor platforms should not set this bit. Server

platforms should set or clear this bit based on platform

performance observed in validation and testing.

BIOS may contain a setup option that controls the setting of this

bit.

21:20

Reserved.

Limit CPUID MAXVAL (R/W)

3, 4, 6

See Table 2-2.

Setting this can cause unexpected behavior to software that

depends on the availability of CPUID leaves greater than 3.

xTPR Message Disable (R/W)

Shared

See Table 2-2.

L1 Data Cache Context Mode (R/W)

When set, the L1 data cache is placed in shared mode; when clear

(default), the cache is placed in adaptive mode. This bit is only

enabled for IA-32 processors that support Intel Hyper-Threading

Technology. See Section 14.5.6, “L1 Data Cache Context Mode.”

When L1 is running in adaptive mode and CR3s are identical, data

in L1 is shared across logical processors. Otherwise, L1 is not

shared and cache use is competitive.

If the Context ID feature flag (ECX[10]) is set to 0 after executing

CPUID with EAX = 1, the ability to switch modes is not supported.

BIOS must not alter the contents of IA32_MISC_ENABLE[24].

33:25

Reserved.

XD Bit Disable (R/W)

Unique

See Table 2-3.

63:35

Reserved.

MSR_PLATFORM_BRV

Platform Feature Requirements (R)

3, 4, 6

Shared

17:0

Reserved.

PLATFORM Requirements

When set to 1, indicates the processor has specific platform

requirements. The details of the platform requirements are listed

in the respective data sheets of the processor.

63:19

Reserved.

MSR_LER_FROM_LIP

2-538 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-63. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

Last Exception Record From Linear IP (R)

0, 1, 2, 3, 4, 6

Unique

Contains a pointer to the last branch instruction that the processor executed prior to the last

exception that was generated or the last interrupt that was handled.

See Section 20.13.3, “Last Exception Records.”

31:0

From Linear IP

Linear address of the last branch instruction.

63:32

Reserved.

MSR_LER_FROM_LIP

63:0

From Linear IP

Unique

Linear address of the last branch instruction (If IA-32e mode is

active).

MSR_LER_TO_LIP

Last Exception Record To Linear IP (R)

0, 1, 2, 3, 4, 6

Unique

This area contains a pointer to the target of the last branch instruction that the processor executed

prior to the last exception that was generated or the last interrupt that was handled.

See Section 20.13.3, “Last Exception Records.”

31:0

From Linear IP

Linear address of the target of the last branch instruction.

63:32

Reserved.

MSR_LER_TO_LIP

63:0

From Linear IP

Unique

Linear address of the target of the last branch instruction (If IA-

32e mode is active).

MSR_DEBUGCTLA

Debug Control (R/W)

0, 1, 2, 3, 4, 6

Unique

Controls how several debug features are used. Bit definitions are discussed in the referenced section.

See Section 20.13.1, “MSR_DEBUGCTLA MSR.”

MSR_LASTBRANCH_TOS

Last Branch Record Stack TOS (R/O)

0, 1, 2, 3, 4, 6

Unique

Contains an index (0-3 or 0-15) that points to the top of the last branch record stack (that is, that

points the index of the MSR containing the most recent branch record).

See Section 20.13.2, “LBR Stack for Processors Based on Intel NetBurst® Microarchitecture,” and

addresses 1DBH-1DEH and 680H-68FH.

MSR_LASTBRANCH_0

Last Branch Record 0 (R/O)

0, 1, 2

Unique

One of four last branch record registers on the last branch record stack. It contains pointers to the

source and destination instruction for one of the last four branches, exceptions, or interrupts that the

processor took.

MSR_LASTBRANCH_0 through MSR_LASTBRANCH_3 at 1DBH-1DEH are available only on family 0FH,

models 0H-02H. They have been replaced by the MSRs at 680H-68FH and 6C0H-6CFH.

See Section 20.12, “Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based

on Skylake Microarchitecture.”

Vol. 4

2-539

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-63. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

MSR_LASTBRANCH_1

Last Branch Record 1

0, 1, 2

Unique

See description of the MSR_LASTBRANCH_0 MSR at 1DBH.

MSR_LASTBRANCH_2

Last Branch Record 2

0, 1, 2

Unique

See description of the MSR_LASTBRANCH_0 MSR at 1DBH.

MSR_LASTBRANCH_3

Last Branch Record 3

0, 1, 2

Unique

See description of the MSR_LASTBRANCH_0 MSR at 1DBH.

IA32_MTRR_PHYSBASE0

Variable Range Base MTRR

0, 1, 2, 3, 4, 6

Shared

See Section 14.11.2.3, “Variable Range MTRRs.”

IA32_MTRR_PHYSMASK0

Variable Range Mask MTRR

0, 1, 2, 3, 4, 6

Shared

See Section 14.11.2.3, “Variable Range MTRRs.”

IA32_MTRR_PHYSBASE1

Variable Range Mask MTRR

0, 1, 2, 3, 4, 6

Shared

See Section 14.11.2.3, “Variable Range MTRRs.”

IA32_MTRR_PHYSMASK1

Variable Range Mask MTRR

0, 1, 2, 3, 4, 6

Shared

See Section 14.11.2.3, “Variable Range MTRRs.”

IA32_MTRR_PHYSBASE2

Variable Range Mask MTRR

0, 1, 2, 3, 4, 6

Shared

See Section 14.11.2.3, “Variable Range MTRRs.”

IA32_MTRR_PHYSMASK2

Variable Range Mask MTRR

0, 1, 2, 3, 4, 6

Shared

See Section 14.11.2.3, “Variable Range MTRRs”.

IA32_MTRR_PHYSBASE3

Variable Range Mask MTRR

0, 1, 2, 3, 4, 6

Shared

See Section 14.11.2.3, “Variable Range MTRRs.”

IA32_MTRR_PHYSMASK3

Variable Range Mask MTRR

0, 1, 2, 3, 4, 6

Shared

See Section 14.11.2.3, “Variable Range MTRRs.”

IA32_MTRR_PHYSBASE4

Variable Range Mask MTRR

0, 1, 2, 3, 4, 6

Shared

See Section 14.11.2.3, “Variable Range MTRRs.”

IA32_MTRR_PHYSMASK4

2-540 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-63. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

Variable Range Mask MTRR

0, 1, 2, 3, 4, 6

Shared

See Section 14.11.2.3, “Variable Range MTRRs.”

IA32_MTRR_PHYSBASE5

Variable Range Mask MTRR

0, 1, 2, 3, 4, 6

Shared

See Section 14.11.2.3, “Variable Range MTRRs.”

IA32_MTRR_PHYSMASK5

Variable Range Mask MTRR

0, 1, 2, 3, 4, 6

Shared

See Section 14.11.2.3, “Variable Range MTRRs.”

IA32_MTRR_PHYSBASE6

Variable Range Mask MTRR

0, 1, 2, 3, 4, 6

Shared

See Section 14.11.2.3, “Variable Range MTRRs.”

IA32_MTRR_PHYSMASK6

Variable Range Mask MTRR

0, 1, 2, 3, 4, 6

Shared

See Section 14.11.2.3, “Variable Range MTRRs.”

IA32_MTRR_PHYSBASE7

Variable Range Mask MTRR

0, 1, 2, 3, 4, 6

Shared

See Section 14.11.2.3, “Variable Range MTRRs.”

IA32_MTRR_PHYSMASK7

Variable Range Mask MTRR

0, 1, 2, 3, 4, 6

Shared

See Section 14.11.2.3, “Variable Range MTRRs.”

IA32_MTRR_FIX64K_00000

Fixed Range MTRR

0, 1, 2, 3, 4, 6

Shared

See Section 14.11.2.2, “Fixed Range MTRRs.”

IA32_MTRR_FIX16K_80000

Fixed Range MTRR

0, 1, 2, 3, 4, 6

Shared

See Section 14.11.2.2, “Fixed Range MTRRs.”

IA32_MTRR_FIX16K_A0000

Fixed Range MTRR

0, 1, 2, 3, 4, 6

Shared

See Section 14.11.2.2, “Fixed Range MTRRs.”

IA32_MTRR_FIX4K_C0000

Fixed Range MTRR

0, 1, 2, 3, 4, 6

Shared

See Section 14.11.2.2, “Fixed Range MTRRs.”

IA32_MTRR_FIX4K_C8000

Fixed Range MTRR

0, 1, 2, 3, 4, 6

Shared

See Section 14.11.2.2, “Fixed Range MTRRs”.

IA32_MTRR_FIX4K_D0000

Fixed Range MTRR

0, 1, 2, 3, 4, 6

Shared

See Section 14.11.2.2, “Fixed Range MTRRs”.

Vol. 4

2-541

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-63. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

IA32_MTRR_FIX4K_D8000

Fixed Range MTRR

0, 1, 2, 3, 4, 6

Shared

See Section 14.11.2.2, “Fixed Range MTRRs.”

IA32_MTRR_FIX4K_E0000

Fixed Range MTRR

0, 1, 2, 3, 4, 6

Shared

See Section 14.11.2.2, “Fixed Range MTRRs.”

IA32_MTRR_FIX4K_E8000

Fixed Range MTRR

0, 1, 2, 3, 4, 6

Shared

See Section 14.11.2.2, “Fixed Range MTRRs.”

IA32_MTRR_FIX4K_F0000

Fixed Range MTRR

0, 1, 2, 3, 4, 6

Shared

See Section 14.11.2.2, “Fixed Range MTRRs.”

IA32_MTRR_FIX4K_F8000

Fixed Range MTRR

0, 1, 2, 3, 4, 6

Shared

See Section 14.11.2.2, “Fixed Range MTRRs.”

IA32_PAT

Page Attribute Table

0, 1, 2, 3, 4, 6

Unique

See Section 14.11.2.2, “Fixed Range MTRRs.”

IA32_MTRR_DEF_TYPE

Default Memory Types (R/W)

0, 1, 2, 3, 4, 6

Shared

See Table 2-2 and Section 14.11.2.1, “IA32_MTRR_DEF_TYPE MSR.”

MSR_BPU_COUNTER0

See Section 22.6.3.2, “Performance Counters.”

0, 1, 2, 3, 4, 6

Shared

MSR_BPU_COUNTER1

See Section 22.6.3.2, “Performance Counters.”

0, 1, 2, 3, 4, 6

Shared

MSR_BPU_COUNTER2

See Section 22.6.3.2, “Performance Counters.”

0, 1, 2, 3, 4, 6

Shared

MSR_BPU_COUNTER3

See Section 22.6.3.2, “Performance Counters.”

0, 1, 2, 3, 4, 6

Shared

MSR_MS_COUNTER0

See Section 22.6.3.2, “Performance Counters.”

0, 1, 2, 3, 4, 6

Shared

MSR_MS_COUNTER1

See Section 22.6.3.2, “Performance Counters.”

0, 1, 2, 3, 4, 6

Shared

MSR_MS_COUNTER2

See Section 22.6.3.2, “Performance Counters.”

0, 1, 2, 3, 4, 6

Shared

MSR_MS_COUNTER3

See Section 22.6.3.2, “Performance Counters.”

0, 1, 2, 3, 4, 6

Shared

MSR_FLAME_COUNTER0

2-542 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-63. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

See Section 22.6.3.2, “Performance Counters.”

0, 1, 2, 3, 4, 6

Shared

MSR_FLAME_COUNTER1

See Section 22.6.3.2, “Performance Counters.”

0, 1, 2, 3, 4, 6

Shared

MSR_FLAME_COUNTER2

See Section 22.6.3.2, “Performance Counters.”

0, 1, 2, 3, 4, 6

Shared

MSR_FLAME_COUNTER3

See Section 22.6.3.2, “Performance Counters.”

0, 1, 2, 3, 4, 6

Shared

MSR_IQ_COUNTER0

See Section 22.6.3.2, “Performance Counters.”

0, 1, 2, 3, 4, 6

Shared

MSR_IQ_COUNTER1

See Section 22.6.3.2, “Performance Counters.”

0, 1, 2, 3, 4, 6

Shared

MSR_IQ_COUNTER2

See Section 22.6.3.2, “Performance Counters.”

0, 1, 2, 3, 4, 6

Shared

MSR_IQ_COUNTER3

See Section 22.6.3.2, “Performance Counters.”

0, 1, 2, 3, 4, 6

Shared

MSR_IQ_COUNTER4

See Section 22.6.3.2, “Performance Counters.”

0, 1, 2, 3, 4, 6

Shared

MSR_IQ_COUNTER5

See Section 22.6.3.2, “Performance Counters.”

0, 1, 2, 3, 4, 6

Shared

MSR_BPU_CCCR0

See Section 22.6.3.3, “CCCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_BPU_CCCR1

See Section 22.6.3.3, “CCCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_BPU_CCCR2

See Section 22.6.3.3, “CCCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_BPU_CCCR3

See Section 22.6.3.3, “CCCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_MS_CCCR0

See Section 22.6.3.3, “CCCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_MS_CCCR1

See Section 22.6.3.3, “CCCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_MS_CCCR2

See Section 22.6.3.3, “CCCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_MS_CCCR3

See Section 22.6.3.3, “CCCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_FLAME_CCCR0

See Section 22.6.3.3, “CCCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

Vol. 4

2-543

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-63. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

MSR_FLAME_CCCR1

See Section 22.6.3.3, “CCCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_FLAME_CCCR2

See Section 22.6.3.3, “CCCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_FLAME_CCCR3

See Section 22.6.3.3, “CCCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_IQ_CCCR0

See Section 22.6.3.3, “CCCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_IQ_CCCR1

See Section 22.6.3.3, “CCCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_IQ_CCCR2

See Section 22.6.3.3, “CCCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_IQ_CCCR3

See Section 22.6.3.3, “CCCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_IQ_CCCR4

See Section 22.6.3.3, “CCCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_IQ_CCCR5

See Section 22.6.3.3, “CCCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_BSU_ESCR0

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_BSU_ESCR1

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_FSB_ESCR0

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_FSB_ESCR1

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_FIRM_ESCR0

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_FIRM_ESCR1

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_FLAME_ESCR0

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_FLAME_ESCR1

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_DAC_ESCR0

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_DAC_ESCR1

2-544 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-63. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_MOB_ESCR0

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_MOB_ESCR1

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_PMH_ESCR0

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_PMH_ESCR1

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_SAAT_ESCR0

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_SAAT_ESCR1

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_U2L_ESCR0

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_U2L_ESCR1

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_BPU_ESCR0

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_BPU_ESCR1

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_IS_ESCR0

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_IS_ESCR1

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_ITLB_ESCR0

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_ITLB_ESCR1

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_CRU_ESCR0

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_CRU_ESCR1

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_IQ_ESCR0

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2

Shared

This MSR is not available on later processors. It is only available on processor family 0FH, models 01H-

02H.

Vol. 4

2-545

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-63. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

MSR_IQ_ESCR1

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2

Shared

This MSR is not available on later processors. It is only available on processor family 0FH, models 01H-

02H.

MSR_RAT_ESCR0

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_RAT_ESCR1

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_SSU_ESCR0

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_MS_ESCR0

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_MS_ESCR1

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_TBPU_ESCR0

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_TBPU_ESCR1

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_TC_ESCR0

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_TC_ESCR1

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_IX_ESCR0

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_IX_ESCR1

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_ALF_ESCR0

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_ALF_ESCR1

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_CRU_ESCR2

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_CRU_ESCR3

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_CRU_ESCR4

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_CRU_ESCR5

2-546 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-63. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

MSR_TC_PRECISE_EVENT

See Section 22.6.3.1, “ESCR MSRs.”

0, 1, 2, 3, 4, 6

Shared

IA32_PEBS_ENABLE (MSR_PEBS_ENABLE)

Processor Event Based Sampling (PEBS) (R/W)

0, 1, 2, 3, 4, 6

Shared

Controls the enabling of processor event sampling and replay tagging.

12:0

See https://perfmon-events.intel.com/.

23:13

Reserved.

UOP Tag

Enables replay tagging when set.

ENABLE_PEBS_MY_THR (R/W)

Enables PEBS for the target logical processor when set; disables

PEBS when clear (default).

See Section 22.6.4.3, “IA32_PEBS_ENABLE MSR,” for an

explanation of the target logical processor.

This bit is called ENABLE_PEBS in IA-32 processors that do not

support Intel Hyper-Threading Technology.

ENABLE_PEBS_OTH_THR (R/W)

Enables PEBS for the target logical processor when set; disables

PEBS when clear (default).

See Section 22.6.4.3, “IA32_PEBS_ENABLE MSR,” for an

explanation of the target logical processor.

This bit is reserved for IA-32 processors that do not support Intel

Hyper-Threading Technology.

63:27

Reserved.

MSR_PEBS_MATRIX_VERT

See https://perfmon-events.intel.com/.

0, 1, 2, 3, 4, 6

Shared

IA32_MC0_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

0, 1, 2, 3, 4, 6

Shared

IA32_MC0_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

0, 1, 2, 3, 4, 6

Shared

IA32_MC0_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

0, 1, 2, 3, 4, 6

Shared

The IA32_MC0_ADDR register is either not implemented or contains no address if the ADDRV flag in

the IA32_MC0_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-

protection exception.

IA32_MC0_MISC

Vol. 4

2-547

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-63. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

See Section 18.3.2.4, “IA32_MCi_MISC MSRs.”

0, 1, 2, 3, 4, 6

Shared

The IA32_MC0_MISC MSR is either not implemented or does not contain additional information if the

MISCV flag in the IA32_MC0_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-

protection exception.

IA32_MC1_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

0, 1, 2, 3, 4, 6

Shared

IA32_MC1_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

0, 1, 2, 3, 4, 6

Shared

IA32_MC1_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

0, 1, 2, 3, 4, 6

Shared

The IA32_MC1_ADDR register is either not implemented or contains no address if the ADDRV flag in

the IA32_MC1_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-

protection exception.

IA32_MC1_MISC

See Section 18.3.2.4, “IA32_MCi_MISC MSRs.”

Shared

The IA32_MC1_MISC MSR is either not implemented or does not contain additional information if the

MISCV flag in the IA32_MC1_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-

protection exception.

IA32_MC2_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

0, 1, 2, 3, 4, 6

Shared

IA32_MC2_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

0, 1, 2, 3, 4, 6

Shared

IA32_MC2_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in

the IA32_MC2_STATUS register is clear. When not implemented in the processor, all reads and writes

to this MSR will cause a general-protection exception.

IA32_MC2_MISC

See Section 18.3.2.4, “IA32_MCi_MISC MSRs.”

The IA32_MC2_MISC MSR is either not implemented or does not contain additional information if the

MISCV flag in the IA32_MC2_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-

protection exception.

IA32_MC3_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

0, 1, 2, 3, 4, 6

Shared

IA32_MC3_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

0, 1, 2, 3, 4, 6

Shared

IA32_MC3_ADDR

2-548 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-63. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

0, 1, 2, 3, 4, 6

Shared

The IA32_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in

the IA32_MC3_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-

protection exception.

IA32_MC3_MISC

See Section 18.3.2.4, “IA32_MCi_MISC MSRs.”

0, 1, 2, 3, 4, 6

Shared

The IA32_MC3_MISC MSR is either not implemented or does not contain additional information if the

MISCV flag in the IA32_MC3_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-

protection exception.

IA32_MC4_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

0, 1, 2, 3, 4, 6

Shared

IA32_MC4_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

0, 1, 2, 3, 4, 6

Shared

IA32_MC4_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in

the IA32_MC4_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-

protection exception.

IA32_MC4_MISC

See Section 18.3.2.4, “IA32_MCi_MISC MSRs.”

The IA32_MC2_MISC MSR is either not implemented or does not contain additional information if the

MISCV flag in the IA32_MC4_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-

protection exception.

IA32_VMX_BASIC

Reporting Register of Basic VMX Capabilities (R/O)

3, 4, 6

Unique

See Table 2-2 and Appendix A.1, “Basic VMX Information.”

IA32_VMX_PINBASED_CTLS

Capability Reporting Register of Pin-Based VM-Execution Controls (R/O)

3, 4, 6

Unique

See Table 2-2 and Appendix A.3, “VM-Execution Controls.”

IA32_VMX_PROCBASED_CTLS

Capability Reporting Register of Primary Processor-Based VM-Execution Controls (R/O)

3, 4, 6

Unique

See Appendix A.3, “VM-Execution Controls,” and Table 2-2.

IA32_VMX_EXIT_CTLS

Capability Reporting Register of VM-Exit Controls (R/O)

3, 4, 6

Unique

See Appendix A.4, “VM-Exit Controls,” and Table 2-2.

IA32_VMX_ENTRY_CTLS

Vol. 4

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-63. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

Capability Reporting Register of VM-Entry Controls (R/O)

3, 4, 6

Unique

See Appendix A.5, “VM-Entry Controls,” and Table 2-2.

IA32_VMX_MISC

Reporting Register of Miscellaneous VMX Capabilities (R/O)

3, 4, 6

Unique

See Appendix A.6, “Miscellaneous Data,” and Table 2-2.

IA32_VMX_CR0_FIXED0

Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)

3, 4, 6

Unique

See Appendix A.7, “VMX-Fixed Bits in CR0,” and Table 2-2.

IA32_VMX_CR0_FIXED1

Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)

3, 4, 6

Unique

See Appendix A.7, “VMX-Fixed Bits in CR0,” and Table 2-2.

IA32_VMX_CR4_FIXED0

Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)

3, 4, 6

Unique

See Appendix A.8, “VMX-Fixed Bits in CR4,” and Table 2-2.

IA32_VMX_CR4_FIXED1

Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)

3, 4, 6

Unique

See Appendix A.8, “VMX-Fixed Bits in CR4,” and Table 2-2.

IA32_VMX_VMCS_ENUM

Capability Reporting Register of VMCS Field Enumeration (R/O)

3, 4, 6

Unique

See Appendix A.9, “VMCS Enumeration,” and Table 2-2.

IA32_VMX_PROCBASED_CTLS2

Capability Reporting Register of Secondary Processor-Based VM-Execution Controls (R/O)

3, 4, 6

Unique

See Appendix A.3, “VM-Execution Controls,” and Table 2-2.

IA32_DS_AREA

DS Save Area (R/W)

0, 1, 2, 3, 4, 6

Unique

See Table 2-2 and Section 22.6.3.4, “Debug Store (DS) Mechanism.”

MSR_LASTBRANCH_0_FROM_IP

Last Branch Record 0 (R/W)

3, 4, 6

Unique

One of 16 pairs of last branch record registers on the last branch record stack (680H-68FH). This part

of the stack contains pointers to the source instruction for one of the last 16 branches, exceptions, or

interrupts taken by the processor.

The MSRs at 680H-68FH, 6C0H-6CfH are not available in processor releases before family 0FH, model

03H. These MSRs replace MSRs previously located at 1DBH-1DEH. which performed the same function

for early releases.

See Section 20.12, “Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based

on Skylake Microarchitecture.”

MSR_LASTBRANCH_1_FROM_IP

Last Branch Record 1

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 680H.

MSR_LASTBRANCH_2_FROM_IP

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-63. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

Last Branch Record 2

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 680H.

MSR_LASTBRANCH_3_FROM_IP

Last Branch Record 3

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 680H.

MSR_LASTBRANCH_4_FROM_IP

Last Branch Record 4

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 680H.

MSR_LASTBRANCH_5_FROM_IP

Last Branch Record 5

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 680H.

MSR_LASTBRANCH_6_FROM_IP

Last Branch Record 6

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 680H.

MSR_LASTBRANCH_7_FROM_IP

Last Branch Record 7

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 680H.

MSR_LASTBRANCH_8_FROM_IP

Last Branch Record 8

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 680H.

MSR_LASTBRANCH_9_FROM_IP

Last Branch Record 9

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 680H.

MSR_LASTBRANCH_10_FROM_IP

Last Branch Record 10

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 680H.

MSR_LASTBRANCH_11_FROM_IP

Last Branch Record 11

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 680H.

MSR_LASTBRANCH_12_FROM_IP

Last Branch Record 12

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 680H.

MSR_LASTBRANCH_13_FROM_IP

Last Branch Record 13

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 680H.

MSR_LASTBRANCH_14_FROM_IP

Last Branch Record 14

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 680H.

Vol. 4

2-551

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-63. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

MSR_LASTBRANCH_15_FROM_IP

Last Branch Record 15

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 680H.

MSR_LASTBRANCH_0_TO_IP

Last Branch Record 0 (R/W)

3, 4, 6

Unique

One of 16 pairs of last branch record registers on the last branch record stack (6C0H-6CFH). This part

of the stack contains pointers to the destination instruction for one of the last 16 branches,

exceptions, or interrupts that the processor took.

See Section 20.12, “Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based

on Skylake Microarchitecture.”

MSR_LASTBRANCH_1_TO_IP

Last Branch Record 1

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 6C0H.

MSR_LASTBRANCH_2_TO_IP

Last Branch Record 2

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 6C0H.

MSR_LASTBRANCH_3_TO_IP

Last Branch Record 3

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 6C0H.

MSR_LASTBRANCH_4_TO_IP

Last Branch Record 4

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 6C0H.

MSR_LASTBRANCH_5_TO_IP

Last Branch Record 5

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 6C0H.

MSR_LASTBRANCH_6_TO_IP

Last Branch Record 6

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 6C0H.

MSR_LASTBRANCH_7_TO_IP

Last Branch Record 7

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 6C0H.

MSR_LASTBRANCH_8_TO_IP

Last Branch Record 8

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 6C0H.

MSR_LASTBRANCH_9_TO_IP

Last Branch Record 9

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 6C0H.

MSR_LASTBRANCH_10_TO_IP

2-552 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-63. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

Last Branch Record 10

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 6C0H.

MSR_LASTBRANCH_11_TO_IP

Last Branch Record 11

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 6C0H.

MSR_LASTBRANCH_12_TO_IP

Last Branch Record 12

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 6C0H.

MSR_LASTBRANCH_13_TO_IP

Last Branch Record 13

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 6C0H.

MSR_LASTBRANCH_14_TO_IP

Last Branch Record 14

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 6C0H.

MSR_LASTBRANCH_15_TO_IP

Last Branch Record 15

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 6C0H.

IA32_EFER

Extended Feature Enables

3, 4, 6

Unique

See Table 2-2.

IA32_STAR

System Call Target Address (R/W)

3, 4, 6

Unique

See Table 2-2.

IA32_LSTAR

IA-32e Mode System Call Target Address (R/W)

3, 4, 6

Unique

See Table 2-2.

IA32_FMASK

System Call Flag Mask (R/W)

3, 4, 6

Unique

See Table 2-2.

IA32_FS_BASE

Map of BASE Address of FS (R/W)

3, 4, 6

Unique

See Table 2-2.

IA32_GS_BASE

Map of BASE Address of GS (R/W)

3, 4, 6

Unique

See Table 2-2.

IA32_KERNEL_GS_BASE

Swap Target of BASE Address of GS (R/W)

3, 4, 6

Unique

See Table 2-2.

Vol. 4

2-553

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-63. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

NOTES

1. For HT-enabled processors, there may be more than one logical processors per physical unit. If an MSR is Shared, this means that

one MSR is shared between logical processors. If an MSR is unique, this means that each logical processor has its own MSR.

2.19.1 MSRs Unique to Intel^® Xeon^® Processor MP with L3 Cache

The MSRs listed in Table 2-64 apply to Intel^® Xeon^® Processor MP with up to 8MB level three cache. These proces-

sors can be detected by enumerating the deterministic cache parameter leaf, CPUID.04H, to detect the presence of

the third level cache, and with CPUID reporting family encoding 0FH, model encoding 3 or 4 (see CPUID instruction

for more details).

Table 2-64. MSRs Unique to 64-bit Intel® Xeon® Processor MP with Up to an 8 MB L3 Cache

Model

Shared/

Availability

Unique

MSR_IFSB_BUSQ0

IFSB BUSQ Event Control and Counter Register (R/W)

3, 4

Shared

See Section 22.6.6, “Performance Monitoring on 64-bit Intel® Xeon® Processor MP with Up to 8-MByte

L3 Cache.”

MSR_IFSB_BUSQ1

IFSB BUSQ Event Control and Counter Register (R/W)

3, 4

Shared

MSR_IFSB_SNPQ0

IFSB SNPQ Event Control and Counter Register (R/W)

3, 4

Shared

See Section 22.6.6, “Performance Monitoring on 64-bit Intel® Xeon® Processor MP with Up to 8-MByte

L3 Cache.”

MSR_IFSB_SNPQ1

IFSB SNPQ Event Control and Counter Register (R/W)

3, 4

Shared

MSR_EFSB_DRDY0

EFSB DRDY Event Control and Counter Register (R/W)

3, 4

Shared

See Section 22.6.6, “Performance Monitoring on 64-bit Intel® Xeon® Processor MP with Up to 8-MByte

L3 Cache.”

MSR_EFSB_DRDY1

EFSB DRDY Event Control and Counter Register (R/W)

3, 4

Shared

MSR_IFSB_CTL6

IFSB Latency Event Control Register (R/W)

3, 4

Shared

See Section 22.6.6, “Performance Monitoring on 64-bit Intel® Xeon® Processor MP with Up to 8-MByte

L3 Cache.”

MSR_IFSB_CNTR7

IFSB Latency Event Counter Register (R/W)

3, 4

Shared

See Section 22.6.6, “Performance Monitoring on 64-bit Intel® Xeon® Processor MP with Up to 8-MByte

L3 Cache.”

The MSRs listed in Table 2-65 apply to Intel^® Xeon^® Processor 7100 series. These processors can be detected by

enumerating the deterministic cache parameter, CPUID.04H, to detect the presence of the third level cache, and

2-554 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

with CPUID reporting family encoding 0FH, model encoding 6 (See CPUID instruction for more details.). The perfor-

mance monitoring MSRs listed in Table 2-65 are shared between logical processors in the same core, but are repli-

cated for each core.

Table 2-65. MSRs Unique to Intel® Xeon® Processor 7100 Series

Model

Shared/

Availability

Unique

MSR_EMON_L3_CTR_CTL0

GBUSQ Event Control and Counter Register (R/W)

Shared

See Section 22.6.6, “Performance Monitoring on 64-bit Intel® Xeon® Processor MP with Up to 8-MByte L3

Cache.”

MSR_EMON_L3_CTR_CTL1

GBUSQ Event Control and Counter Register (R/W)

Shared

MSR_EMON_L3_CTR_CTL2

GSNPQ Event Control and Counter Register (R/W)

Shared

See Section 22.6.6, “Performance Monitoring on 64-bit Intel® Xeon® Processor MP with Up to 8-MByte L3

Cache.”

MSR_EMON_L3_CTR_CTL3

GSNPQ Event Control and Counter Register (R/W)

Shared

MSR_EMON_L3_CTR_CTL4

FSB Event Control and Counter Register (R/W)

Shared

See Section 22.6.6, “Performance Monitoring on 64-bit Intel® Xeon® Processor MP with Up to 8-MByte L3

Cache.”

MSR_EMON_L3_CTR_CTL5

FSB Event Control and Counter Register (R/W)

Shared

MSR_EMON_L3_CTR_CTL6

FSB Event Control and Counter Register (R/W)

Shared

MSR_EMON_L3_CTR_CTL7

FSB Event Control and Counter Register (R/W)

Shared

2.20

MSRS IN INTEL® CORE™ SOLO AND INTEL® CORE™ DUO PROCESSORS

Model-specific registers (MSRs) for Intel Core Solo, Intel Core Duo processors, and Dual-core Intel Xeon processor

LV are listed in Table 2-66. The column “Shared/Unique” applies to Intel Core Duo processor. “Unique” means each

processor core has a separate MSR, or a bit field in an MSR governs only a core independently. “Shared” means the

MSR or the bit field in an MSR address governs the operation of both processor cores.

Table 2-66. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV

Shared/

Bit Description

Unique

P5_MC_ADDR

See Section 2.23, “MSRs in Pentium Processors,” and Table 2-2.

Unique

P5_MC_TYPE

See Section 2.23, “MSRs in Pentium Processors,” and Table 2-2.

Unique

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-66. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)

Shared/

Bit Description

Unique

IA32_MONITOR_FILTER_SIZE

See Section 11.10.5, “Monitor/Mwait Address Range Determination,” and Table 2-2.

Unique

IA32_TIME_STAMP_COUNTER

See Section 20.17, “Time-Stamp Counter,” and Table 2-2.

Unique

IA32_PLATFORM_ID

Platform ID (R)

Shared

See Table 2-2. The operating system can use this MSR to determine “slot” information for the processor and the proper

microcode update to load.

IA32_APIC_BASE

See Section 13.4.4, “Local APIC Status and Location,” and Table 2-2.

Unique

MSR_EBL_CR_POWERON

Processor Hard Power-On Configuration (R/W)

Shared

Enables and disables processor features; (R) indicates current processor configuration.

Reserved.

Data Error Checking Enable (R/W)

1 = Enabled; 0 = Disabled.

Note: Not all processor implements R/W.

Response Error Checking Enable (R/W)

1 = Enabled; 0 = Disabled.

Note: Not all processor implements R/W.

MCERR# Drive Enable (R/W)

1 = Enabled; 0 = Disabled.

Note: Not all processor implements R/W.

Address Parity Enable (R/W)

1 = Enabled; 0 = Disabled.

Note: Not all processor implements R/W.

6: 5

Reserved.

BINIT# Driver Enable (R/W)

1 = Enabled; 0 = Disabled.

Note: Not all processor implements R/W.

Output Tri-state Enabled (R/O)

1 = Enabled; 0 = Disabled.

Execute BIST (R/O)

1 = Enabled; 0 = Disabled.

MCERR# Observation Enabled (R/O)

1 = Enabled; 0 = Disabled.

Reserved.

BINIT# Observation Enabled (R/O)

1 = Enabled; 0 = Disabled.

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-66. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)

Shared/

Bit Description

Unique

Reserved

1 MByte Power on Reset Vector (R/O)

1 = 1 MByte; 0 = 4 GBytes

Reserved.

17:16

APIC Cluster ID (R/O)

System Bus Frequency (R/O)

0 = 100 MHz.

1 = Reserved.

Reserved.

21: 20

Symmetric Arbitration ID (R/O)

26:22

Clock Frequency Ratio (R/O)

IA32_FEATURE_CONTROL

Control Features in IA-32 Processor (R/W)

Unique

See Table 2-2.

MSR_LASTBRANCH_0

Last Branch Record 0 (R/W)

Unique

One of 8 last branch record registers on the last branch record stack: bits 31-0 hold the ‘from’ address and bits 63-32

hold the ‘to’ address. See also:

• Last Branch Record Stack TOS at 1C9H.

• Section 20.15, “Last Branch, Interrupt, and Exception Recording (Pentium M Processors).”

MSR_LASTBRANCH_1

Last Branch Record 1 (R/W)

Unique

See description of MSR_LASTBRANCH_0.

MSR_LASTBRANCH_2

Last Branch Record 2 (R/W)

Unique

See description of MSR_LASTBRANCH_0.

MSR_LASTBRANCH_3

Last Branch Record 3 (R/W)

Unique

See description of MSR_LASTBRANCH_0.

MSR_LASTBRANCH_4

Last Branch Record 4 (R/W)

Unique

See description of MSR_LASTBRANCH_0.

MSR_LASTBRANCH_5

Last Branch Record 5 (R/W)

Unique

See description of MSR_LASTBRANCH_0.

MSR_LASTBRANCH_6

Last Branch Record 6 (R/W)

Unique

See description of MSR_LASTBRANCH_0.

MSR_LASTBRANCH_7

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-66. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)

Shared/

Bit Description

Unique

Last Branch Record 7 (R/W)

Unique

See description of MSR_LASTBRANCH_0.

IA32_BIOS_UPDT_TRIG

BIOS Update Trigger Register (W)

Unique

See Table 2-2.

IA32_BIOS_SIGN_ID

BIOS Update Signature ID (R/W)

Unique

See Table 2-2.

IA32_PMC0

Performance Counter Register

Unique

See Table 2-2.

IA32_PMC1

Performance Counter Register

Unique

See Table 2-2.

MSR_FSB_FREQ

Scaleable Bus Speed (R/O)

Shared

This field indicates the scalable bus clock speed.

2:0

•

101B: 100 MHz (FSB 400)

•

001B: 133 MHz (FSB 533)

•

011B: 167 MHz (FSB 667)

133.33 MHz should be utilized if performing calculation with System Bus Speed

when encoding is 101B.

166.67 MHz should be utilized if performing calculation with System Bus Speed

when encoding is 001B.

63:3

Reserved.

IA32_MPERF

Maximum Performance Frequency Clock Count (R/W)

Unique

See Table 2-2.

IA32_APERF

Actual Performance Frequency Clock Count (R/W)

Unique

See Table 2-2.

IA32_MTRRCAP

See Table 2-2.

Unique

MSR_BBL_CR_CTL3

Control Register 3

Shared

Used to configure the L2 Cache.

L2 Hardware Enabled (R/O)

1 = If the L2 is hardware-enabled.

0 = Indicates if the L2 is hardware-disabled.

2-558 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-66. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)

Shared/

Bit Description

Unique

7:1

Reserved.

L2 Enabled (R/W)

1 = L2 cache has been initialized.

0 = Disabled (default).

Until this bit is set the processor will not respond to the WBINVD instruction or

the assertion of the FLUSH# input.

22:9

Reserved.

L2 Not Present (R/O)

0 = L2 Present.

1 = L2 Not Present.

63:24

Reserved.

IA32_SYSENTER_CS

See Table 2-2.

Unique

IA32_SYSENTER_ESP

See Table 2-2.

Unique

IA32_SYSENTER_EIP

See Table 2-2.

Unique

IA32_MCG_CAP

See Table 2-2.

Unique

IA32_MCG_STATUS

Global Machine Check Status

Unique

RIPV

When set, this bit indicates that the instruction addressed by the instruction

pointer pushed on the stack (when the machine check was generated) can be

used to restart the program. If this bit is cleared, the program cannot be reliably

restarted.

EIPV

When set, this bit indicates that the instruction addressed by the instruction

pointer pushed on the stack (when the machine check was generated) is directly

associated with the error.

MCIP

When set, this bit indicates that a machine check has been generated. If a second

machine check is detected while this bit is still set, the processor enters a

shutdown state. Software should write this bit to 0 after processing a machine

check exception.

63:3

Reserved

IA32_PERFEVTSEL0

See Table 2-2.

Unique

IA32_PERFEVTSEL1

See Table 2-2.

Unique

IA32_PERF_STATUS

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-66. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)

Shared/

Bit Description

Unique

See Table 2-2.

Shared

IA32_PERF_CTL

See Table 2-2.

Unique

IA32_CLOCK_MODULATION

Clock Modulation (R/W)

Unique

See Table 2-2.

IA32_THERM_INTERRUPT

Thermal Interrupt Control (R/W)

Unique

See Table 2-2 and Section 17.8.2, “Thermal Monitor.”

IA32_THERM_STATUS

Thermal Monitor Status (R/W)

Unique

See Table 2-2 and Section 17.8.2, “Thermal Monitor”.

MSR_THERM2_CTL

Thermal Monitor 2 Control

Unique

15:0

Reserved.

TM_SELECT (R/W)

Mode of automatic thermal monitor:

0 = Thermal Monitor 1 (thermally-initiated on-die modulation of the stop-clock

duty cycle)

1 = Thermal Monitor 2 (thermally-initiated frequency transitions)

If bit 3 of the IA32_MISC_ENABLE register is cleared, TM_SELECT has no effect.

Neither TM1 nor TM2 will be enabled.

63:16

Reserved.

IA32_MISC_ENABLE

Enable Miscellaneous Processor Features (R/W)

Allows a variety of processor functions to be enabled and disabled.

2:0

Reserved.

Automatic Thermal Control Circuit Enable (R/W)

Unique

See Table 2-2.

6:4

Reserved.

Performance Monitoring Available (R)

Shared

See Table 2-2.

9:8

Reserved.

FERR# Multiplexing Enable (R/W)

Shared

1 = FERR# asserted by the processor to indicate a pending break event within

the processor

0 = Indicates compatible FERR# signaling behavior

This bit must be set to 1 to support XAPIC interrupt model usage.

Branch Trace Storage Unavailable (R/O)

Shared

See Table 2-2.

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-66. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)

Shared/

Bit Description

Unique

Reserved.

TM2 Enable (R/W)

Shared

When this bit is set (1) and the thermal sensor indicates that the die temperature

is at the pre-determined threshold, the Thermal Monitor 2 mechanism is

engaged. TM2 will reduce the bus to core ratio and voltage according to the value

last written to MSR_THERM2_CTL bits 15:0.

When this bit is clear (0, default), the processor does not change the VID signals

or the bus to core ratio when the processor enters a thermal managed state.

If the TM2 feature flag (ECX[8]) is not set to 1 after executing CPUID with EAX =

1, then this feature is not supported and BIOS must not alter the contents of this

bit location. The processor is operating out of spec if both this bit and the TM1

bit are set to disabled states.

15:14

Reserved.

Enhanced Intel SpeedStep Technology Enable (R/W)

Shared

1 = Enhanced Intel SpeedStep Technology enabled

ENABLE MONITOR FSM (R/W)

Shared

See Table 2-2.

Reserved.

Limit CPUID Maxval (R/W)

Shared

See Table 2-2.

Setting this bit may cause behavior in software that depends on the availability

of CPUID leaves greater than 2.

33:23

Reserved.

XD Bit Disable (R/W)

Shared

See Table 2-3.

63:35

Reserved.

MSR_LASTBRANCH_TOS

Last Branch Record Stack TOS (R/W)

Unique

Contains an index (bits 0-3) that points to the MSR containing the most recent branch record.

See MSR_LASTBRANCH_0_FROM_IP (at 40H).

IA32_DEBUGCTL

Debug Control (R/W)

Unique

Controls how several debug features are used. Bit definitions are discussed in Table 2-2.

MSR_LER_FROM_LIP

Last Exception Record From Linear IP (R)

Unique

Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was

generated or the last interrupt that was handled.

MSR_LER_TO_LIP

Last Exception Record To Linear IP (R)

Unique

This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last

exception that was generated or the last interrupt that was handled.

MTRRphysBase0

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-66. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)

Shared/

Bit Description

Unique

Memory Type Range Registers

Unique

MTRRphysMask0

Memory Type Range Registers

Unique

MTRRphysBase1

Memory Type Range Registers

Unique

MTRRphysMask1

Memory Type Range Registers

Unique

MTRRphysBase2

Memory Type Range Registers

Unique

MTRRphysMask2

Memory Type Range Registers

Unique

MTRRphysBase3

Memory Type Range Registers

Unique

MTRRphysMask3

Memory Type Range Registers

Unique

MTRRphysBase4

Memory Type Range Registers

Unique

MTRRphysMask4

Memory Type Range Registers

Unique

MTRRphysBase5

Memory Type Range Registers

Unique

MTRRphysMask5

Memory Type Range Registers

Unique

MTRRphysBase6

Memory Type Range Registers

Unique

MTRRphysMask6

Memory Type Range Registers

Unique

MTRRphysBase7

Memory Type Range Registers

Unique

MTRRphysMask7

Memory Type Range Registers

Unique

MTRRfix64K_00000

Memory Type Range Registers

Unique

MTRRfix16K_80000

Memory Type Range Registers

Unique

MTRRfix16K_A0000

Memory Type Range Registers

Unique

2-562 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-66. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)

Shared/

Bit Description

Unique

MTRRfix4K_C0000

Memory Type Range Registers

Unique

MTRRfix4K_C8000

Memory Type Range Registers

Unique

MTRRfix4K_D0000

Memory Type Range Registers

Unique

MTRRfix4K_D8000

Memory Type Range Registers

Unique

MTRRfix4K_E0000

Memory Type Range Registers

Unique

MTRRfix4K_E8000

Memory Type Range Registers

Unique

MTRRfix4K_F0000

Memory Type Range Registers

Unique

MTRRfix4K_F8000

Memory Type Range Registers

Unique

IA32_MTRR_DEF_TYPE

Default Memory Types (R/W)

Unique

See Table 2-2 and Section 14.11.2.1, “IA32_MTRR_DEF_TYPE MSR.”

IA32_MC0_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Unique

IA32_MC0_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

Unique

IA32_MC0_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

Unique

The IA32_MC0_ADDR register is either not implemented or contains no address if the ADDRV flag in the

IA32_MC0_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will

cause a general-protection exception.

IA32_MC1_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Unique

IA32_MC1_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

Unique

IA32_MC1_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

Unique

The IA32_MC1_ADDR register is either not implemented or contains no address if the ADDRV flag in the

IA32_MC1_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will

cause a general-protection exception.

IA32_MC2_CTL

Vol. 4

2-563

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-66. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)

Shared/

Bit Description

Unique

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Unique

IA32_MC2_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

Unique

IA32_MC2_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

Unique

The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in the

IA32_MC2_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will

cause a general-protection exception.

MSR_MC4_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

Unique

MSR_MC4_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

Unique

MSR_MC4_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

Unique

The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the

MSR_MC4_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause

a general-protection exception.

IA32_MC3_CTL

See Section 18.3.2.1, “IA32_MCi_CTL MSRs.”

IA32_MC3_STATUS

See Section 18.3.2.2, “IA32_MCi_STATUS MSRS.”

MSR_MC3_ADDR

See Section 18.3.2.3, “IA32_MCi_ADDR MSRs.”

Unique

The MSR_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in the

MSR_MC3_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause

a general-protection exception.

MSR_MC3_MISC

Machine Check Error Reporting Register - contains additional information describing the machine-check error if the

Unique

MISCV flag in the IA32_MCi_STATUS register is set.

MSR_MC5_CTL

Machine Check Error Reporting Register - controls signaling of #MC for errors produced by a particular hardware unit

Unique

(or group of hardware units).

MSR_MC5_STATUS

Machine Check Error Reporting Register - contains information related to a machine-check error if its VAL (valid) flag is

Unique

set. Software is responsible for clearing IA32_MCi_STATUS MSRs by explicitly writing 0s to them; writing 1s to them

causes a general-protection exception.

MSR_MC5_ADDR

Machine Check Error Reporting Register - contains the address of the code or data memory location that produced the

Unique

machine-check error if the ADDRV flag in the IA32_MCi_STATUS register is set.

MSR_MC5_MISC

2-564 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-66. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)

Shared/

Bit Description

Unique

Machine Check Error Reporting Register - contains additional information describing the machine-check error if the

Unique

MISCV flag in the IA32_MCi_STATUS register is set.

IA32_VMX_BASIC

Reporting Register of Basic VMX Capabilities (R/O)

Unique

See Table 2-2 and Appendix A.1, “Basic VMX Information.” (If CPUID.01H:ECX[5])

IA32_VMX_PINBASED_CTLS

Capability Reporting Register of Pin-Based VM-Execution Controls (R/O)

Unique

See Appendix A.3, “VM-Execution Controls.” (If CPUID.01H:ECX[5])

IA32_VMX_PROCBASED_CTLS

Capability Reporting Register of Primary Processor-Based VM-Execution Controls (R/O)

Unique

See Appendix A.3, “VM-Execution Controls.” (If CPUID.01H:ECX[5])

IA32_VMX_EXIT_CTLS

Capability Reporting Register of VM-Exit Controls (R/O)

Unique

See Appendix A.4, “VM-Exit Controls.” (If CPUID.01H:ECX[5])

IA32_VMX_ENTRY_CTLS

Capability Reporting Register of VM-Entry Controls (R/O)

Unique

See Appendix A.5, “VM-Entry Controls.” (If CPUID.01H:ECX[5])

IA32_VMX_MISC

Reporting Register of Miscellaneous VMX Capabilities (R/O)

Unique

See Appendix A.6, “Miscellaneous Data.” (If CPUID.01H:ECX[5])

IA32_VMX_CR0_FIXED0

Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)

Unique

See Appendix A.7, “VMX-Fixed Bits in CR0.” (If CPUID.01H:ECX[5])

IA32_VMX_CR0_FIXED1

Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)

Unique

See Appendix A.7, “VMX-Fixed Bits in CR0.” (If CPUID.01H:ECX[5])

IA32_VMX_CR4_FIXED0

Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)

Unique

See Appendix A.8, “VMX-Fixed Bits in CR4.” (If CPUID.01H:ECX[5])

IA32_VMX_CR4_FIXED1

Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)

Unique

See Appendix A.8, “VMX-Fixed Bits in CR4.” (If CPUID.01H:ECX[5])

IA32_VMX_VMCS_ENUM

Capability Reporting Register of VMCS Field Enumeration (R/O)

Unique

See Appendix A.9, “VMCS Enumeration.” (If CPUID.01H:ECX[5])

IA32_VMX_PROCBASED_CTLS2

Capability Reporting Register of Secondary Processor-Based VM-Execution Controls (R/O)

Unique

See Appendix A.3, “VM-Execution Controls.” (If CPUID.01H:ECX[5] and IA32_VMX_PROCBASED_CTLS[bit 63])

IA32_DS_AREA

Vol. 4

2-565

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-66. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)

Shared/

Bit Description

Unique

DS Save Area (R/W)

Unique

See Table 2-2 and Section 22.6.3.4, “Debug Store (DS) Mechanism.”

31:0

DS Buffer Management Area

Linear address of the first byte of the DS buffer management area.

63:32

Reserved.

IA32_EFER

See Table 2-2.

Unique

10:0

Reserved.

Execute Disable Bit Enable

63:12

Reserved.

2.21

MSRS IN THE PENTIUM M PROCESSOR

Model-specific registers (MSRs) for the Pentium M processor are similar to those described in Section 2.22 for P6

family processors. The following table describes new MSRs and MSRs whose behavior has changed on the Pentium

M processor.

Table 2-67. MSRs in Pentium M Processors

Bit Description

P5_MC_ADDR

See Section 2.23, “MSRs in Pentium Processors.”

P5_MC_TYPE

See Section 2.23, “MSRs in Pentium Processors.”

IA32_TIME_STAMP_COUNTER

See Section 20.17, “Time-Stamp Counter,” and see Table 2-2.

IA32_PLATFORM_ID

Platform ID (R)

See Table 2-2.

The operating system can use this MSR to determine “slot” information for the processor and the proper microcode update to load.

MSR_EBL_CR_POWERON

Processor Hard Power-On Configuration

(R/W) Enables and disables processor features.

(R) Indicates current processor configuration.

Reserved.

Data Error Checking Enable (R)

0 = Disabled.

Always 0 on the Pentium M processor.

2-566 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-67. MSRs in Pentium M Processors (Contd.)

Bit Description

Response Error Checking Enable (R)

0 = Disabled.

Always 0 on the Pentium M processor.

MCERR# Drive Enable (R)

0 = Disabled.

Always 0 on the Pentium M processor.

Address Parity Enable (R)

0 = Disabled.

Always 0 on the Pentium M processor.

6:5

Reserved.

BINIT# Driver Enable (R)

1 = Enabled; 0 = Disabled.

Always 0 on the Pentium M processor.

Output Tri-state Enabled (R/O)

1 = Enabled; 0 = Disabled.

Execute BIST (R/O)

1 = Enabled; 0 = Disabled.

MCERR# Observation Enabled (R/O)

1 = Enabled; 0 = Disabled.

Always 0 on the Pentium M processor.

Reserved.

BINIT# Observation Enabled (R/O)

1 = Enabled; 0 = Disabled.

Always 0 on the Pentium M processor.

Reserved.

1 MByte Power on Reset Vector (R/O)

1 = 1 MByte; 0 = 4 GBytes.

Always 0 on the Pentium M processor.

Reserved.

17:16

APIC Cluster ID (R/O)

Always 00B on the Pentium M processor.

System Bus Frequency (R/O)

0 = 100 MHz.

1 = Reserved.

Always 0 on the Pentium M processor.

Reserved.

21: 20

Symmetric Arbitration ID (R/O)

Always 00B on the Pentium M processor.

26:22

Clock Frequency Ratio (R/O)

MSR_LASTBRANCH_0

Vol. 4

2-567

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-67. MSRs in Pentium M Processors (Contd.)

Bit Description

Last Branch Record 0 (R/W)

One of 8 last branch record registers on the last branch record stack: bits 31-0 hold the ‘from’ address and bits 63-32 hold the to

address.

Intel 64 and IA-32 Architectures. Software Developer’s Manual (2026) - page 77