Intel 64 and IA-32 Architectures. Software Developer’s Manual (2026) - page 31
VBROADCASTF64X4 (EVEX.512 Encoded Version)
FOR j := 0 TO 7
i := j * 64
n := (j modulo 4) * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] := SRC[n+63:n]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VBROADCASTF32x2 __m512 _mm512_broadcast_f32x2( __m128 a);
VBROADCASTF32x2 __m512 _mm512_mask_broadcast_f32x2(__m512 s, __mmask16 k, __m128 a);
VBROADCASTF32x2 __m512 _mm512_maskz_broadcast_f32x2( __mmask16 k, __m128 a);
VBROADCASTF32x2 __m256 _mm256_broadcast_f32x2( __m128 a);
VBROADCASTF32x2 __m256 _mm256_mask_broadcast_f32x2(__m256 s, __mmask8 k, __m128 a);
VBROADCASTF32x2 __m256 _mm256_maskz_broadcast_f32x2( __mmask8 k, __m128 a);
VBROADCASTF32x4 __m512 _mm512_broadcast_f32x4( __m128 a);
VBROADCASTF32x4 __m512 _mm512_mask_broadcast_f32x4(__m512 s, __mmask16 k, __m128 a);
VBROADCASTF32x4 __m512 _mm512_maskz_broadcast_f32x4( __mmask16 k, __m128 a);
VBROADCASTF32x4 __m256 _mm256_broadcast_f32x4( __m128 a);
VBROADCASTF32x4 __m256 _mm256_mask_broadcast_f32x4(__m256 s, __mmask8 k, __m128 a);
VBROADCASTF32x4 __m256 _mm256_maskz_broadcast_f32x4( __mmask8 k, __m128 a);
VBROADCASTF32x8 __m512 _mm512_broadcast_f32x8( __m256 a);
VBROADCASTF32x8 __m512 _mm512_mask_broadcast_f32x8(__m512 s, __mmask16 k, __m256 a);
VBROADCASTF32x8 __m512 _mm512_maskz_broadcast_f32x8( __mmask16 k, __m256 a);
VBROADCASTF64x2 __m512d _mm512_broadcast_f64x2( __m128d a);
VBROADCASTF64x2 __m512d _mm512_mask_broadcast_f64x2(__m512d s, __mmask8 k, __m128d a);
VBROADCASTF64x2 __m512d _mm512_maskz_broadcast_f64x2( __mmask8 k, __m128d a);
VBROADCASTF64x2 __m256d _mm256_broadcast_f64x2( __m128d a);
VBROADCASTF64x2 __m256d _mm256_mask_broadcast_f64x2(__m256d s, __mmask8 k, __m128d a);
VBROADCASTF64x2 __m256d _mm256_maskz_broadcast_f64x2( __mmask8 k, __m128d a);
VBROADCASTF64x4 __m512d _mm512_broadcast_f64x4( __m256d a);
VBROADCASTF64x4 __m512d _mm512_mask_broadcast_f64x4(__m512d s, __mmask8 k, __m256d a);
VBROADCASTF64x4 __m512d _mm512_maskz_broadcast_f64x4( __mmask8 k, __m256d a);
VBROADCASTSD __m512d _mm512_broadcastsd_pd( __m128d a);
VBROADCASTSD __m512d _mm512_mask_broadcastsd_pd(__m512d s, __mmask8 k, __m128d a);
VBROADCASTSD __m512d _mm512_maskz_broadcastsd_pd(__mmask8 k, __m128d a);
VBROADCASTSD __m256d _mm256_broadcastsd_pd(__m128d a);
VBROADCASTSD __m256d _mm256_mask_broadcastsd_pd(__m256d s, __mmask8 k, __m128d a);
VBROADCASTSD __m256d _mm256_maskz_broadcastsd_pd( __mmask8 k, __m128d a);
VBROADCASTSD __m256d _mm256_broadcast_sd(double *a);
VBROADCASTSS __m512 _mm512_broadcastss_ps( __m128 a);
VBROADCASTSS __m512 _mm512_mask_broadcastss_ps(__m512 s, __mmask16 k, __m128 a);
VBROADCASTSS __m512 _mm512_maskz_broadcastss_ps( __mmask16 k, __m128 a);
VBROADCASTSS __m256 _mm256_broadcastss_ps(__m128 a);
VBROADCASTSS __m256 _mm256_mask_broadcastss_ps(__m256 s, __mmask8 k, __m128 a);
VBROADCASTSS __m256 _mm256_maskz_broadcastss_ps( __mmask8 k, __m128 a);
VBROADCAST-Load with Broadcast Floating-Point Data
Vol. 2C
5-18
VBROADCASTSS __m128 _mm_broadcastss_ps(__m128 a);
VBROADCASTSS __m128 _mm_mask_broadcastss_ps(__m128 s, __mmask8 k, __m128 a);
VBROADCASTSS __m128 _mm_maskz_broadcastss_ps( __mmask8 k, __m128 a);
VBROADCASTSS __m128 _mm_broadcast_ss(float *a);
VBROADCASTSS __m256 _mm256_broadcast_ss(float *a);
VBROADCASTF128 __m256 _mm256_broadcast_ps(__m128 * a);
VBROADCASTF128 __m256d _mm256_broadcast_pd(__m128d * a);
Exceptions
VEX-encoded instructions, see Table 2-23, “Type 6 Class Exception Conditions.”
EVEX-encoded instructions, see Table 2-55, “Type E6 Class Exception Conditions.”
Additionally:
#UD
If VEX.L = 0 for VBROADCASTSD or VBROADCASTF128.
If EVEX.L’L = 0 for VBROADCASTSD/VBROADCASTF32X2/VBROADCASTF32X4/VBROAD-
CASTF64X2.
If EVEX.L’L < 10b for VBROADCASTF32X8/VBROADCASTF64X4.
VBROADCAST-Load with Broadcast Floating-Point Data
Vol. 2C
5-19
VCMPPH-Compare Packed FP16 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.NP.0F3A.W0 C2 /r /ib
A
V/V
(AVX512_FP16
Compare packed FP16 values in
VCMPPH k1{k2}, xmm2,
AND AVX512VL)
xmm3/m128/m16bcst and xmm2 using bits 4:0 of
xmm3/m128/m16bcst, imm8
OR AVX10.1
imm8 as a comparison predicate subject to
writemask k2, and store the result in mask
register k1.
EVEX.256.NP.0F3A.W0 C2 /r /ib
A
V/V
(AVX512_FP16
Compare packed FP16 values in
VCMPPH k1{k2}, ymm2,
AND AVX512VL)
ymm3/m256/m16bcst and ymm2 using bits 4:0 of
ymm3/m256/m16bcst, imm8
OR AVX10.1
imm8 as a comparison predicate subject to
writemask k2, and store the result in mask
register k1.
EVEX.512.NP.0F3A.W0 C2 /r /ib
A
V/V
AVX512_FP16
Compare packed FP16 values in
VCMPPH k1{k2}, zmm2,
OR AVX10.1
zmm3/m512/m16bcst and zmm2 using bits 4:0 of
zmm3/m512/m16bcst {sae}, imm8
imm8 as a comparison predicate subject to
writemask k2, and store the result in mask
register k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
imm8 (r)
Description
This instruction compares packed FP16 values from source operands and stores the result in the destination mask
operand. The comparison predicate operand (immediate byte bits 4:0) specifies the type of comparison performed
on each of the pairs of packed values. The destination elements are updated according to the writemask.
Operation
CASE (imm8 & 0x1F) OF
0: CMP_OPERATOR := EQ_OQ;
1: CMP_OPERATOR := LT_OS;
2: CMP_OPERATOR := LE_OS;
3: CMP_OPERATOR := UNORD_Q;
4: CMP_OPERATOR := NEQ_UQ;
5: CMP_OPERATOR := NLT_US;
6: CMP_OPERATOR := NLE_US;
7: CMP_OPERATOR := ORD_Q;
8: CMP_OPERATOR := EQ_UQ;
9: CMP_OPERATOR := NGE_US;
10: CMP_OPERATOR := NGT_US;
11: CMP_OPERATOR := FALSE_OQ;
12: CMP_OPERATOR := NEQ_OQ;
13: CMP_OPERATOR := GE_OS;
14: CMP_OPERATOR := GT_OS;
15: CMP_OPERATOR := TRUE_UQ;
16: CMP_OPERATOR := EQ_OS;
17: CMP_OPERATOR := LT_OQ;
18: CMP_OPERATOR := LE_OQ;
19: CMP_OPERATOR := UNORD_S;
20: CMP_OPERATOR := NEQ_US;
VCMPPH-Compare Packed FP16 Values
Vol. 2C
5-20
21: CMP_OPERATOR := NLT_UQ;
22: CMP_OPERATOR := NLE_UQ;
23: CMP_OPERATOR := ORD_S;
24: CMP_OPERATOR := EQ_US;
25: CMP_OPERATOR := NGE_UQ;
26: CMP_OPERATOR := NGT_UQ;
27: CMP_OPERATOR := FALSE_OS;
28: CMP_OPERATOR := NEQ_OS;
29: CMP_OPERATOR := GE_OQ;
30: CMP_OPERATOR := GT_OQ;
31: CMP_OPERATOR := TRUE_US;
ESAC
VCMPPH (EVEX Encoded Versions)
VL = 128, 256 or 512
KL := VL/16
FOR j := 0 TO KL-1:
IF k2[j] OR *no writemask*:
IF EVEX.b = 1:
tsrc2 := SRC2.fp16[0]
ELSE:
tsrc2 := SRC2.fp16[j]
DEST.bit[j] := SRC1.fp16[j] CMP_OPERATOR tsrc2
ELSE
DEST.bit[j] := 0
DEST[MAXKL-1:KL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCMPPH
___mmask8 _mm_cmp_ph_mask (__m128h a, __m128h b, const int imm8);
VCMPPH
___mmask8 _mm_mask_cmp_ph_mask (__mmask8 k1, __m128h a, __m128h b, const int imm8);
VCMPPH
___mmask16 _mm256_cmp_ph_mask (__m256h a, __m256h b, const int imm8);
VCMPPH
___mmask16 _mm256_mask_cmp_ph_mask (__mmask16 k1, __m256h a, __m256h b, const int imm8);
VCMPPH
___mmask32 _mm512_cmp_ph_mask (__m512h a, __m512h b, const int imm8);
VCMPPH
___mmask32 _mm512_mask_cmp_ph_mask (__mmask32 k1, __m512h a, __m512h b, const int imm8);
VCMPPH
___mmask32 _mm512_cmp_round_ph_mask (__m512h a, __m512h b, const int imm8, const int sae);
VCMPPH
___mmask32 _mm512_mask_cmp_round_ph_mask (__mmask32 k1, __m512h a, __m512h b, const int imm8, const int sae);
SIMD Floating-Point Exceptions
Invalid, Denormal.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
VCMPPH-Compare Packed FP16 Values
Vol. 2C
5-21
VCMPSH-Compare Scalar FP16 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.LLIG.F3.0F3A.W0 C2 /r /ib
A
V/V
AVX512_FP16
Compare low FP16 values in xmm3/m16 and
VCMPSH k1{k2}, xmm2, xmm3/m16
OR AVX10.1
xmm2 using bits 4:0 of imm8 as a comparison
{sae}, imm8
predicate subject to writemask k2, and store the
result in mask register k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
imm8 (r)
Description
This instruction compares the FP16 values from the lowest element of the source operands and stores the result in
the destination mask operand. The comparison predicate operand (immediate byte bits 4:0) specifies the type of
comparison performed on the pair of packed FP16 values. The low destination bit is updated according to the write-
mask. Bits MAXKL-1:1 of the destination operand are zeroed.
Operation
CASE (imm8 & 0x1F) OF
0: CMP_OPERATOR := EQ_OQ;
1: CMP_OPERATOR := LT_OS;
2: CMP_OPERATOR := LE_OS;
3: CMP_OPERATOR := UNORD_Q;
4: CMP_OPERATOR := NEQ_UQ;
5: CMP_OPERATOR := NLT_US;
6: CMP_OPERATOR := NLE_US;
7: CMP_OPERATOR := ORD_Q;
8: CMP_OPERATOR := EQ_UQ;
9: CMP_OPERATOR := NGE_US;
10: CMP_OPERATOR := NGT_US;
11: CMP_OPERATOR := FALSE_OQ;
12: CMP_OPERATOR := NEQ_OQ;
13: CMP_OPERATOR := GE_OS;
14: CMP_OPERATOR := GT_OS;
15: CMP_OPERATOR := TRUE_UQ;
16: CMP_OPERATOR := EQ_OS;
17: CMP_OPERATOR := LT_OQ;
18: CMP_OPERATOR := LE_OQ;
19: CMP_OPERATOR := UNORD_S;
20: CMP_OPERATOR := NEQ_US;
21: CMP_OPERATOR := NLT_UQ;
22: CMP_OPERATOR := NLE_UQ;
23: CMP_OPERATOR := ORD_S;
24: CMP_OPERATOR := EQ_US;
25: CMP_OPERATOR := NGE_UQ;
26: CMP_OPERATOR := NGT_UQ;
27: CMP_OPERATOR := FALSE_OS;
28: CMP_OPERATOR := NEQ_OS;
29: CMP_OPERATOR := GE_OQ;
30: CMP_OPERATOR := GT_OQ;
VCMPSH-Compare Scalar FP16 Values
Vol. 2C
5-22
31: CMP_OPERATOR := TRUE_US;
ESAC
VCMPSH (EVEX Encoded Versions)
IF k2[0] OR *no writemask*:
DEST.bit[0] := SRC1.fp16[0] CMP_OPERATOR SRC2.fp16[0]
ELSE
DEST.bit[0] := 0
DEST[MAXKL-1:1] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCMPSH __mmask8 _mm_cmp_round_sh_mask (__m128h a, __m128h b, const int imm8, const int sae);
VCMPSH __mmask8 _mm_mask_cmp_round_sh_mask (__mmask8 k1, __m128h a, __m128h b, const int imm8, const int sae);
VCMPSH __mmask8 _mm_cmp_sh_mask (__m128h a, __m128h b, const int imm8);
VCMPSH __mmask8 _mm_mask_cmp_sh_mask (__mmask8 k1, __m128h a, __m128h b, const int imm8);
SIMD Floating-Point Exceptions
Invalid, Denormal.
Other Exceptions
EVEX-encoded instructions, see Table 2-49, “Type E3 Class Exception Conditions.”
VCMPSH-Compare Scalar FP16 Values
Vol. 2C
5-23
VCOMISH-Compare Scalar Ordered FP16 Values and Set EFLAGS
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.LLIG.NP.MAP5.W0 2F /r
A
V/V
AVX512_FP16
Compare low FP16 values in xmm1 and
VCOMISH xmm1, xmm2/m16 {sae}
OR AVX10.1
xmm2/m16, and set the EFLAGS flags accordingly.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (r)
ModRM:r/m (r)
N/A
N/A
Description
This instruction compares the FP16 values in the low word of operand 1 (first operand) and operand 2 (second
operand), and sets the ZF, PF, and CF flags in the EFLAGS register according to the result (unordered, greater than,
less than, or equal). The OF, SF and AF flags in the EFLAGS register are set to 0. The unordered result is returned
if either source operand is a NaN (QNaN or SNaN).
Operand 1 is an XMM register; operand 2 can be an XMM register or a 16-bit memory location.
The VCOMISH instruction differs from the VUCOMISH instruction in that it signals a SIMD floating-point invalid oper-
ation exception (#I) when a source operand is either a QNaN or SNaN. The VUCOMISH instruction signals an invalid
numeric exception only if a source operand is an SNaN.
The EFLAGS register is not updated if an unmasked SIMD floating-point exception is generated. EVEX.vvvv is
reserved and must be 1111b, otherwise instructions will #UD.
Operation
VCOMISH SRC1, SRC2
RESULT := OrderedCompare(SRC1.fp16[0],SRC2.fp16[0])
IF RESULT is UNORDERED:
ZF, PF, CF := 1, 1, 1
ELSE IF RESULT is GREATER_THAN:
ZF, PF, CF := 0, 0, 0
ELSE IF RESULT is LESS_THAN:
ZF, PF, CF := 0, 0, 1
ELSE: // RESULT is EQUALS
ZF, PF, CF := 1, 0, 0
OF, AF, SF := 0, 0, 0
Intel C/C++ Compiler Intrinsic Equivalent
VCOMISH int _mm_comi_round_sh (__m128h a, __m128h b, const int imm8, const int sae);
VCOMISH int _mm_comi_sh (__m128h a, __m128h b, const int imm8);
VCOMISH int _mm_comieq_sh (__m128h a, __m128h b);
VCOMISH int _mm_comige_sh (__m128h a, __m128h b);
VCOMISH int _mm_comigt_sh (__m128h a, __m128h b);
VCOMISH int _mm_comile_sh (__m128h a, __m128h b);
VCOMISH int _mm_comilt_sh (__m128h a, __m128h b);
VCOMISH int _mm_comineq_sh (__m128h a, __m128h b);
SIMD Floating-Point Exceptions
Invalid, Denormal.
VCOMISH-Compare Scalar Ordered FP16 Values and Set EFLAGS
Vol. 2C
5-24
Other Exceptions
EVEX-encoded instructions, see Table 2-50, “Type E3NF Class Exception Conditions.”
VCOMISH-Compare Scalar Ordered FP16 Values and Set EFLAGS
Vol. 2C
5-25
VCOMPRESSPD-Store Sparse Packed Double Precision Floating-Point Values Into Dense
Memory
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.66.0F38.W1 8A /r
A
V/V
(AVX512VL AND
Compress packed double precision floating-
VCOMPRESSPD xmm1/m128 {k1}{z},
AVX512F) OR
point values from xmm2 to xmm1/m128 using
xmm2
AVX10.1
writemask k1.
EVEX.256.66.0F38.W1 8A /r
A
V/V
(AVX512VL AND
Compress packed double precision floating-
VCOMPRESSPD ymm1/m256 {k1}{z},
AVX512F) OR
point values from ymm2 to ymm1/m256 using
ymm2
AVX10.1
writemask k1.
EVEX.512.66.0F38.W1 8A /r
A
V/V
AVX512F
Compress packed double precision floating-
VCOMPRESSPD zmm1/m512 {k1}{z},
OR AVX10.1
point values from zmm2 using control mask k1
zmm2
to zmm1/m512.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Scalar
ModRM:r/m (w)
ModRM:reg (r)
N/A
N/A
Description
Compress (store) up to 8 double precision floating-point values from the source operand (the second operand) as
a contiguous vector to the destination operand (the first operand) The source operand is a ZMM/YMM/XMM register,
the destination operand can be a ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The opmask register k1 selects the active elements (partial vector or possibly non-contiguous if less than 8 active
elements) from the source operand to compress into a contiguous vector. The contiguous vector is written to the
destination starting from the low element of the destination operand.
Memory destination version: Only the contiguous vector is written to the destination memory location. EVEX.z
must be zero.
Register destination version: If the vector length of the contiguous vector is less than that of the input vector in the
source operand, the upper bits of the destination register are unmodified if EVEX.z is not set, otherwise the upper
bits are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element
instead of the size of the full vector.
VCOMPRESSPD-Store Sparse Packed Double Precision Floating-Point Values Into Dense Memory
Vol. 2C
5-26
Operation
VCOMPRESSPD (EVEX Encoded Versions) Store Form
(KL, VL) = (2, 128), (4, 256), (8, 512)
SIZE := 64
k := 0
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN
DEST[k+SIZE-1:k] := SRC[i+63:i]
k := k + SIZE
FI;
ENDFOR
VCOMPRESSPD (EVEX Encoded Versions) Reg-Reg Form
(KL, VL) = (2, 128), (4, 256), (8, 512)
SIZE := 64
k := 0
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN
DEST[k+SIZE-1:k] := SRC[i+63:i]
k := k + SIZE
FI;
ENDFOR
IF *merging-masking*
THEN *DEST[VL-1:k] remains unchanged*
ELSE DEST[VL-1:k] := 0
FI
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCOMPRESSPD __m512d _mm512_mask_compress_pd( __m512d s, __mmask8 k, __m512d a);
VCOMPRESSPD __m512d _mm512_maskz_compress_pd( __mmask8 k, __m512d a);
VCOMPRESSPD void _mm512_mask_compressstoreu_pd( void * d, __mmask8 k, __m512d a);
VCOMPRESSPD __m256d _mm256_mask_compress_pd( __m256d s, __mmask8 k, __m256d a);
VCOMPRESSPD __m256d _mm256_maskz_compress_pd( __mmask8 k, __m256d a);
VCOMPRESSPD void _mm256_mask_compressstoreu_pd( void * d, __mmask8 k, __m256d a);
VCOMPRESSPD __m128d _mm_mask_compress_pd( __m128d s, __mmask8 k, __m128d a);
VCOMPRESSPD __m128d _mm_maskz_compress_pd( __mmask8 k, __m128d a);
VCOMPRESSPD void _mm_mask_compressstoreu_pd( void * d, __mmask8 k, __m128d a);
SIMD Floating-Point Exceptions
None.
Other Exceptions
EVEX-encoded instructions, see Exceptions Type E4.nb in Table 2-51, “Type E4 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VCOMPRESSPD-Store Sparse Packed Double Precision Floating-Point Values Into Dense Memory
Vol. 2C
5-27
VCOMPRESSPS-Store Sparse Packed Single Precision Floating-Point Values Into Dense Memory
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.66.0F38.W0 8A /r
A
V/V
(AVX512VL AND
Compress packed single precision floating-
VCOMPRESSPS xmm1/m128 {k1}{z},
AVX512F) OR
point values from xmm2 to xmm1/m128 using
xmm2
AVX10.1
writemask k1.
EVEX.256.66.0F38.W0 8A /r
A
V/V
(AVX512VL AND
Compress packed single precision floating-
VCOMPRESSPS ymm1/m256 {k1}{z},
AVX512F) OR
point values from ymm2 to ymm1/m256 using
ymm2
AVX10.1
writemask k1.
EVEX.512.66.0F38.W0 8A /r
A
V/V
AVX512F
Compress packed single precision floating-
VCOMPRESSPS zmm1/m512 {k1}{z},
OR AVX10.1
point values from zmm2 using control mask k1
zmm2
to zmm1/m512.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Scalar
ModRM:r/m (w)
ModRM:reg (r)
N/A
N/A
Description
Compress (stores) up to 16 single precision floating-point values from the source operand (the second operand) to
the destination operand (the first operand). The source operand is a ZMM/YMM/XMM register, the destination
operand can be a ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The opmask register k1 selects the active elements (a partial vector or possibly non-contiguous if less than 16
active elements) from the source operand to compress into a contiguous vector. The contiguous vector is written to
the destination starting from the low element of the destination operand.
Memory destination version: Only the contiguous vector is written to the destination memory location. EVEX.z
must be zero.
Register destination version: If the vector length of the contiguous vector is less than that of the input vector in the
source operand, the upper bits of the destination register are unmodified if EVEX.z is not set, otherwise the upper
bits are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element
instead of the size of the full vector.
VCOMPRESSPS-Store Sparse Packed Single Precision Floating-Point Values Into Dense Memory
Vol. 2C
5-28
Operation
VCOMPRESSPS (EVEX Encoded Versions) Store Form
(KL, VL) = (4, 128), (8, 256), (16, 512)
SIZE := 32
k := 0
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN
DEST[k+SIZE-1:k] := SRC[i+31:i]
k := k + SIZE
FI;
ENDFOR;
VCOMPRESSPS (EVEX Encoded Versions) Reg-Reg Form
(KL, VL) = (4, 128), (8, 256), (16, 512)
SIZE := 32
k := 0
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN
DEST[k+SIZE-1:k] := SRC[i+31:i]
k := k + SIZE
FI;
ENDFOR
IF *merging-masking*
THEN *DEST[VL-1:k] remains unchanged*
ELSE DEST[VL-1:k] := 0
FI
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCOMPRESSPS __m512 _mm512_mask_compress_ps( __m512 s, __mmask16 k, __m512 a);
VCOMPRESSPS __m512 _mm512_maskz_compress_ps( __mmask16 k, __m512 a);
VCOMPRESSPS void _mm512_mask_compressstoreu_ps( void * d, __mmask16 k, __m512 a);
VCOMPRESSPS __m256 _mm256_mask_compress_ps( __m256 s, __mmask8 k, __m256 a);
VCOMPRESSPS __m256 _mm256_maskz_compress_ps( __mmask8 k, __m256 a);
VCOMPRESSPS void _mm256_mask_compressstoreu_ps( void * d, __mmask8 k, __m256 a);
VCOMPRESSPS __m128 _mm_mask_compress_ps( __m128 s, __mmask8 k, __m128 a);
VCOMPRESSPS __m128 _mm_maskz_compress_ps( __mmask8 k, __m128 a);
VCOMPRESSPS void _mm_mask_compressstoreu_ps( void * d, __mmask8 k, __m128 a);
SIMD Floating-Point Exceptions
None.
Other Exceptions
EVEX-encoded instructions, see Exceptions Type E4.nb. in Table 2-51, “Type E4 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VCOMPRESSPS-Store Sparse Packed Single Precision Floating-Point Values Into Dense Memory
Vol. 2C
5-29
VCVTDQ2PH-Convert Packed Signed Doubleword Integers to Packed FP16 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.NP.MAP5.W0 5B /r
A
V/V
(AVX512_FP16
Convert four packed signed doubleword integers
VCVTDQ2PH xmm1{k1}{z},
AND AVX512VL)
from xmm2/m128/m32bcst to four packed FP16
xmm2/m128/m32bcst
OR AVX10.1
values, and store the result in xmm1 subject to
writemask k1.
EVEX.256.NP.MAP5.W0 5B /r
A
V/V
(AVX512_FP16
Convert eight packed signed doubleword integers
VCVTDQ2PH xmm1{k1}{z},
AND AVX512VL)
from ymm2/m256/m32bcst to eight packed
ymm2/m256/m32bcst
OR AVX10.1
FP16 values, and store the result in xmm1
subject to writemask k1.
EVEX.512.NP.MAP5.W0 5B /r
A
V/V
AVX512_FP16
Convert sixteen packed signed doubleword
VCVTDQ2PH ymm1{k1}{z},
OR AVX10.1
integers from zmm2/m512/m32bcst to sixteen
zmm2/m512/m32bcst {er}
packed FP16 values, and store the result in
ymm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts four, eight, or sixteen packed signed doubleword integers in the source operand to four,
eight, or sixteen packed FP16 values in the destination operand.
EVEX encoded versions: The source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-
tion or a 512/256/128-bit vector broadcast from a 32-bit memory location. The destination operand is a YMM/XMM
register conditionally updated with writemask k1.
EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
If the result of the convert operation is overflow and MXCSR.OM=0 then a SIMD exception will be raised with OE=1,
PE=1.
VCVTDQ2PH-Convert Packed Signed Doubleword Integers to Packed FP16 Values
Vol. 2C
5-30
Operation
VCVTDQ2PH DEST, SRC
VL = 128, 256 or 512
KL := VL / 32
IF *SRC is a register* and (VL = 512) AND (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.dword[0]
ELSE
tsrc := SRC.dword[j]
DEST.fp16[j] := Convert_integer32_to_fp16(tsrc)
ELSE IF *zeroing*:
DEST.fp16[j] := 0
// else dest.fp16[j] remains unchanged
DEST[MAXVL-1:VL/2] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTDQ2PH __m256h _mm512_cvt_roundepi32_ph (__m512i a, int rounding);
VCVTDQ2PH __m256h _mm512_mask_cvt_roundepi32_ph (__m256h src, __mmask16 k, __m512i a, int rounding);
VCVTDQ2PH __m256h _mm512_maskz_cvt_roundepi32_ph (__mmask16 k, __m512i a, int rounding);
VCVTDQ2PH __m128h _mm_cvtepi32_ph (__m128i a);
VCVTDQ2PH __m128h _mm_mask_cvtepi32_ph (__m128h src, __mmask8 k, __m128i a);
VCVTDQ2PH __m128h _mm_maskz_cvtepi32_ph (__mmask8 k, __m128i a);
VCVTDQ2PH __m128h _mm256_cvtepi32_ph (__m256i a);
VCVTDQ2PH __m128h _mm256_mask_cvtepi32_ph (__m128h src, __mmask8 k, __m256i a);
VCVTDQ2PH __m128h _mm256_maskz_cvtepi32_ph (__mmask8 k, __m256i a);
VCVTDQ2PH __m256h _mm512_cvtepi32_ph (__m512i a);
VCVTDQ2PH __m256h _mm512_mask_cvtepi32_ph (__m256h src, __mmask16 k, __m512i a);
VCVTDQ2PH __m256h _mm512_maskz_cvtepi32_ph (__mmask16 k, __m512i a);
SIMD Floating-Point Exceptions
Overflow, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
VCVTDQ2PH-Convert Packed Signed Doubleword Integers to Packed FP16 Values
Vol. 2C
5-31
VCVTNE2PS2BF16-Convert Two Packed Single Data to One Packed BF16 Data
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.F2.0F38.W0 72 /r
A
V/V
(AVX512_BF16
Convert packed single data from xmm2 and
VCVTNE2PS2BF16 xmm1{k1}{z},
AND AVX512VL)
xmm3/m128/m32bcst to packed BF16 data in
xmm2, xmm3/m128/m32bcst
OR AVX10.1
xmm1 with writemask k1.
EVEX.256.F2.0F38.W0 72 /r
A
V/V
(AVX512_BF16
Convert packed single data from ymm2 and
VCVTNE2PS2BF16 ymm1{k1}{z},
AND AVX512VL)
ymm3/m256/m32bcst to packed BF16 data in
ymm2, ymm3/m256/m32bcst
OR AVX10.1
ymm1 with writemask k1.
EVEX.512.F2.0F38.W0 72 /r
A
V/V
(AVX512_BF16
Convert packed single data from zmm2 and
VCVTNE2PS2BF16 zmm1{k1}{z},
AND AVX512F)
zmm3/m512/m32bcst to packed BF16 data in
zmm2, zmm3/m512/m32bcst
OR AVX10.1
zmm1 with writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Converts two SIMD registers of packed single data into a single register of packed BF16 data.
This instruction does not support memory fault suppression.
This instruction uses “Round to nearest (even)” rounding mode. Output denormals are always flushed to zero and
input denormals are always treated as zero. MXCSR is not consulted nor updated. No floating-point exceptions are
generated.
Operation
VCVTNE2PS2BF16 dest, src1, src2
VL = (128, 256, 512)
KL = VL/16
origdest := dest
FOR i := 0 to KL-1:
IF k1[ i ] or *no writemask*:
IF i < KL/2:
IF src2 is memory and evex.b == 1:
t := src2.fp32[0]
ELSE:
t := src2.fp32[ i ]
ELSE:
t := src1.fp32[ i-KL/2]
// See VCVTNEPS2BF16 for definition of convert helper function
dest.word[i] := convert_fp32_to_bfloat16(t)
ELSE IF *zeroing*:
dest.word[ i ] := 0
ELSE: // Merge masking, dest element unchanged
dest.word[ i ] := origdest.word[ i ]
DEST[MAXVL-1:VL] := 0
VCVTNE2PS2BF16-Convert Two Packed Single Data to One Packed BF16 Data
Vol. 2C
5-32
Intel C/C++ Compiler Intrinsic Equivalent
VCVTNE2PS2BF16 __m128bh _mm_cvtne2ps_pbh (__m128, __m128);
VCVTNE2PS2BF16 __m128bh _mm_mask_cvtne2ps_pbh (__m128bh, __mmask8, __m128, __m128);
VCVTNE2PS2BF16 __m128bh _mm_maskz_cvtne2ps_pbh (__mmask8, __m128, __m128);
VCVTNE2PS2BF16 __m256bh _mm256_cvtne2ps_pbh (__m256, __m256);
VCVTNE2PS2BF16 __m256bh _mm256_mask_cvtne2ps_pbh (__m256bh, __mmask16, __m256, __m256);
VCVTNE2PS2BF16 __m256bh _mm256_maskz_cvtne2ps_ pbh (__mmask16, __m256, __m256);
VCVTNE2PS2BF16 __m512bh _mm512_cvtne2ps_pbh (__m512, __m512);
VCVTNE2PS2BF16 __m512bh _mm512_mask_cvtne2ps_pbh (__m512bh, __mmask32, __m512, __m512);
VCVTNE2PS2BF16 __m512bh _mm512_maskz_cvtne2ps_pbh (__mmask32, __m512, __m512);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-52, “Type E4NF Class Exception Conditions.”
VCVTNE2PS2BF16-Convert Two Packed Single Data to One Packed BF16 Data
Vol. 2C
5-33
VCVTNEEBF162PS-Convert Even Elements of Packed BF16 Values to FP32 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
VEX.128.F3.0F38.W0 B0 !(11):rrr:bbb
A
V/V
AVX_NE_
Convert even elements of packed BF16
CONVERT
values from m128 to FP32 values and store
VCVTNEEBF162PS xmm1, m128
in xmm1.
VEX.256.F3.0F38.W0 B0 !(11):rrr:bbb
A
V/V
AVX_NE_
Convert even elements of packed BF16
CONVERT
values from m256 to FP32 values and store
VCVTNEEBF162PS ymm1, m256
in ymm1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction loads packed BF16 elements from memory, converts the even elements to FP32, and writes the
result to the destination SIMD register.
This instruction does not generate floating-point exceptions and does not consult or update MXCSR.
Since any BF16 number can be represented in FP32, the conversion result is exact and no rounding is needed.
Operation
VCVTNEEBF162PS dest, src (VEX encoded version)
VL = (128, 256)
KL = VL/32
FOR i in range(0, KL):
dest.dword[i] = make_fp32(src.dword[i].word[0])
DEST[MAXVL-1:VL] := 0
Flags Affected
None.
Intel C/C++ Compiler Intrinsic Equivalent
VCVTNEEBF162PS __m128 _mm_cvtneebf16_ps (const __m128bh* __A);
VCVTNEEBF162PS __m256 _mm256_cvtneebf16_ps (const __m256bh* __A);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-21, “Type 4 Class Exception Conditions.”
VCVTNEEBF162PS-Convert Even Elements of Packed BF16 Values to FP32 Values
Vol. 2C
5-34
VCVTNEEPH2PS-Convert Even Elements of Packed FP16 Values to FP32 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
VEX.128.66.0F38.W0 B0 !(11):rrr:bbb
A
V/V
AVX_NE_
Convert even elements of packed FP16
CONVERT
values from m128 to FP32 values and store
VCVTNEEPH2PS xmm1, m128
in xmm1.
VEX.256.66.0F38.W0 B0 !(11):rrr:bbb
A
V/V
AVX_NE_
Convert even elements of packed FP16
CONVERT
values from m256 to FP32 values and store
VCVTNEEPH2PS ymm1, m256
in ymm1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction loads packed FP16 elements from memory, converts the even elements to FP32, and writes the
result to the destination SIMD register.
This instruction does not generate floating-point exceptions and does not consult or update MXCSR.
Input FP16 denormals are converted to normal FP32 numbers and not treated as zero. Since any FP16 number can
be represented in FP32, the conversion result is exact and no rounding is needed.
Operation
VCVTNEEPH2PS dest, src (VEX encoded version)
VL = (128, 256)
KL = VL/32
FOR i in range(0, KL):
dest.dword[i] = convert_fp16_to_fp32(src.dword[i].word[0]) //SAE
DEST[MAXVL-1:VL] := 0
Flags Affected
None.
Intel C/C++ Compiler Intrinsic Equivalent
VCVTNEEPH2PS __m128 _mm_cvtneeph_ps (const __m128h* __A);
VCVTNEEPH2PS __m256 _mm256_cvtneeph_ps (const __m256h* __A);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-21, “Type 4 Class Exception Conditions.”
VCVTNEEPH2PS-Convert Even Elements of Packed FP16 Values to FP32 Values
Vol. 2C
5-35
VCVTNEOBF162PS-Convert Odd Elements of Packed BF16 Values to FP32 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
VEX.128.F2.0F38.W0 B0 !(11):rrr:bbb
A
V/V
AVX_NE_
Convert odd elements of packed BF16 values
CONVERT
from m128 to FP32 values and store in
VCVTNEOBF162PS xmm1, m128
xmm1.
VEX.256.F2.0F38.W0 B0 !(11):rrr:bbb
A
V/V
AVX_NE_
Convert odd elements of packed BF16 values
CONVERT
from m256 to FP32 values and store in
VCVTNEOBF162PS ymm1, m256
ymm1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction loads packed BF16 elements from memory, converts the odd elements to FP32, and writes the
result to the destination SIMD register.
This instruction does not generate floating-point exceptions and does not consult or update MXCSR.
Since any BF16 number can be represented in FP32, the conversion result is exact and no rounding is needed.
Operation
VCVTNEOBF162PS dest, src (VEX encoded version)
VL = (128, 256)
KL = VL/32
FOR i in range(0, KL):
dest.dword[i] = make_fp32(src.dword[i].word[1])
DEST[MAXVL-1:VL] := 0
Flags Affected
None.
Intel C/C++ Compiler Intrinsic Equivalent
VCVTNEOBF162PS __m128 _mm_cvtneobf16_ps (const __m128bh* __A);
VCVTNEOBF162PS __m256 _mm256_cvtneobf16_ps (const __m256bh* __A);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-21, “Type 4 Class Exception Conditions.”
VCVTNEOBF162PS-Convert Odd Elements of Packed BF16 Values to FP32 Values
Vol. 2C
5-36
VCVTNEOPH2PS-Convert Odd Elements of Packed FP16 Values to FP32 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
VEX.128.NP.0F38.W0 B0 !(11):rrr:bbb
A
V/V
AVX_NE_
Convert odd elements of packed FP16 values
CONVERT
from m128 to FP32 values and store in
VCVTNEOPH2PS xmm1, m128
xmm1.
VEX.256.NP.0F38.W0 B0 !(11):rrr:bbb
A
V/V
AVX_NE_
Convert odd elements of packed FP16 values
CONVERT
from m256 to FP32 values and store in
VCVTNEOPH2PS ymm1, m256
ymm1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction loads packed FP16 elements from memory, converts the odd elements to FP32, and writes the
result to the destination SIMD register.
This instruction does not generate floating-point exceptions and does not consult or update MXCSR.
Input FP16 denormals are converted to normal FP32 numbers and not treated as zero. Since any FP16 number can
be represented in FP32, the conversion result is exact and no rounding is needed.
Operation
VCVTNEOPH2PS dest, src (VEX encoded version)
VL = (128, 256)
KL = VL/32
FOR i in range(0, KL):
dest.dword[i] = convert_fp16_to_fp32(src.dword[i].word[1]) //SAE
DEST[MAXVL-1:VL] := 0
Flags Affected
None.
Intel C/C++ Compiler Intrinsic Equivalent
VCVTNEOPH2PS __m128 _mm_cvtneoph_ps (const __m128h* __A);
VCVTNEOPH2PS __m256 _mm256_cvtneoph_ps (const __m256h* __A);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-21, “Type 4 Class Exception Conditions.”
VCVTNEOPH2PS-Convert Odd Elements of Packed FP16 Values to FP32 Values
Vol. 2C
5-37
VCVTNEPS2BF16-Convert Packed Single Data to Packed BF16 Data
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
VEX.128.F3.0F38.W0 72 /r
A
V/V
AVX_NE_
Convert packed single precision floating-point
CONVERT
values from xmm2/m128 to packed BF16
VCVTNEPS2BF16 xmm1,
values and store in xmm1.
xmm2/m128
VEX.256.F3.0F38.W0 72 /r
A
V/V
AVX_NE_
Convert packed single precision floating-point
CONVERT
values from ymm2/m256 to packed BF16
VCVTNEPS2BF16 xmm1,
values and store in xmm1.
ymm2/m256
EVEX.128.F3.0F38.W0 72 /r
B
V/V
(AVX512_BF16
Convert packed single data from xmm2/m128
VCVTNEPS2BF16 xmm1{k1}{z},
AND AVX512VL)
to packed BF16 data in xmm1 with writemask
xmm2/m128/m32bcst
OR AVX10.1
k1.
EVEX.256.F3.0F38.W0 72 /r
B
V/V
(AVX512_BF16
Convert packed single data from ymm2/m256
VCVTNEPS2BF16 xmm1{k1}{z},
AND AVX512VL)
to packed BF16 data in xmm1 with writemask
ymm2/m256/m32bcst
OR AVX10.1
k1.
EVEX.512.F3.0F38.W0 72 /r
B
V/V
(AVX512_BF16
Convert packed single data from zmm2/m512
VCVTNEPS2BF16 ymm1{k1}{z},
AND AVX512F)
to packed BF16 data in ymm1 with writemask
zmm2/m512/m32bcst
OR AVX10.1
k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
B
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction loads packed FP32 elements from a SIMD register or memory, converts the elements to BF16, and
writes the result to the destination SIMD register.
The upper bits of the destination register beyond the down-converted BF16 elements are zeroed.
This instruction uses “Round to nearest (even)” rounding mode. Output denormals are always flushed to zero and
input denormals are always treated as zero. MXCSR is not consulted nor updated.
As the instruction operand encoding table shows, the EVEX.vvvv field is not used for encoding an operand.
EVEX.vvvv is reserved and must be 0b1111 otherwise instructions will #UD.
Operation
Define convert_fp32_to_bfloat16(x):
IF x is zero or denormal:
dest[15] := x[31] // sign preserving zero (denormal go to zero)
dest[14:0] := 0
ELSE IF x is infinity:
dest[15:0] := x[31:16]
ELSE IF x is NAN:
dest[15:0] := x[31:16] // truncate and set MSB of the mantissa to force QNAN
dest[6] := 1
ELSE // normal number
LSB := x[16]
rounding_bias := 0x00007FFF + LSB
temp[31:0] := x[31:0] + rounding_bias // integer add
dest[15:0] := temp[31:16]
RETURN dest
VCVTNEPS2BF16-Convert Packed Single Data to Packed BF16 Data
Vol. 2C
5-38
VCVTNEPS2BF16 dest, src (VEX encoded version)
VL = (128, 256)
KL = VL/16
FOR i := 0 to KL/2-1:
t := src.fp32[i]
dest.word[i] := convert_fp32_to_bfloat16(t)
DEST[MAXVL-1:VL/2] := 0
VCVTNEPS2BF16 dest, src (EVEX encoded version)
VL = (128, 256, 512)
KL = VL/16
origdest := dest
FOR i := 0 to KL/2-1:
IF k1[ i ] or *no writemask*:
IF src is memory and evex.b == 1:
t := src.fp32[0]
ELSE:
t := src.fp32[ i ]
dest.word[i] := convert_fp32_to_bfloat16(t)
ELSE IF *zeroing*:
dest.word[ i ] := 0
ELSE: // Merge masking, dest element unchanged
dest.word[ i ] := origdest.word[ i ]
DEST[MAXVL-1:VL/2] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTNEPS2BF16 __m128bh _mm_cvtneps_avx_pbh (__m128 __A);
VCVTNEPS2BF16 __m128bh _mm256_cvtneps_avx_pbh (__m256 __A);
VCVTNEPS2BF16 __m128bh _mm_cvtneps_pbh (__m128 a);
VCVTNEPS2BF16 __m128bh _mm_cvtneps_pbh (__m128 __A);
VCVTNEPS2BF16 __m128bh _mm_mask_cvtneps_pbh (__m128bh src, __mmask8 k, __m128 a);
VCVTNEPS2BF16 __m128bh _mm_maskz_cvtneps_pbh (__mmask8 k, __m128 a);
VCVTNEPS2BF16 __m128bh _mm256_cvtneps_pbh (__m256 a);
VCVTNEPS2BF16 __m128bh _mm256_cvtneps_pbh (__m256 __A);
VCVTNEPS2BF16 __m128bh _mm256_mask_cvtneps_pbh (__m128bh src, __mmask8 k, __m256 a);
VCVTNEPS2BF16 __m128bh _mm256_maskz_cvtneps_pbh (__mmask8 k, __m256 a);
VCVTNEPS2BF16 __m256bh _mm512_cvtneps_pbh (__m512 a);
VCVTNEPS2BF16 __m256bh _mm512_mask_cvtneps_pbh (__m256bh src, __mmask16 k, __m512 a);
VCVTNEPS2BF16 __m256bh _mm512_maskz_cvtneps_pbh (__mmask16 k, __m512 a);
SIMD Floating-Point Exceptions
None.
Other Exceptions
VEX-encoded instructions, see Table 2-21, “Type 4 Class Exception Conditions.”
EVEX-encoded instructions, see Table 2-51, “Type E4 Class Exception Conditions.”
VCVTNEPS2BF16-Convert Packed Single Data to Packed BF16 Data
Vol. 2C
5-39
VCVTPD2PH-Convert Packed Double Precision FP Values to Packed FP16 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.66.MAP5.W1 5A /r
A
V/V
(AVX512_FP16
Convert two packed double precision floating-
VCVTPD2PH xmm1{k1}{z},
AND AVX512VL)
point values in xmm2/m128/m64bcst to two
xmm2/m128/m64bcst
OR AVX10.1
packed FP16 values, and store the result in xmm1
subject to writemask k1.
EVEX.256.66.MAP5.W1 5A /r
A
V/V
(AVX512_FP16
Convert four packed double precision floating-
VCVTPD2PH xmm1{k1}{z},
AND AVX512VL)
point values in ymm2/m256/m64bcst to four
ymm2/m256/m64bcst
OR AVX10.1
packed FP16 values, and store the result in xmm1
subject to writemask k1.
EVEX.512.66.MAP5.W1 5A /r
A
V/V
AVX512_FP16
Convert eight packed double precision floating-
VCVTPD2PH xmm1{k1}{z},
OR AVX10.1
point values in zmm2/m512/m64bcst to eight
zmm2/m512/m64bcst {er}
packed FP16 values, and store the result in ymm1
subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts two, four, or eight packed double precision floating-point values in the source operand
(second operand) to two, four, or eight packed FP16 values in the destination operand (first operand). When a
conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or
the embedded rounding control bits.
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or
a 512/256/128-bit vector broadcasts from a 64-bit memory location. The destination operand is a XMM register
conditionally updated with writemask k1. The upper bits (MAXVL-1:128/64/32) of the corresponding destination
are zeroed.
EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
This instruction uses MXCSR.DAZ for handling FP64 inputs. FP16 outputs can be normal or denormal, and are not
conditionally flushed to zero.
VCVTPD2PH-Convert Packed Double Precision FP Values to Packed FP16 Values
Vol. 2C
5-40
Operation
VCVTPD2PH DEST, SRC
VL = 128, 256 or 512
KL := VL / 64
IF *SRC is a register* and (VL = 512) AND (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.double[0]
ELSE
tsrc := SRC.double[j]
DEST.fp16[j] := Convert_fp64_to_fp16(tsrc)
ELSE IF *zeroing*:
DEST.fp16[j] := 0
// else dest.fp16[j] remains unchanged
DEST[MAXVL-1:VL/4] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPD2PH __m128h _mm512_cvt_roundpd_ph (__m512d a, int rounding);
VCVTPD2PH __m128h _mm512_mask_cvt_roundpd_ph (__m128h src, __mmask8 k, __m512d a, int rounding);
VCVTPD2PH __m128h _mm512_maskz_cvt_roundpd_ph (__mmask8 k, __m512d a, int rounding);
VCVTPD2PH __m128h _mm_cvtpd_ph (__m128d a);
VCVTPD2PH __m128h _mm_mask_cvtpd_ph (__m128h src, __mmask8 k, __m128d a);
VCVTPD2PH __m128h _mm_maskz_cvtpd_ph (__mmask8 k, __m128d a);
VCVTPD2PH __m128h _mm256_cvtpd_ph (__m256d a);
VCVTPD2PH __m128h _mm256_mask_cvtpd_ph (__m128h src, __mmask8 k, __m256d a);
VCVTPD2PH __m128h _mm256_maskz_cvtpd_ph (__mmask8 k, __m256d a);
VCVTPD2PH __m128h _mm512_cvtpd_ph (__m512d a);
VCVTPD2PH __m128h _mm512_mask_cvtpd_ph (__m128h src, __mmask8 k, __m512d a);
VCVTPD2PH __m128h _mm512_maskz_cvtpd_ph (__mmask8 k, __m512d a);
SIMD Floating-Point Exceptions
Invalid, Underflow, Overflow, Precision, Denormal.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
VCVTPD2PH-Convert Packed Double Precision FP Values to Packed FP16 Values
Vol. 2C
5-41
VCVTPD2QQ-Convert Packed Double Precision Floating-Point Values to Packed Quadword
Integers
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.66.0F.W1 7B /r
A
V/V
(AVX512VL AND
Convert two packed double precision floating-point values
VCVTPD2QQ xmm1 {k1}{z},
AVX512DQ) OR
from xmm2/m128/m64bcst to two packed signed
xmm2/m128/m64bcst
AVX10.1
quadword integers in xmm1 with writemask k1.
EVEX.256.66.0F.W1 7B /r
A
V/V
(AVX512VL AND
Convert four packed double precision floating-point
VCVTPD2QQ ymm1 {k1}{z},
AVX512DQ) OR
values from ymm2/m256/m64bcst to four packed signed
ymm2/m256/m64bcst
AVX10.1
quadword integers in ymm1 with writemask k1.
EVEX.512.66.0F.W1 7B /r
A
V/V
AVX512DQ
Convert eight packed double precision floating-point
VCVTPD2QQ zmm1 {k1}{z},
OR AVX10.1
values from zmm2/m512/m64bcst to eight packed
zmm2/m512/m64bcst {er}
signed quadword integers in zmm1 with writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts packed double precision floating-point values in the source operand (second operand) to packed quad-
word integers in the destination operand (first operand).
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The destination operation is a ZMM/YMM/XMM register conditionally updated with writemask k1.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value
80000000_00000000H is returned.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VCVTPD2QQ (EVEX Encoded Version) When SRC Operand is a Register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL == 512) AND (EVEX.b == 1)
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
ELSE
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
FI;
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] :=
Convert_Double_Precision_Floating_Point_To_QuadInteger(SRC[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
VCVTPD2QQ-Convert Packed Double Precision Floating-Point Values to Packed Quadword Integers
Vol. 2C
5-42
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VCVTPD2QQ (EVEX Encoded Version) When SRC Operand is a Memory Source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[i+63:i] :=
Convert_Double_Precision_Floating_Point_To_QuadInteger(SRC[63:0])
ELSE
DEST[i+63:i] := Convert_Double_Precision_Floating_Point_To_QuadInteger(SRC[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPD2QQ __m512i _mm512_cvtpd_epi64( __m512d a);
VCVTPD2QQ __m512i _mm512_mask_cvtpd_epi64( __m512i s, __mmask8 k, __m512d a);
VCVTPD2QQ __m512i _mm512_maskz_cvtpd_epi64( __mmask8 k, __m512d a);
VCVTPD2QQ __m512i _mm512_cvt_roundpd_epi64( __m512d a, int r);
VCVTPD2QQ __m512i _mm512_mask_cvt_roundpd_epi64( __m512i s, __mmask8 k, __m512d a, int r);
VCVTPD2QQ __m512i _mm512_maskz_cvt_roundpd_epi64( __mmask8 k, __m512d a, int r);
VCVTPD2QQ __m256i _mm256_mask_cvtpd_epi64( __m256i s, __mmask8 k, __m256d a);
VCVTPD2QQ __m256i _mm256_maskz_cvtpd_epi64( __mmask8 k, __m256d a);
VCVTPD2QQ __m128i _mm_mask_cvtpd_epi64( __m128i s, __mmask8 k, __m128d a);
VCVTPD2QQ __m128i _mm_maskz_cvtpd_epi64( __mmask8 k, __m128d a);
VCVTPD2QQ __m256i _mm256_cvtpd_epi64 (__m256d src)
VCVTPD2QQ __m128i _mm_cvtpd_epi64 (__m128d src)
SIMD Floating-Point Exceptions
Invalid, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VCVTPD2QQ-Convert Packed Double Precision Floating-Point Values to Packed Quadword Integers
Vol. 2C
5-43
VCVTPD2UDQ-Convert Packed Double Precision Floating-Point Values to Packed Unsigned
Doubleword Integers
Opcode
Op /
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.0F.W1 79 /r
A
V/V
(AVX512VL AND
Convert two packed double precision floating-point
VCVTPD2UDQ xmm1 {k1}{z},
AVX512F) OR
values in xmm2/m128/m64bcst to two unsigned
xmm2/m128/m64bcst
AVX10.1
doubleword integers in xmm1 subject to writemask
k1.
EVEX.256.0F.W1 79 /r
A
V/V
(AVX512VL AND
Convert four packed double precision floating-point
VCVTPD2UDQ xmm1 {k1}{z},
AVX512F) OR
values in ymm2/m256/m64bcst to four unsigned
ymm2/m256/m64bcst
AVX10.1
doubleword integers in xmm1 subject to writemask
k1.
EVEX.512.0F.W1 79 /r
A
V/V
AVX512F
Convert eight packed double precision floating-point
VCVTPD2UDQ ymm1 {k1}{z},
OR AVX10.1
values in zmm2/m512/m64bcst to eight unsigned
zmm2/m512/m64bcst {er}
doubleword integers in ymm1 subject to writemask
k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts packed double precision floating-point values in the source operand (the second operand) to packed
unsigned doubleword integers in the destination operand (the first operand).
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the integer value FFFFFFFFH
is returned.
The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector
broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1. The upper bits (MAXVL-1:256) of the corresponding destination are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VCVTPD2UDQ (EVEX Encoded Versions) When SRC2 Operand is a Register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
ELSE
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
FI;
FOR j := 0 TO KL-1
i := j * 32
k := j * 64
IF k1[j] OR *no writemask*
THEN
DEST[i+31:i] :=
Convert_Double_Precision_Floating_Point_To_UInteger(SRC[k+63:k])
VCVTPD2UDQ-Convert Packed Double Precision Floating-Point Values to Packed Unsigned Doubleword Integers
Vol. 2C
5-44
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0
VCVTPD2UDQ (EVEX Encoded Versions) When SRC Operand is a Memory Source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 32
k := j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i] :=
Convert_Double_Precision_Floating_Point_To_UInteger(SRC[63:0])
ELSE
DEST[i+31:i] :=
Convert_Double_Precision_Floating_Point_To_UInteger(SRC[k+63:k])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPD2UDQ __m256i _mm512_cvtpd_epu32( __m512d a);
VCVTPD2UDQ __m256i _mm512_mask_cvtpd_epu32( __m256i s, __mmask8 k, __m512d a);
VCVTPD2UDQ __m256i _mm512_maskz_cvtpd_epu32( __mmask8 k, __m512d a);
VCVTPD2UDQ __m256i _mm512_cvt_roundpd_epu32( __m512d a, int r);
VCVTPD2UDQ __m256i _mm512_mask_cvt_roundpd_epu32( __m256i s, __mmask8 k, __m512d a, int r);
VCVTPD2UDQ __m256i _mm512_maskz_cvt_roundpd_epu32( __mmask8 k, __m512d a, int r);
VCVTPD2UDQ __m128i _mm256_mask_cvtpd_epu32( __m128i s, __mmask8 k, __m256d a);
VCVTPD2UDQ __m128i _mm256_maskz_cvtpd_epu32( __mmask8 k, __m256d a);
VCVTPD2UDQ __m128i _mm_mask_cvtpd_epu32( __m128i s, __mmask8 k, __m128d a);
VCVTPD2UDQ __m128i _mm_maskz_cvtpd_epu32( __mmask8 k, __m128d a);
SIMD Floating-Point Exceptions
Invalid, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
VCVTPD2UDQ-Convert Packed Double Precision Floating-Point Values to Packed Unsigned Doubleword Integers
Vol. 2C
5-45
Additionally:
#UD
If EVEX.vvvv != 1111B.
VCVTPD2UDQ-Convert Packed Double Precision Floating-Point Values to Packed Unsigned Doubleword Integers
Vol. 2C
5-46
VCVTPD2UQQ-Convert Packed Double Precision Floating-Point Values to Packed Unsigned
Quadword Integers
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.66.0F.W1 79 /r
A
V/V
(AVX512VL AND
Convert two packed double precision floating-point
VCVTPD2UQQ xmm1 {k1}{z},
AVX512DQ) OR
values from xmm2/mem to two packed unsigned
xmm2/m128/m64bcst
AVX10.1
quadword integers in xmm1 with writemask k1.
EVEX.256.66.0F.W1 79 /r
A
V/V
(AVX512VL AND
Convert fourth packed double precision floating-point
VCVTPD2UQQ ymm1 {k1}{z},
AVX512DQ) OR
values from ymm2/mem to four packed unsigned
ymm2/m256/m64bcst
AVX10.1
quadword integers in ymm1 with writemask k1.
EVEX.512.66.0F.W1 79 /r
A
V/V
AVX512DQ
Convert eight packed double precision floating-point
VCVTPD2UQQ zmm1 {k1}{z},
OR AVX10.1
values from zmm2/mem to eight packed unsigned
zmm2/m512/m64bcst {er}
quadword integers in zmm1 with writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts packed double precision floating-point values in the source operand (second operand) to packed unsigned
quadword integers in the destination operand (first operand).
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the integer value
FFFFFFFF_FFFFFFFFH is returned.
The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operation
is a ZMM/YMM/XMM register conditionally updated with writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VCVTPD2UQQ (EVEX Encoded Versions) When SRC Operand is a Register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL == 512) AND (EVEX.b == 1)
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
ELSE
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
FI;
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] :=
Convert_Double_Precision_Floating_Point_To_UQuadInteger(SRC[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
VCVTPD2UQQ-Convert Packed Double Precision Floating-Point Values to Packed Unsigned Quadword Integers
Vol. 2C
5-47
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VCVTPD2UQQ (EVEX Encoded Versions) When SRC Operand is a Memory Source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[i+63:i] :=
Convert_Double_Precision_Floating_Point_To_UQuadInteger(SRC[63:0])
ELSE
DEST[i+63:i] :=
Convert_Double_Precision_Floating_Point_To_UQuadInteger(SRC[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPD2UQQ __m512i _mm512_cvtpd_epu64( __m512d a);
VCVTPD2UQQ __m512i _mm512_mask_cvtpd_epu64( __m512i s, __mmask8 k, __m512d a);
VCVTPD2UQQ __m512i _mm512_maskz_cvtpd_epu64( __mmask8 k, __m512d a);
VCVTPD2UQQ __m512i _mm512_cvt_roundpd_epu64( __m512d a, int r);
VCVTPD2UQQ __m512i _mm512_mask_cvt_roundpd_epu64( __m512i s, __mmask8 k, __m512d a, int r);
VCVTPD2UQQ __m512i _mm512_maskz_cvt_roundpd_epu64( __mmask8 k, __m512d a, int r);
VCVTPD2UQQ __m256i _mm256_mask_cvtpd_epu64( __m256i s, __mmask8 k, __m256d a);
VCVTPD2UQQ __m256i _mm256_maskz_cvtpd_epu64( __mmask8 k, __m256d a);
VCVTPD2UQQ __m128i _mm_mask_cvtpd_epu64( __m128i s, __mmask8 k, __m128d a);
VCVTPD2UQQ __m128i _mm_maskz_cvtpd_epu64( __mmask8 k, __m128d a);
VCVTPD2UQQ __m256i _mm256_cvtpd_epu64 (__m256d src)
VCVTPD2UQQ __m128i _mm_cvtpd_epu64 (__m128d src)
SIMD Floating-Point Exceptions
Invalid, Precision.
VCVTPD2UQQ-Convert Packed Double Precision Floating-Point Values to Packed Unsigned Quadword Integers
Vol. 2C
5-48
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VCVTPD2UQQ-Convert Packed Double Precision Floating-Point Values to Packed Unsigned Quadword Integers
Vol. 2C
5-49
VCVTPH2DQ-Convert Packed FP16 Values to Signed Doubleword Integers
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.66.MAP5.W0 5B /r
A
V/V
(AVX512_FP16
Convert four packed FP16 values in
VCVTPH2DQ xmm1{k1}{z},
AND AVX512VL)
xmm2/m64/m16bcst to four signed doubleword
xmm2/m64/m16bcst
OR AVX10.1
integers, and store the result in xmm1 subject to
writemask k1.
EVEX.256.66.MAP5.W0 5B /r
A
V/V
(AVX512_FP16
Convert eight packed FP16 values in
VCVTPH2DQ ymm1{k1}{z},
AND AVX512VL)
xmm2/m128/m16bcst to eight signed
xmm2/m128/m16bcst
OR AVX10.1
doubleword integers, and store the result in
ymm1 subject to writemask k1.
EVEX.512.66.MAP5.W0 5B /r
A
V/V
AVX512_FP16
Convert sixteen packed FP16 values in
VCVTPH2DQ zmm1{k1}{z},
OR AVX10.1
ymm2/m256/m16bcst to sixteen signed
ymm2/m256/m16bcst {er}
doubleword integers, and store the result in
zmm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Half
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed FP16 values in the source operand to signed doubleword integers in destination
operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value
80000000H is returned.
The destination elements are updated according to the writemask.
VCVTPH2DQ-Convert Packed FP16 Values to Signed Doubleword Integers
Vol. 2C
5-50
Operation
VCVTPH2DQ DEST, SRC
VL = 128, 256 or 512
KL := VL / 32
IF *SRC is a register* and (VL = 512) and (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.fp16[0]
ELSE
tsrc := SRC.fp16[j]
DEST.dword[j] := Convert_fp16_to_integer32(tsrc)
ELSE IF *zeroing*:
DEST.dword[j] := 0
// else dest.dword[j] remains unchanged
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPH2DQ __m512i _mm512_cvt_roundph_epi32 (__m256h a, int rounding);
VCVTPH2DQ __m512i _mm512_mask_cvt_roundph_epi32 (__m512i src, __mmask16 k, __m256h a, int rounding);
VCVTPH2DQ __m512i _mm512_maskz_cvt_roundph_epi32 (__mmask16 k, __m256h a, int rounding);
VCVTPH2DQ __m128i _mm_cvtph_epi32 (__m128h a);
VCVTPH2DQ __m128i _mm_mask_cvtph_epi32 (__m128i src, __mmask8 k, __m128h a);
VCVTPH2DQ __m128i _mm_maskz_cvtph_epi32 (__mmask8 k, __m128h a);
VCVTPH2DQ __m256i _mm256_cvtph_epi32 (__m128h a);
VCVTPH2DQ __m256i _mm256_mask_cvtph_epi32 (__m256i src, __mmask8 k, __m128h a);
VCVTPH2DQ __m256i _mm256_maskz_cvtph_epi32 (__mmask8 k, __m128h a);
VCVTPH2DQ __m512i _mm512_cvtph_epi32 (__m256h a);
VCVTPH2DQ __m512i _mm512_mask_cvtph_epi32 (__m512i src, __mmask16 k, __m256h a);
VCVTPH2DQ __m512i _mm512_maskz_cvtph_epi32 (__mmask16 k, __m256h a);
SIMD Floating-Point Exceptions
Invalid, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
VCVTPH2DQ-Convert Packed FP16 Values to Signed Doubleword Integers
Vol. 2C
5-51
VCVTPH2PD-Convert Packed FP16 Values to FP64 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.NP.MAP5.W0 5A /r
A
V/V
(AVX512_FP16
Convert packed FP16 values in
VCVTPH2PD xmm1{k1}{z},
AND AVX512VL)
xmm2/m32/m16bcst to FP64 values, and store
xmm2/m32/m16bcst
OR AVX10.1
result in xmm1 subject to writemask k1.
EVEX.256.NP.MAP5.W0 5A /r
A
V/V
(AVX512_FP16
Convert packed FP16 values in
VCVTPH2PD ymm1{k1}{z},
AND AVX512VL)
xmm2/m64/m16bcst to FP64 values, and store
xmm2/m64/m16bcst
OR AVX10.1
result in ymm1 subject to writemask k1.
EVEX.512.NP.MAP5.W0 5A /r
A
V/V
AVX512_FP16
Convert packed FP16 values in
VCVTPH2PD zmm1{k1}{z},
OR AVX10.1
xmm2/m128/m16bcst to FP64 values, and store
xmm2/m128/m16bcst {sae}
result in zmm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Quarter
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed FP16 values to FP64 values in the destination register. The destination elements
are updated according to the writemask.
This instruction handles both normal and denormal FP16 inputs.
Operation
VCVTPH2PD DEST, SRC
VL = 128, 256, or 512
KL := VL/64
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.fp16[0]
ELSE
tsrc := SRC.fp16[j]
DEST.fp64[j] := Convert_fp16_to_fp64(tsrc)
ELSE IF *zeroing*:
DEST.fp64[j] := 0
// else dest.fp64[j] remains unchanged
DEST[MAXVL-1:VL] := 0
VCVTPH2PD-Convert Packed FP16 Values to FP64 Values
Vol. 2C
5-52
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPH2PD __m512d _mm512_cvt_roundph_pd (__m128h a, int sae);
VCVTPH2PD __m512d _mm512_mask_cvt_roundph_pd (__m512d src, __mmask8 k, __m128h a, int sae);
VCVTPH2PD __m512d _mm512_maskz_cvt_roundph_pd (__mmask8 k, __m128h a, int sae);
VCVTPH2PD __m128d _mm_cvtph_pd (__m128h a);
VCVTPH2PD __m128d _mm_mask_cvtph_pd (__m128d src, __mmask8 k, __m128h a);
VCVTPH2PD __m128d _mm_maskz_cvtph_pd (__mmask8 k, __m128h a);
VCVTPH2PD __m256d _mm256_cvtph_pd (__m128h a);
VCVTPH2PD __m256d _mm256_mask_cvtph_pd (__m256d src, __mmask8 k, __m128h a);
VCVTPH2PD __m256d _mm256_maskz_cvtph_pd (__mmask8 k, __m128h a);
VCVTPH2PD __m512d _mm512_cvtph_pd (__m128h a);
VCVTPH2PD __m512d _mm512_mask_cvtph_pd (__m512d src, __mmask8 k, __m128h a);
VCVTPH2PD __m512d _mm512_maskz_cvtph_pd (__mmask8 k, __m128h a);
SIMD Floating-Point Exceptions
Invalid, Denormal.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
VCVTPH2PD-Convert Packed FP16 Values to FP64 Values
Vol. 2C
5-53
VCVTPH2PS/VCVTPH2PSX-Convert Packed FP16 Values to Single Precision Floating-Point
Values
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
VEX.128.66.0F38.W0 13 /r
A
V/V
F16C
Convert four packed FP16 values in xmm2/m64 to
VCVTPH2PS xmm1, xmm2/m64
packed single precision floating-point value in xmm1.
VEX.256.66.0F38.W0 13 /r
A
V/V
F16C
Convert eight packed FP16 values in xmm2/m128 to
VCVTPH2PS ymm1, xmm2/m128
packed single precision floating-point value in ymm1.
EVEX.128.66.0F38.W0 13 /r
B
V/V
(AVX512VL AND
Convert four packed FP16 values in xmm2/m64 to
VCVTPH2PS xmm1 {k1}{z},
AVX512F) OR
packed single precision floating-point values in xmm1
xmm2/m64
AVX10.1
subject to writemask k1.
EVEX.256.66.0F38.W0 13 /r
B
V/V
(AVX512VL AND
Convert eight packed FP16 values in xmm2/m128 to
VCVTPH2PS ymm1 {k1}{z},
AVX512F) OR
packed single precision floating-point values in ymm1
xmm2/m128
AVX10.1
subject to writemask k1.
EVEX.512.66.0F38.W0 13 /r
B
V/V
AVX512F
Convert sixteen packed FP16 values in ymm2/m256
VCVTPH2PS zmm1 {k1}{z},
OR AVX10.1
to packed single precision floating-point values in
ymm2/m256 {sae}
zmm1 subject to writemask k1.
EVEX.128.66.MAP6.W0 13 /r
C
V/V
(AVX512_FP16
Convert four packed FP16 values in
VCVTPH2PSX xmm1{k1}{z},
AND AVX512VL)
xmm2/m64/m16bcst to four packed single precision
xmm2/m64/m16bcst
OR AVX10.1
floating-point values, and store result in xmm1
subject to writemask k1.
EVEX.256.66.MAP6.W0 13 /r
C
V/V
(AVX512_FP16
Convert eight packed FP16 values in
VCVTPH2PSX ymm1{k1}{z},
AND AVX512VL)
xmm2/m128/m16bcst to eight packed single
xmm2/m128/m16bcst
OR AVX10.1
precision floating-point values, and store result in
ymm1 subject to writemask k1.
EVEX.512.66.MAP6.W0 13 /r
C
V/V
AVX512_FP16
Convert sixteen packed FP16 values in
VCVTPH2PSX zmm1{k1}{z},
OR AVX10.1
ymm2/m256/m16bcst to sixteen packed single
ymm2/m256/m16bcst {sae}
precision floating-point values, and store result in
zmm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
B
Half Mem
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
C
Half
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed half precision (16-bits) floating-point values in the low-order bits of the source
operand (the second operand) to packed single precision floating-point values and writes the converted values into
the destination operand (the first operand).
If case of a denormal operand, the correct normal result is returned. MXCSR.DAZ is ignored and is treated as if it
0. No denormal exception is reported on MXCSR.
VEX.128 version: The source operand is a XMM register or 64-bit memory location. The destination operand is a
XMM register. The upper bits (MAXVL-1:128) of the corresponding destination register are zeroed.
VEX.256 version: The source operand is a XMM register or 128-bit memory location. The destination operand is a
YMM register. Bits (MAXVL-1:256) of the corresponding destination register are zeroed.
VCVTPH2PS/VCVTPH2PSX-Convert Packed FP16 Values to Single Precision Floating-Point Values
Vol. 2C
5-54
EVEX encoded versions: The source operand is a YMM/XMM/XMM (low 64-bits) register or a 256/128/64-bit
memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.
The diagram below illustrates how data is converted from four packed half precision (in 64 bits) to four single preci-
sion (in 128 bits) floating-point values.
Note: VEX.vvvv and EVEX.vvvv are reserved (must be 1111b).
VCVTPH2PS xmm1, xmm2/mem64, imm8
127
96
95
64
63
48
47
32
31
16
15
0
VH3
VH2
VH1
VH0
xmm2/mem64
convert
convert
convert
convert
127
96
95
64
63
32
31
0
VS3
VS2
VS1
VS0
xmm1
Figure 5-6. VCVTPH2PS (128-bit Version)
The VCVTPH2PSX instruction is a new form of the PH to PS conversion instruction, encoded in map 6. The previous
version of the instruction, VCVTPH2PS, that is present in AVX512F (encoded in map 2, 0F38) does not support
embedded broadcasting. The VCVTPH2PSX instruction has the embedded broadcasting option available.
The instructions associated with AVX512_FP16 always handle FP16 denormal number inputs; denormal inputs are
not treated as zero.
Operation
vCvt_h2s(SRC1[15:0])
{
RETURN Cvt_Half_Precision_To_Single_Precision(SRC1[15:0]);
}
VCVTPH2PS (EVEX Encoded Versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
k := j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] :=
vCvt_h2s(SRC[k+15:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VCVTPH2PS/VCVTPH2PSX-Convert Packed FP16 Values to Single Precision Floating-Point Values
Vol. 2C
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VCVTPH2PS (VEX.256 Encoded Version)
DEST[31:0] := vCvt_h2s(SRC1[15:0]);
DEST[63:32] := vCvt_h2s(SRC1[31:16]);
DEST[95:64] := vCvt_h2s(SRC1[47:32]);
DEST[127:96] := vCvt_h2s(SRC1[63:48]);
DEST[159:128] := vCvt_h2s(SRC1[79:64]);
DEST[191:160] := vCvt_h2s(SRC1[95:80]);
DEST[223:192] := vCvt_h2s(SRC1[111:96]);
DEST[255:224] := vCvt_h2s(SRC1[127:112]);
DEST[MAXVL-1:256] := 0
VCVTPH2PS (VEX.128 Encoded Version)
DEST[31:0] := vCvt_h2s(SRC1[15:0]);
DEST[63:32] := vCvt_h2s(SRC1[31:16]);
DEST[95:64] := vCvt_h2s(SRC1[47:32]);
DEST[127:96] := vCvt_h2s(SRC1[63:48]);
DEST[MAXVL-1:128] := 0
VCVTPH2PSX DEST, SRC
VL = 128, 256, or 512
KL := VL/32
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.fp16[0]
ELSE
tsrc := SRC.fp16[j]
DEST.fp32[j] := Convert_fp16_to_fp32(tsrc)
ELSE IF *zeroing*:
DEST.fp32[j] := 0
// else dest.fp32[j] remains unchanged
DEST[MAXVL-1:VL] := 0
Flags Affected
None.
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPH2PS __m512 _mm512_cvtph_ps( __m256i a);
VCVTPH2PS __m512 _mm512_mask_cvtph_ps(__m512 s, __mmask16 k, __m256i a);
VCVTPH2PS __m512 _mm512_maskz_cvtph_ps(__mmask16 k, __m256i a);
VCVTPH2PS __m512 _mm512_cvt_roundph_ps( __m256i a, int sae);
VCVTPH2PS __m512 _mm512_mask_cvt_roundph_ps(__m512 s, __mmask16 k, __m256i a, int sae);
VCVTPH2PS __m512 _mm512_maskz_cvt_roundph_ps( __mmask16 k, __m256i a, int sae);
VCVTPH2PS __m256 _mm256_mask_cvtph_ps(__m256 s, __mmask8 k, __m128i a);
VCVTPH2PS __m256 _mm256_maskz_cvtph_ps(__mmask8 k, __m128i a);
VCVTPH2PS __m128 _mm_mask_cvtph_ps(__m128 s, __mmask8 k, __m128i a);
VCVTPH2PS __m128 _mm_maskz_cvtph_ps(__mmask8 k, __m128i a);
VCVTPH2PS __m128 _mm_cvtph_ps ( __m128i m1);
VCVTPH2PS __m256 _mm256_cvtph_ps ( __m128i m1)
VCVTPH2PS/VCVTPH2PSX-Convert Packed FP16 Values to Single Precision Floating-Point Values
Vol. 2C
5-56
VCVTPH2PSX __m512 _mm512_cvtx_roundph_ps (__m256h a, int sae);
VCVTPH2PSX __m512 _mm512_mask_cvtx_roundph_ps (__m512 src, __mmask16 k, __m256h a, int sae);
VCVTPH2PSX __m512 _mm512_maskz_cvtx_roundph_ps (__mmask16 k, __m256h a, int sae);
VCVTPH2PSX __m128 _mm_cvtxph_ps (__m128h a);
VCVTPH2PSX __m128 _mm_mask_cvtxph_ps (__m128 src, __mmask8 k, __m128h a);
VCVTPH2PSX __m128 _mm_maskz_cvtxph_ps (__mmask8 k, __m128h a);
VCVTPH2PSX __m256 _mm256_cvtxph_ps (__m128h a);
VCVTPH2PSX __m256 _mm256_mask_cvtxph_ps (__m256 src, __mmask8 k, __m128h a);
VCVTPH2PSX __m256 _mm256_maskz_cvtxph_ps (__mmask8 k, __m128h a);
VCVTPH2PSX __m512 _mm512_cvtxph_ps (__m256h a);
VCVTPH2PSX __m512 _mm512_mask_cvtxph_ps (__m512 src, __mmask16 k, __m256h a);
VCVTPH2PSX __m512 _mm512_maskz_cvtxph_ps (__mmask16 k, __m256h a);
SIMD Floating-Point Exceptions
VEX-encoded instructions: Invalid.
EVEX-encoded instructions: Invalid.
EVEX-encoded instructions with broadcast (VCVTPH2PSX): Invalid, Denormal.
Other Exceptions
VEX-encoded instructions, see Table 2-26, “Type 11 Class Exception Conditions” (do not report #AC).
EVEX-encoded instructions, see Table 2-62, “Type E11 Class Exception Conditions.”
EVEX-encoded instructions with broadcast (VCVTPH2PSX), see Table 2-46, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If VEX.W=1.
#UD
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
VCVTPH2PS/VCVTPH2PSX-Convert Packed FP16 Values to Single Precision Floating-Point Values
Vol. 2C
5-57
VCVTPH2QQ-Convert Packed FP16 Values to Signed Quadword Integer Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.66.MAP5.W0 7B /r
A
V/V
(AVX512_FP16
Convert two packed FP16 values in
VCVTPH2QQ xmm1{k1}{z},
AND AVX512VL)
xmm2/m32/m16bcst to two signed quadword
xmm2/m32/m16bcst
OR AVX10.1
integers, and store the result in xmm1 subject to
writemask k1.
EVEX.256.66.MAP5.W0 7B /r
A
V/V
(AVX512_FP16
Convert four packed FP16 values in
VCVTPH2QQ ymm1{k1}{z},
AND AVX512VL)
xmm2/m64/m16bcst to four signed quadword
xmm2/m64/m16bcst
OR AVX10.1
integers, and store the result in ymm1 subject to
writemask k1.
EVEX.512.66.MAP5.W0 7B /r
A
V/V
AVX512_FP16
Convert eight packed FP16 values in
VCVTPH2QQ zmm1{k1}{z},
OR AVX10.1
xmm2/m128/m16bcst to eight signed quadword
xmm2/m128/m16bcst {er}
integers, and store the result in zmm1 subject to
writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Quarter
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed FP16 values in the source operand to signed quadword integers in destination
operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value
80000000_00000000H is returned.
The destination elements are updated according to the writemask.
VCVTPH2QQ-Convert Packed FP16 Values to Signed Quadword Integer Values
Vol. 2C
5-58
Operation
VCVTPH2QQ DEST, SRC
VL = 128, 256 or 512
KL := VL / 64
IF *SRC is a register* and (VL = 512) and (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.fp16[0]
ELSE
tsrc := SRC.fp16[j]
DEST.qword[j] := Convert_fp16_to_integer64(tsrc)
ELSE IF *zeroing*:
DEST.qword[j] := 0
// else dest.qword[j] remains unchanged
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPH2QQ __m512i _mm512_cvt_roundph_epi64 (__m128h a, int rounding);
VCVTPH2QQ __m512i _mm512_mask_cvt_roundph_epi64 (__m512i src, __mmask8 k, __m128h a, int rounding);
VCVTPH2QQ __m512i _mm512_maskz_cvt_roundph_epi64 (__mmask8 k, __m128h a, int rounding);
VCVTPH2QQ __m128i _mm_cvtph_epi64 (__m128h a);
VCVTPH2QQ __m128i _mm_mask_cvtph_epi64 (__m128i src, __mmask8 k, __m128h a);
VCVTPH2QQ __m128i _mm_maskz_cvtph_epi64 (__mmask8 k, __m128h a);
VCVTPH2QQ __m256i _mm256_cvtph_epi64 (__m128h a);
VCVTPH2QQ __m256i _mm256_mask_cvtph_epi64 (__m256i src, __mmask8 k, __m128h a);
VCVTPH2QQ __m256i _mm256_maskz_cvtph_epi64 (__mmask8 k, __m128h a);
VCVTPH2QQ __m512i _mm512_cvtph_epi64 (__m128h a);
VCVTPH2QQ __m512i _mm512_mask_cvtph_epi64 (__m512i src, __mmask8 k, __m128h a);
VCVTPH2QQ __m512i _mm512_maskz_cvtph_epi64 (__mmask8 k, __m128h a);
SIMD Floating-Point Exceptions
Invalid, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
VCVTPH2QQ-Convert Packed FP16 Values to Signed Quadword Integer Values
Vol. 2C
5-59
VCVTPH2UDQ-Convert Packed FP16 Values to Unsigned Doubleword Integers
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.NP.MAP5.W0 79 /r
A
V/V
(AVX512_FP16
Convert four packed FP16 values in
VCVTPH2UDQ xmm1{k1}{z},
AND AVX512VL)
xmm2/m64/m16bcst to four unsigned
xmm2/m64/m16bcst
OR AVX10.1
doubleword integers, and store the result in
xmm1 subject to writemask k1.
EVEX.256.NP.MAP5.W0 79 /r
A
V/V
(AVX512_FP16
Convert eight packed FP16 values in
VCVTPH2UDQ ymm1{k1}{z},
AND AVX512VL)
xmm2/m128/m16bcst to eight unsigned
xmm2/m128/m16bcst
OR AVX10.1
doubleword integers, and store the result in
ymm1 subject to writemask k1.
EVEX.512.NP.MAP5.W0 79 /r
A
V/V
AVX512_FP16
Convert sixteen packed FP16 values in
VCVTPH2UDQ zmm1{k1}{z},
OR AVX10.1
ymm2/m256/m16bcst to sixteen unsigned
ymm2/m256/m16bcst {er}
doubleword integers, and store the result in
zmm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Half
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed FP16 values in the source operand to unsigned doubleword integers in destination
operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the integer value FFFFFFFFH
is returned.
The destination elements are updated according to the writemask.
VCVTPH2UDQ-Convert Packed FP16 Values to Unsigned Doubleword Integers
Vol. 2C
5-60
Operation
VCVTPH2UDQ DEST, SRC
VL = 128, 256 or 512
KL := VL / 32
IF *SRC is a register* and (VL = 512) and (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.fp16[0]
ELSE
tsrc := SRC.fp16[j]
DEST.dword[j] := Convert_fp16_to_unsigned_integer32(tsrc)
ELSE IF *zeroing*:
DEST.dword[j] := 0
// else dest.dword[j] remains unchanged
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPH2UDQ __m512i _mm512_cvt_roundph_epu32 (__m256h a, int rounding);
VCVTPH2UDQ __m512i _mm512_mask_cvt_roundph_epu32 (__m512i src, __mmask16 k, __m256h a, int rounding);
VCVTPH2UDQ __m512i _mm512_maskz_cvt_roundph_epu32 (__mmask16 k, __m256h a, int rounding);
VCVTPH2UDQ __m128i _mm_cvtph_epu32 (__m128h a);
VCVTPH2UDQ __m128i _mm_mask_cvtph_epu32 (__m128i src, __mmask8 k, __m128h a);
VCVTPH2UDQ __m128i _mm_maskz_cvtph_epu32 (__mmask8 k, __m128h a);
VCVTPH2UDQ __m256i _mm256_cvtph_epu32 (__m128h a);
VCVTPH2UDQ __m256i _mm256_mask_cvtph_epu32 (__m256i src, __mmask8 k, __m128h a);
VCVTPH2UDQ __m256i _mm256_maskz_cvtph_epu32 (__mmask8 k, __m128h a);
VCVTPH2UDQ __m512i _mm512_cvtph_epu32 (__m256h a);
VCVTPH2UDQ __m512i _mm512_mask_cvtph_epu32 (__m512i src, __mmask16 k, __m256h a);
VCVTPH2UDQ __m512i _mm512_maskz_cvtph_epu32 (__mmask16 k, __m256h a);
SIMD Floating-Point Exceptions
Invalid, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
VCVTPH2UDQ-Convert Packed FP16 Values to Unsigned Doubleword Integers
Vol. 2C
5-61
VCVTPH2UQQ-Convert Packed FP16 Values to Unsigned Quadword Integers
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.66.MAP5.W0 79 /r
A
V/V
(AVX512_FP16
Convert two packed FP16 values in
VCVTPH2UQQ xmm1{k1}{z},
AND AVX512VL)
xmm2/m32/m16bcst to two unsigned quadword
xmm2/m32/m16bcst
OR AVX10.1
integers, and store the result in xmm1 subject to
writemask k1.
EVEX.256.66.MAP5.W0 79 /r
A
V/V
(AVX512_FP16
Convert four packed FP16 values in
VCVTPH2UQQ ymm1{k1}{z},
AND AVX512VL)
xmm2/m64/m16bcst to four unsigned quadword
xmm2/m64/m16bcst
OR AVX10.1
integers, and store the result in ymm1 subject to
writemask k1.
EVEX.512.66.MAP5.W0 79 /r
A
V/V
AVX512_FP16
Convert eight packed FP16 values in
VCVTPH2UQQ zmm1{k1}{z},
OR AVX10.1
xmm2/m128/m16bcst to eight unsigned
xmm2/m128/m16bcst {er}
quadword integers, and store the result in zmm1
subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Quarter
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed FP16 values in the source operand to unsigned quadword integers in destination
operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the integer value
FFFFFFFF_FFFFFFFFH is returned.
The destination elements are updated according to the writemask.
VCVTPH2UQQ-Convert Packed FP16 Values to Unsigned Quadword Integers
Vol. 2C
5-62
Operation
VCVTPH2UQQ DEST, SRC
VL = 128, 256 or 512
KL := VL / 64
IF *SRC is a register* and (VL = 512) and (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.fp16[0]
ELSE
tsrc := SRC.fp16[j]
DEST.qword[j] := Convert_fp16_to_unsigned_integer64(tsrc)
ELSE IF *zeroing*:
DEST.qword[j] := 0
// else dest.qword[j] remains unchanged
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPH2UQQ __m512i _mm512_cvt_roundph_epu64 (__m128h a, int rounding);
VCVTPH2UQQ __m512i _mm512_mask_cvt_roundph_epu64 (__m512i src, __mmask8 k, __m128h a, int rounding);
VCVTPH2UQQ __m512i _mm512_maskz_cvt_roundph_epu64 (__mmask8 k, __m128h a, int rounding);
VCVTPH2UQQ __m128i _mm_cvtph_epu64 (__m128h a);
VCVTPH2UQQ __m128i _mm_mask_cvtph_epu64 (__m128i src, __mmask8 k, __m128h a);
VCVTPH2UQQ __m128i _mm_maskz_cvtph_epu64 (__mmask8 k, __m128h a);
VCVTPH2UQQ __m256i _mm256_cvtph_epu64 (__m128h a);
VCVTPH2UQQ __m256i _mm256_mask_cvtph_epu64 (__m256i src, __mmask8 k, __m128h a);
VCVTPH2UQQ __m256i _mm256_maskz_cvtph_epu64 (__mmask8 k, __m128h a);
VCVTPH2UQQ __m512i _mm512_cvtph_epu64 (__m128h a);
VCVTPH2UQQ __m512i _mm512_mask_cvtph_epu64 (__m512i src, __mmask8 k, __m128h a);
VCVTPH2UQQ __m512i _mm512_maskz_cvtph_epu64 (__mmask8 k, __m128h a);
SIMD Floating-Point Exceptions
Invalid, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
VCVTPH2UQQ-Convert Packed FP16 Values to Unsigned Quadword Integers
Vol. 2C
5-63
VCVTPH2UW-Convert Packed FP16 Values to Unsigned Word Integers
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.NP.MAP5.W0 7D /r
A
V/V
(AVX512_FP16
Convert packed FP16 values in
VCVTPH2UW xmm1{k1}{z},
AND AVX512VL)
xmm2/m128/m16bcst to unsigned word integers,
xmm2/m128/m16bcst
OR AVX10.1
and store the result in xmm1.
EVEX.256.NP.MAP5.W0 7D /r
A
V/V
(AVX512_FP16
Convert packed FP16 values in
VCVTPH2UW ymm1{k1}{z},
AND AVX512VL)
ymm2/m256/m16bcst to unsigned word integers,
ymm2/m256/m16bcst
OR AVX10.1
and store the result in ymm1.
EVEX.512.NP.MAP5.W0 7D /r
A
V/V
AVX512_FP16
Convert packed FP16 values in
VCVTPH2UW zmm1{k1}{z},
OR AVX10.1
zmm2/m512/m16bcst to unsigned word integers,
zmm2/m512/m16bcst {er}
and store the result in zmm1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed FP16 values in the source operand to unsigned word integers in the destination
operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the integer value FFFFH is
returned.
The destination elements are updated according to the writemask.
Operation
VCVTPH2UW DEST, SRC
VL = 128, 256 or 512
KL := VL / 16
IF *SRC is a register* and (VL = 512) and (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.fp16[0]
ELSE
tsrc := SRC.fp16[j]
DEST.word[j] := Convert_fp16_to_unsigned_integer16(tsrc)
ELSE IF *zeroing*:
DEST.word[j] := 0
// else dest.word[j] remains unchanged
DEST[MAXVL-1:VL] := 0
VCVTPH2UW-Convert Packed FP16 Values to Unsigned Word Integers
Vol. 2C
5-64
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPH2UW __m512i _mm512_cvt_roundph_epu16 (__m512h a, int sae);
VCVTPH2UW __m512i _mm512_mask_cvt_roundph_epu16 (__m512i src, __mmask32 k, __m512h a, int sae);
VCVTPH2UW __m512i _mm512_maskz_cvt_roundph_epu16 (__mmask32 k, __m512h a, int sae);
VCVTPH2UW __m128i _mm_cvtph_epu16 (__m128h a);
VCVTPH2UW __m128i _mm_mask_cvtph_epu16 (__m128i src, __mmask8 k, __m128h a);
VCVTPH2UW __m128i _mm_maskz_cvtph_epu16 (__mmask8 k, __m128h a);
VCVTPH2UW __m256i _mm256_cvtph_epu16 (__m256h a);
VCVTPH2UW __m256i _mm256_mask_cvtph_epu16 (__m256i src, __mmask16 k, __m256h a);
VCVTPH2UW __m256i _mm256_maskz_cvtph_epu16 (__mmask16 k, __m256h a);
VCVTPH2UW __m512i _mm512_cvtph_epu16 (__m512h a);
VCVTPH2UW __m512i _mm512_mask_cvtph_epu16 (__m512i src, __mmask32 k, __m512h a);
VCVTPH2UW __m512i _mm512_maskz_cvtph_epu16 (__mmask32 k, __m512h a);
SIMD Floating-Point Exceptions
Invalid, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
VCVTPH2UW-Convert Packed FP16 Values to Unsigned Word Integers
Vol. 2C
5-65
VCVTPH2W-Convert Packed FP16 Values to Signed Word Integers
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.66.MAP5.W0 7D /r
A
V/V
(AVX512_FP16
Convert packed FP16 values in
VCVTPH2W xmm1{k1}{z},
AND AVX512VL)
xmm2/m128/m16bcst to signed word integers,
xmm2/m128/m16bcst
OR AVX10.1
and store the result in xmm1.
EVEX.256.66.MAP5.W0 7D /r
A
V/V
(AVX512_FP16
Convert packed FP16 values in
VCVTPH2W ymm1{k1}{z},
AND AVX512VL)
ymm2/m256/m16bcst to signed word integers,
ymm2/m256/m16bcst
OR AVX10.1
and store the result in ymm1.
EVEX.512.66.MAP5.W0 7D /r
A
V/V
AVX512_FP16
Convert packed FP16 values in
VCVTPH2W zmm1{k1}{z},
OR AVX10.1
zmm2/m512/m16bcst to signed word integers,
zmm2/m512/m16bcst {er}
and store the result in zmm1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed FP16 values in the source operand to signed word integers in the destination
operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value
8000H is returned.
The destination elements are updated according to the writemask.
Operation
VCVTPH2W DEST, SRC
VL = 128, 256 or 512
KL := VL / 16
IF *SRC is a register* and (VL = 512) and (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.fp16[0]
ELSE
tsrc := SRC.fp16[j]
DEST.word[j] := Convert_fp16_to_integer16(tsrc)
ELSE IF *zeroing*:
DEST.word[j] := 0
// else dest.word[j] remains unchanged
DEST[MAXVL-1:VL] := 0
VCVTPH2W-Convert Packed FP16 Values to Signed Word Integers
Vol. 2C
5-66
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPH2W __m512i _mm512_cvt_roundph_epi16 (__m512h a, int rounding);
VCVTPH2W __m512i _mm512_mask_cvt_roundph_epi16 (__m512i src, __mmask32 k, __m512h a, int rounding);
VCVTPH2W __m512i _mm512_maskz_cvt_roundph_epi16 (__mmask32 k, __m512h a, int rounding);
VCVTPH2W __m128i _mm_cvtph_epi16 (__m128h a);
VCVTPH2W __m128i _mm_mask_cvtph_epi16 (__m128i src, __mmask8 k, __m128h a);
VCVTPH2W __m128i _mm_maskz_cvtph_epi16 (__mmask8 k, __m128h a);
VCVTPH2W __m256i _mm256_cvtph_epi16 (__m256h a);
VCVTPH2W __m256i _mm256_mask_cvtph_epi16 (__m256i src, __mmask16 k, __m256h a);
VCVTPH2W __m256i _mm256_maskz_cvtph_epi16 (__mmask16 k, __m256h a);
VCVTPH2W __m512i _mm512_cvtph_epi16 (__m512h a);
VCVTPH2W __m512i _mm512_mask_cvtph_epi16 (__m512i src, __mmask32 k, __m512h a);
VCVTPH2W __m512i _mm512_maskz_cvtph_epi16 (__mmask32 k, __m512h a);
SIMD Floating-Point Exceptions
Invalid, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
VCVTPH2W-Convert Packed FP16 Values to Signed Word Integers
Vol. 2C
5-67
VCVTPS2PH-Convert Single Precision FP Value to 16-bit FP Value
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
VEX.128.66.0F3A.W0 1D /r ib
A
V/V
F16C
Convert four packed single precision floating-point
VCVTPS2PH xmm1/m64, xmm2,
values in xmm2 to packed half-precision (16-bit)
imm8
floating-point values in xmm1/m64. Imm8 provides
rounding controls.
VEX.256.66.0F3A.W0 1D /r ib
A
V/V
F16C
Convert eight packed single precision floating-point
VCVTPS2PH xmm1/m128, ymm2,
values in ymm2 to packed half-precision (16-bit)
imm8
floating-point values in xmm1/m128. Imm8 provides
rounding controls.
EVEX.128.66.0F3A.W0 1D /r ib
B
V/V
(AVX512VL AND
Convert four packed single-precision floating-point
VCVTPS2PH xmm1/m64 {k1}{z},
AVX512F) OR
values in xmm2 to packed half-precision (16-bit)
xmm2, imm8
AVX10.1
floating-point values in xmm1/m64. Imm8 provides
rounding controls.
EVEX.256.66.0F3A.W0 1D /r ib
B
V/V
(AVX512VL AND
Convert eight packed single-precision floating-point
VCVTPS2PH xmm1/m128 {k1}{z},
AVX512F) OR
values in ymm2 to packed half-precision (16-bit)
ymm2, imm8
AVX10.1
floating-point values in xmm1/m128. Imm8 provides
rounding controls.
EVEX.512.66.0F3A.W0 1D /r ib
B
V/V
AVX512F
Convert sixteen packed single-precision floating-
VCVTPS2PH ymm1/m256 {k1}{z},
OR AVX10.1
point values in zmm2 to packed half-precision (16-
zmm2 {sae}, imm8
bit) floating-point values in ymm1/m256. Imm8
provides rounding controls.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:r/m (w)
ModRM:reg (r)
imm8
N/A
B
Half Mem
ModRM:r/m (w)
ModRM:reg (r)
imm8
N/A
Description
Convert packed single precision floating values in the source operand to half-precision (16-bit) floating-point
values and store to the destination operand. The rounding mode is specified using the immediate field (imm8).
Underflow results (i.e., tiny results) are converted to denormals. MXCSR.FTZ is ignored. If a source element is
denormal relative to the input format with DM masked and at least one of PM or UM unmasked; a SIMD exception
will be raised with DE, UE and PE set.
VCVTPS2PH xmm1/mem64, xmm2, imm8
127
96
95
64
63
32
31
0
VS3
VS2
VS1
VS0
xmm2
convert
convert
convert
convert
127
96
95
64
63
48
47
32
31
16
15
0
VH3
VH2
VH1
VH0
xmm1/mem64
Figure 5-7. VCVTPS2PH (128-bit Version)
VCVTPS2PH-Convert Single Precision FP Value to 16-bit FP Value
Vol. 2C
5-68
The immediate byte defines several bit fields that control rounding operation. The effect and encoding of the RC
field are listed in Table 5-3.
Table 5-3. Immediate Byte Encoding for 16-bit Floating-Point Conversion Instructions
Bits
Field Name/value
Description
Comment
Imm[1:0]
RC=00B
Round to nearest even
If Imm[2] = 0
RC=01B
Round down
RC=10B
Round up
RC=11B
Truncate
Imm[2]
MS1=0
Use imm[1:0] for rounding
Ignore MXCSR.RC
MS1=1
Use MXCSR.RC for rounding
Imm[7:3]
Ignored
Ignored by processor
VEX.128 version: The source operand is a XMM register. The destination operand is a XMM register or 64-bit
memory location. If the destination operand is a register then the upper bits (MAXVL-1:64) of corresponding
register are zeroed.
VEX.256 version: The source operand is a YMM register. The destination operand is a XMM register or 128-bit
memory location. If the destination operand is a register, the upper bits (MAXVL-1:128) of the corresponding desti-
nation register are zeroed.
Note: VEX.vvvv and EVEX.vvvv are reserved (must be 1111b).
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register. The destination operand is a
YMM/XMM/XMM (low 64-bits) register or a 256/128/64-bit memory location, conditionally updated with writemask
k1. Bits (MAXVL-1:256/128/64) of the corresponding destination register are zeroed.
Operation
vCvt_s2h(SRC1[31:0])
{
IF Imm[2] = 0
THEN
; using Imm[1:0] for rounding control, see Table 5-3
RETURN Cvt_Single_Precision_To_Half_Precision_FP_Imm(SRC1[31:0]);
ELSE
; using MXCSR.RC for rounding control
RETURN Cvt_Single_Precision_To_Half_Precision_FP_Mxcsr(SRC1[31:0]);
FI;
}
VCVTPS2PH-Convert Single Precision FP Value to 16-bit FP Value
Vol. 2C
5-69
VCVTPS2PH (EVEX Encoded Versions) When DEST is a Register
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 16
k := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] :=
vCvt_s2h(SRC[k+31:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+15:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0
VCVTPS2PH (EVEX Encoded Versions) When DEST is Memory
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 16
k := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] :=
vCvt_s2h(SRC[k+31:k])
ELSE
*DEST[i+15:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VCVTPS2PH (VEX.256 Encoded Version)
DEST[15:0] := vCvt_s2h(SRC1[31:0]);
DEST[31:16] := vCvt_s2h(SRC1[63:32]);
DEST[47:32] := vCvt_s2h(SRC1[95:64]);
DEST[63:48] := vCvt_s2h(SRC1[127:96]);
DEST[79:64] := vCvt_s2h(SRC1[159:128]);
DEST[95:80] := vCvt_s2h(SRC1[191:160]);
DEST[111:96] := vCvt_s2h(SRC1[223:192]);
DEST[127:112] := vCvt_s2h(SRC1[255:224]);
DEST[MAXVL-1:128] := 0
VCVTPS2PH (VEX.128 Encoded Version)
DEST[15:0] := vCvt_s2h(SRC1[31:0]);
DEST[31:16] := vCvt_s2h(SRC1[63:32]);
DEST[47:32] := vCvt_s2h(SRC1[95:64]);
DEST[63:48] := vCvt_s2h(SRC1[127:96]);
DEST[MAXVL-1:64] := 0
Flags Affected
None.
VCVTPS2PH-Convert Single Precision FP Value to 16-bit FP Value
Vol. 2C
5-70
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPS2PH __m256i _mm512_cvtps_ph(__m512 a);
VCVTPS2PH __m256i _mm512_mask_cvtps_ph(__m256i s, __mmask16 k,__m512 a);
VCVTPS2PH __m256i _mm512_maskz_cvtps_ph(__mmask16 k,__m512 a);
VCVTPS2PH __m256i _mm512_cvt_roundps_ph(__m512 a, const int imm);
VCVTPS2PH __m256i _mm512_mask_cvt_roundps_ph(__m256i s, __mmask16 k,__m512 a, const int imm);
VCVTPS2PH __m256i _mm512_maskz_cvt_roundps_ph(__mmask16 k,__m512 a, const int imm);
VCVTPS2PH __m128i _mm256_mask_cvtps_ph(__m128i s, __mmask8 k,__m256 a);
VCVTPS2PH __m128i _mm256_maskz_cvtps_ph(__mmask8 k,__m256 a);
VCVTPS2PH __m128i _mm_mask_cvtps_ph(__m128i s, __mmask8 k,__m128 a);
VCVTPS2PH __m128i _mm_maskz_cvtps_ph(__mmask8 k,__m128 a);
VCVTPS2PH __m128i _mm_cvtps_ph ( __m128 m1, const int imm);
VCVTPS2PH __m128i _mm256_cvtps_ph(__m256 m1, const int imm);
SIMD Floating-Point Exceptions
Invalid, Underflow, Overflow, Precision, Denormal (if MXCSR.DAZ=0).
Other Exceptions
VEX-encoded instructions, see Table 2-26, “Type 11 Class Exception Conditions” (do not report #AC);
EVEX-encoded instructions, see Table 2-62, “Type E11 Class Exception Conditions.”
Additionally:
#UD
If VEX.W=1.
#UD
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
VCVTPS2PH-Convert Single Precision FP Value to 16-bit FP Value
Vol. 2C
5-71
VCVTPS2PHX-Convert Packed Single Precision Floating-Point Values to Packed FP16 Values
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.66.MAP5.W0 1D /r
A
V/V
(AVX512_FP16
Convert four packed single precision floating-
VCVTPS2PHX xmm1{k1}{z},
AND AVX512VL)
point values in xmm2/m128/m32bcst to
xmm2/m128/m32bcst
OR AVX10.1
packed FP16 values, and store the result in
xmm1 subject to writemask k1.
EVEX.256.66.MAP5.W0 1D /r
A
V/V
(AVX512_FP16
Convert eight packed single precision floating-
VCVTPS2PHX xmm1{k1}{z},
AND AVX512VL)
point values in ymm2/m256/m32bcst to
ymm2/m256/m32bcst
OR AVX10.1
packed FP16 values, and store the result in
xmm1 subject to writemask k1.
EVEX.512.66.MAP5.W0 1D /r
A
V/V
AVX512_FP16
Convert sixteen packed single precision
VCVTPS2PHX ymm1{k1}{z},
OR AVX10.1
floating-point values in zmm2 /m512/m32bcst
zmm2/m512/m32bcst {er}
to packed FP16 values, and store the result in
ymm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed single precision floating values in the source operand to FP16 values and stores to
the destination operand.
The VCVTPS2PHX instruction supports broadcasting.
This instruction uses MXCSR.DAZ for handling FP32 inputs. FP16 outputs can be normal or denormal numbers, and
are not conditionally flushed based on MXCSR settings.
Operation
VCVTPS2PHX DEST, SRC (AVX512_FP16 Load Version With Broadcast Support)
VL = 128, 256, or 512
KL := VL / 32
IF *SRC is a register* and (VL == 512) and (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.fp32[0]
ELSE
tsrc := SRC.fp32[j]
DEST.fp16[j] := Convert_fp32_to_fp16(tsrc)
ELSE IF *zeroing*:
DEST.fp16[j] := 0
// else dest.fp16[j] remains unchanged
DEST[MAXVL-1:VL/2] := 0
VCVTPS2PHX-Convert Packed Single Precision Floating-Point Values to Packed FP16 Values
Vol. 2C
5-72
Flags Affected
None.
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPS2PHX __m256h _mm512_cvtx_roundps_ph (__m512 a, int rounding);
VCVTPS2PHX __m256h _mm512_mask_cvtx_roundps_ph (__m256h src, __mmask16 k, __m512 a, int rounding);
VCVTPS2PHX __m256h _mm512_maskz_cvtx_roundps_ph (__mmask16 k, __m512 a, int rounding);
VCVTPS2PHX __m128h _mm_cvtxps_ph (__m128 a);
VCVTPS2PHX __m128h _mm_mask_cvtxps_ph (__m128h src, __mmask8 k, __m128 a);
VCVTPS2PHX __m128h _mm_maskz_cvtxps_ph (__mmask8 k, __m128 a);
VCVTPS2PHX __m128h _mm256_cvtxps_ph (__m256 a);
VCVTPS2PHX __m128h _mm256_mask_cvtxps_ph (__m128h src, __mmask8 k, __m256 a);
VCVTPS2PHX __m128h _mm256_maskz_cvtxps_ph (__mmask8 k, __m256 a);
VCVTPS2PHX __m256h _mm512_cvtxps_ph (__m512 a);
VCVTPS2PHX __m256h _mm512_mask_cvtxps_ph (__m256h src, __mmask16 k, __m512 a);
VCVTPS2PHX __m256h _mm512_maskz_cvtxps_ph (__mmask16 k, __m512 a);
SIMD Floating-Point Exceptions
Invalid, Underflow, Overflow, Precision, Denormal (if MXCSR.DAZ=0).
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If VEX.W=1.
#UD
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
VCVTPS2PHX-Convert Packed Single Precision Floating-Point Values to Packed FP16 Values
Vol. 2C
5-73
VCVTPS2QQ-Convert Packed Single Precision Floating-Point Values to Packed Signed
Quadword Integer Values
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.66.0F.W0 7B /r
A
V/V
(AVX512VL AND
Convert two packed single precision floating-point values
VCVTPS2QQ xmm1 {k1}{z},
AVX512DQ) OR
from xmm2/m64/m32bcst to two packed signed
xmm2/m64/m32bcst
AVX10.1
quadword values in xmm1 subject to writemask k1.
EVEX.256.66.0F.W0 7B /r
A
V/V
(AVX512VL AND
Convert four packed single precision floating-point values
VCVTPS2QQ ymm1 {k1}{z},
AVX512DQ) OR
from xmm2/m128/m32bcst to four packed signed
xmm2/m128/m32bcst
AVX10.1
quadword values in ymm1 subject to writemask k1.
EVEX.512.66.0F.W0 7B /r
A
V/V
AVX512DQ
Convert eight packed single precision floating-point values
VCVTPS2QQ zmm1 {k1}{z},
OR AVX10.1
from ymm2/m256/m32bcst to eight packed signed
ymm2/m256/m32bcst {er}
quadword values in zmm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Half
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts eight packed single precision floating-point values in the source operand to eight signed quadword inte-
gers in the destination operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value
80000000_00000000H is returned.
The source operand is a YMM/XMM/XMM (low 64- bits) register or a 256/128/64-bit memory location. The destina-
tion operation is a ZMM/YMM/XMM register conditionally updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VCVTPS2QQ (EVEX Encoded Versions) When SRC Operand is a Register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL == 512) AND (EVEX.b == 1)
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
ELSE
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
FI;
FOR j := 0 TO KL-1
i := j * 64
k := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] :=
Convert_Single_Precision_To_QuadInteger(SRC[k+31:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
VCVTPS2QQ-Convert Packed Single Precision Floating-Point Values to Packed Signed Quadword Integer Values
Vol. 2C
5-74
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VCVTPS2QQ (EVEX Encoded Versions) When SRC Operand is a Memory Source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
k := j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[i+63:i] :=
Convert_Single_Precision_To_QuadInteger(SRC[31:0])
ELSE
DEST[i+63:i] :=
Convert_Single_Precision_To_QuadInteger(SRC[k+31:k])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPS2QQ __m512i _mm512_cvtps_epi64( __m512 a);
VCVTPS2QQ __m512i _mm512_mask_cvtps_epi64( __m512i s, __mmask16 k, __m512 a);
VCVTPS2QQ __m512i _mm512_maskz_cvtps_epi64( __mmask16 k, __m512 a);
VCVTPS2QQ __m512i _mm512_cvt_roundps_epi64( __m512 a, int r);
VCVTPS2QQ __m512i _mm512_mask_cvt_roundps_epi64( __m512i s, __mmask16 k, __m512 a, int r);
VCVTPS2QQ __m512i _mm512_maskz_cvt_roundps_epi64( __mmask16 k, __m512 a, int r);
VCVTPS2QQ __m256i _mm256_cvtps_epi64( __m256 a);
VCVTPS2QQ __m256i _mm256_mask_cvtps_epi64( __m256i s, __mmask8 k, __m256 a);
VCVTPS2QQ __m256i _mm256_maskz_cvtps_epi64( __mmask8 k, __m256 a);
VCVTPS2QQ __m128i _mm_cvtps_epi64( __m128 a);
VCVTPS2QQ __m128i _mm_mask_cvtps_epi64( __m128i s, __mmask8 k, __m128 a);
VCVTPS2QQ __m128i _mm_maskz_cvtps_epi64( __mmask8 k, __m128 a);
SIMD Floating-Point Exceptions
Invalid, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VCVTPS2QQ-Convert Packed Single Precision Floating-Point Values to Packed Signed Quadword Integer Values
Vol. 2C
5-75
VCVTPS2UDQ-Convert Packed Single Precision Floating-Point Values to Packed Unsigned
Doubleword Integer Values
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.0F.W0 79 /r
A
V/V
(AVX512VL AND
Convert four packed single precision floating-
VCVTPS2UDQ xmm1 {k1}{z},
AVX512F) OR
point values from xmm2/m128/m32bcst to four
xmm2/m128/m32bcst
AVX10.1
packed unsigned doubleword values in xmm1
subject to writemask k1.
EVEX.256.0F.W0 79 /r
A
V/V
(AVX512VL AND
Convert eight packed single precision floating-
VCVTPS2UDQ ymm1 {k1}{z},
AVX512F) OR
point values from ymm2/m256/m32bcst to eight
ymm2/m256/m32bcst
AVX10.1
packed unsigned doubleword values in ymm1
subject to writemask k1.
EVEX.512.0F.W0 79 /r
A
V/V
AVX512F
Convert sixteen packed single precision floating-
VCVTPS2UDQ zmm1 {k1}{z},
OR AVX10.1
point values from zmm2/m512/m32bcst to
zmm2/m512/m32bcst {er}
sixteen packed unsigned doubleword values in
zmm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts sixteen packed single precision floating-point values in the source operand to sixteen unsigned double-
word integers in the destination operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the integer value FFFFFFFFH
is returned.
The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector
broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
VCVTPS2UDQ-Convert Packed Single Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values
Vol. 2C
5-76
Operation
VCVTPS2UDQ (EVEX Encoded Versions) When SRC Operand is a Register
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
ELSE
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
FI;
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] :=
Convert_Single_Precision_Floating_Point_To_UInteger(SRC[i+31:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VCVTPS2UDQ (EVEX Encoded Versions) When SRC Operand is a Memory Source
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no *
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i] :=
Convert_Single_Precision_Floating_Point_To_UInteger(SRC[31:0])
ELSE
DEST[i+31:i] :=
Convert_Single_Precision_Floating_Point_To_UInteger(SRC[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VCVTPS2UDQ-Convert Packed Single Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values
Vol. 2C
5-77
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPS2UDQ __m512i _mm512_cvtps_epu32( __m512 a);
VCVTPS2UDQ __m512i _mm512_mask_cvtps_epu32( __m512i s, __mmask16 k, __m512 a);
VCVTPS2UDQ __m512i _mm512_maskz_cvtps_epu32( __mmask16 k, __m512 a);
VCVTPS2UDQ __m512i _mm512_cvt_roundps_epu32( __m512 a, int r);
VCVTPS2UDQ __m512i _mm512_mask_cvt_roundps_epu32( __m512i s, __mmask16 k, __m512 a, int r);
VCVTPS2UDQ __m512i _mm512_maskz_cvt_roundps_epu32( __mmask16 k, __m512 a, int r);
VCVTPS2UDQ __m256i _mm256_cvtps_epu32( __m256d a);
VCVTPS2UDQ __m256i _mm256_mask_cvtps_epu32( __m256i s, __mmask8 k, __m256 a);
VCVTPS2UDQ __m256i _mm256_maskz_cvtps_epu32( __mmask8 k, __m256 a);
VCVTPS2UDQ __m128i _mm_cvtps_epu32( __m128 a);
VCVTPS2UDQ __m128i _mm_mask_cvtps_epu32( __m128i s, __mmask8 k, __m128 a);
VCVTPS2UDQ __m128i _mm_maskz_cvtps_epu32( __mmask8 k, __m128 a);
SIMD Floating-Point Exceptions
Invalid, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VCVTPS2UDQ-Convert Packed Single Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values
Vol. 2C
5-78
VCVTPS2UQQ-Convert Packed Single Precision Floating-Point Values to Packed Unsigned
Quadword Integer Values
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.66.0F.W0 79 /r
A
V/V
(AVX512VL AND
Convert two packed single precision floating-point values
VCVTPS2UQQ xmm1 {k1}{z},
AVX512DQ) OR
from zmm2/m64/m32bcst to two packed unsigned
xmm2/m64/m32bcst
AVX10.1
quadword values in zmm1 subject to writemask k1.
EVEX.256.66.0F.W0 79 /r
A
V/V
(AVX512VL AND
Convert four packed single precision floating-point values
VCVTPS2UQQ ymm1 {k1}{z},
AVX512DQ) OR
from xmm2/m128/m32bcst to four packed unsigned
xmm2/m128/m32bcst
AVX10.1
quadword values in ymm1 subject to writemask k1.
EVEX.512.66.0F.W0 79 /r
A
V/V
AVX512DQ
Convert eight packed single precision floating-point values
VCVTPS2UQQ zmm1 {k1}{z},
OR AVX10.1
from ymm2/m256/m32bcst to eight packed unsigned
ymm2/m256/m32bcst {er}
quadword values in zmm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Half
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts up to eight packed single precision floating-point values in the source operand to unsigned quadword
integers in the destination operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the integer value
FFFFFFFF_FFFFFFFFH is returned.
The source operand is a YMM/XMM/XMM (low 64- bits) register or a 256/128/64-bit memory location. The destina-
tion operation is a ZMM/YMM/XMM register conditionally updated with writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VCVTPS2UQQ (EVEX Encoded Versions) When SRC Operand is a Register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL == 512) AND (EVEX.b == 1)
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
ELSE
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
FI;
FOR j := 0 TO KL-1
i := j * 64
k := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] :=
Convert_Single_Precision_To_UQuadInteger(SRC[k+31:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
VCVTPS2UQQ-Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values
Vol. 2C
5-79
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VCVTPS2UQQ (EVEX Encoded Versions) When SRC Operand is a Memory Source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
k := j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[i+63:i] :=
Convert_Single_Precision_To_UQuadInteger(SRC[31:0])
ELSE
DEST[i+63:i] :=
Convert_Single_Precision_To_UQuadInteger(SRC[k+31:k])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPS2UQQ __m512i _mm512_cvtps_epu64( __m512 a);
VCVTPS2UQQ __m512i _mm512_mask_cvtps_epu64( __m512i s, __mmask16 k, __m512 a);
VCVTPS2UQQ __m512i _mm512_maskz_cvtps_epu64( __mmask16 k, __m512 a);
VCVTPS2UQQ __m512i _mm512_cvt_roundps_epu64( __m512 a, int r);
VCVTPS2UQQ __m512i _mm512_mask_cvt_roundps_epu64( __m512i s, __mmask16 k, __m512 a, int r);
VCVTPS2UQQ __m512i _mm512_maskz_cvt_roundps_epu64( __mmask16 k, __m512 a, int r);
VCVTPS2UQQ __m256i _mm256_cvtps_epu64( __m256 a);
VCVTPS2UQQ __m256i _mm256_mask_cvtps_epu64( __m256i s, __mmask8 k, __m256 a);
VCVTPS2UQQ __m256i _mm256_maskz_cvtps_epu64( __mmask8 k, __m256 a);
VCVTPS2UQQ __m128i _mm_cvtps_epu64( __m128 a);
VCVTPS2UQQ __m128i _mm_mask_cvtps_epu64( __m128i s, __mmask8 k, __m128 a);
VCVTPS2UQQ __m128i _mm_maskz_cvtps_epu64( __mmask8 k, __m128 a);
SIMD Floating-Point Exceptions
Invalid, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VCVTPS2UQQ-Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values
Vol. 2C
5-80
VCVTQQ2PD-Convert Packed Quadword Integers to Packed Double Precision Floating-Point
Values
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.F3.0F.W1 E6 /r
A
V/V
(AVX512VL AND
Convert two packed quadword integers from
VCVTQQ2PD xmm1 {k1}{z},
AVX512DQ) OR
xmm2/m128/m64bcst to packed double precision
xmm2/m128/m64bcst
AVX10.1
floating-point values in xmm1 with writemask k1.
EVEX.256.F3.0F.W1 E6 /r
A
V/V
(AVX512VL AND
Convert four packed quadword integers from
VCVTQQ2PD ymm1 {k1}{z},
AVX512DQ) OR
ymm2/m256/m64bcst to packed double precision
ymm2/m256/m64bcst
AVX10.1
floating-point values in ymm1 with writemask k1.
EVEX.512.F3.0F.W1 E6 /r
A
V/V
AVX512DQ
Convert eight packed quadword integers from
VCVTQQ2PD zmm1 {k1}{z},
OR AVX10.1
zmm2/m512/m64bcst to eight packed double precision
zmm2/m512/m64bcst {er}
floating-point values in zmm1 with writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts packed quadword integers in the source operand (second operand) to packed double precision floating-
point values in the destination operand (first operand).
The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operation
is a ZMM/YMM/XMM register conditionally updated with writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VCVTQQ2PD (EVEX2 Encoded Versions) When SRC Operand is a Register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL == 512) AND (EVEX.b == 1)
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
ELSE
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
FI;
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] :=
Convert_QuadInteger_To_Double_Precision_Floating_Point(SRC[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VCVTQQ2PD-Convert Packed Quadword Integers to Packed Double Precision Floating-Point Values
Vol. 2C
5-81
VCVTQQ2PD (EVEX Encoded Versions) when SRC Operand is a Memory Source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[i+63:i] :=
Convert_QuadInteger_To_Double_Precision_Floating_Point(SRC[63:0])
ELSE
DEST[i+63:i] :=
Convert_QuadInteger_To_Double_Precision_Floating_Point(SRC[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTQQ2PD __m512d _mm512_cvtepi64_pd( __m512i a);
VCVTQQ2PD __m512d _mm512_mask_cvtepi64_pd( __m512d s, __mmask16 k, __m512i a);
VCVTQQ2PD __m512d _mm512_maskz_cvtepi64_pd( __mmask16 k, __m512i a);
VCVTQQ2PD __m512d _mm512_cvt_roundepi64_pd( __m512i a, int r);
VCVTQQ2PD __m512d _mm512_mask_cvt_roundepi64_pd( __m512d s, __mmask8 k, __m512i a, int r);
VCVTQQ2PD __m512d _mm512_maskz_cvt_roundepi64_pd( __mmask8 k, __m512i a, int r);
VCVTQQ2PD __m256d _mm256_mask_cvtepi64_pd( __m256d s, __mmask8 k, __m256i a);
VCVTQQ2PD __m256d _mm256_maskz_cvtepi64_pd( __mmask8 k, __m256i a);
VCVTQQ2PD __m128d _mm_mask_cvtepi64_pd( __m128d s, __mmask8 k, __m128i a);
VCVTQQ2PD __m128d _mm_maskz_cvtepi64_pd( __mmask8 k, __m128i a);
SIMD Floating-Point Exceptions
Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VCVTQQ2PD-Convert Packed Quadword Integers to Packed Double Precision Floating-Point Values
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VCVTQQ2PH-Convert Packed Signed Quadword Integers to Packed FP16 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.NP.MAP5.W1 5B /r
A
V/V
(AVX512_FP16
Convert two packed signed quadword integers in
VCVTQQ2PH xmm1{k1}{z},
AND AVX512VL)
xmm2/m128/m64bcst to packed FP16 values,
xmm2/m128/m64bcst
OR AVX10.1
and store the result in xmm1 subject to
writemask k1.
EVEX.256.NP.MAP5.W1 5B /r
A
V/V
(AVX512_FP16
Convert four packed signed quadword integers in
VCVTQQ2PH xmm1{k1}{z},
AND AVX512VL)
ymm2/m256/m64bcst to packed FP16 values,
ymm2/m256/m64bcst
OR AVX10.1
and store the result in xmm1 subject to
writemask k1.
EVEX.512.NP.MAP5.W1 5B /r
A
V/V
AVX512_FP16
Convert eight packed signed quadword integers in
VCVTQQ2PH xmm1{k1}{z},
OR AVX10.1
zmm2/m512/m64bcst to packed FP16 values,
zmm2/m512/m64bcst {er}
and store the result in xmm1 subject to
writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed signed quadword integers in the source operand to packed FP16 values in the desti-
nation operand. The destination elements are updated according to the writemask.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
If the result of the convert operation is overflow and MXCSR.OM=0 then a SIMD exception will be raised with OE=1,
PE=1.
Operation
VCVTQQ2PH DEST, SRC
VL = 128, 256 or 512
KL := VL / 64
IF *SRC is a register* and (VL = 512) AND (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.qword[0]
ELSE
tsrc := SRC.qword[j]
DEST.fp16[j] := Convert_integer64_to_fp16(tsrc)
ELSE IF *zeroing*:
DEST.fp16[j] := 0
// else dest.fp16[j] remains unchanged
DEST[MAXVL-1:VL/4] := 0
VCVTQQ2PH-Convert Packed Signed Quadword Integers to Packed FP16 Values
Vol. 2C
5-83
Intel C/C++ Compiler Intrinsic Equivalent
VCVTQQ2PH __m128h _mm512_cvt_roundepi64_ph (__m512i a, int rounding);
VCVTQQ2PH __m128h _mm512_mask_cvt_roundepi64_ph (__m128h src, __mmask8 k, __m512i a, int rounding);
VCVTQQ2PH __m128h _mm512_maskz_cvt_roundepi64_ph (__mmask8 k, __m512i a, int rounding);
VCVTQQ2PH __m128h _mm_cvtepi64_ph (__m128i a);
VCVTQQ2PH __m128h _mm_mask_cvtepi64_ph (__m128h src, __mmask8 k, __m128i a);
VCVTQQ2PH __m128h _mm_maskz_cvtepi64_ph (__mmask8 k, __m128i a);
VCVTQQ2PH __m128h _mm256_cvtepi64_ph (__m256i a);
VCVTQQ2PH __m128h _mm256_mask_cvtepi64_ph (__m128h src, __mmask8 k, __m256i a);
VCVTQQ2PH __m128h _mm256_maskz_cvtepi64_ph (__mmask8 k, __m256i a);
VCVTQQ2PH __m128h _mm512_cvtepi64_ph (__m512i a);
VCVTQQ2PH __m128h _mm512_mask_cvtepi64_ph (__m128h src, __mmask8 k, __m512i a);
VCVTQQ2PH __m128h _mm512_maskz_cvtepi64_ph (__mmask8 k, __m512i a);
SIMD Floating-Point Exceptions
Overflow, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
VCVTQQ2PH-Convert Packed Signed Quadword Integers to Packed FP16 Values
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5-84
VCVTQQ2PS-Convert Packed Quadword Integers to Packed Single Precision Floating-Point
Values
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.0F.W1 5B /r
A
V/V
(AVX512VL AND
Convert two packed quadword integers from xmm2/mem
VCVTQQ2PS xmm1 {k1}{z},
AVX512DQ) OR
to packed single precision floating-point values in xmm1
xmm2/m128/m64bcst
AVX10.1
with writemask k1.
EVEX.256.0F.W1 5B /r
A
V/V
(AVX512VL AND
Convert four packed quadword integers from ymm2/mem
VCVTQQ2PS xmm1 {k1}{z},
AVX512DQ) OR
to packed single precision floating-point values in xmm1
ymm2/m256/m64bcst
AVX10.1
with writemask k1.
EVEX.512.0F.W1 5B /r
A
V/V
AVX512DQ
Convert eight packed quadword integers from
VCVTQQ2PS ymm1 {k1}{z},
OR AVX10.1
zmm2/mem to eight packed single precision floating-point
zmm2/m512/m64bcst {er}
values in ymm1 with writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts packed quadword integers in the source operand (second operand) to packed single precision floating-
point values in the destination operand (first operand).
The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operation
is a YMM/XMM/XMM (lower 64 bits) register conditionally updated with writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VCVTQQ2PS (EVEX Encoded Versions) When SRC Operand is a Register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
k := j * 32
IF k1[j] OR *no writemask*
THEN DEST[k+31:k] :=
Convert_QuadInteger_To_Single_Precision_Floating_Point(SRC[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[k+31:k] remains unchanged*
ELSE
; zeroing-masking
DEST[k+31:k] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0
VCVTQQ2PS-Convert Packed Quadword Integers to Packed Single Precision Floating-Point Values
Vol. 2C
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VCVTQQ2PS (EVEX Encoded Versions) When SRC Operand is a Memory Source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
k := j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[k+31:k] :=
Convert_QuadInteger_To_Single_Precision_Floating_Point(SRC[63:0])
ELSE
DEST[k+31:k] :=
Convert_QuadInteger_To_Single_Precision_Floating_Point(SRC[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[k+31:k] remains unchanged*
ELSE
; zeroing-masking
DEST[k+31:k] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTQQ2PS __m256 _mm512_cvtepi64_ps( __m512i a);
VCVTQQ2PS __m256 _mm512_mask_cvtepi64_ps( __m256 s, __mmask16 k, __m512i a);
VCVTQQ2PS __m256 _mm512_maskz_cvtepi64_ps( __mmask16 k, __m512i a);
VCVTQQ2PS __m256 _mm512_cvt_roundepi64_ps( __m512i a, int r);
VCVTQQ2PS __m256 _mm512_mask_cvt_roundepi_ps( __m256 s, __mmask8 k, __m512i a, int r);
VCVTQQ2PS __m256 _mm512_maskz_cvt_roundepi64_ps( __mmask8 k, __m512i a, int r);
VCVTQQ2PS __m128 _mm256_cvtepi64_ps( __m256i a);
VCVTQQ2PS __m128 _mm256_mask_cvtepi64_ps( __m128 s, __mmask8 k, __m256i a);
VCVTQQ2PS __m128 _mm256_maskz_cvtepi64_ps( __mmask8 k, __m256i a);
VCVTQQ2PS __m128 _mm_cvtepi64_ps( __m128i a);
VCVTQQ2PS __m128 _mm_mask_cvtepi64_ps( __m128 s, __mmask8 k, __m128i a);
VCVTQQ2PS __m128 _mm_maskz_cvtepi64_ps( __mmask8 k, __m128i a);
SIMD Floating-Point Exceptions
Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VCVTQQ2PS-Convert Packed Quadword Integers to Packed Single Precision Floating-Point Values
Vol. 2C
5-86
VCVTSD2SH-Convert Low FP64 Value to an FP16 Value
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.LLIG.F2.MAP5.W1 5A /r
A
V/V
AVX512_FP16
Convert the low FP64 value in xmm3/m64 to an
VCVTSD2SH xmm1{k1}{z}, xmm2,
OR AVX10.1
FP16 value and store the result in the low
xmm3/m64 {er}
element of xmm1 subject to writemask k1. Bits
127:16 of xmm2 are copied to xmm1[127:16].
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
This instruction converts the low FP64 value in the second source operand to an FP16 value, and stores the result in
the low element of the destination operand.
When the conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register.
Bits 127:16 of the destination operand are copied from the corresponding bits of the first source operand. Bits
MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the destination is updated according
to the writemask.
Operation
VCVTSD2SH dest, src1, src2
IF *SRC2 is a register* and (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
IF k1[0] OR *no writemask*:
DEST.fp16[0] := Convert_fp64_to_fp16(SRC2.fp64[0])
ELSE IF *zeroing*:
DEST.fp16[0] := 0
// else dest.fp16[0] remains unchanged
DEST[127:16] := SRC1[127:16]
DEST[MAXVL-1:128] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSD2SH __m128h _mm_cvt_roundsd_sh (__m128h a, __m128d b, const int rounding);
VCVTSD2SH __m128h _mm_mask_cvt_roundsd_sh (__m128h src, __mmask8 k, __m128h a, __m128d b, const int rounding);
VCVTSD2SH __m128h _mm_maskz_cvt_roundsd_sh (__mmask8 k, __m128h a, __m128d b, const int rounding);
VCVTSD2SH __m128h _mm_cvtsd_sh (__m128h a, __m128d b);
VCVTSD2SH __m128h _mm_mask_cvtsd_sh (__m128h src, __mmask8 k, __m128h a, __m128d b);
VCVTSD2SH __m128h _mm_maskz_cvtsd_sh (__mmask8 k, __m128h a, __m128d b);
SIMD Floating-Point Exceptions
Invalid, Underflow, Overflow, Precision, Denormal.
Other Exceptions
EVEX-encoded instructions, see Table 2-49, “Type E3 Class Exception Conditions.”
VCVTSD2SH-Convert Low FP64 Value to an FP16 Value
Vol. 2C
5-87