Intel 64 and IA-32 Architectures. Software Developer’s Manual (2026) - page 32
VCVTSD2USI-Convert Scalar Double Precision Floating-Point Value to Unsigned Integer
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
Bit Mode
Feature
Support
Flag
EVEX.LLIG.F2.0F.W0 79 /r
A
V/V
AVX512F
Convert one double precision floating-point value from
VCVTSD2USI r32, xmm1/m64{er}
OR
xmm1/m64 to one unsigned doubleword integer r32.
AVX10.1
EVEX.LLIG.F2.0F.W1 79 /r
A
V/N.E.1
AVX512F
Convert one double precision floating-point value from
VCVTSD2USI r64, xmm1/m64{er}
OR
xmm1/m64 to one unsigned quadword integer zero-
AVX10.1
extended into r64.
NOTES:
1. EVEX.W1 in non-64 bit is ignored; the instruction behaves as if the W0 version is used.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Fixed
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts a double precision floating-point value in the source operand (the second operand) to an unsigned
doubleword integer in the destination operand (the first operand). The source operand can be an XMM register or
a 64-bit memory location. The destination operand is a general-purpose register. When the source operand is an
XMM register, the double precision floating-point value is contained in the low quadword of the register.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits.
If a converted result exceeds the range limits of signed doubleword integer (in non-64-bit modes or 64-bit mode
with REX.W/VEX.W/EVEX.W=0), the floating-point invalid exception is raised, and if this exception is masked, the
integer value FFFFFFFFH is returned.
If a converted result exceeds the range limits of signed quadword integer (in 64-bit mode and
REX.W/VEX.W/EVEX.W = 1), the floating-point invalid exception is raised, and if this exception is masked, the
integer value FFFFFFFF_FFFFFFFFH is returned.
Operation
VCVTSD2USI (EVEX Encoded Version)
IF (SRC *is register*) AND (EVEX.b = 1)
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
ELSE
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
FI;
IF 64-Bit Mode and OperandSize = 64
THEN
DEST[63:0] := Convert_Double_Precision_Floating_Point_To_UInteger(SRC[63:0]);
ELSE
DEST[31:0] := Convert_Double_Precision_Floating_Point_To_UInteger(SRC[63:0]);
FI
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSD2USI unsigned int _mm_cvtsd_u32(__m128d);
VCVTSD2USI unsigned int _mm_cvt_roundsd_u32(__m128d, int r);
VCVTSD2USI unsigned __int64 _mm_cvtsd_u64(__m128d);
VCVTSD2USI unsigned __int64 _mm_cvt_roundsd_u64(__m128d, int r);
VCVTSD2USI-Convert Scalar Double Precision Floating-Point Value to Unsigned Integer
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SIMD Floating-Point Exceptions
Invalid, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-50, “Type E3NF Class Exception Conditions.”
VCVTSD2USI-Convert Scalar Double Precision Floating-Point Value to Unsigned Integer
Vol. 2C
5-89
VCVTSH2SD-Convert Low FP16 Value to an FP64 Value
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.LLIG.F3.MAP5.W0 5A /r
A
V/V
AVX512_FP16
Convert the low FP16 value in xmm3/m16 to an
VCVTSH2SD xmm1{k1}{z}, xmm2,
OR AVX10.1
FP64 value and store the result in the low
xmm3/m16 {sae}
element of xmm1 subject to writemask k1. Bits
127:64 of xmm2 are copied to xmm1[127:64].
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
This instruction converts the low FP16 element in the second source operand to a FP64 element in the low element
of the destination operand.
Bits 127:64 of the destination operand are copied from the corresponding bits of the first source operand. Bits
MAXVL-1:128 of the destination operand are zeroed. The low FP64 element of the destination is updated according
to the writemask.
Operation
VCVTSH2SD dest, src1, src2
IF k1[0] OR *no writemask*:
DEST.fp64[0] := Convert_fp16_to_fp64(SRC2.fp16[0])
ELSE IF *zeroing*:
DEST.fp64[0] := 0
// else dest.fp64[0] remains unchanged
DEST[127:64] := SRC1[127:64]
DEST[MAXVL-1:128] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSH2SD __m128d _mm_cvt_roundsh_sd (__m128d a, __m128h b, const int sae);
VCVTSH2SD __m128d _mm_mask_cvt_roundsh_sd (__m128d src, __mmask8 k, __m128d a, __m128h b, const int sae);
VCVTSH2SD __m128d _mm_maskz_cvt_roundsh_sd (__mmask8 k, __m128d a, __m128h b, const int sae);
VCVTSH2SD __m128d _mm_cvtsh_sd (__m128d a, __m128h b);
VCVTSH2SD __m128d _mm_mask_cvtsh_sd (__m128d src, __mmask8 k, __m128d a, __m128h b);
VCVTSH2SD __m128d _mm_maskz_cvtsh_sd (__mmask8 k, __m128d a, __m128h b);
SIMD Floating-Point Exceptions
Invalid, Denormal.
Other Exceptions
EVEX-encoded instructions, see Table 2-49, “Type E3 Class Exception Conditions.”
VCVTSH2SD-Convert Low FP16 Value to an FP64 Value
Vol. 2C
5-90
VCVTSH2SI-Convert Low FP16 Value to Signed Integer
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.LLIG.F3.MAP5.W0 2D /r
A
V/V1
AVX512_FP16
Convert the low FP16 element in xmm1/m16 to a
VCVTSH2SI r32, xmm1/m16 {er}
OR AVX10.1
signed doubleword integer and store the result in
r32.
EVEX.LLIG.F3.MAP5.W1 2D /r
A
V/N.E.
AVX512_FP16
Convert the low FP16 element in xmm1/m16 to a
VCVTSH2SI r64, xmm1/m16 {er}
OR AVX10.1
signed quadword integer and store the result in
r64.
NOTES:
1. Outside of 64b mode, the EVEX.W field is ignored. The instruction behaves as if W=0 was used.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts the low FP16 element in the source operand to a signed integer in the destination general
purpose register.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits.
If a converted result exceeds the range limits of signed doubleword integer (in non-64-bit modes or 64-bit mode
with REX.W/VEX.W/EVEX.W=0), the floating-point invalid exception is raised, and if this exception is masked, the
indefinite integer value 80000000H is returned.
If a converted result exceeds the range limits of signed quadword integer (in 64-bit mode and
REX.W/VEX.W/EVEX.W = 1), the floating-point invalid exception is raised, and if this exception is masked, the
indefinite integer value 80000000_00000000H is returned.
Operation
VCVTSH2SI dest, src
IF *SRC is a register* and (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
IF 64-mode and OperandSize == 64:
DEST.qword := Convert_fp16_to_integer64(SRC.fp16[0])
ELSE:
DEST.dword := Convert_fp16_to_integer32(SRC.fp16[0])
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSH2SI int _mm_cvt_roundsh_i32 (__m128h a, int rounding);
VCVTSH2SI __int64 _mm_cvt_roundsh_i64 (__m128h a, int rounding);
VCVTSH2SI int _mm_cvtsh_i32 (__m128h a);
VCVTSH2SI __int64 _mm_cvtsh_i64 (__m128h a);
SIMD Floating-Point Exceptions
Invalid, Precision.
VCVTSH2SI-Convert Low FP16 Value to Signed Integer
Vol. 2C
5-91
Other Exceptions
EVEX-encoded instructions, see Table 2-50, “Type E3NF Class Exception Conditions.”
VCVTSH2SI-Convert Low FP16 Value to Signed Integer
Vol. 2C
5-92
VCVTSH2SS-Convert Low FP16 Value to FP32 Value
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.LLIG.NP.MAP6.W0 13 /r
A
V/V
AVX512_FP16
Convert the low FP16 element in xmm3/m16 to
VCVTSH2SS xmm1{k1}{z}, xmm2,
OR AVX10.1
an FP32 value and store in the low element of
xmm3/m16 {sae}
xmm1 subject to writemask k1. Bits 127:32 of
xmm2 are copied to xmm1[127:32].
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
This instruction converts the low FP16 element in the second source operand to the low FP32 element of the desti-
nation operand.
Bits 127:32 of the destination operand are copied from the corresponding bits of the first source operand. Bits
MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the destination is updated according
to the writemask.
Operation
VCVTSH2SS dest, src1, src2
IF k1[0] OR *no writemask*:
DEST.fp32[0] := Convert_fp16_to_fp32(SRC2.fp16[0])
ELSE IF *zeroing*:
DEST.fp32[0] := 0
// else dest.fp32[0] remains unchanged
DEST[127:32] := SRC1[127:32]
DEST[MAXVL-1:128] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSH2SS __m128 _mm_cvt_roundsh_ss (__m128 a, __m128h b, const int sae);
VCVTSH2SS __m128 _mm_mask_cvt_roundsh_ss (__m128 src, __mmask8 k, __m128 a, __m128h b, const int sae);
VCVTSH2SS __m128 _mm_maskz_cvt_roundsh_ss (__mmask8 k, __m128 a, __m128h b, const int sae);
VCVTSH2SS __m128 _mm_cvtsh_ss (__m128 a, __m128h b);
VCVTSH2SS __m128 _mm_mask_cvtsh_ss (__m128 src, __mmask8 k, __m128 a, __m128h b);
VCVTSH2SS __m128 _mm_maskz_cvtsh_ss (__mmask8 k, __m128 a, __m128h b);
SIMD Floating-Point Exceptions
Invalid, Denormal.
Other Exceptions
EVEX-encoded instructions, see Table 2-49, “Type E3 Class Exception Conditions.”
VCVTSH2SS-Convert Low FP16 Value to FP32 Value
Vol. 2C
5-93
VCVTSH2USI-Convert Low FP16 Value to Unsigned Integer
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.LLIG.F3.MAP5.W0 79 /r
A
V/V1
AVX512_FP16
Convert the low FP16 element in xmm1/m16 to
VCVTSH2USI r32, xmm1/m16 {er}
OR AVX10.1
an unsigned doubleword integer and store the
result in r32.
EVEX.LLIG.F3.MAP5.W1 79 /r
A
V/N.E.
AVX512_FP16
Convert the low FP16 element in xmm1/m16 to
VCVTSH2USI r64, xmm1/m16 {er}
OR AVX10.1
an unsigned quadword integer and store the
result in r64.
NOTES:
1. Outside of 64b mode, the EVEX.W field is ignored. The instruction behaves as if W=0 was used.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts the low FP16 element in the source operand to an unsigned integer in the destination
general purpose register.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits.
If a converted result exceeds the range limits of signed doubleword integer (in non-64-bit modes or 64-bit mode
with REX.W/VEX.W/EVEX.W=0), the floating-point invalid exception is raised, and if this exception is masked, the
integer value FFFFFFFFH is returned.
If a converted result exceeds the range limits of signed quadword integer (in 64-bit mode and
REX.W/VEX.W/EVEX.W = 1), the floating-point invalid exception is raised, and if this exception is masked, the
integer value FFFFFFFF_FFFFFFFFH is returned.
Operation
VCVTSH2USI dest, src
// SET_RM() sets the rounding mode used for this instruction.
IF *SRC is a register* and (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
IF 64-mode and OperandSize == 64:
DEST.qword := Convert_fp16_to_unsigned_integer64(SRC.fp16[0])
ELSE:
DEST.dword := Convert_fp16_to_unsigned_integer32(SRC.fp16[0])
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSH2USI unsigned int _mm_cvt_roundsh_u32 (__m128h a, int sae);
VCVTSH2USI unsigned __int64 _mm_cvt_roundsh_u64 (__m128h a, int rounding);
VCVTSH2USI unsigned int _mm_cvtsh_u32 (__m128h a);
VCVTSH2USI unsigned __int64 _mm_cvtsh_u64 (__m128h a);
SIMD Floating-Point Exceptions
Invalid, Precision.
VCVTSH2USI-Convert Low FP16 Value to Unsigned Integer
Vol. 2C
5-94
Other Exceptions
EVEX-encoded instructions, see Table 2-50, “Type E3NF Class Exception Conditions.”
VCVTSH2USI-Convert Low FP16 Value to Unsigned Integer
Vol. 2C
5-95
VCVTSI2SH-Convert a Signed Doubleword/Quadword Integer to an FP16 Value
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.LLIG.F3.MAP5.W0 2A /r
A
V/V1
AVX512_FP16
Convert the signed doubleword integer in
VCVTSI2SH xmm1, xmm2, r32/m32
OR AVX10.1
r32/m32 to an FP16 value and store the result in
{er}
xmm1. Bits 127:16 of xmm2 are copied to
xmm1[127:16].
EVEX.LLIG.F3.MAP5.W1 2A /r
A
V/N.E.
AVX512_FP16
Convert the signed quadword integer in r64/m64
VCVTSI2SH xmm1, xmm2, r64/m64
OR AVX10.1
to an FP16 value and store the result in xmm1.
{er}
Bits 127:16 of xmm2 are copied to
xmm1[127:16].
NOTES:
1. Outside of 64b mode, the EVEX.W field is ignored. The instruction behaves as if W=0 was used.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
This instruction converts a signed doubleword integer (or signed quadword integer if operand size is 64 bits) in the
second source operand to an FP16 value in the destination operand. The result is stored in the low word of the desti-
nation operand. When conversion is inexact, the value returned is rounded according to the rounding control bits
in the MXCSR register or embedded rounding controls.
The second source operand can be a general-purpose register or a 32/64-bit memory location. The first source and
destination operands are XMM registers. Bits 127:16 of the XMM register destination are copied from corre-
sponding bits in the first source operand. Bits MAXVL-1:128 of the destination register are zeroed.
If the result of the convert operation is overflow and MXCSR.OM=0 then a SIMD exception will be raised with OE=1,
PE=1.
Operation
VCVTSI2SH dest, src1, src2
IF *SRC2 is a register* and (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
IF 64-mode and OperandSize == 64:
DEST.fp16[0] := Convert_integer64_to_fp16(SRC2.qword)
ELSE:
DEST.fp16[0] := Convert_integer32_to_fp16(SRC2.dword)
DEST[127:16] := SRC1[127:16]
DEST[MAXVL-1:128] := 0
VCVTSI2SH-Convert a Signed Doubleword/Quadword Integer to an FP16 Value
Vol. 2C
5-96
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSI2SH __m128h _mm_cvt_roundi32_sh (__m128h a, int b, int rounding);
VCVTSI2SH __m128h _mm_cvt_roundi64_sh (__m128h a, __int64 b, int rounding);
VCVTSI2SH __m128h _mm_cvti32_sh (__m128h a, int b);
VCVTSI2SH __m128h _mm_cvti64_sh (__m128h a, __int64 b);
SIMD Floating-Point Exceptions
Overflow, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-50, “Type E3NF Class Exception Conditions.”
VCVTSI2SH-Convert a Signed Doubleword/Quadword Integer to an FP16 Value
Vol. 2C
5-97
VCVTSS2SH-Convert Low FP32 Value to an FP16 Value
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.LLIG.NP.MAP5.W0 1D /r
A
V/V
AVX512_FP16
Convert low FP32 value in xmm3/m32 to an
VCVTSS2SH xmm1{k1}{z}, xmm2,
OR AVX10.1
FP16 value and store in the low element of
xmm3/m32 {er}
xmm1 subject to writemask k1. Bits 127:16 from
xmm2 are copied to xmm1[127:16].
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
This instruction converts the low FP32 value in the second source operand to a FP16 value in the low element of the
destination operand.
When the conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register.
Bits 127:16 of the destination operand are copied from the corresponding bits of the first source operand. Bits
MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the destination is updated according
to the writemask.
Operation
VCVTSS2SH dest, src1, src2
IF *SRC2 is a register* and (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
IF k1[0] OR *no writemask*:
DEST.fp16[0] := Convert_fp32_to_fp16(SRC2.fp32[0])
ELSE IF *zeroing*:
DEST.fp16[0] := 0
// else dest.fp16[0] remains unchanged
DEST[127:16] := SRC1[127:16]
DEST[MAXVL-1:128] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSS2SH __m128h _mm_cvt_roundss_sh (__m128h a, __m128 b, const int rounding);
VCVTSS2SH __m128h _mm_mask_cvt_roundss_sh (__m128h src, __mmask8 k, __m128h a, __m128 b, const int rounding);
VCVTSS2SH __m128h _mm_maskz_cvt_roundss_sh (__mmask8 k, __m128h a, __m128 b, const int rounding);
VCVTSS2SH __m128h _mm_cvtss_sh (__m128h a, __m128 b);
VCVTSS2SH __m128h _mm_mask_cvtss_sh (__m128h src, __mmask8 k, __m128h a, __m128 b);
VCVTSS2SH __m128h _mm_maskz_cvtss_sh (__mmask8 k, __m128h a, __m128 b);
SIMD Floating-Point Exceptions
Invalid, Underflow, Overflow, Precision, Denormal.
Other Exceptions
EVEX-encoded instructions, see Table 2-49, “Type E3 Class Exception Conditions.”
VCVTSS2SH-Convert Low FP32 Value to an FP16 Value
Vol. 2C
5-98
VCVTSS2USI-Convert Scalar Single Precision Floating-Point Value to Unsigned Doubleword
Integer
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
Bit Mode
Feature Flag
Support
EVEX.LLIG.F3.0F.W0 79 /r
A
V/V
AVX512F
Convert one single precision floating-point value
VCVTSS2USI r32, xmm1/m32{er}
OR AVX10.1
from xmm1/m32 to one unsigned doubleword
integer in r32.
EVEX.LLIG.F3.0F.W1 79 /r
A
V/N.E.1
AVX512F
Convert one single precision floating-point value
VCVTSS2USI r64, xmm1/m32{er}
OR AVX10.1
from xmm1/m32 to one unsigned quadword
integer in r64.
NOTES:
1. EVEX.W1 in non-64 bit is ignored; the instruction behaves as if the W0 version is used.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Fixed
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts a single precision floating-point value in the source operand (the second operand) to an unsigned double-
word integer (or unsigned quadword integer if operand size is 64 bits) in the destination operand (the first
operand). The source operand can be an XMM register or a memory location. The destination operand is a general-
purpose register. When the source operand is an XMM register, the single precision floating-point value is contained
in the low doubleword of the register.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits.
If a converted result exceeds the range limits of signed doubleword integer (in non-64-bit modes or 64-bit mode
with REX.W/VEX.W/EVEX.W=0), the floating-point invalid exception is raised, and if this exception is masked, the
integer value FFFFFFFFH is returned.
If a converted result exceeds the range limits of signed quadword integer (in 64-bit mode and
REX.W/VEX.W/EVEX.W = 1), the floating-point invalid exception is raised, and if this exception is masked, the
integer value FFFFFFFF_FFFFFFFFH is returned.
VEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
VCVTSS2USI (EVEX Encoded Version)
IF (SRC *is register*) AND (EVEX.b = 1)
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
ELSE
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
FI;
IF 64-bit Mode and OperandSize = 64
THEN
DEST[63:0] := Convert_Single_Precision_Floating_Point_To_UInteger(SRC[31:0]);
ELSE
DEST[31:0] := Convert_Single_Precision_Floating_Point_To_UInteger(SRC[31:0]);
FI;
VCVTSS2USI-Convert Scalar Single Precision Floating-Point Value to Unsigned Doubleword Integer
Vol. 2C
5-99
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSS2USI unsigned _mm_cvtss_u32( __m128 a);
VCVTSS2USI unsigned _mm_cvt_roundss_u32( __m128 a, int r);
VCVTSS2USI unsigned __int64 _mm_cvtss_u64( __m128 a);
VCVTSS2USI unsigned __int64 _mm_cvt_roundss_u64( __m128 a, int r);
SIMD Floating-Point Exceptions
Invalid, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-50, “Type E3NF Class Exception Conditions.”
VCVTSS2USI-Convert Scalar Single Precision Floating-Point Value to Unsigned Doubleword Integer
Vol. 2C
5-100
VCVTTPD2QQ-Convert With Truncation Packed Double Precision Floating-Point Values to
Packed Quadword Integers
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.66.0F.W1 7A /r
A
V/V
(AVX512VL AND
Convert two packed double precision floating-point
VCVTTPD2QQ xmm1 {k1}{z},
AVX512DQ) OR
values from zmm2/m128/m64bcst to two packed signed
xmm2/m128/m64bcst
AVX10.1
quadword integers in zmm1 using truncation with
writemask k1.
EVEX.256.66.0F.W1 7A /r
A
V/V
(AVX512VL AND
Convert four packed double precision floating-point
VCVTTPD2QQ ymm1 {k1}{z},
AVX512DQ) OR
values from ymm2/m256/m64bcst to four packed signed
ymm2/m256/m64bcst
AVX10.1
quadword integers in ymm1 using truncation with
writemask k1.
EVEX.512.66.0F.W1 7A /r
A
V/V
AVX512DQ
Convert eight packed double precision floating-point
VCVTTPD2QQ zmm1 {k1}{z},
OR AVX10.1
values from zmm2/m512 to eight packed signed
zmm2/m512/m64bcst {sae}
quadword integers in zmm1 using truncation with
writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts with truncation packed double precision floating-point values in the source operand (second operand) to
packed quadword integers in the destination operand (first operand).
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result cannot be
represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked,
the indefinite integer value 80000000_00000000H is returned.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
VCVTTPD2QQ (EVEX Encoded Version) When SRC Operand is a Register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] :=
Convert_Double_Precision_Floating_Point_To_QuadInteger_Truncate(SRC[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VCVTTPD2QQ (EVEX Encoded Version) When SRC Operand is a Memory Source
VCVTTPD2QQ-Convert With Truncation Packed Double Precision Floating-Point Values to Packed Quadword Integers
Vol. 2C
5-101
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[i+63:i] :=
Convert_Double_Precision_Floating_Point_To_QuadInteger_Truncate(SRC[63:0])
ELSE
DEST[i+63:i] := Convert_Double_Precision_Floating_Point_To_QuadInteger_Truncate(SRC[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPD2QQ __m512i _mm512_cvttpd_epi64( __m512d a);
VCVTTPD2QQ __m512i _mm512_mask_cvttpd_epi64( __m512i s, __mmask8 k, __m512d a);
VCVTTPD2QQ __m512i _mm512_maskz_cvttpd_epi64( __mmask8 k, __m512d a);
VCVTTPD2QQ __m512i _mm512_cvtt_roundpd_epi64( __m512d a, int sae);
VCVTTPD2QQ __m512i _mm512_mask_cvtt_roundpd_epi64( __m512i s, __mmask8 k, __m512d a, int sae);
VCVTTPD2QQ __m512i _mm512_maskz_cvtt_roundpd_epi64( __mmask8 k, __m512d a, int sae);
VCVTTPD2QQ __m256i _mm256_mask_cvttpd_epi64( __m256i s, __mmask8 k, __m256d a);
VCVTTPD2QQ __m256i _mm256_maskz_cvttpd_epi64( __mmask8 k, __m256d a);
VCVTTPD2QQ __m128i _mm_mask_cvttpd_epi64( __m128i s, __mmask8 k, __m128d a);
VCVTTPD2QQ __m128i _mm_maskz_cvttpd_epi64( __mmask8 k, __m128d a);
SIMD Floating-Point Exceptions
Invalid, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VCVTTPD2QQ-Convert With Truncation Packed Double Precision Floating-Point Values to Packed Quadword Integers
Vol. 2C
5-102
VCVTTPD2UDQ-Convert With Truncation Packed Double Precision Floating-Point Values to
Packed Unsigned Doubleword Integers
Opcode
Op /
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.0F.W1 78 /r
A
V/V
(AVX512VL AND
Convert two packed double precision floating-point
VCVTTPD2UDQ xmm1 {k1}{z},
AVX512F) OR
values in xmm2/m128/m64bcst to two unsigned
xmm2/m128/m64bcst
AVX10.1
doubleword integers in xmm1 using truncation
subject to writemask k1.
EVEX.256.0F.W1 78 02 /r
A
V/V
(AVX512VL AND
Convert four packed double precision floating-point
VCVTTPD2UDQ xmm1 {k1}{z},
AVX512F) OR
values in ymm2/m256/m64bcst to four unsigned
ymm2/m256/m64bcst
AVX10.1
doubleword integers in xmm1 using truncation
subject to writemask k1.
EVEX.512.0F.W1 78 /r
A
V/V
AVX512F
Convert eight packed double precision floating-point
VCVTTPD2UDQ ymm1 {k1}{z},
OR AVX10.1
values in zmm2/m512/m64bcst to eight unsigned
zmm2/m512/m64bcst {sae}
doubleword integers in ymm1 using truncation
subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts with truncation packed double precision floating-point values in the source operand (the second operand)
to packed unsigned doubleword integers in the destination operand (the first operand).
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result cannot be
represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked,
the integer value FFFFFFFFH is returned.
The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector
broadcasted from a 64-bit memory location. The destination operand is a YMM/XMM/XMM (low 64 bits) register
conditionally updated with writemask k1. The upper bits (MAXVL-1:256) of the corresponding destination are
zeroed.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
VCVTTPD2UDQ (EVEX Encoded Versions) When SRC2 Operand is a Register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 32
k := j * 64
IF k1[j] OR *no writemask*
THEN
DEST[i+31:i] :=
Convert_Double_Precision_Floating_Point_To_UInteger_Truncate(SRC[k+63:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
VCVTTPD2UDQ-Convert With Truncation Packed Double Precision Floating-Point Values to Packed Unsigned Doubleword Integers
Vol. 2C
5-103
ENDFOR
DEST[MAXVL-1:VL/2] := 0
VCVTTPD2UDQ (EVEX Encoded Versions) When SRC Operand is a Memory Source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 32
k := j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i] :=
Convert_Double_Precision_Floating_Point_To_UInteger_Truncate(SRC[63:0])
ELSE
DEST[i+31:i] :=
Convert_Double_Precision_Floating_Point_To_UInteger_Truncate(SRC[k+63:k])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPD2UDQ __m256i _mm512_cvttpd_epu32( __m512d a);
VCVTTPD2UDQ __m256i _mm512_mask_cvttpd_epu32( __m256i s, __mmask8 k, __m512d a);
VCVTTPD2UDQ __m256i _mm512_maskz_cvttpd_epu32( __mmask8 k, __m512d a);
VCVTTPD2UDQ __m256i _mm512_cvtt_roundpd_epu32( __m512d a, int sae);
VCVTTPD2UDQ __m256i _mm512_mask_cvtt_roundpd_epu32( __m256i s, __mmask8 k, __m512d a, int sae);
VCVTTPD2UDQ __m256i _mm512_maskz_cvtt_roundpd_epu32( __mmask8 k, __m512d a, int sae);
VCVTTPD2UDQ __m128i _mm256_mask_cvttpd_epu32( __m128i s, __mmask8 k, __m256d a);
VCVTTPD2UDQ __m128i _mm256_maskz_cvttpd_epu32( __mmask8 k, __m256d a);
VCVTTPD2UDQ __m128i _mm_mask_cvttpd_epu32( __m128i s, __mmask8 k, __m128d a);
VCVTTPD2UDQ __m128i _mm_maskz_cvttpd_epu32( __mmask8 k, __m128d a);
SIMD Floating-Point Exceptions
Invalid, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VCVTTPD2UDQ-Convert With Truncation Packed Double Precision Floating-Point Values to Packed Unsigned Doubleword Integers
Vol. 2C
5-104
VCVTTPD2UQQ-Convert With Truncation Packed Double Precision Floating-Point Values to
Packed Unsigned Quadword Integers
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.66.0F.W1 78 /r
A
V/V
(AVX512VL AND
Convert two packed double precision floating-point
VCVTTPD2UQQ xmm1 {k1}{z},
AVX512DQ) OR
values from xmm2/m128/m64bcst to two packed
xmm2/m128/m64bcst
AVX10.1
unsigned quadword integers in xmm1 using truncation
with writemask k1.
EVEX.256.66.0F.W1 78 /r
A
V/V
(AVX512VL AND
Convert four packed double precision floating-point
VCVTTPD2UQQ ymm1 {k1}{z},
AVX512DQ) OR
values from ymm2/m256/m64bcst to four packed
ymm2/m256/m64bcst
AVX10.1
unsigned quadword integers in ymm1 using truncation
with writemask k1.
EVEX.512.66.0F.W1 78 /r
A
V/V
AVX512DQ
Convert eight packed double precision floating-point
VCVTTPD2UQQ zmm1 {k1}{z},
OR AVX10.1
values from zmm2/mem to eight packed unsigned
zmm2/m512/m64bcst {sae}
quadword integers in zmm1 using truncation with
writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts with truncation packed double precision floating-point values in the source operand (second operand) to
packed unsigned quadword integers in the destination operand (first operand).
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result cannot be
represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked,
the integer value FFFFFFFF_FFFFFFFFH is returned.
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The destination operation is a ZMM/YMM/XMM register conditionally updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
VCVTTPD2UQQ (EVEX Encoded Versions) When SRC Operand is a Register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] :=
Convert_Double_Precision_Floating_Point_To_UQuadInteger_Truncate(SRC[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VCVTTPD2UQQ (EVEX Encoded Versions) When SRC Operand is a Memory Source
VCVTTPD2UQQ-Convert With Truncation Packed Double Precision Floating-Point Values to Packed Unsigned Quadword Integers
Vol. 2C
5-105
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[i+63:i] :=
Convert_Double_Precision_Floating_Point_To_UQuadInteger_Truncate(SRC[63:0])
ELSE
DEST[i+63:i] :=
Convert_Double_Precision_Floating_Point_To_UQuadInteger_Truncate(SRC[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPD2UQQ _mm<size>[_mask[z]]_cvtt[_round]pd_epu64
VCVTTPD2UQQ __m512i _mm512_cvttpd_epu64( __m512d a);
VCVTTPD2UQQ __m512i _mm512_mask_cvttpd_epu64( __m512i s, __mmask8 k, __m512d a);
VCVTTPD2UQQ __m512i _mm512_maskz_cvttpd_epu64( __mmask8 k, __m512d a);
VCVTTPD2UQQ __m512i _mm512_cvtt_roundpd_epu64( __m512d a, int sae);
VCVTTPD2UQQ __m512i _mm512_mask_cvtt_roundpd_epu64( __m512i s, __mmask8 k, __m512d a, int sae);
VCVTTPD2UQQ __m512i _mm512_maskz_cvtt_roundpd_epu64( __mmask8 k, __m512d a, int sae);
VCVTTPD2UQQ __m256i _mm256_mask_cvttpd_epu64( __m256i s, __mmask8 k, __m256d a);
VCVTTPD2UQQ __m256i _mm256_maskz_cvttpd_epu64( __mmask8 k, __m256d a);
VCVTTPD2UQQ __m128i _mm_mask_cvttpd_epu64( __m128i s, __mmask8 k, __m128d a);
VCVTTPD2UQQ __m128i _mm_maskz_cvttpd_epu64( __mmask8 k, __m128d a);
SIMD Floating-Point Exceptions
Invalid, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VCVTTPD2UQQ-Convert With Truncation Packed Double Precision Floating-Point Values to Packed Unsigned Quadword Integers
Vol. 2C
5-106
VCVTTPH2DQ-Convert with Truncation Packed FP16 Values to Signed Doubleword Integers
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.F3.MAP5.W0 5B /r
A
V/V
(AVX512_FP16
Convert four packed FP16 values in
VCVTTPH2DQ xmm1{k1}{z},
AND AVX512VL)
xmm2/m64/m16bcst to four signed doubleword
xmm2/m64/m16bcst
OR AVX10.1
integers, and store the result in xmm1 using
truncation subject to writemask k1.
EVEX.256.F3.MAP5.W0 5B /r
A
V/V
(AVX512_FP16
Convert eight packed FP16 values in
VCVTTPH2DQ ymm1{k1}{z},
AND AVX512VL)
xmm2/m128/m16bcst to eight signed
xmm2/m128/m16bcst
OR AVX10.1
doubleword integers, and store the result in
ymm1 using truncation subject to writemask k1.
EVEX.512.F3.MAP5.W0 5B /r
A
V/V
AVX512_FP16
Convert sixteen packed FP16 values in
VCVTTPH2DQ zmm1{k1}{z},
OR AVX10.1
ymm2/m256/m16bcst to sixteen signed
ymm2/m256/m16bcst {sae}
doubleword integers, and store the result in
zmm1 using truncation subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Half
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed FP16 values in the source operand to signed doubleword integers in destination
operand.
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result is larger than
the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is
masked, the indefinite integer value 80000000H is returned.
The destination elements are updated according to the writemask.
Operation
VCVTTPH2DQ dest, src
VL = 128, 256 or 512
KL := VL / 32
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.fp16[0]
ELSE
tsrc := SRC.fp16[j]
DEST.fp32[j] := Convert_fp16_to_integer32_truncate(tsrc)
ELSE IF *zeroing*:
DEST.fp32[j] := 0
// else dest.fp32[j] remains unchanged
DEST[MAXVL-1:VL] := 0
VCVTTPH2DQ-Convert with Truncation Packed FP16 Values to Signed Doubleword Integers
Vol. 2C
5-107
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPH2DQ __m512i _mm512_cvtt_roundph_epi32 (__m256h a, int sae);
VCVTTPH2DQ __m512i _mm512_mask_cvtt_roundph_epi32 (__m512i src, __mmask16 k, __m256h a, int sae);
VCVTTPH2DQ __m512i _mm512_maskz_cvtt_roundph_epi32 (__mmask16 k, __m256h a, int sae);
VCVTTPH2DQ __m128i _mm_cvttph_epi32 (__m128h a);
VCVTTPH2DQ __m128i _mm_mask_cvttph_epi32 (__m128i src, __mmask8 k, __m128h a);
VCVTTPH2DQ __m128i _mm_maskz_cvttph_epi32 (__mmask8 k, __m128h a);
VCVTTPH2DQ __m256i _mm256_cvttph_epi32 (__m128h a);
VCVTTPH2DQ __m256i _mm256_mask_cvttph_epi32 (__m256i src, __mmask8 k, __m128h a);
VCVTTPH2DQ __m256i _mm256_maskz_cvttph_epi32 (__mmask8 k, __m128h a);
VCVTTPH2DQ __m512i _mm512_cvttph_epi32 (__m256h a);
VCVTTPH2DQ __m512i _mm512_mask_cvttph_epi32 (__m512i src, __mmask16 k, __m256h a);
VCVTTPH2DQ __m512i _mm512_maskz_cvttph_epi32 (__mmask16 k, __m256h a);
SIMD Floating-Point Exceptions
Invalid, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
VCVTTPH2DQ-Convert with Truncation Packed FP16 Values to Signed Doubleword Integers
Vol. 2C
5-108
VCVTTPH2QQ-Convert with Truncation Packed FP16 Values to Signed Quadword Integers
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.66.MAP5.W0 7A /r
A
V/V
(AVX512_FP16
Convert two packed FP16 values in
VCVTTPH2QQ xmm1{k1}{z},
AND AVX512VL)
xmm2/m32/m16bcst to two signed quadword
xmm2/m32/m16bcst
OR AVX10.1
integers, and store the result in xmm1 using
truncation subject to writemask k1.
EVEX.256.66.MAP5.W0 7A /r
A
V/V
(AVX512_FP16
Convert four packed FP16 values in
VCVTTPH2QQ ymm1{k1}{z},
AND AVX512VL)
xmm2/m64/m16bcst to four signed quadword
xmm2/m64/m16bcst
OR AVX10.1
integers, and store the result in ymm1 using
truncation subject to writemask k1.
EVEX.512.66.MAP5.W0 7A /r
A
V/V
AVX512_FP16
Convert eight packed FP16 values in
VCVTTPH2QQ zmm1{k1}{z},
OR AVX10.1
xmm2/m128/m16bcst to eight signed quadword
xmm2/m128/m16bcst {sae}
integers, and store the result in zmm1 using
truncation subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Quarter
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed FP16 values in the source operand to signed quadword integers in the destination
operand.
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result cannot be
represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked,
the indefinite integer value 80000000_00000000H is returned.
The destination elements are updated according to the writemask.
Operation
VCVTTPH2QQ dest, src
VL = 128, 256 or 512
KL := VL / 64
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.fp16[0]
ELSE
tsrc := SRC.fp16[j]
DEST.qword[j] := Convert_fp16_to_integer64_truncate(tsrc)
ELSE IF *zeroing*:
DEST.qword[j] := 0
// else dest.qword[j] remains unchanged
DEST[MAXVL-1:VL] := 0
VCVTTPH2QQ-Convert with Truncation Packed FP16 Values to Signed Quadword Integers
Vol. 2C
5-109
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPH2QQ __m512i _mm512_cvtt_roundph_epi64 (__m128h a, int sae);
VCVTTPH2QQ __m512i _mm512_mask_cvtt_roundph_epi64 (__m512i src, __mmask8 k, __m128h a, int sae);
VCVTTPH2QQ __m512i _mm512_maskz_cvtt_roundph_epi64 (__mmask8 k, __m128h a, int sae);
VCVTTPH2QQ __m128i _mm_cvttph_epi64 (__m128h a);
VCVTTPH2QQ __m128i _mm_mask_cvttph_epi64 (__m128i src, __mmask8 k, __m128h a);
VCVTTPH2QQ __m128i _mm_maskz_cvttph_epi64 (__mmask8 k, __m128h a);
VCVTTPH2QQ __m256i _mm256_cvttph_epi64 (__m128h a);
VCVTTPH2QQ __m256i _mm256_mask_cvttph_epi64 (__m256i src, __mmask8 k, __m128h a);
VCVTTPH2QQ __m256i _mm256_maskz_cvttph_epi64 (__mmask8 k, __m128h a);
VCVTTPH2QQ __m512i _mm512_cvttph_epi64 (__m128h a);
VCVTTPH2QQ __m512i _mm512_mask_cvttph_epi64 (__m512i src, __mmask8 k, __m128h a);
VCVTTPH2QQ __m512i _mm512_maskz_cvttph_epi64 (__mmask8 k, __m128h a);
SIMD Floating-Point Exceptions
Invalid, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
VCVTTPH2QQ-Convert with Truncation Packed FP16 Values to Signed Quadword Integers
Vol. 2C
5-110
VCVTTPH2UDQ-Convert with Truncation Packed FP16 Values to Unsigned Doubleword
Integers
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.NP.MAP5.W0 78 /r
A
V/V
(AVX512_FP16
Convert four packed FP16 values in
VCVTTPH2UDQ xmm1{k1}{z},
AND AVX512VL)
xmm2/m64/m16bcst to four unsigned
xmm2/m64/m16bcst
OR AVX10.1
doubleword integers, and store the result in
xmm1 using truncation subject to writemask k1.
EVEX.256.NP.MAP5.W0 78 /r
A
V/V
(AVX512_FP16
Convert eight packed FP16 values in
VCVTTPH2UDQ ymm1{k1}{z},
AND AVX512VL)
xmm2/m128/m16bcst to eight unsigned
xmm2/m128/m16bcst
OR AVX10.1
doubleword integers, and store the result in
ymm1 using truncation subject to writemask k1.
EVEX.512.NP.MAP5.W0 78 /r
A
V/V
AVX512_FP16
Convert sixteen packed FP16 values in
VCVTTPH2UDQ zmm1{k1}{z},
OR AVX10.1
ymm2/m256/m16bcst to sixteen unsigned
ymm2/m256/m16bcst {sae}
doubleword integers, and store the result in
zmm1 using truncation subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Half
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed FP16 values in the source operand to unsigned doubleword integers in the destina-
tion operand.
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result cannot be
represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked,
the integer value FFFFFFFFH is returned.
The destination elements are updated according to the writemask.
Operation
VCVTTPH2UDQ dest, src
VL = 128, 256 or 512
KL := VL / 32
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.fp16[0]
ELSE
tsrc := SRC.fp16[j]
DEST.dword[j] := Convert_fp16_to_unsigned_integer32_truncate(tsrc)
ELSE IF *zeroing*:
DEST.dword[j] := 0
// else dest.dword[j] remains unchanged
DEST[MAXVL-1:VL] := 0
VCVTTPH2UDQ-Convert with Truncation Packed FP16 Values to Unsigned Doubleword Integers
Vol. 2C
5-111
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPH2UDQ __m512i _mm512_cvtt_roundph_epu32 (__m256h a, int sae);
VCVTTPH2UDQ __m512i _mm512_mask_cvtt_roundph_epu32 (__m512i src, __mmask16 k, __m256h a, int sae);
VCVTTPH2UDQ __m512i _mm512_maskz_cvtt_roundph_epu32 (__mmask16 k, __m256h a, int sae);
VCVTTPH2UDQ __m128i _mm_cvttph_epu32 (__m128h a);
VCVTTPH2UDQ __m128i _mm_mask_cvttph_epu32 (__m128i src, __mmask8 k, __m128h a);
VCVTTPH2UDQ __m128i _mm_maskz_cvttph_epu32 (__mmask8 k, __m128h a);
VCVTTPH2UDQ __m256i _mm256_cvttph_epu32 (__m128h a);
VCVTTPH2UDQ __m256i _mm256_mask_cvttph_epu32 (__m256i src, __mmask8 k, __m128h a);
VCVTTPH2UDQ __m256i _mm256_maskz_cvttph_epu32 (__mmask8 k, __m128h a);
VCVTTPH2UDQ __m512i _mm512_cvttph_epu32 (__m256h a);
VCVTTPH2UDQ __m512i _mm512_mask_cvttph_epu32 (__m512i src, __mmask16 k, __m256h a);
VCVTTPH2UDQ __m512i _mm512_maskz_cvttph_epu32 (__mmask16 k, __m256h a);
SIMD Floating-Point Exceptions
Invalid, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
VCVTTPH2UDQ-Convert with Truncation Packed FP16 Values to Unsigned Doubleword Integers
Vol. 2C
5-112
VCVTTPH2UQQ-Convert with Truncation Packed FP16 Values to Unsigned Quadword Integers
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.66.MAP5.W0 78 /r
A
V/V
(AVX512_FP16
Convert two packed FP16 values in
VCVTTPH2UQQ xmm1{k1}{z},
AND AVX512VL)
xmm2/m32/m16bcst to two unsigned quadword
xmm2/m32/m16bcst
OR AVX10.1
integers, and store the result in xmm1 using
truncation subject to writemask k1.
EVEX.256.66.MAP5.W0 78 /r
A
V/V
(AVX512_FP16
Convert four packed FP16 values in
VCVTTPH2UQQ ymm1{k1}{z},
AND AVX512VL)
xmm2/m64/m16bcst to four unsigned quadword
xmm2/m64/m16bcst
OR AVX10.1
integers, and store the result in ymm1 using
truncation subject to writemask k1.
EVEX.512.66.MAP5.W0 78 /r
A
V/V
AVX512_FP16
Convert eight packed FP16 values in
VCVTTPH2UQQ zmm1{k1}{z},
OR AVX10.1
xmm2/m128/m16bcst to eight unsigned
xmm2/m128/m16bcst {sae}
quadword integers, and store the result in zmm1
using truncation subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Quarter
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed FP16 values in the source operand to unsigned quadword integers in the destina-
tion operand.
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result cannot be
represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked,
the integer value FFFFFFFF_FFFFFFFFH is returned.
The destination elements are updated according to the writemask.
Operation
VCVTTPH2UQQ dest, src
VL = 128, 256 or 512
KL := VL / 64
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.fp16[0]
ELSE
tsrc := SRC.fp16[j]
DEST.qword[j] := Convert_fp16_to_unsigned_integer64_truncate(tsrc)
ELSE IF *zeroing*:
DEST.qword[j] := 0
// else dest.qword[j] remains unchanged
DEST[MAXVL-1:VL] := 0
VCVTTPH2UQQ-Convert with Truncation Packed FP16 Values to Unsigned Quadword Integers
Vol. 2C
5-113
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPH2UQQ __m512i _mm512_cvtt_roundph_epu64 (__m128h a, int sae);
VCVTTPH2UQQ __m512i _mm512_mask_cvtt_roundph_epu64 (__m512i src, __mmask8 k, __m128h a, int sae);
VCVTTPH2UQQ __m512i _mm512_maskz_cvtt_roundph_epu64 (__mmask8 k, __m128h a, int sae);
VCVTTPH2UQQ __m128i _mm_cvttph_epu64 (__m128h a);
VCVTTPH2UQQ __m128i _mm_mask_cvttph_epu64 (__m128i src, __mmask8 k, __m128h a);
VCVTTPH2UQQ __m128i _mm_maskz_cvttph_epu64 (__mmask8 k, __m128h a);
VCVTTPH2UQQ __m256i _mm256_cvttph_epu64 (__m128h a);
VCVTTPH2UQQ __m256i _mm256_mask_cvttph_epu64 (__m256i src, __mmask8 k, __m128h a);
VCVTTPH2UQQ __m256i _mm256_maskz_cvttph_epu64 (__mmask8 k, __m128h a);
VCVTTPH2UQQ __m512i _mm512_cvttph_epu64 (__m128h a);
VCVTTPH2UQQ __m512i _mm512_mask_cvttph_epu64 (__m512i src, __mmask8 k, __m128h a);
VCVTTPH2UQQ __m512i _mm512_maskz_cvttph_epu64 (__mmask8 k, __m128h a);
SIMD Floating-Point Exceptions
Invalid, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
VCVTTPH2UQQ-Convert with Truncation Packed FP16 Values to Unsigned Quadword Integers
Vol. 2C
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VCVTTPH2UW-Convert Packed FP16 Values to Unsigned Word Integers
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.NP.MAP5.W0 7C /r
A
V/V
(AVX512_FP16
Convert eight packed FP16 values in
VCVTTPH2UW xmm1{k1}{z},
AND AVX512VL)
xmm2/m128/m16bcst to eight unsigned word
xmm2/m128/m16bcst
OR AVX10.1
integers, and store the result in xmm1 using
truncation subject to writemask k1.
EVEX.256.NP.MAP5.W0 7C /r
A
V/V
(AVX512_FP16
Convert sixteen packed FP16 values in
VCVTTPH2UW ymm1{k1}{z},
AND AVX512VL)
ymm2/m256/m16bcst to sixteen unsigned word
ymm2/m256/m16bcst
OR AVX10.1
integers, and store the result in ymm1 using
truncation subject to writemask k1.
EVEX.512.NP.MAP5.W0 7C /r
A
V/V
AVX512_FP16
Convert thirty-two packed FP16 values in
VCVTTPH2UW zmm1{k1}{z},
OR AVX10.1
zmm2/m512/m16bcst to thirty-two unsigned
zmm2/m512/m16bcst {sae}
word integers, and store the result in zmm1
using truncation subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed FP16 values in the source operand to unsigned word integers in the destination
operand.
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result cannot be
represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked,
the integer value FFFFH is returned.
The destination elements are updated according to the writemask.
Operation
VCVTTPH2UW dest, src
VL = 128, 256 or 512
KL := VL / 16
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.fp16[0]
ELSE
tsrc := SRC.fp16[j]
DEST.word[j] := Convert_fp16_to_unsigned_integer16_truncate(tsrc)
ELSE IF *zeroing*:
DEST.word[j] := 0
// else dest.word[j] remains unchanged
DEST[MAXVL-1:VL] := 0
VCVTTPH2UW-Convert Packed FP16 Values to Unsigned Word Integers
Vol. 2C
5-115
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPH2UW __m512i _mm512_cvtt_roundph_epu16 (__m512h a, int sae);
VCVTTPH2UW __m512i _mm512_mask_cvtt_roundph_epu16 (__m512i src, __mmask32 k, __m512h a, int sae);
VCVTTPH2UW __m512i _mm512_maskz_cvtt_roundph_epu16 (__mmask32 k, __m512h a, int sae);
VCVTTPH2UW __m128i _mm_cvttph_epu16 (__m128h a);
VCVTTPH2UW __m128i _mm_mask_cvttph_epu16 (__m128i src, __mmask8 k, __m128h a);
VCVTTPH2UW __m128i _mm_maskz_cvttph_epu16 (__mmask8 k, __m128h a);
VCVTTPH2UW __m256i _mm256_cvttph_epu16 (__m256h a);
VCVTTPH2UW __m256i _mm256_mask_cvttph_epu16 (__m256i src, __mmask16 k, __m256h a);
VCVTTPH2UW __m256i _mm256_maskz_cvttph_epu16 (__mmask16 k, __m256h a);
VCVTTPH2UW __m512i _mm512_cvttph_epu16 (__m512h a);
VCVTTPH2UW __m512i _mm512_mask_cvttph_epu16 (__m512i src, __mmask32 k, __m512h a);
VCVTTPH2UW __m512i _mm512_maskz_cvttph_epu16 (__mmask32 k, __m512h a);
SIMD Floating-Point Exceptions
Invalid, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
VCVTTPH2UW-Convert Packed FP16 Values to Unsigned Word Integers
Vol. 2C
5-116
VCVTTPH2W-Convert Packed FP16 Values to Signed Word Integers
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.66.MAP5.W0 7C /r
A
V/V
(AVX512_FP16
Convert eight packed FP16 values in
VCVTTPH2W xmm1{k1}{z},
AND AVX512VL)
xmm2/m128/m16bcst to eight signed word
xmm2/m128/m16bcst
OR AVX10.1
integers, and store the result in xmm1 using
truncation subject to writemask k1.
EVEX.256.66.MAP5.W0 7C /r
A
V/V
(AVX512_FP16
Convert sixteen packed FP16 values in
VCVTTPH2W ymm1{k1}{z},
AND AVX512VL)
ymm2/m256/m16bcst to sixteen signed word
ymm2/m256/m16bcst
OR AVX10.1
integers, and store the result in ymm1 using
truncation subject to writemask k1.
EVEX.512.66.MAP5.W0 7C /r
A
V/V
AVX512_FP16
Convert thirty-two packed FP16 values in
VCVTTPH2W zmm1{k1}{z},
OR AVX10.1
zmm2/m512/m16bcst to thirty-two signed word
zmm2/m512/m16bcst {sae}
integers, and store the result in zmm1 using
truncation subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed FP16 values in the source operand to signed word integers in the destination
operand.
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result cannot be
represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked,
the integer indefinite value 8000H is returned.
The destination elements are updated according to the writemask.
Operation
VCVTTPH2W dest, src
VL = 128, 256 or 512
KL := VL / 16
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.fp16[0]
ELSE
tsrc := SRC.fp16[j]
DEST.word[j] := Convert_fp16_to_integer16_truncate(tsrc)
ELSE IF *zeroing*:
DEST.word[j] := 0
// else dest.word[j] remains unchanged
DEST[MAXVL-1:VL] := 0
VCVTTPH2W-Convert Packed FP16 Values to Signed Word Integers
Vol. 2C
5-117
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPH2W __m512i _mm512_cvtt_roundph_epi16 (__m512h a, int sae);
VCVTTPH2W __m512i _mm512_mask_cvtt_roundph_epi16 (__m512i src, __mmask32 k, __m512h a, int sae);
VCVTTPH2W __m512i _mm512_maskz_cvtt_roundph_epi16 (__mmask32 k, __m512h a, int sae);
VCVTTPH2W __m128i _mm_cvttph_epi16 (__m128h a);
VCVTTPH2W __m128i _mm_mask_cvttph_epi16 (__m128i src, __mmask8 k, __m128h a);
VCVTTPH2W __m128i _mm_maskz_cvttph_epi16 (__mmask8 k, __m128h a);
VCVTTPH2W __m256i _mm256_cvttph_epi16 (__m256h a);
VCVTTPH2W __m256i _mm256_mask_cvttph_epi16 (__m256i src, __mmask16 k, __m256h a);
VCVTTPH2W __m256i _mm256_maskz_cvttph_epi16 (__mmask16 k, __m256h a);
VCVTTPH2W __m512i _mm512_cvttph_epi16 (__m512h a);
VCVTTPH2W __m512i _mm512_mask_cvttph_epi16 (__m512i src, __mmask32 k, __m512h a);
VCVTTPH2W __m512i _mm512_maskz_cvttph_epi16 (__mmask32 k, __m512h a);
SIMD Floating-Point Exceptions
Invalid, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
VCVTTPH2W-Convert Packed FP16 Values to Signed Word Integers
Vol. 2C
5-118
VCVTTPS2QQ-Convert With Truncation Packed Single Precision Floating-Point Values to
Packed Signed Quadword Integer Values
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.66.0F.W0 7A /r
A
V/V
(AVX512VL AND
Convert two packed single precision floating-point values
VCVTTPS2QQ xmm1 {k1}{z},
AVX512DQ) OR
from xmm2/m64/m32bcst to two packed signed
xmm2/m64/m32bcst
AVX10.1
quadword values in xmm1 using truncation subject to
writemask k1.
EVEX.256.66.0F.W0 7A /r
A
V/V
(AVX512VL AND
Convert four packed single precision floating-point values
VCVTTPS2QQ ymm1 {k1}{z},
AVX512DQ) OR
from xmm2/m128/m32bcst to four packed signed
xmm2/m128/m32bcst
AVX10.1
quadword values in ymm1 using truncation subject to
writemask k1.
EVEX.512.66.0F.W0 7A /r
A
V/V
AVX512DQ
Convert eight packed single precision floating-point values
VCVTTPS2QQ zmm1 {k1}{z},
OR AVX10.1
from ymm2/m256/m32bcst to eight packed signed
ymm2/m256/m32bcst {sae}
quadword values in zmm1 using truncation subject to
writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Half
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts with truncation packed single precision floating-point values in the source operand to eight signed quad-
word integers in the destination operand.
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result cannot be
represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked,
the indefinite integer value 80000000_00000000H is returned.
EVEX encoded versions: The source operand is a YMM/XMM/XMM (low 64 bits) register or a 256/128/64-bit
memory location. The destination operation is a vector register conditionally updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VCVTTPS2QQ (EVEX Encoded Versions) When SRC Operand is a Register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
k := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] :=
Convert_Single_Precision_To_QuadInteger_Truncate(SRC[k+31:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VCVTTPS2QQ-Convert With Truncation Packed Single Precision Floating-Point Values to Packed Signed Quadword Integer Values
Vol. 2C
5-119
VCVTTPS2QQ (EVEX Encoded Versions) When SRC Operand is a Memory Source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
k := j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[i+63:i] :=
Convert_Single_Precision_To_QuadInteger_Truncate(SRC[31:0])
ELSE
DEST[i+63:i] :=
Convert_Single_Precision_To_QuadInteger_Truncate(SRC[k+31:k])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPS2QQ __m512i _mm512_cvttps_epi64( __m256 a);
VCVTTPS2QQ __m512i _mm512_mask_cvttps_epi64( __m512i s, __mmask16 k, __m256 a);
VCVTTPS2QQ __m512i _mm512_maskz_cvttps_epi64( __mmask16 k, __m256 a);
VCVTTPS2QQ __m512i _mm512_cvtt_roundps_epi64( __m256 a, int sae);
VCVTTPS2QQ __m512i _mm512_mask_cvtt_roundps_epi64( __m512i s, __mmask16 k, __m256 a, int sae);
VCVTTPS2QQ __m512i _mm512_maskz_cvtt_roundps_epi64( __mmask16 k, __m256 a, int sae);
VCVTTPS2QQ __m256i _mm256_mask_cvttps_epi64( __m256i s, __mmask8 k, __m128 a);
VCVTTPS2QQ __m256i _mm256_maskz_cvttps_epi64( __mmask8 k, __m128 a);
VCVTTPS2QQ __m128i _mm_mask_cvttps_epi64( __m128i s, __mmask8 k, __m128 a);
VCVTTPS2QQ __m128i _mm_maskz_cvttps_epi64( __mmask8 k, __m128 a);
SIMD Floating-Point Exceptions
Invalid, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VCVTTPS2QQ-Convert With Truncation Packed Single Precision Floating-Point Values to Packed Signed Quadword Integer Values
Vol. 2C
5-120
VCVTTPS2UDQ-Convert With Truncation Packed Single Precision Floating-Point Values to
Packed Unsigned Doubleword Integer Values
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.0F.W0 78 /r
A
V/V
(AVX512VL AND
Convert four packed single precision floating-
VCVTTPS2UDQ xmm1 {k1}{z},
AVX512F) OR
point values from xmm2/m128/m32bcst to four
xmm2/m128/m32bcst
AVX10.1
packed unsigned doubleword values in xmm1
using truncation subject to writemask k1.
EVEX.256.0F.W0 78 /r
A
V/V
(AVX512VL AND
Convert eight packed single precision floating-
VCVTTPS2UDQ ymm1 {k1}{z},
AVX512F) OR
point values from ymm2/m256/m32bcst to eight
ymm2/m256/m32bcst
AVX10.1
packed unsigned doubleword values in ymm1
using truncation subject to writemask k1.
EVEX.512.0F.W0 78 /r
A
V/V
AVX512F
Convert sixteen packed single precision floating-
VCVTTPS2UDQ zmm1 {k1}{z},
OR AVX10.1
point values from zmm2/m512/m32bcst to
zmm2/m512/m32bcst {sae}
sixteen packed unsigned doubleword values in
zmm1 using truncation subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts with truncation packed single precision floating-point values in the source operand to sixteen unsigned
doubleword integers in the destination operand.
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result cannot be
represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked,
the integer value FFFFFFFFH is returned.
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or
a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a
ZMM/YMM/XMM register conditionally updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VCVTTPS2UDQ (EVEX Encoded Versions) When SRC Operand is a Register
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] :=
Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[i+31:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VCVTTPS2UDQ-Convert With Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Doubleword Integer Val-
Vol. 2C
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VCVTTPS2UDQ (EVEX Encoded Versions) When SRC Operand is a Memory Source
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i] :=
Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[31:0])
ELSE
DEST[i+31:i] :=
Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPS2UDQ __m512i _mm512_cvttps_epu32( __m512 a);
VCVTTPS2UDQ __m512i _mm512_mask_cvttps_epu32( __m512i s, __mmask16 k, __m512 a);
VCVTTPS2UDQ __m512i _mm512_maskz_cvttps_epu32( __mmask16 k, __m512 a);
VCVTTPS2UDQ __m512i _mm512_cvtt_roundps_epu32( __m512 a, int sae);
VCVTTPS2UDQ __m512i _mm512_mask_cvtt_roundps_epu32( __m512i s, __mmask16 k, __m512 a, int sae);
VCVTTPS2UDQ __m512i _mm512_maskz_cvtt_roundps_epu32( __mmask16 k, __m512 a, int sae);
VCVTTPS2UDQ __m256i _mm256_mask_cvttps_epu32( __m256i s, __mmask8 k, __m256 a);
VCVTTPS2UDQ __m256i _mm256_maskz_cvttps_epu32( __mmask8 k, __m256 a);
VCVTTPS2UDQ __m128i _mm_mask_cvttps_epu32( __m128i s, __mmask8 k, __m128 a);
VCVTTPS2UDQ __m128i _mm_maskz_cvttps_epu32( __mmask8 k, __m128 a);
SIMD Floating-Point Exceptions
Invalid, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VCVTTPS2UDQ-Convert With Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Doubleword Integer Val-
Vol. 2C
5-122
VCVTTPS2UQQ-Convert With Truncation Packed Single Precision Floating-Point Values to
Packed Unsigned Quadword Integer Values
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.66.0F.W0 78 /r
A
V/V
(AVX512VL AND
Convert two packed single precision floating-point
VCVTTPS2UQQ xmm1 {k1}{z},
AVX512DQ) OR
values from xmm2/m64/m32bcst to two packed
xmm2/m64/m32bcst
AVX10.1
unsigned quadword values in xmm1 using truncation
subject to writemask k1.
EVEX.256.66.0F.W0 78 /r
A
V/V
(AVX512VL AND
Convert four packed single precision floating-point
VCVTTPS2UQQ ymm1 {k1}{z},
AVX512DQ) OR
values from xmm2/m128/m32bcst to four packed
xmm2/m128/m32bcst
AVX10.1
unsigned quadword values in ymm1 using truncation
subject to writemask k1.
EVEX.512.66.0F.W0 78 /r
A
V/V
AVX512DQ
Convert eight packed single precision floating-point
VCVTTPS2UQQ zmm1 {k1}{z},
OR AVX10.1
values from ymm2/m256/m32bcst to eight packed
ymm2/m256/m32bcst {sae}
unsigned quadword values in zmm1 using truncation
subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Half
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts with truncation up to eight packed single precision floating-point values in the source operand to
unsigned quadword integers in the destination operand.
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result cannot be
represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked,
the integer value FFFFFFFF_FFFFFFFFH is returned.
EVEX encoded versions: The source operand is a YMM/XMM/XMM (low 64 bits) register or a 256/128/64-bit
memory location. The destination operation is a vector register conditionally updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VCVTTPS2UQQ (EVEX Encoded Versions) When SRC Operand is a Register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
k := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] :=
Convert_Single_Precision_To_UQuadInteger_Truncate(SRC[k+31:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VCVTTPS2UQQ-Convert With Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values
Vol. 2C
5-123
VCVTTPS2UQQ (EVEX Encoded Versions) When SRC Operand is a Memory Source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
k := j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[i+63:i] :=
Convert_Single_Precision_To_UQuadInteger_Truncate(SRC[31:0])
ELSE
DEST[i+63:i] :=
Convert_Single_Precision_To_UQuadInteger_Truncate(SRC[k+31:k])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPS2UQQ _mm<size>[_mask[z]]_cvtt[_round]ps_epu64
VCVTTPS2UQQ __m512i _mm512_cvttps_epu64( __m256 a);
VCVTTPS2UQQ __m512i _mm512_mask_cvttps_epu64( __m512i s, __mmask16 k, __m256 a);
VCVTTPS2UQQ __m512i _mm512_maskz_cvttps_epu64( __mmask16 k, __m256 a);
VCVTTPS2UQQ __m512i _mm512_cvtt_roundps_epu64( __m256 a, int sae);
VCVTTPS2UQQ __m512i _mm512_mask_cvtt_roundps_epu64( __m512i s, __mmask16 k, __m256 a, int sae);
VCVTTPS2UQQ __m512i _mm512_maskz_cvtt_roundps_epu64( __mmask16 k, __m256 a, int sae);
VCVTTPS2UQQ __m256i _mm256_mask_cvttps_epu64( __m256i s, __mmask8 k, __m128 a);
VCVTTPS2UQQ __m256i _mm256_maskz_cvttps_epu64( __mmask8 k, __m128 a);
VCVTTPS2UQQ __m128i _mm_mask_cvttps_epu64( __m128i s, __mmask8 k, __m128 a);
VCVTTPS2UQQ __m128i _mm_maskz_cvttps_epu64( __mmask8 k, __m128 a);
SIMD Floating-Point Exceptions
Invalid, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VCVTTPS2UQQ-Convert With Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values
Vol. 2C
5-124
VCVTTSD2USI-Convert With Truncation Scalar Double Precision Floating-Point Value to
Unsigned Integer
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
Bit Mode
Feature Flag
Support
EVEX.LLIG.F2.0F.W0 78 /r
A
V/V
AVX512F
Convert one double precision floating-point value
VCVTTSD2USI r32, xmm1/m64{sae}
OR AVX10.1
from xmm1/m64 to one unsigned doubleword
integer r32 using truncation.
EVEX.LLIG.F2.0F.W1 78 /r
A
V/N.E.1
AVX512F
Convert one double precision floating-point value
VCVTTSD2USI r64, xmm1/m64{sae}
OR AVX10.1
from xmm1/m64 to one unsigned quadword
integer zero-extended into r64 using truncation.
NOTES:
1. For this specific instruction, EVEX.W in non-64 bit is ignored; the instruction behaves as if the W0 version is used.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Fixed
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts with truncation a double precision floating-point value in the source operand (the second operand) to an
unsigned doubleword integer (or unsigned quadword integer if operand size is 64 bits) in the destination operand
(the first operand). The source operand can be an XMM register or a 64-bit memory location. The destination
operand is a general-purpose register. When the source operand is an XMM register, the double precision floating-
point value is contained in the low quadword of the register.
When a conversion is inexact, a truncated (round toward zero) value is returned.
If a converted result exceeds the range limits of signed doubleword integer (in non-64-bit modes or 64-bit mode
with REX.W/VEX.W/EVEX.W=0), the floating-point invalid exception is raised, and if this exception is masked, the
integer value FFFFFFFFH is returned.
If a converted result exceeds the range limits of signed quadword integer (in 64-bit mode and
REX.W/VEX.W/EVEX.W = 1), the floating-point invalid exception is raised, and if this exception is masked, the
integer value FFFFFFFF_FFFFFFFFH is returned.
EVEX.W1 version: promotes the instruction to produce 64-bit data in 64-bit mode.
Operation
VCVTTSD2USI (EVEX Encoded Version)
IF 64-Bit Mode and OperandSize = 64
THEN
DEST[63:0] := Convert_Double_Precision_Floating_Point_To_UInteger_Truncate(SRC[63:0]);
ELSE
DEST[31:0] := Convert_Double_Precision_Floating_Point_To_UInteger_Truncate(SRC[63:0]);
FI
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTSD2USI unsigned int _mm_cvttsd_u32(__m128d);
VCVTTSD2USI unsigned int _mm_cvtt_roundsd_u32(__m128d, int sae);
VCVTTSD2USI unsigned __int64 _mm_cvttsd_u64(__m128d);
VCVTTSD2USI unsigned __int64 _mm_cvtt_roundsd_u64(__m128d, int sae);
SIMD Floating-Point Exceptions
Invalid, Precision.
VCVTTSD2USI-Convert With Truncation Scalar Double Precision Floating-Point Value to Unsigned Integer
Vol. 2C
5-125
Other Exceptions
EVEX-encoded instructions, see Table 2-50, “Type E3NF Class Exception Conditions.”
VCVTTSD2USI-Convert With Truncation Scalar Double Precision Floating-Point Value to Unsigned Integer
Vol. 2C
5-126
VCVTTSH2SI-Convert with Truncation Low FP16 Value to a Signed Integer
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.LLIG.F3.MAP5.W0 2C /r
A
V/V1
AVX512_FP16
Convert FP16 value in the low element of
VCVTTSH2SI r32, xmm1/m16 {sae}
OR AVX10.1
xmm1/m16 to a signed doubleword integer and
store the result in r32 using truncation.
EVEX.LLIG.F3.MAP5.W1 2C /r
A
V/N.E.
AVX512_FP16
Convert FP16 value in the low element of
VCVTTSH2SI r64, xmm1/m16 {sae}
OR AVX10.1
xmm1/m16 to a signed quadword integer and
store the result in r64 using truncation.
NOTES:
1. Outside of 64b mode, the EVEX.W field is ignored. The instruction behaves as if W=0 was used.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts the low FP16 element in the source operand to a signed integer in the destination general
purpose register.
When a conversion is inexact, a truncated (round toward zero) value is returned.
If a converted result exceeds the range limits of signed doubleword integer (in non-64-bit modes or 64-bit mode
with REX.W/VEX.W/EVEX.W=0), the floating-point invalid exception is raised, and if this exception is masked, the
indefinite integer value 80000000H is returned.
If a converted result exceeds the range limits of signed quadword integer (in 64-bit mode and
REX.W/VEX.W/EVEX.W = 1), the floating-point invalid exception is raised, and if this exception is masked, the
indefinite integer value 80000000_00000000H is returned.
Operation
VCVTTSH2SI dest, src
IF 64-mode and OperandSize == 64:
DEST.qword := Convert_fp16_to_integer64_truncate(SRC.fp16[0])
ELSE:
DEST.dword := Convert_fp16_to_integer32_truncate(SRC.fp16[0])
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTSH2SI int _mm_cvtt_roundsh_i32 (__m128h a, int sae);
VCVTTSH2SI __int64 _mm_cvtt_roundsh_i64 (__m128h a, int sae);
VCVTTSH2SI int _mm_cvttsh_i32 (__m128h a);
VCVTTSH2SI __int64 _mm_cvttsh_i64 (__m128h a);
SIMD Floating-Point Exceptions
Invalid, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-50, “Type E3NF Class Exception Conditions.”
VCVTTSH2SI-Convert with Truncation Low FP16 Value to a Signed Integer
Vol. 2C
5-127
VCVTTSH2USI-Convert with Truncation Low FP16 Value to an Unsigned Integer
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.LLIG.F3.MAP5.W0 78 /r
A
V/V1
AVX512_FP16
Convert FP16 value in the low element of
VCVTTSH2USI r32, xmm1/m16 {sae}
OR AVX10.1
xmm1/m16 to an unsigned doubleword integer
and store the result in r32 using truncation.
EVEX.LLIG.F3.MAP5.W1 78 /r
A
V/N.E.
AVX512_FP16
Convert FP16 value in the low element of
VCVTTSH2USI r64, xmm1/m16 {sae}
OR AVX10.1
xmm1/m16 to an unsigned quadword integer
and store the result in r64 using truncation.
NOTES:
1. Outside of 64b mode, the EVEX.W field is ignored. The instruction behaves as if W=0 was used.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts the low FP16 element in the source operand to an unsigned integer in the destination
general purpose register.
When a conversion is inexact, a truncated (round toward zero) value is returned.
If a converted result exceeds the range limits of signed doubleword integer (in non-64-bit modes or 64-bit mode
with REX.W/VEX.W/EVEX.W=0), the floating-point invalid exception is raised, and if this exception is masked, the
integer value FFFFFFFFH is returned.
If a converted result exceeds the range limits of signed quadword integer (in 64-bit mode and
REX.W/VEX.W/EVEX.W = 1), the floating-point invalid exception is raised, and if this exception is masked, the
integer value FFFFFFFF_FFFFFFFFH is returned.
Operation
VCVTTSH2USI dest, src
IF 64-mode and OperandSize == 64:
DEST.qword := Convert_fp16_to_unsigned_integer64_truncate(SRC.fp16[0])
ELSE:
DEST.dword := Convert_fp16_to_unsigned_integer32_truncate(SRC.fp16[0])
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTSH2USI unsigned int _mm_cvtt_roundsh_u32 (__m128h a, int sae);
VCVTTSH2USI unsigned __int64 _mm_cvtt_roundsh_u64 (__m128h a, int sae);
VCVTTSH2USI unsigned int _mm_cvttsh_u32 (__m128h a);
VCVTTSH2USI unsigned __int64 _mm_cvttsh_u64 (__m128h a);
SIMD Floating-Point Exceptions
Invalid, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-50, “Type E3NF Class Exception Conditions.”
VCVTTSH2USI-Convert with Truncation Low FP16 Value to an Unsigned Integer
Vol. 2C
5-128
VCVTTSS2USI-Convert With Truncation Scalar Single Precision Floating-Point Value to
Unsigned Integer
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.LLIG.F3.0F.W0 78 /r
A
V/V
AVX512F
Convert one single precision floating-point value
VCVTTSS2USI r32, xmm1/m32{sae}
OR AVX10.1
from xmm1/m32 to one unsigned doubleword
integer in r32 using truncation.
EVEX.LLIG.F3.0F.W1 78 /r
A
V/N.E.1
AVX512F
Convert one single precision floating-point value
VCVTTSS2USI r64, xmm1/m32{sae}
OR AVX10.1
from xmm1/m32 to one unsigned quadword
integer in r64 using truncation.
NOTES:
1. For this specific instruction, EVEX.W in non-64 bit is ignored; the instruction behaves as if the W0 version is used.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Fixed
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts with truncation a single precision floating-point value in the source operand (the second operand) to an
unsigned doubleword integer (or unsigned quadword integer if operand size is 64 bits) in the destination operand
(the first operand). The source operand can be an XMM register or a memory location. The destination operand is
a general-purpose register. When the source operand is an XMM register, the single precision floating-point value
is contained in the low doubleword of the register.
When a conversion is inexact, a truncated (round toward zero) value is returned.
If a converted result exceeds the range limits of signed doubleword integer (in non-64-bit modes or 64-bit mode
with REX.W/VEX.W/EVEX.W=0), the floating-point invalid exception is raised, and if this exception is masked, the
integer value FFFFFFFFH is returned.
If a converted result exceeds the range limits of signed quadword integer (in 64-bit mode and
REX.W/VEX.W/EVEX.W = 1), the floating-point invalid exception is raised, and if this exception is masked, the
integer value FFFFFFFF_FFFFFFFFH is returned.
EVEX.W1 version: promotes the instruction to produce 64-bit data in 64-bit mode.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
VCVTTSS2USI (EVEX Encoded Version)
IF 64-bit Mode and OperandSize = 64
THEN
DEST[63:0] := Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[31:0]);
ELSE
DEST[31:0] := Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[31:0]);
FI;
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTSS2USI unsigned int _mm_cvttss_u32( __m128 a);
VCVTTSS2USI unsigned int _mm_cvtt_roundss_u32( __m128 a, int sae);
VCVTTSS2USI unsigned __int64 _mm_cvttss_u64( __m128 a);
VCVTTSS2USI unsigned __int64 _mm_cvtt_roundss_u64( __m128 a, int sae);
VCVTTSS2USI-Convert With Truncation Scalar Single Precision Floating-Point Value to Unsigned Integer
Vol. 2C
5-129
SIMD Floating-Point Exceptions
Invalid, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-50, “Type E3NF Class Exception Conditions.”
VCVTTSS2USI-Convert With Truncation Scalar Single Precision Floating-Point Value to Unsigned Integer
Vol. 2C
5-130
VCVTUDQ2PD-Convert Packed Unsigned Doubleword Integers to Packed Double Precision
Floating-Point Values
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.F3.0F.W0 7A /r
A
V/V
(AVX512VL AND
Convert two packed unsigned doubleword integers
VCVTUDQ2PD xmm1 {k1}{z},
AVX512F) OR
from xmm2/m64/m32bcst to packed double
xmm2/m64/m32bcst
AVX10.1
precision floating-point values in xmm1 with
writemask k1.
EVEX.256.F3.0F.W0 7A /r
A
V/V
(AVX512VL AND
Convert four packed unsigned doubleword integers
VCVTUDQ2PD ymm1 {k1}{z},
AVX512F) OR
from xmm2/m128/m32bcst to packed double
xmm2/m128/m32bcst
AVX10.1
precision floating-point values in ymm1 with
writemask k1.
EVEX.512.F3.0F.W0 7A /r
A
V/V
AVX512F
Convert eight packed unsigned doubleword integers
VCVTUDQ2PD zmm1 {k1}{z},
OR AVX10.1
from ymm2/m256/m32bcst to eight packed double
ymm2/m256/m32bcst
precision floating-point values in zmm1 with
writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Half
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts packed unsigned doubleword integers in the source operand (second operand) to packed double precision
floating-point values in the destination operand (first operand).
The source operand is a YMM/XMM/XMM (low 64 bits) register, a 256/128/64-bit memory location or a
256/128/64-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM
register conditionally updated with writemask k1.
Attempt to encode this instruction with EVEX embedded rounding is ignored.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
VCVTUDQ2PD (EVEX Encoded Versions) When SRC Operand is a Register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
k := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] :=
Convert_UInteger_To_Double_Precision_Floating_Point(SRC[k+31:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VCVTUDQ2PD (EVEX Encoded Versions) When SRC Operand is a Memory Source
VCVTUDQ2PD-Convert Packed Unsigned Doubleword Integers to Packed Double Precision Floating-Point Values
Vol. 2C
5-131
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
k := j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+63:i] :=
Convert_UInteger_To_Double_Precision_Floating_Point(SRC[31:0])
ELSE
DEST[i+63:i] :=
Convert_UInteger_To_Double_Precision_Floating_Point(SRC[k+31:k])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTUDQ2PD __m512d _mm512_cvtepu32_pd( __m256i a);
VCVTUDQ2PD __m512d _mm512_mask_cvtepu32_pd( __m512d s, __mmask8 k, __m256i a);
VCVTUDQ2PD __m512d _mm512_maskz_cvtepu32_pd( __mmask8 k, __m256i a);
VCVTUDQ2PD __m256d _mm256_cvtepu32_pd( __m128i a);
VCVTUDQ2PD __m256d _mm256_mask_cvtepu32_pd( __m256d s, __mmask8 k, __m128i a);
VCVTUDQ2PD __m256d _mm256_maskz_cvtepu32_pd( __mmask8 k, __m128i a);
VCVTUDQ2PD __m128d _mm_cvtepu32_pd( __m128i a);
VCVTUDQ2PD __m128d _mm_mask_cvtepu32_pd( __m128d s, __mmask8 k, __m128i a);
VCVTUDQ2PD __m128d _mm_maskz_cvtepu32_pd( __mmask8 k, __m128i a);
SIMD Floating-Point Exceptions
None.
Other Exceptions
EVEX-encoded instructions, see Table 2-53, “Type E5 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VCVTUDQ2PD-Convert Packed Unsigned Doubleword Integers to Packed Double Precision Floating-Point Values
Vol. 2C
5-132
VCVTUDQ2PH-Convert Packed Unsigned Doubleword Integers to Packed FP16 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.F2.MAP5.W0 7A /r
A
V/V
(AVX512_FP16
Convert four packed unsigned doubleword
VCVTUDQ2PH xmm1{k1}{z},
AND AVX512VL)
integers from xmm2/m128/m32bcst to packed
xmm2/m128/m32bcst
OR AVX10.1
FP16 values, and store the result in xmm1
subject to writemask k1.
EVEX.256.F2.MAP5.W0 7A /r
A
V/V
(AVX512_FP16
Convert eight packed unsigned doubleword
VCVTUDQ2PH xmm1{k1}{z},
AND AVX512VL)
integers from ymm2/m256/m32bcst to packed
ymm2/m256/m32bcst
OR AVX10.1
FP16 values, and store the result in xmm1
subject to writemask k1.
EVEX.512.F2.MAP5.W0 7A /r
A
V/V
AVX512_FP16
Convert sixteen packed unsigned doubleword
VCVTUDQ2PH ymm1{k1}{z},
OR AVX10.1
integers from zmm2/m512/m32bcst to packed
zmm2/m512/m32bcst {er}
FP16 values, and store the result in ymm1
subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed unsigned doubleword integers in the source operand to packed FP16 values in the
destination operand. The destination elements are updated according to the writemask.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
If the result of the convert operation is overflow and MXCSR.OM=0 then a SIMD exception will be raised with OE=1,
PE=1.
Operation
VCVTUDQ2PH dest, src
VL = 128, 256 or 512
KL := VL / 32
IF *SRC is a register* and (VL = 512) AND (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.dword[0]
ELSE
tsrc := SRC.dword[j]
DEST.fp16[j] := Convert_unsigned_integer32_to_fp16(tsrc)
ELSE IF *zeroing*:
DEST.fp16[j] := 0
// else dest.fp16[j] remains unchanged
DEST[MAXVL-1:VL/2] := 0
VCVTUDQ2PH-Convert Packed Unsigned Doubleword Integers to Packed FP16 Values
Vol. 2C
5-133
Intel C/C++ Compiler Intrinsic Equivalent
VCVTUDQ2PH __m256h _mm512_cvt_roundepu32_ph (__m512i a, int rounding);
VCVTUDQ2PH __m256h _mm512_mask_cvt_roundepu32_ph (__m256h src, __mmask16 k, __m512i a, int rounding);
VCVTUDQ2PH __m256h _mm512_maskz_cvt_roundepu32_ph (__mmask16 k, __m512i a, int rounding);
VCVTUDQ2PH __m128h _mm_cvtepu32_ph (__m128i a);
VCVTUDQ2PH __m128h _mm_mask_cvtepu32_ph (__m128h src, __mmask8 k, __m128i a);
VCVTUDQ2PH __m128h _mm_maskz_cvtepu32_ph (__mmask8 k, __m128i a);
VCVTUDQ2PH __m128h _mm256_cvtepu32_ph (__m256i a);
VCVTUDQ2PH __m128h _mm256_mask_cvtepu32_ph (__m128h src, __mmask8 k, __m256i a);
VCVTUDQ2PH __m128h _mm256_maskz_cvtepu32_ph (__mmask8 k, __m256i a);
VCVTUDQ2PH __m256h _mm512_cvtepu32_ph (__m512i a);
VCVTUDQ2PH __m256h _mm512_mask_cvtepu32_ph (__m256h src, __mmask16 k, __m512i a);
VCVTUDQ2PH __m256h _mm512_maskz_cvtepu32_ph (__mmask16 k, __m512i a);
SIMD Floating-Point Exceptions
Overflow, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
VCVTUDQ2PH-Convert Packed Unsigned Doubleword Integers to Packed FP16 Values
Vol. 2C
5-134
VCVTUDQ2PS-Convert Packed Unsigned Doubleword Integers to Packed Single Precision
Floating-Point Values
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.F2.0F.W0 7A /r
A
V/V
(AVX512VL AND
Convert four packed unsigned doubleword integers
VCVTUDQ2PS xmm1 {k1}{z},
AVX512F) OR
from xmm2/m128/m32bcst to packed single
xmm2/m128/m32bcst
AVX10.1
precision floating-point values in xmm1 with
writemask k1.
EVEX.256.F2.0F.W0 7A /r
A
V/V
(AVX512VL AND
Convert eight packed unsigned doubleword integers
VCVTUDQ2PS ymm1 {k1}{z},
AVX512F) OR
from ymm2/m256/m32bcst to packed single
ymm2/m256/m32bcst
AVX10.1
precision floating-point values in ymm1 with
writemask k1.
EVEX.512.F2.0F.W0 7A /r
A
V/V
AVX512F
Convert sixteen packed unsigned doubleword
VCVTUDQ2PS zmm1 {k1}{z},
OR AVX10.1
integers from zmm2/m512/m32bcst to sixteen
zmm2/m512/m32bcst {er}
packed single precision floating-point values in
zmm1 with writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts packed unsigned doubleword integers in the source operand (second operand) to single precision
floating-point values in the destination operand (first operand).
The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
VCVTUDQ2PS (EVEX Encoded Version) When SRC Operand is a Register
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
ELSE
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
FI;
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] :=
Convert_UInteger_To_Single_Precision_Floating_Point(SRC[i+31:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
VCVTUDQ2PS-Convert Packed Unsigned Doubleword Integers to Packed Single Precision Floating-Point Values
Vol. 2C
5-135
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VCVTUDQ2PS (EVEX Encoded Version) When SRC Operand is a Memory Source
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i] :=
Convert_UInteger_To_Single_Precision_Floating_Point(SRC[31:0])
ELSE
DEST[i+31:i] :=
Convert_UInteger_To_Single_Precision_Floating_Point(SRC[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTUDQ2PS __m512 _mm512_cvtepu32_ps( __m512i a);
VCVTUDQ2PS __m512 _mm512_mask_cvtepu32_ps( __m512 s, __mmask16 k, __m512i a);
VCVTUDQ2PS __m512 _mm512_maskz_cvtepu32_ps( __mmask16 k, __m512i a);
VCVTUDQ2PS __m512 _mm512_cvt_roundepu32_ps( __m512i a, int r);
VCVTUDQ2PS __m512 _mm512_mask_cvt_roundepu32_ps( __m512 s, __mmask16 k, __m512i a, int r);
VCVTUDQ2PS __m512 _mm512_maskz_cvt_roundepu32_ps( __mmask16 k, __m512i a, int r);
VCVTUDQ2PS __m256 _mm256_cvtepu32_ps( __m256i a);
VCVTUDQ2PS __m256 _mm256_mask_cvtepu32_ps( __m256 s, __mmask8 k, __m256i a);
VCVTUDQ2PS __m256 _mm256_maskz_cvtepu32_ps( __mmask8 k, __m256i a);
VCVTUDQ2PS __m128 _mm_cvtepu32_ps( __m128i a);
VCVTUDQ2PS __m128 _mm_mask_cvtepu32_ps( __m128 s, __mmask8 k, __m128i a);
VCVTUDQ2PS __m128 _mm_maskz_cvtepu32_ps( __mmask8 k, __m128i a);
SIMD Floating-Point Exceptions
Precision.
VCVTUDQ2PS-Convert Packed Unsigned Doubleword Integers to Packed Single Precision Floating-Point Values
Vol. 2C
5-136
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VCVTUDQ2PS-Convert Packed Unsigned Doubleword Integers to Packed Single Precision Floating-Point Values
Vol. 2C
5-137
VCVTUQQ2PD-Convert Packed Unsigned Quadword Integers to Packed Double Precision
Floating-Point Values
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.F3.0F.W1 7A /r
A
V/V
(AVX512VL AND
Convert two packed unsigned quadword integers from
VCVTUQQ2PD xmm1 {k1}{z},
AVX512DQ) OR
xmm2/m128/m64bcst to two packed double precision
xmm2/m128/m64bcst
AVX10.1
floating-point values in xmm1 with writemask k1.
EVEX.256.F3.0F.W1 7A /r
A
V/V
(AVX512VL AND
Convert four packed unsigned quadword integers from
VCVTUQQ2PD ymm1 {k1}{z},
AVX512DQ) OR
ymm2/m256/m64bcst to packed double precision
ymm2/m256/m64bcst
AVX10.1
floating-point values in ymm1 with writemask k1.
EVEX.512.F3.0F.W1 7A /r
A
V/V
AVX512DQ
Convert eight packed unsigned quadword integers
VCVTUQQ2PD zmm1 {k1}{z},
OR AVX10.1
from zmm2/m512/m64bcst to eight packed double
zmm2/m512/m64bcst {er}
precision floating-point values in zmm1 with
writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts packed unsigned quadword integers in the source operand (second operand) to packed double precision
floating-point values in the destination operand (first operand).
The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
VCVTUQQ2PD (EVEX Encoded Version) When SRC Operand is a Register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL == 512) AND (EVEX.b == 1)
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
ELSE
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
FI;
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] :=
Convert_UQuadInteger_To_Double_Precision_Floating_Point(SRC[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
VCVTUQQ2PD-Convert Packed Unsigned Quadword Integers to Packed Double Precision Floating-Point Values
Vol. 2C
5-138
DEST[MAXVL-1:VL] := 0
VCVTUQQ2PD (EVEX Encoded Version) When SRC Operand is a Memory Source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[i+63:i] :=
Convert_UQuadInteger_To_Double_Precision_Floating_Point(SRC[63:0])
ELSE
DEST[i+63:i] :=
Convert_UQuadInteger_To_Double_Precision_Floating_Point(SRC[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTUQQ2PD __m512d _mm512_cvtepu64_ps( __m512i a);
VCVTUQQ2PD __m512d _mm512_mask_cvtepu64_ps( __m512d s, __mmask8 k, __m512i a);
VCVTUQQ2PD __m512d _mm512_maskz_cvtepu64_ps( __mmask8 k, __m512i a);
VCVTUQQ2PD __m512d _mm512_cvt_roundepu64_ps( __m512i a, int r);
VCVTUQQ2PD __m512d _mm512_mask_cvt_roundepu64_ps( __m512d s, __mmask8 k, __m512i a, int r);
VCVTUQQ2PD __m512d _mm512_maskz_cvt_roundepu64_ps( __mmask8 k, __m512i a, int r);
VCVTUQQ2PD __m256d _mm256_cvtepu64_ps( __m256i a);
VCVTUQQ2PD __m256d _mm256_mask_cvtepu64_ps( __m256d s, __mmask8 k, __m256i a);
VCVTUQQ2PD __m256d _mm256_maskz_cvtepu64_ps( __mmask8 k, __m256i a);
VCVTUQQ2PD __m128d _mm_cvtepu64_ps( __m128i a);
VCVTUQQ2PD __m128d _mm_mask_cvtepu64_ps( __m128d s, __mmask8 k, __m128i a);
VCVTUQQ2PD __m128d _mm_maskz_cvtepu64_ps( __mmask8 k, __m128i a);
SIMD Floating-Point Exceptions
Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VCVTUQQ2PD-Convert Packed Unsigned Quadword Integers to Packed Double Precision Floating-Point Values
Vol. 2C
5-139
VCVTUQQ2PH-Convert Packed Unsigned Quadword Integers to Packed FP16 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.F2.MAP5.W1 7A /r
A
V/V
(AVX512_FP16
Convert two packed unsigned quadword integers
VCVTUQQ2PH xmm1{k1}{z},
AND AVX512VL)
from xmm2/m128/m64bcst to packed FP16
xmm2/m128/m64bcst
OR AVX10.1
values, and store the result in xmm1 subject to
writemask k1.
EVEX.256.F2.MAP5.W1 7A /r
A
V/V
(AVX512_FP16
Convert four packed unsigned quadword integers
VCVTUQQ2PH xmm1{k1}{z},
AND AVX512VL)
from ymm2/m256/m64bcst to packed FP16
ymm2/m256/m64bcst
OR AVX10.1
values, and store the result in xmm1 subject to
writemask k1.
EVEX.512.F2.MAP5.W1 7A /r
A
V/V
AVX512_FP16
Convert eight packed unsigned quadword
VCVTUQQ2PH xmm1{k1}{z},
OR AVX10.1
integers from zmm2/m512/m64bcst to packed
zmm2/m512/m64bcst {er}
FP16 values, and store the result in xmm1
subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed unsigned quadword integers in the source operand to packed FP16 values in the
destination operand. The destination elements are updated according to the writemask.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
If the result of the convert operation is overflow and MXCSR.OM=0 then a SIMD exception will be raised with OE=1,
PE=1.
Operation
VCVTUQQ2PH dest, src
VL = 128, 256 or 512
KL := VL / 64
IF *SRC is a register* and (VL = 512) AND (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.qword[0]
ELSE
tsrc := SRC.qword[j]
DEST.fp16[j] := Convert_unsigned_integer64_to_fp16(tsrc)
ELSE IF *zeroing*:
DEST.fp16[j] := 0
// else dest.fp16[j] remains unchanged
DEST[MAXVL-1:VL/4] := 0
VCVTUQQ2PH-Convert Packed Unsigned Quadword Integers to Packed FP16 Values
Vol. 2C
5-140
Intel C/C++ Compiler Intrinsic Equivalent
VCVTUQQ2PH __m128h _mm512_cvt_roundepu64_ph (__m512i a, int rounding);
VCVTUQQ2PH __m128h _mm512_mask_cvt_roundepu64_ph (__m128h src, __mmask8 k, __m512i a, int rounding);
VCVTUQQ2PH __m128h _mm512_maskz_cvt_roundepu64_ph (__mmask8 k, __m512i a, int rounding);
VCVTUQQ2PH __m128h _mm_cvtepu64_ph (__m128i a);
VCVTUQQ2PH __m128h _mm_mask_cvtepu64_ph (__m128h src, __mmask8 k, __m128i a);
VCVTUQQ2PH __m128h _mm_maskz_cvtepu64_ph (__mmask8 k, __m128i a);
VCVTUQQ2PH __m128h _mm256_cvtepu64_ph (__m256i a);
VCVTUQQ2PH __m128h _mm256_mask_cvtepu64_ph (__m128h src, __mmask8 k, __m256i a);
VCVTUQQ2PH __m128h _mm256_maskz_cvtepu64_ph (__mmask8 k, __m256i a);
VCVTUQQ2PH __m128h _mm512_cvtepu64_ph (__m512i a);
VCVTUQQ2PH __m128h _mm512_mask_cvtepu64_ph (__m128h src, __mmask8 k, __m512i a);
VCVTUQQ2PH __m128h _mm512_maskz_cvtepu64_ph (__mmask8 k, __m512i a);
SIMD Floating-Point Exceptions
Overflow, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
VCVTUQQ2PH-Convert Packed Unsigned Quadword Integers to Packed FP16 Values
Vol. 2C
5-141
VCVTUQQ2PS-Convert Packed Unsigned Quadword Integers to Packed Single Precision
Floating-Point Values
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.F2.0F.W1 7A /r
A
V/V
(AVX512VL AND
Convert two packed unsigned quadword integers from
VCVTUQQ2PS xmm1 {k1}{z},
AVX512DQ) OR
xmm2/m128/m64bcst to packed single precision
xmm2/m128/m64bcst
AVX10.1
floating-point values in xmm1 with writemask k1.
EVEX.256.F2.0F.W1 7A /r
A
V/V
(AVX512VL AND
Convert four packed unsigned quadword integers from
VCVTUQQ2PS xmm1 {k1}{z},
AVX512DQ) OR
ymm2/m256/m64bcst to packed single precision
ymm2/m256/m64bcst
AVX10.1
floating-point values in xmm1 with writemask k1.
EVEX.512.F2.0F.W1 7A /r
A
V/V
AVX512DQ
Convert eight packed unsigned quadword integers from
VCVTUQQ2PS ymm1 {k1}{z},
OR AVX10.1
zmm2/m512/m64bcst to eight packed single precision
zmm2/m512/m64bcst {er}
floating-point values in ymm1 with writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts packed unsigned quadword integers in the source operand (second operand) to single precision floating-
point values in the destination operand (first operand).
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The destination operand is a YMM/XMM/XMM (low 64 bits) register conditionally updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
VCVTUQQ2PS (EVEX Encoded Version) When SRC Operand is a Register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
ELSE
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
FI;
FOR j := 0 TO KL-1
i := j * 32
k := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] :=
Convert_UQuadInteger_To_Single_Precision_Floating_Point(SRC[k+63:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0
VCVTUQQ2PS-Convert Packed Unsigned Quadword Integers to Packed Single Precision Floating-Point Values
Vol. 2C
5-142
VCVTUQQ2PS (EVEX Encoded Version) When SRC Operand is a Memory Source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 32
k := j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i] :=
Convert_UQuadInteger_To_Single_Precision_Floating_Point(SRC[63:0])
ELSE
DEST[i+31:i] :=
Convert_UQuadInteger_To_Single_Precision_Floating_Point(SRC[k+63:k])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTUQQ2PS __m256 _mm512_cvtepu64_ps( __m512i a);
VCVTUQQ2PS __m256 _mm512_mask_cvtepu64_ps( __m256 s, __mmask8 k, __m512i a);
VCVTUQQ2PS __m256 _mm512_maskz_cvtepu64_ps( __mmask8 k, __m512i a);
VCVTUQQ2PS __m256 _mm512_cvt_roundepu64_ps( __m512i a, int r);
VCVTUQQ2PS __m256 _mm512_mask_cvt_roundepu64_ps( __m256 s, __mmask8 k, __m512i a, int r);
VCVTUQQ2PS __m256 _mm512_maskz_cvt_roundepu64_ps( __mmask8 k, __m512i a, int r);
VCVTUQQ2PS __m128 _mm256_cvtepu64_ps( __m256i a);
VCVTUQQ2PS __m128 _mm256_mask_cvtepu64_ps( __m128 s, __mmask8 k, __m256i a);
VCVTUQQ2PS __m128 _mm256_maskz_cvtepu64_ps( __mmask8 k, __m256i a);
VCVTUQQ2PS __m128 _mm_cvtepu64_ps( __m128i a);
VCVTUQQ2PS __m128 _mm_mask_cvtepu64_ps( __m128 s, __mmask8 k, __m128i a);
VCVTUQQ2PS __m128 _mm_maskz_cvtepu64_ps( __mmask8 k, __m128i a);
SIMD Floating-Point Exceptions
Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VCVTUQQ2PS-Convert Packed Unsigned Quadword Integers to Packed Single Precision Floating-Point Values
Vol. 2C
5-143
VCVTUSI2SD-Convert Unsigned Integer to Scalar Double Precision Floating-Point Value
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
Bit Mode
Feature Flag
Support
EVEX.LLIG.F2.0F.W0 7B /r
A
V/V
AVX512F
Convert one unsigned doubleword integer from
VCVTUSI2SD xmm1, xmm2, r/m32
OR AVX10.1
r/m32 to one double precision floating-point
value in xmm1.
EVEX.LLIG.F2.0F.W1 7B /r
A
V/N.E.1
AVX512F
Convert one unsigned quadword integer from
VCVTUSI2SD xmm1, xmm2, r/m64{er}
OR AVX10.1
r/m64 to one double precision floating-point
value in xmm1.
NOTES:
1. For this specific instruction, EVEX.W in non-64 bit is ignored; the instruction behaves as if the W0 version is used.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Scalar
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Converts an unsigned doubleword integer (or unsigned quadword integer if operand size is 64 bits) in the second
source operand to a double precision floating-point value in the destination operand. The result is stored in the low
quadword of the destination operand. When conversion is inexact, the value returned is rounded according to the
rounding control bits in the MXCSR register.
The second source operand can be a general-purpose register or a 32/64-bit memory location. The first source and
destination operands are XMM registers. Bits (127:64) of the XMM register destination are copied from corre-
sponding bits in the first source operand. Bits (MAXVL-1:128) of the destination register are zeroed.
EVEX.W1 version: promotes the instruction to use 64-bit input value in 64-bit mode.
EVEX.W0 version: attempt to encode this instruction with EVEX embedded rounding is ignored.
Operation
VCVTUSI2SD (EVEX Encoded Version)
IF (SRC2 *is register*) AND (EVEX.b = 1)
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
ELSE
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
FI;
IF 64-Bit Mode And OperandSize = 64
THEN
DEST[63:0] := Convert_UInteger_To_Double_Precision_Floating_Point(SRC2[63:0]);
ELSE
DEST[63:0] := Convert_UInteger_To_Double_Precision_Floating_Point(SRC2[31:0]);
FI;
DEST[127:64] := SRC1[127:64]
DEST[MAXVL-1:128] := 0
VCVTUSI2SD-Convert Unsigned Integer to Scalar Double Precision Floating-Point Value
Vol. 2C
5-144
Intel C/C++ Compiler Intrinsic Equivalent
VCVTUSI2SD __m128d _mm_cvtu32_sd( __m128d s, unsigned a);
VCVTUSI2SD __m128d _mm_cvtu64_sd( __m128d s, unsigned __int64 a);
VCVTUSI2SD __m128d _mm_cvt_roundu64_sd( __m128d s, unsigned __int64 a, int r);
SIMD Floating-Point Exceptions
Precision.
Other Exceptions
See Table 2-50, “Type E3NF Class Exception Conditions” if W1; otherwise, see Table 2-61, “Type E10NF Class
Exception Conditions.”
VCVTUSI2SD-Convert Unsigned Integer to Scalar Double Precision Floating-Point Value
Vol. 2C
5-145
VCVTUSI2SH-Convert Unsigned Doubleword Integer to an FP16 Value
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.LLIG.F3.MAP5.W0 7B /r
A
V/V1
AVX512_FP16
Convert an unsigned doubleword integer from
VCVTUSI2SH xmm1, xmm2, r32/m32
r32/m32 to an FP16 value, and store the result in
{er}
xmm1. Bits 127:16 from xmm2 are copied to
xmm1[127:16].
EVEX.LLIG.F3.MAP5.W1 7B /r
A
V/N.E.
AVX512_FP16
Convert an unsigned quadword integer from
VCVTUSI2SH xmm1, xmm2, r64/m64
r64/m64 to an FP16 value, and store the result in
{er}
xmm1. Bits 127:16 from xmm2 are copied to
xmm1[127:16].
NOTES:
1. Outside of 64b mode, the EVEX.W field is ignored. The instruction behaves as if W=0 was used.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
This instruction converts an unsigned doubleword integer (or unsigned quadword integer if operand size is 64 bits)
in the second source operand to a FP16 value in the destination operand. The result is stored in the low word of the
destination operand. When conversion is inexact, the value returned is rounded according to the rounding control
bits in the MXCSR register or embedded rounding controls.
The second source operand can be a general-purpose register or a 32/64-bit memory location. The first source and
destination operands are XMM registers. Bits 127:16 of the XMM register destination are copied from corre-
sponding bits in the first source operand. Bits MAXVL-1:128 of the destination register are zeroed.
If the result of the convert operation is overflow and MXCSR.OM=0 then a SIMD exception will be raised with OE=1,
PE=1.
Operation
VCVTUSI2SH dest, src1, src2
IF *SRC2 is a register* and (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
IF 64-mode and OperandSize == 64:
DEST.fp16[0] := Convert_unsigned_integer64_to_fp16(SRC2.qword)
ELSE:
DEST.fp16[0] := Convert_unsigned_integer32_to_fp16(SRC2.dword)
DEST[127:16] := SRC1[127:16]
DEST[MAXVL-1:128] := 0
VCVTUSI2SH-Convert Unsigned Doubleword Integer to an FP16 Value
Vol. 2C
5-146
Intel C/C++ Compiler Intrinsic Equivalent
VCVTUSI2SH __m128h _mm_cvt_roundu32_sh (__m128h a, unsigned int b, int rounding);
VCVTUSI2SH __m128h _mm_cvt_roundu64_sh (__m128h a, unsigned __int64 b, int rounding);
VCVTUSI2SH __m128h _mm_cvtu32_sh (__m128h a, unsigned int b);
VCVTUSI2SH __m128h _mm_cvtu64_sh (__m128h a, unsigned __int64 b);
SIMD Floating-Point Exceptions
Overflow, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-50, “Type E3NF Class Exception Conditions.”
VCVTUSI2SH-Convert Unsigned Doubleword Integer to an FP16 Value
Vol. 2C
5-147
VCVTUSI2SS-Convert Unsigned Integer to Scalar Single Precision Floating-Point Value
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
Bit Mode
Feature Flag
Support
EVEX.LLIG.F3.0F.W0 7B /r
A
V/V
AVX512F
Convert one unsigned doubleword integer from
VCVTUSI2SS xmm1, xmm2, r/m32{er}
OR AVX10.1
r/m32 to one single precision floating-point value in
xmm1.
EVEX.LLIG.F3.0F.W1 7B /r
A
V/N.E.1
AVX512F
Convert one unsigned quadword integer from
VCVTUSI2SS xmm1, xmm2, r/m64{er}
OR AVX10.1
r/m64 to one single precision floating-point value in
xmm1.
NOTES:
1. For this specific instruction, EVEX.W in non-64 bit is ignored; the instruction behaves as if the W0 version is used.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Scalar
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Converts an unsigned doubleword integer (or unsigned quadword integer if operand size is 64 bits) in the source
operand (second operand) to a single precision floating-point value in the destination operand (first operand). The
source operand can be a general-purpose register or a memory location. The destination operand is an XMM
register. The result is stored in the low doubleword of the destination operand. When a conversion is inexact, the
value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding
control bits.
The second source operand can be a general-purpose register or a 32/64-bit memory location. The first source and
destination operands are XMM registers. Bits (127:32) of the XMM register destination are copied from corre-
sponding bits in the first source operand. Bits (MAXVL-1:128) of the destination register are zeroed.
EVEX.W1 version: promotes the instruction to use 64-bit input value in 64-bit mode.
Operation
VCVTUSI2SS (EVEX Encoded Version)
IF (SRC2 *is register*) AND (EVEX.b = 1)
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
ELSE
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
FI;
IF 64-Bit Mode And OperandSize = 64
THEN
DEST[31:0] := Convert_UInteger_To_Single_Precision_Floating_Point(SRC[63:0]);
ELSE
DEST[31:0] := Convert_UInteger_To_Single_Precision_Floating_Point(SRC[31:0]);
FI;
DEST[127:32] := SRC1[127:32]
DEST[MAXVL-1:128] := 0
VCVTUSI2SS-Convert Unsigned Integer to Scalar Single Precision Floating-Point Value
Vol. 2C
5-148
Intel C/C++ Compiler Intrinsic Equivalent
VCVTUSI2SS __m128 _mm_cvtu32_ss( __m128 s, unsigned a);
VCVTUSI2SS __m128 _mm_cvt_roundu32_ss( __m128 s, unsigned a, int r);
VCVTUSI2SS __m128 _mm_cvtu64_ss( __m128 s, unsigned __int64 a);
VCVTUSI2SS __m128 _mm_cvt_roundu64_ss( __m128 s, unsigned __int64 a, int r);
SIMD Floating-Point Exceptions
Precision.
Other Exceptions
See Table 2-50, “Type E3NF Class Exception Conditions.”
VCVTUSI2SS-Convert Unsigned Integer to Scalar Single Precision Floating-Point Value
Vol. 2C
5-149
VCVTUW2PH-Convert Packed Unsigned Word Integers to FP16 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.F2.MAP5.W0 7D /r
A
V/V
(AVX512_FP16
Convert eight packed unsigned word integers
VCVTUW2PH xmm1{k1}{z},
AND AVX512VL)
from xmm2/m128/m16bcst to FP16 values, and
xmm2/m128/m16bcst
OR AVX10.1
store the result in xmm1 subject to writemask k1.
EVEX.256.F2.MAP5.W0 7D /r
A
V/V
(AVX512_FP16
Convert sixteen packed unsigned word integers
VCVTUW2PH ymm1{k1}{z},
AND AVX512VL)
from ymm2/m256/m16bcst to FP16 values, and
ymm2/m256/m16bcst
OR AVX10.1
store the result in ymm1 subject to writemask k1.
EVEX.512.F2.MAP5.W0 7D /r
A
V/V
AVX512_FP16
Convert thirty-two packed unsigned word
VCVTUW2PH zmm1{k1}{z},
OR AVX10.1
integers from zmm2/m512/m16bcst to FP16
zmm2/m512/m16bcst {er}
values, and store the result in zmm1 subject to
writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed unsigned word integers in the source operand to FP16 values in the destination
operand. When conversion is inexact, the value returned is rounded according to the rounding control bits in the
MXCSR register or embedded rounding controls.
The destination elements are updated according to the writemask.
If the result of the convert operation is overflow and MXCSR.OM=0 then a SIMD exception will be raised with OE=1,
PE=1.
Operation
VCVTUW2PH dest, src
VL = 128, 256 or 512
KL := VL / 16
IF *SRC is a register* and (VL = 512) AND (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.word[0]
ELSE
tsrc := SRC.word[j]
DEST.fp16[j] := Convert_unsignd_integer16_to_fp16(tsrc)
ELSE IF *zeroing*:
DEST.fp16[j] := 0
// else dest.fp16[j] remains unchanged
DEST[MAXVL-1:VL] := 0
VCVTUW2PH-Convert Packed Unsigned Word Integers to FP16 Values
Vol. 2C
5-150
Intel C/C++ Compiler Intrinsic Equivalent
VCVTUW2PH __m512h _mm512_cvt_roundepu16_ph (__m512i a, int rounding);
VCVTUW2PH __m512h _mm512_mask_cvt_roundepu16_ph (__m512h src, __mmask32 k, __m512i a, int rounding);
VCVTUW2PH __m512h _mm512_maskz_cvt_roundepu16_ph (__mmask32 k, __m512i a, int rounding);
VCVTUW2PH __m128h _mm_cvtepu16_ph (__m128i a);
VCVTUW2PH __m128h _mm_mask_cvtepu16_ph (__m128h src, __mmask8 k, __m128i a);
VCVTUW2PH __m128h _mm_maskz_cvtepu16_ph (__mmask8 k, __m128i a);
VCVTUW2PH __m256h _mm256_cvtepu16_ph (__m256i a);
VCVTUW2PH __m256h _mm256_mask_cvtepu16_ph (__m256h src, __mmask16 k, __m256i a);
VCVTUW2PH __m256h _mm256_maskz_cvtepu16_ph (__mmask16 k, __m256i a);
VCVTUW2PH __m512h _mm512_cvtepu16_ph (__m512i a);
VCVTUW2PH __m512h _mm512_mask_cvtepu16_ph (__m512h src, __mmask32 k, __m512i a);
VCVTUW2PH __m512h _mm512_maskz_cvtepu16_ph (__mmask32 k, __m512i a);
SIMD Floating-Point Exceptions
Overflow, Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
VCVTUW2PH-Convert Packed Unsigned Word Integers to FP16 Values
Vol. 2C
5-151
VCVTW2PH-Convert Packed Signed Word Integers to FP16 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.F3.MAP5.W0 7D /r
A
V/V
(AVX512_FP16
Convert eight packed signed word integers from
VCVTW2PH xmm1{k1}{z},
AND AVX512VL)
xmm2/m128/m16bcst to FP16 values, and store
xmm2/m128/m16bcst
OR AVX10.1
the result in xmm1 subject to writemask k1.
EVEX.256.F3.MAP5.W0 7D /r
A
V/V
(AVX512_FP16
Convert sixteen packed signed word integers
VCVTW2PH ymm1{k1}{z},
AND AVX512VL)
from ymm2/m256/m16bcst to FP16 values, and
ymm2/m256/m16bcst
OR AVX10.1
store the result in ymm1 subject to writemask k1.
EVEX.512.F3.MAP5.W0 7D /r
A
V/V
AVX512_FP16
Convert thirty-two packed signed word integers
VCVTW2PH zmm1{k1}{z},
OR AVX10.1
from zmm2/m512/m16bcst to FP16 values, and
zmm2/m512/m16bcst {er}
store the result in zmm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed signed word integers in the source operand to FP16 values in the destination
operand. When conversion is inexact, the value returned is rounded according to the rounding control bits in the
MXCSR register or embedded rounding controls.
The destination elements are updated according to the writemask.
Operation
VCVTW2PH dest, src
VL = 128, 256 or 512
KL := VL / 16
IF *SRC is a register* and (VL = 512) AND (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.word[0]
ELSE
tsrc := SRC.word[j]
DEST.fp16[j] := Convert_integer16_to_fp16(tsrc)
ELSE IF *zeroing*:
DEST.fp16[j] := 0
// else dest.fp16[j] remains unchanged
DEST[MAXVL-1:VL] := 0
VCVTW2PH-Convert Packed Signed Word Integers to FP16 Values
Vol. 2C
5-152
Intel C/C++ Compiler Intrinsic Equivalent
VCVTW2PH __m512h _mm512_cvt_roundepi16_ph (__m512i a, int rounding);
VCVTW2PH __m512h _mm512_mask_cvt_roundepi16_ph (__m512h src, __mmask32 k, __m512i a, int rounding);
VCVTW2PH __m512h _mm512_maskz_cvt_roundepi16_ph (__mmask32 k, __m512i a, int rounding);
VCVTW2PH __m128h _mm_cvtepi16_ph (__m128i a);
VCVTW2PH __m128h _mm_mask_cvtepi16_ph (__m128h src, __mmask8 k, __m128i a);
VCVTW2PH __m128h _mm_maskz_cvtepi16_ph (__mmask8 k, __m128i a);
VCVTW2PH __m256h _mm256_cvtepi16_ph (__m256i a);
VCVTW2PH __m256h _mm256_mask_cvtepi16_ph (__m256h src, __mmask16 k, __m256i a);
VCVTW2PH __m256h _mm256_maskz_cvtepi16_ph (__mmask16 k, __m256i a);
VCVTW2PH __m512h _mm512_cvtepi16_ph (__m512i a);
VCVTW2PH __m512h _mm512_mask_cvtepi16_ph (__m512h src, __mmask32 k, __m512i a);
VCVTW2PH __m512h _mm512_maskz_cvtepi16_ph (__mmask32 k, __m512i a);
SIMD Floating-Point Exceptions
Precision.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
VCVTW2PH-Convert Packed Signed Word Integers to FP16 Values
Vol. 2C
5-153
VDBPSADBW-Double Block Packed Sum-Absolute-Differences (SAD) on Unsigned Bytes
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.66.0F3A.W0 42 /r ib
A
V/V
(AVX512VL AND
Compute packed SAD word results of unsigned bytes in
VDBPSADBW xmm1 {k1}{z}, xmm2,
AVX512BW) OR
dword block from xmm2 with unsigned bytes of dword
xmm3/m128, imm8
AVX10.1
blocks transformed from xmm3/m128 using the shuffle
controls in imm8. Results are written to xmm1 under the
writemask k1.
EVEX.256.66.0F3A.W0 42 /r ib
A
V/V
(AVX512VL AND
Compute packed SAD word results of unsigned bytes in
VDBPSADBW ymm1 {k1}{z}, ymm2,
AVX512BW) OR
dword block from ymm2 with unsigned bytes of dword
ymm3/m256, imm8
AVX10.1
blocks transformed from ymm3/m256 using the shuffle
controls in imm8. Results are written to ymm1 under the
writemask k1.
EVEX.512.66.0F3A.W0 42 /r ib
A
V/V
AVX512BW
Compute packed SAD word results of unsigned bytes in
VDBPSADBW zmm1 {k1}{z}, zmm2,
OR AVX10.1
dword block from zmm2 with unsigned bytes of dword
zmm3/m512, imm8
blocks transformed from zmm3/m512 using the shuffle
controls in imm8. Results are written to zmm1 under the
writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full Mem
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
imm8
Description
Compute packed SAD (sum of absolute differences) word results of unsigned bytes from two 32-bit dword
elements. Packed SAD word results are calculated in multiples of qword superblocks, producing 4 SAD word results
in each 64-bit superblock of the destination register.
Within each super block of packed word results, the SAD results from two 32-bit dword elements are calculated as
follows:
• The lower two word results are calculated each from the SAD operation between a sliding dword element within
a qword superblock from an intermediate vector with a stationary dword element in the corresponding qword
superblock of the first source operand. The intermediate vector, see “Tmp1” in Figure 5-8, is constructed from
the second source operand the imm8 byte as shuffle control to select dword elements within a 128-bit lane of
the second source operand. The two sliding dword elements in a qword superblock of Tmp1 are located at byte
offset 0 and 1 within the superblock, respectively. The stationary dword element in the qword superblock from
the first source operand is located at byte offset 0.
• The next two word results are calculated each from the SAD operation between a sliding dword element within
a qword superblock from the intermediate vector Tmp1 with a second stationary dword element in the corre-
sponding qword superblock of the first source operand. The two sliding dword elements in a qword superblock
of Tmp1 are located at byte offset 2and 3 within the superblock, respectively. The stationary dword element in
the qword superblock from the first source operand is located at byte offset 4.
• The intermediate vector is constructed in 128-bits lanes. Within each 128-bit lane, each dword element of the
intermediate vector is selected by a two-bit field within the imm8 byte on the corresponding 128-bits of the
second source operand. The imm8 byte serves as dword shuffle control within each 128-bit lanes of the inter-
mediate vector and the second source operand, similarly to PSHUFD.
The first source operand is a ZMM/YMM/XMM register. The second source operand is a ZMM/YMM/XMM register, or
a 512/256/128-bit memory location. The destination operand is conditionally updated based on writemask k1 at
16-bit word granularity.
VDBPSADBW-Double Block Packed Sum-Absolute-Differences (SAD) on Unsigned Bytes
Vol. 2C
5-154
127+128*n
95+128*n
63+128*n
31+128*n
128*n
128-bit Lane of Src2
DW3
DW2
DW1
DW0
00B: DW0
01B: DW1
imm8 shuffle control
10B: DW2
11B: DW3
7
5
3
1
0
127+128*n
95+128*n
63+128*n
31+128*n
128*n
128-bit Lane of Tmp1
Tmp1 qword superblock
55
47
39
31
24
39
31
23
15
8
Tmp1 sliding dword
Tmp1 sliding dword
63
55
47
39
32
31
23
15
7
0
Src1 stationary dword 0
Src1 stationary dword 1
_
_
_
_
_
_
_
_
abs
abs
abs
abs
abs
abs
abs
abs
+
47
39
31
23
16
+
31
23
15
7
0
Tmp1 sliding dword
Tmp1 sliding dword
63
55
47
39
32
31
23
15
7
0
Src1 stationary dword 1
Src1 stationary dword 0
_
_
_
_
_
_
_
_
abs
abs
abs
abs
abs
abs
abs
abs
+
+
63
47
31
15
0
Destination qword superblock
Figure 5-8. 64-bit Super Block of SAD Operation in VDBPSADBW
Operation
VDBPSADBW (EVEX Encoded Versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
Selection of quadruplets:
FOR I = 0 to VL step 128
TMP1[I+31:I] := select (SRC2[I+127: I], imm8[1:0])
TMP1[I+63: I+32] := select (SRC2[I+127: I], imm8[3:2])
TMP1[I+95: I+64] := select (SRC2[I+127: I], imm8[5:4])
TMP1[I+127: I+96] := select (SRC2[I+127: I], imm8[7:6])
END FOR
SAD of quadruplets:
FOR I =0 to VL step 64
TMP_DEST[I+15:I] := ABS(SRC1[I+7: I] - TMP1[I+7: I]) +
ABS(SRC1[I+15: I+8]- TMP1[I+15: I+8]) +
VDBPSADBW-Double Block Packed Sum-Absolute-Differences (SAD) on Unsigned Bytes
Vol. 2C
5-155