Intel 64 and IA-32 Architectures. Software Developer’s Manual (2026)

PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION

CPUID.10H -- Intel® Resource Director Technology (Intel® RDT) Allocation

CPUID.10H returns information for Intel Resource Director Technology Allocation. This leaf is valid when

CPUID.07H.00H:EBX.RDT_A[15] = 1. As described below, software uses the bit vector returned in EBX by subleaf

00H to determine the available QoS Enforcement (allocation) resource types that are supported in the

processor. This information is necessary for software to configure each class of services using capability bit masks

in the QoS Mask registers, IA32_resourceType_Mask_n.

• This leaf is valid if CPUID.07H.00H:EBX.RDT_A[15] = 1 and MAX_LEAF ≥ 10H.

• If the leaf is valid, sub-leaf 00H is always valid. Sub-leaf n (n ≥ 1) is only valid when (CPUID.10H.00H:EBX[n] ==

1).

CPUID.10H.00H -- Intel® RDT Allocation Main Sub-Leaf

CPUID.10H.00H returns information about Intel RDT Allocation.

Table 21-40. Leaf 10H.00H Intel® Resource Director Technology (Intel® RDT) Allocation

Field Name

Description

Domain

EAX[31:0]

Reserved

Reserved.

EBX[0]

Reserved

Reserved.

EBX[1]

CAT_L3

If 1, supports L3 Cache Allocation Technology.

Platform

Sub-leaf index 0 reports valid resource

identification (ResID) starting at bit position 1

of EBX.

EBX[2]

CAT_L2

If 1, supports L2 Cache Allocation Technology.

Platform

EBX[3]

MBA

If 1, supports Memory Bandwidth Allocation.

Platform

EBX[4]

Reserved

Reserved.

EBX[5]

CBA

If 1, supports Cache Bandwidth Allocation.

Platform

EBX[6]

RESOURCE_PRIORITY

If 1, supports Resource Priority.

Platform

EBX[31:7]

Reserved

Reserved.

ECX[31:0]

Reserved

Reserved.

EDX[31:0]

Reserved

Reserved.

CPUID.10H.00H returns information about the bit-vector representation of QoS Enforcement resource types that

are supported in the processor. Each bit, starting from bit 1, corresponds to a specific resource type if the bit is set.

The bit position corresponds to the sub-leaf index (or ResID) that software must use to query QoS enforcement

capability available for that type.

CPUID.10H.01H -- L3 Cache Allocation Technology

CPUID.10H.ResID=1 returns information about L3 Cache Allocation Technology.

Table 21-41. Leaf 10H.01H Intel® Resource Director Technology (Intel® RDT) Allocation

Field Name

Description

Domain

EAX[4:0]

CAT_L3_BITMASK_LENGTH

Length of the capacity bit mask for the

Platform

corresponding ResID.

Add one to the return value to get the result.

EAX[31:5]

Reserved

Reserved.

EBX[31:0]

CAT_L3_CONTENTION

Bit-granular map of isolation/contention of

Platform

allocation units.

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PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION

ECX[0]

Reserved

Reserved.

ECX[1]

CAT_L3_NONCPU

If 1, supports L3 CAT for non-CPU agents.

Platform

ECX[2]

CAT_L3_CDP

If 1, supports L3 Code and Data Prioritization

Platform

Technology.

ECX[3]

CAT_L3_NONCONTIG

If 1, supports non-contiguous capacity

Platform

bitmasks. The bits that are set in the various

IA32_L3_MASK_n registers do not have to be

contiguous.

ECX[31:4]

Reserved

Reserved.

EDX[15:0]

CAT_L3_MAX_CLOS

Highest Class of Service (COS) number

Platform

supported for this ResID.

EDX[31:16]

Reserved

Reserved.

CPUID.10H.02H -- L2 Cache Allocation Technology

CPUID.10H.ResID=2 returns information about L2 Cache Allocation Technology.

Table 21-42. Leaf 10H.02H Intel® Resource Director Technology (Intel® RDT) Allocation

Field Name

Description

Domain

EAX[4:0]

CAT_L2_BITMASK_LENGTH

Length of the capacity bit mask for the

Platform

corresponding ResID.

Add one to the return value to get the result.

EAX[31:5]

Reserved

Reserved.

EBX[31:0]

CAT_L2_CONTENTION

Bit-granular map of isolation/contention of

Platform

allocation units.

ECX[1:0]

Reserved

Reserved.

ECX[2]

CAT_L2_CDP

If 1, supports L2 Code and Data Prioritization

Platform

Technology.

ECX[3]

CAT_L2_NONCONTIG

If 1, supports non-contiguous capacity

Platform

bitmasks. The bits that are set in the various

IA32_L2_MASK_n registers do not have to be

contiguous.

ECX[31:4]

Reserved

Reserved.

EDX[15:0]

CAT_L2_MAX_CLOS

Highest Class of Service (COS) number

Platform

supported for this ResID.

EDX[31:16]

Reserved

Reserved.

CPUID.10H.03H -- Memory Bandwidth Allocation

CPUID.10H.ResID=3 returns information about Memory Bandwidth Allocation.

Table 21-43. Leaf 10H.03H Intel® Resource Director Technology (Intel® RDT) Allocation

Field Name

Description

Domain

EAX[11:0]

MBA_MAX

Reports the maximum MBA throttling value

Platform

supported for the corresponding ResID.

Add one to the return value to get the result.

EAX[31:12]

Reserved

Reserved.

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EBX[31:0]

Reserved

Reserved.

ECX[0]

PER_THREAD_MBA

Per-thread MBA controls are supported.

Platform

ECX[1]

Reserved

Reserved.

ECX[2]

MBA_LINEAR

If 1, the response of the delay values is linear.

Platform

ECX[31:3]

Reserved

Reserved.

EDX[15:0]

MBA_MAX_CLOS

Highest Class of Service (COS) number

Platform

supported for this ResID.

EDX[31:16]

Reserved

Reserved.

CPUID.10H.05H -- Cache Bandwidth Allocation

Table 21-44. Leaf 10H.05H Intel® Resource Director Technology (Intel® RDT) Allocation

Field Name

Description

Domain

EAX[7:0]

CBA_MAX_LEVELS

Reports the maximum core throttling level

Platform

supported for the corresponding ResID. Add one

to the return value to get the number of

throttling levels supported.

EAX[11:8]

BW_SCOPE

If 1, indicates the logical processor scope of the

Platform

IA32_QoS_Core_BW_Thrtl_n MSRs. Other

values are reserved.

EAX[31:12]

Reserved

Reserved.

EBX[31:0]

Reserved

Reserved.

ECX[2:0]

Reserved

Reserved.

ECX[3]

CBA_LINEAR

If 1, the response of the bandwidth control is

Platform

approximately linear. If 0, the response of the

bandwidth control is non-linear.

ECX[31:4]

Reserved

Reserved.

EDX[15:0]

CBA_MAX_CLOS

Highest Class of Service (COS) number

Platform

supported for this ResID.

EDX[31:16]

Reserved

Reserved.

CPUID.10H.06H -- Resource Priority Control

Table 21-45. Leaf 10H.06H Intel® Resource Director Technology (Intel® RDT) Allocation

Field Name

Description

Domain

EAX[0]

THREAD_ENABLE

If 1, supports per-thread enable of RP through

Platform

the IA32_RESOURCE_PRIORITY MSR.

EAX[1]

PACKAGE_ENABLE

If 1, supports physical processor package

Platform

enable of RP through the IA32_RESOURCE

PRIORITY_PKG MSR.

EAX[31:2]

Reserved

Reserved.

EBX[31:0]

Reserved

Reserved.

ECX[31:0]

Reserved

Reserved.

EDX[31:0]

Reserved

Reserved.

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PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION

CPUID.12H -- Intel® Software Guard Extensions (Intel® SGX) Capability

CPUID.12H returns information about Intel® SGX capabilities. More details can be found in Chapter 35, “Introduc-

tion to Intel® Software Guard Extensions,” and Chapter 36, “Enclave Access Control and Data Structures,” of the

Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3D.

• This leaf is valid when CPUID.07H.00H:EBX.SGX[2] = 1 and MAX_LEAF ≥ 12H.

• If the leaf is valid, sub-leaf 00H and 01H are always valid. Sub-leaf n (n ≥ 2) is only valid when

CPUID.12H.n:EAX[3:0] != 0.

CPUID.12H.00H -- Intel® SGX Main Sub-Leaf

CPUID.12H.00H returns information about Intel® SGX capabilities. It is only valid when CPUID.07H.00H:EBX.SGX

= 1.

Table 21-47. Leaf 12H.00H Intel® Software Guard Extensions (Intel® SGX) Capability

Field Name

Description

Domain

EAX[0]

SGX1

If 1, supports the collection of SGX1 Leaf

Platform

functions.

EAX[1]

SGX2

If 1, supports the collection of SGX2 Leaf

Platform

functions.

EAX[6:2]

Reserved

Reserved.

EAX[7]

EVERIFYREPORT2

If 1, supports the ENCLU instruction Leaf

Platform

EVERIFYREPORT2.

EAX[9:8]

Reserved

Reserved.

EAX[10]

EUPDATESVN

If 1, supports the ENCLS instruction Leaf

Platform

EUPDATESVN.

EAX[11]

EDECCSSA

If 1, supports the ENCLU instruction Leaf

Platform

EDECCSSA.

EAX[31:12]

Reserved

Reserved.

EBX[31:0]

MISCSELECT

Bit vector of supported extended SGX features.

Platform

The definition of MISCSELECT can be found in

Section 36.7.2, “SECS.MISCSELECT Field,” of the

Intel® 64 and IA-32 Architectures Software

Developer’s Manual, Volume 3D.

ECX[31:0]

Reserved

Reserved.

EDX[7:0]

MAX_ENCLAVE_SIZE_NOT_64

The maximum supported enclave size in non-

Platform

64-bit mode is 2^(EDX[7:0]).

EDX[15:8]

MAX_ENCLAVE_SIZE_64

The maximum supported enclave size in 64-bit

Platform

mode is 2^(EDX[15:8]).

EDX[31:16]

Reserved

Reserved.

CPUID.12H.01H -- Intel® SGX Attributes

CPUID.12H.01H returns information about Intel® SGX Attributes. It is only valid when CPUID.07H.00H:EBX.SGX =

Table 21-48. Leaf 12H.01H Intel® Software Guard Extensions (Intel® SGX) Capability

Field Name

Description

Domain

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PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION

EAX[31:0]

ECREATE_SECS_ATTRIBUTES_31_0

Reports the valid bits of

Platform

SECS.ATTRIBUTES[31:0] that software can set

with ECREATE.

EBX[31:0]

ECREATE_SECS_ATTRIBUTES_63_32

Reports the valid bits of

Platform

SECS.ATTRIBUTES[63:32] that software can set

with ECREATE.

ECX[31:0]

ECREATE_SECS_ATTRIBUTES_95_64

Reports the valid bits of

Platform

SECS.ATTRIBUTES[95:64] that software can set

with ECREATE.

EDX[31:0]

ECREATE_SECS_ATTRIBUTES_127_96

Reports the valid bits of

Platform

SECS.ATTRIBUTES[127:96] that software can

set with ECREATE.

The definition of the attributes can be found in Section 36.7.1, “ATTRIBUTES,” of the Intel® 64 and IA-32 Architec-

tures Software Developer’s Manual, Volume 3D

CPUID.12H -- n≥2 - Intel® SGX Enclave Page Cache

CPUID.12H with ECX≥2 returns information about Intel® SGX Enclave Page Cache and is supported if

CPUID.07H.00H:EBX.SGX = 1.

For sub-leaves where ECX≥2, the definition of EAX[31:4], EBX, ECX, and EDX depends on the sub-leaf type listed

below.

Sub-Leaf Encoding Type EAX[3:0] = 0000b (Invalid)

This sub-leaf is invalid. EDX:ECX:EBX:EAX return 0.

CPUID.12H -- Sub-Leaf Encoding Type EAX[3:0] = 0001b

This sub-leaf enumerates an EPC section with EDX:ECX, EBX:EAX defined as follows.

Table 21-49. Leaf 12H.SUB-LEAF ENCODING TYPE EAX[3:0] = 0001B Intel® Software Guard Extensions (Intel® SGX)

Capability

Field Name

Description

Domain

EAX[3:0]

SUB_LEAF_TYPE

Value is 0001b.

Platform

EAX[11:4]

Reserved

Reserved.

EAX[31:12]

EPC_SECTION_ADDR_31_12

Bits 31:12 of the physical address of the base

Platform

of the EPC section.

EBX[19:0]

EPC_SECTION_ADDR_51_32

Bits 51:32 of the physical address of the base

Platform

of the EPC section.

EBX[31:20]

Reserved

Reserved.

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PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION

CPUID.14H -- Intel® Processor Trace (Intel® PT)

CPUID.14H returns information about Intel® Processor Trace (PT).

CPUID.14H.00H returns information about Intel Processor Trace extensions.

CPUID.14H.n (n > 0 and less than the number of non-zero bits in CPUID.14H.00H:EAX) returns information about

packet generation in Intel Processor Trace.

For more details on Intel PT, see Chapter 34, “Intel® Processor Trace,” in the Intel® 64 and IA-32 Architectures

Software Developer’s Manual, Volume 3D.

• This leaf is valid when CPUID.07H.00H:EBX.INTEL_PROC_TRACE[25] = 1 and MAX_LEAF ≥ 14H.

• The maximum sub-leaf value for ECX is specified in CPUID.14H.00H.EAX[31:0] MAX_SUBLEAF.

• If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index n is invalid if n exceeds the

value that sub-leaf 0 returns in EAX.

CPUID.14H.00H -- Intel® PT Main Sub-Leaf

CPUID.14H.00H returns information about Intel Processor Trace extensions.

Table 21-51. Leaf 14H.00H Intel® Processor Trace (Intel® PT)

Field Name

Description

Domain

EAX[31:0]

MAX_SUBLEAF

Reports the maximum sub-leaf supported in

Platform

leaf 14H.

EBX[0]

CR3_FILTER

If 1, supports that IA32_RTIT_CTL.CR3Filter

Platform

can be set to 1, and that

IA32_RTIT_CR3_MATCH MSR can be accessed.

EBX[1]

CYC_ACC

If 1, supports Configurable PSB and Cycle-

Platform

Accurate Mode.

EBX[2]

IP_FILTER

If 1, supports IP Filtering, TraceStop filtering,

Platform

and preservation of Intel PT MSRs across warm

reset.

EBX[3]

MTC

If 1, supports MTC timing packet and

Platform

suppression of COFI-based packets.

EBX[4]

PTWRITE

If 1, supports PTWRITE. Writes can set

Platform

IA32_RTIT_CTL[12] (PTWEn) and

IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE

can generate packets.

EBX[5]

PWR_EVT_TRACE

If 1, supports Power Event Trace. Writes can set

Platform

IA32_RTIT_CTL[4] (PwrEvtEn), enabling Power

Event Trace packet generation.

EBX[6]

PMI_PRESERVE

If 1, supports the PSB and PMI preservation.

Platform

Writes can set IA32_RTIT_CTL[56]

(InjectPsbPmiOnEn- able), enabling the

processor to set IA32_RTIT_STATUS[7]

(PendTopaPMI) and/or IA32_RTIT_STATUS[6]

(PendPSB) in order to preserve ToPA PMIs

and/or PSBs otherwise lost due to Intel PT

disable. Writes can also set PendToPAPMI and

PendPSB.

EBX[7]

EVENT_TRACE

If 1, supports that writes can set

Platform

IA32_RTIT_CTL[31] (EventEn), enabling Event

Trace packet generation.

EBX[8]

TNT_DIS

If 1, supports that writes can set

Platform

IA32_RTIT_CTL[55] (DisTNT), disabling TNT

packet generation.

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EBX[9]

PTTT

If 1, Processor Trace Trigger Tracing (PTTT) is

Platform

supported.

EBX[31:10]

Reserved

Reserved.

ECX[0]

TOPAOUT

If 1, supports that tracing can be enabled with

Platform

IA32_RTIT_CTL.ToPA = 1, hence utilizing the

ToPA output scheme;

IA32_RTIT_OUTPUT_BASE and

IA32_RTIT_OUPUT_MASK_PTRS MSRs can be

accessed.

ECX[1]

MENTRY

If 1, supports that ToPA tables can hold any

Platform

number of output entries, up to the maximum

allowed by the MaskOrTableOffset field of

IA32_RTIT_OUTPUT_MASK_PTRS.

ECX[2]

SNGL_RNG_OUT

If 1, supports the Single-Range Output scheme.

Platform

ECX[3]

TRACE_TRANSPORT_SUBSYSTEM

If 1, supports the output to Trace Transport

Platform

subsystem.

ECX[30:4]

Reserved

Reserved.

ECX[31]

LIP

If 1, the generated packets which contain IP

Logical

payloads contain LIP. If 0, the generated packets

Processor

which contain IP payloads contain Effective IP.

Trace segments using a flat memory model will

generate the same information regardless of

how a logical processor reports this value since

LIP=EIP.

EDX[31:0]

Reserved

Reserved.

CPUID.14H.01H -- Feature Information Sub-Leaf

CPUID.14H.01H returns information about packet generation in Intel Processor Trace.

Table 21-52. Leaf 14H.01H Intel® Processor Trace (Intel® PT)

Field Name

Description

Domain

EAX[2:0]

RANGECNT

Number of configurable Address Ranges for

Platform

filtering.

EAX[7:3]

Reserved

Reserved.

EAX[10:8]

TRIGGER_CFG_CNT

Number of IA32_RTIT_TRIGGERx_CFG MSRs.

Platform

The number of triggers supported is 4x this

value.

EAX[15:11]

Reserved

Reserved.

EAX[31:16]

MTC_RATE

Bitmap of supported MTC period encodings.

Platform

EBX[15:0]

CYC_THRESHOLDS

Bitmap of supported Cycle Threshold value

Platform

encodings.

EBX[31:16]

PSB_RATE

Bitmap of supported Configurable PSB

Platform

frequency encodings.

ECX[0]

ICNT

If 1, the trigger action EN_ICNT is supported.

Platform

ECX[1]

TRIGGER_PAUSE

If 1, the trigger actions TRACE_PAUSE and

Platform

TRACE_RESUME are supported.

ECX[14:2]

Reserved

Reserved.

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PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION

CPUID.15H -- Time Stamp Counter and Nominal Core Crystal Clock

CPUID.15H returns information about the Time Stamp Counter and the Nominal Core Crystal Clock.

• This leaf is valid if MAX_LEAF ≥ 15H.

• This leaf does not contain sub-leaves and provides the same information regardless of the value of ECX.

Table 21-53. Leaf 15H Time Stamp Counter and Nominal Core Crystal Clock

Field Name

Description

Domain

EAX[31:0]

DENOMINATOR

An unsigned integer which is the denominator

Platform

of the TSC/”core crystal clock” ratio.

EBX[31:0]

NUMERATOR

An unsigned integer which is the numerator of

Platform

the TSC/”core crystal clock” ratio. If 0, the

TSC/”core crystal clock” ratio is not enumerated.

ECX[31:0]

NOMINAL_ART_FREQUENCY

An unsigned integer which is the nominal

Platform

frequency of the core crystal clock in Hz. If 0,

the nominal core crystal clock frequency is not

enumerated. Note, the core crystal clock may

differ from the reference clock, bus clock or

core clock frequencies.

EDX[31:0]

Reserved

Reserved.

Dividing EBX[31:0] by EAX[31:0] provides the ratio of the TSC frequency to the core crystal clock frequency. The

Timestamp Counter frequency is computed by multiplying that ratio by ECX[31:0], such as TSC_frequency = ECX

* EBX/EAX.

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PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION

CPUID.16H -- Processor Frequency Information

CPUID.16H returns information about processor frequency information.

Data is returned from this interface in accordance with the processor's specification and does not reflect actual

values. Suitable use of this data includes the display of processor information in like manner to the processor brand

string and for determining the appropriate range to use when displaying processor information e.g. frequency

history graphs. The returned information should not be used for any other purpose as the returned information

does not accurately correlate to information / counters returned by other processor interfaces.

While a processor may support the Processor Frequency Information leaf, fields that return a value of zero are not

supported.

• This leaf is valid if MAX_LEAF ≥ 16H.

• This leaf does not contain sub-leaves and provides the same information regardless of the value of ECX.

Table 21-54. Leaf 16H Processor Frequency Information

Field Name

Description

Domain

EAX[15:0]

PROCESSOR_BASE_FREQUENCY

Processor Base Frequency (in MHz).

Logical

Processor

EAX[31:16]

Reserved

Reserved.

EBX[15:0]

MAXIMUM_FREQUENCY

Maximum Frequency (in MHz).

Logical

Processor

EBX[31:16]

Reserved

Reserved.

ECX[15:0]

BUS_FREQUENCY

Bus (Reference) Frequency (in MHz).

Logical

Processor

ECX[31:16]

Reserved

Reserved.

EDX[31:0]

Reserved

Reserved.

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PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION

CPUID.17H -- System-on-Chip Vendor Attribute

CPUID.17H returns System-on-Chip vendor attribute information.

• This leaf is valid if CPUID.17H.00H:EAX[31:0] (MaxSOCID_Index) ≥ 3 and MAX_LEAF ≥ 17H.

• The maximum sub-leaf value for ECX is specified in CPUID.17H.00H.EAX[31:0] MaxSOCID_Index.

• If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index n is invalid if n exceeds the

value that sub-leaf 0 returns in EAX.

CPUID.17H.00H -- Main Sub-Leaf

CPUID.17H.00H returns System-on-Chip vendor attribute information.

Table 21-55. Leaf 17H.00H System-on-Chip Vendor Attribute

Field Name

Description

Domain

EAX[31:0]

MAX_SOCID_INDEX

Reports the maximum input value of supported

Platform

Sub-leaf in Leaf 17H.

EBX[15:0]

SOC_VENDOR_ID

SOC Vendor ID.

Platform

EBX[16]

IS_VENDOR_SCHEME

If 1, the SOC Vendor ID field is assigned via an

Platform

industry standard enumeration scheme.

Otherwise, the SOC Vendor ID field is assigned

by Intel.

EBX[31:17]

Reserved

Reserved.

ECX[31:0]

PROJECT_ID

A unique number an SOC vendor assigns to its

Platform

SOC projects.

EDX[31:0]

STEPPING_ID

A unique number within an SOC project that an

Package

SOC vendor assigns.

CPUID.17H.01H -- Vendor Brand String Sub-Leaf (Bytes 0 to 15)

CPUID.17H with ECX=1, 2, or 3 returns information for System-on-Chip vendor branding string.

SOC Vendor Brand String is a UTF-8 encoded string padded with trailing bytes of 00H. The complete SOC Vendor

Brand String is constructed by concatenating in ascending order the output of each sub-leaf 1 to 3. For the output

of each sub-leaf, byte are ordered in ascending order of EAX:EBX:ECX:EDX.

Leaf 17H sub-leaves 4 and above are reserved.

Table 21-56. Leaf 17H.01H System-on-Chip Vendor Attribute

Field Name

Description

Domain

EAX[31:0]

VENDOR_BRAND_STRING_BYTES_0_to_3

SOC Vendor Brand String. UTF-8 encoded string.

Platform

EBX[31:0]

VENDOR_BRAND_STRING_BYTES_4_to_7

SOC Vendor Brand String. UTF-8 encoded string.

Platform

ECX[31:0]

VENDOR_BRAND_STRING_BYTES_8_to_11

SOC Vendor Brand String. UTF-8 encoded string.

Platform

EDX[31:0]

VENDOR_BRAND_STRING_BYTES_12_to_15

SOC Vendor Brand String. UTF-8 encoded string.

Platform

CPUID.17H.02H -- Vendor Brand String Sub-Leaf (Bytes 16 to 31)

Table 21-57. Leaf 17H.02H System-on-Chip Vendor Attribute

Field Name

Description

Domain

EAX[31:0]

VENDOR_BRAND_STRING_BYTES_16_to_19

SOC Vendor Brand String. UTF-8 encoded string.

Platform

EBX[31:0]

VENDOR_BRAND_STRING_BYTES_20_to_23

SOC Vendor Brand String. UTF-8 encoded string.

Platform

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ECX[31:0]

VENDOR_BRAND_STRING_BYTES_24_to_27

SOC Vendor Brand String. UTF-8 encoded string.

Platform

EDX[31:0]

VENDOR_BRAND_STRING_BYTES_28_to_31

SOC Vendor Brand String. UTF-8 encoded string.

Platform

CPUID.17H.03H -- Vendor Brand String Sub-Leaf (Bytes 32 to 47)

Table 21-58. Leaf 17H.03H System-on-Chip Vendor Attribute

Field Name

Description

Domain

EAX[31:0]

VENDOR_BRAND_STRING_BYTES_32_to_35

SOC Vendor Brand String. UTF-8 encoded string.

Platform

EBX[31:0]

VENDOR_BRAND_STRING_BYTES_36_to_39

SOC Vendor Brand String. UTF-8 encoded string.

Platform

ECX[31:0]

VENDOR_BRAND_STRING_BYTES_40_to_43

SOC Vendor Brand String. UTF-8 encoded string.

Platform

EDX[31:0]

VENDOR_BRAND_STRING_BYTES_44_to_47

SOC Vendor Brand String. UTF-8 encoded string.

Platform

CPUID.17H.M>MAXSOCID_INDEX-RESERVED SUB-LEAVES -- m>MaxSOCID_Index-Reserved

Sub-Leaves

CPUID.17H with ECX > MaxSOCID_Index is reserved and returns all zeroes.

Table 21-59. Leaf 17H.M>MAXSOCID_INDEX-RESERVED SUB-LEAVES System-on-Chip Vendor Attribute

Field Name

Description

Domain

EAX[31:0]

Reserved

EBX[31:0]

Reserved

ECX[31:0]

Reserved

EDX[31:0]

Reserved

21-62

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CPUID.18H -- Deterministic Address Translation Parameters

CPUID.18H returns information about the Deterministic Address Translation Parameters. Each sub-leaf enumerates

a different address translation structure.

• This leaf is valid if CPUID.18H.00H:EAX[31:0] <> 0 and MAX_LEAF ≥ 18H.

• The maximum sub-leaf value for ECX is specified in CPUID.18H.00H.EAX[31:0] MAX_SUBLEAF.

• If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index n is invalid if n exceeds the

value that sub-leaf 0 returns in EAX. A sub-leaf index is also invalid if EDX[4:0] returns 0.

• Valid sub-leaves do not need to be contiguous or in any particular order. A valid sub-leaf may be in a higher input

ECX value than an invalid sub-leaf or than a valid sub-leaf of a higher or lower-level structure.

CPUID.18H.00H -- Main Sub-Leaf

Deterministic Address Translation Parameters Main Leaf

Table 21-60. Leaf 18H.00H Deterministic Address Translation Parameters

Field Name

Description

Domain

EAX[31:0]

MAX_SUBLEAF

Reports the maximum input value of supported

Logical

sub-leaf in leaf 18H.

Processor

EBX[31:0]

Reserved

Reserved.

ECX[31:0]

Reserved

Reserved.

EDX[4:0]

TYPE

Will always return 0.

Logical

Processor

EDX[31:5]

Reserved

Reserved.

CPUID.18H.ECX >= 1 -- Sub-Leaves

CPUID.18H with ECX≥1 returns Deterministic Address Translation Parameters information.

Table 21-61. Leaf 18H.ECX >= 1 Deterministic Address Translation Parameters

Field Name

Description

Domain

EAX[31:0]

Reserved

Reserved.

EBX[0]

4KB_ENTRIES

If 1, supports 4K page size entries in this

Logical

structure.

Processor

EBX[1]

2MB_ENTRIES

If 1, supports 2MB page size entries in this

Logical

structure.

Processor

EBX[2]

4MB_ENTRIES

If 1, supports 4MB page size entries in this

Logical

structure.

Processor

EBX[3]

1GB_ENTRIES

If 1, supports 1 GB page size entries in this

Logical

structure.

Processor

EBX[7:4]

Reserved

Reserved.

EBX[10:8]

PARTITIONING

Partitioning (0:Soft partitioning between the

Logical

logical processors sharing this structure).

Processor

EBX[15:11]

Reserved

Reserved.

EBX[31:16]

NUM_WAYS

W = ways of associativity.

Logical

Processor

ECX[31:0]

NUM_SETS

S = number of sets.

Logical

Processor

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PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION

EDX[4:0]

TYPE

00000b: Null (indicates this Sub-leaf is not

Logical

valid).

Processor

00001b: Data TLB.

00010b: Instruction TLB.

00011b: Unified TLB.1

00100b: Load Only TLB. Hit on loads; fills on

both loads and stores.

00101b: Store Only TLB. Hit on stores; fill on

stores.

All other encodings are reserved.

Some unified TLBs will allow a single TLB entry

to satisfy data read/write and instruction

fetches. Others will require separate entries

(e.g., one loaded on data read/write and another

loaded on an instruction fetch). See the Intel®

64 and IA-32 Architectures Optimization

Reference Manual for details of a particular

product.

EDX[7:5]

LEVEL_NUM

Translation cache level (starts at 1).

Logical

Processor

EDX[8]

FULLY_ASSOC

Fully associative structure.

Logical

Processor

EDX[13:9]

Reserved

Reserved.

EDX[25:14]

MAX_LP_ADDRESSABLE_IDS

Maximum number of addressable IDs for logical

Logical

processors sharing this translation cache.

Processor

Add one to the return value to get the result.

EDX[31:26]

Reserved

Reserved.

21-64

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PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION

CPUID.19H -- Key Locker

CPUID.19H returns Key Locker information.

• This leaf is valid if CPUID.07H.00H:ECX.KEY_LOCKER[23] = 1 and MAX_LEAF ≥ 19H.

• This leaf does not contain sub-leaves and provides the same information regardless of the value of ECX.

Table 21-62. Leaf 19H Key Locker

Field Name

Description

Domain

EAX[0]

CPL0_RESTRICT

If 1, supports the Key Locker restriction of

Platform

CPL0-only.¹

EAX[1]

NO_ENCRYPT_RESTRICT

If 1, supports the Key Locker restriction of no-

Platform

encrypt.¹

EAX[2]

NO_DECRYPT_RESTRICT

If 1, supports the Key Locker restriction of no-

Platform

decrypt.¹

EAX[31:3]

Reserved

Reserved.

EBX[0]

AESKLE

If 1, the AES Key Locker instructions are fully

Logical

enabled.

Processor

CPUID.19H:EBX.AESKLE[0] is enumerated as 1

if the AES Key Locker instructions have been

activated by system firmware and CR4.KL[bit

19] = 1. Software can check this bit after

setting CR4.KL to determine whether AES Key

Locker instructions have been enabled. Note

that some processors may allow enabling of

those instructions without activation by system

firmware. Some processors may not support

the use of AES Key Locker instructions in

system-management-mode (SMM). Those

processors enumerate

CPUID.19H:EBX.AESKLE[0] as 0 in SMM

regardless of the setting of CR4.KL.

EBX[1]

Reserved

Reserved.

EBX[2]

AES_WIDE

If 1, supports the AES wide Key Locker

Platform

instructions.¹

EBX[3]

Reserved

Reserved.

EBX[4]

IWKEYBACKUP

If 1, supports the Key Locker MSRs

Platform

(IA32_COPY_LOCAL_TO_PLATFORM,

IA23_COPY_PLATFORM_TO_LOCAL,

IA32_COPY_STATUS, and

IA32_IWKEYBACKUP_STATUS) and backing up

the internal wrapping key.¹

EBX[31:5]

Reserved

Reserved.

ECX[0]

NOBACKUP

If 1, supports the NoBackup parameter to

Platform

LOADIWKEY.¹

ECX[1]

RAND_IWKEY

If 1, supports KeySource encoding of 1

Platform

(randomization of the internal wrapping key).¹

ECX[31:2]

Reserved

Reserved.

EDX[31:0]

Reserved

Reserved.

NOTE

1. This field is valid only if CPUID.19H:EBX.AESKLE[0] = 1.

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PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION

CPUID.1AH -- Native Model ID Enumeration

CPUID.1AH returns Native Model ID information.

This leaf exists on all logical processors in a hybrid package, it may also be present in other processor configura-

tions.

• This leaf is valid if CPUID.1AH.00H:EAX[31:0] <> 0 and MAX_LEAF ≥ 1AH.

• The only valid sub-leaf is 0 and ECX must be set to 0.

Table 21-63. Leaf 1AH Native Model ID Enumeration

Field Name

Description

Domain

EAX[23:0]

CORE_NATIVE_MODEL_ID

The core-type and native model ID can be used

Logical

to uniquely identify the microarchitecture of

Processor

the core. This native model ID is not unique

across core types, and not related to the model

ID reported in CPUID.01H, and does not identify

the SOC.

EAX[31:24]

CORE_TYPE

10H: Reserved

Logical

20H: Intel® Atom®

Processor

30H: Reserved

40H: Intel® Core

The core type may only be used as an

identification of the microarchitecture for this

logical processor and its numeric value has no

significance, neither large nor small. This field

neither implies nor expresses any other

attribute to this logical processor and software

should not assume any.

EBX[31:0]

Reserved

Reserved.

ECX[31:0]

Reserved

Reserved.

EDX[31:0]

Reserved

Reserved.

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PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION

CPUID.1BH -- PCONFIG Information

CPUID.1BH -- Output Registers Format for All Sub-Leaves

CPUID.1BH returns information for PCONFIG capabilities. This information is enumerated in sub-leaves selected by

the value of ECX (starting with 0).

• This leaf is valid if CPUID.07H.00H:EDX.PCONFIG[18] = 1 and MAX_LEAF ≥ 1BH.

• Sub-leaves are enumerated until sub-leaf n, where EAX[11:0] returns 0.

Table 21-64. Leaf 1BH PCONFIG Information

Field Name

Description

Domain

EAX[11:0]

SUB_LEAF_TYPE

0 (Invalid)

Platform

EAX[31:12]

Reserved

Reserved.

EBX[31:0]

Reserved

Reserved.

ECX[31:0]

Reserved

Reserved.

EDX[31:0]

Reserved

Reserved.

Each sub-leaf of CPUID.1BH enumerates its sub-leaf type in EAX. If a sub-leaf type is 0, the sub-leaf is invalid and

zero is returned in EBX, ECX, and EDX. In this case, all subsequent sub-leaves (selected by larger input values of

ECX) are also invalid.

The only valid sub-leaf type currently defined is 1, indicating that the sub-leaf enumerates target identifiers for the

PCONFIG instruction. Any non-zero value returned in EBX, ECX, or EDX indicates a valid target identifier of the

PCONFIG instruction (any value of zero should be ignored). The only target identifier currently defined is 1, indi-

cating TME-MK. See the “PCONFIG-Platform Configuration” instruction in Chapter 4 of the Intel® 64 and IA-32

Architectures Software Developer’s Manual, Volume 2B, for more information.

CPUID.1BH.OUTPUT REGISTERS FOR SUB-LEAVE TYPE TARGET IDENTIFIER (1) -- Output Regis-

ters for Sub-Leave Type Target Identifier (1)

Table 21-65. Leaf 1BH.OUTPUT REGISTERS FOR SUB-LEAVE TYPE TARGET IDENTIFIER (1) PCONFIG Information

Field Name

Description

Domain

EAX[11:0]

SUB_LEAF_TYPE

1 (Target Identifier)

Platform

EAX[31:12]

Reserved

Reserved.

EBX[31:0]

TARGET_IDENTIFIER_1

Target identifier

Platform

ECX[31:0]

TARGET_IDENTIFIER_2

Target identifier

Platform

EDX[31:0]

TARGET_IDENTIFIER_3

Target identifier

Platform

The only current valid target identifier is 1 for MK-TME.

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PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION

CPUID.1CH -- Last Branch Records (LBR) Information

CPUID.1CH returns information about architectural Last Branch Records (LBR). For details on LBR, see Chapter 20,

“Last Branch Records,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.

• This leaf is valid if CPUID.07H.00H:EDX.ARCH_LBRS[19] = 1 and MAX_LEAF ≥ 1CH.

• This leaf does not contain sub-leaves and provides the same information regardless of the value of ECX.

Table 21-66. Leaf 1CH Last Branch Records (LBR) Information

Field Name

Description

Domain

EAX[7:0]

LBR_DEPTH_VALUES

For each bit n set in this field, the

Platform

IA32_LBR_DEPTH.DEPTH value 8*(n+1) is

supported.

EAX[29:8]

Reserved

Reserved.

EAX[30]

DEEP_C_STATE_RESET

If 1, supports that LBRs may be cleared on an

Platform

MWAIT that requests a C-state numerically

greater than C1.

EAX[31]

IP_VALUES_CONTAIN_LIP

If 1, the LBR IP values contain LIP. If 0, IP values

Logical

contain Effective IP.

Processor

Trace segments using a flat memory model will

generate the same information regardless of

how a logical processor reports this value since

LIP = EIP

EBX[0]

CPL_FILTERING

If 1, supports setting IA32_LBR_CTL[2:1] to a

Platform

non-zero value.

EBX[1]

BRANCH_FILTERING

If 1, supports setting IA32_LBR_CTL[22:16] to

Platform

a non-zero value.

EBX[2]

CALL_STACK_MODE

If 1, supports setting IA32_LBR_CTL[3] to 1.

Platform

EBX[31:3]

Reserved

Reserved.

ECX[0]

MISPREDICT_BIT

If 1, IA32_LBR_x_INFO[63] holds indication of

Platform

branch misprediction (MISPRED).

ECX[1]

TIMED_LBRS

If 1, IA32_LBR_x_INFO[15:0] holds CPU cycles

Platform

since last LBR entry (CYC_CNT), and

IA32_LBR_x_INFO[60] holds an indication of

whether the value held there is valid

(CYC_CNT_VALID).

ECX[2]

BRANCH_TYPE_FIELD_SUPPORTED

If 1, IA32_LBR_INFO_x[59:56] holds indication

Platform

of the recorded operation's branch type

(BR_TYPE).

ECX[15:3]

Reserved

Reserved.

ECX[19:16]

EVENT_LOGGING_BITMAP

The event logging bitmap, wherein each set bit

Platform

corresponds to a programmable performance

monitoring counter that supports LBR event

logging.

ECX[31:20]

Reserved

Reserved.

EDX[31:0]

Reserved

Reserved.

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PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION

CPUID.1DH -- Tile Information

CPUID.1DH returns information about tile architecture and tile palette 1 (see Chapter 19, “Programming with

Intel® Advanced Matrix Extensions,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,

Volume 1).

• This leaf is valid if CPUID.07H.00H:EDX.AMX_TILE[24] = 1 and MAX_LEAF ≥ 1DH.

• The maximum sub-leaf value for ECX is specified in CPUID.1DH.00H.EAX[31:0] max_palette.

• If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index n is invalid if n exceeds the

value that sub-leaf 0 returns in EAX.

CPUID.1DH.00H -- Tile Information Main Sub-Leaf

CPUID.1DH.00H returns the tile architecture information.

Table 21-67. Leaf 1DH.00H Tile Information

Field Name

Description

Domain

EAX[31:0]

MAX_PALETTE

Highest numbered palette sub-leaf. Value = 1.

Platform

EBX[31:0]

Reserved

Reserved.

ECX[31:0]

Reserved

Reserved.

EDX[31:0]

Reserved

Reserved.

CPUID.1DH.01H -- Tile Palette 1

CPUID.1DH.01H returns tile palette information.

Table 21-68. Leaf 1DH.01H Tile Information

Field Name

Description

Domain

EAX[15:0]

TOTAL_TILE_BYTES

Palette 1 total_tile_bytes. Value = 8192.

Platform

EAX[31:16]

BYTES_PER_TILE

Palette 1 bytes_per_tile. Value = 1024.

Platform

EBX[15:0]

BYTES_PER_ROW

Palette 1 bytes_per_row. Value = 64.

Platform

EBX[31:16]

MAX_NAMES

Palette 1 max_names (number of tile registers).

Platform

Value = 8.

ECX[15:0]

MAX_ROWS

Palette 1 max_rows. Value = 16.

Platform

ECX[31:16]

Reserved

Reserved.

EDX[31:0]

Reserved

Reserved.

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PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION

CPUID.1FH -- V2 Extended Topology

CPUID.1FH returns information about V2 Extended Topology.

CPUID.1FH is a preferred superset to leaf 0BH. Intel recommends using leaf 1FH when available rather than leaf

0BH and ensuring that any leaf 0BH algorithms are updated to support leaf 1FH.

• This leaf is valid if CPUID.1FH.00H:EBX[15:0] <> 0 and MAX_LEAF ≥ 1FH.

• When the leaf is invalid, CPUID.1FH.00H:ECX.DOMAIN_TYPE[15:8] will report the Domain Type ID as Invalid

(0).

• The sub-leaves are enumerated until sub-leaf n returns 0 in EBX[15:0].

• If ECX contains an invalid sub-leaf index, EAX/EBX return 0. Sub-leaf index n+1 is invalid if sub-leaf n returns

EBX[15:0] as 0.

CPUID.1FH -- ECX >= 0

Table 21-70. Leaf 1FH V2 Extended Topology

Field Name

Description

Domain

EAX[4:0]

SHIFT_COUNT

The number of bits that the x2APIC ID must be

Platform

shifted to the right to address instances of the

next higher-scoped domain. When logical

processor is not supported by the processor,

the value of this field at the Logical Processor

domain sub-leaf may be returned as either 0

(no allocated bits in the x2APIC ID) or 1 (one

allocated bit in the x2APIC ID); software should

plan accordingly.

EAX[31:5]

Reserved

Reserved.

EBX[15:0]

NEXT_LEVEL_NUM_LP

The number of logical processors across all

Logical

instances of this domain within the next higher-

Processor

scoped domain relative to this current logical

processor. (For example, in a processor

socket/package comprising “M” dies of “N” cores

each, where each core has “L” logical

processors, the “die” domain sub-leaf value of

this field would be M*N*L. In an asymmetric

topology this would be the summation of the

value across the lower domain level instances

to create each upper domain level instance.)

This number reflects configuration as shipped

by Intel. Note that the number of logical

processors can be asymmetric in which case “L”

may be different on different logical processors,

as an example a core with 2 logical processors

on the same platform as a core with 1 logical

processor.

Note, software must not use this field to

enumerate processor topology.

Software must not use the value of EBX[15:0]

to enumerate processor topology of the

system. The value is only intended for display

and diagnostic purposes. The actual number of

logical processors available to

BIOS/OS/Applications may be different from the

value of EBX[15:0], depending on software and

platform hardware configurations.

EBX[31:16]

Reserved

Reserved.

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PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION

ECX[7:0]

LEVEL_NUM

The input ECX sub-leaf index.

Platform

ECX[15:8]

DOMAIN_TYPE

This field provides an identification value which

Platform

indicates the domain as shown in the table.

Although domains are ordered, their assigned

identification values are not and software

should not depend on it. (For example, if a new

domain between core and module is specified, it

will have an identification value higher than 5.)

See the table below for the current list of valid

enumerations. Note that enumeration values of

0 and 7-255 are reserved.

ECX[31:16]

Reserved

Reserved.

EDX[31:0]

X2APIC_ID

The x2APIC ID of the current logical processor is

Logical

always valid and does not vary with the sub-

Processor

leaf index in ECX.

The sub-leaves of CPUID.1FH describe an ordered hierarchy of logical processors starting from the smallest scoped

domain of a Logical Processor (sub-leaf index 0) to the Core domain (sub-leaf index 1) to the largest scoped

domain (the last valid sub-leaf index) that is implicitly subordinate to the unenumerated highest-scoped domain of

the processor package (socket).

The details of each valid domain is enumerated by a corresponding sub-leaf. Details for a domain include its type

and how all instances of that domain determine the number of logical processors and x2 APIC ID partitioning at the

next higher-scoped domain. The ordering of domains within the hierarchy is fixed architecturally as shown below.

For a given processor, not all domains may be relevant or enumerated; however, the logical processor and core

domains are always enumerated. As an example, a processor may report an ordered hierarchy consisting only of

“Logical Processor,” “Core,” and “Die.”

For two valid sub-leaves N and N+1, sub-leaf N+1 represents the next immediate higher-scoped domain with

respect to the domain of sub-leaf N for the given processor.

If sub-leaf index “N” returns an invalid domain type in ECX[15:08] (00H), then all sub-leaves with an index greater

than “N” also return an invalid domain type. A sub-leaf returning an invalid domain always returns 0 in EAX and

EBX.

Table 21-71. Hierarchy of Valid Domain Enumerations in CPUID.1FH:ECX[15:8]

Hierarchy

Domain

Domain Type ID Value

Invalid

Lowest

Logical Processor

Core

Module

Tile

Die

DieGrp

Highest

Package/Socket

(Implied)

Reserved

7-255

21-72

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PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION

CPUID.20H -- Processor History Reset Information

CPUID.20H returns information about processor history reset when CPUID.07H.01H:EAX.HRESET[22] = 1.

• This leaf is valid if CPUID.07H.01H:EAX.HRESET[22] = 1 and MAX_LEAF ≥ 20H.

• The maximum sub-leaf value for ECX is specified in CPUID.20H.00H.EAX[31:0] MAX_SUBLEAF.

• If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index n is invalid if n exceeds the

value that sub-leaf 0 returns in EAX.

CPUID.20H.00H -- Processor History Reset Sub-leaf

Table 21-72. Leaf 20H.00H Processor History Reset Information

Field Name

Description

Domain

EAX[31:0]

MAX_SUBLEAF

Reports the maximum number of sub-leaves

Platform

that are supported in leaf 20H.

EBX[0]

THREAD_DIRECTOR_HRESET

Indicates support for both HRESET’s EAX[0]

Platform

parameter, and IA32_HRESET_ENABLE[0] set

by the OS to enable reset of Intel® Thread

Director history.

EBX[31:1]

Reserved

Reserved.

ECX[31:0]

Reserved

Reserved.

EDX[31:0]

Reserved

Reserved.

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PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION

CPUID.23H -- Architectural Performance Monitoring Extended

CPUID.23H returns architectural performance monitoring extended information.

• This leaf is valid if CPUID.07H.01H:EAX.ARCH_PERFMON_EXT[8] = 1 and MAX_LEAF ≥ 23H.

• The sub-leaves of this leaf are enumerated by a bitmask specified in CPUID.23H.00H.EAX[31:0] SUBLEAF_MASK.

The bit numbers of set bits in the bitmask represent valid sub-leaf indexes.

• If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index is invalid if the index as a

bit number is clear in the Available Sub-Leaf Mask or is greater than 31.

CPUID.23H.00H -- Main Sub-Leaf

Table 21-74. Leaf 23H.00H Architectural Performance Monitoring Extended

Field Name

Description

Domain

EAX[31:0]

SUBLEAF_MASK

If bit n is set, sub-leaf n is supported. (For

Logical

unsupported sub-leaves, 0 is returned in the

Processor

registers EAX, EBX, ECX, and EDX.)

EBX[0]

UNITMASK2

If 1, supports the UnitMask2 field in the

Logical

IA32_PERFEVTSELx MSRs.

Processor

EBX[1]

If 1, supports the equal flag in the

Logical

IA32_PERFEVTSELx MSRS.

Processor

EBX[31:2]

Reserved

Reserved.

ECX[7:0]

SLOTS_PER_CYC

If this field is non-zero, it represents the

Logical

number of Top-down Microarchitecture Analysis

Processor

(TMA) slots per cycle. This number can be

multiplied by the number of cycles (from

CPU_CLK_UNHALTED.THREAD /

CPU_CLK_UNHALTED.CORE or

IA32_FIXED_CTR1) to determine the total

number of slots. If this field is zero,

IA32_FIXED_CTR3 should be used to determine

the total number of slots.

ECX[31:8]

Reserved

Reserved.

EDX[31:0]

Reserved

Reserved.

CPUID.23H.01H -- Counter Information Sub-Leaf

Table 21-75. Leaf 23H.01H Architectural Performance Monitoring Extended

Field Name

Description

Domain

EAX[31:0]

GP_COUNTERS

For each bit n set in this field, the processor

Logical

supports general-purpose performance

Processor

monitoring counter n.

EBX[31:0]

FIXED_COUNTERS

For each bit m set in this field, the processor

Logical

supports fixed-function performance

Processor

monitoring counter m.

The valid range of fixed-function counters is 0

through 15.

ECX[31:0]

Reserved

Reserved.

EDX[31:0]

Reserved

Reserved.

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PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION

CPUID.23H.02H -- Bitmap of Auto Counter Reload Sub-Leaf

Table 21-76. Leaf 23H.02H Architectural Performance Monitoring Extended

Field Name

Description

Domain

EAX[31:0]

ACR_GP_RELOAD

General counters that can be reloaded. For each

Logical

bit n set in this field, the processor supports

Processor

ACR for general-purpose performance

monitoring counter n.

EBX[31:0]

ACR_FIXED_RELOAD

Fixed counters that can be reloaded. For each

Logical

bit m set in this field, the processor supports

Processor

ACR for fixed-function performance monitoring

counter m.

ECX[31:0]

ACR_GP_TRIGGER

General counters that can cause reloads. For

Logical

each bit y set in this field, the processor allows

Processor

general-purpose performance monitoring

counter y to reload all existing general-purpose

performance monitoring counters capable of

being reloaded.

EDX[31:0]

ACR_FIXED_TRIGGER

Fixed counters that can cause reloads. For each

Logical

bit x set in this field, the processor allows fixed-

Processor

function performance monitoring counter x to

reload all existing fixed-function performance

monitoring counters capable of being reloaded.

CPUID.23H.03H -- Architectural Performance Monitoring Events Bitmap Sub-Leaf

For each bit n set in this field, the processor supports Architectural Performance Monitoring Event of index n.

Table 21-77. Leaf 23H.03H Architectural Performance Monitoring Extended

Field Name

Description

Domain

EAX[0]

CORE_CYC

If 1, supports architectural index 0.

Logical

Processor

EAX[1]

INSTR_RET

If 1, supports architectural index 1.

Logical

Processor

EAX[2]

REF_CYC

If 1, supports architectural index 2.

Logical

Processor

EAX[3]

LLC_REF

If 1, supports architectural index 3.

Logical

Processor

EAX[4]

LLC_MISSES

If 1, supports architectural index 4.

Logical

Processor

EAX[5]

BR_INSTR_RET

If 1, supports architectural index 5

Logical

Processor

EAX[6]

BR_MISPRED_RET

If 1, supports architectural index 6

Logical

Processor

EAX[7]

SLOTS

If 1, supports architectural index 7

Logical

Processor

EAX[8]

BACKEND

If 1, supports architectural index 8

Logical

Processor

EAX[9]

BADSPEC

If 1, supports architectural index 9

Logical

Processor

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PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION

EAX[10]

FRONTEND

If 1, supports architectural index 10

Logical

Processor

EAX[11]

RETIRING

If 1, supports architectural index 11

Logical

Processor

EAX[12]

LBR_INSERTS

If 1, supports architectural index 12

Logical

Processor

EAX[31:13]

Reserved

Reserved.

EBX[31:0]

Reserved

Reserved.

ECX[31:0]

Reserved

Reserved.

EDX[31:0]

Reserved

Reserved.

CPUID.23H.04H -- PEBS Capabilities

Table 21-78. Leaf 23H.04H Architectural Performance Monitoring Extended

Field Name

Description

Domain

EAX[31:0]

Reserved

Reserved.

EBX[2:0]

Reserved

Reserved.

EBX[3]

ALLOW_IN_RECORD

If 1, indicates that the ALLOW_IN_RECORD bit is

Logical

available in the IA32_PMC_GPn_CFG_C and

Processor

IA32_PMC_FXm_CFG_C MSRs

EBX[7:4]

CNTR

Counters group sub-groups general-purpose

Logical

counters, fixed-function counters, and

Processor

performance metrics are available.

EBX[9:8]

LBR

LBR group and both bits [41:40] are available.

Logical

Processor

EBX[15:10]

Reserved

Reserved.

EBX[23:16]

XER

XER group bits [50:49] and bits [55:53] are

Logical

available. See Section 11.4.4, “XSAVEEnabled

Processor

Registers Group,” for XER fields.

EBX[28:24]

Reserved

Reserved.

EBX[29]

GPR

If 1, the GPR group is available.

Logical

Processor

EBX[30]

AUX

If 1, the AUX group is available.

Logical

Processor

EBX[31]

Reserved

Reserved.

ECX[31:0]

Reserved

Reserved.

EDX[31:0]

Reserved

Reserved.

CPUID.23H.05H -- Arch PEBS GP and Fixed Counters supported

Table 21-79. Leaf 23H.05H Architectural Performance Monitoring Extended

Field Name

Description

Domain

21-78

Vol. 1

PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION

EAX[31:0]

GP_PEBS

Bit vector of general-purpose counters for

Logical

which the Architectural PEBS mechanism is

Processor

available (bit n == GP counter #n). If EAX[n] ==

1, then the IA32_PMC_GPn_CFG_C MSR is

available, and PEBS is supported on that

counter; the PEBS_EN[63] field can be set; and

the RELOAD[31:0] field can be set. Note that

CPUID.23H.04H:EBX governs which adaptive

group bits can be set.

EBX[31:0]

GP_PDIST

General-purpose counters for which PEBS

Logical

supports PDIST.

Processor

ECX[31:0]

FIXED_PEBS

Bit vector of fixed-function counters for which

Logical

the Architectural PEBS mechanism is available.

Processor

If ECX[x] == 1, then the IA32_PMC_FXm_CFG_C

MSR is available, and PEBS is supported; the

PEBS_EN[63] field can be set; and the

RELOAD[31:0] field can be set. Note that

CPUID.23H.04H:EBX governs which adaptive

group bits can be set.

EDX[31:0]

FIXED_PDIST

Fixed-function counters for which PEBS

Logical

supports PDIST.

Processor

Vol. 1

21-79

PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION

CPUID.24H -- Converged Vector ISA

When CPUID.24H, the processor returns Intel AVX10 converged vector ISA information.

This leaf is supported when CPUID.07H.01H:EDX.AVX10[19] = 1.

• This leaf is valid if CPUID.07H.01H:EDX.AVX10[19] = 1 and MAX_LEAF ≥ 24H.

• The maximum sub-leaf value for ECX is specified in CPUID.24H.00H.EAX[31:0] MAX_SUBLEAF.

• If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index n is invalid if n exceeds the

value that sub-leaf 0 returns in EAX.

CPUID.24H.00H -- Converged Vector ISA Main Sub-Leaf

Table 21-80. Leaf 24H.00H Converged Vector ISA

Field Name

Description

Domain

EAX[31:0]

MAX_SUBLEAF

Reports the maximum number of sub-leaves

Platform

that are supported in leaf 24H.

EBX[7:0]

VECTOR_ISA_VERSION

Reports the Intel® AVX10 Converged Vector ISA

Platform

version.

EBX[15:8]

Reserved

Reserved.

EBX[18:16]

Reserved at 111

Always 111b.

Platform

Earlier versions of this specification

documented these bits as enumerating support

for different vector lengths. Processors

enumerating Intel® AVX10 support all vector

lengths.

EBX[31:19]

Reserved

Reserved.

ECX[31:0]

Reserved

Reserved.

EDX[31:0]

Reserved

Reserved.

21-80

Vol. 1

PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION

CPUID.27H -- Intel® Resource Director Technology (Intel® RDT) Asymmetric

Monitoring

CPUID.27H returns information for the Intel Resource Director Technology Monitoring capabilities with asymmetric

topology.

As described below, software uses the bit vector returned in EDX by sub-leaf 00H to determine the available

resource types (ResID) that can be monitored. This information is necessary for software to program the

IA32_PQR_ASSOC and IA32_QM_EVTSEL MSRs such that Quality-of-Service data can be read afterwards from the

IA32_QM_CTR MSR.

• This leaf is valid if CPUID.07H.01H:ECX.RDT_M_ASYM[0] = 1 and MAX_LEAF ≥ 27H.

• If the leaf is valid, sub-leaf 00H is always valid. Sub-leaf n (n ≥ 1) is only valid when (CPUID.27H.00H:EDX[n] ==

1).

• This leaf must be read on each logical processor to determine the support on each processor.

CPUID.27H.00H -- Intel® RDT Asymmetric Monitoring Main Sub-Leaf

CPUID.27H.00H returns information about Intel RDT Monitoring Asymmetric.

Table 21-81. Leaf 27H.00H Intel® Resource Director Technology (Intel® RDT) Asymmetric Monitoring

Field Name

Description

Domain

EAX[31:0]

Reserved

Reserved.

EBX[31:0]

MAX_RMID

Maximum range (zero-based) of RMID within

Logical

this physical processor of all types.

Processor

ECX[31:0]

Reserved

Reserved.

EDX[0]

Reserved

Reserved.

EDX[1]

L3_MON

If 1, supports L3 Cache Intel RDT Monitoring.

Logical

Sub-leaf index 0 reports valid resource type

Processor

starting at bit position 1 of EDX.

EDX[31:2]

Reserved

Reserved.

CPUID.27H.00H returns information about the bit-vector representation of QoS monitoring resource types that are

supported in the processor and maximum range of RMID values the processor can use to monitor of any supported

resource types. Each bit, starting from bit 1, corresponds to a specific resource type if the bit is set. The bit position

corresponds to the sub-leaf index (or ResID) that software must use to query QoS monitoring capability available

for that type.

CPUID.27H.01H -- L3 Cache Intel® Resource Director Technology Asymmetric Monitoring

CPUID.27H.01H returns information about L3 Cache Intel RDT monitoring asymmetric.

Table 21-82. Leaf 27H.01H Intel® Resource Director Technology (Intel® RDT) Asymmetric Monitoring

Field Name

Description

Domain

EAX[7:0]

CTR_WIDTH

The counter width is encoded as an offset from

Logical

24b. A value of zero in this field indicates that

Processor

24-bit counters are supported. A value of 8 in

this field indicates that 32-bit counters are

supported.

EAX[8]

RDT_M_OVF

If 1, supports an overflow bit in the

Logical

IA32_QM_CTR MSR (bit 61).

Processor

Vol. 1

21-81

PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION

CPUID.28H -- Intel® Resource Director Technology (Intel® RDT) Asymmetric

Allocation

CPUID.28H returns information for Intel Resource Director Technology Allocation with asymmetric topology. This

leaf is valid when CPUID.07H.01H:ECX.RDT_A_SYM[1] = 1. As described below, software uses the bit vector

returned in EBX by subleaf 00H to determine the available QoS Enforcement (allocation) resource types that are

supported in the

processor. This information is necessary for software to configure each class of services using capability bit masks

in the QoS Mask registers, IA32_resourceType_Mask_n.

• This leaf is valid if CPUID.07H.01H:ECX.RDT_A_SYM[1] = 1 and MAX_LEAF ≥ 28H.

• If the leaf is valid, sub-leaf 00H is always valid. Sub-leaf n (n ≥ 1) is only valid when (CPUID.28H.00H:EBX[n] ==

1).

CPUID.28H.00H -- Intel® RDT Asymmetric Allocation Main Sub-Leaf

CPUID.28H.00H returns information about Intel RDT Allocation Asymmetric.

Table 21-83. Leaf 28H.00H Intel® Resource Director Technology (Intel® RDT) Asymmetric Allocation

Field Name

Description

Domain

EAX[31:0]

Reserved

Reserved.

EBX[0]

Reserved

Reserved.

EBX[1]

CAT_L3

Supports L3 Cache Allocation Technology if 1.

Logical

Processor

EBX[2]

CAT_L2

Supports L2 Cache Allocation Technology if 1.

Logical

Processor

EBX[3]

MBA

Supports Memory Bandwidth Allocation if 1.

Logical

Processor

EBX[4]

Reserved

Reserved.

EBX[4]

Reserved

Reserved.

EBX[5]

CBA

If 1, supports Cache Bandwidth Allocation.

Logical

Processor

EBX[6]

RESOURCE_PRIORITY

If 1, supports Resource Priority.

Platform

EBX[6:5]

Reserved

Reserved.

EBX[31:7]

Reserved

Reserved.

ECX[31:0]

Reserved

Reserved.

EDX[31:0]

Reserved

Reserved.

CPUID.28H.00H returns information about the bit-vector representation of QoS Enforcement resource types that

are supported in the processor. Each bit, starting from bit 1, corresponds to a specific resource type if the bit is set.

The bit position corresponds to the sub-leaf index (or ResID) that software must use to query QoS enforcement

capability available for that type.

CPUID.28H.01H -- Asymmetric L3 Cache Allocation Technology

CPUID.28H.ResID=1 returns information about Asymmetric L3 Cache Allocation Technology.

Table 21-84. Leaf 28H.01H Intel® Resource Director Technology (Intel® RDT) Asymmetric Allocation

Field Name

Description

Domain

Vol. 1

21-83

PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION

EAX[4:0]

CAT_L3_BITMASK_LENGTH

Length of the capacity bit mask for the

Logical

corresponding ResID. Add one to the return

Processor

value to get the result.

EAX[31:5]

Reserved

Reserved.

EBX[31:0]

CAT_L3_CONTENTION

Bit-granular map of isolation/contention of

Logical

allocation units.

Processor

ECX[0]

Reserved

Reserved.

ECX[1]

CAT_L3_NONCPU

N/A

Logical

Processor

ECX[2]

CAT_L3_CDP

If 1, supports L3 Code and Data Prioritization

Logical

Technology.

Processor

ECX[3]

CAT_L3_NONCONTIG

If 1, supports non-contiguous capacity

Logical

bitmasks. The bits that are set in the various

Processor

IA32_L3_MASK_n registers do not have to be

contiguous.

ECX[31:4]

Reserved

Reserved.

EDX[15:0]

CAT_L3_MAX_CLOS

Highest Class of Service (COS) number

Logical

supported for this ResID.

Processor

EDX[31:16]

Reserved

Reserved.

CPUID.28H.02H -- Asymmetric L2 Cache Allocation Technology

CPUID.28H.ResID=2 returns information about Asymmetric L2 Cache Allocation Technology.

Table 21-85. Leaf 28H.02H Intel® Resource Director Technology (Intel® RDT) Asymmetric Allocation

Field Name

Description

Domain

EAX[4:0]

CAT_L2_BITMASK_LENGTH

Length of the capacity bit mask for the

Logical

corresponding ResID. Add one to the return

Processor

value to get the result.

EAX[31:5]

Reserved

Reserved.

EBX[31:0]

CAT_L2_MAP

Bit-granular map of isolation/contention of

Logical

allocation units.

Processor

ECX[1:0]

Reserved

Reserved.

ECX[2]

CAT_L2_CDP

If 1, supports L2 Code and Data Prioritization

Logical

Technology.

Processor

ECX[3]

CAT_L2_NONCONTIG

If 1, supports non-contiguous capacity

Logical

bitmasks. The bits that are set in the various

Processor

IA32_L2_MASK_n registers do not have to be

contiguous.

ECX[31:4]

Reserved

Reserved.

EDX[15:0]

CAT_L2_MAX_CLOS

Highest Class of Service (COS) number

Logical

supported for this ResID.

Processor

EDX[31:16]

Reserved

Reserved.

CPUID.28H.03H -- Asymmetric Memory Bandwidth Allocation

CPUID.28H.ResID=3 returns information about Asymmetric Memory Bandwidth Allocation.

21-84

Vol. 1

PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION

Table 21-86. Leaf 28H.03H Intel® Resource Director Technology (Intel® RDT) Asymmetric Allocation

Field Name

Description

Domain

EAX[11:0]

MBA_MAX

Reports the maximum MBA throttling value

Logical

supported for the corresponding ResID. Add

Processor

one to the return value to get the result.

EAX[31:12]

Reserved

Reserved.

EBX[31:0]

Reserved

Reserved.

ECX[0]

PER_THREAD_MBA

Per-thread MBA controls are supported.

Logical

Processor

ECX[1]

Reserved

Reserved.

ECX[2]

MBA_LINEAR

If 1, the response of the delay values is linear.

Logical

Processor

ECX[31:3]

Reserved

Reserved.

EDX[15:0]

MBA_MAX_CLOS

Highest Class of Service (COS) number

Logical

supported for this ResID.

Processor

EDX[31:16]

Reserved

Reserved.

CPUID.28H.05H -- Asymmetric Cache Bandwidth Allocation

Table 21-87. Leaf 28H.05H Intel® Resource Director Technology (Intel® RDT) Asymmetric Allocation

Field Name

Description

Domain

EAX[7:0]

CBA_MAX_LEVELS

Reports the maximum core throttling level

Logical

supported for the corresponding ResID. Add one

Processor

to the return value to get the number of

throttling levels supported.

EAX[11:8]

BW_SCOPE

If 1, indicates the logical processor scope of the

Logical

IA32_QoS_Core_BW_Thrtl_n MSRs. Other

Processor

values are reserved.

EAX[31:12]

Reserved

Reserved.

EBX[31:0]

Reserved

Reserved.

ECX[2:0]

Reserved

Reserved.

ECX[3]

CBA_LINEAR

If 1, the response of the bandwidth control is

Logical

approximately linear. If 0, the response of the

Processor

bandwidth control is non-linear.

ECX[31:4]

Reserved

Reserved.

EDX[15:0]

CBA_MAX_CLOS

Highest Class of Service (COS) number

Logical

supported for this ResID.

Processor

EDX[31:16]

Reserved

Reserved.

CPUID.28H.06H -- Resource Priority Control

Table 21-88. Leaf 28H.06H Intel® Resource Director Technology (Intel® RDT) Asymmetric Allocation

Field Name

Description

Domain

EAX[0]

THREAD_ENABLE

If 1, supports per-thread enable of RP through

Platform

the IA32_RESOURCE_PRIORITY MSR.

Vol. 1

21-85

PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION

CPUID.80000001H -- Extended Processor Signature and Feature Bits

CPUID.80000001H returns information about extended processor signature and features bits.

• This leaf is valid if MAX_EXTENDED_LEAF ≥ 80000001H.

• This leaf does not contain sub-leaves and provides the same information regardless of the value of ECX.

Table 21-90. Leaf 80000001H Extended Processor Signature and Feature Bits

Field Name

Description

Domain

EAX[31:0]

Reserved

Reserved.

EBX[31:0]

Reserved

Reserved.

ECX[0]

LAHF_SAHF_64

If 1, supports the LAHF/SAHF instructions in

Platform

64-bit mode.

LAHF and SAHF are always available in other

modes, regardless of the enumeration of this

feature flag.

ECX[4:1]

Reserved

Reserved.

ECX[5]

LZCNT

If 1, supports the LZCNT instruction.

Platform

ECX[7:6]

Reserved

Reserved.

ECX[8]

PREFETCHW

If 1, supports the PREFETCHW instruction.

Platform

ECX[31:9]

Reserved

Reserved.

EDX[10:0]

Reserved

Reserved.

EDX[11]

SYSCALL_SYSRET_64

If 1, supports SYSCALL/SYSRET.

Platform

Intel processors support SYSCALL and SYSRET

only in 64-bit mode. This feature flag is always

enumerated as 0 outside 64-bit mode.

EDX[19:12]

Reserved

Reserved.

EDX[20]

EXECUTE_DIS

If 1, supports Execute Disable Bit.

Platform

EDX[25:21]

Reserved

Reserved.

EDX[26]

PAGE_1GB

If 1, supports 1-GByte pages.

Platform

EDX[27]

RDTSCP

If 1, supports RDTSCP and IA32_TSC_AUX.

Platform

EDX[28]

Reserved

Reserved.

EDX[29]

INTEL64

If 1, supports Intel® 64 Architecture.

Platform

EDX[31:30]

Reserved

Reserved.

21-88

Vol. 1

PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION

CPUID.80000006H -- Extended Function CPUID Information

CPUID.80000006H returns Extended Function CPUID information. The preferred method to enumerate caching

information description is to use CPUID.04H-Deterministic Cache Parameters.

• This leaf is valid if MAX_EXTENDED_LEAF ≥ 80000006H.

• This leaf does not contain sub-leaves and provides the same information regardless of the value of ECX

Table 21-95. Leaf 80000006H Extended Function CPUID Information

Field Name

Description

Domain

EAX[31:0]

Reserved

Reserved.

EBX[31:0]

Reserved

Reserved.

ECX[7:0]

L2_LINE_SIZE

Cache line size in bytes.

Logical

Processor

ECX[11:8]

Reserved

Reserved.

ECX[15:12]

L2_ASSOC

L2 associativity field. The L2 associativity field

Logical

encodings are listed in the table below.

Processor

ECX[31:16]

L2_SIZE

Cache size in 1K units.

Logical

Processor

EDX[7:0]

Reserved

Reserved.

EDX[31:8]

Reserved

Reserved.

Table 21-96. L2 Associativity Field Encodings

Encoding Value

Description

Encoding Value

Description

00H

Disabled

08H

16 Ways

01H

1 Way (direct mapped)

09H

Reserved

02H

2 Ways

0AH

32 Ways

03H

Reserved

0BH

48 Ways

04H

4 Ways

0CH

64 Ways

05H

Reserved

0DH

96 Ways

06H

8 Ways

0EH

128 Ways

07H

See CPUID leaf 4 sub-leaf 2¹

0FH

Fully Associative

Vol. 1

21-93

PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION

CPUID.80000008H -- Extended Function CPUID Information 2

CPUID.80000008H returns Extended Function CPUID information.

• This leaf is valid if MAX_EXTENDED_LEAF ≥ 80000008H.

• This leaf does not contain sub-leaves and provides the same information regardless of the value of ECX.

Table 21-98. Leaf 80000008H Extended Function CPUID Information 2

Field Name

Description

Domain

EAX[7:0]

PHYS_ADDR_SIZE

Number of physical-address bits. If TME-MK is

Platform

enabled, the number of bits that can be used to

address memory may be reduced by

IA32_TME_ACTIVATE[35:32].

EAX[15:8]

LIN_ADDR_SIZE

Number of linear-address bits.

Platform

EAX[23:16]

GUEST_PHYS_ADDR_SIZE

Number of guest-physical-address bits (for

Platform

software operating in a virtual machine). If this

field is zero, PHYS_ADDR_SIZE should be used.

Intel processors return zero for this field.

Software emulating CPUID may return a

different value.

EAX[31:24]

Reserved

Reserved.

EBX[8:0]

Reserved

Reserved.

EBX[9]

WBNOINVD

If 1, supports the WBNOINVD instruction.

Platform

EBX[31:10]

Reserved

Reserved.

ECX[31:0]

Reserved

Reserved.

EDX[31:0]

Reserved

Reserved.

Vol. 1

21-95

APPENDIX B

EFLAGS CONDITION CODES

B.1

CONDITION CODES

Table B-1 lists condition codes that can be queried using CMOVcc, FCMOVcc, Jcc, and SETcc. Condition codes refer

to the setting of one or more status flags (CF, OF, SF, ZF, and PF) in the EFLAGS register. In the table below:

• The “Mnemonic” column provides the suffix (cc) added to the instruction to specify a test condition.

• “Condition Tested For” describes the targeted condition.

• “Instruction Subcode” provides the opcode suffix added to the main opcode to specify the test condition.

• “Status Flags Setting” describes the flag setting.

Table B-1. EFLAGS Condition Codes

Instruction

Mnemonic (cc)

Condition Tested For

Subcode

Status Flags Setting

Overflow

0000

OF = 1

No overflow

0001

OF = 0

Below

0010

CF = 1

Carry

NAE

Neither above nor equal

Not below

0011

CF = 0

Not carry

Above or equal

Equal

0100

ZF = 1

Zero

Not equal

0101

ZF = 0

Not zero

Below or equal

0110

(CF OR ZF) = 1

Not above

NBE

Neither below nor equal

0111

(CF OR ZF) = 0

Above

Sign

1000

SF = 1

No sign

1001

SF = 0

Parity

1010

PF = 1

Parity even

No parity

1011

PF = 0

Parity odd

Less

1100

(SF XOR OF) = 1

NGE

Neither greater nor equal

Not less

1101

(SF XOR OF) = 0

Greater or equal

Less or equal

1110

((SF XOR OF) OR ZF) = 1

Not greater

NLE

Neither less nor equal

1111

((SF XOR OF) OR ZF) = 0

Greater

Vol. 1

B-1

APPENDIX C

FLOATING-POINT EXCEPTIONS SUMMARY

C.1

OVERVIEW

This appendix shows which of the floating-point exceptions can be generated for:

• x87 FPU instructions - see Table C-2.

• Intel SSE instructions - see Table C-3.

• Intel SSE2 instructions - see Table C-4.

• Intel SSE3 instructions - see Table C-5.

• Intel SSE4 instructions - see Table C-6.

Table C-1 lists types of floating-point exceptions that potentially can be generated by the x87 FPU and by Intel SSE,

SSE2, and SSE3 instructions.

Table C-1. x87 FPU and SIMD Floating-Point Exceptions

Floating-

point

Exception

Description

#IS

Invalid-operation exception for stack underflow or stack overflow (can only be generated for x87 FPU instructions)*

#IA or #I

Invalid-operation exception for invalid arithmetic operands and unsupported formats*

Denormal-operand exception

Divide-by-zero exception

Numeric-overflow exception

Numeric-underflow exception

Inexact-result (precision) exception

NOTE:

* The x87 FPU instruction set generates two types of invalid-operation exceptions: #IS (stack underflow or stack overflow) and #IA

(invalid arithmetic operation due to invalid arithmetic operands or unsupported formats). Intel SSE, SSE2, and SSE3 instructions

potentially generate #I (invalid operation exceptions due to invalid arithmetic operands or unsupported formats).

The floating-point exceptions shown in Table C-1 (except for #D and #IS) are defined in IEEE Standard 754-1985

for Binary Floating-Point Arithmetic. See Section 4.9.1, “Floating-Point Exception Conditions,” for a detailed discus-

sion of floating-point exceptions.

C.2

X87 FPU INSTRUCTIONS

Table C-2 lists the x87 FPU instructions in alphabetical order. For each instruction, it summarizes the floating-point

exceptions that the instruction can generate.

Table C-2. Exceptions Generated with x87 FPU Floating-Point Instructions

Mnemonic

Instruction

#IS

#IA

F2XM1

Exponential

FABS

Absolute value

FADD(P)

Add floating-point

FBLD

BCD load

Vol. 1

C-1

FLOATING-POINT EXCEPTIONS SUMMARY

Table C-2. Exceptions Generated with x87 FPU Floating-Point Instructions (Contd.)

Mnemonic

Instruction

#IS

#IA

FBSTP

BCD store and pop

FCHS

Change sign

FCLEX

Clear exceptions

FCMOVcc

Floating-point conditional move

FCOM, FCOMP, FCOMPP

Compare floating-point

FCOMI, FCOMIP, FUCOMI,

Compare floating-point and set EFLAGS

FUCOMIP

FCOS

Cosine

FDECSTP

Decrement stack pointer

FDIV(R)(P)

Divide floating-point

FFREE

Free register

FIADD

Integer add

FICOM(P)

Integer compare

FIDIV

Integer divide

FIDIVR

Integer divide reversed

FILD

Integer load

FIMUL

Integer multiply

FINCSTP

Increment stack pointer

FINIT

Initialize processor

FIST(P)

Integer store

FISTTP

Truncate to integer

(SSE3 instruction)

FISUB(R)

Integer subtract

FLD extended or stack

Load floating-point

FLD single or double

Load floating-point

FLD1

Load + 1.0

FLDCW

Load Control word

FLDENV

Load environment

FLDL2E

Load log₂e

FLDL2T

Load log₂10

FLDLG2

Load log₁₀2

FLDLN2

Load log_e2

FLDPI

Load π

FLDZ

Load + 0.0

FMUL(P)

Multiply floating-point

FNOP

No operation

FPATAN

Partial arctangent

FPREM

Partial remainder

FPREM1

IEEE partial remainder

C-2

Vol. 1

FLOATING-POINT EXCEPTIONS SUMMARY

Table C-2. Exceptions Generated with x87 FPU Floating-Point Instructions (Contd.)

Mnemonic

Instruction

#IS

#IA

FPTAN

Partial tangent

FRNDINT

Round to integer

FRSTOR

Restore state

FSAVE

Save state

FSCALE

Scale

FSIN

Sine

FSINCOS

Sine and cosine

FSQRT

Square root

FST(P) stack or extended

Store floating-point

FST(P) single or double

Store floating-point

FSTCW

Store control word

FSTENV

Store environment

FSTSW (AX)

Store status word

FSUB(R)(P)

Subtract floating-point

FTST

Test

FUCOM(P)(P)

Unordered compare floating-point

FWAIT

CPU Wait

FXAM

Examine

FXCH

Exchange registers

FXTRACT

Extract

FYL2X

Logarithm

FYL2XP1

Logarithm epsilon

C.3

INTEL® SSE INSTRUCTIONS

Table C-3 lists the Intel SSE instructions with at least one of the following characteristics:

• Has floating-point operands.

• Generates floating-point results.

• Reads or writes floating-point status and control information.

The table also summarizes the floating-point exceptions that each instruction can generate.

Table C-3. Exceptions Generated with Intel® SSE Instructions

Mnemonic

Instruction

ADDPS

Packed add.

ADDSS

Scalar add.

ANDNPS

Packed logical INVERT and AND.

ANDPS

Packed logical AND.

CMPPS

Packed compare.

CMPSS

Scalar compare.

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C-3

FLOATING-POINT EXCEPTIONS SUMMARY

Table C-3. Exceptions Generated with Intel® SSE Instructions (Contd.)

Mnemonic

Instruction

COMISS

Scalar ordered compare lower SP FP numbers and set the status

flags.

CVTPI2PS

Convert two 32-bit signed integers from MM2/Mem to two SP FP.

CVTPS2PI

Convert lower two SP FP from XMM/Mem to two 32-bit signed

integers in MM using rounding specified by MXCSR.

CVTSI2SS

Convert one 32-bit or 64-bit signed integer from Integer

Reg/Mem to one SP FP.

CVTSS2SI

Convert one SP FP from XMM/Mem to one 32-bit or 64-bit signed

integer using rounding mode specified by MXCSR, and move the

result to an integer register.

CVTTPS2PI

Convert two SP FP from XMM2/Mem to two 32-bit signed

integers in MM1 using truncate.

CVTTSS2SI

Convert lowest SP FP from XMM/Mem to one 32-bit signed

integer using truncate, and move the result to an integer register.

DIVPS

Packed divide.

DIVSS

Scalar divide.

LDMXCSR

Load control/status word.

MAXPS

Packed maximum.

MAXSS

Scalar maximum.

MINPS

Packed minimum.

MINSS

Scalar minimum.

MOVAPS

Move four packed SP values.

MOVHLPS

Move packed SP high to low.

MOVHPS

Move two packed SP values between memory and the high half of

an XMM register.

MOVLHPS

Move packed SP low to high.

MOVLPS

Move two packed SP values between memory and the low half of

an XMM register.

MOVMSKPS

Move sign mask to r32.

MOVSS

Move scalar SP number between an XMM register and memory or

a second XMM register.

MOVUPS

Move unaligned packed data.

MULPS

Packed multiply.

MULSS

Scalar multiply.

ORPS

Packed OR.

RCPPS

Packed reciprocal.

RCPSS

Scalar reciprocal.

RSQRTPS

Packed reciprocal square root.

RSQRTSS

Scalar reciprocal square root.

SHUFPS

Shuffle.

SQRTPS

Square Root of the packed SP FP numbers.

SQRTSS

Scalar square root.

C-4

Vol. 1

FLOATING-POINT EXCEPTIONS SUMMARY

Table C-3. Exceptions Generated with Intel® SSE Instructions (Contd.)

Mnemonic

Instruction

STMXCSR

Store control/status word.

SUBPS

Packed subtract.

SUBSS

Scalar subtract.

UCOMISS

Unordered compare lower SP FP numbers and set the status flags.

UNPCKHPS

Interleave SP FP numbers.

UNPCKLPS

Interleave SP FP numbers.

XORPS

Packed XOR.

C.4

INTEL® SSE2 INSTRUCTIONS

Table C-4 lists the Intel SSE2 instructions with at least one of the following characteristics:

• Floating-point operands.

• Floating-point results.

For each instruction, the table summarizes the floating-point exceptions that the instruction can generate.

Table C-4. Exceptions Generated with Intel® SSE2 Instructions

Instruction

Description

ADDPD

Add two packed DP FP numbers from XMM2/Mem to XMM1.

ADDSD

Add the lower DP FP number from XMM2/Mem to XMM1.

ANDNPD

Invert the 128 bits in XMM1 and then AND the result with 128

bits from XMM2/Mem.

ANDPD

Logical And of 128 bits from XMM2/Mem to XMM1 register.

CMPPD

Compare packed DP FP numbers from XMM2/Mem to packed DP

FP numbers in XMM1 register using imm8 as predicate.

CMPSD

Compare lowest DP FP number from XMM2/Mem to lowest DP FP

number in XMM1 register using imm8 as predicate.

COMISD

Compare lower DP FP number in XMM1 register with lower DP FP

number in XMM2/Mem and set the status flags accordingly

CVTDQ2PS

Convert four 32-bit signed integers from XMM/Mem to four SP FP.

CVTPS2DQ

Convert four SP FP from XMM/Mem to four 32-bit signed integers

in XMM using rounding specified by MXCSR.

CVTTPS2DQ

Convert four SP FP from XMM/Mem to four 32-bit signed integers

in XMM using truncate.

CVTDQ2PD

Convert two 32-bit signed integers in XMM2/Mem to 2 DP FP in

xmm1 using rounding specified by MXCSR.

CVTPD2DQ

Convert two DP FP from XMM2/Mem to two 32-bit signed

integers in xmm1 using rounding specified by MXCSR.

CVTPD2PI

Convert lower two DP FP from XMM/Mem to two 32-bit signed

integers in MM using rounding specified by MXCSR.

CVTPD2PS

Convert two DP FP to two SP FP.

CVTPI2PD

Convert two 32-bit signed integers from MM2/Mem to two DP FP.

CVTPS2PD

Convert two SP FP to two DP FP.

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FLOATING-POINT EXCEPTIONS SUMMARY

Table C-4. Exceptions Generated with Intel® SSE2 Instructions (Contd.)

Instruction

Description

CVTSD2SI

Convert one DP FP from XMM/Mem to one 32-bit or 64-bit signed

integer using rounding mode specified by MXCSR, and move the

result to an integer register.

CVTSD2SS

Convert scalar DP FP to scalar SP FP.

CVTSI2SD

Convert one 32-bit or 64-bit signed integer from Integer

Reg/Mem to one DP FP.

CVTSS2SD

Convert scalar SP FP to scalar DP FP.

CVTTPD2DQ

Convert two DP FP from XMM2/Mem to two 32-bit signed

integers in XMM1 using truncate.

CVTTPD2PI

Convert two DP FP from XMM2/Mem to two 32-bit signed

integers in MM1 using truncate.

CVTTSD2SI

Convert lowest DP FP from XMM/Mem to one 32 bit signed

integer using truncate, and move the result to an integer register.

DIVPD

Divide packed DP FP numbers in XMM1 by XMM2/Mem

DIVSD

Divide lower DP FP numbers in XMM1 by XMM2/Mem

MAXPD

Return the maximum DP FP numbers between XMM2/Mem and

XMM1.

MAXSD

Return the maximum DP FP number between the lower DP FP

numbers from XMM2/Mem and XMM1.

MINPD

Return the minimum DP numbers between XMM2/Mem and

XMM1.

MINSD

Return the minimum DP FP number between the lowest DP FP

numbers from XMM2/Mem and XMM1.

MOVAPD

Move 128 bits representing 2 packed DP data from XMM2/Mem to

XMM1 register.

Or Move 128 bits representing 2 packed DP from XMM1 register

to XMM2/Mem.

MOVHPD

Move 64 bits representing one DP operand from Mem to upper

field of XMM register.

Or move 64 bits representing one DP operand from upper field of

XMM register to Mem.

MOVLPD

Move 64 bits representing one DP operand from Mem to lower

field of XMM register.

Or move 64 bits representing one DP operand from lower field of

XMM register to Mem.

MOVMSKPD

Move the sign mask to r32.

MOVSD

Move 64 bits representing one scalar DP operand from

XMM2/Mem to XMM1 register.

Or move 64 bits representing one scalar DP operand from XMM1

MOVUPD

Move 128 bits representing 2 DP data from XMM2/Mem to XMM1

Or move 128 bits representing 2 DP data from XMM1 register to

XMM2/Mem.

MULPD

Multiply packed DP FP numbers in XMM2/Mem to XMM1.

C-6

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FLOATING-POINT EXCEPTIONS SUMMARY

Table C-4. Exceptions Generated with Intel® SSE2 Instructions (Contd.)

Instruction

Description

MULSD

Multiply the lowest DP FP number in XMM2/Mem to XMM1.

ORPD

OR 128 bits from XMM2/Mem to XMM1 register.

SHUFPD

Shuffle Double.

SQRTPD

Square Root Packed Double Precision

SQRTSD

Square Root Scaler Double Precision

SUBPD

Subtract Packed Double Precision.

SUBSD

Subtract Scaler Double Precision.

UCOMISD

Compare lower DP FP number in XMM1 register with lower DP FP

number in XMM2/Mem and set the status flags accordingly.

UNPCKHPD

Interleaves DP FP numbers from the high halves of XMM1 and

XMM2/Mem into XMM1 register.

UNPCKLPD

Interleaves DP FP numbers from the low halves of XMM1 and

XMM2/Mem into XMM1 register.

XORPD

XOR 128 bits from XMM2/Mem to XMM1 register.

C.5

INTEL® SSE3 INSTRUCTIONS

Table C-5 lists the Intel SSE3 instructions that have at least one of the following characteristics:

• Has floating-point operands.

• Generates floating-point results.

For each instruction, the table summarizes the floating-point exceptions that the instruction can generate.

Table C-5. Exceptions Generated with Intel® SSE3 Instructions

Instruction

Description

ADDSUBPD

Add /Sub packed DP FP numbers from XMM2/Mem to XMM1.

ADDSUBPS

Add /Sub packed SP FP numbers from XMM2/Mem to XMM1.

FISTTP

See Table C-2.

HADDPD

Add horizontally packed DP FP numbers XMM2/Mem to XMM1.

HADDPS

Add horizontally packed SP FP numbers XMM2/Mem to XMM1

HSUBPD

Sub horizontally packed DP FP numbers XMM2/Mem to XMM1

HSUBPS

Sub horizontally packed SP FP numbers XMM2/Mem to XMM1

Other Intel SSE3 instructions do not generate floating-point exceptions.

C.6

SSSE3 INSTRUCTIONS

SSSE3 instructions operate on integer data elements. They do not generate floating-point exceptions.

C.7

INTEL® SSE4 INSTRUCTIONS

Table C-6 lists the Intel SSE4.1 instructions that generate floating-point results.

For each instruction, the table summarizes the floating-point exceptions that the instruction can generate.

Vol. 1

C-7

APPENDIX D

GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION

HANDLERS

See Section 11.5, “Intel® SSE, SSE2, and SSE3 Exceptions,” for a detailed discussion of SIMD floating-point excep-

tions.

This appendix considers only Intel SSE, SSE2, and SSE3 instructions that can generate numeric (SIMD floating-

point) exceptions, and gives an overview of the necessary support for handling such exceptions. This appendix

does not address instructions that do not generate floating-point exceptions (such as RSQRTSS, RSQRTPS, RCPSS,

or RCPPS), any x87 instructions, or any unlisted instruction.

For detailed information on which instructions generate numeric exceptions, and a listing of those exceptions, refer

to Appendix C, “Floating-Point Exceptions Summary.” Non-numeric exceptions are handled in a way similar to that

for the standard IA-32 instructions.

D.1

TWO OPTIONS FOR HANDLING FLOATING-POINT EXCEPTIONS

Just as for x87 FPU floating-point exceptions, the processor takes one of two possible courses of action when an

SSE/SSE2/SSE3 instruction raises a floating-point exception:

• If the exception being raised is masked (by setting the corresponding mask bit in the MXCSR to 1), then a

default result is produced which is acceptable in most situations. No external indication of the exception is

given, but the corresponding exception flags in the MXCSR are set and may be examined later. Note though

that for packed operations, an exception flag that is set in the MXCSR will not tell which of the sub-operands

caused the event to occur.

• If the exception being raised is not masked (by setting the corresponding mask bit in the MXCSR to 0), a

software exception handler previously registered by the user with operating system support will be invoked

through the SIMD floating-point exception (#XM, exception 19). This case is discussed below in Section D.2,

“Software Exception Handling.”

D.2

SOFTWARE EXCEPTION HANDLING

The #XM handler is usually part of the system software (the operating system kernel). Note that an interrupt

descriptor table (IDT) entry must have been previously set up for exception 19 (refer to Chapter 7, “Interrupt and

Exception Handling,” in the Intel^®64 and IA-32 Architectures Software Developer’s Manual, Volume 3A). Some

compilers use specific run-time libraries to assist in floating-point exception handling. If any x87 FPU floating-point

operations are going to be performed that might raise floating-point exceptions, then the exception handling

routine must either disable all floating-point exceptions (for example, loading a local control word with FLDCW), or

it must be implemented as re-entrant. If this is not the case, the routine has to clear the status flags for x87 FPU

exceptions or to mask all x87 FPU floating-point exceptions. For SIMD floating-point exceptions though, the excep-

tion flags in MXCSR do not have to be cleared, even if they remain unmasked (but they may still be cleared). Excep-

tions are in this case precise and occur immediately, and a SIMD floating-point exception status flag that is set

when the corresponding exception is unmasked will not generate an exception.

Typical actions performed by this low-level exception handling routine are:

• Incrementing an exception counter for later display or printing.

• Printing or displaying diagnostic information (e.g., the MXCSR and XMM registers).

• Aborting further execution, or using the exception pointers to build an instruction that will run without

exception and executing it.

• Storing information about the exception in a data structure that will be passed to a higher level user exception

handler.

Vol. 1

D-1

GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS

In most cases (and this applies also to the Intel SSE, SSE2, and SSE3 instructions), there will be three main

components of a low-level floating-point exception handler: a prologue, a body, and an epilogue.

The prologue performs functions that must be protected from possible interruption by higher-priority sources -

typically saving registers and transferring diagnostic information from the processor to memory. When the critical

processing has been completed, the prologue may re-enable interrupts to allow higher-priority interrupt handlers

to preempt the exception handler (assuming that the interrupt handler was called through an interrupt gate,

meaning that the processor cleared the interrupt enable (IF) flag in the EFLAGS register - refer to Section 6.5.1,

“Call and Return Operation for Interrupt or Exception Handling Procedures”).

The body of the exception handler examines the diagnostic information and makes a response that is application-

dependent. It may range from halting execution, to displaying a message, to attempting to fix the problem and

then proceeding with normal execution, to setting up a data structure, calling a higher-level user exception handler

and continuing execution upon return from it. This latter case will be assumed in Section D.4, “SIMD Floating-Point

Exceptions and the IEEE Standard 754,” below.

Finally, the epilogue essentially reverses the actions of the prologue, restoring the processor state so that normal

execution can be resumed.

The following example represents a typical exception handler. To link it with Example D-2 that will follow in Section

D.4.3, “Example SIMD Floating-Point Emulation Implementation,” assume that the body of the handler (not shown

here in detail) passes the saved state to a routine that will examine in turn all the sub-operands of the excepting

instruction, invoking a user floating-point exception handler if a particular set of sub-operands raises an unmasked

(enabled) exception, or emulating the instruction otherwise.

Example D-1. SIMD Floating-Point Exception Handler

SIMD_FP_EXC_HANDLER PROC

;PROLOGUE

;SAVE REGISTERS THAT MIGHT BE USED BY THE EXCEPTION HANDLER

PUSH EBP

;SAVE EBP

PUSH EAX

;SAVE EAX

MOV EBP, ESP

;SAVE ESP in EBP

SUB ESP, 512

;ALLOCATE 512 BYTES

AND ESP, 0fffffff0h

;MAKE THE ADDRESS 16-BYTE ALIGNED

FXSAVE [ESP]

;SAVE FP, MMX, AND SIMD FP STATE

PUSH [EBP+EFLAGS_OFFSET]

;COPY OLD EFLAGS TO STACK TOP

POPFD

;RESTORE THE INTERRUPT ENABLE FLAG IF

;TO VALUE BEFORE SIMD FP EXCEPTION

;BODY

;APPLICATION-DEPENDENT EXCEPTION HANDLING CODE GOES HERE

LDMXCSR LOCAL_MXCSR

;LOAD LOCAL MXCSR VALUE IF NEEDED

;EPILOGUE

FXRSTOR [ESP]

;RESTORE MODIFIED STATE IMAGE

MOV ESP, EBP

;DE-ALLOCATE STACK SPACE

POP EAX

;RESTORE EAX

POP EBP

;RESTORE EBP

IRET

;RETURN TO INTERRUPTED CALCULATION

SIMD_FP_EXC_HANDLER ENDP

D-2

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GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS

D.3

EXCEPTION SYNCHRONIZATION

An SSE/SSE2/SSE3 instruction can execute in parallel with other similar instructions, with integer instructions, and

with floating-point or MMX instructions. Unlike for x87 instructions, special precaution for exception synchroniza-

tion is not necessary in this case. This is because floating-point exceptions for SSE/SSE2/SSE3 instructions occur

immediately and are not delayed until a subsequent floating-point instruction is executed. However, floating-

point emulation may be necessary when unmasked floating-point exceptions are generated.

D.4

SIMD FLOATING-POINT EXCEPTIONS AND THE IEEE STANDARD 754

SSE/SSE2/SSE3 extensions are 100% compatible with the IEEE Standard 754 for Floating-Point Arithmetic, satis-

fying all of its mandatory requirements (when the flush-to-zero or denormals-are-zeros modes are not enabled).

But a programming environment that includes SSE/SSE2/SSE3 instructions will comply with both the obligatory

and the strongly recommended requirements of the IEEE Standard 754 regarding floating-point exception

handling, only as a combination of hardware and software (which is acceptable). The standard states that a user

should be able to request a trap on any of the five floating-point exceptions (note that the denormal exception is

an IA-32 addition), and it also specifies the values (operands or result) to be delivered to the exception handler.

The main issue is that for SSE/SSE2/SSE3 instructions that raise post-computation exceptions (traps: overflow,

underflow, or inexact), unlike for x87 FPU instructions, the processor does not provide the result recommended by

IEEE Standard 754 to the user handler. If a user program needs the result of an instruction that generated a post-

computation exception, it is the responsibility of the software to produce this result by emulating the faulting

SSE/SSE2/SSE3 instruction. Another issue is that the standard does not specify explicitly how to handle multiple

floating-point exceptions that occur simultaneously. For packed operations, a logical OR of the flags that would be

set by each sub-operation is used to set the exception flags in the MXCSR. The following subsections present one

possible way to solve these problems.

D.4.1

Floating-Point Emulation

Every operating system must provide a kernel level floating-point exception handler (a template was presented in

Section D.2, “Software Exception Handling,” above). In the following discussion, assume that a user mode floating-

point exception filter is supplied for SIMD floating-point exceptions (for example as part of a library of C functions),

that a user program can invoke in order to handle unmasked exceptions. The user mode floating-point exception

filter (not shown here) has to be able to emulate the subset of Intel SSE, SSE2, and SSE3 instructions that can

generate numeric exceptions, and has to be able to invoke a user provided floating-point exception handler for

floating-point exceptions. When a floating-point exception that is not masked is raised by an Intel SSE, SSE2, and

SSE3 instruction, the low-level floating-point exception handler will be called. This low-level handler may in turn

call the user mode floating-point exception filter. The filter function receives the original operands of the excepting

instruction as no results are provided by the hardware, whether a pre-computation or a post-computation excep-

tion has occurred. The filter will unpack the operands into up to four sets of sub-operands, and will submit them

one set at a time to an emulation function (See Example D-2 in Section D.4.3, “Example SIMD Floating-Point

Emulation Implementation.”) The emulation function will examine the sub-operands, and will possibly redo the

necessary calculation.

Two cases are possible:

• If an unmasked (enabled) exception would occur in this process, the emulation function will return to its caller

(the filter function) with the appropriate information. The filter will invoke a (previously registered) user

floating-point exception handler for this set of sub-operands, and will record the result upon return from the

user handler (provided the user handler allows continuation of the execution).

• If no unmasked (enabled) exception would occur, the emulation function will determine and will return to its

caller the result of the operation for the current set of sub-operands (it has to be IEEE Standard 754

compliant). The filter function will record the result (plus any new flag settings).

The user level filter function will then call the emulation function for the next set of sub-operands (if any). When

done with all the operand sets, the partial results will be packed (if the excepting instruction has a packed floating-

point result, which is true for most SSE/SSE2/SSE3 numeric instructions) and the filter will return to the low-level

exception handler, which in turn will return from the interruption, allowing execution to continue. Note that the

Vol. 1

D-3

GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS

instruction pointer (EIP) has to be altered to point to the instruction following the excepting instruction, in order to

continue execution correctly.

If a user mode floating-point exception filter is not provided, then all the work for decoding the excepting instruc-

tion, reading its operands, emulating the instruction for the components of the result that do not correspond to

unmasked floating-point exceptions, and providing the compounded result will have to be performed by the user-

provided floating-point exception handler.

Actual emulation might have to take place for one operand or pair of operands for scalar operations, and for all sub-

operands or pairs of sub-operands for packed operations. The steps to perform are the following:

• The excepting instruction has to be decoded and the operands have to be read from the saved context.

• The instruction has to be emulated for each (pair of) sub-operand(s); if no floating-point exception occurs, the

partial result has to be saved; if a masked floating-point exception occurs, the masked result has to be

produced through emulation and saved, and the appropriate status flags have to be set; if an unmasked

floating-point exception occurs, the result has to be generated by the user provided floating-point exception

handler, and the appropriate status flags have to be set.

• The partial results have to be combined and written to the context that will be restored upon application

program resumption.

A diagram of the control flow in handling an unmasked floating-point exception is presented below.

User Application

Low-Level Floating-Point Exception Handler

User Level Floating-Point Exception Filter

User Floating-Point Exception Handler

Figure D-1. Control Flow for Handling Unmasked Floating-Point Exceptions

From the user-level floating-point filter, Example D-2 in Section D.4.3, “Example SIMD Floating-Point Emulation

Implementation,” presents only the floating-point emulation part. In order to understand the actions involved, the

expected response to exceptions has to be known for all Intel SSE, SSE2, and SSE3 numeric instructions in two

situations: with exceptions enabled (unmasked result), and with exceptions disabled (masked result). The latter

can be found in Section 6.5, “Interrupts and Exceptions.” The response to NaN operands that do not raise an excep-

tion is specified in Section 4.8.3.4, “NaNs.” Operations on NaNs are explained in the same source. This response is

also discussed in more detail in the next subsection, along with the unmasked and masked responses to floating-

point exceptions.

D.4.2

Intel® SSE, SSE2, and SSE3 Response To Floating-Point Exceptions

This subsection specifies the unmasked response expected from the Intel SSE, SSE2, and SSE3 instructions that

raise floating-point exceptions. The masked response is given in parallel, as it is necessary in the emulation process

D-4

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Intel 64 and IA-32 Architectures. Software Developer’s Manual (2026) - page 8