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Intel 64 and IA-32 Architectures. Software Developer’s Manual (2026) - page 4

PROGRAMMING WITH THE X87 FPU

register addressing modes, using the expression ST(0), or simply ST, to represent the current stack top and ST(i)

to specify the ith register from TOP in the stack (0 ≤ i ≤ 7). For example, if TOP contains 011B (register 3 is the top

of the stack), the following instruction would add the contents of two registers in the stack (registers 3 and 5):

FADD ST, ST(2);

Figure 8-3 shows an example of how the stack structure of the x87 FPU registers and instructions are typically used

to perform a series of computations. Here, a two-dimensional dot product is computed, as follows:

1.

The first instruction (FLD value1) decrements the stack register pointer (TOP) and loads the value 5.6 from

memory into ST(0). The result of this operation is shown in snap-shot (a).

2.

The second instruction multiplies the value in ST(0) by the value 2.4 from memory and stores the result in

ST(0), shown in snap-shot (b).

3.

The third instruction decrements TOP and loads the value 3.8 in ST(0).

4.

The fourth instruction multiplies the value in ST(0) by the value 10.3 from memory and stores the result in

ST(0), shown in snap-shot (c).

5.

The fifth instruction adds the value and the value in ST(1) and stores the result in ST(0), shown in snap-shot

(d).

Computation

Dot Product = (5.6 x 2.4) + (3.8 x 10.3)

Code:

FLD value1 ;(a) value1 = 5.6

FMUL value2 ;(b) value2 = 2.4

FLD value3 ; value3 = 3.8

FMUL value4 ;(c)value4 = 10.3

FADD ST(1)

;(d)

(a)

(b)

(c)

(d)

R7

R7

R7

R7

R6

R6

R6

R6

R5

R5

R5

R5

R4

5.6

ST(0)

R4

13.44

ST(0)

R4

13.44

ST(1)

R4

13.44

ST(1)

R3

R3

R3

39.14

ST(0)

R3

52.58

ST(0)

R2

R2

R2

R2

R1

R1

R1

R1

R0

R0

R0

R0

Figure 8-3. Example x87 FPU Dot Product Computation

The style of programming demonstrated in this example is supported by the floating-point instruction set. In cases

where the stack structure causes computation bottlenecks, the FXCH (exchange x87 FPU register contents)

instruction can be used to streamline a computation.

8.1.2.1

Parameter Passing With the x87 FPU Register Stack

Like the general-purpose registers, the contents of the x87 FPU data registers are unaffected by procedure calls, or

in other words, the values are maintained across procedure boundaries. A calling procedure can thus use the x87

FPU data registers (as well as the procedure stack) for passing parameter between procedures. The called proce-

dure can reference parameters passed through the register stack using the current stack register pointer (TOP)

and the ST(0) and ST(i) nomenclature. It is also common practice for a called procedure to leave a return value or

result in register ST(0) when returning execution to the calling procedure or program.

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PROGRAMMING WITH THE X87 FPU

When mixing MMX and x87 FPU instructions in the procedures or code sequences, the programmer is responsible

for maintaining the integrity of parameters being passed in the x87 FPU data registers. If an MMX instruction is

executed before the parameters in the x87 FPU data registers have been passed to another procedure, the param-

eters may be lost (see Section 9.5, “Compatibility with x87 FPU Architecture”).

8.1.3

x87 FPU Status Register

The 16-bit x87 FPU status register (see Figure 8-4) indicates the current state of the x87 FPU. The flags in the x87

FPU status register include the FPU busy flag, top-of-stack (TOP) pointer, condition code flags, exception summary

status flag, stack fault flag, and exception flags. The x87 FPU sets the flags in this register to show the results of

operations.

FPU Busy

Top of Stack Pointer

15 14 13

11 10 9

8

7

6

5

4

3

2

1

0

C

C

C

C

E

S

P

U

O

Z

D

I

B

TOP

3

2

1

0

S

F

E

E

E

E

E

E

Condition

Code

Exception Summary Status

Stack Fault

Exception Flags

Precision

Underflow

Overflow

Zero Divide

Denormalized Operand

Invalid Operation

Figure 8-4. x87 FPU Status Word

The contents of the x87 FPU status register (referred to as the x87 FPU status word) can be stored in memory using

the FSTSW/FNSTSW, FSTENV/FNSTENV, FSAVE/FNSAVE, and FXSAVE instructions. It can also be stored in the AX

register of the integer unit, using the FSTSW/FNSTSW instructions.

8.1.3.1

Top of Stack (TOP) Pointer

A pointer to the x87 FPU data register that is currently at the top of the x87 FPU register stack is contained in bits

11 through 13 of the x87 FPU status word. This pointer, which is commonly referred to as TOP (for top-of-stack),

is a binary value from 0 to 7. See Section 8.1.2, “x87 FPU Data Registers,” for more information about the TOP

pointer.

8.1.3.2

Condition Code Flags

The four condition code flags (C0 through C3) indicate the results of floating-point comparison and arithmetic oper-

ations. Table 8-1 summarizes the manner in which the floating-point instructions set the condition code flags.

These condition code bits are used principally for conditional branching and for storage of information used in

exception handling (see Section 8.1.4, “Branching and Conditional Moves on Condition Codes”).

As shown in Table 8-1, the C1 condition code flag is used for a variety of functions. When both the IE and SF flags

in the x87 FPU status word are set, indicating a stack overflow or underflow exception (#IS), the C1 flag distin-

guishes between overflow (C1 = 1) and underflow (C1 = 0). When the PE flag in the status word is set, indicating

an inexact (rounded) result, the C1 flag is set to 1 if the last rounding by the instruction was upward. The FXAM

instruction sets C1 to the sign of the value being examined.

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PROGRAMMING WITH THE X87 FPU

The C2 condition code flag is used by the FPREM and FPREM1 instructions to indicate an incomplete reduction (or

partial remainder). When a successful reduction has been completed, the C0, C3, and C1 condition code flags are

set to the three least-significant bits of the quotient (Q2, Q1, and Q0, respectively). See “FPREM1-Partial

Remainder” in Chapter 3, “Instruction Set Reference, A-L,” of the Intel^® 64 and IA-32 Architectures Software

Developer’s Manual, Volume 2A, for more information on how these instructions use the condition code flags.

The FPTAN, FSIN, FCOS, and FSINCOS instructions set the C2 flag to 1 to indicate that the source operand is

beyond the allowable range of ±2⁶³ and clear the C2 flag if the source operand is within the allowable range.

Where the state of the condition code flags are listed as undefined in Table 8-1, do not rely on any specific value in

these flags.

8.1.3.3

x87 FPU Floating-Point Exception Flags

The six x87 FPU floating-point exception flags (bits 0 through 5) of the x87 FPU status word indicate that one or

more floating-point exceptions have been detected since the bits were last cleared. The individual exception flags

(IE, DE, ZE, OE, UE, and PE) are described in detail in Section 8.4, “x87 FPU Floating-Point Exception Handling.”

Each of the exception flags can be masked by an exception mask bit in the x87 FPU control word (see Section 8.1.5,

“x87 FPU Control Word”). The exception summary status flag (ES, bit 7) is set when any of the unmasked exception

flags are set. When the ES flag is set, the x87 FPU exception handler is invoked, using one of the techniques

described in Section 8.7, “Handling x87 FPU Exceptions in Software.” (Note that if an exception flag is masked, the

x87 FPU will still set the appropriate flag if the associated exception occurs, but it will not set the ES flag.)

The exception flags are “sticky” bits (once set, they remain set until explicitly cleared). They can be cleared by

executing the FCLEX/FNCLEX (clear exceptions) instructions, by reinitializing the x87 FPU with the FINIT/FNINIT or

FSAVE/FNSAVE instructions, or by overwriting the flags with an FRSTOR or FLDENV instruction.

The B-bit (bit 15) is included for 8087 compatibility only. It reflects the contents of the ES flag.

Table 8-1. Condition Code Interpretation

Instruction

C0

C3

C2

C1

FCOM, FCOMP, FCOMPP, FICOM, FICOMP, FTST,

Result of Comparison

Operands

0 or #IS

FUCOM, FUCOMP, FUCOMPP

are not

Comparable

FCOMI, FCOMIP, FUCOMI, FUCOMIP

Undefined. (These instructions set the

#IS

status flags in the EFLAGS register.)

FXAM

Operand class

Sign

FPREM, FPREM1

Q2

Q1

0 = reduction

Q0 or #IS

complete

1 = reduction

incomplete

F2XM1, FADD, FADDP, FBSTP, FCMOVcc,

Undefined

Roundup or #IS

FIADD, FDIV, FDIVP, FDIVR, FDIVRP, FIDIV,

FIDIVR, FIMUL, FIST, FISTP, FISUB, FISUBR,

FMUL, FMULP, FPATAN, FRNDINT, FSCALE, FST,

FSTP, FSUB, FSUBP, FSUBR, FSUBRP, FSQRT,

FYL2X, FYL2XP1

FCOS, FSIN, FSINCOS, FPTAN

Undefined

0 = source

Roundup or #IS

operand within

(Undefined if C2 =

range

1)

1 = source

operand out of

range

FABS, FBLD, FCHS, FDECSTP, FILD, FINCSTP,

Undefined

0 or #IS

FLD, Load Constants, FSTP (ext. prec.), FXCH,

FXTRACT

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PROGRAMMING WITH THE X87 FPU

Table 8-1. Condition Code Interpretation (Contd.)

FLDENV, FRSTOR

Each bit loaded from memory

FFREE, FLDCW, FCLEX/FNCLEX, FNOP,

FSTCW/FNSTCW, FSTENV/FNSTENV,

Undefined

FSTSW/FNSTSW,

FINIT/FNINIT, FSAVE/FNSAVE

0

0

0

0

8.1.3.4

Stack Fault Flag

The stack fault flag (bit 6 of the x87 FPU status word) indicates that stack overflow or stack underflow has occurred

with data in the x87 FPU data register stack. The x87 FPU explicitly sets the SF flag when it detects a stack overflow

or underflow condition, but it does not explicitly clear the flag when it detects an invalid-arithmetic-operand condi-

tion.

When this flag is set, the condition code flag C1 indicates the nature of the fault: overflow (C1 = 1) and under-

flow (C1 = 0). The SF flag is a “sticky” flag, meaning that after it is set, the processor does not clear it until it is

explicitly instructed to do so (for example, by an FINIT/FNINIT, FCLEX/FNCLEX, or FSAVE/FNSAVE instruction).

See Section 8.1.7, “x87 FPU Tag Word,” for more information on x87 FPU stack faults.

8.1.4

Branching and Conditional Moves on Condition Codes

The x87 FPU (beginning with the P6 family processors) supports two mechanisms for branching and performing

conditional moves according to comparisons of two floating-point values. These mechanism are referred to here as

the “old mechanism” and the “new mechanism.”

The old mechanism is available in the x87 FPU prior to the P6 family processors and in P6 family processors. This

mechanism uses the floating-point compare instructions (FCOM, FCOMP, FCOMPP, FTST, FUCOMPP, FICOM, and

FICOMP) to compare two floating-point values and set the condition code flags (C0 through C3) according to the

results. The contents of the condition code flags are then copied into the status flags of the EFLAGS register using

a two step process (see Figure 8-5):

1. The FSTSW AX instruction moves the x87 FPU status word into the AX register.

2. The SAHF instruction copies the upper 8 bits of the AX register, which includes the condition code flags, into the

lower 8 bits of the EFLAGS register.

When the condition code flags have been loaded into the EFLAGS register, conditional jumps or conditional moves

can be performed based on the new settings of the status flags in the EFLAGS register.

15

x87 FPU Status Word

0

Condition

Status

C

C

C

C

Code

Flag

3

2

1

0

C0

CF

C1

(none)

C2

PF

FSTSW AX Instruction

C3

ZF

15

AX Register

0

C

C

C

C

3

2

1

0

SAHF Instruction

31

EFLAGS Register

7

0

Z

P

C

1

F

F

F

Figure 8-5. Moving the Condition Codes to the EFLAGS Register

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PROGRAMMING WITH THE X87 FPU

The new mechanism is available beginning with the P6 family processors. Using this mechanism, the new floating-

point compare and set EFLAGS instructions (FCOMI, FCOMIP, FUCOMI, and FUCOMIP) compare two floating-point

values and set the ZF, PF, and CF flags in the EFLAGS register directly. A single instruction thus replaces the three

instructions required by the old mechanism.

Note also that the FCMOVcc instructions (also new in the P6 family processors) allow conditional moves of floating-

point values (values in the x87 FPU data registers) based on the setting of the status flags (ZF, PF, and CF) in the

EFLAGS register. These instructions eliminate the need for an IF statement to perform conditional moves of

floating-point values.

8.1.5

x87 FPU Control Word

The 16-bit x87 FPU control word (see Figure 8-6) controls the precision of the x87 FPU and rounding method used.

It also contains the x87 FPU floating-point exception mask bits. The control word is cached in the x87 FPU control

register. The contents of this register can be loaded with the FLDCW instruction and stored in memory with the

FSTCW/FNSTCW instructions.

Infinity Control

Rounding Control

Precision Control

15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

P

U

O

Z

D

I

X

RC

PC

M

M

M

M

M

M

Exception Masks

Precision

Underflow

Overflow

Zero Divide

Denormal Operand

Invalid Operation

Reserved

Figure 8-6. x87 FPU Control Word

When the x87 FPU is initialized with either an FINIT/FNINIT or FSAVE/FNSAVE instruction, the x87 FPU control

word is set to 037FH, which masks all floating-point exceptions, sets rounding to nearest, and sets the x87 FPU

precision to 64 bits.

8.1.5.1

x87 FPU Floating-Point Exception Mask Bits

The exception-flag mask bits (bits 0 through 5 of the x87 FPU control word) mask the 6 floating-point exception

flags in the x87 FPU status word. When one of these mask bits is set, its corresponding x87 FPU floating-point

exception is blocked from being generated.

8.1.5.2

Precision Control Field

The precision-control (PC) field (bits 8 and 9 of the x87 FPU control word) determines the precision (64, 53, or 24

bits) of floating-point calculations made by the x87 FPU (see Table 8-2). The default precision is double extended

precision, which uses the full 64-bit significand available with the double extended precision floating-point format

of the x87 FPU data registers. This setting is best suited for most applications, because it allows applications to take

full advantage of the maximum precision available with the x87 FPU data registers.

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PROGRAMMING WITH THE X87 FPU

Table 8-2. Precision Control Field (PC)

Precision

PC Field

Single Precision (24 bits)

00B

Reserved

01B

Double Precision (53 bits)

10B

Double Extended Precision (64 bits)

11B

The double precision and single precision settings reduce the size of the significand to 53 bits and 24 bits, respec-

tively. These settings are provided to support IEEE Standard 754 and to provide compatibility with the specifica-

tions of certain existing programming languages. Using these settings nullifies the advantages of the double

extended precision floating-point format's 64-bit significand length. When reduced precision is specified, the

rounding of the significand value clears the unused bits on the right to zeros.

The precision-control bits only affect the results of the following floating-point instructions: FADD, FADDP, FIADD,

FSUB, FSUBP, FISUB, FSUBR, FSUBRP, FISUBR, FMUL, FMULP, FIMUL, FDIV, FDIVP, FIDIV, FDIVR, FDIVRP, FIDIVR,

and FSQRT.

8.1.5.3

Rounding Control Field

The rounding-control (RC) field of the x87 FPU control register (bits 10 and 11) controls how the results of x87 FPU

floating-point instructions are rounded. See Section 4.8.4, “Rounding,” for a discussion of rounding of floating-

point values; See Section 4.8.4.1, “Rounding Control (RC) Fields,” for the encodings of the RC field.

8.1.6

Infinity Control Flag

The infinity control flag (bit 12 of the x87 FPU control word) is provided for compatibility with the Intel 287 Math

Coprocessor; it is not meaningful for later version x87 FPU coprocessors or IA-32 processors. See Section 4.8.3.3,

“Signed Infinities,” for information on how the x87 FPUs handle infinity values.

8.1.7

x87 FPU Tag Word

The 16-bit tag word (see Figure 8-7) indicates the contents of each the 8 registers in the x87 FPU data-register

stack (one 2-bit tag per register). The tag codes indicate whether a register contains a valid number, zero, or a

special floating-point number (NaN, infinity, denormal, or unsupported format), or whether it is empty. The x87

FPU tag word is cached in the x87 FPU in the x87 FPU tag word register. When the x87 FPU is initialized with either

an FINIT/FNINIT or FSAVE/FNSAVE instruction, the x87 FPU tag word is set to FFFFH, which marks all the x87 FPU

data registers as empty.

15

0

TAG(7)

T

AG(6)

TAG(5)

TAG(4)

TAG(3)

TAG(2)

TAG(1)

TAG(0)

TAG Values

00 - Valid

01 - Zero

10 - Special: invalid (NaN, unsupported), infinity, or denormal

11 - Empty

Figure 8-7. x87 FPU Tag Word

Each tag in the x87 FPU tag word corresponds to a physical register (numbers 0 through 7). The current top-of-

stack (TOP) pointer stored in the x87 FPU status word can be used to associate tags with registers relative to ST(0).

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PROGRAMMING WITH THE X87 FPU

• FXRSTOR, XRSTOR. These instructions load data from a memory image whose format depend on operating

mode and the REX prefix. The memory formats are given in Tables 3-45, 3-48, and 3-49 in Chapter 3,

“Instruction Set Reference, A-L,” of the Intel^® 64 and IA-32 Architectures Software Developer’s Manual,

Volume 2A.

- Outside of 64-bit mode or if REX.W = 0, the instructions operate as follows:

• For each of FIP and FDP, each instruction loads the lower 32 bits from memory and clears the upper 32

bits.

• Each instruction loads FCS and FDS from memory.

- In 64-bit mode with REX.W = 1, the instructions operate as follows:

• Each instruction loads FIP and FDP from memory.

• Each instruction clears FCS and FDS.

• FXSAVE, XSAVE, and XSAVEOPT. These instructions store data into a memory image whose format depend on

operating mode and the REX prefix. The memory formats are given in Tables 3-45, 3-48, and 3-49 in Chapter

3, “Instruction Set Reference, A-L,” of the Intel^® 64 and IA-32 Architectures Software Developer’s Manual,

Volume 2A.

- Outside of 64-bit mode or if REX.W = 0, the instructions operate as follows:

• Each instruction saves the lower 32 bits of each of FIP and FDP into memory. The upper 32 bits are not

saved.

• Each instruction saves FCS and FDS into memory. If CPUID.07H.00H:EBX[13] = 1, the processor

deprecates FCS and FDS; it saves each as 0000H.

- In 64-bit mode with REX.W = 1, each instruction saves FIP and FDP into memory. FCS and FDS are not

saved.

8.1.9

Last Instruction Opcode

The x87 FPU stores in the 11-bit x87 FPU opcode register (FOP) the opcode of the last x87 non-control instruction

executed that incurred an unmasked x87 exception. (This information provides state information for exception

handlers.) Only the first and second opcode bytes (after all prefixes) are stored in the x87 FPU opcode register.

Figure 8-8 shows the encoding of these two bytes. Since the upper 5 bits of the first opcode byte are the same for

all floating-point opcodes (11011B), only the lower 3 bits of this byte are stored in the opcode register.

8.1.9.1

Fopcode Compatibility Sub-mode

Some Pentium 4 and Intel Xeon processors provide program control over the value stored into FOP. Here, bit 2 of

the IA32_MISC_ENABLE MSR enables (set) or disables (clear) the fopcode compatibility mode.

If fopcode compatibility mode is enabled, FOP is defined as it had been in previous IA-32 implementations, as the

opcode of the last x87 non-control instruction executed (even if that instruction did not incur an unmasked x87

exception).

1st Instruction Byte

2nd Instruction Byte

7

2

0

7

0

10

8

7

0

x87 FPU Opcode Register

Figure 8-8. Contents of x87 FPU Opcode Registers

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PROGRAMMING WITH THE X87 FPU

The fopcode compatibility mode should be enabled only when x87 FPU floating-point exception handlers are

designed to use the fopcode to analyze program performance or restart a program after an exception has been

handled.

More recent Intel 64 processors do not support fopcode compatibility mode and do not allow software to set bit 2

of the IA32_MISC_ENABLE MSR.

8.1.10 Saving the x87 FPU State with FSTENV/FNSTENV and FSAVE/FNSAVE

The FSTENV/FNSTENV and FSAVE/FNSAVE instructions store x87 FPU state information in memory for use by

exception handlers and other system and application software. The FSTENV/FNSTENV instruction saves the

contents of the status, control, tag, x87 FPU instruction pointer, x87 FPU data pointer, and opcode registers. The

FSAVE/FNSAVE instruction stores that information plus the contents of the x87 FPU data registers. Note that the

FSAVE/FNSAVE instruction also initializes the x87 FPU to default values (just as the FINIT/FNINIT instruction does)

after it has saved the original state of the x87 FPU.

The manner in which this information is stored in memory depends on the operating mode of the processor

(protected mode or real-address mode) and on the operand-size attribute in effect (32-bit or 16-bit). See Figures

8-9 through 8-12. In virtual-8086 mode or SMM, the real-address mode formats shown in Figure 8-12 is used. See

Chapter 34, “System Management Mode,” of the Intel^® 64 and IA-32 Architectures Software Developer’s Manual,

Volume 3C, for information on using the x87 FPU while in SMM.

The FLDENV and FRSTOR instructions allow x87 FPU state information to be loaded from memory into the x87 FPU.

Here, the FLDENV instruction loads only the status, control, tag, x87 FPU instruction pointer, x87 FPU data pointer,

and opcode registers, and the FRSTOR instruction loads all the x87 FPU registers, including the x87 FPU stack

registers.

32-Bit Protected Mode Format

31

16

15

0

Control Word

0

Status Word

4

Tag Word

8

FPU Instruction Pointer Offset (FIP)

12

0 0 0 0 0

Bits 10:0 of opcode

FPU Instruction Pointer Selector

16

FPU Data Pointer Offset (FDP)

20

FPU Data Pointer Selector (FDS)

24

For instructions that also store x87 FPU data registers, the eight

80-bit registers (R0-R7) follow the above structure in sequence.

Figure 8-9. Protected Mode x87 FPU State Image in Memory, 32-Bit Format

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PROGRAMMING WITH THE X87 FPU

32-Bit Real-Address Mode Format

31

16

15

0

Control Word

0

Status Word

4

Tag Word

8

FIP[15:0]

12

0 0 0 0

FIP[31:16]

FOP[10:0]

16

FDP[15:0]

20

0 0 0 0

FDP[31:16]

0 0 0 0 0 0 0 0 0 0 0 0

24

For instructions that also store x87 FPU data registers, the eight

80-bit registers (R0-R7) follow the above structure in sequence.

Figure 8-10. Real Mode x87 FPU State Image in Memory, 32-Bit Format

16-Bit Protected Mode Format

15

0

Control Word

0

Status Word

2

Tag Word

4

FIP

6

FCS

8

FDP

10

FDS

12

Figure 8-11. Protected Mode x87 FPU State Image in Memory, 16-Bit Format

16-Bit Real-Address Mode and

Virtual-8086 Mode Format

15

0

Control Word

0

Status Word

2

Tag Word

4

FIP[15:0]

6

FIP[19:16]

0

Bits 10:0 of opcode

8

FDP[15:0]

10

FDP[19:16]

0

0 0 0 0 0 0 0 0 0 0 0

12

Figure 8-12. Real Mode x87 FPU State Image in Memory, 16-Bit Format

8.1.11 Saving the x87 FPU State with FXSAVE

The FXSAVE and FXRSTOR instructions save and restore, respectively, the x87 FPU state along with the state of the

XMM registers and the MXCSR register. Using the FXSAVE instruction to save the x87 FPU state has two benefits:

(1) FXSAVE executes faster than FSAVE, and (2) FXSAVE saves the entire x87 FPU, MMX, and XMM state in one

operation. See Section 10.5, “FXSAVE and FXRSTOR Instructions,” for additional information about these instruc-

tions.

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PROGRAMMING WITH THE X87 FPU

8.2

X87 FPU DATA TYPES

The x87 FPU recognizes and operates on the following seven data types (see Figures 8-13): single precision

floating-point, double precision floating-point, double extended precision floating-point, signed word integer,

signed doubleword integer, signed quadword integer, and packed BCD decimal integers.

For detailed information about these data types, see Section 4.2.2, “Floating-Point Data Types,” Section 4.2.1.2,

“Signed Integers,” and Section 4.7, “BCD and Packed BCD Integers.”

With the exception of the 80-bit double extended precision floating-point format, all of these data types exist in

memory only. When they are loaded into x87 FPU data registers, they are converted into double extended precision

floating-point format and operated on in that format.

Denormal values are also supported in each of the floating-point types, as required by IEEE Standard 754. When a

denormal number in single precision or double precision floating-point format is used as a source operand and the

denormal exception is masked, the x87 FPU automatically normalizes the number when it is converted to double

extended precision format.

When stored in memory, the least significant byte of an x87 FPU data-type value is stored at the initial address

specified for the value. Successive bytes from the value are then stored in successively higher addresses in

memory. The floating-point instructions load and store memory operands using only the initial address of the

operand.

Single Precision Floating-Point

Sign

Exp.

Fraction

3130

23 22

Implied Integer

0

Double Precision Floating-Point

Sign

Exponent

Fraction

6362

52 51

0

Implied Integer

Sign

Double Extended Precision Floating-Point

Exponent

Fraction

7978

646362

0

Integer

Word Integer

Sign

15

14

0

Doubleword Integer

Sign

3130

0

Quadword Integer

Sign

Sign

6362

0

Packed BCD Integers

X

D17 D16 D15 D14 D13 D12 D11 D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

79

78

7271

4 Bits = 1 BCD Digit

0

Figure 8-13. x87 FPU Data Type Formats

As a general rule, values should be stored in memory in double precision format. This format provides sufficient

range and precision to return correct results with a minimum of programmer attention. The single precision format

is useful for debugging algorithms, because rounding problems will manifest themselves more quickly in this

format. The double extended precision format is normally reserved for holding intermediate results in the x87 FPU

registers and constants. Its extra length is designed to shield final results from the effects of rounding and over-

flow/underflow in intermediate calculations. However, when an application requires the maximum range and preci-

sion of the x87 FPU (for data storage, computations, and results), values can be stored in memory in double

extended precision format.

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PROGRAMMING WITH THE X87 FPU

8.2.1

Indefinites

For each x87 FPU data type, one unique encoding is reserved for representing the special value indefinite. The x87

FPU produces indefinite values as responses to some masked floating-point invalid-operation exceptions. See

Tables 4-1, 4-3, and 4-5 for the encoding of the integer indefinite, QNaN floating-point indefinite, and packed BCD

integer indefinite, respectively.

The binary integer encoding 100..00B represents either of two things, depending on the circumstances of its use:

• The largest negative number supported by the format (-2¹⁵, -2³¹, or -2⁶³).

• The integer indefinite value.

If this encoding is used as a source operand (as in an integer load or integer arithmetic instruction), the x87 FPU

interprets it as the largest negative number representable in the format being used. If the x87 FPU detects an

invalid operation when storing an integer value in memory with an FIST/FISTP instruction and the invalid-operation

exception is masked, the x87 FPU stores the integer indefinite encoding in the destination operand as a masked

response to the exception. In situations where the origin of a value with this encoding may be ambiguous, the

invalid-operation exception flag can be examined to see if the value was produced as a response to an exception.

8.2.2

Unsupported Double Extended Precision Floating-Point Encodings and Pseudo-

Denormals

The double extended precision floating-point format permits many encodings that do not fall into any of the cate-

gories shown in Table 4-3. Table 8-3 shows these unsupported encodings. Some of these encodings were supported

by the Intel 287 math coprocessor; however, most of them are not supported by the Intel 387 math coprocessor

and later IA-32 processors. These encodings are no longer supported due to changes made in the final version of

IEEE Standard 754 that eliminated these encodings.

Specifically, the categories of encodings formerly known as pseudo-NaNs, pseudo-infinities, and un-normal

numbers are not supported and should not be used as operand values. The Intel 387 math coprocessor and later

IA-32 processors generate an invalid-operation exception when these encodings are encountered as operands.

Beginning with the Intel 387 math coprocessor, the encodings formerly known as pseudo-denormal numbers are

not generated by IA-32 processors. When encountered as operands, however, they are handled correctly, consid-

ering the biased exponent as 1 (and the unbiased exponent as -16382); that is, they are treated as denormals and

a denormal exception is generated. Pseudo-denormal numbers should not be used as operand values. They are

supported by current IA-32 processors (as described here) to support legacy code.

Table 8-3. Unsupported Double Extended Precision Floating-Point Encodings and Pseudo-Denormals

Significand

Class

Sign

Biased Exponent

Integer

Fraction

Positive

0

11..11

0

11..11

Pseudo-NaNs

Quiet

0

11..11

10..00

0

11..11

0

01..11

Signaling

0

11..11

00..01

Positive Floating-Point

Pseudo-infinity

0

11..11

0

00..00

0

11..10

0

11..11

Unnormals

0

00..01

00..00

Pseudo-denormals

0

00..00

1

11..11

0

00..00

00..00

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PROGRAMMING WITH THE X87 FPU

Table 8-3. Unsupported Double Extended Precision Floating-Point Encodings and Pseudo-Denormals (Contd.)

Negative Floating-Point

Pseudo-denormals

1

00..00

1

11..11

1

00..00

00..00

1

11..10

0

11..01

Unnormals

1

00..01

00..00

Pseudo-infinity

1

11..11

0

00..00

Negative Pseudo-NaNs

1

11..11

0

01..11

Signaling

1

11..11

00..01

1

11..11

0

11..11

Quiet

1

11..11

10..00

← 15 bits →

← 63 bits →

8.3

X87 FPU INSTRUCTION SET

The floating-point instructions that the x87 FPU supports can be grouped into six functional categories:

• Data transfer instructions.

• Basic arithmetic instructions.

• Comparison instructions.

• Transcendental instructions.

• Load constant instructions.

• x87 FPU control instructions.

See Section 5.2, “x87 FPU Instructions,” for a list of the floating-point instructions by category.

The following section briefly describes the instructions in each category. Detailed descriptions of the floating-point

instructions are given in the Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C,

& 2D.

8.3.1

Escape (ESC) Instructions

All of the instructions in the x87 FPU instruction set fall into a class of instructions known as escape (ESC) instruc-

tions. All of these instructions have a common opcode format, where the first byte of the opcode is one of the

numbers from D8H through DFH.

8.3.2

x87 FPU Instruction Operands

Most floating-point instructions require one or two operands, located on the x87 FPU data-register stack or in

memory. (None of the floating-point instructions accept immediate operands.)

When an operand is located in a data register, it is referenced relative to the ST(0) register (the register at the top

of the register stack), rather than by a physical register number. Often the ST(0) register is an implied operand.

Operands in memory can be referenced using the same operand addressing methods described in Section 3.7,

“Operand Addressing.”

8.3.3

Data Transfer Instructions

The data transfer instructions (see Table 8-4) perform the following operations:

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PROGRAMMING WITH THE X87 FPU

• Load a floating-point, integer, or packed BCD operand from memory into the ST(0) register.

• Store the value in an ST(0) register to memory in floating-point, integer, or packed BCD format.

• Move values between registers in the x87 FPU register stack.

The FLD (load floating-point) instruction pushes a floating-point operand from memory onto the top of the x87 FPU

data-register stack. If the operand is in single precision or double precision floating-point format, it is automatically

converted to double extended precision floating-point format. This instruction can also be used to push the value in

a selected x87 FPU data register onto the top of the register stack.

The FILD (load integer) instruction converts an integer operand in memory into double extended precision floating-

point format and pushes the value onto the top of the register stack. The FBLD (load packed decimal) instruction

performs the same load operation for a packed BCD operand in memory.

Table 8-4. Data Transfer Instructions

Floating-Point

Integer

Packed Decimal

FLD

Load Floating-Point

FILD

Load Integer

FBLD

Load Packed

Decimal

FST

Store Floating-Point

FIST

Store Integer

FSTP

Store Floating-Point and

FISTP

Store Integer

FBSTP

Store Packed

Pop

and Pop

Decimal and Pop

FXCH

Exchange Register

Contents

FCMOVcc

Conditional Move

The FST (store floating-point) and FIST (store integer) instructions store the value in register ST(0) in memory in

the destination format (floating-point or integer, respectively). Again, the format conversion is carried out auto-

matically.

The FSTP (store floating-point and pop), FISTP (store integer and pop), and FBSTP (store packed decimal and pop)

instructions store the value in the ST(0) registers into memory in the destination format (floating-point, integer, or

packed BCD), then performs a pop operation on the register stack. A pop operation causes the ST(0) register to be

marked empty and the stack pointer (TOP) in the x87 FPU control work to be incremented by 1. The FSTP instruc-

tion can also be used to copy the value in the ST(0) register to another x87 FPU register [ST(i)].

The FXCH (exchange register contents) instruction exchanges the value in a selected register in the stack [ST(i)]

with the value in ST(0).

The FCMOVcc (conditional move) instructions move the value in a selected register in the stack [ST(i)] to register

ST(0) if a condition specified with a condition code (cc) is satisfied (see Table 8-5). The condition being tested for

is represented by the status flags in the EFLAGS register. The condition code mnemonics are appended to the

letters “FCMOV” to form the mnemonic for a FCMOVcc instruction.

Table 8-5. Floating-Point Conditional Move Instructions

Instruction Mnemonic

Status Flag States

Condition Description

FCMOVB

CF=1

Below

FCMOVNB

CF=0

Not below

FCMOVE

ZF=1

Equal

FCMOVNE

ZF=0

Not equal

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PROGRAMMING WITH THE X87 FPU

Table 8-5. Floating-Point Conditional Move Instructions (Contd.)

Instruction Mnemonic

Status Flag States

Condition Description

FCMOVBE

CF=1 or ZF=1

Below or equal

FCMOVNBE

CF=0 or ZF=0

Not below nor equal

FCMOVU

PF=1

Unordered

FCMOVNU

PF=0

Not unordered

Like the CMOVcc instructions, the FCMOVcc instructions are useful for optimizing small IF constructions. They also

help eliminate branching overhead for IF operations and the possibility of branch mispredictions by the processor.

Software can check if the FCMOVcc instructions are supported by checking the processor’s feature information with

the CPUID instruction.

8.3.4

Load Constant Instructions

The following instructions push commonly used constants onto the top [ST(0)] of the x87 FPU register stack:

FLDZ

Load +0.0.

FLD1

Load +1.0.

FLDPI

Load π.

FLDL2T

Load log₂ 10.

FLDL2E

Load log₂e.

FLDLG2

Load log₁₀2.

FLDLN2

Load log_e2.

The constant values have full double extended precision floating-point precision (64 bits) and are accurate to

approximately 19 decimal digits. They are stored internally in a format more precise than double extended preci-

sion floating-point. When loading the constant, the x87 FPU rounds the more precise internal constant according

to the RC (rounding control) field of the x87 FPU control word. The inexact-result exception (#P) is not generated

as a result of this rounding, nor is the C1 flag set in the x87 FPU status word if the value is rounded up. See

Section 8.3.8, “Approximation of Pi,” for information on the π constant.

8.3.5

Basic Arithmetic Instructions

The following floating-point instructions perform basic arithmetic operations on floating-point numbers. Where

applicable, these instructions match IEEE Standard 754:

FADD/FADDP

Add floating-point.

FIADD

Add integer to floating-point.

FSUB/FSUBP

Subtract floating-point.

FISUB

Subtract integer from floating-point.

FSUBR/FSUBRP

Reverse subtract floating-point.

FISUBR

Reverse subtract floating-point from integer.

FMUL/FMULP

Multiply floating-point.

FIMUL

Multiply integer by floating-point.

FDIV/FDIVP

Divide floating-point.

FIDIV

Divide floating-point by integer.

FDIVR/FDIVRP

Reverse divide.

FIDIVR

Reverse divide integer by floating-point.

FABS

Absolute value.

FCHS

Change sign.

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PROGRAMMING WITH THE X87 FPU

FXAM

Examine.

Comparison of floating-point values differ from comparison of integers because floating-point values have four

(rather than three) mutually exclusive relationships: less than, equal, greater than, and unordered.

The unordered relationship is true when at least one of the two values being compared is a NaN or in an unsup-

ported format. This additional relationship is required because, by definition, NaNs are not numbers, so they

cannot have less than, equal, or greater than relationships with other floating-point values.

The FCOM, FCOMP, and FCOMPP instructions compare the value in register ST(0) with a floating-point source

operand and set the condition code flags (C0, C2, and C3) in the x87 FPU status word according to the results (see

Table 8-6).

If an unordered condition is detected (one or both of the values are NaNs or in an undefined format), a floating-

point invalid-operation exception is generated.

The pop versions of the instruction pop the x87 FPU register stack once or twice after the comparison operation is

complete.

The FUCOM, FUCOMP, and FUCOMPP instructions operate the same as the FCOM, FCOMP, and FCOMPP instructions.

The only difference is that with the FUCOM, FUCOMP, and FUCOMPP instructions, if an unordered condition is

detected because one or both of the operands are QNaNs, the floating-point invalid-operation exception is not

generated.

Table 8-6. Setting of x87 FPU Condition Code Flags for Floating-Point Number Comparisons

Condition

C3

C2

C0

ST(0) > Source Operand

0

0

0

ST(0) < Source Operand

0

0

1

ST(0) = Source Operand

1

0

0

Unordered

1

1

1

The FICOM and FICOMP instructions also operate the same as the FCOM and FCOMP instructions, except that the

source operand is an integer value in memory. The integer value is automatically converted into an double

extended precision floating-point value prior to making the comparison. The FICOMP instruction pops the x87 FPU

register stack following the comparison operation.

The FTST instruction performs the same operation as the FCOM instruction, except that the value in register ST(0)

is always compared with the value 0.0.

The FCOMI and FCOMIP instructions were introduced into the IA-32 architecture in the P6 family processors. They

perform the same comparison as the FCOM and FCOMP instructions, except that they set the status flags (ZF, PF,

and CF) in the EFLAGS register to indicate the results of the comparison (see Table 8-7) instead of the x87 FPU

condition code flags. The FCOMI and FCOMIP instructions allow condition branch instructions (Jcc) to be executed

directly from the results of their comparison.

Table 8-7. Setting of EFLAGS Status Flags for Floating-Point Number Comparisons

Comparison Results

ZF

PF

CF

ST0 > ST(i)

0

0

0

ST0 < ST(i)

0

0

1

ST0 = ST(i)

1

0

0

Unordered

1

1

1

Software can check if the FCOMI and FCOMIP instructions are supported by checking the processor’s feature infor-

mation with the CPUID instruction.

The FUCOMI and FUCOMIP instructions operate the same as the FCOMI and FCOMIP instructions, except that they

do not generate a floating-point invalid-operation exception if the unordered condition is the result of one or both

of the operands being a QNaN. The FCOMIP and FUCOMIP instructions pop the x87 FPU register stack following the

comparison operation.

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PROGRAMMING WITH THE X87 FPU

The FXAM instruction determines the classification of the floating-point value in the ST(0) register (that is, whether

the value is zero, a denormal number, a normal finite number, ∞, a NaN, or an unsupported format) or that the

register is empty. It sets the x87 FPU condition code flags to indicate the classification (see “FXAM-Examine” in

Chapter 3, “Instruction Set Reference, A-L,” of the Intel^® 64 and IA-32 Architectures Software Developer’s Manual,

Volume 2A). It also sets the C1 flag to indicate the sign of the value.

8.3.6.1

Branching on the x87 FPU Condition Codes

The processor does not offer any control-flow instructions that branch on the setting of the condition code flags

(C0, C2, and C3) in the x87 FPU status word. To branch on the state of these flags, the x87 FPU status word must

first be moved to the AX register in the integer unit. The FSTSW AX (store status word) instruction can be used for

this purpose. When these flags are in the AX register, the TEST instruction can be used to control conditional

branching as follows:

1. Check for an unordered result. Use the TEST instruction to compare the contents of the AX register with the

constant 0400H (see Table 8-8). This operation will clear the ZF flag in the EFLAGS register if the condition code

flags indicate an unordered result; otherwise, the ZF flag will be set. The JNZ instruction can then be used to

transfer control (if necessary) to a procedure for handling unordered operands.

Table 8-8. TEST Instruction Constants for Conditional Branching

Order

Constant

Branch

ST(0) > Source Operand

4500H

JZ

ST(0) < Source Operand

0100H

JNZ

ST(0) = Source Operand

4000H

JNZ

Unordered

0400H

JNZ

2. Check ordered comparison result. Use the constants given in Table 8-8 in the TEST instruction to test for a less

than, equal to, or greater than result, then use the corresponding conditional branch instruction to transfer

program control to the appropriate procedure or section of code.

If a program or procedure has been thoroughly tested and it incorporates periodic checks for QNaN results, then it

is not necessary to check for the unordered result every time a comparison is made.

See Section 8.1.4, “Branching and Conditional Moves on Condition Codes,” for another technique for branching on

x87 FPU condition codes.

Some non-comparison x87 FPU instructions update the condition code flags in the x87 FPU status word. To ensure

that the status word is not altered inadvertently, store it immediately following a comparison operation.

8.3.7

Trigonometric Instructions

The following instructions perform four common trigonometric functions:

FSIN

Sine.

FCOS

Cosine.

FSINCOS

Sine and cosine.

FPTAN

Tangent.

FPATAN

Arctangent.

These instructions operate on the top one or two registers of the x87 FPU register stack and they return their

results to the stack. The source operands for the FSIN, FCOS, FSINCOS, and FPTAN instructions must be given in

radians; the source operand for the FPATAN instruction is given in rectangular coordinate units.

The FSINCOS instruction returns both the sine and the cosine of a source operand value. It operates faster than

executing the FSIN and FCOS instructions in succession.

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PROGRAMMING WITH THE X87 FPU

The following sections give specific information about how the x87 FPU handles floating-point exceptions that are

unique to the x87 FPU.

8.4.1

Arithmetic vs. Non-arithmetic Instructions

When dealing with floating-point exceptions, it is useful to distinguish between arithmetic instructions and non-

arithmetic instructions. Non-arithmetic instructions have no operands or do not make substantial changes to

their operands. Arithmetic instructions do make significant changes to their operands; in particular, they make

changes that could result in floating-point exceptions being signaled. Table 8-9 lists the non-arithmetic and arith-

metic instructions. It should be noted that some non-arithmetic instructions can signal a floating-point stack (fault)

exception, but this exception is not the result of an operation on an operand.

Table 8-9. Arithmetic and Non-arithmetic Instructions

Non-arithmetic Instructions

Arithmetic Instructions

FABS

F2XM1

FCHS

FADD/FADDP

FCLEX

FBLD

FDECSTP

FBSTP

FFREE

FCOM/FCOMP/FCOMPP

FINCSTP

FCOS

FINIT/FNINIT

FDIV/FDIVP/FDIVR/FDIVRP

FLD (register-to-register)

FIADD

FLD (extended format from memory)

FICOM/FICOMP

FLD constant

FIDIV/FIDIVR

FLDCW

FILD

FLDENV

FIMUL

FNOP

FIST/FISTP¹

FRSTOR

FISUB/FISUBR

FSAVE/FNSAVE

FLD (single and double)

FST/FSTP (register-to-register)

FMUL/FMULP

FSTP (extended format to memory)

FPATAN

FSTCW/FNSTCW

FPREM/FPREM1

FSTENV/FNSTENV

FPTAN

FSTSW/FNSTSW

FRNDINT

WAIT/FWAIT

FSCALE

FXAM

FSIN

FXCH

FSINCOS

FSQRT

FST/FSTP (single and double)

FSUB/FSUBP/FSUBR/FSUBRP

FTST

FUCOM/FUCOMP/FUCOMPP

FXTRACT

FYL2X/FYL2XP1

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PROGRAMMING WITH THE X87 FPU

Table 8-9. Arithmetic and Non-arithmetic Instructions (Contd.)

Non-arithmetic Instructions

Arithmetic Instructions

NOTE:

1. The FISTTP instruction in SSE3 is an arithmetic x87 FPU instruction.

8.5

X87 FPU FLOATING-POINT EXCEPTION CONDITIONS

The following sections describe the various conditions that cause a floating-point exception to be generated by the

x87 FPU and the masked response of the x87 FPU when these conditions are detected. The Intel^® 64 and IA-32

Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C, & 2D, lists the floating-point exceptions that can

be signaled for each floating-point instruction.

See Section 4.9.2, “Floating-Point Exception Priority,” for a description of the rules for exception precedence when

more than one floating-point exception condition is detected for an instruction.

8.5.1

Invalid Operation Exception

The floating-point invalid-operation exception occurs in response to two sub-classes of operations:

• Stack overflow or underflow (#IS).

• Invalid arithmetic operand (#IA).

The flag for this exception (IE) is bit 0 of the x87 FPU status word, and the mask bit (IM) is bit 0 of the x87 FPU

control word. The stack fault flag (SF) of the x87 FPU status word indicates the type of operation that caused the

exception. When the SF flag is set to 1, a stack operation has resulted in stack overflow or underflow; when the flag

is cleared to 0, an arithmetic instruction has encountered an invalid operand. Note that the x87 FPU explicitly sets

the SF flag when it detects a stack overflow or underflow condition, but it does not explicitly clear the flag when it

detects an invalid-arithmetic-operand condition. As a result, the state of the SF flag can be 1 following an invalid-

arithmetic-operation exception, if it was not cleared from the last time a stack overflow or underflow condition

occurred. See Section 8.1.3.4, “Stack Fault Flag,” for more information about the SF flag.

8.5.1.1

Stack Overflow or Underflow Exception (#IS)

The x87 FPU tag word keeps track of the contents of the registers in the x87 FPU register stack (see Section 8.1.7,

“x87 FPU Tag Word”). It then uses this information to detect two different types of stack faults:

• Stack overflow - An instruction attempts to load a non-empty x87 FPU register from memory. A non-empty

register is defined as a register containing a zero (tag value of 01), a valid value (tag value of 00), or a special

value (tag value of 10).

• Stack underflow - An instruction references an empty x87 FPU register as a source operand, including

attempting to write the contents of an empty register to memory. An empty register has a tag value of 11.

NOTES

The term stack overflow originates from the situation where the program has loaded (pushed) eight

values from memory onto the x87 FPU register stack and the next value pushed on the stack causes

a stack wraparound to a register that already contains a value.

The term stack underflow originates from the opposite situation. Here, a program has stored

(popped) eight values from the x87 FPU register stack to memory and the next value popped from

the stack causes stack wraparound to an empty register.

When the x87 FPU detects stack overflow or underflow, it sets the IE flag (bit 0) and the SF flag (bit 6) in the x87

FPU status word to 1. It then sets condition-code flag C1 (bit 9) in the x87 FPU status word to 1 if stack overflow

occurred or to 0 if stack underflow occurred.

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PROGRAMMING WITH THE X87 FPU

If the invalid-operation exception is masked, the x87 FPU returns the floating-point, integer, or packed decimal

integer indefinite value to the destination operand, depending on the instruction being executed. This value over-

writes the destination register or memory location specified by the instruction.

If the invalid-operation exception is not masked, a software exception handler is invoked (see Section 8.7,

“Handling x87 FPU Exceptions in Software”) and the top-of-stack pointer (TOP) and source operands remain

unchanged.

8.5.1.2

Invalid Arithmetic Operand Exception (#IA)

The x87 FPU is able to detect a variety of invalid arithmetic operations that can be coded in a program. These oper-

ations are listed in Table 8-10. (This list includes the invalid operations defined in IEEE Standard 754.)

When the x87 FPU detects an invalid arithmetic operand, it sets the IE flag (bit 0) in the x87 FPU status word to 1.

If the invalid-operation exception is masked, the x87 FPU then returns an indefinite value or QNaN to the destina-

tion operand and/or sets the floating-point condition codes as shown in Table 8-10. If the invalid-operation excep-

tion is not masked, a software exception handler is invoked (see Section 8.7, “Handling x87 FPU Exceptions in

Software”) and the top-of-stack pointer (TOP) and source operands remain unchanged.

Table 8-10. Invalid Arithmetic Operations and the Masked Responses to Them

Condition

Masked Response

Any arithmetic operation on an operand that is in an unsupported

Return the QNaN floating-point indefinite value to the

format.

destination operand.

Any arithmetic operation on a SNaN.

Return a QNaN to the destination operand (see Table 4-8).

Ordered compare and test operations: one or both operands are

Set the condition code flags (C0, C2, and C3) in the x87 FPU

NaNs.

status word or the CF, PF, and ZF flags in the EFLAGS register to

111B (not comparable).

Addition: operands are opposite-signed infinities.

Return the QNaN floating-point indefinite value to the

Subtraction: operands are like-signed infinities.

destination operand.

Multiplication: ∞ by 0; 0 by ∞ .

Return the QNaN floating-point indefinite value to the

destination operand.

Division: ∞ by ∞ ; 0 by 0.

Return the QNaN floating-point indefinite value to the

destination operand.

Remainder instructions FPREM, FPREM1: modulus (divisor) is 0 or

Return the QNaN floating-point indefinite; clear condition code

dividend is ∞ .

flag C2 to 0.

Trigonometric instructions FCOS, FPTAN, FSIN, FSINCOS: source

Return the QNaN floating-point indefinite; clear condition code

operand is ∞ .

flag C2 to 0.

FSQRT: negative operand (except FSQRT (-0) = -0); FYL2X: negative

Return the QNaN floating-point indefinite value to the

operand (except FYL2X (-0) = -∞); FYL2XP1: operand more

destination operand.

negative than -1.

FBSTP: Converted value cannot be represented in 18 decimal digits,

Store packed BCD integer indefinite value in the destination

or source value is an SNaN, QNaN, ± ∞ , or in an unsupported

operand.

format.

FIST/FISTP: Converted value exceeds representable integer range

Store integer indefinite value in the destination operand.

of the destination operand, or source value is an SNaN, QNaN, ±∞,

or in an unsupported format.

FXCH: one or both registers are tagged empty.

Load empty registers with the QNaN floating-point indefinite

value, then perform the exchange.

Normally, when one or both of the source operands is a QNaN (and neither is an SNaN or in an unsupported

format), an invalid-operand exception is not generated. An exception to this rule is most of the compare instruc-

tions (such as the FCOM and FCOMI instructions) and the floating-point to integer conversion instructions

Vol. 1

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PROGRAMMING WITH THE X87 FPU

(FIST/FISTP and FBSTP). With these instructions, a QNaN source operand will generate an invalid-operand excep-

tion.

8.5.2

Denormal Operand Exception (#D)

The x87 FPU signals the denormal-operand exception under the following conditions:

• If an arithmetic instruction attempts to operate on a denormal operand (see Section 4.8.3.2, “Normalized and

Denormalized Finite Numbers”).

• If an attempt is made to load a denormal single precision or double precision floating-point value into an x87

FPU register. (If the denormal value being loaded is a double extended precision floating-point value, the

denormal-operand exception is not reported.)

The flag (DE) for this exception is bit 1 of the x87 FPU status word, and the mask bit (DM) is bit 1 of the x87 FPU

control word.

When a denormal-operand exception occurs and the exception is masked, the x87 FPU sets the DE flag, then

proceeds with the instruction. The denormal operand in single- or double precision floating-point format is auto-

matically normalized when converted to the double extended precision floating-point format. Subsequent opera-

tions will benefit from the additional precision of the internal double extended precision floating-point format.

When a denormal-operand exception occurs and the exception is not masked, the DE flag is set and a software

exception handler is invoked (see Section 8.7, “Handling x87 FPU Exceptions in Software”). The top-of-stack

pointer (TOP) and source operands remain unchanged.

For additional information about the denormal-operation exception, see Section 4.9.1.2, “Denormal Operand

Exception (#D).”

8.5.3

Divide-By-Zero Exception (#Z)

The x87 FPU reports a floating-point divide-by-zero exception whenever an instruction attempts to divide a finite

non-zero operand by 0. The flag (ZE) for this exception is bit 2 of the x87 FPU status word, and the mask bit (ZM)

is bit 2 of the x87 FPU control word. The FDIV, FDIVP, FDIVR, FDIVRP, FIDIV, and FIDIVR instructions and the other

instructions that perform division internally (FYL2X and FXTRACT) can report the divide-by-zero exception.

When a divide-by-zero exception occurs and the exception is masked, the x87 FPU sets the ZE flag and returns the

values shown in Table 8-11. If the divide-by-zero exception is not masked, the ZE flag is set, a software exception

handler is invoked (see Section 8.7, “Handling x87 FPU Exceptions in Software”), and the top-of-stack pointer

(TOP) and source operands remain unchanged.

Table 8-11. Divide-By-Zero Conditions and the Masked Responses to Them

Condition

Masked Response

Divide or reverse divide operation with a

Returns an ∞ signed with the exclusive OR of the sign of the two operands to the

0 divisor.

destination operand.

FYL2X instruction.

Returns an ∞ signed with the opposite sign of the non-zero operand to the destination

operand.

FXTRACT instruction.

ST(1) is set to -∞; ST(0) is set to 0 with the same sign as the source operand.

8.5.4

Numeric Overflow Exception (#O)

The x87 FPU reports a floating-point numeric overflow exception (#O) whenever the rounded result of an arith-

metic instruction exceeds the largest allowable finite value that will fit into the floating-point format of the destina-

tion operand. (See Section 4.9.1.4, “Numeric Overflow Exception (#O),” for additional information about the

numeric overflow exception.)

When using the x87 FPU, numeric overflow can occur on arithmetic operations where the result is stored in an x87

FPU data register. It can also occur on store floating-point operations (using the FST and FSTP instructions), where

a within-range value in a data register is stored in memory in a single precision or double precision floating-point

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Address Space

2³² -1

MMX Registers

Eight 64-Bit

General-Purpose

Registers

Eight 32-Bit

0

Figure 9-1. MMX Technology Execution Environment

• General-purpose registers - The eight general-purpose registers (see Figure 3-5) are used with existing IA-

32 addressing modes to address operands in memory. (MMX registers cannot be used to address memory).

General-purpose registers are also used to hold operands for some MMX technology operations. They are EAX,

EBX, ECX, EDX, EBP, ESI, EDI, and ESP.

9.2.1

MMX Technology in 64-Bit Mode and Compatibility Mode

In compatibility mode and 64-bit mode, MMX instructions function like they do in protected mode. Memory oper-

ands are specified using the ModR/M, SIB encoding described in Section 3.7.5.

9.2.2

MMX Registers

The MMX register set consists of eight 64-bit registers (see Figure 9-2), that are used to perform calculations on

the MMX packed integer data types. Values in MMX registers have the same format as a 64-bit quantity in memory.

The MMX registers have two data access modes: 64-bit access mode and 32-bit access mode. The 64-bit access

mode is used for:

•

64-bit memory accesses.

•

64-bit transfers between MMX registers.

• All pack, logical, and arithmetic instructions.

• Some unpack instructions.

The 32-bit access mode is used for:

•

32-bit memory accesses.

•

32-bit transfer between general-purpose registers and MMX registers.

• Some unpack instructions.

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63

0

MM7

MM6

MM5

MM4

MM3

MM2

MM1

MM0

Figure 9-2. MMX Register Set

Although MMX registers are defined in the IA-32 architecture as separate registers, they are aliased to the registers

in the FPU data register stack (R0 through R7).

See also Section 9.5, “Compatibility with x87 FPU Architecture.”

9.2.3

MMX Data Types

MMX technology introduced the following 64-bit data types to the IA-32 architecture (see Figure 9-3):

•

64-bit packed byte integers - eight packed bytes.

•

64-bit packed word integers - four packed words.

•

64-bit packed doubleword integers - two packed doublewords.

MMX instructions move 64-bit packed data types (packed bytes, packed words, or packed doublewords) and the

quadword data type between MMX registers and memory or between MMX registers in 64-bit blocks. However,

when performing arithmetic or logical operations on the packed data types, MMX instructions operate in parallel on

the individual bytes, words, or doublewords contained in MMX registers; see Section 9.2.5, “Single Instruction,

Multiple Data (SIMD) Execution Model.”

Packed Byte Integers

63

0

Packed Word Integers

63

0

Packed Doubleword Integers

63

0

Figure 9-3. Data Types Introduced with the MMX Technology

9.2.4

Memory Data Formats

When stored in memory: bytes, words, and doublewords in the packed data types are stored in consecutive

addresses. The least significant byte, word, or doubleword is stored at the lowest address and the most significant

byte, word, or doubleword is stored at the high address. The ordering of bytes, words, or doublewords in memory

is always little endian. That is, the bytes with the low addresses are less significant than the bytes with high

addresses.

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9.2.5

Single Instruction, Multiple Data (SIMD) Execution Model

MMX technology uses the single instruction, multiple data (SIMD) technique for performing arithmetic and logical

operations on bytes, words, or doublewords packed into MMX registers (see Figure 9-4). For example, the PADDSW

instruction adds 4 signed word integers from one source operand to 4 signed word integers in a second source

operand and stores 4 word integer results in a destination operand. This SIMD technique speeds up software

performance by allowing the same operation to be carried out on multiple data elements in parallel. MMX tech-

nology supports parallel operations on byte, word, and doubleword data elements when contained in MMX regis-

ters.

The SIMD execution model supported in the MMX technology directly addresses the needs of modern media,

communications, and graphics applications, which often use sophisticated algorithms that perform the same oper-

ations on a large number of small data types (bytes, words, and doublewords). For example, most audio data is

represented in 16-bit (word) quantities. The MMX instructions can operate on 4 words simultaneously with one

instruction. Video and graphics information is commonly represented as palletized 8-bit (byte) quantities. In

Figure 9-4, one MMX instruction operates on 8 bytes simultaneously.

Source 1

X3

X2

X1

X0

Source 2

Y3

Y2

Y1

Y0

OP

OP

OP

OP

Destination

X3 OP Y3

X2 OP Y2

X1 OP Y1

X0 OP Y0

Figure 9-4. SIMD Execution Model

9.3

SATURATION AND WRAPAROUND MODES

When performing integer arithmetic, an operation may result in an out-of-range condition, where the true result

cannot be represented in the destination format. For example, when performing arithmetic on signed word inte-

gers, positive overflow can occur when the true signed result is larger than 16 bits.

The MMX technology provides three ways of handling out-of-range conditions:

• Wraparound arithmetic - With wraparound arithmetic, a true out-of-range result is truncated (that is, the

carry or overflow bit is ignored and only the least significant bits of the result are returned to the destination).

Wraparound arithmetic is suitable for applications that control the range of operands to prevent out-of-range

results. If the range of operands is not controlled, however, wraparound arithmetic can lead to large errors. For

example, adding two large signed numbers can cause positive overflow and produce a negative result.

• Signed saturation arithmetic - With signed saturation arithmetic, out-of-range results are limited to the

representable range of signed integers for the integer size being operated on (see Table 9-1). For example, if

positive overflow occurs when operating on signed word integers, the result is “saturated” to 7FFFH, which is

the largest positive integer that can be represented in 16 bits; if negative overflow occurs, the result is

saturated to 8000H.

• Unsigned saturation arithmetic - With unsigned saturation arithmetic, out-of-range results are limited to

the representable range of unsigned integers for the integer size. So, positive overflow when operating on

unsigned byte integers results in FFH being returned and negative overflow results in 00H being returned.

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Table 9-1. Data Range Limits for Saturation

Data Type

Lower Limit

Upper Limit

Hexadecimal

Decimal

Hexadecimal

Decimal

Signed Byte

80H

-128

7FH

127

Signed Word

8000H

-32,768

7FFFH

32,767

Unsigned Byte

00H

0

FFH

255

Unsigned Word

0000H

0

FFFFH

65,535

Saturation arithmetic provides an answer for many overflow situations. For example, in color calculations, satura-

tion causes a color to remain pure black or pure white without allowing inversion. It also prevents wraparound arti-

facts from entering into computations when range checking of source operands it not used.

MMX instructions do not indicate overflow or underflow occurrence by generating exceptions or setting flags in the

EFLAGS register.

9.4

MMX INSTRUCTIONS

The MMX instruction set consists of 47 instructions, grouped into the following categories:

• Data transfer

• Arithmetic

• Comparison

• Conversion

• Unpacking

• Logical

• Shift

• Empty MMX state instruction (EMMS)

Table 9-2 gives a summary of the instructions in the MMX instruction set. The following sections give a brief over-

view of the instructions within each group.

NOTES

The MMX instructions described in this chapter are those instructions that are available in an IA-32

processor when CPUID.01H:EDX.MMX[23] = 1.

Section 10.4.4, “Intel® SSE 64-Bit SIMD Integer Instructions,” and Section 11.4.2, “Intel® SSE2

64-Bit and 128-Bit SIMD Integer Instructions,” list additional instructions included with the Intel

SSE/SSE2 extensions that operate on MMX registers but are not considered part of the MMX

instruction set.

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Table 9-2. MMX Instruction Set Summary

Category

Wraparound

Signed Saturation

Unsigned Saturation

Arithmetic

Addition

PADDB, PADDW, PADDD

PADDSB, PADDSW

PADDUSB, PADDUSW

PSUBB, PSUBW, PSUBD

PSUBSB, PSUBSW

PSUBUSB, PSUBUSW

Subtraction

PMULL, PMULH

PMADD

Multiplication

Multiply and Add

Comparison

Compare for Equal

PCMPEQB, PCMPEQW,

PCMPEQD

PCMPGTPB, PCMPGTPW,

Compare for Greater

PCMPGTPD

Than

Conversion

Pack

PACKSSWB,

PACKUSWB

PACKSSDW

Unpack

Unpack High

PUNPCKHBW,

PUNPCKHWD,

PUNPCKHDQ

Unpack Low

PUNPCKLBW,

PUNPCKLWD,

PUNPCKLDQ

Packed

Full Quadword

Logical

And

PAND

And Not

PANDN

Or

POR

Exclusive OR

PXOR

Shift

Shift Left Logical

PSLLW, PSLLD

PSLLQ

Shift Right Logical

PSRLW, PSRLD

PSRLQ

Shift Right Arithmetic

PSRAW, PSRAD

Doubleword Transfers

Quadword Transfers

Data Transfer

Register to Register

MOVD

MOVQ

Load from Memory

MOVD

MOVQ

Store to Memory

MOVD

MOVQ

Empty MMX State

EMMS

9.4.1

Data Transfer Instructions

The MOVD (Move 32 Bits) instruction transfers 32 bits of packed data from memory to an MMX register and vice

versa; or from a general-purpose register to an MMX register and vice versa.

The MOVQ (Move 64 Bits) instruction transfers 64 bits of packed data from memory to an MMX register and vice

versa; or transfers data between MMX registers.

9.4.2

Arithmetic Instructions

The arithmetic instructions perform addition, subtraction, multiplication, and multiply/add operations on packed

data types.

The PADDB/PADDW/PADDD (add packed integers) instructions and the PSUBB/PSUBW/ PSUBD (subtract packed

integers) instructions add or subtract the corresponding signed or unsigned data elements of the source and desti-

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9.6.7

Exception Handling in MMX Code

MMX instructions generate the same type of memory-access exceptions as other IA-32 instructions (page fault,

segment not present, and limit violations). Existing exception handlers do not have to be modified to handle these

types of exceptions for MMX code.

Unless there is a pending floating-point exception, MMX instructions do not generate numeric exceptions. There-

fore, there is no need to modify existing exception handlers or add new ones to handle numeric exceptions.

If a floating-point exception is pending, the subsequent MMX instruction generates a numeric error exception

(interrupt 16 and/or assertion of the FERR# pin). The MMX instruction resumes execution upon return from the

exception handler.

9.6.8

Register Mapping

MMX registers and their tags are mapped to physical locations of the floating-point registers and their tags.

Register aliasing and mapping is described in more detail in Chapter 15, “Intel® MMX™ Technology System

Programming,” in the Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

9.6.9

Effect of Instruction Prefixes on MMX Instructions

Table 9-3 describes the effect of instruction prefixes on MMX instructions. Unpredictable behavior can range from

being treated as a reserved operation on one generation of IA-32 processors to generating an invalid opcode

exception on another generation of processors.

Table 9-3. Effect of Prefixes on MMX Instructions

Prefix Type

Effect on MMX Instructions

Address Size Prefix (67H)

Affects instructions with a memory operand.

Reserved for instructions without a memory operand and may result in

unpredictable behavior.

Operand Size (66H)

Reserved and may result in unpredictable behavior.

Segment Override (2EH, 36H, 3EH, 26H, 64H,

Affects instructions with a memory operand.

65H)

Reserved for instructions without a memory operand and may result in

unpredictable behavior.

Repeat Prefix (F3H)

Reserved and may result in unpredictable behavior.

Repeat NE Prefix(F2H)

Reserved and may result in unpredictable behavior.

Lock Prefix (F0H)

Reserved; generates invalid opcode exception (#UD).

See “Instruction Prefixes” in Chapter 2, “Instruction Format,” of the Intel^® 64 and IA-32 Architectures Software

Developer’s Manual, Volume 2A, for a description of the instruction prefixes.

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PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)

Intel SSE is fully compatible with all software written for IA-32 processors. All existing software continues to run

correctly, without modification, on processors that incorporate Intel SSE. Enhancements to CPUID permit detection

of Intel SSE. Intel SSE is accessible from all IA-32 execution modes: protected mode, real address mode, and

virtual-8086 mode.

The following sections of this chapter describe the programming environment for Intel SSE, including: XMM regis-

ters, the packed single precision floating-point data type, and Intel SSE instructions. For additional information,

see:

• Section 11.6, “Writing Applications with Intel® SSE and SSE2.”

• Section 11.5, “Intel® SSE, SSE2, and SSE3 Exceptions,” describes the exceptions that can be generated with

Intel SSE/SSE2/SSE3 instructions.

• The Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C, & 2D, provides a

detailed description of these instructions.

• Chapter 16, “System Programming for Instruction Set Extensions and Processor Extended States,” in the Intel^®

64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, gives guidelines for integrating these

extensions into an operating-system environment.

10.2

INTEL® SSE PROGRAMMING ENVIRONMENT

Figure 10-1 shows the execution environment for Intel SSE. All Intel SSE instructions operate on the XMM regis-

ters, MMX registers, and/or memory as follows:

• XMM registers - These eight registers (see Figure 10-2 and Section 10.2.2, “XMM Registers”) are used to

operate on packed or scalar single precision floating-point data. Scalar operations are operations performed on

individual (unpacked) single precision floating-point values stored in the low doubleword of an XMM register.

XMM registers are referenced by the names XMM0 through XMM7.

Address Space

2³² -1

XMM Registers

Eight 128-Bit

MXCSR Register

32 Bits

MMX Registers

Eight 64-Bit

General-Purpose

Registers

Eight 32-Bit

0

EFLAGS Register

32 Bits

Figure 10-1. Intel® SSE Execution Environment

• MXCSR register - This 32-bit register (see Figure 10-3 and Section 10.2.3, “MXCSR Control and Status

Register”) provides status and control bits used in SIMD floating-point operations.

• MMX registers - These eight registers (see Figure 9-2) are used to perform operations on 64-bit packed

integer data. They are also used to hold operands for some operations performed between the MMX and XMM

registers. MMX registers are referenced by the names MM0 through MM7.

• General-purpose registers - The eight general-purpose registers (see Figure 3-5) are used along with the

existing IA-32 addressing modes to address operands in memory. (MMX and XMM registers cannot be used to

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address memory). The general-purpose registers are also used to hold operands for some SSE instructions and

are referenced as EAX, EBX, ECX, EDX, EBP, ESI, EDI, and ESP.

• EFLAGS register - This 32-bit register (see Figure 3-8) is used to record result of some compare operations.

10.2.1 Intel® SSE in 64-Bit Mode and Compatibility Mode

In compatibility mode, Intel SSE functions like it does in protected mode. In 64-bit mode, eight additional XMM

registers are accessible. Registers XMM8-XMM15 are accessed by using REX prefixes. Memory operands are spec-

ified using the ModR/M, SIB encoding described in Section 3.7.5.

Some Intel SSE instructions may be used to operate on general-purpose registers. Use the REX.W prefix to access

64-bit general-purpose registers. Note that if a REX prefix is used when it has no meaning, the prefix is ignored.

10.2.2 XMM Registers

Eight 128-bit XMM data registers were introduced into the IA-32 architecture with Intel SSE (see Figure 10-2).

These registers can be accessed directly using the names XMM0 to XMM7; and they can be accessed independently

from the x87 FPU and MMX registers and the general-purpose registers (that is, they are not aliased to any other

of the processor’s registers).

127

0

XMM7

XMM6

XMM5

XMM4

XMM3

XMM2

XMM1

XMM0

Figure 10-2. XMM Registers

Intel SSE instructions use the XMM registers only to operate on packed single precision floating-point operands.

SSE2 extensions expand the functions of the XMM registers to operand on packed or scalar double precision

floating-point operands and packed integer operands; see Section 11.2, “Intel® SSE2 Programming Environment,”

and Section 12.1, “Programming Environment and Data types.”

XMM registers can only be used to perform calculations on data; they cannot be used to address memory.

Addressing memory is accomplished by using the general-purpose registers.

Data can be loaded into XMM registers or written from the registers to memory in 32-bit, 64-bit, and 128-bit incre-

ments. When storing the entire contents of an XMM register in memory (128-bit store), the data is stored in 16

consecutive bytes, with the low-order byte of the register being stored in the first byte in memory.

10.2.3 MXCSR Control and Status Register

The 32-bit MXCSR register (see Figure 10-3) contains control and status information for Intel SSE, SSE2, and SSE3

SIMD floating-point operations. This register contains:

• Flag and mask bits for SIMD floating-point exceptions.

• Rounding control field for SIMD floating-point operations.

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• Flush-to-zero flag that provides a means of controlling underflow conditions on SIMD floating-point operations.

• Denormals-are-zeros flag that controls how SIMD floating-point instructions handle denormal source operands.

The contents of this register can be loaded from memory with the LDMXCSR and FXRSTOR instructions and stored

in memory with STMXCSR and FXSAVE.

Bits 16 through 31 of the MXCSR register are reserved and are cleared on a power-up or reset of the processor;

attempting to write a non-zero value to these bits, using either the FXRSTOR or LDMXCSR instructions, will result

in a general-protection exception (#GP) being generated.

31

16

15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

F

D

P

U

O

Z

D

I

P

U

O

Z

D

I

Reserved

T R

A

C

M

M

M

M

M

M

E

E

E

E

E

E

Z

Z

Flush to Zero

Rounding Control

Precision Mask

Underflow Mask

Overflow Mask

Divide-by-Zero Mask

Denormal Operation Mask

Invalid Operation Mask

Denormals Are Zeros*

Precision Flag

Underflow Flag

Overflow Flag

Divide-by-Zero Flag

Denormal Flag

Invalid Operation Flag

* The denormals-are-zeros flag was introduced in the Pentium 4 and Intel Xeon processor.

Figure 10-3. MXCSR Control/Status Register

10.2.3.1 SIMD Floating-Point Mask and Flag Bits

Bits 0 through 5 of the MXCSR register indicate whether a SIMD floating-point exception has been detected. They

are “sticky” flags. That is, after a flag is set, it remains set until explicitly cleared. To clear these flags, use the

LDMXCSR or the FXRSTOR instruction to write zeroes to them.

Bits 7 through 12 provide individual mask bits for the SIMD floating-point exceptions. An exception type is masked

if the corresponding mask bit is set, and it is unmasked if the bit is clear. These mask bits are set upon a power-up

or reset. This causes all SIMD floating-point exceptions to be initially masked.

If LDMXCSR or FXRSTOR clears a mask bit and sets the corresponding exception flag bit, a SIMD floating-point

exception will not be generated as a result of this change. The unmasked exception will be generated only upon the

execution of the next SSE/SSE2/SSE3 instruction that detects the unmasked exception condition.

For more information about the use of the SIMD floating-point exception mask and flag bits, see Section 11.5,

“Intel® SSE, SSE2, and SSE3 Exceptions,” and Section 12.8, “Intel® SSE3, SSSE3, And Intel® SSE4 Exceptions.”

10.2.3.2 SIMD Floating-Point Rounding Control Field

Bits 13 and 14 of the MXCSR register (the rounding control [RC] field) control how the results of SIMD floating-point

instructions are rounded. See Section 4.8.4, “Rounding,” for a description of the function and encoding of the

rounding control bits.

10.2.3.3 Flush-To-Zero

Bit 15 (FTZ) of the MXCSR register enables the flush-to-zero mode, which controls the masked response to a SIMD

floating-point underflow condition. When the underflow exception is masked and the flush-to-zero mode is

enabled, the processor performs the following operations when it detects a floating-point underflow condition.

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into a double quadword. See Figure 4-3 for the layout of a single precision floating-point value; refer to Section

4.2.2, “Floating-Point Data Types,” for a detailed description of the single precision floating-point format.

Contains 4 Single Precision

Floating-Point Values

127

96 95

64 63

32 31

0

Figure 10-4. 128-Bit Packed Single Precision Floating-Point Data Type

This 128-bit packed single precision floating-point data type is operated on in the XMM registers or in memory.

Conversion instructions are provided to convert two packed single precision floating-point values into two packed

doubleword integers or a scalar single precision floating-point value into a doubleword integer (see Figure 11-8).

Intel SSE provides conversion instructions between XMM registers and MMX registers, and between XMM registers

and general-purpose bit registers. See Figure 11-8.

The address of a 128-bit packed memory operand must be aligned on a 16-byte boundary, except in the following

cases:

• The MOVUPS instruction supports unaligned accesses.

• Scalar instructions that use a 4-byte memory operand that is not subject to alignment requirements.

Figure 4-2 shows the byte order of 128-bit (double quadword) data types in memory.

10.4

INTEL® SSE INSTRUCTION SET

Intel SSE instructions are divided into four functional groups:

• Packed and scalar single precision floating-point instructions.

•

64-bit SIMD integer instructions.

• State management instructions.

• Cacheability control, prefetch, and memory ordering instructions.

The following sections give an overview of each of the instructions in these groups.

10.4.1 Intel® SSE Packed and Scalar Floating-Point Instructions

The packed and scalar single precision floating-point instructions are divided into the following subgroups:

• Data movement instructions.

• Arithmetic instructions.

• Logical instructions.

• Comparison instructions.

• Shuffle instructions.

• Conversion instructions.

The packed single precision floating-point instructions perform SIMD operations on packed single precision

floating-point operands (see Figure 10-5). Each source operand contains four single precision floating-point values,

and the destination operand contains the results of the operation (OP) performed in parallel on the corresponding

values (X0 and Y0, X1 and Y1, X2 and Y2, and X3 and Y3) in each operand.

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X3

X2

X1

X0

Y3

Y2

Y1

Y0

OP

OP

OP

OP

X3 OP Y3

X2 OP Y2

X1 OP Y1

X0 OP Y0

Figure 10-5. Packed Single Precision Floating-Point Operation

The scalar single precision floating-point instructions operate on the low (least significant) doublewords of the two

source operands (X0 and Y0); see Figure 10-6. The three most significant doublewords (X1, X2, and X3) of the first

source operand are passed through to the destination. The scalar operations are similar to the floating-point oper-

ations performed in the x87 FPU data registers with the precision control field in the x87 FPU control word set for

single precision (24-bit significand), except that x87 stack operations use a 15-bit exponent range for the result,

while SSE operations use an 8-bit exponent range.

X3

X2

X1

X0

Y3

Y2

Y1

Y0

OP

X3

X2

X1

X0 OP Y0

Figure 10-6. Scalar Single Precision Floating-Point Operation

10.4.1.1 Intel® SSE Data Movement Instructions

Intel SSE data movement instructions move single precision floating-point data between XMM registers and

between an XMM register and memory.

The MOVAPS (move aligned packed single precision floating-point values) instruction transfers a double quadword

operand containing four packed single precision floating-point values from memory to an XMM register and vice

versa, or between XMM registers. The memory address must be aligned to a 16-byte boundary; otherwise, a

general-protection exception (#GP) is generated.

The MOVUPS (move unaligned packed single precision, floating-point) instruction performs the same operations as

the MOVAPS instruction, except that 16-byte alignment of a memory address is not required.

The MOVSS (move scalar single precision floating-point) instruction transfers a 32-bit single precision floating-

point operand from memory to the low doubleword of an XMM register and vice versa, or between XMM registers.

The MOVLPS (move low packed single precision floating-point) instruction moves two packed single precision

floating-point values from memory to the low quadword of an XMM register and vice versa. The high quadword of

the register is left unchanged.

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DEST

X3

X2

X1

X0

SRC

Y3

Y2

Y1

Y0

DEST

Y3 ... Y0

Y3 ... Y0

X3 ... X0

X3 ... X0

Figure 10-7. SHUFPS Instruction, Packed Shuffle Operation

The UNPCKHPS (unpack and interleave high packed single precision floating-point values) instruction performs an

interleaved unpack of the high-order single precision floating-point values from the source and destination oper-

ands and stores the result in the destination operand (see Figure 10-8).

DEST

X3

X2

X1

X0

SRC

Y3

Y2

Y1

Y0

DEST

Y3

X3

Y2

X2

Figure 10-8. UNPCKHPS Instruction, High Unpack and Interleave Operation

The UNPCKLPS (unpack and interleave low packed single precision floating-point values) instruction performs an

interleaved unpack of the low-order single precision floating-point values from the source and destination operands

and stores the result in the destination operand (see Figure 10-9).

DEST

X3

X2

X1

X0

SRC

Y3

Y2

Y1

Y0

DEST

Y1

X1

Y0

X0

Figure 10-9. UNPCKLPS Instruction, Low Unpack and Interleave Operation

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PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)

• The non-temporal data is written to memory with WC semantics.

See also: Chapter 14, “Memory Cache Control,” in the Intel^® 64 and IA-32 Architectures Software Developer’s

Manual, Volume 3A.

Using the WC semantics, the store transaction will be weakly ordered, meaning that the data may not be written to

memory in program order, and the store will not write allocate (that is, the processor will not fetch the corre-

sponding cache line into the cache hierarchy, prior to performing the store). Also, different processor implementa-

tions may choose to collapse and combine these stores.

The memory type of the region being written to can override the non-temporal hint, if the memory address speci-

fied for the non-temporal store is in uncacheable memory. Uncacheable as referred to here means that the region

being written to has been mapped with either an uncacheable (UC) or write protected (WP) memory type.

In general, WC semantics require software to ensure coherence, with respect to other processors and other system

agents (such as graphics cards). Appropriate use of synchronization and fencing must be performed for producer-

consumer usage models. Fencing ensures that all system agents have global visibility of the stored data; for

instance, failure to fence may result in a written cache line staying within a processor and not being visible to other

agents.

The memory type visible on the bus in the presence of memory type aliasing is implementation specific. As one

possible example, the memory type written to the bus may reflect the memory type for the first store to this line,

as seen in program order; other alternatives are possible. This behavior should be considered reserved, and

dependence on the behavior of any particular implementation risks future incompatibility.

NOTE

Some older CPU implementations (e.g., Pentium M) may implement non-temporal stores by

updating in place data that already reside in the cache hierarchy. For such processors, the

destination region should also be mapped as WC. If mapped as WB or WT, there is the potential for

speculative processor reads to bring the data into the caches; in this case, non-temporal stores

would then update in place, and data would not be flushed from the processor by a subsequent

fencing operation.

10.4.6.3 PREFETCHh Instructions

The PREFETCHh instructions permit programs to load data into the processor at a suggested cache level, so that

the data is closer to the processor’s load and store unit when it is needed. These instructions fetch 32 aligned bytes

(or more, depending on the implementation) containing the addressed byte to a location in the cache hierarchy

specified by the temporal locality hint (see Table 10-1). In this table, the first-level cache is closest to the processor

and second-level cache is farther away from the processor than the first-level cache. The hints specify a prefetch

of either temporal or non-temporal data (see Section 10.4.6.2, “Caching of Temporal vs. Non-Temporal Data”).

Subsequent accesses to temporal data are treated like normal accesses, while those to non-temporal data will

continue to minimize cache pollution. If the data is already present at a level of the cache hierarchy that is closer

to the processor, the PREFETCHh instruction will not result in any data movement. The PREFETCHh instructions do

not affect functional behavior of the program.

See Section 11.6.13, “Cacheability Hint Instructions,” for additional information about the PREFETCHh instructions.

Table 10-1. PREFETCHh Instructions Caching Hints

PREFETCHh Instruction

Mnemonic

Actions

PREFETCHT0

Temporal data-fetch data into all levels of cache hierarchy:

• Pentium III processor-1st-level cache or 2nd-level cache

• Pentium 4 and Intel Xeon processor-2nd-level cache

PREFETCHT1

Temporal data-fetch data into level 2 cache and higher

• Pentium III processor-2nd-level cache

• Pentium 4 and Intel Xeon processor-2nd-level cache

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PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)

Table 10-1. PREFETCHh Instructions Caching Hints (Contd.)

PREFETCHh Instruction

Mnemonic

Actions

PREFETCHT2

Temporal data-fetch data into level 2 cache and higher

• Pentium III processor-2nd-level cache

• Pentium 4 and Intel Xeon processor-2nd-level cache

PREFETCHNTA

Non-temporal data-fetch data into location close to the processor, minimizing cache pollution

• Pentium III processor-1st-level cache

• Pentium 4 and Intel Xeon processor-2nd-level cache

10.4.6.4 SFENCE Instruction

The SFENCE (Store Fence) instruction controls write ordering by creating a fence for memory store operations. This

instruction guarantees that the result of every store instruction that precedes the store fence in program order is

globally visible before any store instruction that follows the fence. The SFENCE instruction provides an efficient way

of ensuring ordering between procedures that produce weakly-ordered data and procedures that consume that

data.

10.5

FXSAVE AND FXRSTOR INSTRUCTIONS

The FXSAVE and FXRSTOR instructions were introduced into the IA-32 architecture in the Pentium II processor

family (prior to the introduction of the SSE extensions). The original versions of these instructions performed a fast

save and restore, respectively, of the x87 execution environment (x87 state). (By saving the state of the x87 FPU

data registers, the FXSAVE and FXRSTOR instructions implicitly save and restore the state of the MMX registers.)

The SSE extensions expanded the scope of these instructions to save and restore the states of the XMM registers

and the MXCSR register (SSE state), along with x87 state.

The FXSAVE and FXRSTOR instructions can be used in place of the FSAVE/FNSAVE and FRSTOR instructions;

however, the operation of the FXSAVE and FXRSTOR instructions are not identical to the operation of

FSAVE/FNSAVE and FRSTOR.

NOTE

The FXSAVE and FXRSTOR instructions are not considered part of the SSE instruction group. They

have a separate CPUID feature bit to indicate whether they are present (if

CPUID.01H:EDX.FXSR[24] = 1). The CPUID feature bit for SSE extensions does not indicate the

presence of FXSAVE and FXRSTOR.

The FXSAVE and FXRSTOR instructions organize x87 state and SSE state in a region of memory called the FXSAVE

area. Section 10.5.1 provides details of the FXSAVE area and its format. Section 10.5.2 describes operation of

FXSAVE, and Section 10.5.3 describes the operation of FXRSTOR.

10.5.1 FXSAVE Area

The FXSAVE and FXRSTOR instructions organize x87 state and SSE state in a region of memory called the FXSAVE

area. Each of the instructions takes a memory operand that specifies the 16-byte aligned base address of the

FXSAVE area on which it operates.

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PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)

Every FXSAVE area comprises the 512 bytes starting at the area’s base address. Table 10-2 illustrates the format

of the first 416 bytes of the legacy region of an FXSAVE area.

Table 10-2. Format of an FXSAVE Area

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CS or FPU

Reserved

FPU IP bits 31:0

FOP

Rsvd.

FTW

FSW

FCW

0

IP bits 63:32

DS or

MXCSR_MASK

MXCSR

Reserved

FPU DP

FPU DP bits 31:0

16

bits 63:32

Reserved

ST0/MM0

32

Reserved

ST1/MM1

48

Reserved

ST2/MM2

64

Reserved

ST3/MM3

80

Reserved

ST4/MM4

96

Reserved

ST5/MM5

112

Reserved

ST6/MM6

128

Reserved

ST7/MM7

144

XMM0

160

XMM1

176

XMM2

192

XMM3

208

XMM4

224

XMM5

240

XMM6

256

XMM7

272

XMM8

288

XMM9

304

XMM10

320

XMM11

336

XMM12

352

XMM13

368

XMM14

384

XMM15

400

The x87 state component comprises bytes 23:0 and bytes 159:32. The SSE state component comprises

bytes 31:24 and bytes 415:160. FXSAVE and FXRSTOR do not use bytes 511:416; bytes 463:416 are reserved.

Section 10.5.2 and Section 10.5.3 provide details of how FXSAVE and FXRSTOR use an FXSAVE area.

10.5.1.1 x87 State

Table 10-2 illustrates how FXSAVE and FXRSTOR organize x87 state and SSE state; the x87 state is listed below,

along with details of its interactions with FXSAVE and FXRSTOR:

• Bytes 1:0, 3:2, and 7:6 are used for x87 FPU Control Word (FCW), x87 FPU Status Word (FSW), and x87 FPU

Opcode (FOP), respectively.

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PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)

Intel SSE2 is fully compatible with all software written for IA-32 processors. All existing software continues to run

correctly, without modification, on processors that incorporate Intel SSE2, as well as in the presence of applications

that incorporate these extensions. Enhancements to the CPUID instruction permit detection of Intel SSE2. Also,

because Intel SSE2 uses the same registers as Intel SSE, no new operating-system support is required for saving

and restoring program state during a context switch beyond that provided for Intel SSE.

Intel SSE2 is accessible from all IA-32 execution modes: protected mode, real address mode, and virtual 8086

mode.

The following sections in this chapter describe the programming environment for Intel SSE2, including: the 128-bit

XMM floating-point register set, data types, and Intel SSE2 instructions. The chapter also describes exceptions that

can be generated with the Intel SSE and SSE2 instructions and gives guidelines for writing applications with Intel

SSE and SSE2.

For additional information about Intel SSE2, see:

• The Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C, & 2D, provides a

detailed description of individual Intel SSE2 instructions.

• Chapter 16, “System Programming for Instruction Set Extensions and Processor Extended States,” in the Intel^®

64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, gives guidelines for integrating Intel SSE

and SSE2 into an operating-system environment.

11.2

INTEL® SSE2 PROGRAMMING ENVIRONMENT

Figure 11-1 shows the programming environment for Intel SSE2. No new registers or other instruction execution

state are defined with Intel SSE2. Intel SSE2 instructions use XMM registers, MMX registers, and/or IA-32 general-

purpose registers, as follows:

• XMM registers - These eight registers (see Figure 10-2) are used to operate on packed or scalar double

precision floating-point data. Scalar operations are operations performed on individual (unpacked) double

precision floating-point values stored in the low quadword of an XMM register. XMM registers are also used to

perform operations on 128-bit packed integer data. They are referenced by the names XMM0 through XMM7.

Address Space

2³² -1

XMM Registers

Eight 128-Bit

MXCSR Register

32 Bits

MMX Registers

Eight 64-Bit

General-Purpose

Registers

Eight 32-Bit

0

EFLAGS Register

32 Bits

Figure 11-1. Intel® Streaming SIMD Extensions 2 Execution Environment

• MXCSR register - This 32-bit register (see Figure 10-3) provides status and control bits used in floating-point

operations. The denormals-are-zeros and flush-to-zero flags in this register provide a higher performance

alternative for the handling of denormal source operands and denormal (underflow) results. For more

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PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)

128-Bit Packed Double-

Precision Floating-Point

127

64 63

0

128-Bit Packed Byte Integers

127

0

128-Bit Packed Word Integers

127

0

128-Bit Packed Doubleword

Integers

127

0

128-Bit Packed Quadword

Integers

127

0

Figure 11-2. Data Types Introduced with Intel® SSE2

All of these data types are operated on in XMM registers or memory. Instructions are provided to convert between

these 128-bit data types and the 64-bit and 32-bit data types.

The address of a 128-bit packed memory operand must be aligned on a 16-byte boundary, except in the following

cases:

• A MOVUPD instruction that supports unaligned accesses.

• Scalar instructions that use an 8-byte memory operand that is not subject to alignment requirements.

Figure 4-2 shows the byte order of 128-bit (double quadword) and 64-bit (quadword) data types in memory.

11.4

INTEL® SSE2 INSTRUCTIONS

The Intel SSE2 instructions are divided into four functional groups:

• Packed and scalar double precision floating-point instructions.

•

64-bit and 128-bit SIMD integer instructions.

•

128-bit extensions of SIMD integer instructions introduced with the MMX technology and Intel SSE.

• Cacheability-control and instruction-ordering instructions.

The following sections provide more information about each group.

11.4.1 Packed and Scalar Double Precision Floating-Point Instructions

The packed and scalar double precision floating-point instructions are divided into the following sub-groups:

• Data movement instructions.

• Arithmetic instructions.

• Comparison instructions.

• Conversion instructions.

• Logical instructions.

• Shuffle instructions.

The packed double precision floating-point instructions perform SIMD operations similarly to the packed single

precision floating-point instructions (see Figure 11-3). Each source operand contains two double precision floating-

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