Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023)

INSTRUCTION FORMATS AND ENCODINGS

Table B-13. General Purpose Instruction Formats and Encodings for Non-64-Bit Modes (Contd.)

Instruction and Format

Encoding

SUB - Integer Subtraction

register1 to register2

0010 100w : 11 reg1 reg2

register2 to register1

0010 101w : 11 reg1 reg2

memory to register

0010 101w : mod reg r/m

0010 100w : mod reg r/m

immediate to register

1000 00sw : 11 101 reg : immediate data

immediate to AL, AX, or EAX

0010 110w : immediate data

immediate to memory

1000 00sw : mod 101 r/m : immediate data

TEST - Logical Compare

register1 and register2

1000 010w : 11 reg1 reg2

memory and register

1000 010w : mod reg r/m

immediate and register

1111 011w : 11 000 reg : immediate data

immediate and AL, AX, or EAX

1010 100w : immediate data

immediate and memory

1111 011w : mod 000 r/m : immediate data

UD0 - Undefined instruction

0000 1111 : 1111 1111

UD1 - Undefined instruction

0000 1111 : 0000 1011

UD2 - Undefined instruction

0000 FFFF : 0000 1011

VERR - Verify a Segment for Reading

0000 1111 : 0000 0000 : 11 100 reg

memory

0000 1111 : 0000 0000 : mod 100 r/m

VERW - Verify a Segment for Writing

0000 1111 : 0000 0000 : 11 101 reg

memory

0000 1111 : 0000 0000 : mod 101 r/m

WAIT - Wait

1001 1011

WBINVD - Writeback and Invalidate Data Cache

0000 1111 : 0000 1001

WRMSR - Write to Model-Specific Register

0000 1111 : 0011 0000

XADD - Exchange and Add

register1, register2

0000 1111 : 1100 000w : 11 reg2 reg1

memory, reg

0000 1111 : 1100 000w : mod reg r/m

XCHG - Exchange Register/Memory with Register

register1 with register2

1000 011w : 11 reg1 reg2

AX or EAX with reg

1001 0 reg

memory with reg

1000 011w : mod reg r/m

XLAT/XLATB - Table Look-up Translation

1101 0111

XOR - Logical Exclusive OR

register1 to register2

0011 000w : 11 reg1 reg2

register2 to register1

0011 001w : 11 reg1 reg2

memory to register

0011 001w : mod reg r/m

Vol. 2D B-17

INSTRUCTION FORMATS AND ENCODINGS

Table B-13. General Purpose Instruction Formats and Encodings for Non-64-Bit Modes (Contd.)

Instruction and Format

Encoding

0011 000w : mod reg r/m

immediate to register

1000 00sw : 11 110 reg : immediate data

immediate to AL, AX, or EAX

0011 010w : immediate data

immediate to memory

1000 00sw : mod 110 r/m : immediate data

Prefix Bytes

address size

0110 0111

LOCK

1111 0000

operand size

0110 0110

CS segment override

0010 1110

DS segment override

0011 1110

ES segment override

0010 0110

FS segment override

0110 0100

GS segment override

0110 0101

SS segment override

0011 0110

NOTES:

1. The multi-byte NOP instruction does not alter the content of the register and will not issue a memory operation.

B.2.1

General Purpose Instruction Formats and Encodings for 64-Bit Mode

Table B-15 shows machine instruction formats and encodings for general purpose instructions in 64-bit mode.

Table B-14. Special Symbols

Symbol

Application

If the value of REX.W. is 1, it overrides the presence of 66H.

The value of bit W. in REX is has no effect.

Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode

Instruction and Format

Encoding

ADC - ADD with Carry

register1 to register2

0100 0R0B : 0001 000w : 11 reg1 reg2

qwordregister1 to qwordregister2

0100 1R0B : 0001 0001 : 11 qwordreg1 qwordreg2

register2 to register1

0100 0R0B : 0001 001w : 11 reg1 reg2

qwordregister1 to qwordregister2

0100 1R0B : 0001 0011 : 11 qwordreg1 qwordreg2

memory to register

0100 0RXB : 0001 001w : mod reg r/m

memory to qwordregister

0100 1RXB : 0001 0011 : mod qwordreg r/m

0100 0RXB : 0001 000w : mod reg r/m

qwordregister to memory

0100 1RXB : 0001 0001 : mod qwordreg r/m

immediate to register

0100 000B : 1000 00sw : 11 010 reg : immediate

immediate to qwordregister

0100 100B : 1000 0001 : 11 010 qwordreg : imm32

immediate to qwordregister

0100 1R0B : 1000 0011 : 11 010 qwordreg : imm8

B-18

Vol. 2D

INSTRUCTION FORMATS AND ENCODINGS

Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)

Instruction and Format

Encoding

immediate to AL, AX, or EAX

0001 010w : immediate data

immediate to RAX

0100 1000 : 0000 0101 : imm32

immediate to memory

0100 00XB : 1000 00sw : mod 010 r/m : immediate

immediate32 to memory64

0100 10XB : 1000 0001 : mod 010 r/m : imm32

immediate8 to memory64

0100 10XB : 1000 0031 : mod 010 r/m : imm8

ADD - Add

register1 to register2

0100 0R0B : 0000 000w : 11 reg1 reg2

qwordregister1 to qwordregister2

0100 1R0B 0000 0000 : 11 qwordreg1 qwordreg2

register2 to register1

0100 0R0B : 0000 001w : 11 reg1 reg2

qwordregister1 to qwordregister2

0100 1R0B 0000 0010 : 11 qwordreg1 qwordreg2

memory to register

0100 0RXB : 0000 001w : mod reg r/m

memory64 to qwordregister

0100 1RXB : 0000 0000 : mod qwordreg r/m

0100 0RXB : 0000 000w : mod reg r/m

qwordregister to memory64

0100 1RXB : 0000 0011 : mod qwordreg r/m

immediate to register

0100 0000B : 1000 00sw : 11 000 reg : immediate data

immediate32 to qwordregister

0100 100B : 1000 0001 : 11 010 qwordreg : imm

immediate to AL, AX, or EAX

0000 010w : immediate8

immediate to RAX

0100 1000 : 0000 0101 : imm32

immediate to memory

0100 00XB : 1000 00sw : mod 000 r/m : immediate

immediate32 to memory64

0100 10XB : 1000 0001 : mod 010 r/m : imm32

immediate8 to memory64

0100 10XB : 1000 0011 : mod 010 r/m : imm8

AND - Logical AND

register1 to register2

0100 0R0B 0010 000w : 11 reg1 reg2

qwordregister1 to qwordregister2

0100 1R0B 0010 0001 : 11 qwordreg1 qwordreg2

register2 to register1

0100 0R0B 0010 001w : 11 reg1 reg2

register1 to register2

0100 1R0B 0010 0011 : 11 qwordreg1 qwordreg2

memory to register

0100 0RXB 0010 001w : mod reg r/m

memory64 to qwordregister

0100 1RXB : 0010 0011 : mod qwordreg r/m

0100 0RXB : 0010 000w : mod reg r/m

qwordregister to memory64

0100 1RXB : 0010 0001 : mod qwordreg r/m

immediate to register

0100 000B : 1000 00sw : 11 100 reg : immediate

immediate32 to qwordregister

0100 100B 1000 0001 : 11 100 qwordreg : imm32

immediate to AL, AX, or EAX

0010 010w : immediate

immediate32 to RAX

0100 1000 0010 1001 : imm32

immediate to memory

0100 00XB : 1000 00sw : mod 100 r/m : immediate

immediate32 to memory64

0100 10XB : 1000 0001 : mod 100 r/m : immediate32

immediate8 to memory64

0100 10XB : 1000 0011 : mod 100 r/m : imm8

BSF - Bit Scan Forward

Vol. 2D B-19

INSTRUCTION FORMATS AND ENCODINGS

Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)

Instruction and Format

Encoding

register1, register2

0100 0R0B 0000 1111 : 1011 1100 : 11 reg1 reg2

qwordregister1, qwordregister2

0100 1R0B 0000 1111 : 1011 1100 : 11 qwordreg1

qwordreg2

memory, register

0100 0RXB 0000 1111 : 1011 1100 : mod reg r/m

memory64, qwordregister

0100 1RXB 0000 1111 : 1011 1100 : mod qwordreg r/m

BSR - Bit Scan Reverse

register1, register2

0100 0R0B 0000 1111 : 1011 1101 : 11 reg1 reg2

qwordregister1, qwordregister2

0100 1R0B 0000 1111 : 1011 1101 : 11 qwordreg1

qwordreg2

memory, register

0100 0RXB 0000 1111 : 1011 1101 : mod reg r/m

memory64, qwordregister

0100 1RXB 0000 1111 : 1011 1101 : mod qwordreg r/m

BSWAP - Byte Swap

0000 1111 : 1100 1 reg

BSWAP - Byte Swap

0100 100B 0000 1111 : 1100 1 qwordreg

BT - Bit Test

0100 000B 0000 1111 : 1011 1010 : 11 100 reg: imm8

qwordregister, immediate8

0100 100B 1111 : 1011 1010 : 11 100 qwordreg: imm8 data

memory, immediate

0100 00XB 0000 1111 : 1011 1010 : mod 100 r/m : imm8

memory64, immediate8

0100 10XB 0000 1111 : 1011 1010 : mod 100 r/m : imm8 data

register1, register2

0100 0R0B 0000 1111 : 1010 0011 : 11 reg2 reg1

qwordregister1, qwordregister2

0100 1R0B 0000 1111 : 1010 0011 : 11 qwordreg2

qwordreg1

memory, reg

0100 0RXB 0000 1111 : 1010 0011 : mod reg r/m

memory, qwordreg

0100 1RXB 0000 1111 : 1010 0011 : mod qwordreg r/m

BTC - Bit Test and Complement

0100 000B 0000 1111 : 1011 1010 : 11 111 reg: imm8

qwordregister, immediate8

0100 100B 0000 1111 : 1011 1010 : 11 111 qwordreg: imm8

memory, immediate

0100 00XB 0000 1111 : 1011 1010 : mod 111 r/m : imm8

memory64, immediate8

0100 10XB 0000 1111 : 1011 1010 : mod 111 r/m : imm8

register1, register2

0100 0R0B 0000 1111 : 1011 1011 : 11 reg2 reg1

qwordregister1, qwordregister2

0100 1R0B 0000 1111 : 1011 1011 : 11 qwordreg2

qwordreg1

memory, register

0100 0RXB 0000 1111 : 1011 1011 : mod reg r/m

memory, qwordreg

0100 1RXB 0000 1111 : 1011 1011 : mod qwordreg r/m

BTR - Bit Test and Reset

0100 000B 0000 1111 : 1011 1010 : 11 110 reg: imm8

qwordregister, immediate8

0100 100B 0000 1111 : 1011 1010 : 11 110 qwordreg: imm8

memory, immediate

0100 00XB 0000 1111 : 1011 1010 : mod 110 r/m : imm8

memory64, immediate8

0100 10XB 0000 1111 : 1011 1010 : mod 110 r/m : imm8

register1, register2

0100 0R0B 0000 1111 : 1011 0011 : 11 reg2 reg1

B-20

Vol. 2D

INSTRUCTION FORMATS AND ENCODINGS

Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)

Instruction and Format

Encoding

qwordregister1, qwordregister2

0100 1R0B 0000 1111 : 1011 0011 : 11 qwordreg2

qwordreg1

memory, register

0100 0RXB 0000 1111 : 1011 0011 : mod reg r/m

memory64, qwordreg

0100 1RXB 0000 1111 : 1011 0011 : mod qwordreg r/m

BTS - Bit Test and Set

0100 000B 0000 1111 : 1011 1010 : 11 101 reg: imm8

qwordregister, immediate8

0100 100B 0000 1111 : 1011 1010 : 11 101 qwordreg: imm8

memory, immediate

0100 00XB 0000 1111 : 1011 1010 : mod 101 r/m : imm8

memory64, immediate8

0100 10XB 0000 1111 : 1011 1010 : mod 101 r/m : imm8

register1, register2

0100 0R0B 0000 1111 : 1010 1011 : 11 reg2 reg1

qwordregister1, qwordregister2

0100 1R0B 0000 1111 : 1010 1011 : 11 qwordreg2

qwordreg1

memory, register

0100 0RXB 0000 1111 : 1010 1011 : mod reg r/m

memory64, qwordreg

0100 1RXB 0000 1111 : 1010 1011 : mod qwordreg r/m

CALL - Call Procedure (in same segment)

direct

1110 1000 : displacement32

0100 WR00^w 1111 1111 : 11 010 reg

memory indirect

0100 W0XB^w 1111 1111 : mod 010 r/m

CALL - Call Procedure (in other segment)

indirect

1111 1111 : mod 011 r/m

indirect

0100 10XB 0100 1000 1111 1111 : mod 011 r/m

CBW - Convert Byte to Word

1001 1000

CDQ - Convert Doubleword to Qword+

1001 1001

CDQE - RAX, Sign-Extend of EAX

0100 1000 1001 1001

CLC - Clear Carry Flag

1111 1000

CLD - Clear Direction Flag

1111 1100

CLI - Clear Interrupt Flag

1111 1010

CLTS - Clear Task-Switched Flag in CR0

0000 1111 : 0000 0110

CMC - Complement Carry Flag

1111 0101

CMP - Compare Two Operands

register1 with register2

0100 0R0B 0011 100w : 11 reg1 reg2

qwordregister1 with qwordregister2

0100 1R0B 0011 1001 : 11 qwordreg1 qwordreg2

register2 with register1

0100 0R0B 0011 101w : 11 reg1 reg2

qwordregister2 with qwordregister1

0100 1R0B 0011 101w : 11 qwordreg1 qwordreg2

memory with register

0100 0RXB 0011 100w : mod reg r/m

memory64 with qwordregister

0100 1RXB 0011 1001 : mod qwordreg r/m

0100 0RXB 0011 101w : mod reg r/m

qwordregister with memory64

0100 1RXB 0011 101w1 : mod qwordreg r/m

immediate with register

0100 000B 1000 00sw : 11 111 reg : imm

Vol. 2D B-21

INSTRUCTION FORMATS AND ENCODINGS

Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)

Instruction and Format

Encoding

immediate32 with qwordregister

0100 100B 1000 0001 : 11 111 qwordreg : imm64

immediate with AL, AX, or EAX

0011 110w : imm

immediate32 with RAX

0100 1000 0011 1101 : imm32

immediate with memory

0100 00XB 1000 00sw : mod 111 r/m : imm

immediate32 with memory64

0100 1RXB 1000 0001 : mod 111 r/m : imm64

immediate8 with memory64

0100 1RXB 1000 0011 : mod 111 r/m : imm8

CMPS/CMPSB/CMPSW/CMPSD/CMPSQ - Compare String Operands

compare string operands [ X at DS:(E)SI with Y at ES:(E)DI ]

1010 011w

qword at address RSI with qword at address RDI

0100 1000 1010 0111

CMPXCHG - Compare and Exchange

register1, register2

0000 1111 : 1011 000w : 11 reg2 reg1

byteregister1, byteregister2

0100 000B 0000 1111 : 1011 0000 : 11 bytereg2 reg1

qwordregister1, qwordregister2

0100 100B 0000 1111 : 1011 0001 : 11 qwordreg2 reg1

memory, register

0000 1111 : 1011 000w : mod reg r/m

memory8, byteregister

0100 00XB 0000 1111 : 1011 0000 : mod bytereg r/m

memory64, qwordregister

0100 10XB 0000 1111 : 1011 0001 : mod qwordreg r/m

CPUID - CPU Identification

0000 1111 : 1010 0010

CQO - Sign-Extend RAX

0100 1000 1001 1001

CWD - Convert Word to Doubleword

1001 1001

CWDE - Convert Word to Doubleword

1001 1000

DEC - Decrement by 1

0100 000B 1111 111w : 11 001 reg

qwordregister

0100 100B 1111 1111 : 11 001 qwordreg

memory

0100 00XB 1111 111w : mod 001 r/m

memory64

0100 10XB 1111 1111 : mod 001 r/m

DIV - Unsigned Divide

AL, AX, or EAX by register

0100 000B 1111 011w : 11 110 reg

Divide RDX:RAX by qwordregister

0100 100B 1111 0111 : 11 110 qwordreg

AL, AX, or EAX by memory

0100 00XB 1111 011w : mod 110 r/m

Divide RDX:RAX by memory64

0100 10XB 1111 0111 : mod 110 r/m

ENTER - Make Stack Frame for High Level Procedure

1100 1000 : 16-bit displacement : 8-bit level (L)

HLT - Halt

1111 0100

IDIV - Signed Divide

AL, AX, or EAX by register

0100 000B 1111 011w : 11 111 reg

RDX:RAX by qwordregister

0100 100B 1111 0111 : 11 111 qwordreg

AL, AX, or EAX by memory

0100 00XB 1111 011w : mod 111 r/m

RDX:RAX by memory64

0100 10XB 1111 0111 : mod 111 r/m

IMUL - Signed Multiply

B-22

Vol. 2D

INSTRUCTION FORMATS AND ENCODINGS

Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)

Instruction and Format

Encoding

AL, AX, or EAX with register

0100 000B 1111 011w : 11 101 reg

RDX:RAX := RAX with qwordregister

0100 100B 1111 0111 : 11 101 qwordreg

AL, AX, or EAX with memory

0100 00XB 1111 011w : mod 101 r/m

RDX:RAX := RAX with memory64

0100 10XB 1111 0111 : mod 101 r/m

register1 with register2

0000 1111 : 1010 1111 : 11 : reg1 reg2

qwordregister1 := qwordregister1 with qwordregister2

0100 1R0B 0000 1111 : 1010 1111 : 11 : qwordreg1

qwordreg2

0100 0RXB 0000 1111 : 1010 1111 : mod reg r/m

qwordregister := qwordregister with memory64

0100 1RXB 0000 1111 : 1010 1111 : mod qwordreg r/m

register1 with immediate to register2

0100 0R0B 0110 10s1 : 11 reg1 reg2 : imm

qwordregister1 := qwordregister2 with sign-extended

0100 1R0B 0110 1011 : 11 qwordreg1 qwordreg2 : imm8

immediate8

qwordregister1 := qwordregister2 with immediate32

0100 1R0B 0110 1001 : 11 qwordreg1 qwordreg2 : imm32

memory with immediate to register

0100 0RXB 0110 10s1 : mod reg r/m : imm

qwordregister := memory64 with sign-extended immediate8

0100 1RXB 0110 1011 : mod qwordreg r/m : imm8

qwordregister := memory64 with immediate32

0100 1RXB 0110 1001 : mod qwordreg r/m : imm32

IN - Input From Port

fixed port

1110 010w : port number

variable port

1110 110w

INC - Increment by 1

reg

0100 000B 1111 111w : 11 000 reg

qwordreg

0100 100B 1111 1111 : 11 000 qwordreg

memory

0100 00XB 1111 111w : mod 000 r/m

memory64

0100 10XB 1111 1111 : mod 000 r/m

INS - Input from DX Port

0110 110w

INT n - Interrupt Type n

1100 1101 : type

INT - Single-Step Interrupt 3

1100 1100

INTO - Interrupt 4 on Overflow

1100 1110

INVD - Invalidate Cache

0000 1111 : 0000 1000

INVLPG - Invalidate TLB Entry

0000 1111 : 0000 0001 : mod 111 r/m

INVPCID - Invalidate Process-Context Identifier

0110 0110:0000 1111:0011 1000:1000 0010: mod reg r/m

IRETO - Interrupt Return

1100 1111

Jcc - Jump if Condition is Met

8-bit displacement

0111 tttn : 8-bit displacement

displacements (excluding 16-bit relative offsets)

0000 1111 : 1000 tttn : displacement32

JCXZ/JECXZ - Jump on CX/ECX Zero

Address-size prefix differentiates JCXZ and JECXZ

1110 0011 : 8-bit displacement

JMP - Unconditional Jump (to same segment)

short

1110 1011 : 8-bit displacement

Vol. 2D B-23

INSTRUCTION FORMATS AND ENCODINGS

Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)

Instruction and Format

Encoding

direct

1110 1001 : displacement32

0100 W00B^w : 1111 1111 : 11 100 reg

memory indirect

0100 W0XB^w : 1111 1111 : mod 100 r/m

JMP - Unconditional Jump (to other segment)

indirect intersegment

0100 00XB : 1111 1111 : mod 101 r/m

64-bit indirect intersegment

0100 10XB : 1111 1111 : mod 101 r/m

LAR - Load Access Rights Byte

from register

0100 0R0B : 0000 1111 : 0000 0010 : 11 reg1 reg2

from dwordregister to qwordregister, masked by 00FxFF00H

0100 WR0B : 0000 1111 : 0000 0010 : 11 qwordreg1

dwordreg2

from memory

0100 0RXB : 0000 1111 : 0000 0010 : mod reg r/m

from memory32 to qwordregister, masked by 00FxFF00H

0100 WRXB 0000 1111 : 0000 0010 : mod r/m

LEA - Load Effective Address

in wordregister/dwordregister

0100 0RXB : 1000 1101 : mod^A reg r/m

in qwordregister

0100 1RXB : 1000 1101 : mod^A qwordreg r/m

LEAVE - High Level Procedure Exit

1100 1001

LFS - Load Pointer to FS

FS:r16/r32 with far pointer from memory

0100 0RXB : 0000 1111 : 1011 0100 : mod^A reg r/m

FS:r64 with far pointer from memory

0100 1RXB : 0000 1111 : 1011 0100 : mod^A qwordreg r/m

LGDT - Load Global Descriptor Table Register

0100 10XB : 0000 1111 : 0000 0001 : mod^A 010 r/m

LGS - Load Pointer to GS

GS:r16/r32 with far pointer from memory

0100 0RXB : 0000 1111 : 1011 0101 : mod^A reg r/m

GS:r64 with far pointer from memory

0100 1RXB : 0000 1111 : 1011 0101 : mod^A qwordreg r/m

LIDT - Load Interrupt Descriptor Table Register

0100 10XB : 0000 1111 : 0000 0001 : mod^A 011 r/m

LLDT - Load Local Descriptor Table Register

LDTR from register

0100 000B : 0000 1111 : 0000 0000 : 11 010 reg

LDTR from memory

0100 00XB :0000 1111 : 0000 0000 : mod 010 r/m

LMSW - Load Machine Status Word

from register

0100 000B : 0000 1111 : 0000 0001 : 11 110 reg

from memory

0100 00XB :0000 1111 : 0000 0001 : mod 110 r/m

LOCK - Assert LOCK# Signal Prefix

1111 0000

LODS/LODSB/LODSW/LODSD/LODSQ - Load String Operand

at DS:(E)SI to AL/EAX/EAX

1010 110w

at (R)SI to RAX

0100 1000 1010 1101

LOOP - Loop Count

if count ≠ 0, 8-bit displacement

1110 0010

if count ≠ 0, RIP + 8-bit displacement sign-extended to 64-bits

0100 1000 1110 0010

LOOPE - Loop Count while Zero/Equal

B-24

Vol. 2D

INSTRUCTION FORMATS AND ENCODINGS

Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)

Instruction and Format

Encoding

if count ≠ 0 & ZF =1, 8-bit displacement

1110 0001

if count ≠ 0 & ZF = 1, RIP + 8-bit displacement sign-extended to

0100 1000 1110 0001

64-bits

LOOPNE/LOOPNZ - Loop Count while not Zero/Equal

if count ≠ 0 & ZF = 0, 8-bit displacement

1110 0000

if count ≠ 0 & ZF = 0, RIP + 8-bit displacement sign-extended to

0100 1000 1110 0000

64-bits

LSL - Load Segment Limit

from register

0000 1111 : 0000 0011 : 11 reg1 reg2

from qwordregister

0100 1R00 0000 1111 : 0000 0011 : 11 qwordreg1 reg2

from memory16

0000 1111 : 0000 0011 : mod reg r/m

from memory64

0100 1RXB 0000 1111 : 0000 0011 : mod qwordreg r/m

LSS - Load Pointer to SS

SS:r16/r32 with far pointer from memory

0100 0RXB : 0000 1111 : 1011 0010 : mod^A reg r/m

SS:r64 with far pointer from memory

0100 1WXB : 0000 1111 : 1011 0010 : mod^A qwordreg r/m

LTR - Load Task Register

from register

0100 0R00 : 0000 1111 : 0000 0000 : 11 011 reg

from memory

0100 00XB : 0000 1111 : 0000 0000 : mod 011 r/m

MOV - Move Data

register1 to register2

0100 0R0B : 1000 100w : 11 reg1 reg2

qwordregister1 to qwordregister2

0100 1R0B 1000 1001 : 11 qwordeg1 qwordreg2

register2 to register1

0100 0R0B : 1000 101w : 11 reg1 reg2

qwordregister2 to qwordregister1

0100 1R0B 1000 1011 : 11 qwordreg1 qwordreg2

memory to reg

0100 0RXB : 1000 101w : mod reg r/m

memory64 to qwordregister

0100 1RXB 1000 1011 : mod qwordreg r/m

reg to memory

0100 0RXB : 1000 100w : mod reg r/m

qwordregister to memory64

0100 1RXB 1000 1001 : mod qwordreg r/m

immediate to register

0100 000B : 1100 011w : 11 000 reg : imm

immediate32 to qwordregister (zero extend)

0100 100B 1100 0111 : 11 000 qwordreg : imm32

immediate to register (alternate encoding)

0100 000B : 1011 w reg : imm

immediate64 to qwordregister (alternate encoding)

0100 100B 1011 1000 reg : imm64

immediate to memory

0100 00XB : 1100 011w : mod 000 r/m : imm

immediate32 to memory64 (zero extend)

0100 10XB 1100 0111 : mod 000 r/m : imm32

memory to AL, AX, or EAX

0100 0000 : 1010 000w : displacement

memory64 to RAX

0100 1000 1010 0001 : displacement64

AL, AX, or EAX to memory

0100 0000 : 1010 001w : displacement

RAX to memory64

0100 1000 1010 0011 : displacement64

MOV - Move to/from Control Registers

CR0-CR4 from register

0100 0R0B : 0000 1111 : 0010 0010 : 11 eee reg (eee = CR#)

Vol. 2D B-25

INSTRUCTION FORMATS AND ENCODINGS

Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)

Instruction and Format

Encoding

CRx from qwordregister

0100 1R0B : 0000 1111 : 0010 0010 : 11 eee qwordreg (Reee

= CR#)

0100 0R0B : 0000 1111 : 0010 0000 : 11 eee reg (eee = CR#)

qwordregister from CRx

0100 1R0B 0000 1111 : 0010 0000 : 11 eee qwordreg

(Reee = CR#)

MOV - Move to/from Debug Registers

DR0-DR7 from register

0000 1111 : 0010 0011 : 11 eee reg (eee = DR#)

DR0-DR7 from quadregister

0100 10OB 0000 1111 : 0010 0011 : 11 eee reg (eee = DR#)

0000 1111 : 0010 0001 : 11 eee reg (eee = DR#)

quadregister from DR0-DR7

0100 10OB 0000 1111 : 0010 0001 : 11 eee quadreg (eee =

DR#)

MOV - Move to/from Segment Registers

0100 W00B^w : 1000 1110 : 11 sreg reg

0100 000B : 1000 1110 : 11 sreg reg

memory to segment register

0100 00XB : 1000 1110 : mod sreg r/m

memory64 to segment register (lower 16 bits)

0100 10XB 1000 1110 : mod sreg r/m

memory to SS

0100 00XB : 1000 1110 : mod sreg r/m

segment register to register

0100 000B : 1000 1100 : 11 sreg reg

segment register to qwordregister (zero extended)

0100 100B 1000 1100 : 11 sreg qwordreg

segment register to memory

0100 00XB : 1000 1100 : mod sreg r/m

segment register to memory64 (zero extended)

0100 10XB 1000 1100 : mod sreg3 r/m

MOVBE - Move data after swapping bytes

memory to register

0100 0RXB : 0000 1111 : 0011 1000:1111 0000 : mod reg r/m

memory64 to qwordregister

0100 1RXB : 0000 1111 : 0011 1000:1111 0000 : mod reg r/m

0100 0RXB :0000 1111 : 0011 1000:1111 0001 : mod reg r/m

qwordregister to memory64

0100 1RXB :0000 1111 : 0011 1000:1111 0001 : mod reg r/m

MOVS/MOVSB/MOVSW/MOVSD/MOVSQ - Move Data from String to String

Move data from string to string

1010 010w

Move data from string to string (qword)

0100 1000 1010 0101

MOVSX/MOVSXD - Move with Sign-Extend

register2 to register1

0100 0R0B : 0000 1111 : 1011 111w : 11 reg1 reg2

byteregister2 to qwordregister1 (sign-extend)

0100 1R0B 0000 1111 : 1011 1110 : 11 quadreg1 bytereg2

wordregister2 to qwordregister1

0100 1R0B 0000 1111 : 1011 1111 : 11 quadreg1 wordreg2

dwordregister2 to qwordregister1

0100 1R0B 0110 0011 : 11 quadreg1 dwordreg2

memory to register

0100 0RXB : 0000 1111 : 1011 111w : mod reg r/m

memory8 to qwordregister (sign-extend)

0100 1RXB 0000 1111 : 1011 1110 : mod qwordreg r/m

memory16 to qwordregister

0100 1RXB 0000 1111 : 1011 1111 : mod qwordreg r/m

memory32 to qwordregister

0100 1RXB 0110 0011 : mod qwordreg r/m

MOVZX - Move with Zero-Extend

B-26

Vol. 2D

INSTRUCTION FORMATS AND ENCODINGS

Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)

Instruction and Format

Encoding

register2 to register1

0100 0R0B : 0000 1111 : 1011 011w : 11 reg1 reg2

dwordregister2 to qwordregister1

0100 1R0B 0000 1111 : 1011 0111 : 11 qwordreg1

dwordreg2

memory to register

0100 0RXB : 0000 1111 : 1011 011w : mod reg r/m

memory32 to qwordregister

0100 1RXB 0000 1111 : 1011 0111 : mod qwordreg r/m

MUL - Unsigned Multiply

AL, AX, or EAX with register

0100 000B : 1111 011w : 11 100 reg

RAX with qwordregister (to RDX:RAX)

0100 100B 1111 0111 : 11 100 qwordreg

AL, AX, or EAX with memory

0100 00XB 1111 011w : mod 100 r/m

RAX with memory64 (to RDX:RAX)

0100 10XB 1111 0111 : mod 100 r/m

NEG - Two's Complement Negation

0100 000B : 1111 011w : 11 011 reg

qwordregister

0100 100B 1111 0111 : 11 011 qwordreg

memory

0100 00XB : 1111 011w : mod 011 r/m

memory64

0100 10XB 1111 0111 : mod 011 r/m

NOP - No Operation

1001 0000

NOT - One's Complement Negation

0100 000B : 1111 011w : 11 010 reg

qwordregister

0100 000B 1111 0111 : 11 010 qwordreg

memory

0100 00XB : 1111 011w : mod 010 r/m

memory64

0100 1RXB 1111 0111 : mod 010 r/m

OR - Logical Inclusive OR

register1 to register2

0000 100w : 11 reg1 reg2

byteregister1 to byteregister2

0100 0R0B 0000 1000 : 11 bytereg1 bytereg2

qwordregister1 to qwordregister2

0100 1R0B 0000 1001 : 11 qwordreg1 qwordreg2

register2 to register1

0000 101w : 11 reg1 reg2

byteregister2 to byteregister1

0100 0R0B 0000 1010 : 11 bytereg1 bytereg2

qwordregister2 to qwordregister1

0100 0R0B 0000 1011 : 11 qwordreg1 qwordreg2

memory to register

0000 101w : mod reg r/m

memory8 to byteregister

0100 0RXB 0000 1010 : mod bytereg r/m

memory8 to qwordregister

0100 0RXB 0000 1011 : mod qwordreg r/m

0000 100w : mod reg r/m

byteregister to memory8

0100 0RXB 0000 1000 : mod bytereg r/m

qwordregister to memory64

0100 1RXB 0000 1001 : mod qwordreg r/m

immediate to register

1000 00sw : 11 001 reg : imm

immediate8 to byteregister

0100 000B 1000 0000 : 11 001 bytereg : imm8

immediate32 to qwordregister

0100 000B 1000 0001 : 11 001 qwordreg : imm32

immediate8 to qwordregister

0100 000B 1000 0011 : 11 001 qwordreg : imm8

immediate to AL, AX, or EAX

0000 110w : imm

Vol. 2D

B-27

INSTRUCTION FORMATS AND ENCODINGS

Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)

Instruction and Format

Encoding

immediate64 to RAX

0100 1000 0000 1101 : imm64

immediate to memory

1000 00sw : mod 001 r/m : imm

immediate8 to memory8

0100 00XB 1000 0000 : mod 001 r/m : imm8

immediate32 to memory64

0100 00XB 1000 0001 : mod 001 r/m : imm32

immediate8 to memory64

0100 00XB 1000 0011 : mod 001 r/m : imm8

OUT - Output to Port

fixed port

1110 011w : port number

variable port

1110 111w

OUTS - Output to DX Port

output to DX Port

0110 111w

POP - Pop a Value from the Stack

wordregister

0101 0101 : 0100 000B : 1000 1111 : 11 000 reg16

qwordregister

0100 W00B^S : 1000 1111 : 11 000 reg64

wordregister (alternate encoding)

0101 0101 : 0100 000B : 0101 1 reg16

qwordregister (alternate encoding)

0100 W00B : 0101 1 reg64

memory64

0100 W0XB^S : 1000 1111 : mod 000 r/m

memory16

0101 0101 : 0100 00XB 1000 1111 : mod 000 r/m

POP - Pop a Segment Register from the Stack

(Note: CS cannot be sreg2 in this usage.)

segment register FS, GS

0000 1111: 10 sreg3 001

POPF/POPFQ - Pop Stack into FLAGS/RFLAGS Register

pop stack to FLAGS register

0101 0101 : 1001 1101

pop Stack to RFLAGS register

0100 1000 1001 1101

PUSH - Push Operand onto the Stack

wordregister

0101 0101 : 0100 000B : 1111 1111 : 11 110 reg16

qwordregister

0100 W00B^S : 1111 1111 : 11 110 reg64

wordregister (alternate encoding)

0101 0101 : 0100 000B : 0101 0 reg16

qwordregister (alternate encoding)

0100 W00B^S : 0101 0 reg64

memory16

0101 0101 : 0100 000B : 1111 1111 : mod 110 r/m

memory64

0100 W00B^S : 1111 1111 : mod 110 r/m

immediate8

0110 1010 : imm8

immediate16

0101 0101 : 0110 1000 : imm16

immediate64

0110 1000 : imm64

PUSH - Push Segment Register onto the Stack

segment register FS,GS

0000 1111: 10 sreg3 000

PUSHF/PUSHFD - Push Flags Register onto the Stack

1001 1100

RCL - Rotate thru Carry Left

0100 000B : 1101 000w : 11 010 reg

qwordregister by 1

0100 100B 1101 0001 : 11 010 qwordreg

B-28

Vol. 2D

INSTRUCTION FORMATS AND ENCODINGS

Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)

Instruction and Format

Encoding

memory by 1

0100 00XB : 1101 000w : mod 010 r/m

memory64 by 1

0100 10XB 1101 0001 : mod 010 r/m

0100 000B : 1101 001w : 11 010 reg

qwordregister by CL

0100 100B 1101 0011 : 11 010 qwordreg

memory by CL

0100 00XB : 1101 001w : mod 010 r/m

memory64 by CL

0100 10XB 1101 0011 : mod 010 r/m

0100 000B : 1100 000w : 11 010 reg : imm

qwordregister by immediate count

0100 100B 1100 0001 : 11 010 qwordreg : imm8

memory by immediate count

0100 00XB : 1100 000w : mod 010 r/m : imm

memory64 by immediate count

0100 10XB 1100 0001 : mod 010 r/m : imm8

RCR - Rotate thru Carry Right

0100 000B : 1101 000w : 11 011 reg

qwordregister by 1

0100 100B 1101 0001 : 11 011 qwordreg

memory by 1

0100 00XB : 1101 000w : mod 011 r/m

memory64 by 1

0100 10XB 1101 0001 : mod 011 r/m

0100 000B : 1101 001w : 11 011 reg

qwordregister by CL

0100 000B 1101 0010 : 11 011 qwordreg

memory by CL

0100 00XB : 1101 001w : mod 011 r/m

memory64 by CL

0100 10XB 1101 0011 : mod 011 r/m

0100 000B : 1100 000w : 11 011 reg : imm8

qwordregister by immediate count

0100 100B 1100 0001 : 11 011 qwordreg : imm8

memory by immediate count

0100 00XB : 1100 000w : mod 011 r/m : imm8

memory64 by immediate count

0100 10XB 1100 0001 : mod 011 r/m : imm8

RDMSR - Read from Model-Specific Register

load ECX-specified register into EDX:EAX

0000 1111 : 0011 0010

RDPMC - Read Performance Monitoring Counters

load ECX-specified performance counter into EDX:EAX

0000 1111 : 0011 0011

RDTSC - Read Time-Stamp Counter

read time-stamp counter into EDX:EAX

0000 1111 : 0011 0001

RDTSCP - Read Time-Stamp Counter and Processor ID

0000 1111 : 0000 0001: 1111 1001

REP INS - Input String

REP LODS - Load String

REP MOVS - Move String

REP OUTS - Output String

REP STOS - Store String

REPE CMPS - Compare String

REPE SCAS - Scan String

REPNE CMPS - Compare String

Vol. 2D B-29

INSTRUCTION FORMATS AND ENCODINGS

Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)

Instruction and Format

Encoding

REPNE SCAS - Scan String

RET - Return from Procedure (to same segment)

no argument

1100 0011

adding immediate to SP

1100 0010 : 16-bit displacement

RET - Return from Procedure (to other segment)

intersegment

1100 1011

adding immediate to SP

1100 1010 : 16-bit displacement

ROL - Rotate Left

0100 000B 1101 000w : 11 000 reg

byteregister by 1

0100 000B 1101 0000 : 11 000 bytereg

qwordregister by 1

0100 100B 1101 0001 : 11 000 qwordreg

memory by 1

0100 00XB 1101 000w : mod 000 r/m

memory8 by 1

0100 00XB 1101 0000 : mod 000 r/m

memory64 by 1

0100 10XB 1101 0001 : mod 000 r/m

0100 000B 1101 001w : 11 000 reg

byteregister by CL

0100 000B 1101 0010 : 11 000 bytereg

qwordregister by CL

0100 100B 1101 0011 : 11 000 qwordreg

memory by CL

0100 00XB 1101 001w : mod 000 r/m

memory8 by CL

0100 00XB 1101 0010 : mod 000 r/m

memory64 by CL

0100 10XB 1101 0011 : mod 000 r/m

1100 000w : 11 000 reg : imm8

byteregister by immediate count

0100 000B 1100 0000 : 11 000 bytereg : imm8

qwordregister by immediate count

0100 100B 1100 0001 : 11 000 bytereg : imm8

memory by immediate count

1100 000w : mod 000 r/m : imm8

memory8 by immediate count

0100 00XB 1100 0000 : mod 000 r/m : imm8

memory64 by immediate count

0100 10XB 1100 0001 : mod 000 r/m : imm8

ROR - Rotate Right

0100 000B 1101 000w : 11 001 reg

byteregister by 1

0100 000B 1101 0000 : 11 001 bytereg

qwordregister by 1

0100 100B 1101 0001 : 11 001 qwordreg

memory by 1

0100 00XB 1101 000w : mod 001 r/m

memory8 by 1

0100 00XB 1101 0000 : mod 001 r/m

memory64 by 1

0100 10XB 1101 0001 : mod 001 r/m

0100 000B 1101 001w : 11 001 reg

byteregister by CL

0100 000B 1101 0010 : 11 001 bytereg

qwordregister by CL

0100 100B 1101 0011 : 11 001 qwordreg

memory by CL

0100 00XB 1101 001w : mod 001 r/m

memory8 by CL

0100 00XB 1101 0010 : mod 001 r/m

B-30

Vol. 2D

INSTRUCTION FORMATS AND ENCODINGS

Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)

Instruction and Format

Encoding

memory64 by CL

0100 10XB 1101 0011 : mod 001 r/m

0100 000B 1100 000w : 11 001 reg : imm8

byteregister by immediate count

0100 000B 1100 0000 : 11 001 reg : imm8

qwordregister by immediate count

0100 100B 1100 0001 : 11 001 qwordreg : imm8

memory by immediate count

0100 00XB 1100 000w : mod 001 r/m : imm8

memory8 by immediate count

0100 00XB 1100 0000 : mod 001 r/m : imm8

memory64 by immediate count

0100 10XB 1100 0001 : mod 001 r/m : imm8

RSM - Resume from System Management Mode

0000 1111 : 1010 1010

SAL - Shift Arithmetic Left

same instruction as SHL

SAR - Shift Arithmetic Right

0100 000B 1101 000w : 11 111 reg

byteregister by 1

0100 000B 1101 0000 : 11 111 bytereg

qwordregister by 1

0100 100B 1101 0001 : 11 111 qwordreg

memory by 1

0100 00XB 1101 000w : mod 111 r/m

memory8 by 1

0100 00XB 1101 0000 : mod 111 r/m

memory64 by 1

0100 10XB 1101 0001 : mod 111 r/m

0100 000B 1101 001w : 11 111 reg

byteregister by CL

0100 000B 1101 0010 : 11 111 bytereg

qwordregister by CL

0100 100B 1101 0011 : 11 111 qwordreg

memory by CL

0100 00XB 1101 001w : mod 111 r/m

memory8 by CL

0100 00XB 1101 0010 : mod 111 r/m

memory64 by CL

0100 10XB 1101 0011 : mod 111 r/m

0100 000B 1100 000w : 11 111 reg : imm8

byteregister by immediate count

0100 000B 1100 0000 : 11 111 bytereg : imm8

qwordregister by immediate count

0100 100B 1100 0001 : 11 111 qwordreg : imm8

memory by immediate count

0100 00XB 1100 000w : mod 111 r/m : imm8

memory8 by immediate count

0100 00XB 1100 0000 : mod 111 r/m : imm8

memory64 by immediate count

0100 10XB 1100 0001 : mod 111 r/m : imm8

SBB - Integer Subtraction with Borrow

register1 to register2

0100 0R0B 0001 100w : 11 reg1 reg2

byteregister1 to byteregister2

0100 0R0B 0001 1000 : 11 bytereg1 bytereg2

quadregister1 to quadregister2

0100 1R0B 0001 1001 : 11 quadreg1 quadreg2

register2 to register1

0100 0R0B 0001 101w : 11 reg1 reg2

byteregister2 to byteregister1

0100 0R0B 0001 1010 : 11 reg1 bytereg2

byteregister2 to byteregister1

0100 1R0B 0001 1011 : 11 reg1 bytereg2

memory to register

0100 0RXB 0001 101w : mod reg r/m

memory8 to byteregister

0100 0RXB 0001 1010 : mod bytereg r/m

memory64 to byteregister

0100 1RXB 0001 1011 : mod quadreg r/m

Vol. 2D B-31

INSTRUCTION FORMATS AND ENCODINGS

Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)

Instruction and Format

Encoding

0100 0RXB 0001 100w : mod reg r/m

byteregister to memory8

0100 0RXB 0001 1000 : mod reg r/m

quadregister to memory64

0100 1RXB 0001 1001 : mod reg r/m

immediate to register

0100 000B 1000 00sw : 11 011 reg : imm

immediate8 to byteregister

0100 000B 1000 0000 : 11 011 bytereg : imm8

immediate32 to qwordregister

0100 100B 1000 0001 : 11 011 qwordreg : imm32

immediate8 to qwordregister

0100 100B 1000 0011 : 11 011 qwordreg : imm8

immediate to AL, AX, or EAX

0100 000B 0001 110w : imm

immediate32 to RAL

0100 1000 0001 1101 : imm32

immediate to memory

0100 00XB 1000 00sw : mod 011 r/m : imm

immediate8 to memory8

0100 00XB 1000 0000 : mod 011 r/m : imm8

immediate32 to memory64

0100 10XB 1000 0001 : mod 011 r/m : imm32

immediate8 to memory64

0100 10XB 1000 0011 : mod 011 r/m : imm8

SCAS/SCASB/SCASW/SCASD - Scan String

scan string

1010 111w

scan string (compare AL with byte at RDI)

0100 1000 1010 1110

scan string (compare RAX with qword at RDI)

0100 1000 1010 1111

SETcc - Byte Set on Condition

0100 000B 0000 1111 : 1001 tttn : 11 000 reg

0100 0000 0000 1111 : 1001 tttn : 11 000 reg

memory

0100 00XB 0000 1111 : 1001 tttn : mod 000 r/m

memory

0100 0000 0000 1111 : 1001 tttn : mod 000 r/m

SGDT - Store Global Descriptor Table Register

0000 1111 : 0000 0001 : mod^A 000 r/m

SHL - Shift Left

0100 000B 1101 000w : 11 100 reg

byteregister by 1

0100 000B 1101 0000 : 11 100 bytereg

qwordregister by 1

0100 100B 1101 0001 : 11 100 qwordreg

memory by 1

0100 00XB 1101 000w : mod 100 r/m

memory8 by 1

0100 00XB 1101 0000 : mod 100 r/m

memory64 by 1

0100 10XB 1101 0001 : mod 100 r/m

0100 000B 1101 001w : 11 100 reg

byteregister by CL

0100 000B 1101 0010 : 11 100 bytereg

qwordregister by CL

0100 100B 1101 0011 : 11 100 qwordreg

memory by CL

0100 00XB 1101 001w : mod 100 r/m

memory8 by CL

0100 00XB 1101 0010 : mod 100 r/m

memory64 by CL

0100 10XB 1101 0011 : mod 100 r/m

0100 000B 1100 000w : 11 100 reg : imm8

byteregister by immediate count

0100 000B 1100 0000 : 11 100 bytereg : imm8

B-32

Vol. 2D

INSTRUCTION FORMATS AND ENCODINGS

Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)

Instruction and Format

Encoding

quadregister by immediate count

0100 100B 1100 0001 : 11 100 quadreg : imm8

memory by immediate count

0100 00XB 1100 000w : mod 100 r/m : imm8

memory8 by immediate count

0100 00XB 1100 0000 : mod 100 r/m : imm8

memory64 by immediate count

0100 10XB 1100 0001 : mod 100 r/m : imm8

SHLD - Double Precision Shift Left

0100 0R0B 0000 1111 : 1010 0100 : 11 reg2 reg1 : imm8

qwordregister by immediate8

0100 1R0B 0000 1111 : 1010 0100 : 11 qworddreg2

qwordreg1 : imm8

memory by immediate count

0100 0RXB 0000 1111 : 1010 0100 : mod reg r/m : imm8

memory64 by immediate8

0100 1RXB 0000 1111 : 1010 0100 : mod qwordreg r/m :

imm8

0100 0R0B 0000 1111 : 1010 0101 : 11 reg2 reg1

quadregister by CL

0100 1R0B 0000 1111 : 1010 0101 : 11 quadreg2 quadreg1

memory by CL

0100 00XB 0000 1111 : 1010 0101 : mod reg r/m

memory64 by CL

0100 1RXB 0000 1111 : 1010 0101 : mod quadreg r/m

SHR - Shift Right

0100 000B 1101 000w : 11 101 reg

byteregister by 1

0100 000B 1101 0000 : 11 101 bytereg

qwordregister by 1

0100 100B 1101 0001 : 11 101 qwordreg

memory by 1

0100 00XB 1101 000w : mod 101 r/m

memory8 by 1

0100 00XB 1101 0000 : mod 101 r/m

memory64 by 1

0100 10XB 1101 0001 : mod 101 r/m

0100 000B 1101 001w : 11 101 reg

byteregister by CL

0100 000B 1101 0010 : 11 101 bytereg

qwordregister by CL

0100 100B 1101 0011 : 11 101 qwordreg

memory by CL

0100 00XB 1101 001w : mod 101 r/m

memory8 by CL

0100 00XB 1101 0010 : mod 101 r/m

memory64 by CL

0100 10XB 1101 0011 : mod 101 r/m

0100 000B 1100 000w : 11 101 reg : imm8

byteregister by immediate count

0100 000B 1100 0000 : 11 101 reg : imm8

qwordregister by immediate count

0100 100B 1100 0001 : 11 101 reg : imm8

memory by immediate count

0100 00XB 1100 000w : mod 101 r/m : imm8

memory8 by immediate count

0100 00XB 1100 0000 : mod 101 r/m : imm8

memory64 by immediate count

0100 10XB 1100 0001 : mod 101 r/m : imm8

SHRD - Double Precision Shift Right

0100 0R0B 0000 1111 : 1010 1100 : 11 reg2 reg1 : imm8

qwordregister by immediate8

0100 1R0B 0000 1111 : 1010 1100 : 11 qwordreg2

qwordreg1 : imm8

memory by immediate count

0100 00XB 0000 1111 : 1010 1100 : mod reg r/m : imm8

Vol. 2D B-33

INSTRUCTION FORMATS AND ENCODINGS

Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)

Instruction and Format

Encoding

memory64 by immediate8

0100 1RXB 0000 1111 : 1010 1100 : mod qwordreg r/m :

imm8

0100 000B 0000 1111 : 1010 1101 : 11 reg2 reg1

qwordregister by CL

0100 1R0B 0000 1111 : 1010 1101 : 11 qwordreg2

qwordreg1

memory by CL

0000 1111 : 1010 1101 : mod reg r/m

memory64 by CL

0100 1RXB 0000 1111 : 1010 1101 : mod qwordreg r/m

SIDT - Store Interrupt Descriptor Table Register

0000 1111 : 0000 0001 : mod^A 001 r/m

SLDT - Store Local Descriptor Table Register

to register

0100 000B 0000 1111 : 0000 0000 : 11 000 reg

to memory

0100 00XB 0000 1111 : 0000 0000 : mod 000 r/m

SMSW - Store Machine Status Word

to register

0100 000B 0000 1111 : 0000 0001 : 11 100 reg

to memory

0100 00XB 0000 1111 : 0000 0001 : mod 100 r/m

STC - Set Carry Flag

1111 1001

STD - Set Direction Flag

1111 1101

STI - Set Interrupt Flag

1111 1011

STOS/STOSB/STOSW/STOSD/STOSQ - Store String Data

store string data

1010 101w

store string data (RAX at address RDI)

0100 1000 1010 1011

STR - Store Task Register

to register

0100 000B 0000 1111 : 0000 0000 : 11 001 reg

to memory

0100 00XB 0000 1111 : 0000 0000 : mod 001 r/m

SUB - Integer Subtraction

register1 from register2

0100 0R0B 0010 100w : 11 reg1 reg2

byteregister1 from byteregister2

0100 0R0B 0010 1000 : 11 bytereg1 bytereg2

qwordregister1 from qwordregister2

0100 1R0B 0010 1000 : 11 qwordreg1 qwordreg2

register2 from register1

0100 0R0B 0010 101w : 11 reg1 reg2

byteregister2 from byteregister1

0100 0R0B 0010 1010 : 11 bytereg1 bytereg2

qwordregister2 from qwordregister1

0100 1R0B 0010 1011 : 11 qwordreg1 qwordreg2

memory from register

0100 00XB 0010 101w : mod reg r/m

memory8 from byteregister

0100 0RXB 0010 1010 : mod bytereg r/m

memory64 from qwordregister

0100 1RXB 0010 1011 : mod qwordreg r/m

0100 0RXB 0010 100w : mod reg r/m

byteregister from memory8

0100 0RXB 0010 1000 : mod bytereg r/m

qwordregister from memory8

0100 1RXB 0010 1000 : mod qwordreg r/m

immediate from register

0100 000B 1000 00sw : 11 101 reg : imm

immediate8 from byteregister

0100 000B 1000 0000 : 11 101 bytereg : imm8

immediate32 from qwordregister

0100 100B 1000 0001 : 11 101 qwordreg : imm32

B-34

Vol. 2D

INSTRUCTION FORMATS AND ENCODINGS

Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)

Instruction and Format

Encoding

immediate8 from qwordregister

0100 100B 1000 0011 : 11 101 qwordreg : imm8

immediate from AL, AX, or EAX

0100 000B 0010 110w : imm

immediate32 from RAX

0100 1000 0010 1101 : imm32

immediate from memory

0100 00XB 1000 00sw : mod 101 r/m : imm

immediate8 from memory8

0100 00XB 1000 0000 : mod 101 r/m : imm8

immediate32 from memory64

0100 10XB 1000 0001 : mod 101 r/m : imm32

immediate8 from memory64

0100 10XB 1000 0011 : mod 101 r/m : imm8

SWAPGS - Swap GS Base Register

Exchanges the current GS base register value for value in MSR

0000 1111 0000 0001 1111 1000

C0000102H

SYSCALL - Fast System Call

fast call to privilege level 0 system procedures

0000 1111 0000 0101

SYSRET - Return From Fast System Call

return from fast system call

0000 1111 0000 0111

TEST - Logical Compare

register1 and register2

0100 0R0B 1000 010w : 11 reg1 reg2

byteregister1 and byteregister2

0100 0R0B 1000 0100 : 11 bytereg1 bytereg2

qwordregister1 and qwordregister2

0100 1R0B 1000 0101 : 11 qwordreg1 qwordreg2

memory and register

0100 0R0B 1000 010w : mod reg r/m

memory8 and byteregister

0100 0RXB 1000 0100 : mod bytereg r/m

memory64 and qwordregister

0100 1RXB 1000 0101 : mod qwordreg r/m

immediate and register

0100 000B 1111 011w : 11 000 reg : imm

immediate8 and byteregister

0100 000B 1111 0110 : 11 000 bytereg : imm8

immediate32 and qwordregister

0100 100B 1111 0111 : 11 000 bytereg : imm8

immediate and AL, AX, or EAX

0100 000B 1010 100w : imm

immediate32 and RAX

0100 1000 1010 1001 : imm32

immediate and memory

0100 00XB 1111 011w : mod 000 r/m : imm

immediate8 and memory8

0100 1000 1111 0110 : mod 000 r/m : imm8

immediate32 and memory64

0100 1000 1111 0111 : mod 000 r/m : imm32

UD2 - Undefined instruction

0000 FFFF : 0000 1011

VERR - Verify a Segment for Reading

0100 000B 0000 1111 : 0000 0000 : 11 100 reg

memory

0100 00XB 0000 1111 : 0000 0000 : mod 100 r/m

VERW - Verify a Segment for Writing

0100 000B 0000 1111 : 0000 0000 : 11 101 reg

memory

0100 00XB 0000 1111 : 0000 0000 : mod 101 r/m

WAIT - Wait

1001 1011

WBINVD - Writeback and Invalidate Data Cache

0000 1111 : 0000 1001

Vol. 2D

B-35

INSTRUCTION FORMATS AND ENCODINGS

Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)

Instruction and Format

Encoding

WRMSR - Write to Model-Specific Register

write EDX:EAX to ECX specified MSR

0000 1111 : 0011 0000

write RDX[31:0]:RAX[31:0] to RCX specified MSR

0100 1000 0000 1111 : 0011 0000

XADD - Exchange and Add

register1, register2

0100 0R0B 0000 1111 : 1100 000w : 11 reg2 reg1

byteregister1, byteregister2

0100 0R0B 0000 1111 : 1100 0000 : 11 bytereg2 bytereg1

qwordregister1, qwordregister2

0100 0R0B 0000 1111 : 1100 0001 : 11 qwordreg2

qwordreg1

memory, register

0100 0RXB 0000 1111 : 1100 000w : mod reg r/m

memory8, bytereg

0100 1RXB 0000 1111 : 1100 0000 : mod bytereg r/m

memory64, qwordreg

0100 1RXB 0000 1111 : 1100 0001 : mod qwordreg r/m

XCHG - Exchange Register/Memory with Register

register1 with register2

1000 011w : 11 reg1 reg2

AX or EAX with register

1001 0 reg

memory with register

1000 011w : mod reg r/m

XLAT/XLATB - Table Look-up Translation

AL to byte DS:[(E)BX + unsigned AL]

1101 0111

AL to byte DS:[RBX + unsigned AL]

0100 1000 1101 0111

XOR - Logical Exclusive OR

register1 to register2

0100 0RXB 0011 000w : 11 reg1 reg2

byteregister1 to byteregister2

0100 0R0B 0011 0000 : 11 bytereg1 bytereg2

qwordregister1 to qwordregister2

0100 1R0B 0011 0001 : 11 qwordreg1 qwordreg2

register2 to register1

0100 0R0B 0011 001w : 11 reg1 reg2

byteregister2 to byteregister1

0100 0R0B 0011 0010 : 11 bytereg1 bytereg2

qwordregister2 to qwordregister1

0100 1R0B 0011 0011 : 11 qwordreg1 qwordreg2

memory to register

0100 0RXB 0011 001w : mod reg r/m

memory8 to byteregister

0100 0RXB 0011 0010 : mod bytereg r/m

memory64 to qwordregister

0100 1RXB 0011 0011 : mod qwordreg r/m

0100 0RXB 0011 000w : mod reg r/m

byteregister to memory8

0100 0RXB 0011 0000 : mod bytereg r/m

qwordregister to memory8

0100 1RXB 0011 0001 : mod qwordreg r/m

immediate to register

0100 000B 1000 00sw : 11 110 reg : imm

immediate8 to byteregister

0100 000B 1000 0000 : 11 110 bytereg : imm8

immediate32 to qwordregister

0100 100B 1000 0001 : 11 110 qwordreg : imm32

immediate8 to qwordregister

0100 100B 1000 0011 : 11 110 qwordreg : imm8

immediate to AL, AX, or EAX

0100 000B 0011 010w : imm

immediate to RAX

0100 1000 0011 0101 : immediate data

immediate to memory

0100 00XB 1000 00sw : mod 110 r/m : imm

immediate8 to memory8

0100 00XB 1000 0000 : mod 110 r/m : imm8

B-36

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INSTRUCTION FORMATS AND ENCODINGS

Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)

Instruction and Format

Encoding

immediate32 to memory64

0100 10XB 1000 0001 : mod 110 r/m : imm32

immediate8 to memory64

0100 10XB 1000 0011 : mod 110 r/m : imm8

Prefix Bytes

address size

0110 0111

LOCK

1111 0000

operand size

0110 0110

CS segment override

0010 1110

DS segment override

0011 1110

ES segment override

0010 0110

FS segment override

0110 0100

GS segment override

0110 0101

SS segment override

0011 0110

B.3

PENTIUM® PROCESSOR FAMILY INSTRUCTION FORMATS AND ENCODINGS

The following table shows formats and encodings introduced by the Pentium processor family.

Table B-16. Pentium® Processor Family Instruction Formats and Encodings, Non-64-Bit Modes

Instruction and Format

Encoding

CMPXCHG8B - Compare and Exchange 8 Bytes

EDX:EAX with memory64

0000 1111 : 1100 0111 : mod 001 r/m

Table B-17. Pentium® Processor Family Instruction Formats and Encodings, 64-Bit Mode

Instruction and Format

Encoding

CMPXCHG8B/CMPXCHG16B - Compare and Exchange Bytes

EDX:EAX with memory64

0000 1111 : 1100 0111 : mod 001 r/m

RDX:RAX with memory128

0100 10XB 0000 1111 : 1100 0111 : mod 001 r/m

B.4

64-BIT MODE INSTRUCTION ENCODINGS FOR SIMD INSTRUCTION

EXTENSIONS

Non-64-bit mode instruction encodings for MMX Technology, SSE, SSE2, and SSE3 are covered by applying these

rules to Table B-19 through Table B-31. Table B-34 lists special encodings (instructions that do not follow the rules

below).

1. The REX instruction has no effect:

• On immediates.

• If both operands are MMX registers.

• On MMX registers and XMM registers.

• If an MMX register is encoded in the reg field of the ModR/M byte.

Vol. 2D B-37

INSTRUCTION FORMATS AND ENCODINGS

2. If a memory operand is encoded in the r/m field of the ModR/M byte, REX.X and REX.B may be used for

encoding the memory operand.

3. If a general-purpose register is encoded in the r/m field of the ModR/M byte, REX.B may be used for register

encoding and REX.W may be used to encode the 64-bit operand size.

4. If an XMM register operand is encoded in the reg field of the ModR/M byte, REX.R may be used for register

encoding. If an XMM register operand is encoded in the r/m field of the ModR/M byte, REX.B may be used for

B.5

MMX INSTRUCTION FORMATS AND ENCODINGS

MMX instructions, except the EMMS instruction, use a format similar to the 2-byte Intel Architecture integer format.

Details of subfield encodings within these formats are presented below.

B.5.1

Granularity Field (gg)

The granularity field (gg) indicates the size of the packed operands that the instruction is operating on. When this

field is used, it is located in bits 1 and 0 of the second opcode byte. Table B-18 shows the encoding of the gg field.

Table B-18. Encoding of Granularity of Data Field (gg)

Granularity of Data

Packed Bytes

Packed Words

Packed Doublewords

Quadword

B.5.2

MMX Technology and General-Purpose Register Fields (mmxreg and reg)

When MMX technology registers (mmxreg) are used as operands, they are encoded in the ModR/M byte in the reg

field (bits 5, 4, and 3) and/or the R/M field (bits 2, 1, and 0).

If an MMX instruction operates on a general-purpose register (reg), the register is encoded in the R/M field of the

ModR/M byte.

B.5.3

MMX Instruction Formats and Encodings Table

Table B-19 shows the formats and encodings of the integer instructions.

Table B-19. MMX Instruction Formats and Encodings

Instruction and Format

Encoding

EMMS - Empty MMX technology state

0000 1111:01110111

MOVD - Move doubleword

reg to mmxreg

0000 1111:0110 1110: 11 mmxreg reg

reg from mmxreg

0000 1111:0111 1110: 11 mmxreg reg

mem to mmxreg

0000 1111:0110 1110: mod mmxreg r/m

mem from mmxreg

0000 1111:0111 1110: mod mmxreg r/m

MOVQ - Move quadword

mmxreg2 to mmxreg1

0000 1111:0110 1111: 11 mmxreg1 mmxreg2

mmxreg2 from mmxreg1

0000 1111:0111 1111: 11 mmxreg1 mmxreg2

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INSTRUCTION FORMATS AND ENCODINGS

Table B-19. MMX Instruction Formats and Encodings (Contd.)

Instruction and Format

Encoding

mem to mmxreg

0000 1111:0110 1111: mod mmxreg r/m

mem from mmxreg

0000 1111:0111 1111: mod mmxreg r/m

PACKSSDW¹ - Pack dword to word data (signed with saturation)

mmxreg2 to mmxreg1

0000 1111:0110 1011: 11 mmxreg1 mmxreg2

memory to mmxreg

0000 1111:0110 1011: mod mmxreg r/m

PACKSSWB¹ - Pack word to byte data (signed with saturation)

mmxreg2 to mmxreg1

0000 1111:0110 0011: 11 mmxreg1 mmxreg2

memory to mmxreg

0000 1111:0110 0011: mod mmxreg r/m

PACKUSWB¹ - Pack word to byte data (unsigned with saturation)

mmxreg2 to mmxreg1

0000 1111:0110 0111: 11 mmxreg1 mmxreg2

memory to mmxreg

0000 1111:0110 0111: mod mmxreg r/m

PADD - Add with wrap-around

mmxreg2 to mmxreg1

0000 1111: 1111 11gg: 11 mmxreg1 mmxreg2

memory to mmxreg

0000 1111: 1111 11gg: mod mmxreg r/m

PADDS - Add signed with saturation

mmxreg2 to mmxreg1

0000 1111: 1110 11gg: 11 mmxreg1 mmxreg2

memory to mmxreg

0000 1111: 1110 11gg: mod mmxreg r/m

PADDUS - Add unsigned with saturation

mmxreg2 to mmxreg1

0000 1111: 1101 11gg: 11 mmxreg1 mmxreg2

memory to mmxreg

0000 1111: 1101 11gg: mod mmxreg r/m

PAND - Bitwise And

mmxreg2 to mmxreg1

0000 1111:1101 1011: 11 mmxreg1 mmxreg2

memory to mmxreg

0000 1111:1101 1011: mod mmxreg r/m

PANDN - Bitwise AndNot

mmxreg2 to mmxreg1

0000 1111:1101 1111: 11 mmxreg1 mmxreg2

memory to mmxreg

0000 1111:1101 1111: mod mmxreg r/m

PCMPEQ - Packed compare for equality

mmxreg1 with mmxreg2

0000 1111:0111 01gg: 11 mmxreg1 mmxreg2

mmxreg with memory

0000 1111:0111 01gg: mod mmxreg r/m

PCMPGT - Packed compare greater (signed)

mmxreg1 with mmxreg2

0000 1111:0110 01gg: 11 mmxreg1 mmxreg2

mmxreg with memory

0000 1111:0110 01gg: mod mmxreg r/m

PMADDWD - Packed multiply add

mmxreg2 to mmxreg1

0000 1111:1111 0101: 11 mmxreg1 mmxreg2

memory to mmxreg

0000 1111:1111 0101: mod mmxreg r/m

PMULHUW - Packed multiplication, store high word (unsigned)

mmxreg2 to mmxreg1

0000 1111: 1110 0100: 11 mmxreg1 mmxreg2

memory to mmxreg

0000 1111: 1110 0100: mod mmxreg r/m

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INSTRUCTION FORMATS AND ENCODINGS

Table B-19. MMX Instruction Formats and Encodings (Contd.)

Instruction and Format

Encoding

PMULHW - Packed multiplication, store high word

mmxreg2 to mmxreg1

0000 1111:1110 0101: 11 mmxreg1 mmxreg2

memory to mmxreg

0000 1111:1110 0101: mod mmxreg r/m

PMULLW - Packed multiplication, store low word

mmxreg2 to mmxreg1

0000 1111:1101 0101: 11 mmxreg1 mmxreg2

memory to mmxreg

0000 1111:1101 0101: mod mmxreg r/m

POR - Bitwise Or

mmxreg2 to mmxreg1

0000 1111:1110 1011: 11 mmxreg1 mmxreg2

memory to mmxreg

0000 1111:1110 1011: mod mmxreg r/m

PSLL² - Packed shift left logical

mmxreg1 by mmxreg2

0000 1111:1111 00gg: 11 mmxreg1 mmxreg2

mmxreg by memory

0000 1111:1111 00gg: mod mmxreg r/m

mmxreg by immediate

0000 1111:0111 00gg: 11 110 mmxreg: imm8 data

PSRA² - Packed shift right arithmetic

mmxreg1 by mmxreg2

0000 1111:1110 00gg: 11 mmxreg1 mmxreg2

mmxreg by memory

0000 1111:1110 00gg: mod mmxreg r/m

mmxreg by immediate

0000 1111:0111 00gg: 11 100 mmxreg: imm8 data

PSRL² - Packed shift right logical

mmxreg1 by mmxreg2

0000 1111:1101 00gg: 11 mmxreg1 mmxreg2

mmxreg by memory

0000 1111:1101 00gg: mod mmxreg r/m

mmxreg by immediate

0000 1111:0111 00gg: 11 010 mmxreg: imm8 data

PSUB - Subtract with wrap-around

mmxreg2 from mmxreg1

0000 1111:1111 10gg: 11 mmxreg1 mmxreg2

memory from mmxreg

0000 1111:1111 10gg: mod mmxreg r/m

PSUBS - Subtract signed with saturation

mmxreg2 from mmxreg1

0000 1111:1110 10gg: 11 mmxreg1 mmxreg2

memory from mmxreg

0000 1111:1110 10gg: mod mmxreg r/m

PSUBUS - Subtract unsigned with saturation

mmxreg2 from mmxreg1

0000 1111:1101 10gg: 11 mmxreg1 mmxreg2

memory from mmxreg

0000 1111:1101 10gg: mod mmxreg r/m

PUNPCKH - Unpack high data to next larger type

mmxreg2 to mmxreg1

0000 1111:0110 10gg: 11 mmxreg1 mmxreg2

memory to mmxreg

0000 1111:0110 10gg: mod mmxreg r/m

PUNPCKL - Unpack low data to next larger type

mmxreg2 to mmxreg1

0000 1111:0110 00gg: 11 mmxreg1 mmxreg2

memory to mmxreg

0000 1111:0110 00gg: mod mmxreg r/m

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INSTRUCTION FORMATS AND ENCODINGS

Table B-19. MMX Instruction Formats and Encodings (Contd.)

Instruction and Format

Encoding

PXOR - Bitwise Xor

mmxreg2 to mmxreg1

0000 1111:1110 1111: 11 mmxreg1 mmxreg2

memory to mmxreg

0000 1111:1110 1111: mod mmxreg r/m

NOTES:

1. The pack instructions perform saturation from signed packed data of one type to signed or unsigned data of the next smaller type.

2. The format of the shift instructions has one additional format to support shifting by immediate shift-counts. The shift operations

are not supported equally for all data types.

B.6

PROCESSOR EXTENDED STATE INSTRUCTION FORMATS AND ENCODINGS

Table B-20 shows the formats and encodings for several instructions that relate to processor extended state

management.

Table B-20. Formats and Encodings of XSAVE/XRSTOR/XGETBV/XSETBV Instructions

Instruction and Format

Encoding

XGETBV - Get Value of Extended Control Register

0000 1111:0000 0001: 1101 0000

XRSTOR - Restore Processor Extended States¹

0000 1111:1010 1110: mod^A 101 r/m

XSAVE - Save Processor Extended States¹

0000 1111:1010 1110: mod^A 100 r/m

XSETBV - Set Extended Control Register

0000 1111:0000 0001: 1101 0001

NOTES:

1. For XSAVE and XRSTOR, “mod = 11” is reserved.

B.7

P6 FAMILY INSTRUCTION FORMATS AND ENCODINGS

Table B-20 shows the formats and encodings for several instructions that were introduced into the IA-32 architec-

ture in the P6 family processors.

Table B-21. Formats and Encodings of P6 Family Instructions

Instruction and Format

Encoding

CMOVcc - Conditional Move

register2 to register1

0000 1111: 0100 tttn : 11 reg1 reg2

memory to register

0000 1111 : 0100 tttn : mod reg r/m

FCMOVcc - Conditional Move on EFLAG Register Condition Codes

move if below (B)

11011 010 : 11 000 ST(i)

move if equal (E)

11011 010 : 11 001 ST(i)

move if below or equal (BE)

11011 010 : 11 010 ST(i)

move if unordered (U)

11011 010 : 11 011 ST(i)

move if not below (NB)

11011 011 : 11 000 ST(i)

move if not equal (NE)

11011 011 : 11 001 ST(i)

move if not below or equal (NBE)

11011 011 : 11 010 ST(i)

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INSTRUCTION FORMATS AND ENCODINGS

Table B-21. Formats and Encodings of P6 Family Instructions (Contd.)

Instruction and Format

Encoding

move if not unordered (NU)

11011 011 : 11 011 ST(i)

FCOMI - Compare Real and Set EFLAGS

11011 011 : 11 110 ST(i)

FXRSTOR - Restore x87 FPU, MMX, SSE, and SSE2 State¹

0000 1111:1010 1110: mod^A 001 r/m

FXSAVE - Save x87 FPU, MMX, SSE, and SSE2 State¹

0000 1111:1010 1110: mod^A 000 r/m

SYSENTER - Fast System Call

0000 1111:0011 0100

SYSEXIT - Fast Return from Fast System Call

0000 1111:0011 0101

NOTES:

1. For FXSAVE and FXRSTOR, “mod = 11” is reserved.

B.8

SSE INSTRUCTION FORMATS AND ENCODINGS

The SSE instructions use the ModR/M format and are preceded by the 0FH prefix byte. In general, operations are

not duplicated to provide two directions (that is, separate load and store variants).

The following three tables (Tables B-22, B-23, and B-24) show the formats and encodings for the SSE SIMD

floating-point, SIMD integer, and cacheability and memory ordering instructions, respectively. Some SSE instruc-

tions require a mandatory prefix (66H, F2H, F3H) as part of the two-byte opcode. Mandatory prefixes are included

in the tables.

Table B-22. Formats and Encodings of SSE Floating-Point Instructions

Instruction and Format

Encoding

ADDPS—Add Packed Single Precision Floating-Point Values

xmmreg2 to xmmreg1

0000 1111:0101 1000:11 xmmreg1 xmmreg2

mem to xmmreg

0000 1111:0101 1000: mod xmmreg r/m

ADDSS—Add Scalar Single Precision Floating-Point Values

xmmreg2 to xmmreg1

1111 0011:0000 1111:01011000:11 xmmreg1 xmmreg2

mem to xmmreg

1111 0011:0000 1111:01011000: mod xmmreg r/m

ANDNPS—Bitwise Logical AND NOT of Packed Single Precision Floating-Point Values

xmmreg2 to xmmreg1

0000 1111:0101 0101:11 xmmreg1 xmmreg2

mem to xmmreg

0000 1111:0101 0101: mod xmmreg r/m

ANDPS—Bitwise Logical AND of Packed Single Precision Floating-Point Values

xmmreg2 to xmmreg1

0000 1111:0101 0100:11 xmmreg1 xmmreg2

mem to xmmreg

0000 1111:0101 0100: mod xmmreg r/m

CMPPS—Compare Packed Single Precision Floating-Point Values

xmmreg2 to xmmreg1, imm8

0000 1111:1100 0010:11 xmmreg1 xmmreg2: imm8

mem to xmmreg, imm8

0000 1111:1100 0010: mod xmmreg r/m: imm8

CMPSS—Compare Scalar Single Precision Floating-Point Values

xmmreg2 to xmmreg1, imm8

1111 0011:0000 1111:1100 0010:11 xmmreg1 xmmreg2: imm8

mem to xmmreg, imm8

1111 0011:0000 1111:1100 0010: mod xmmreg r/m: imm8

COMISS—Compare Scalar Ordered Single Precision Floating-Point Values and Set EFLAGS

xmmreg2 to xmmreg1

0000 1111:0010 1111:11 xmmreg1 xmmreg2

mem to xmmreg

0000 1111:0010 1111: mod xmmreg r/m

B-42

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Table B-22. Formats and Encodings of SSE Floating-Point Instructions (Contd.)

Instruction and Format

Encoding

CVTPI2PS—Convert Packed Doubleword Integers to Packed Single Precision Floating-Point Values

mmreg to xmmreg

0000 1111:0010 1010:11 xmmreg1 mmreg1

mem to xmmreg

0000 1111:0010 1010: mod xmmreg r/m

CVTPS2PI—Convert Packed Single Precision Floating-Point Values to Packed Doubleword Integers

xmmreg to mmreg

0000 1111:0010 1101:11 mmreg1 xmmreg1

mem to mmreg

0000 1111:0010 1101: mod mmreg r/m

CVTSI2SS—Convert Doubleword Integer to Scalar Single Precision Floating-Point Value

r32 to xmmreg1

1111 0011:0000 1111:00101010:11 xmmreg1 r32

mem to xmmreg

1111 0011:0000 1111:00101010: mod xmmreg r/m

CVTSS2SI—Convert Scalar Single Precision Floating-Point Value to Doubleword Integer

xmmreg to r32

1111 0011:0000 1111:0010 1101:11 r32 xmmreg

mem to r32

1111 0011:0000 1111:0010 1101: mod r32 r/m

CVTTPS2PI—Convert with Truncation Packed Single Precision Floating-Point Values to Packed Doubleword Integers

xmmreg to mmreg

0000 1111:0010 1100:11 mmreg1 xmmreg1

mem to mmreg

0000 1111:0010 1100: mod mmreg r/m

CVTTSS2SI—Convert with Truncation Scalar Single Precision Floating-Point Value to Doubleword Integer

xmmreg to r32

1111 0011:0000 1111:0010 1100:11 r32 xmmreg1

mem to r32

1111 0011:0000 1111:0010 1100: mod r32 r/m

DIVPS—Divide Packed Single Precision Floating-Point Values

xmmreg2 to xmmreg1

0000 1111:0101 1110:11 xmmreg1 xmmreg2

mem to xmmreg

0000 1111:0101 1110: mod xmmreg r/m

DIVSS—Divide Scalar Single Precision Floating-Point Values

xmmreg2 to xmmreg1

1111 0011:0000 1111:0101 1110:11 xmmreg1 xmmreg2

mem to xmmreg

1111 0011:0000 1111:0101 1110: mod xmmreg r/m

LDMXCSR—Load MXCSR Register State

m32 to MXCSR

0000 1111:1010 1110:mod^A 010 mem

MAXPS—Return Maximum Packed Single Precision Floating-Point Values

xmmreg2 to xmmreg1

0000 1111:0101 1111:11 xmmreg1 xmmreg2

mem to xmmreg

0000 1111:0101 1111: mod xmmreg r/m

MAXSS—Return Maximum Scalar Double Precision Floating-Point Value

xmmreg2 to xmmreg1

1111 0011:0000 1111:0101 1111:11 xmmreg1 xmmreg2

mem to xmmreg

1111 0011:0000 1111:0101 1111: mod xmmreg r/m

MINPS—Return Minimum Packed Double Precision Floating-Point Values

xmmreg2 to xmmreg1

0000 1111:0101 1101:11 xmmreg1 xmmreg2

mem to xmmreg

0000 1111:0101 1101: mod xmmreg r/m

MINSS—Return Minimum Scalar Double Precision Floating-Point Value

xmmreg2 to xmmreg1

1111 0011:0000 1111:0101 1101:11 xmmreg1 xmmreg2

mem to xmmreg

1111 0011:0000 1111:0101 1101: mod xmmreg r/m

Vol. 2D B-43

INSTRUCTION FORMATS AND ENCODINGS

Table B-22. Formats and Encodings of SSE Floating-Point Instructions (Contd.)

Instruction and Format

Encoding

MOVAPS—Move Aligned Packed Single Precision Floating-Point Values

xmmreg2 to xmmreg1

0000 1111:0010 1000:11 xmmreg2 xmmreg1

mem to xmmreg1

0000 1111:0010 1000: mod xmmreg r/m

xmmreg1 to xmmreg2

0000 1111:0010 1001:11 xmmreg1 xmmreg2

xmmreg1 to mem

0000 1111:0010 1001: mod xmmreg r/m

MOVHLPS—Move Packed Single Precision Floating-Point Values High to Low

xmmreg2 to xmmreg1

0000 1111:0001 0010:11 xmmreg1 xmmreg2

MOVHPS—Move High Packed Single Precision Floating-Point Values

mem to xmmreg

0000 1111:0001 0110: mod xmmreg r/m

xmmreg to mem

0000 1111:0001 0111: mod xmmreg r/m

MOVLHPS—Move Packed Single Precision Floating-Point Values Low to High

xmmreg2 to xmmreg1

0000 1111:00010110:11 xmmreg1 xmmreg2

MOVLPS—Move Low Packed Single Precision Floating-Point Values

mem to xmmreg

0000 1111:0001 0010: mod xmmreg r/m

xmmreg to mem

0000 1111:0001 0011: mod xmmreg r/m

MOVMSKPS—Extract Packed Single Precision Floating-Point Sign Mask

xmmreg to r32

0000 1111:0101 0000:11 r32 xmmreg

MOVSS—Move Scalar Single Precision Floating-Point Values

xmmreg2 to xmmreg1

1111 0011:0000 1111:0001 0000:11 xmmreg2 xmmreg1

mem to xmmreg1

1111 0011:0000 1111:0001 0000: mod xmmreg r/m

xmmreg1 to xmmreg2

1111 0011:0000 1111:0001 0001:11 xmmreg1 xmmreg2

xmmreg1 to mem

1111 0011:0000 1111:0001 0001: mod xmmreg r/m

MOVUPS—Move Unaligned Packed Single Precision Floating-Point Values

xmmreg2 to xmmreg1

0000 1111:0001 0000:11 xmmreg2 xmmreg1

mem to xmmreg1

0000 1111:0001 0000: mod xmmreg r/m

xmmreg1 to xmmreg2

0000 1111:0001 0001:11 xmmreg1 xmmreg2

xmmreg1 to mem

0000 1111:0001 0001: mod xmmreg r/m

MULPS—Multiply Packed Single Precision Floating-Point Values

xmmreg2 to xmmreg1

0000 1111:0101 1001:11 xmmreg1 xmmreg2

mem to xmmreg

0000 1111:0101 1001: mod xmmreg r/m

MULSS—Multiply Scalar Single Precision Floating-Point Values

xmmreg2 to xmmreg1

1111 0011:0000 1111:0101 1001:11 xmmreg1 xmmreg2

mem to xmmreg

1111 0011:0000 1111:0101 1001: mod xmmreg r/m

ORPS—Bitwise Logical OR of Single Precision Floating-Point Values

xmmreg2 to xmmreg1

0000 1111:0101 0110:11 xmmreg1 xmmreg2

mem to xmmreg

0000 1111:0101 0110: mod xmmreg r/m

RCPPS—Compute Reciprocals of Packed Single Precision Floating-Point Values

xmmreg2 to xmmreg1

0000 1111:0101 0011:11 xmmreg1 xmmreg2

B-44

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Table B-22. Formats and Encodings of SSE Floating-Point Instructions (Contd.)

Instruction and Format

Encoding

mem to xmmreg

0000 1111:0101 0011: mod xmmreg r/m

RCPSS—Compute Reciprocals of Scalar Single Precision Floating-Point Value

xmmreg2 to xmmreg1

1111 0011:0000 1111:01010011:11 xmmreg1 xmmreg2

mem to xmmreg

1111 0011:0000 1111:01010011: mod xmmreg r/m

RSQRTPS—Compute Reciprocals of Square Roots of Packed Single Precision Floating-Point Values

xmmreg2 to xmmreg1

0000 1111:0101 0010:11 xmmreg1 xmmreg2

mem to xmmreg

0000 1111:0101 0010: mode xmmreg r/m

RSQRTSS—Compute Reciprocals of Square Roots of Scalar Single Precision Floating-Point Value

xmmreg2 to xmmreg1

1111 0011:0000 1111:0101 0010:11 xmmreg1 xmmreg2

mem to xmmreg

1111 0011:0000 1111:0101 0010: mod xmmreg r/m

SHUFPS—Shuffle Packed Single Precision Floating-Point Values

xmmreg2 to xmmreg1, imm8

0000 1111:1100 0110:11 xmmreg1 xmmreg2: imm8

mem to xmmreg, imm8

0000 1111:1100 0110: mod xmmreg r/m: imm8

SQRTPS—Compute Square Roots of Packed Single Precision Floating-Point Values

xmmreg2 to xmmreg1

0000 1111:0101 0001:11 xmmreg1 xmmreg2

mem to xmmreg

0000 1111:0101 0001: mod xmmreg r/m

SQRTSS—Compute Square Root of Scalar Single Precision Floating-Point Value

xmmreg2 to xmmreg1

1111 0011:0000 1111:0101 0001:11 xmmreg1 xmmreg2

mem to xmmreg

1111 0011:0000 1111:0101 0001:mod xmmreg r/m

STMXCSR—Store MXCSR Register State

MXCSR to mem

0000 1111:1010 1110:mod^A 011 mem

SUBPS—Subtract Packed Single Precision Floating-Point Values

xmmreg2 to xmmreg1

0000 1111:0101 1100:11 xmmreg1 xmmreg2

mem to xmmreg

0000 1111:0101 1100:mod xmmreg r/m

SUBSS—Subtract Scalar Single Precision Floating-Point Values

xmmreg2 to xmmreg1

1111 0011:0000 1111:0101 1100:11 xmmreg1 xmmreg2

mem to xmmreg

1111 0011:0000 1111:0101 1100:mod xmmreg r/m

UCOMISS—Unordered Compare Scalar Ordered Single Precision Floating-Point Values and Set EFLAGS

xmmreg2 to xmmreg1

0000 1111:0010 1110:11 xmmreg1 xmmreg2

mem to xmmreg

0000 1111:0010 1110: mod xmmreg r/m

UNPCKHPS—Unpack and Interleave High Packed Single Precision Floating-Point Values

xmmreg2 to xmmreg1

0000 1111:0001 0101:11 xmmreg1 xmmreg2

mem to xmmreg

0000 1111:0001 0101: mod xmmreg r/m

UNPCKLPS—Unpack and Interleave Low Packed Single Precision Floating-Point Values

xmmreg2 to xmmreg1

0000 1111:0001 0100:11 xmmreg1 xmmreg2

mem to xmmreg

0000 1111:0001 0100: mod xmmreg r/m

XORPS—Bitwise Logical XOR of Single Precision Floating-Point Values

xmmreg2 to xmmreg1

0000 1111:0101 0111:11 xmmreg1 xmmreg2

Vol. 2D B-45

INSTRUCTION FORMATS AND ENCODINGS

Table B-22. Formats and Encodings of SSE Floating-Point Instructions (Contd.)

Instruction and Format

Encoding

mem to xmmreg

0000 1111:0101 0111: mod xmmreg r/m

Table B-23. Formats and Encodings of SSE Integer Instructions

Instruction and Format

Encoding

PAVGB/PAVGW—Average Packed Integers

mmreg2 to mmreg1

0000 1111:1110 0000:11 mmreg1 mmreg2

0000 1111:1110 0011:11 mmreg1 mmreg2

mem to mmreg

0000 1111:1110 0000: mod mmreg r/m

0000 1111:1110 0011: mod mmreg r/m

PEXTRW—Extract Word

mmreg to reg32, imm8

0000 1111:1100 0101:11 r32 mmreg: imm8

PINSRW—Insert Word

reg32 to mmreg, imm8

0000 1111:1100 0100:11 mmreg r32: imm8

m16 to mmreg, imm8

0000 1111:1100 0100: mod mmreg r/m: imm8

PMAXSW—Maximum of Packed Signed Word Integers

mmreg2 to mmreg1

0000 1111:1110 1110:11 mmreg1 mmreg2

mem to mmreg

0000 1111:1110 1110: mod mmreg r/m

PMAXUB—Maximum of Packed Unsigned Byte Integers

mmreg2 to mmreg1

0000 1111:1101 1110:11 mmreg1 mmreg2

mem to mmreg

0000 1111:1101 1110: mod mmreg r/m

PMINSW—Minimum of Packed Signed Word Integers

mmreg2 to mmreg1

0000 1111:1110 1010:11 mmreg1 mmreg2

mem to mmreg

0000 1111:1110 1010: mod mmreg r/m

PMINUB—Minimum of Packed Unsigned Byte Integers

mmreg2 to mmreg1

0000 1111:1101 1010:11 mmreg1 mmreg2

mem to mmreg

0000 1111:1101 1010: mod mmreg r/m

PMOVMSKB—Move Byte Mask To Integer

mmreg to reg32

0000 1111:1101 0111:11 r32 mmreg

PMULHUW—Multiply Packed Unsigned Integers and Store High Result

mmreg2 to mmreg1

0000 1111:1110 0100:11 mmreg1 mmreg2

mem to mmreg

0000 1111:1110 0100: mod mmreg r/m

PSADBW—Compute Sum of Absolute Differences

mmreg2 to mmreg1

0000 1111:1111 0110:11 mmreg1 mmreg2

mem to mmreg

0000 1111:1111 0110: mod mmreg r/m

PSHUFW—Shuffle Packed Words

mmreg2 to mmreg1, imm8

0000 1111:0111 0000:11 mmreg1 mmreg2: imm8

mem to mmreg, imm8

0000 1111:0111 0000: mod mmreg r/m: imm8

B-46

Vol. 2D

INSTRUCTION FORMATS AND ENCODINGS

Table B-24. Format and Encoding of SSE Cacheability & Memory Ordering Instructions

Instruction and Format

Encoding

MASKMOVQ—Store Selected Bytes of Quadword

mmreg2 to mmreg1

0000 1111:1111 0111:11 mmreg1 mmreg2

MOVNTPS—Store Packed Single Precision Floating-Point Values Using Non-Temporal Hint

xmmreg to mem

0000 1111:0010 1011: mod xmmreg r/m

MOVNTQ—Store Quadword Using Non-Temporal Hint

mmreg to mem

0000 1111:1110 0111: mod mmreg r/m

PREFETCHT0—Prefetch Temporal to All Cache Levels

0000 1111:0001 1000:mod^A 001 mem

PREFETCHT1—Prefetch Temporal to First Level Cache

0000 1111:0001 1000:mod^A 010 mem

PREFETCHT2—Prefetch Temporal to Second Level Cache

0000 1111:0001 1000:mod^A 011 mem

PREFETCHNTA—Prefetch Non-Temporal to All Cache Levels

0000 1111:0001 1000:mod^A 000 mem

SFENCE—Store Fence

0000 1111:1010 1110:11 111 000

B.9

SSE2 INSTRUCTION FORMATS AND ENCODINGS

The SSE2 instructions use the ModR/M format and are preceded by the 0FH prefix byte. In general, operations are

not duplicated to provide two directions (that is, separate load and store variants).

The following three tables show the formats and encodings for the SSE2 SIMD floating-point, SIMD integer, and

cacheability instructions, respectively. Some SSE2 instructions require a mandatory prefix (66H, F2H, F3H) as part

of the two-byte opcode. These prefixes are included in the tables.

B.9.1

Granularity Field (gg)

The granularity field (gg) indicates the size of the packed operands that the instruction is operating on. When this

field is used, it is located in bits 1 and 0 of the second opcode byte. Table B-25 shows the encoding of this gg field.

Table B-25. Encoding of Granularity of Data Field (gg)

Granularity of Data

Packed Bytes

Packed Words

Packed Doublewords

Quadword

Vol. 2D B-47

INSTRUCTION FORMATS AND ENCODINGS

Table B-26. Formats and Encodings of SSE2 Floating-Point Instructions

Instruction and Format

Encoding

ADDPD—Add Packed Double Precision Floating-Point Values

xmmreg2 to xmmreg1

0110 0110:0000 1111:0101 1000:11 xmmreg1 xmmreg2

mem to xmmreg

0110 0110:0000 1111:0101 1000: mod xmmreg r/m

ADDSD—Add Scalar Double Precision Floating-Point Values

xmmreg2 to xmmreg1

1111 0010:0000 1111:0101 1000:11 xmmreg1 xmmreg2

mem to xmmreg

1111 0010:0000 1111:0101 1000: mod xmmreg r/m

ANDNPD—Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values

xmmreg2 to xmmreg1

0110 0110:0000 1111:0101 0101:11 xmmreg1 xmmreg2

mem to xmmreg

0110 0110:0000 1111:0101 0101: mod xmmreg r/m

ANDPD—Bitwise Logical AND of Packed Double Precision Floating-Point Values

xmmreg2 to xmmreg1

0110 0110:0000 1111:0101 0100:11 xmmreg1 xmmreg2

mem to xmmreg

0110 0110:0000 1111:0101 0100: mod xmmreg r/m

CMPPD—Compare Packed Double Precision Floating-Point Values

xmmreg2 to xmmreg1, imm8

0110 0110:0000 1111:1100 0010:11 xmmreg1 xmmreg2: imm8

mem to xmmreg, imm8

0110 0110:0000 1111:1100 0010: mod xmmreg r/m: imm8

CMPSD—Compare Scalar Double Precision Floating-Point Values

xmmreg2 to xmmreg1, imm8

1111 0010:0000 1111:1100 0010:11 xmmreg1 xmmreg2: imm8

mem to xmmreg, imm8

11110 010:0000 1111:1100 0010: mod xmmreg r/m: imm8

COMISD—Compare Scalar Ordered Double Precision Floating-Point Values and Set EFLAGS

xmmreg2 to xmmreg1

0110 0110:0000 1111:0010 1111:11 xmmreg1 xmmreg2

mem to xmmreg

0110 0110:0000 1111:0010 1111: mod xmmreg r/m

CVTPI2PD—Convert Packed Doubleword Integers to Packed Double Precision Floating-Point Values

mmreg to xmmreg

0110 0110:0000 1111:0010 1010:11 xmmreg1 mmreg1

mem to xmmreg

0110 0110:0000 1111:0010 1010: mod xmmreg r/m

CVTPD2PI—Convert Packed Double Precision Floating-Point Values to Packed Doubleword Integers

xmmreg to mmreg

0110 0110:0000 1111:0010 1101:11 mmreg1 xmmreg1

mem to mmreg

0110 0110:0000 1111:0010 1101: mod mmreg r/m

CVTSI2SD—Convert Doubleword Integer to Scalar Double Precision Floating-Point Value

r32 to xmmreg1

1111 0010:0000 1111:0010 1010:11 xmmreg r32

mem to xmmreg

1111 0010:0000 1111:0010 1010: mod xmmreg r/m

CVTSD2SI—Convert Scalar Double Precision Floating-Point Value to Doubleword Integer

xmmreg to r32

1111 0010:0000 1111:0010 1101:11 r32 xmmreg

mem to r32

1111 0010:0000 1111:0010 1101: mod r32 r/m

CVTTPD2PI—Convert with Truncation Packed Double Precision Floating-Point Values to Packed Doubleword Integers

xmmreg to mmreg

0110 0110:0000 1111:0010 1100:11 mmreg xmmreg

mem to mmreg

0110 0110:0000 1111:0010 1100: mod mmreg r/m

CVTTSD2SI—Convert with Truncation Scalar Double Precision Floating-Point Value to Doubleword Integer

xmmreg to r32

1111 0010:0000 1111:0010 1100:11 r32 xmmreg

B-48

Vol. 2D

INSTRUCTION FORMATS AND ENCODINGS

Table B-26. Formats and Encodings of SSE2 Floating-Point Instructions (Contd.)

Instruction and Format

Encoding

mem to r32

1111 0010:0000 1111:0010 1100: mod r32 r/m

CVTPD2PS—Covert Packed Double Precision Floating-Point Values to Packed Single Precision Floating-Point Values

xmmreg2 to xmmreg1

0110 0110:0000 1111:0101 1010:11 xmmreg1 xmmreg2

mem to xmmreg

0110 0110:0000 1111:0101 1010: mod xmmreg r/m

CVTPS2PD—Covert Packed Single Precision Floating-Point Values to Packed Double Precision Floating-Point Values

xmmreg2 to xmmreg1

0000 1111:0101 1010:11 xmmreg1 xmmreg2

mem to xmmreg

0000 1111:0101 1010: mod xmmreg r/m

CVTSD2SS—Covert Scalar Double Precision Floating-Point Value to Scalar Single Precision Floating-Point Value

xmmreg2 to xmmreg1

1111 0010:0000 1111:0101 1010:11 xmmreg1 xmmreg2

mem to xmmreg

1111 0010:0000 1111:0101 1010: mod xmmreg r/m

CVTSS2SD—Covert Scalar Single Precision Floating-Point Value to Scalar Double Precision Floating-Point Value

xmmreg2 to xmmreg1

1111 0011:0000 1111:0101 1010:11 xmmreg1 xmmreg2

mem to xmmreg

1111 0011:00001 111:0101 1010: mod xmmreg r/m

CVTPD2DQ—Convert Packed Double Precision Floating-Point Values to Packed Doubleword Integers

xmmreg2 to xmmreg1

1111 0010:0000 1111:1110 0110:11 xmmreg1 xmmreg2

mem to xmmreg

1111 0010:0000 1111:1110 0110: mod xmmreg r/m

CVTTPD2DQ—Convert With Truncation Packed Double Precision Floating-Point Values to Packed Doubleword Integers

xmmreg2 to xmmreg1

0110 0110:0000 1111:1110 0110:11 xmmreg1 xmmreg2

mem to xmmreg

0110 0110:0000 1111:1110 0110: mod xmmreg r/m

CVTDQ2PD—Convert Packed Doubleword Integers to Packed Single Precision Floating-Point Values

xmmreg2 to xmmreg1

1111 0011:0000 1111:1110 0110:11 xmmreg1 xmmreg2

mem to xmmreg

1111 0011:0000 1111:1110 0110: mod xmmreg r/m

CVTPS2DQ—Convert Packed Single Precision Floating-Point Values to Packed Doubleword Integers

xmmreg2 to xmmreg1

0110 0110:0000 1111:0101 1011:11 xmmreg1 xmmreg2

mem to xmmreg

0110 0110:0000 1111:0101 1011: mod xmmreg r/m

CVTTPS2DQ—Convert With Truncation Packed Single Precision Floating-Point Values to Packed Doubleword Integers

xmmreg2 to xmmreg1

1111 0011:0000 1111:0101 1011:11 xmmreg1 xmmreg2

mem to xmmreg

1111 0011:0000 1111:0101 1011: mod xmmreg r/m

CVTDQ2PS—Convert Packed Doubleword Integers to Packed Double Precision Floating-Point Values

xmmreg2 to xmmreg1

0000 1111:0101 1011:11 xmmreg1 xmmreg2

mem to xmmreg

0000 1111:0101 1011: mod xmmreg r/m

DIVPD—Divide Packed Double Precision Floating-Point Values

xmmreg2 to xmmreg1

0110 0110:0000 1111:0101 1110:11 xmmreg1 xmmreg2

mem to xmmreg

0110 0110:0000 1111:0101 1110: mod xmmreg r/m

DIVSD—Divide Scalar Double Precision Floating-Point Values

xmmreg2 to xmmreg1

1111 0010:0000 1111:0101 1110:11 xmmreg1 xmmreg2

Vol. 2D

B-49

INSTRUCTION FORMATS AND ENCODINGS

Table B-26. Formats and Encodings of SSE2 Floating-Point Instructions (Contd.)

Instruction and Format

Encoding

mem to xmmreg

1111 0010:0000 1111:0101 1110: mod xmmreg r/m

MAXPD—Return Maximum Packed Double Precision Floating-Point Values

xmmreg2 to xmmreg1

0110 0110:0000 1111:0101 1111:11 xmmreg1 xmmreg2

mem to xmmreg

0110 0110:0000 1111:0101 1111: mod xmmreg r/m

MAXSD—Return Maximum Scalar Double Precision Floating-Point Value

xmmreg2 to xmmreg1

1111 0010:0000 1111:0101 1111:11 xmmreg1 xmmreg2

mem to xmmreg

1111 0010:0000 1111:0101 1111: mod xmmreg r/m

MINPD—Return Minimum Packed Double Precision Floating-Point Values

xmmreg2 to xmmreg1

0110 0110:0000 1111:0101 1101:11 xmmreg1 xmmreg2

mem to xmmreg

0110 0110:0000 1111:0101 1101: mod xmmreg r/m

MINSD—Return Minimum Scalar Double Precision Floating-Point Value

xmmreg2 to xmmreg1

1111 0010:0000 1111:0101 1101:11 xmmreg1 xmmreg2

mem to xmmreg

1111 0010:0000 1111:0101 1101: mod xmmreg r/m

MOVAPD—Move Aligned Packed Double Precision Floating-Point Values

xmmreg1 to xmmreg2

0110 0110:0000 1111:0010 1001:11 xmmreg2 xmmreg1

xmmreg1 to mem

0110 0110:0000 1111:0010 1001: mod xmmreg r/m

xmmreg2 to xmmreg1

0110 0110:0000 1111:0010 1000:11 xmmreg1 xmmreg2

mem to xmmreg1

0110 0110:0000 1111:0010 1000: mod xmmreg r/m

MOVHPD—Move High Packed Double Precision Floating-Point Values

xmmreg to mem

0110 0110:0000 1111:0001 0111: mod xmmreg r/m

mem to xmmreg

0110 0110:0000 1111:0001 0110: mod xmmreg r/m

MOVLPD—Move Low Packed Double Precision Floating-Point Values

xmmreg to mem

0110 0110:0000 1111:0001 0011: mod xmmreg r/m

mem to xmmreg

0110 0110:0000 1111:0001 0010: mod xmmreg r/m

MOVMSKPD—Extract Packed Double Precision Floating-Point Sign Mask

xmmreg to r32

0110 0110:0000 1111:0101 0000:11 r32 xmmreg

MOVSD—Move Scalar Double Precision Floating-Point Values

xmmreg1 to xmmreg2

1111 0010:0000 1111:0001 0001:11 xmmreg2 xmmreg1

xmmreg1 to mem

1111 0010:0000 1111:0001 0001: mod xmmreg r/m

xmmreg2 to xmmreg1

1111 0010:0000 1111:0001 0000:11 xmmreg1 xmmreg2

mem to xmmreg1

1111 0010:0000 1111:0001 0000: mod xmmreg r/m

MOVUPD—Move Unaligned Packed Double Precision Floating-Point Values

xmmreg2 to xmmreg1

0110 0110:0000 1111:0001 0001:11 xmmreg2 xmmreg1

mem to xmmreg1

0110 0110:0000 1111:0001 0001: mod xmmreg r/m

xmmreg1 to xmmreg2

0110 0110:0000 1111:0001 0000:11 xmmreg1 xmmreg2

xmmreg1 to mem

0110 0110:0000 1111:0001 0000: mod xmmreg r/m

MULPD—Multiply Packed Double Precision Floating-Point Values

xmmreg2 to xmmreg1

0110 0110:0000 1111:0101 1001:11 xmmreg1 xmmreg2

B-50

Vol. 2D

INSTRUCTION FORMATS AND ENCODINGS

Table B-26. Formats and Encodings of SSE2 Floating-Point Instructions (Contd.)

Instruction and Format

Encoding

mem to xmmreg

0110 0110:0000 1111:0101 1001: mod xmmreg r/m

MULSD—Multiply Scalar Double Precision Floating-Point Values

xmmreg2 to xmmreg1

1111 0010:00001111:01011001:11 xmmreg1 xmmreg2

mem to xmmreg

1111 0010:00001111:01011001: mod xmmreg r/m

ORPD—Bitwise Logical OR of Double Precision Floating-Point Values

xmmreg2 to xmmreg1

0110 0110:0000 1111:0101 0110:11 xmmreg1 xmmreg2

mem to xmmreg

0110 0110:0000 1111:0101 0110: mod xmmreg r/m

SHUFPD—Shuffle Packed Double Precision Floating-Point Values

xmmreg2 to xmmreg1, imm8

0110 0110:0000 1111:1100 0110:11 xmmreg1 xmmreg2: imm8

mem to xmmreg, imm8

0110 0110:0000 1111:1100 0110: mod xmmreg r/m: imm8

SQRTPD—Compute Square Roots of Packed Double Precision Floating-Point Values

xmmreg2 to xmmreg1

0110 0110:0000 1111:0101 0001:11 xmmreg1 xmmreg2

mem to xmmreg

0110 0110:0000 1111:0101 0001: mod xmmreg r/m

SQRTSD—Compute Square Root of Scalar Double Precision Floating-Point Value

xmmreg2 to xmmreg1

1111 0010:0000 1111:0101 0001:11 xmmreg1 xmmreg2

mem to xmmreg

1111 0010:0000 1111:0101 0001: mod xmmreg r/m

SUBPD—Subtract Packed Double Precision Floating-Point Values

xmmreg2 to xmmreg1

0110 0110:0000 1111:0101 1100:11 xmmreg1 xmmreg2

mem to xmmreg

0110 0110:0000 1111:0101 1100: mod xmmreg r/m

SUBSD—Subtract Scalar Double Precision Floating-Point Values

xmmreg2 to xmmreg1

1111 0010:0000 1111:0101 1100:11 xmmreg1 xmmreg2

mem to xmmreg

1111 0010:0000 1111:0101 1100: mod xmmreg r/m

UCOMISD—Unordered Compare Scalar Ordered Double Precision Floating-Point Values and Set EFLAGS

xmmreg2 to xmmreg1

0110 0110:0000 1111:0010 1110:11 xmmreg1 xmmreg2

mem to xmmreg

0110 0110:0000 1111:0010 1110: mod xmmreg r/m

UNPCKHPD—Unpack and Interleave High Packed Double Precision Floating-Point Values

xmmreg2 to xmmreg1

0110 0110:0000 1111:0001 0101:11 xmmreg1 xmmreg2

mem to xmmreg

0110 0110:0000 1111:0001 0101: mod xmmreg r/m

UNPCKLPD—Unpack and Interleave Low Packed Double Precision Floating-Point Values

xmmreg2 to xmmreg1

0110 0110:0000 1111:0001 0100:11 xmmreg1 xmmreg2

mem to xmmreg

0110 0110:0000 1111:0001 0100: mod xmmreg r/m

XORPD—Bitwise Logical OR of Double Precision Floating-Point Values

xmmreg2 to xmmreg1

0110 0110:0000 1111:0101 0111:11 xmmreg1 xmmreg2

mem to xmmreg

0110 0110:0000 1111:0101 0111: mod xmmreg r/m

Vol. 2D B-51

INSTRUCTION FORMATS AND ENCODINGS

Table B-27. Formats and Encodings of SSE2 Integer Instructions

Instruction and Format

Encoding

MOVD—Move Doubleword

reg to xmmreg

0110 0110:0000 1111:0110 1110: 11 xmmreg reg

reg from xmmreg

0110 0110:0000 1111:0111 1110: 11 xmmreg reg

mem to xmmreg

0110 0110:0000 1111:0110 1110: mod xmmreg r/m

mem from xmmreg

0110 0110:0000 1111:0111 1110: mod xmmreg r/m

MOVDQA—Move Aligned Double Quadword

xmmreg2 to xmmreg1

0110 0110:0000 1111:0110 1111:11 xmmreg1 xmmreg2

xmmreg2 from xmmreg1

0110 0110:0000 1111:0111 1111:11 xmmreg1 xmmreg2

mem to xmmreg

0110 0110:0000 1111:0110 1111: mod xmmreg r/m

mem from xmmreg

0110 0110:0000 1111:0111 1111: mod xmmreg r/m

MOVDQU—Move Unaligned Double Quadword

xmmreg2 to xmmreg1

1111 0011:0000 1111:0110 1111:11 xmmreg1 xmmreg2

xmmreg2 from xmmreg1

1111 0011:0000 1111:0111 1111:11 xmmreg1 xmmreg2

mem to xmmreg

1111 0011:0000 1111:0110 1111: mod xmmreg r/m

mem from xmmreg

1111 0011:0000 1111:0111 1111: mod xmmreg r/m

MOVQ2DQ—Move Quadword from MMX to XMM Register

mmreg to xmmreg

1111 0011:0000 1111:1101 0110:11 mmreg1 mmreg2

MOVDQ2Q—Move Quadword from XMM to MMX Register

xmmreg to mmreg

1111 0010:0000 1111:1101 0110:11 mmreg1 mmreg2

MOVQ—Move Quadword

xmmreg2 to xmmreg1

1111 0011:0000 1111:0111 1110: 11 xmmreg1 xmmreg2

xmmreg2 from xmmreg1

0110 0110:0000 1111:1101 0110: 11 xmmreg1 xmmreg2

mem to xmmreg

1111 0011:0000 1111:0111 1110: mod xmmreg r/m

mem from xmmreg

0110 0110:0000 1111:1101 0110: mod xmmreg r/m

PACKSSDW¹—Pack Dword To Word Data (signed with saturation)

xmmreg2 to xmmreg1

0110 0110:0000 1111:0110 1011: 11 xmmreg1 xmmreg2

memory to xmmreg

0110 0110:0000 1111:0110 1011: mod xmmreg r/m

PACKSSWB—Pack Word To Byte Data (signed with saturation)

xmmreg2 to xmmreg1

0110 0110:0000 1111:0110 0011: 11 xmmreg1 xmmreg2

memory to xmmreg

0110 0110:0000 1111:0110 0011: mod xmmreg r/m

PACKUSWB—Pack Word To Byte Data (unsigned with saturation)

xmmreg2 to xmmreg1

0110 0110:0000 1111:0110 0111: 11 xmmreg1 xmmreg2

memory to xmmreg

0110 0110:0000 1111:0110 0111: mod xmmreg r/m

PADDQ—Add Packed Quadword Integers

mmreg2 to mmreg1

0000 1111:1101 0100:11 mmreg1 mmreg2

mem to mmreg

0000 1111:1101 0100: mod mmreg r/m

xmmreg2 to xmmreg1

0110 0110:0000 1111:1101 0100:11 xmmreg1 xmmreg2

mem to xmmreg

0110 0110:0000 1111:1101 0100: mod xmmreg r/m

B-52

Vol. 2D

INSTRUCTION FORMATS AND ENCODINGS

Table B-27. Formats and Encodings of SSE2 Integer Instructions (Contd.)

Instruction and Format

Encoding

PADD—Add With Wrap-around

xmmreg2 to xmmreg1

0110 0110:0000 1111: 1111 11gg: 11 xmmreg1 xmmreg2

memory to xmmreg

0110 0110:0000 1111: 1111 11gg: mod xmmreg r/m

PADDS—Add Signed With Saturation

xmmreg2 to xmmreg1

0110 0110:0000 1111: 1110 11gg: 11 xmmreg1 xmmreg2

memory to xmmreg

0110 0110:0000 1111: 1110 11gg: mod xmmreg r/m

PADDUS—Add Unsigned With Saturation

xmmreg2 to xmmreg1

0110 0110:0000 1111: 1101 11gg: 11 xmmreg1 xmmreg2

memory to xmmreg

0110 0110:0000 1111: 1101 11gg: mod xmmreg r/m

PAND—Bitwise And

xmmreg2 to xmmreg1

0110 0110:0000 1111:1101 1011: 11 xmmreg1 xmmreg2

memory to xmmreg

0110 0110:0000 1111:1101 1011: mod xmmreg r/m

PANDN—Bitwise AndNot

xmmreg2 to xmmreg1

0110 0110:0000 1111:1101 1111: 11 xmmreg1 xmmreg2

memory to xmmreg

0110 0110:0000 1111:1101 1111: mod xmmreg r/m

PAVGB—Average Packed Integers

xmmreg2 to xmmreg1

0110 0110:0000 1111:11100 000:11 xmmreg1 xmmreg2

mem to xmmreg

01100110:00001111:11100000 mod xmmreg r/m

PAVGW—Average Packed Integers

xmmreg2 to xmmreg1

0110 0110:0000 1111:1110 0011:11 xmmreg1 xmmreg2

mem to xmmreg

0110 0110:0000 1111:1110 0011 mod xmmreg r/m

PCMPEQ—Packed Compare For Equality

xmmreg1 with xmmreg2

0110 0110:0000 1111:0111 01gg: 11 xmmreg1 xmmreg2

xmmreg with memory

0110 0110:0000 1111:0111 01gg: mod xmmreg r/m

PCMPGT—Packed Compare Greater (signed)

xmmreg1 with xmmreg2

0110 0110:0000 1111:0110 01gg: 11 xmmreg1 xmmreg2

xmmreg with memory

0110 0110:0000 1111:0110 01gg: mod xmmreg r/m

PEXTRW—Extract Word

xmmreg to reg32, imm8

0110 0110:0000 1111:1100 0101:11 r32 xmmreg: imm8

PINSRW—Insert Word

reg32 to xmmreg, imm8

0110 0110:0000 1111:1100 0100:11 xmmreg r32: imm8

m16 to xmmreg, imm8

0110 0110:0000 1111:1100 0100: mod xmmreg r/m: imm8

PMADDWD—Packed Multiply Add

xmmreg2 to xmmreg1

0110 0110:0000 1111:1111 0101: 11 xmmreg1 xmmreg2

memory to xmmreg

0110 0110:0000 1111:1111 0101: mod xmmreg r/m

PMAXSW—Maximum of Packed Signed Word Integers

xmmreg2 to xmmreg1

0110 0110:0000 1111:1110 1110:11 xmmreg1 xmmreg2

mem to xmmreg

01100110:00001111:11101110: mod xmmreg r/m

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Table B-27. Formats and Encodings of SSE2 Integer Instructions (Contd.)

Instruction and Format

Encoding

PMAXUB—Maximum of Packed Unsigned Byte Integers

xmmreg2 to xmmreg1

0110 0110:0000 1111:1101 1110:11 xmmreg1 xmmreg2

mem to xmmreg

0110 0110:0000 1111:1101 1110: mod xmmreg r/m

PMINSW—Minimum of Packed Signed Word Integers

xmmreg2 to xmmreg1

0110 0110:0000 1111:1110 1010:11 xmmreg1 xmmreg2

mem to xmmreg

0110 0110:0000 1111:1110 1010: mod xmmreg r/m

PMINUB—Minimum of Packed Unsigned Byte Integers

xmmreg2 to xmmreg1

0110 0110:0000 1111:1101 1010:11 xmmreg1 xmmreg2

mem to xmmreg

0110 0110:0000 1111:1101 1010 mod xmmreg r/m

PMOVMSKB—Move Byte Mask To Integer

xmmreg to reg32

0110 0110:0000 1111:1101 0111:11 r32 xmmreg

PMULHUW—Packed multiplication, store high word (unsigned)

xmmreg2 to xmmreg1

0110 0110:0000 1111:1110 0100: 11 xmmreg1 xmmreg2

memory to xmmreg

0110 0110:0000 1111:1110 0100: mod xmmreg r/m

PMULHW—Packed Multiplication, store high word

xmmreg2 to xmmreg1

0110 0110:0000 1111:1110 0101: 11 xmmreg1 xmmreg2

memory to xmmreg

0110 0110:0000 1111:1110 0101: mod xmmreg r/m

PMULLW—Packed Multiplication, store low word

xmmreg2 to xmmreg1

0110 0110:0000 1111:1101 0101: 11 xmmreg1 xmmreg2

memory to xmmreg

0110 0110:0000 1111:1101 0101: mod xmmreg r/m

PMULUDQ—Multiply Packed Unsigned Doubleword Integers

mmreg2 to mmreg1

0000 1111:1111 0100:11 mmreg1 mmreg2

mem to mmreg

0000 1111:1111 0100: mod mmreg r/m

xmmreg2 to xmmreg1

0110 0110:00001111:1111 0100:11 xmmreg1 xmmreg2

mem to xmmreg

0110 0110:00001111:1111 0100: mod xmmreg r/m

POR—Bitwise Or

xmmreg2 to xmmreg1

0110 0110:0000 1111:1110 1011: 11 xmmreg1 xmmreg2

memory to xmmreg

0110 0110:0000 1111:1110 1011: mod xmmreg r/m

PSADBW—Compute Sum of Absolute Differences

xmmreg2 to xmmreg1

0110 0110:0000 1111:1111 0110:11 xmmreg1 xmmreg2

mem to xmmreg

0110 0110:0000 1111:1111 0110: mod xmmreg r/m

PSHUFLW—Shuffle Packed Low Words

xmmreg2 to xmmreg1, imm8

1111 0010:0000 1111:0111 0000:11 xmmreg1 xmmreg2: imm8

mem to xmmreg, imm8

1111 0010:0000 1111:0111 0000:11 mod xmmreg r/m: imm8

PSHUFHW—Shuffle Packed High Words

xmmreg2 to xmmreg1, imm8

1111 0011:0000 1111:0111 0000:11 xmmreg1 xmmreg2: imm8

mem to xmmreg, imm8

1111 0011:0000 1111:0111 0000: mod xmmreg r/m: imm8

PSHUFD—Shuffle Packed Doublewords

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Table B-27. Formats and Encodings of SSE2 Integer Instructions (Contd.)

Instruction and Format

Encoding

xmmreg2 to xmmreg1, imm8

0110 0110:0000 1111:0111 0000:11 xmmreg1 xmmreg2: imm8

mem to xmmreg, imm8

0110 0110:0000 1111:0111 0000: mod xmmreg r/m: imm8

PSLLDQ—Shift Double Quadword Left Logical

xmmreg, imm8

0110 0110:0000 1111:0111 0011:11 111 xmmreg: imm8

PSLL—Packed Shift Left Logical

xmmreg1 by xmmreg2

0110 0110:0000 1111:1111 00gg: 11 xmmreg1 xmmreg2

xmmreg by memory

0110 0110:0000 1111:1111 00gg: mod xmmreg r/m

xmmreg by immediate

0110 0110:0000 1111:0111 00gg: 11 110 xmmreg: imm8

PSRA—Packed Shift Right Arithmetic

xmmreg1 by xmmreg2

0110 0110:0000 1111:1110 00gg: 11 xmmreg1 xmmreg2

xmmreg by memory

0110 0110:0000 1111:1110 00gg: mod xmmreg r/m

xmmreg by immediate

0110 0110:0000 1111:0111 00gg: 11 100 xmmreg: imm8

PSRLDQ—Shift Double Quadword Right Logical

xmmreg, imm8

0110 0110:00001111:01110011:11 011 xmmreg: imm8

PSRL—Packed Shift Right Logical

xmmreg1 by xmmreg2

0110 0110:0000 1111:1101 00gg: 11 xmmreg1 xmmreg2

xmmreg by memory

0110 0110:0000 1111:1101 00gg: mod xmmreg r/m

xmmreg by immediate

0110 0110:0000 1111:0111 00gg: 11 010 xmmreg: imm8

PSUBQ—Subtract Packed Quadword Integers

mmreg2 to mmreg1

0000 1111:11111 011:11 mmreg1 mmreg2

mem to mmreg

0000 1111:1111 1011: mod mmreg r/m

xmmreg2 to xmmreg1

0110 0110:0000 1111:1111 1011:11 xmmreg1 xmmreg2

mem to xmmreg

0110 0110:0000 1111:1111 1011: mod xmmreg r/m

PSUB—Subtract With Wrap-around

xmmreg2 from xmmreg1

0110 0110:0000 1111:1111 10gg: 11 xmmreg1 xmmreg2

memory from xmmreg

0110 0110:0000 1111:1111 10gg: mod xmmreg r/m

PSUBS—Subtract Signed With Saturation

xmmreg2 from xmmreg1

0110 0110:0000 1111:1110 10gg: 11 xmmreg1 xmmreg2

memory from xmmreg

0110 0110:0000 1111:1110 10gg: mod xmmreg r/m

PSUBUS—Subtract Unsigned With Saturation

xmmreg2 from xmmreg1

0000 1111:1101 10gg: 11 xmmreg1 xmmreg2

memory from xmmreg

0000 1111:1101 10gg: mod xmmreg r/m

PUNPCKH—Unpack High Data To Next Larger Type

xmmreg2 to xmmreg1

0110 0110:0000 1111:0110 10gg:11 xmmreg1 xmmreg2

mem to xmmreg

0110 0110:0000 1111:0110 10gg: mod xmmreg r/m

PUNPCKHQDQ—Unpack High Data

xmmreg2 to xmmreg1

0110 0110:0000 1111:0110 1101:11 xmmreg1 xmmreg2

mem to xmmreg

0110 0110:0000 1111:0110 1101: mod xmmreg r/m

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Table B-27. Formats and Encodings of SSE2 Integer Instructions (Contd.)

Instruction and Format

Encoding

PUNPCKL—Unpack Low Data To Next Larger Type

xmmreg2 to xmmreg1

0110 0110:0000 1111:0110 00gg:11 xmmreg1 xmmreg2

mem to xmmreg

0110 0110:0000 1111:0110 00gg: mod xmmreg r/m

PUNPCKLQDQ—Unpack Low Data

xmmreg2 to xmmreg1

0110 0110:0000 1111:0110 1100:11 xmmreg1 xmmreg2

mem to xmmreg

0110 0110:0000 1111:0110 1100: mod xmmreg r/m

PXOR—Bitwise Xor

xmmreg2 to xmmreg1

0110 0110:0000 1111:1110 1111: 11 xmmreg1 xmmreg2

memory to xmmreg

0110 0110:0000 1111:1110 1111: mod xmmreg r/m

Table B-28. Format and Encoding of SSE2 Cacheability Instructions

Instruction and Format

Encoding

MASKMOVDQU—Store Selected Bytes of Double Quadword

xmmreg2 to xmmreg1

0110 0110:0000 1111:1111 0111:11 xmmreg1 xmmreg2

CLFLUSH—Flush Cache Line

mem

0000 1111:1010 1110: mod 111 r/m

MOVNTPD—Store Packed Double Precision Floating-Point Values Using Non-Temporal Hint

xmmreg to mem

0110 0110:0000 1111:0010 1011: mod xmmreg r/m

MOVNTDQ—Store Double Quadword Using Non-Temporal Hint

xmmreg to mem

0110 0110:0000 1111:1110 0111: mod xmmreg r/m

MOVNTI—Store Doubleword Using Non-Temporal Hint

reg to mem

0000 1111:1100 0011: mod reg r/m

PAUSE—Spin Loop Hint

1111 0011:1001 0000

LFENCE—Load Fence

0000 1111:1010 1110: 11 101 000

MFENCE—Memory Fence

0000 1111:1010 1110: 11 110 000

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B.10 SSE3 FORMATS AND ENCODINGS TABLE

The tables in this section provide SSE3 formats and encodings. Some SSE3 instructions require a mandatory prefix

(66H, F2H, F3H) as part of the two-byte opcode. These prefixes are included in the tables.

When in IA-32e mode, use of the REX.R prefix permits instructions that use general purpose and XMM registers to

access additional registers. Some instructions require the REX.W prefix to promote the instruction to 64-bit opera-

tion. Instructions that require the REX.W prefix are listed (with their opcodes) in Section B.13.

Table B-29. Formats and Encodings of SSE3 Floating-Point Instructions

Instruction and Format

Encoding

ADDSUBPD—Add /Sub packed DP FP numbers from XMM2/Mem to XMM1

xmmreg2 to xmmreg1

01100110:00001111:11010000:11 xmmreg1 xmmreg2

mem to xmmreg

01100110:00001111:11010000: mod xmmreg r/m

ADDSUBPS—Add /Sub packed SP FP numbers from XMM2/Mem to XMM1

xmmreg2 to xmmreg1

11110010:00001111:11010000:11 xmmreg1 xmmreg2

mem to xmmreg

11110010:00001111:11010000: mod xmmreg r/m

HADDPD—Add horizontally packed DP FP numbers XMM2/Mem to XMM1

xmmreg2 to xmmreg1

01100110:00001111:01111100:11 xmmreg1 xmmreg2

mem to xmmreg

01100110:00001111:01111100: mod xmmreg r/m

HADDPS—Add horizontally packed SP FP numbers XMM2/Mem to XMM1

xmmreg2 to xmmreg1

11110010:00001111:01111100:11 xmmreg1 xmmreg2

mem to xmmreg

11110010:00001111:01111100: mod xmmreg r/m

HSUBPD—Sub horizontally packed DP FP numbers XMM2/Mem to XMM1

xmmreg2 to xmmreg1

01100110:00001111:01111101:11 xmmreg1 xmmreg2

mem to xmmreg

01100110:00001111:01111101: mod xmmreg r/m

HSUBPS—Sub horizontally packed SP FP numbers XMM2/Mem to XMM1

xmmreg2 to xmmreg1

11110010:00001111:01111101:11 xmmreg1 xmmreg2

mem to xmmreg

11110010:00001111:01111101: mod xmmreg r/m

Table B-30. Formats and Encodings for SSE3 Event Management Instructions

Instruction and Format

Encoding

MONITOR—Set up a linear address range to be monitored by hardware

eax, ecx, edx

0000 1111 : 0000 0001:11 001 000

MWAIT—Wait until write-back store performed within the range specified by the instruction MONITOR

eax, ecx

0000 1111 : 0000 0001:11 001 001

Table B-31. Formats and Encodings for SSE3 Integer and Move Instructions

Instruction and Format

Encoding

FISTTP—Store ST in int16 (chop) and pop

m16int

11011 111 : mod^A 001 r/m

FISTTP—Store ST in int32 (chop) and pop

m32int

11011 011 : mod^A 001 r/m

FISTTP—Store ST in int64 (chop) and pop

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Table B-31. Formats and Encodings for SSE3 Integer and Move Instructions (Contd.)

Instruction and Format

Encoding

m64int

11011 101 : mod^A 001 r/m

LDDQU—Load unaligned integer 128-bit

xmm, m128

11110010:00001111:11110000: mod^A xmmreg r/m

MOVDDUP—Move 64 bits representing one DP data from XMM2/Mem to XMM1 and duplicate

xmmreg2 to xmmreg1

11110010:00001111:00010010:11 xmmreg1 xmmreg2

mem to xmmreg

11110010:00001111:00010010: mod xmmreg r/m

MOVSHDUP—Move 128 bits representing 4 SP data from XMM2/Mem to XMM1 and duplicate high

xmmreg2 to xmmreg1

11110011:00001111:00010110:11 xmmreg1 xmmreg2

mem to xmmreg

11110011:00001111:00010110: mod xmmreg r/m

MOVSLDUP—Move 128 bits representing 4 SP data from XMM2/Mem to XMM1 and duplicate low

xmmreg2 to xmmreg1

11110011:00001111:00010010:11 xmmreg1 xmmreg2

mem to xmmreg

11110011:00001111:00010010: mod xmmreg r/m

B.11 SSSE3 FORMATS AND ENCODING TABLE

The tables in this section provide SSSE3 formats and encodings. Some SSSE3 instructions require a mandatory

prefix (66H) as part of the three-byte opcode. These prefixes are included in the table below.

Table B-32. Formats and Encodings for SSSE3 Instructions

Instruction and Format

Encoding

PABSB—Packed Absolute Value Bytes

mmreg2 to mmreg1

0000 1111:0011 1000: 0001 1100:11 mmreg1 mmreg2

mem to mmreg

0000 1111:0011 1000: 0001 1100: mod mmreg r/m

xmmreg2 to xmmreg1

0110 0110:0000 1111:0011 1000: 0001 1100:11 xmmreg1

xmmreg2

mem to xmmreg

0110 0110:0000 1111:0011 1000: 0001 1100: mod xmmreg r/m

PABSD—Packed Absolute Value Double Words

mmreg2 to mmreg1

0000 1111:0011 1000: 0001 1110:11 mmreg1 mmreg2

mem to mmreg

0000 1111:0011 1000: 0001 1110: mod mmreg r/m

xmmreg2 to xmmreg1

0110 0110:0000 1111:0011 1000: 0001 1110:11 xmmreg1

xmmreg2

mem to xmmreg

0110 0110:0000 1111:0011 1000: 0001 1110: mod xmmreg r/m

PABSW—Packed Absolute Value Words

mmreg2 to mmreg1

0000 1111:0011 1000: 0001 1101:11 mmreg1 mmreg2

mem to mmreg

0000 1111:0011 1000: 0001 1101: mod mmreg r/m

xmmreg2 to xmmreg1

0110 0110:0000 1111:0011 1000: 0001 1101:11 xmmreg1

xmmreg2

mem to xmmreg

0110 0110:0000 1111:0011 1000: 0001 1101: mod xmmreg r/m

PALIGNR—Packed Align Right

mmreg2 to mmreg1, imm8

0000 1111:0011 1010: 0000 1111:11 mmreg1 mmreg2: imm8

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Table B-32. Formats and Encodings for SSSE3 Instructions (Contd.)

Instruction and Format

Encoding

mem to mmreg, imm8

0000 1111:0011 1010: 0000 1111: mod mmreg r/m: imm8

xmmreg2 to xmmreg1, imm8

0110 0110:0000 1111:0011 1010: 0000 1111:11 xmmreg1

xmmreg2: imm8

mem to xmmreg, imm8

0110 0110:0000 1111:0011 1010: 0000 1111: mod xmmreg r/m:

imm8

PHADDD—Packed Horizontal Add Double Words

mmreg2 to mmreg1

0000 1111:0011 1000: 0000 0010:11 mmreg1 mmreg2

mem to mmreg

0000 1111:0011 1000: 0000 0010: mod mmreg r/m

xmmreg2 to xmmreg1

0110 0110:0000 1111:0011 1000: 0000 0010:11 xmmreg1

xmmreg2

mem to xmmreg

0110 0110:0000 1111:0011 1000: 0000 0010: mod xmmreg r/m

PHADDSW—Packed Horizontal Add and Saturate

mmreg2 to mmreg1

0000 1111:0011 1000: 0000 0011:11 mmreg1 mmreg2

mem to mmreg

0000 1111:0011 1000: 0000 0011: mod mmreg r/m

xmmreg2 to xmmreg1

0110 0110:0000 1111:0011 1000: 0000 0011:11 xmmreg1

xmmreg2

mem to xmmreg

0110 0110:0000 1111:0011 1000: 0000 0011: mod xmmreg r/m

PHADDW—Packed Horizontal Add Words

mmreg2 to mmreg1

0000 1111:0011 1000: 0000 0001:11 mmreg1 mmreg2

mem to mmreg

0000 1111:0011 1000: 0000 0001: mod mmreg r/m

xmmreg2 to xmmreg1

0110 0110:0000 1111:0011 1000: 0000 0001:11 xmmreg1

xmmreg2

mem to xmmreg

0110 0110:0000 1111:0011 1000: 0000 0001: mod xmmreg r/m

PHSUBD—Packed Horizontal Subtract Double Words

mmreg2 to mmreg1

0000 1111:0011 1000: 0000 0110:11 mmreg1 mmreg2

mem to mmreg

0000 1111:0011 1000: 0000 0110: mod mmreg r/m

xmmreg2 to xmmreg1

0110 0110:0000 1111:0011 1000: 0000 0110:11 xmmreg1

xmmreg2

mem to xmmreg

0110 0110:0000 1111:0011 1000: 0000 0110: mod xmmreg r/m

PHSUBSW—Packed Horizontal Subtract and Saturate

mmreg2 to mmreg1

0000 1111:0011 1000: 0000 0111:11 mmreg1 mmreg2

mem to mmreg

0000 1111:0011 1000: 0000 0111: mod mmreg r/m

xmmreg2 to xmmreg1

0110 0110:0000 1111:0011 1000: 0000 0111:11 xmmreg1

xmmreg2

mem to xmmreg

0110 0110:0000 1111:0011 1000: 0000 0111: mod xmmreg r/m

PHSUBW—Packed Horizontal Subtract Words

mmreg2 to mmreg1

0000 1111:0011 1000: 0000 0101:11 mmreg1 mmreg2

mem to mmreg

0000 1111:0011 1000: 0000 0101: mod mmreg r/m

xmmreg2 to xmmreg1

0110 0110:0000 1111:0011 1000: 0000 0101:11 xmmreg1

xmmreg2

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Table B-32. Formats and Encodings for SSSE3 Instructions (Contd.)

Instruction and Format

Encoding

mem to xmmreg

0110 0110:0000 1111:0011 1000: 0000 0101: mod xmmreg r/m

PMADDUBSW—Multiply and Add Packed Signed and Unsigned Bytes

mmreg2 to mmreg1

0000 1111:0011 1000: 0000 0100:11 mmreg1 mmreg2

mem to mmreg

0000 1111:0011 1000: 0000 0100: mod mmreg r/m

xmmreg2 to xmmreg1

0110 0110:0000 1111:0011 1000: 0000 0100:11 xmmreg1

xmmreg2

mem to xmmreg

0110 0110:0000 1111:0011 1000: 0000 0100: mod xmmreg r/m

PMULHRSW—Packed Multiply HIgn with Round and Scale

mmreg2 to mmreg1

0000 1111:0011 1000: 0000 1011:11 mmreg1 mmreg2

mem to mmreg

0000 1111:0011 1000: 0000 1011: mod mmreg r/m

xmmreg2 to xmmreg1

0110 0110:0000 1111:0011 1000: 0000 1011:11 xmmreg1

xmmreg2

mem to xmmreg

0110 0110:0000 1111:0011 1000: 0000 1011: mod xmmreg r/m

PSHUFB—Packed Shuffle Bytes

mmreg2 to mmreg1

0000 1111:0011 1000: 0000 0000:11 mmreg1 mmreg2

mem to mmreg

0000 1111:0011 1000: 0000 0000: mod mmreg r/m

xmmreg2 to xmmreg1

0110 0110:0000 1111:0011 1000: 0000 0000:11 xmmreg1

xmmreg2

mem to xmmreg

0110 0110:0000 1111:0011 1000: 0000 0000: mod xmmreg r/m

PSIGNB—Packed Sign Bytes

mmreg2 to mmreg1

0000 1111:0011 1000: 0000 1000:11 mmreg1 mmreg2

mem to mmreg

0000 1111:0011 1000: 0000 1000: mod mmreg r/m

xmmreg2 to xmmreg1

0110 0110:0000 1111:0011 1000: 0000 1000:11 xmmreg1

xmmreg2

mem to xmmreg

0110 0110:0000 1111:0011 1000: 0000 1000: mod xmmreg r/m

PSIGND—Packed Sign Double Words

mmreg2 to mmreg1

0000 1111:0011 1000: 0000 1010:11 mmreg1 mmreg2

mem to mmreg

0000 1111:0011 1000: 0000 1010: mod mmreg r/m

xmmreg2 to xmmreg1

0110 0110:0000 1111:0011 1000: 0000 1010:11 xmmreg1

xmmreg2

mem to xmmreg

0110 0110:0000 1111:0011 1000: 0000 1010: mod xmmreg r/m

PSIGNW—Packed Sign Words

mmreg2 to mmreg1

0000 1111:0011 1000: 0000 1001:11 mmreg1 mmreg2

mem to mmreg

0000 1111:0011 1000: 0000 1001: mod mmreg r/m

xmmreg2 to xmmreg1

0110 0110:0000 1111:0011 1000: 0000 1001:11 xmmreg1

xmmreg2

mem to xmmreg

0110 0110:0000 1111:0011 1000: 0000 1001: mod xmmreg r/m

B.12 AESNI AND PCLMULQDQ INSTRUCTION FORMATS AND ENCODINGS

Table B-33 shows the formats and encodings for AESNI and PCLMULQDQ instructions.

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Table B-33. Formats and Encodings of AESNI and PCLMULQDQ Instructions

Instruction and Format

Encoding

AESDEC—Perform One Round of an AES Decryption Flow

xmmreg2 to xmmreg1

0110 0110:0000 1111:0011 1000:1101 1110:11 xmmreg1

xmmreg2

mem to xmmreg

0110 0110:0000 1111:0011 1000:1101 1110: mod xmmreg r/m

AESDECLAST—Perform Last Round of an AES Decryption Flow

xmmreg2 to xmmreg1

0110 0110:0000 1111:0011 1000:1101 1111:11 xmmreg1

xmmreg2

mem to xmmreg

0110 0110:0000 1111:0011 1000:1101 1111: mod xmmreg r/m

AESENC—Perform One Round of an AES Encryption Flow

xmmreg2 to xmmreg1

0110 0110:0000 1111:0011 1000:1101 1100:11 xmmreg1

xmmreg2

mem to xmmreg

0110 0110:0000 1111:0011 1000:1101 1100: mod xmmreg r/m

AESENCLAST—Perform Last Round of an AES Encryption Flow

xmmreg2 to xmmreg1

0110 0110:0000 1111:0011 1000:1101 1101:11 xmmreg1

xmmreg2

mem to xmmreg

0110 0110:0000 1111:0011 1000:1101 1101: mod xmmreg r/m

AESIMC—Perform the AES InvMixColumn Transformation

xmmreg2 to xmmreg1

0110 0110:0000 1111:0011 1000:1101 1011:11 xmmreg1

xmmreg2

mem to xmmreg

0110 0110:0000 1111:0011 1000:1101 1011: mod xmmreg r/m

AESKEYGENASSIST—AES Round Key Generation Assist

xmmreg2 to xmmreg1, imm8

0110 0110:0000 1111:0011 1010:1101 1111:11 xmmreg1

xmmreg2: imm8

mem to xmmreg, imm8

0110 0110:0000 1111:0011 1010:1101 1111: mod xmmreg r/m:

imm8

PCLMULQDQ—Carry-Less Multiplication Quadword

xmmreg2 to xmmreg1, imm8

0110 0110:0000 1111:0011 1010:0100 0100:11 xmmreg1

xmmreg2: imm8

mem to xmmreg, imm8

0110 0110:0000 1111:0011 1010:0100 0100: mod xmmreg r/m:

imm8

B.13 SPECIAL ENCODINGS FOR 64-BIT MODE

The following Pentium, P6, MMX, SSE, SSE2, SSE3 instructions are promoted to 64-bit operation in IA-32e mode

by using REX.W. However, these entries are special cases that do not follow the general rules (specified in Section

B.4).

Table B-34. Special Case Instructions Promoted Using REX.W

Instruction and Format

Encoding

CMOVcc—Conditional Move

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INSTRUCTION FORMATS AND ENCODINGS

Table B-34. Special Case Instructions Promoted Using REX.W (Contd.)

Instruction and Format

Encoding

register2 to register1

0100 0R0B 0000 1111: 0100 tttn : 11 reg1 reg2

qwordregister2 to qwordregister1

0100 1R0B 0000 1111: 0100 tttn : 11 qwordreg1 qwordreg2

memory to register

0100 0RXB 0000 1111 : 0100 tttn : mod reg r/m

memory64 to qwordregister

0100 1RXB 0000 1111 : 0100 tttn : mod qwordreg r/m

CVTSD2SI—Convert Scalar Double Precision Floating-Point Value to Doubleword Integer

xmmreg to r32

0100 0R0B 1111 0010:0000 1111:0010 1101:11 r32

xmmreg

xmmreg to r64

0100 1R0B 1111 0010:0000 1111:0010 1101:11 r64

xmmreg

mem64 to r32

0100 0R0XB 1111 0010:0000 1111:0010 1101: mod r32 r/m

mem64 to r64

0100 1RXB 1111 0010:0000 1111:0010 1101: mod r64 r/m

CVTSI2SS—Convert Doubleword Integer to Scalar Single Precision Floating-Point Value

r32 to xmmreg1

0100 0R0B 1111 0011:0000 1111:0010 1010:11 xmmreg

r32

r64 to xmmreg1

0100 1R0B 1111 0011:0000 1111:0010 1010:11 xmmreg

r64

mem to xmmreg

0100 0RXB 1111 0011:0000 1111:0010 1010: mod xmmreg

r/m

mem64 to xmmreg

0100 1RXB 1111 0011:0000 1111:0010 1010: mod xmmreg

r/m

CVTSI2SD—Convert Doubleword Integer to Scalar Double Precision Floating-Point Value

r32 to xmmreg1

0100 0R0B 1111 0010:0000 1111:0010 1010:11 xmmreg

r32

r64 to xmmreg1

0100 1R0B 1111 0010:0000 1111:0010 1010:11 xmmreg

r64

mem to xmmreg

0100 0RXB 1111 0010:0000 1111:00101 010: mod xmmreg

r/m

mem64 to xmmreg

0100 1RXB 1111 0010:0000 1111:0010 1010: mod xmmreg

r/m

CVTSS2SI—Convert Scalar Single Precision Floating-Point Value to Doubleword Integer

xmmreg to r32

0100 0R0B 1111 0011:0000 1111:0010 1101:11 r32

xmmreg

xmmreg to r64

0100 1R0B 1111 0011:0000 1111:0010 1101:11 r64

xmmreg

mem to r32

0100 0RXB 11110011:00001111:00101101: mod r32 r/m

mem32 to r64

0100 1RXB 1111 0011:0000 1111:0010 1101: mod r64 r/m

CVTTSD2SI—Convert with Truncation Scalar Double Precision Floating-Point Value to Doubleword Integer

xmmreg to r32

0100 0R0B 11110010:00001111:00101100:11 r32 xmmreg

xmmreg to r64

0100 1R0B 1111 0010:0000 1111:0010 1100:11 r64

xmmreg

mem64 to r32

0100 0RXB 1111 0010:0000 1111:0010 1100: mod r32 r/m

mem64 to r64

0100 1RXB 1111 0010:0000 1111:0010 1100: mod r64 r/m

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Table B-34. Special Case Instructions Promoted Using REX.W (Contd.)

Instruction and Format

Encoding

CVTTSS2SI—Convert with Truncation Scalar Single Precision Floating-Point Value to Doubleword Integer

xmmreg to r32

0100 0R0B 1111 0011:0000 1111:0010 1100:11 r32

xmmreg1

xmmreg to r64

0100 1R0B 1111 0011:0000 1111:0010 1100:11 r64

xmmreg1

mem to r32

0100 0RXB 1111 0011:0000 1111:0010 1100: mod r32 r/m

mem32 to r64

0100 1RXB 1111 0011:0000 1111:0010 1100: mod r64 r/m

MOVD/MOVQ—Move doubleword

reg to mmxreg

0100 0R0B 0000 1111:0110 1110: 11 mmxreg reg

qwordreg to mmxreg

0100 1R0B 0000 1111:0110 1110: 11 mmxreg qwordreg

reg from mmxreg

0100 0R0B 0000 1111:0111 1110: 11 mmxreg reg

qwordreg from mmxreg

0100 1R0B 0000 1111:0111 1110: 11 mmxreg qwordreg

mem to mmxreg

0100 0RXB 0000 1111:0110 1110: mod mmxreg r/m

mem64 to mmxreg

0100 1RXB 0000 1111:0110 1110: mod mmxreg r/m

mem from mmxreg

0100 0RXB 0000 1111:0111 1110: mod mmxreg r/m

mem64 from mmxreg

0100 1RXB 0000 1111:0111 1110: mod mmxreg r/m

mmxreg with memory

0100 0RXB 0000 1111:0110 01gg: mod mmxreg r/m

MOVMSKPS—Extract Packed Single Precision Floating-Point Sign Mask

xmmreg to r32

0100 0R0B 0000 1111:0101 0000:11 r32 xmmreg

xmmreg to r64

0100 1R0B 00001111:01010000:11 r64 xmmreg

PEXTRW—Extract Word

mmreg to reg32, imm8

0100 0R0B 0000 1111:1100 0101:11 r32 mmreg: imm8

mmreg to reg64, imm8

0100 1R0B 0000 1111:1100 0101:11 r64 mmreg: imm8

xmmreg to reg32, imm8

0100 0R0B 0110 0110 0000 1111:1100 0101:11 r32

xmmreg: imm8

xmmreg to reg64, imm8

0100 1R0B 0110 0110 0000 1111:1100 0101:11 r64

xmmreg: imm8

PINSRW—Insert Word

reg32 to mmreg, imm8

0100 0R0B 0000 1111:1100 0100:11 mmreg r32: imm8

reg64 to mmreg, imm8

0100 1R0B 0000 1111:1100 0100:11 mmreg r64: imm8

m16 to mmreg, imm8

0100 0R0B 0000 1111:1100 0100 mod mmreg r/m: imm8

m16 to mmreg, imm8

0100 1RXB 0000 1111:11000100 mod mmreg r/m: imm8

reg32 to xmmreg, imm8

0100 0RXB 0110 0110 0000 1111:1100 0100:11 xmmreg

r32: imm8

reg64 to xmmreg, imm8

0100 0RXB 0110 0110 0000 1111:1100 0100:11 xmmreg

r64: imm8

m16 to xmmreg, imm8

0100 0RXB 0110 0110 0000 1111:1100 0100 mod xmmreg

r/m: imm8

m16 to xmmreg, imm8

0100 1RXB 0110 0110 0000 1111:1100 0100 mod xmmreg

r/m: imm8

PMOVMSKB—Move Byte Mask To Integer

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INSTRUCTION FORMATS AND ENCODINGS

Table B-34. Special Case Instructions Promoted Using REX.W (Contd.)

Instruction and Format

Encoding

mmreg to reg32

0100 0RXB 0000 1111:1101 0111:11 r32 mmreg

mmreg to reg64

0100 1R0B 0000 1111:1101 0111:11 r64 mmreg

xmmreg to reg32

0100 0RXB 0110 0110 0000 1111:1101 0111:11 r32 mmreg

xmmreg to reg64

0110 0110 0000 1111:1101 0111:11 r64 xmmreg

B.14 SSE4.1 FORMATS AND ENCODING TABLE

The tables in this section provide SSE4.1 formats and encodings. Some SSE4.1 instructions require a mandatory

prefix (66H, F2H, F3H) as part of the three-byte opcode. These prefixes are included in the tables.

In 64-bit mode, some instructions requires REX.W, the byte sequence of REX.W prefix in the opcode sequence is

shown.

Table B-35. Encodings of SSE4.1 instructions

Instruction and Format

Encoding

BLENDPD — Blend Packed Double Precision Floats

xmmreg2 to xmmreg1

0110 0110:0000 1111:0011 1010: 0000 1101:11 xmmreg1

xmmreg2

mem to xmmreg

0110 0110:0000 1111:0011 1010: 0000 1101: mod xmmreg r/m

BLENDPS — Blend Packed Single Precision Floats

xmmreg2 to xmmreg1

0110 0110:0000 1111:0011 1010: 0000 1100:11 xmmreg1

xmmreg2

mem to xmmreg

0110 0110:0000 1111:0011 1010: 0000 1100: mod xmmreg r/m

BLENDVPD — Variable Blend Packed Double Precision Floats

xmmreg2 to xmmreg1 <xmm0>

0110 0110:0000 1111:0011 1000: 0001 0101:11 xmmreg1

xmmreg2

mem to xmmreg <xmm0>

0110 0110:0000 1111:0011 1000: 0001 0101: mod xmmreg r/m

BLENDVPS — Variable Blend Packed Single Precision Floats

xmmreg2 to xmmreg1 <xmm0>

0110 0110:0000 1111:0011 1000: 0001 0100:11 xmmreg1

xmmreg2

mem to xmmreg <xmm0>

0110 0110:0000 1111:0011 1000: 0001 0100: mod xmmreg r/m

DPPD — Packed Double Precision Dot Products

xmmreg2 to xmmreg1, imm8

0110 0110:0000 1111:0011 1010: 0100 0001:11 xmmreg1

xmmreg2: imm8

mem to xmmreg, imm8

0110 0110:0000 1111:0011 1010: 0100 0001: mod xmmreg r/m:

imm8

DPPS — Packed Single Precision Dot Products

xmmreg2 to xmmreg1, imm8

0110 0110:0000 1111:0011 1010: 0100 0000:11 xmmreg1

xmmreg2: imm8

mem to xmmreg, imm8

0110 0110:0000 1111:0011 1010: 0100 0000: mod xmmreg r/m:

imm8

EXTRACTPS — Extract From Packed Single Precision Floats

reg from xmmreg , imm8

0110 0110:0000 1111:0011 1010: 0001 0111:11 xmmreg reg:

imm8

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INSTRUCTION FORMATS AND ENCODINGS

Table B-35. Encodings of SSE4.1 instructions

Instruction and Format

Encoding

mem from xmmreg , imm8

0110 0110:0000 1111:0011 1010: 0001 0111: mod xmmreg r/m:

imm8

INSERTPS — Insert Into Packed Single Precision Floats

xmmreg2 to xmmreg1, imm8

0110 0110:0000 1111:0011 1010: 0010 0001:11 xmmreg1

xmmreg2: imm8

mem to xmmreg, imm8

0110 0110:0000 1111:0011 1010: 0010 0001: mod xmmreg r/m:

imm8

MOVNTDQA — Load Double Quadword Non-temporal Aligned

m128 to xmmreg

0110 0110:0000 1111:0011 1000: 0010 1010:11 r/m xmmreg2

MPSADBW — Multiple Packed Sums of Absolute Difference

xmmreg2 to xmmreg1, imm8

0110 0110:0000 1111:0011 1010: 0100 0010:11 xmmreg1

xmmreg2: imm8

mem to xmmreg, imm8

0110 0110:0000 1111:0011 1010: 0100 0010: mod xmmreg r/m:

imm8

PACKUSDW — Pack with Unsigned Saturation

xmmreg2 to xmmreg1

0110 0110:0000 1111:0011 1000: 0010 1011:11 xmmreg1

xmmreg2

mem to xmmreg

0110 0110:0000 1111:0011 1000: 0010 1011: mod xmmreg r/m

PBLENDVB — Variable Blend Packed Bytes

xmmreg2 to xmmreg1 <xmm0>

0110 0110:0000 1111:0011 1000: 0001 0000:11 xmmreg1

xmmreg2

mem to xmmreg <xmm0>

0110 0110:0000 1111:0011 1000: 0001 0000: mod xmmreg r/m

PBLENDW — Blend Packed Words

xmmreg2 to xmmreg1, imm8

0110 0110:0000 1111:0011 1010: 0001 1110:11 xmmreg1

xmmreg2: imm8

mem to xmmreg, imm8

0110 0110:0000 1111:0011 1010: 0000 1110: mod xmmreg r/m:

imm8

PCMPEQQ — Compare Packed Qword Data of Equal

xmmreg2 to xmmreg1

0110 0110:0000 1111:0011 1000: 0010 1001:11 xmmreg1

xmmreg2

mem to xmmreg

0110 0110:0000 1111:0011 1000: 0010 1001: mod xmmreg r/m

PEXTRB — Extract Byte

reg from xmmreg , imm8

0110 0110:0000 1111:0011 1010: 0001 0100:11 xmmreg reg:

imm8

xmmreg to mem, imm8

0110 0110:0000 1111:0011 1010: 0001 0100: mod xmmreg r/m:

imm8

PEXTRD — Extract DWord

reg from xmmreg, imm8

0110 0110:0000 1111:0011 1010: 0001 0110:11 xmmreg reg:

imm8

xmmreg to mem, imm8

0110 0110:0000 1111:0011 1010: 0001 0110: mod

xmmreg r/m: imm8

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INSTRUCTION FORMATS AND ENCODINGS

Table B-35. Encodings of SSE4.1 instructions

Instruction and Format

Encoding

PEXTRQ — Extract QWord

r64 from xmmreg, imm8

0110 0110:REX.W:0000 1111:0011 1010: 0001 0110:11 xmmreg

reg: imm8

m64 from xmmreg, imm8

0110 0110:REX.W:0000 1111:0011 1010: 0001 0110: mod

xmmreg r/m: imm8

PEXTRW — Extract Word

reg from xmmreg, imm8

0110 0110:0000 1111:0011 1010: 0001 0101:11 reg xmmreg:

imm8

mem from xmmreg, imm8

0110 0110:0000 1111:0011 1010: 0001 0101: mod xmmreg r/m:

imm8

PHMINPOSUW — Packed Horizontal Word Minimum

xmmreg2 to xmmreg1

0110 0110:0000 1111:0011 1000: 0100 0001:11 xmmreg1

xmmreg2

mem to xmmreg

0110 0110:0000 1111:0011 1000: 0100 0001: mod xmmreg r/m

PINSRB — Extract Byte

reg to xmmreg, imm8

0110 0110:0000 1111:0011 1010: 0010 0000:11 xmmreg reg:

imm8

mem to xmmreg, imm8

0110 0110:0000 1111:0011 1010: 0010 0000: mod xmmreg r/m:

imm8

PINSRD — Extract DWord

reg to xmmreg, imm8

0110 0110:0000 1111:0011 1010: 0010 0010:11 xmmreg reg:

imm8

mem to xmmreg, imm8

0110 0110:0000 1111:0011 1010: 0010 0010: mod xmmreg r/m:

imm8

PINSRQ — Extract QWord

r64 to xmmreg, imm8

0110 0110:REX.W:0000 1111:0011 1010: 0010 0010:11 xmmreg

reg: imm8

m64 to xmmreg, imm8

0110 0110:REX.W:0000 1111:0011 1010: 0010 0010: mod

xmmreg r/m: imm8

PMAXSB — Maximum of Packed Signed Byte Integers

xmmreg2 to xmmreg1

0110 0110:0000 1111:0011 1000: 0011 1100:11 xmmreg1

xmmreg2

mem to xmmreg

0110 0110:0000 1111:0011 1000: 0011 1100: mod xmmreg r/m

PMAXSD — Maximum of Packed Signed Dword Integers

xmmreg2 to xmmreg1

0110 0110:0000 1111:0011 1000: 0011 1101:11 xmmreg1

xmmreg2

mem to xmmreg

0110 0110:0000 1111:0011 1000: 0011 1101: mod xmmreg r/m

PMAXUD — Maximum of Packed Unsigned Dword Integers

xmmreg2 to xmmreg1

0110 0110:0000 1111:0011 1000: 0011 1111:11 xmmreg1

xmmreg2

mem to xmmreg

0110 0110:0000 1111:0011 1000: 0011 1111: mod xmmreg r/m

PMAXUW — Maximum of Packed Unsigned Word Integers

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Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 124