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Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 122

SAFER MODE EXTENSIONS REFERENCE

GETSEC[SEXIT]—Exit Measured Environment

Opcode

Instruction

Description

NP 0F 37

GETSEC[SEXIT]

Exit measured environment.

(EAX=5)

Description

The GETSEC[SEXIT] instruction initiates an exit of a measured environment established by GETSEC[SENTER]. The

SEXIT leaf of GETSEC is selected with EAX set to 5 at execution. This instruction leaf sends a message to all logical

processors in the platform to signal the measured environment exit.

There are restrictions enforced by the processor for the execution of the GETSEC[SEXIT] instruction:

• Execution is not allowed unless the processor is in protected mode (CR0.PE = 1) with CPL = 0 and EFLAGS.VM

= 0.

• The processor must be in a measured environment as launched by a previous GETSEC[SENTER] instruction,

but not still in authenticated code execution mode.

• To avoid potential interoperability conflicts between modes, the processor is not allowed to execute this

instruction if it currently is in SMM or in VMX operation.

• To ensure consistent handling of SIPI messages, the processor executing the GETSEC[SEXIT] instruction must

also be designated the BSP (bootstrap processor) as defined by the register bit IA32_APIC_BASE.BSP (bit 8).

Failure to abide by the above conditions results in the processor signaling a general protection violation.

This instruction initiates a sequence to rendezvous the RLPs with the ILP. It then clears the internal processor flag

indicating the processor is operating in a measured environment.

In response to a message signaling the completion of rendezvous, all RLPs restart execution with the instruction

that was to be executed at the time GETSEC[SEXIT] was recognized. This applies to all processor conditions, with

the following exceptions:

• If an RLP executed HLT and was in this halt state at the time of the message initiated by GETSEC[SEXIT], then

execution resumes in the halt state.

• If an RLP was executing MWAIT, then a message initiated by GETSEC[SEXIT] causes an exit of the MWAIT state,

falling through to the next instruction.

• If an RLP was executing an intermediate iteration of a string instruction, then the processor resumes execution

of the string instruction at the point which the message initiated by GETSEC[SEXIT] was recognized.

• If an RLP is still in the SENTER sleep state (never awakened with GETSEC[WAKEUP]), it will be sent to the wait-

for-SIPI state after first clearing the bootstrap processor indicator flag (IA32_APIC_BASE.BSP) and any

pending SIPI state. In this case, such RLPs are initialized to an architectural state consistent with having taken

a soft reset using the INIT# pin.

Prior to completion of the GETSEC[SEXIT] operation, both the ILP and any active RLPs unmask the response of the

external event signals INIT#, A20M, NMI#, and SMI#. This unmasking is performed unconditionally to recognize

pin events which are masked after a GETSEC[SENTER]. The state of A20M is unmasked, as the A20M pin is not

recognized while the measured environment is active.

On a successful exit of the measured environment, the ILP re-locks the Intel® TXT-capable chipset private config-

uration space. GETSEC[SEXIT] does not affect the content of any PCR.

At completion of GETSEC[SEXIT] by the ILP, execution proceeds to the next instruction. Since EFLAGS and the

debug register state are not modified by this instruction, a pending trap condition is free to be signaled if previously

enabled.

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GETSEC[SEXIT]—Exit Measured Environment

SAFER MODE EXTENSIONS REFERENCE

GETSEC[PARAMETERS]—Report the SMX Parameters

Opcode

Instruction

Description

NP 0F 37

GETSEC[PARAMETERS]

Report the SMX parameters.

(EAX=6)

The parameters index is input in EBX with the result returned in EAX, EBX, and ECX.

Description

The GETSEC[PARAMETERS] instruction returns specific parameter information for SMX features supported by the

processor. Parameter information is returned in EAX, EBX, and ECX, with the input parameter selected using EBX.

Software retrieves parameter information by searching with an input index for EBX starting at 0, and then reading

the returned results in EAX, EBX, and ECX. EAX[4:0] is designated to return a parameter type field indicating if a

parameter is available and what type it is. If EAX[4:0] is returned with 0, this designates a null parameter and indi-

cates no more parameters are available.

Table 7-7 defines the parameter types supported in current and future implementations.

Table 7-7. SMX Reporting Parameters Format

Parameter

Type EAX[4:0]

Parameter Description

EAX[31:5]

EBX[31:0]

ECX[31:0]

0

NULL

Reserved (0 returned)

Reserved (unmodified)

Reserved (unmodified)

1

Supported AC module

Reserved (0 returned)

Version comparison mask

Version numbers

versions

supported

2

Max size of authenticated

Multiply by 32 for size in

Reserved (unmodified)

Reserved (unmodified)

code execution area

bytes

3

External memory types

Memory type bit mask

Reserved (unmodified)

Reserved (unmodified)

supported during AC mode

4

Selective SENTER

EAX[14:8] correspond to

Reserved (unmodified)

Reserved (unmodified)

functionality control

available SENTER function

disable controls

5

TXT extensions support

TXT Feature Extensions

Reserved

Reserved

Flags (see Table )

6-31

Undefined

Reserved (unmodified)

Reserved (unmodified)

Reserved (unmodified)

GETSEC[PARAMETERS]—Report the SMX Parameters

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SAFER MODE EXTENSIONS REFERENCE

Table 7-8. TXT Feature Extensions Flags

Bit

Definition

Description

5

Processor based S-CRTM

Returns 1 if this processor implements a processor-rooted S-CRTM capability and 0

support

if not (S-CRTM is rooted in BIOS).

This flag cannot be used to infer whether the chipset supports TXT or whether the

processor support SMX.

6

Machine Check Handling

Returns 1 if it machine check status registers can be preserved through ENTERACCS

and SENTER. If this bit is 1, the caller of ENTERACCS and SENTER is not required to

clear machine check error status bits before invoking these GETSEC leaves.

If this bit returns 0, the caller of ENTERACCS and SENTER must clear all machine

check error status bits before invoking these GETSEC leaves.

31:7

Reserved

Reserved for future use. Will return 0.

Supported AC module versions (as defined by the AC module HeaderVersion field) can be determined for a partic-

ular SMX capable processor by the type 1 parameter. Using EBX to index through the available parameters reported

by GETSEC[PARAMETERS] for each unique parameter set returned for type 1, software can determine the complete

list of AC module version(s) supported.

For each parameter set, EBX returns the comparison mask and ECX returns the available HeaderVersion field

values supported, after AND'ing the target HeaderVersion with the comparison mask. Software can then determine

if a particular AC module version is supported by following the pseudo-code search routine given below:

parameter_search_index= 0

do {

EBX= parameter_search_index++

EAX= 6

GETSEC

if (EAX[4:0] = 1) {

if ((version_query & EBX) = ECX) {

version_is_supported= 1

break

}

}

} while (EAX[4:0] ≠ 0)

If only AC modules with a HeaderVersion of 0 are supported by the processor, then only one parameter set of type

1 will be returned, as follows: EAX = 00000001H,

EBX = FFFFFFFFH and ECX = 00000000H.

The maximum capacity for an authenticated code execution area supported by the processor is reported with the

parameter type of 2. The maximum supported size in bytes is determined by multiplying the returned size in

EAX[31:5] by 32. Thus, for a maximum supported authenticated RAM size of 32KBytes, EAX returns with

00008002H.

Supportable memory types for memory mapped outside of the authenticated code execution area are reported

with the parameter type of 3. While is active, as initiated by the GETSEC functions SENTER and ENTERACCS and

terminated by EXITAC, there are restrictions on what memory types are allowed for the rest of system memory. It

is the responsibility of the system software to initialize the memory type range register (MTRR) MSRs and/or the

page attribute table (PAT) to only map memory types consistent with the reporting of this parameter. The reporting

of supportable memory types of external memory is indicated using a bit map returned in EAX[31:8]. These bit

positions correspond to the memory type encodings defined for the MTRR MSR and PAT programming. See

Table 7-9.

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GETSEC[PARAMETERS]—Report the SMX Parameters

SAFER MODE EXTENSIONS REFERENCE

The parameter type of 4 is used for enumerating the availability of selective GETSEC[SENTER] function disable

controls. If a 1 is reported in bits 14:8 of the returned parameter EAX, then this indicates a disable control capa-

bility exists with SENTER for a particular function. The enumerated field in bits 14:8 corresponds to use of the EDX

input parameter bits 6:0 for SENTER. If an enumerated field bit is set to 1, then the corresponding EDX input

parameter bit of EDX may be set to 1 to disable that designated function. If the enumerated field bit is 0 or this

parameter is not reported, then no disable capability exists with the corresponding EDX input parameter for

SENTER, and EDX bit(s) must be cleared to 0 to enable execution of SENTER. If no selective disable capability for

SENTER exists as enumerated, then the corresponding bits in the IA32_FEATURE_CONTROL MSR bits 14:8 must

also be programmed to 1 if the SENTER global enable bit 15 of the MSR is set. This is required to enable future

extensibility of SENTER selective disable capability with respect to potentially separate software initialization of the

MSR.

Table 7-9. External Memory Types Using Parameter 3

EAX Bit Position

Parameter Description

8

Uncacheable (UC)

9

Write Combining (WC)

11:10

Reserved

12

Write-through (WT)

13

Write-protected (WP)

14

Write-back (WB)

31:15

Reserved

If the GETSEC[PARAMETERS] leaf or specific parameter is not present for a given SMX capable processor, then

default parameter values should be assumed. These are defined in Table 7-10.

Table 7-10. Default Parameter Values

Parameter Type EAX[4:0]

Default Setting

Parameter Description

1

0.0 only

Supported AC module versions.

2

32 KBytes

Authenticated code execution area size.

3

UC only

External memory types supported during AC execution mode.

4

None

Available SENTER selective disable controls.

Operation

(* example of a processor supporting only a 0.0 HeaderVersion, 32K ACRAM size, memory types UC and WC *)

IF (CR4.SMXE=0)

THEN #UD;

ELSE IF (in VMX non-root operation)

THEN VM Exit (reason=”GETSEC instruction”);

ELSE IF (GETSEC leaf unsupported)

THEN #UD;

(* example of a processor supporting a 0.0 HeaderVersion *)

IF (EBX=0) THEN

EAX := 00000001h;

EBX := FFFFFFFFh;

GETSEC[PARAMETERS]—Report the SMX Parameters

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SAFER MODE EXTENSIONS REFERENCE

GETSEC[SMCTRL]—SMX Mode Control

Opcode

Instruction

Description

NP 0F 37 (EAX = 7)

GETSEC[SMCTRL]

Perform specified SMX mode control as selected with the input EBX.

Description

The GETSEC[SMCTRL] instruction is available for performing certain SMX specific mode control operations. The

operation to be performed is selected through the input register EBX. Currently only an input value in EBX of 0 is

supported. All other EBX settings will result in the signaling of a general protection violation.

If EBX is set to 0, then the SMCTRL leaf is used to re-enable SMI events. SMI is masked by the ILP executing the

GETSEC[SENTER] instruction (SMI is also masked in the responding logical processors in response to SENTER

rendezvous messages.). The determination of when this instruction is allowed and the events that are unmasked

is dependent on the processor context (See Table 7-11). For brevity, the usage of SMCTRL where EBX=0 will be

referred to as GETSEC[SMCTRL(0)].

As part of support for launching a measured environment, the SMI, NMI, and INIT events are masked after

GETSEC[SENTER], and remain masked after exiting authenticated execution mode. Unmasking these events

should be accompanied by securely enabling these event handlers. These security concerns can be addressed in

VMX operation by a MVMM.

The VM monitor can choose two approaches:

• In a dual monitor approach, the executive software will set up an SMM monitor in parallel to the executive VMM

(i.e., the MVMM), see Chapter 32, “System Management Mode‚” of Intel^® 64 and IA-32 Architectures Software

Developer’s Manual, Volume 3C. The SMM monitor is dedicated to handling SMI events without compromising

the security of the MVMM. This usage model of handling SMI while a measured environment is active does not

require the use of GETSEC[SMCTRL(0)] as event re-enabling after the VMX environment launch is handled

implicitly and through separate VMX based controls.

• If a dedicated SMM monitor will not be established and SMIs are to be handled within the measured

environment, then GETSEC[SMCTRL(0)] can be used by the executive software to re-enable SMI that has been

masked as a result of SENTER.

Table 7-11 defines the processor context in which GETSEC[SMCTRL(0)] can be used and which events will be

unmasked. Note that the events that are unmasked are dependent upon the currently operating processor context.

Table 7-11. Supported Actions for GETSEC[SMCTRL(0)]

ILP Mode of Operation

SMCTRL execution action

In VMX non-root operation

VM exit

SENTERFLAG = 0

#GP(0), illegal context

In authenticated code execution mode

#GP(0), illegal context

(ACMODEFLAG = 1)

SENTERFLAG = 1, not in VMX operation, not in

Unmask SMI

SMM

SENTERFLAG = 1, in VMX root operation, not in

Unmask SMI if SMM monitor is not configured, otherwise #GP(0)

SMM

SENTERFLAG = 1, In VMX root operation, in SMM

#GP(0), illegal context

GETSEC[SMCTRL]—SMX Mode Control

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SAFER MODE EXTENSIONS REFERENCE

GETSEC[WAKEUP]—Wake Up Sleeping Processors in Measured Environment

Opcode

Instruction

Description

NP 0F 37

GETSEC[WAKEUP]

Wake up the responding logical processors from the SENTER sleep state.

(EAX=8)

Description

The GETSEC[WAKEUP] leaf function broadcasts a wake-up message to all logical processors currently in the

SENTER sleep state. This GETSEC leaf must be executed only by the ILP, in order to wake-up the RLPs. Responding

logical processors (RLPs) enter the SENTER sleep state after completion of the SENTER rendezvous sequence.

The GETSEC[WAKEUP] instruction may only be executed:

• In a measured environment as initiated by execution of GETSEC[SENTER].

• Outside of authenticated code execution mode.

• Execution is not allowed unless the processor is in protected mode with CPL = 0 and EFLAGS.VM = 0.

• In addition, the logical processor must be designated as the boot-strap processor as configured by setting

IA32_APIC_BASE.BSP = 1.

If these conditions are not met, attempts to execute GETSEC[WAKEUP] result in a general protection violation.

An RLP exits the SENTER sleep state and start execution in response to a WAKEUP signal initiated by ILP’s execution

of GETSEC[WAKEUP]. The RLP retrieves a pointer to a data structure that contains information to enable execution

from a defined entry point. This data structure is located using a physical address held in the Intel^® TXT-capable

chipset configuration register LT.MLE.JOIN. The register is publicly writable in the chipset by all processors and is

not restricted by the Intel^® TXT-capable chipset configuration register lock status. The format of this data structure

is defined in Table 7-12.

Table 7-12. RLP MVMM JOIN Data Structure

Offset

Field

0

GDT limit

4

GDT base pointer

8

Segment selector initializer

12

EIP

The MLE JOIN data structure contains the information necessary to initialize RLP processor state and permit the

processor to join the measured environment. The GDTR, LIP, and CS, DS, SS, and ES selector values are initialized

using this data structure. The CS selector index is derived directly from the segment selector initializer field; DS,

SS, and ES selectors are initialized to CS+8. The segment descriptor fields are initialized implicitly with BASE = 0,

LIMIT = FFFFFH, G = 1, D = 1, P = 1, S = 1; read/write/access for DS, SS, and ES; and execute/read/access for

CS. It is the responsibility of external software to establish a GDT pointed to by the MLE JOIN data structure that

contains descriptor entries consistent with the implicit settings initialized by the processor (see Table 7-6). Certain

states from the content of Table 7-12 are checked for consistency by the processor prior to execution. A failure of

any consistency check results in the RLP aborting entry into the protected environment and signaling an Intel® TXT

shutdown condition. The specific checks performed are documented later in this section. After successful comple-

tion of processor consistency checks and subsequent initialization, RLP execution in the measured environment

begins from the entry point at offset 12 (as indicated in Table 7-12).

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GETSEC[WAKEUP]—Wake Up Sleeping Processors in Measured Environment

CHAPTER 8

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™

PROCESSORS

This chapter describes the instruction set that is unique to Intel^® Xeon Phi™ Processors based on the Knights

Landing and Knights Mill microarchitectures. The set is not supported in any other Intel processors. Included are

Intel^® AVX-512 instructions. For additional instructions supported on these processors, see Chapter 3, “Instruction

Set Reference, A-L”; Chapter 4, “Instruction Set Reference, M-U”; Chapter 5, “Instruction Set Reference, V”; and

Chapter 6, “Instruction Set Reference, W-Z.”

Vol. 2D

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INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

PREFETCHWT1—Prefetch Vector Data Into Caches With Intent to Write and T1 Hint

Opcode/

Op/

64/32 bit

CPUID Feature

Description

Instruction

En

Mode

Flag

Support

0F 0D /2

M

V/V

PREFETCHWT1

Move data from m8 closer to the processor using T1 hint

PREFETCHWT1 m8

with intent to write.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

M

ModRM:r/m (r)

N/A

N/A

N/A

Description

Fetches the line of data from memory that contains the byte specified with the source operand to a location in the

cache hierarchy specified by an intent to write hint (so that data is brought into ‘Exclusive’ state via a request for

ownership) and a locality hint:

• T1 (temporal data with respect to first level cache)—prefetch data into the second level cache.

The source operand is a byte memory location. (The locality hints are encoded into the machine level instruction

using bits 3 through 5 of the ModR/M byte. Use of any ModR/M value other than the specified ones will lead to

unpredictable behavior.)

If the line selected is already present in the cache hierarchy at a level closer to the processor, no data movement

occurs. Prefetches from uncacheable or WC memory are ignored.

The PREFETCHWT1 instruction is merely a hint and does not affect program behavior. If executed, this instruction

moves data closer to the processor in anticipation of future use.

The implementation of prefetch locality hints is implementation-dependent, and can be overloaded or ignored by a

processor implementation. The amount of data prefetched is also processor implementation-dependent. It will,

however, be a minimum of 32 bytes. Additional details of the implementation-dependent locality hints are

described in Section 9.5, “Memory Optimization Using Prefetch” of the Intel® 64 and IA-32 Architectures Optimi-

zation Reference Manual.

It should be noted that processors are free to speculatively fetch and cache data from system memory regions that

are assigned a memory-type that permits speculative reads (that is, the WB, WC, and WT memory types). A

PREFETCHWT1 instruction is considered a hint to this speculative behavior. Because this speculative fetching can

occur at any time and is not tied to instruction execution, a PREFETCHWT1 instruction is not ordered with respect

to the fence instructions (MFENCE, SFENCE, and LFENCE) or locked memory references. A PREFETCHWT1 instruc-

tion is also unordered with respect to CLFLUSH and CLFLUSHOPT instructions, other PREFETCHWT1 instructions, or

any other general instruction. It is ordered with respect to serializing instructions such as CPUID, WRMSR, OUT, and

MOV CR.

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

Operation

PREFETCH(mem, Level, State) Prefetches a byte memory location pointed by ‘mem’ into the cache level specified by ‘Level’; a request

for exclusive/ownership is done if ‘State’ is 1. Note that the memory location ignore cache line splits. This operation is considered a

hint for the processor and may be skipped depending on implementation.

Prefetch (m8, Level = 1, EXCLUSIVE=1);

Flags Affected

All flags are affected.

C/C++ Compiler Intrinsic Equivalent

void _mm_prefetch( char const *, int hint= _MM_HINT_ET1);

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PREFETCHWT1—Prefetch Vector Data Into Caches With Intent to Write and T1 Hint

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

V4FMADDPS/V4FNMADDPS—Packed Single Precision Floating-Point Fused Multiply-Add

(4-Iterations)

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.512.F2.0F38.W0 9A /r

A

V/V

AVX512_4FMAPS

Multiply packed single-precision floating-point

V4FMADDPS zmm1{k1}{z}, zmm2+3,

values from source register block indicated by

m128

zmm2 by values from m128 and accumulate the

result in zmm1.

EVEX.512.F2.0F38.W0 AA /r

A

V/V

AVX512_4FMAPS

Multiply and negate packed single-precision

V4FNMADDPS zmm1{k1}{z},

floating-point values from source register block

zmm2+3, m128

indicated by zmm2 by values from m128 and

accumulate the result in zmm1.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

A

Tuple1_4X

ModRM:reg (r, w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

This instruction computes 4 sequential packed fused single-precision floating-point multiply-add instructions with a

sequentially selected memory operand in each of the four steps.

In the above box, the notation of “+3” is used to denote that the instruction accesses 4 source registers based on

that operand; sources are consecutive, start in a multiple of 4 boundary, and contain the encoded register operand.

This instruction supports memory fault suppression. The entire memory operand is loaded if any of the 16 lowest

significant mask bits is set to 1 or if a “no masking” encoding is used.

The tuple type Tuple1_4X implies that four 32-bit elements (16 bytes) are referenced by the memory operation

portion of this instruction.

Rounding is performed at every FMA (fused multiply and add) boundary. Exceptions are also taken sequentially.

Pre- and post-computational exceptions of the first FMA take priority over the pre- and post-computational excep-

tions of the second FMA, etc.

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V4FMADDPS/V4FNMADDPS—Packed Single Precision Floating-Point Fused Multiply-Add (4-Iterations)

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

V4FMADDSS/V4FNMADDSS—Scalar Single Precision Floating-Point Fused Multiply-Add

(4-Iterations)

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.LLIG.F2.0F38.W0 9B /r

A

V/V

AVX512_4FMAPS

Multiply scalar single-precision floating-point

V4FMADDSS xmm1{k1}{z},

values from source register block indicated by

xmm2+3, m128

xmm2 by values from m128 and accumulate the

result in xmm1.

EVEX.LLIG.F2.0F38.W0 AB /r

A

V/V

AVX512_4FMAPS

Multiply and negate scalar single-precision

V4FNMADDSS xmm1{k1}{z},

floating-point values from source register block

xmm2+3, m128

indicated by xmm2 by values from m128 and

accumulate the result in xmm1.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

A

Tuple1_4X

ModRM:reg (r, w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

This instruction computes 4 sequential scalar fused single-precision floating-point multiply-add instructions with a

sequentially selected memory operand in each of the four steps.

In the above box, the notation of “+3” is used to denote that the instruction accesses 4 source registers based that

operand; sources are consecutive, start in a multiple of 4 boundary, and contain the encoded register operand.

This instruction supports memory fault suppression. The entire memory operand is loaded if the least significant

mask bit is set to 1 or if a “no masking” encoding is used.

The tuple type Tuple1_4X implies that four 32-bit elements (16 bytes) are referenced by the memory operation

portion of this instruction.

Rounding is performed at every FMA boundary. Exceptions are also taken sequentially. Pre- and post-computa-

tional exceptions of the first FMA take priority over the pre- and post-computational exceptions of the second FMA,

etc.

Operation

src_reg_id is the 5 bit index of the vector register specified in the instruction as the src1 register.

define NFMA_SS(vl, dest, k1, msrc, regs_loaded, src_base, posneg):

tmpdest := dest

// reg[] is an array representing the SIMD register file.

IF k1[0] or *no writemask*:

FOR j := 0 to regs_loaded - 1:

IF posneg = 0:

tmpdest.single[0] := RoundFPControl_MXCSR(tmpdest.single[0] - reg[src_base + j ].single[0] * msrc.single[j])

ELSE:

tmpdest.single[0] := RoundFPControl_MXCSR(tmpdest.single[0] + reg[src_base + j ].single[0] * msrc.single[j])

ELSE IF *zeroing*:

tmpdest.single[0] := 0

dest := tmpdst

dest[MAX_VL-1:VL] := 0

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V4FMADDSS/V4FNMADDSS—Scalar Single Precision Floating-Point Fused Multiply-Add (4-Iterations)

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VEXP2PD—Approximation to the Exponential 2^x of Packed Double Precision Floating-Point

Values With Less Than 2^-23 Relative Error

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.512.66.0F38.W1 C8 /r

A

V/V

AVX512ER

Computes approximations to the exponential 2^x (with less

VEXP2PD zmm1 {k1}{z},

than 2^-23 of maximum relative error) of the packed double

zmm2/m512/m64bcst {sae}

precision floating-point values from zmm2/m512/m64bcst and

stores the floating-point result in zmm1with writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

N/A

Description

Computes the approximate base-2 exponential evaluation of the double precision floating-point values in the

source operand (the second operand) and stores the results to the destination operand (the first operand) using

the writemask k1. The approximate base-2 exponential is evaluated with less than 2^-23 of relative error.

Denormal input values are treated as zeros and do not signal #DE, irrespective of MXCSR.DAZ. Denormal results

are flushed to zeros and do not signal #UE, irrespective of MXCSR.FTZ.

The source operand is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit

memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.

EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

A numerically exact implementation of VEXP2xx can be found at https://software.intel.com/en-us/articles/refer-

ence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation

VEXP2PD

(KL, VL) = (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) AND (SRC *is memory*)

THEN DEST[i+63:i] := EXP2_23_DP(SRC[63:0])

ELSE DEST[i+63:i] := EXP2_23_DP(SRC[i+63:i])

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] := 0

FI;

FI;

ENDFOR;

VEXP2PD—Approximation to the Exponential 2^x of Packed Double Precision Floating-Point Values With Less Than 2^-23 Relative

8-8

Vol. 2D

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

Table 8-1. Special Values Behavior

Source Input

Result

Comments

NaN

QNaN(src)

If (SRC = SNaN) then #I

+∞

+∞

+/-0

1.0f

Exact result

-∞

+0.0f

Integral value N

2^ (N)

Exact result

Intel C/C++ Compiler Intrinsic Equivalent

VEXP2PD __m512d _mm512_exp2a23_round_pd (__m512d a, int sae);

VEXP2PD __m512d _mm512_mask_exp2a23_round_pd (__m512d a, __mmask8 m, __m512d b, int sae);

VEXP2PD __m512d _mm512_maskz_exp2a23_round_pd ( __mmask8 m, __m512d b, int sae);

SIMD Floating-Point Exceptions

Invalid (if SNaN input), Overflow.

Other Exceptions

See Table 2-46, “Type E2 Class Exception Conditions.”

VEXP2PD—Approximation to the Exponential 2^x of Packed Double Precision Floating-Point Values With Less Than 2^-23 Relative

Vol. 2D

8-9

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VEXP2PS—Approximation to the Exponential 2^x of Packed Single Precision Floating-Point

Values With Less Than 2^-23 Relative Error

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.512.66.0F38.W0 C8 /r

A

V/V

AVX512ER

Computes approximations to the exponential 2^x (with less

VEXP2PS zmm1 {k1}{z},

than 2^-23 of maximum relative error) of the packed single-

zmm2/m512/m32bcst {sae}

precision floating-point values from zmm2/m512/m32bcst and

stores the floating-point result in zmm1with writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

N/A

Description

Computes the approximate base-2 exponential evaluation of the single-precision floating-point values in the source

operand (the second operand) and store the results in the destination operand (the first operand) using the write-

mask k1. The approximate base-2 exponential is evaluated with less than 2^-23 of relative error.

Denormal input values are treated as zeros and do not signal #DE, irrespective of MXCSR.DAZ. Denormal results

are flushed to zeros and do not signal #UE, irrespective of MXCSR.FTZ.

The source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit

memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.

EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

A numerically exact implementation of VEXP2xx can be found at https://software.intel.com/en-us/articles/refer-

ence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation

VEXP2PS

(KL, VL) = (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) AND (SRC *is memory*)

THEN DEST[i+31:i] := EXP2_23_SP(SRC[31:0])

ELSE DEST[i+31:i] := EXP2_23_SP(SRC[i+31:i])

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

FI;

ENDFOR;

VEXP2PS—Approximation to the Exponential 2^x of Packed Single Precision Floating-Point Values With Less Than 2^-23 Relative Er-

8-10

Vol. 2D

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

Table 8-2. Special Values Behavior

Source Input

Result

Comments

NaN

QNaN(src)

If (SRC = SNaN) then #I

+∞

+∞

+/-0

1.0f

Exact result

-∞

+0.0f

Integral value N

2^ (N)

Exact result

Intel C/C++ Compiler Intrinsic Equivalent

VEXP2PS __m512 _mm512_exp2a23_round_ps (__m512 a, int sae);

VEXP2PS __m512 _mm512_mask_exp2a23_round_ps (__m512 a, __mmask16 m, __m512 b, int sae);

VEXP2PS __m512 _mm512_maskz_exp2a23_round_ps (__mmask16 m, __m512 b, int sae);

SIMD Floating-Point Exceptions

Invalid (if SNaN input), Overflow.

Other Exceptions

See Table 2-46, “Type E2 Class Exception Conditions.”

VEXP2PS—Approximation to the Exponential 2^x of Packed Single Precision Floating-Point Values With Less Than 2^-23 Relative Er-

Vol. 2D

8-11

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHERPF0QPD—Sparse Prefetch

Packed SP/DP Data Values With Signed Dword, Signed Qword Indices Using T0 Hint

Opcode/

Op/

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.512.66.0F38.W0 C6 /1 /vsib

A

V/V

AVX512PF

Using signed dword indices, prefetch sparse byte

VGATHERPF0DPS vm32z {k1}

memory locations containing single-precision data

using opmask k1 and T0 hint.

EVEX.512.66.0F38.W0 C7 /1 /vsib

A

V/V

AVX512PF

Using signed qword indices, prefetch sparse byte

VGATHERPF0QPS vm64z {k1}

memory locations containing single-precision data

using opmask k1 and T0 hint.

EVEX.512.66.0F38.W1 C6 /1 /vsib

A

V/V

AVX512PF

Using signed dword indices, prefetch sparse byte

VGATHERPF0DPD vm32y {k1}

memory locations containing double precision data

using opmask k1 and T0 hint.

EVEX.512.66.0F38.W1 C7 /1 /vsib

A

V/V

AVX512PF

Using signed qword indices, prefetch sparse byte

VGATHERPF0QPD vm64z {k1}

memory locations containing double precision data

using opmask k1 and T0 hint.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Tuple1 Scalar

BaseReg (R): VSIB:base,

N/A

N/A

N/A

VectorReg(R): VSIB:index

Description

The instruction conditionally prefetches up to sixteen 32-bit or eight 64-bit integer byte data elements. The

elements are specified via the VSIB (i.e., the index register is an zmm, holding packed indices). Elements will only

be prefetched if their corresponding mask bit is one.

Lines prefetched are loaded into to a location in the cache hierarchy specified by a locality hint (T0):

• T0 (temporal data)—prefetch data into the first level cache.

[PS data] For dword indices, the instruction will prefetch sixteen memory locations. For qword indices, the instruc-

tion will prefetch eight values.

[PD data] For dword and qword indices, the instruction will prefetch eight memory locations.

Note that:

(1) The prefetches may happen in any order (or not at all). The instruction is a hint.

(2) The mask is left unchanged.

(3) Not valid with 16-bit effective addresses. Will deliver a #UD fault.

(4) No FP nor memory faults may be produced by this instruction.

(5) Prefetches do not handle cache line splits

(6) A #UD is signaled if the memory operand is encoded without the SIB byte.

Operation

BASE_ADDR stands for the memory operand base address (a GPR); may not exist.

VINDEX stands for the memory operand vector of indices (a vector register).

SCALE stands for the memory operand scalar (1, 2, 4 or 8).

DISP is the optional 1, 2 or 4 byte displacement.

PREFETCH(mem, Level, State) Prefetches a byte memory location pointed by ‘mem’ into the cache level specified by ‘Level’; a request

for exclusive/ownership is done if ‘State’ is 1. Note that the memory location ignore cache line splits. This operation is considered a

hint for the processor and may be skipped depending on implementation.

VGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHERPF0QPD—Sparse Prefetch Packed SP/DP Data Values With Signed

8-12

Vol. 2D

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QPD—Sparse Prefetch

Packed SP/DP Data Values With Signed Dword, Signed Qword Indices Using T1 Hint

Opcode/

Op/

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.512.66.0F38.W0 C6 /2 /vsib

A

V/V

AVX512PF

Using signed dword indices, prefetch sparse byte

VGATHERPF1DPS vm32z {k1}

memory locations containing single-precision data using

opmask k1 and T1 hint.

EVEX.512.66.0F38.W0 C7 /2 /vsib

A

V/V

AVX512PF

Using signed qword indices, prefetch sparse byte

VGATHERPF1QPS vm64z {k1}

memory locations containing single-precision data using

opmask k1 and T1 hint.

EVEX.512.66.0F38.W1 C6 /2 /vsib

A

V/V

AVX512PF

Using signed dword indices, prefetch sparse byte

VGATHERPF1DPD vm32y {k1}

memory locations containing double precision data using

opmask k1 and T1 hint.

EVEX.512.66.0F38.W1 C7 /2 /vsib

A

V/V

AVX512PF

Using signed qword indices, prefetch sparse byte

VGATHERPF1QPD vm64z {k1}

memory locations containing double precision data using

opmask k1 and T1 hint.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Tuple1 Scalar

BaseReg (R): VSIB:base,

N/A

N/A

N/A

VectorReg(R): VSIB:index

Description

The instruction conditionally prefetches up to sixteen 32-bit or eight 64-bit integer byte data elements. The

elements are specified via the VSIB (i.e., the index register is an zmm, holding packed indices). Elements will only

be prefetched if their corresponding mask bit is one.

Lines prefetched are loaded into to a location in the cache hierarchy specified by a locality hint (T1):

• T1 (temporal data)—prefetch data into the second level cache.

[PS data] For dword indices, the instruction will prefetch sixteen memory locations. For qword indices, the instruc-

tion will prefetch eight values.

[PD data] For dword and qword indices, the instruction will prefetch eight memory locations.

Note that:

(1) The prefetches may happen in any order (or not at all). The instruction is a hint.

(2) The mask is left unchanged.

(3) Not valid with 16-bit effective addresses. Will deliver a #UD fault.

(4) No FP nor memory faults may be produced by this instruction.

(5) Prefetches do not handle cache line splits

(6) A #UD is signaled if the memory operand is encoded without the SIB byte.

Operation

BASE_ADDR stands for the memory operand base address (a GPR); may not exist.

VINDEX stands for the memory operand vector of indices (a vector register).

SCALE stands for the memory operand scalar (1, 2, 4 or 8).

DISP is the optional 1, 2 or 4 byte displacement.

PREFETCH(mem, Level, State) Prefetches a byte memory location pointed by ‘mem’ into the cache level specified by ‘Level’; a request

for exclusive/ownership is done if ‘State’ is 1. Note that the memory location ignore cache line splits. This operation is considered a

hint for the processor and may be skipped depending on implementation.

VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QPD—Sparse Prefetch Packed SP/DP Data Values With Signed

8-14

Vol. 2D

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VP4DPWSSDS—Dot Product of Signed Words With Dword Accumulation and Saturation

(4-Iterations)

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.512.F2.0F38.W0 53 /r

A

V/V

AVX512_4VNNIW

Multiply signed words from source register block

VP4DPWSSDS zmm1{k1}{z},

indicated by zmm2 by signed words from m128

zmm2+3, m128

and accumulate the resulting dword results with

signed saturation in zmm1.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

A

Tuple1_4X

ModRM:reg (r, w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

This instruction computes 4 sequential register source-block dot-products of two signed word operands with

doubleword accumulation and signed saturation. The memory operand is sequentially selected in each of the four

steps.

In the above box, the notation of “+3” is used to denote that the instruction accesses 4 source registers based on

that operand; sources are consecutive, start in a multiple of 4 boundary, and contain the encoded register operand.

This instruction supports memory fault suppression. The entire memory operand is loaded if any bit of the lowest

16-bits of the mask is set to 1 or if a “no masking” encoding is used.

The tuple type Tuple1_4X implies that four 32-bit elements (16 bytes) are referenced by the memory operation

portion of this instruction.

Operation

src_reg_id is the 5 bit index of the vector register specified in the instruction as the src1 register.

VP4DPWSSDS dest, src1, src2

(KL,VL) = (16,512)

N := 4

ORIGDEST := DEST

src_base := src_reg_id & ~ (N-1) // for src1 operand

FOR i := 0 to KL-1:

IF k1[i] or *no writemask*:

FOR m := 0 to N-1:

t := SRC2.dword[m]

p1dword := reg[src_base+m].word[2*i] * t.word[0]

p2dword := reg[src_base+m].word[2*i+1] * t.word[1]

DEST.dword[i] := SIGNED_DWORD_SATURATE(DEST.dword[i] + p1dword + p2dword)

ELSE IF *zeroing*:

DEST.dword[i] := 0

ELSE

DEST.dword[i] := ORIGDEST.dword[i]

DEST[MAX_VL-1:VL] := 0

8-16

Vol. 2D

VP4DPWSSDS—Dot Product of Signed Words With Dword Accumulation and Saturation (4-Iterations)

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VP4DPWSSD—Dot Product of Signed Words With Dword Accumulation (4-Iterations)

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.512.F2.0F38.W0 52 /r

A

V/V

AVX512_4VNNIW

Multiply signed words from source register block

VP4DPWSSD zmm1{k1}{z}, zmm2+3,

indicated by zmm2 by signed words from m128

m128

and accumulate resulting signed dwords in zmm1.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

A

Tuple1_4X

ModRM:reg (r, w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

This instruction computes 4 sequential register source-block dot-products of two signed word operands with

doubleword accumulation; see Figure 8-1 below. The memory operand is sequentially selected in each of the four

steps.

In the above box, the notation of “+3”' is used to denote that the instruction accesses 4 source registers based on

that operand; sources are consecutive, start in a multiple of 4 boundary, and contain the encoded register operand.

This instruction supports memory fault suppression. The entire memory operand is loaded if any bit of the lowest

16-bits of the mask is set to 1 or if a “no masking” encoding is used.

The tuple type Tuple1_4X implies that four 32-bit elements (16 bytes) are referenced by the memory operation

portion of this instruction.

16b

16b

16b

16b

a3

a2

a1

a0

b1

b0

b1

b0

32b

32b

c1

c0

c1=c1+a2*b0+a3*b1

c0=c0+a0*b0+a1*b1

32b

32b

Figure 8-1. Register Source-Block Dot Product of Two Signed Word Operands With Doubleword Accumulation¹

NOTES:

1. For illustration purposes, one source-block dot product instance is shown out of the four.

8-18

Vol. 2D

VP4DPWSSD—Dot Product of Signed Words With Dword Accumulation (4-Iterations)

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VRCP28PD—Approximation to the Reciprocal of Packed Double Precision Floating-Point Values

With Less Than 2^-28 Relative Error

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.512.66.0F38.W1 CA /r

A

V/V

AVX512ER

Computes the approximate reciprocals ( < 2^-28 relative error)

VRCP28PD zmm1 {k1}{z},

of the packed double precision floating-point values in

zmm2/m512/m64bcst {sae}

zmm2/m512/m64bcst and stores the results in zmm1. Under

writemask.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

Description

Computes the reciprocal approximation of the float64 values in the source operand (the second operand) and store

the results to the destination operand (the first operand). The approximate reciprocal is evaluated with less than

2^-28 of maximum relative error.

Denormal input values are treated as zeros and do not signal #DE, irrespective of MXCSR.DAZ. Denormal results

are flushed to zeros and do not signal #UE, irrespective of MXCSR.FTZ.

If any source element is NaN, the quietized NaN source value is returned for that element. If any source element is

±∞, ±0.0 is returned for that element. Also, if any source element is ±0.0, ±∞ is returned for that element.

The source operand is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit

memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.

EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

A numerically exact implementation of VRCP28xx can be found at https://software.intel.com/en-us/articles/refer-

ence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation

VRCP28PD (EVEX Encoded Versions)

(KL, VL) = (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) AND (SRC *is memory*)

THEN DEST[i+63:i] := RCP_28_DP(1.0/SRC[63:0]);

ELSE DEST[i+63:i] := RCP_28_DP(1.0/SRC[i+63:i]);

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] := 0

FI;

FI;

ENDFOR;

VRCP28PD—Approximation to the Reciprocal of Packed Double Precision Floating-Point Values With Less Than 2^-28 Relative Error

8-20

Vol. 2D

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

Table 8-3. VRCP28PD Special Cases

Input Value

Result Value

Comments

NAN

QNAN(input)

If (SRC = SNaN) then #I

0 ≤ X < 2^-1022

INF

Positive input denormal or zero; #Z

-2^-1022 < X ≤ -0

-INF

Negative input denormal or zero; #Z

X > 2¹⁰²²

+0.0f

X < -2¹⁰²²

-0.0f

X = +∞

+0.0f

X = -∞

-0.0f

X = 2^-n

2ⁿ

Exact result (unless input/output is a denormal)

X = -2^-n

-2ⁿ

Exact result (unless input/output is a denormal)

Intel C/C++ Compiler Intrinsic Equivalent

VRCP28PD __m512d _mm512_rcp28_round_pd ( __m512d a, int sae);

VRCP28PD __m512d _mm512_mask_rcp28_round_pd(__m512d a, __mmask8 m, __m512d b, int sae);

VRCP28PD __m512d _mm512_maskz_rcp28_round_pd( __mmask8 m, __m512d b, int sae);

SIMD Floating-Point Exceptions

Invalid (if SNaN input), Divide-by-zero.

Other Exceptions

See Table 2-46, “Type E2 Class Exception Conditions.”

VRCP28PD—Approximation to the Reciprocal of Packed Double Precision Floating-Point Values With Less Than 2^-28 Relative Error

Vol. 2D

8-21

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VRCP28SD—Approximation to the Reciprocal of Scalar Double Precision Floating-Point Value

With Less Than 2^-28 Relative Error

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.LLIG.66.0F38.W1 CB /r

A

V/V

AVX512ER

Computes the approximate reciprocal ( < 2^-28 relative

VRCP28SD xmm1 {k1}{z}, xmm2,

error) of the scalar double precision floating-point value in

xmm3/m64 {sae}

xmm3/m64 and stores the results in xmm1. Under

writemask. Also, upper double precision floating-point

value (bits[127:64]) from xmm2 is copied to

xmm1[127:64].

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Computes the reciprocal approximation of the low float64 value in the second source operand (the third operand)

and store the result to the destination operand (the first operand). The approximate reciprocal is evaluated with

less than 2^-28 of maximum relative error. The result is written into the low float64 element of the destination

operand according to the writemask k1. Bits 127:64 of the destination is copied from the corresponding bits of the

first source operand (the second operand).

A denormal input value is treated as zero and does not signal #DE, irrespective of MXCSR.DAZ. A denormal result

is flushed to zero and does not signal #UE, irrespective of MXCSR.FTZ.

If any source element is NaN, the quietized NaN source value is returned for that element. If any source element is

±∞, ±0.0 is returned for that element. Also, if any source element is ±0.0, ±∞ is returned for that element.

The first source operand is an XMM register. The second source operand is an XMM register or a 64-bit memory

location. The destination operand is a XMM register, conditionally updated using writemask k1.

A numerically exact implementation of VRCP28xx can be found at https://software.intel.com/en-us/articles/refer-

ence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation

VRCP28SD ((EVEX Encoded Versions)

IF k1[0] OR *no writemask* THEN

DEST[63: 0] := RCP_28_DP(1.0/SRC2[63: 0]);

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[63: 0] remains unchanged*

ELSE

; zeroing-masking

DEST[63: 0] := 0

FI;

FI;

ENDFOR;

DEST[127:64] := SRC1[127: 64]

DEST[MAXVL-1:128] := 0

VRCP28SD—Approximation to the Reciprocal of Scalar Double Precision Floating-Point Value With Less Than 2^-28 Relative Error

8-22

Vol. 2D

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

Table 8-4. VRCP28SD Special Cases

Input Value

Result Value

Comments

NAN

QNAN(input)

If (SRC = SNaN) then #I

0 ≤ X < 2^-1022

INF

Positive input denormal or zero; #Z

-2^-1022 < X ≤ -0

-INF

Negative input denormal or zero; #Z

X > 2¹⁰²²

+0.0f

X < -2¹⁰²²

-0.0f

X = +∞

+0.0f

X = -∞

-0.0f

X = 2^-n

2ⁿ

Exact result (unless input/output is a denormal)

X = -2^-n

-2ⁿ

Exact result (unless input/output is a denormal)

Intel C/C++ Compiler Intrinsic Equivalent

VRCP28SD __m128d _mm_rcp28_round_sd ( __m128d a, __m128d b, int sae);

VRCP28SD __m128d _mm_mask_rcp28_round_sd(__m128d s, __mmask8 m, __m128d a, __m128d b, int sae);

VRCP28SD __m128d _mm_maskz_rcp28_round_sd(__mmask8 m, __m128d a, __m128d b, int sae);

SIMD Floating-Point Exceptions

Invalid (if SNaN input), Divide-by-zero.

Other Exceptions

See Table 2-47, “Type E3 Class Exception Conditions.”

VRCP28SD—Approximation to the Reciprocal of Scalar Double Precision Floating-Point Value With Less Than 2^-28 Relative Error

Vol. 2D

8-23

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VRCP28PS—Approximation to the Reciprocal of Packed Single Precision Floating-Point Values

With Less Than 2^-28 Relative Error

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.512.66.0F38.W0 CA /r

A

V/V

AVX512ER

Computes the approximate reciprocals ( < 2^-28 relative

VRCP28PS zmm1 {k1}{z},

error) of the packed single-precision floating-point values in

zmm2/m512/m32bcst {sae}

zmm2/m512/m32bcst and stores the results in zmm1. Under

writemask.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

Description

Computes the reciprocal approximation of the float32 values in the source operand (the second operand) and store

the results to the destination operand (the first operand) using the writemask k1. The approximate reciprocal is

evaluated with less than 2^-28 of maximum relative error prior to final rounding. The final results are rounded to

< 2^-23 relative error before written to the destination.

Denormal input values are treated as zeros and do not signal #DE, irrespective of MXCSR.DAZ. Denormal results

are flushed to zeros and do not signal #UE, irrespective of MXCSR.FTZ.

If any source element is NaN, the quietized NaN source value is returned for that element. If any source element is

±∞, ±0.0 is returned for that element. Also, if any source element is ±0.0, ±∞ is returned for that element.

The source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit

memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.

EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

A numerically exact implementation of VRCP28xx can be found at https://software.intel.com/en-us/articles/refer-

ence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation

VRCP28PS (EVEX Encoded Versions)

(KL, VL) = (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) AND (SRC *is memory*)

THEN DEST[i+31:i] := RCP_28_SP(1.0/SRC[31:0]);

ELSE DEST[i+31:i] := RCP_28_SP(1.0/SRC[i+31:i]);

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

FI;

ENDFOR;

VRCP28PS—Approximation to the Reciprocal of Packed Single Precision Floating-Point Values With Less Than 2^-28 Relative Error

8-24

Vol. 2D

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

Table 8-5. VRCP28PS Special Cases

Input Value

Result Value

Comments

NAN

QNAN(input)

If (SRC = SNaN) then #I

0 ≤ X < 2^-126

INF

Positive input denormal or zero; #Z

-2^-126 < X ≤ -0

-INF

Negative input denormal or zero; #Z

X > 2¹²⁶

+0.0f

X < -2¹²⁶

-0.0f

X = +∞

+0.0f

X = -∞

-0.0f

X = 2^-n

2ⁿ

Exact result (unless input/output is a denormal)

X = -2^-n

-2ⁿ

Exact result (unless input/output is a denormal)

Intel C/C++ Compiler Intrinsic Equivalent

VRCP28PS _mm512_rcp28_round_ps ( __m512 a, int sae);

VRCP28PS __m512 _mm512_mask_rcp28_round_ps(__m512 s, __mmask16 m, __m512 a, int sae);

VRCP28PS __m512 _mm512_maskz_rcp28_round_ps( __mmask16 m, __m512 a, int sae);

SIMD Floating-Point Exceptions

Invalid (if SNaN input), Divide-by-zero.

Other Exceptions

See Table 2-46, “Type E2 Class Exception Conditions.”

VRCP28PS—Approximation to the Reciprocal of Packed Single Precision Floating-Point Values With Less Than 2^-28 Relative Error

Vol. 2D

8-25

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VRCP28SS—Approximation to the Reciprocal of Scalar Single Precision Floating-Point Value

With Less Than 2^-28 Relative Error

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.LLIG.66.0F38.W0 CB /r

A

V/V

AVX512ER

Computes the approximate reciprocal ( < 2^-28 relative

VRCP28SS xmm1 {k1}{z},

error) of the scalar single-precision floating-point value in

xmm2, xmm3/m32 {sae}

xmm3/m32 and stores the results in xmm1. Under

writemask. Also, upper 3 single-precision floating-point

values (bits[127:32]) from xmm2 is copied to

xmm1[127:32].

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Computes the reciprocal approximation of the low float32 value in the second source operand (the third operand)

and store the result to the destination operand (the first operand). The approximate reciprocal is evaluated with

less than 2^-28 of maximum relative error prior to final rounding. The final result is rounded to < 2^-23 relative

error before written into the low float32 element of the destination according to writemask k1. Bits 127:32 of the

destination is copied from the corresponding bits of the first source operand (the second operand).

A denormal input value is treated as zero and does not signal #DE, irrespective of MXCSR.DAZ. A denormal result

is flushed to zero and does not signal #UE, irrespective of MXCSR.FTZ.

If any source element is NaN, the quietized NaN source value is returned for that element. If any source element is

±∞, ±0.0 is returned for that element. Also, if any source element is ±0.0, ±∞ is returned for that element.

The first source operand is an XMM register. The second source operand is an XMM register or a 32-bit memory

location. The destination operand is a XMM register, conditionally updated using writemask k1.

A numerically exact implementation of VRCP28xx can be found at https://software.intel.com/en-us/articles/refer-

ence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation

VRCP28SS ((EVEX Encoded Versions)

IF k1[0] OR *no writemask* THEN

DEST[31: 0] := RCP_28_SP(1.0/SRC2[31: 0]);

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[31: 0] remains unchanged*

ELSE

; zeroing-masking

DEST[31: 0] := 0

FI;

FI;

ENDFOR;

DEST[127:32] := SRC1[127: 32]

DEST[MAXVL-1:128] := 0

VRCP28SS—Approximation to the Reciprocal of Scalar Single Precision Floating-Point Value With Less Than 2^-28 Relative Error

8-26

Vol. 2D

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

Table 8-6. VRCP28SS Special Cases

Input Value

Result Value

Comments

NAN

QNAN(input)

If (SRC = SNaN) then #I

0 ≤ X < 2^-126

INF

Positive input denormal or zero; #Z

-2^-126 < X ≤ -0

-INF

Negative input denormal or zero; #Z

X > 2¹²⁶

+0.0f

X < -2¹²⁶

-0.0f

X = +∞

+0.0f

X = -∞

-0.0f

X = 2^-n

2ⁿ

Exact result (unless input/output is a denormal)

X = -2^-n

-2ⁿ

Exact result (unless input/output is a denormal)

Intel C/C++ Compiler Intrinsic Equivalent

VRCP28SS __m128 _mm_rcp28_round_ss ( __m128 a, __m128 b, int sae);

VRCP28SS __m128 _mm_mask_rcp28_round_ss(__m128 s, __mmask8 m, __m128 a, __m128 b, int sae);

VRCP28SS __m128 _mm_maskz_rcp28_round_ss(__mmask8 m, __m128 a, __m128 b, int sae);

SIMD Floating-Point Exceptions

Invalid (if SNaN input), Divide-by-zero.

Other Exceptions

See Table 2-47, “Type E3 Class Exception Conditions.”

VRCP28SS—Approximation to the Reciprocal of Scalar Single Precision Floating-Point Value With Less Than 2^-28 Relative Error

Vol. 2D

8-27

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VRSQRT28PD—Approximation to the Reciprocal Square Root of Packed Double Precision

Floating-Point Values With Less Than 2^-28 Relative Error

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.512.66.0F38.W1 CC /r

A

V/V

AVX512ER

Computes approximations to the Reciprocal square root (<2^-

VRSQRT28PD zmm1 {k1}{z},

28 relative error) of the packed double precision floating-point

zmm2/m512/m64bcst {sae}

values from zmm2/m512/m64bcst and stores result in

zmm1with writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

Description

Computes the reciprocal square root of the float64 values in the source operand (the second operand) and store

the results to the destination operand (the first operand). The approximate reciprocal is evaluated with less than

2^-28 of maximum relative error.

If any source element is NaN, the quietized NaN source value is returned for that element. Negative (non-zero)

source numbers, as well as -∞, return the canonical NaN and set the Invalid Flag (#I).

A value of -0 must return -∞ and set the DivByZero flags (#Z). Negative numbers should return NaN and set the

Invalid flag (#I). Note however that the instruction flush input denormals to zero of the same sign, so negative

denormals return -∞ and set the DivByZero flag.

The source operand is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit

memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.

EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

A numerically exact implementation of VRSQRT28xx can be found at https://software.intel.com/en-us/arti-

cles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation

VRSQRT28PD (EVEX Encoded Versions)

(KL, VL) = (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) AND (SRC *is memory*)

THEN DEST[i+63:i] := (1.0/ SQRT(SRC[63:0]));

ELSE DEST[i+63:i] := (1.0/ SQRT(SRC[i+63:i]));

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] := 0

FI;

FI;

ENDFOR;

VRSQRT28PD—Approximation to the Reciprocal Square Root of Packed Double Precision Floating-Point Values With Less Than 2^-28

8-28

Vol. 2D

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

Table 8-7. VRSQRT28PD Special Cases

Input Value

Result Value

Comments

NAN

QNAN(input)

If (SRC = SNaN) then #I

X = 2^-2n

2ⁿ

X < 0

QNaN_Indefinite

Including -INF

X = -0 or negative denormal

-INF

#Z

X = +0 or positive denormal

+INF

#Z

X = +INF

+0

Intel C/C++ Compiler Intrinsic Equivalent

VRSQRT28PD __m512d _mm512_rsqrt28_round_pd(__m512d a, int sae);

VRSQRT28PD __m512d _mm512_mask_rsqrt28_round_pd(__m512d s, __mmask8 m,__m512d a, int sae);

VRSQRT28PD __m512d _mm512_maskz_rsqrt28_round_pd(__mmask8 m,__m512d a, int sae);

SIMD Floating-Point Exceptions

Invalid (if SNaN input), Divide-by-zero.

Other Exceptions

See Table 2-46, “Type E2 Class Exception Conditions.”

VRSQRT28PD—Approximation to the Reciprocal Square Root of Packed Double Precision Floating-Point Values With Less Than 2^-28

Vol. 2D

8-29

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VRSQRT28SD—Approximation to the Reciprocal Square Root of Scalar Double Precision

Floating-Point Value With Less Than 2^-28 Relative Error

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.LLIG.66.0F38.W1 CD /r

A

V/V

AVX512ER

Computes approximate reciprocal square root (<2^-28

VRSQRT28SD xmm1 {k1}{z},

relative error) of the scalar double precision floating-point

xmm2, xmm3/m64 {sae}

value from xmm3/m64 and stores result in xmm1with

writemask k1. Also, upper double precision floating-point

value (bits[127:64]) from xmm2 is copied to

xmm1[127:64].

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Computes the reciprocal square root of the low float64 value in the second source operand (the third operand) and

store the result to the destination operand (the first operand). The approximate reciprocal square root is evaluated

with less than 2^-28 of maximum relative error. The result is written into the low float64 element of xmm1

according to the writemask k1. Bits 127:64 of the destination is copied from the corresponding bits of the first source operand (the

second operand).

If any source element is NaN, the quietized NaN source value is returned for that element. Negative (non-zero)

source numbers, as well as -∞, return the canonical NaN and set the Invalid Flag (#I).

A value of -0 must return -∞ and set the DivByZero flags (#Z). Negative numbers should return NaN and set the

Invalid flag (#I). Note however that the instruction flush input denormals to zero of the same sign, so negative

denormals return -∞ and set the DivByZero flag.

The first source operand is an XMM register. The second source operand is an XMM register or a 64-bit memory

location. The destination operand is a XMM register.

A numerically exact implementation of VRSQRT28xx can be found at https://software.intel.com/en-us/arti-

cles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation

VRSQRT28SD (EVEX Encoded Versions)

IF k1[0] OR *no writemask* THEN

DEST[63: 0] := (1.0/ SQRT(SRC[63: 0]));

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[63: 0] remains unchanged*

ELSE

; zeroing-masking

DEST[63: 0] := 0

FI;

FI;

ENDFOR;

DEST[127:64] := SRC1[127: 64]

DEST[MAXVL-1:128] := 0

VRSQRT28SD—Approximation to the Reciprocal Square Root of Scalar Double Precision Floating-Point Value With Less Than 2^-28

8-30

Vol. 2D

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

Table 8-8. VRSQRT28SD Special Cases

Input Value

Result Value

Comments

NAN

QNAN(input)

If (SRC = SNaN) then #I

X = 2^-2n

2ⁿ

X < 0

QNaN_Indefinite

Including -INF

X = -0 or negative denormal

-INF

#Z

X = +0 or positive denormal

+INF

#Z

X = +INF

+0

Intel C/C++ Compiler Intrinsic Equivalent

VRSQRT28SD __m128d _mm_rsqrt28_round_sd(__m128d a, __m128d b, int rounding);

VRSQRT28SD __m128d _mm_mask_rsqrt28_round_sd(__m128d s, __mmask8 m,__m128d a, __m128d b, int rounding);

VRSQRT28SD __m128d _mm_maskz_rsqrt28_round_sd( __mmask8 m,__m128d a, __m128d b, int rounding);

SIMD Floating-Point Exceptions

Invalid (if SNaN input), Divide-by-zero.

Other Exceptions

See Table 2-47, “Type E3 Class Exception Conditions.”

VRSQRT28SD—Approximation to the Reciprocal Square Root of Scalar Double Precision Floating-Point Value With Less Than 2^-28

Vol. 2D

8-31

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VRSQRT28PS—Approximation to the Reciprocal Square Root of Packed Single Precision

Floating-Point Values With Less Than 2^-28 Relative Error

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.512.66.0F38.W0 CC /r

A

V/V

AVX512ER

Computes approximations to the Reciprocal square root

VRSQRT28PS zmm1 {k1}{z},

(<2^-28 relative error) of the packed single-precision

zmm2/m512/m32bcst {sae}

floating-point values from zmm2/m512/m32bcst and stores

result in zmm1with writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

Description

Computes the reciprocal square root of the float32 values in the source operand (the second operand) and store

the results to the destination operand (the first operand). The approximate reciprocal is evaluated with less than

2^-28 of maximum relative error prior to final rounding. The final results is rounded to < 2^-23 relative error

before written to the destination.

If any source element is NaN, the quietized NaN source value is returned for that element. Negative (non-zero)

source numbers, as well as -∞, return the canonical NaN and set the Invalid Flag (#I).

A value of -0 must return -∞ and set the DivByZero flags (#Z). Negative numbers should return NaN and set the

Invalid flag (#I). Note however that the instruction flush input denormals to zero of the same sign, so negative

denormals return -∞ and set the DivByZero flag.

The source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit

memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.

EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

A numerically exact implementation of VRSQRT28xx can be found at https://software.intel.com/en-us/arti-

cles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation

VRSQRT28PS (EVEX Encoded Versions)

(KL, VL) = (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) AND (SRC *is memory*)

THEN DEST[i+31:i] := (1.0/ SQRT(SRC[31:0]));

ELSE DEST[i+31:i] := (1.0/ SQRT(SRC[i+31:i]));

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

FI;

ENDFOR;

VRSQRT28PS—Approximation to the Reciprocal Square Root of Packed Single Precision Floating-Point Values With Less Than 2^-28

8-32

Vol. 2D

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

Table 8-9. VRSQRT28PS Special Cases

Input Value

Result Value

Comments

NAN

QNAN(input)

If (SRC = SNaN) then #I

X = 2^-2n

2ⁿ

X < 0

QNaN_Indefinite

Including -INF

X = -0 or negative denormal

-INF

#Z

X = +0 or positive denormal

+INF

#Z

X = +INF

+0

Intel C/C++ Compiler Intrinsic Equivalent

VRSQRT28PS __m512 _mm512_rsqrt28_round_ps(__m512 a, int sae);

VRSQRT28PS __m512 _mm512_mask_rsqrt28_round_ps(__m512 s, __mmask16 m,__m512 a, int sae);

VRSQRT28PS __m512 _mm512_maskz_rsqrt28_round_ps(__mmask16 m,__m512 a, int sae);

SIMD Floating-Point Exceptions

Invalid (if SNaN input), Divide-by-zero.

Other Exceptions

See Table 2-46, “Type E2 Class Exception Conditions.”

VRSQRT28PS—Approximation to the Reciprocal Square Root of Packed Single Precision Floating-Point Values With Less Than 2^-28

Vol. 2D

8-33

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VRSQRT28SS—Approximation to the Reciprocal Square Root of Scalar Single Precision Floating-

Point Value With Less Than 2^-28 Relative Error

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.LLIG.66.0F38.W0 CD /r

A

V/V

AVX512ER

Computes approximate reciprocal square root (<2^-28

VRSQRT28SS xmm1 {k1}{z},

relative error) of the scalar single-precision floating-point

xmm2, xmm3/m32 {sae}

value from xmm3/m32 and stores result in xmm1with

writemask k1. Also, upper 3 single-precision floating-point

value (bits[127:32]) from xmm2 is copied to

xmm1[127:32].

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Computes the reciprocal square root of the low float32 value in the second source operand (the third operand) and

store the result to the destination operand (the first operand). The approximate reciprocal square root is evaluated

with less than 2^-28 of maximum relative error prior to final rounding. The final result is rounded to < 2^-23 rela-

tive error before written to the low float32 element of the destination according to the writemask k1. Bits 127:32 of

the destination is copied from the corresponding bits of the first source operand (the second operand).

If any source element is NaN, the quietized NaN source value is returned for that element. Negative (non-zero)

source numbers, as well as -∞, return the canonical NaN and set the Invalid Flag (#I).

A value of -0 must return -∞ and set the DivByZero flags (#Z). Negative numbers should return NaN and set the

Invalid flag (#I). Note however that the instruction flush input denormals to zero of the same sign, so negative

denormals return -∞ and set the DivByZero flag.

The first source operand is an XMM register. The second source operand is an XMM register or a 32-bit memory

location. The destination operand is a XMM register.

A numerically exact implementation of VRSQRT28xx can be found at https://software.intel.com/en-us/arti-

cles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation

VRSQRT28SS (EVEX Encoded Versions)

IF k1[0] OR *no writemask* THEN

DEST[31: 0] := (1.0/ SQRT(SRC[31: 0]));

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[31: 0] remains unchanged*

ELSE

; zeroing-masking

DEST[31: 0] := 0

FI;

FI;

ENDFOR;

DEST[127:32] := SRC1[127: 32]

DEST[MAXVL-1:128] := 0

VRSQRT28SS—Approximation to the Reciprocal Square Root of Scalar Single Precision Floating-Point Value With Less Than 2^-28 Rel-

8-34

Vol. 2D

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

Table 8-10. VRSQRT28SS Special Cases

Input Value

Result Value

Comments

NAN

QNAN(input)

If (SRC = SNaN) then #I

X = 2^-2n

2ⁿ

X < 0

QNaN_Indefinite

Including -INF

X = -0 or negative denormal

-INF

#Z

X = +0 or positive denormal

+INF

#Z

X = +INF

+0

Intel C/C++ Compiler Intrinsic Equivalent

VRSQRT28SS __m128 _mm_rsqrt28_round_ss(__m128 a, __m128 b, int rounding);

VRSQRT28SS __m128 _mm_mask_rsqrt28_round_ss(__m128 s, __mmask8 m,__m128 a,__m128 b, int rounding);

VRSQRT28SS __m128 _mm_maskz_rsqrt28_round_ss(__mmask8 m,__m128 a,__m128 b, int rounding);

SIMD Floating-Point Exceptions

Invalid (if SNaN input), Divide-by-zero.

Other Exceptions

See Table 2-47, “Type E3 Class Exception Conditions.”

VRSQRT28SS—Approximation to the Reciprocal Square Root of Scalar Single Precision Floating-Point Value With Less Than 2^-28 Rel-

Vol. 2D

8-35

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF0QPD—Sparse Prefetch

Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint With Intent

to Write

Opcode/

Op/

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.512.66.0F38.W0 C6 /5 /vsib

A

V/V

AVX512PF

Using signed dword indices, prefetch sparse byte

VSCATTERPF0DPS vm32z {k1}

memory locations containing single-precision data using

writemask k1 and T0 hint with intent to write.

EVEX.512.66.0F38.W0 C7 /5 /vsib

A

V/V

AVX512PF

Using signed qword indices, prefetch sparse byte

VSCATTERPF0QPS vm64z {k1}

memory locations containing single-precision data using

writemask k1 and T0 hint with intent to write.

EVEX.512.66.0F38.W1 C6 /5 /vsib

A

V/V

AVX512PF

Using signed dword indices, prefetch sparse byte

VSCATTERPF0DPD vm32y {k1}

memory locations containing double precision data

using writemask k1 and T0 hint with intent to write.

EVEX.512.66.0F38.W1 C7 /5 /vsib

A

V/V

AVX512PF

Using signed qword indices, prefetch sparse byte

VSCATTERPF0QPD vm64z {k1}

memory locations containing double precision data

using writemask k1 and T0 hint with intent to write.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Tuple1 Scalar

BaseReg (R): VSIB:base,

N/A

N/A

N/A

VectorReg(R): VSIB:index

Description

The instruction conditionally prefetches up to sixteen 32-bit or eight 64-bit integer byte data elements. The

elements are specified via the VSIB (i.e., the index register is an zmm, holding packed indices). Elements will only

be prefetched if their corresponding mask bit is one.

cache lines will be brought into exclusive state (RFO) specified by a locality hint (T0):

• T0 (temporal data)—prefetch data into the first level cache.

[PS data] For dword indices, the instruction will prefetch sixteen memory locations. For qword indices, the instruc-

tion will prefetch eight values.

[PD data] For dword and qword indices, the instruction will prefetch eight memory locations.

Note that:

(1) The prefetches may happen in any order (or not at all). The instruction is a hint.

(2) The mask is left unchanged.

(3) Not valid with 16-bit effective addresses. Will deliver a #UD fault.

(4) No FP nor memory faults may be produced by this instruction.

(5) Prefetches do not handle cache line splits

(6) A #UD is signaled if the memory operand is encoded without the SIB byte.

Operation

BASE_ADDR stands for the memory operand base address (a GPR); may not exist.

VINDEX stands for the memory operand vector of indices (a vector register).

SCALE stands for the memory operand scalar (1, 2, 4 or 8).

DISP is the optional 1, 2 or 4 byte displacement.

PREFETCH(mem, Level, State) Prefetches a byte memory location pointed by ‘mem’ into the cache level specified by ‘Level’; a request

for exclusive/ownership is done if ‘State’ is 1. Note that the memory location ignore cache line splits. This operation is considered a

hint for the processor and may be skipped depending on implementation.

VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF0QPD—Sparse Prefetch Packed SP/DP Data Values with

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