Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 111
INSTRUCTION FORMATS AND ENCODINGS
Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format
Encoding
memory by 1
0100 00XB : 1101 000w : mod 010 r/m
memory64 by 1
0100 10XB 1101 0001 : mod 010 r/m
register by CL
0100 000B : 1101 001w : 11 010 reg
qwordregister by CL
0100 100B 1101 0011 : 11 010 qwordreg
memory by CL
0100 00XB : 1101 001w : mod 010 r/m
memory64 by CL
0100 10XB 1101 0011 : mod 010 r/m
register by immediate count
0100 000B : 1100 000w : 11 010 reg : imm
qwordregister by immediate count
0100 100B 1100 0001 : 11 010 qwordreg : imm8
memory by immediate count
0100 00XB : 1100 000w : mod 010 r/m : imm
memory64 by immediate count
0100 10XB 1100 0001 : mod 010 r/m : imm8
RCR - Rotate thru Carry Right
register by 1
0100 000B : 1101 000w : 11 011 reg
qwordregister by 1
0100 100B 1101 0001 : 11 011 qwordreg
memory by 1
0100 00XB : 1101 000w : mod 011 r/m
memory64 by 1
0100 10XB 1101 0001 : mod 011 r/m
register by CL
0100 000B : 1101 001w : 11 011 reg
qwordregister by CL
0100 000B 1101 0010 : 11 011 qwordreg
memory by CL
0100 00XB : 1101 001w : mod 011 r/m
memory64 by CL
0100 10XB 1101 0011 : mod 011 r/m
register by immediate count
0100 000B : 1100 000w : 11 011 reg : imm8
qwordregister by immediate count
0100 100B 1100 0001 : 11 011 qwordreg : imm8
memory by immediate count
0100 00XB : 1100 000w : mod 011 r/m : imm8
memory64 by immediate count
0100 10XB 1100 0001 : mod 011 r/m : imm8
RDMSR - Read from Model-Specific Register
load ECX-specified register into EDX:EAX
0000 1111 : 0011 0010
RDPMC - Read Performance Monitoring Counters
load ECX-specified performance counter into EDX:EAX
0000 1111 : 0011 0011
RDTSC - Read Time-Stamp Counter
read time-stamp counter into EDX:EAX
0000 1111 : 0011 0001
RDTSCP - Read Time-Stamp Counter and Processor ID
0000 1111 : 0000 0001: 1111 1001
REP INS - Input String
REP LODS - Load String
REP MOVS - Move String
REP OUTS - Output String
REP STOS - Store String
REPE CMPS - Compare String
REPE SCAS - Scan String
REPNE CMPS - Compare String
Vol. 2D B-29
INSTRUCTION FORMATS AND ENCODINGS
Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format
Encoding
REPNE SCAS - Scan String
RET - Return from Procedure (to same segment)
no argument
1100 0011
adding immediate to SP
1100 0010 : 16-bit displacement
RET - Return from Procedure (to other segment)
intersegment
1100 1011
adding immediate to SP
1100 1010 : 16-bit displacement
ROL - Rotate Left
register by 1
0100 000B 1101 000w : 11 000 reg
byteregister by 1
0100 000B 1101 0000 : 11 000 bytereg
qwordregister by 1
0100 100B 1101 0001 : 11 000 qwordreg
memory by 1
0100 00XB 1101 000w : mod 000 r/m
memory8 by 1
0100 00XB 1101 0000 : mod 000 r/m
memory64 by 1
0100 10XB 1101 0001 : mod 000 r/m
register by CL
0100 000B 1101 001w : 11 000 reg
byteregister by CL
0100 000B 1101 0010 : 11 000 bytereg
qwordregister by CL
0100 100B 1101 0011 : 11 000 qwordreg
memory by CL
0100 00XB 1101 001w : mod 000 r/m
memory8 by CL
0100 00XB 1101 0010 : mod 000 r/m
memory64 by CL
0100 10XB 1101 0011 : mod 000 r/m
register by immediate count
1100 000w : 11 000 reg : imm8
byteregister by immediate count
0100 000B 1100 0000 : 11 000 bytereg : imm8
qwordregister by immediate count
0100 100B 1100 0001 : 11 000 bytereg : imm8
memory by immediate count
1100 000w : mod 000 r/m : imm8
memory8 by immediate count
0100 00XB 1100 0000 : mod 000 r/m : imm8
memory64 by immediate count
0100 10XB 1100 0001 : mod 000 r/m : imm8
ROR - Rotate Right
register by 1
0100 000B 1101 000w : 11 001 reg
byteregister by 1
0100 000B 1101 0000 : 11 001 bytereg
qwordregister by 1
0100 100B 1101 0001 : 11 001 qwordreg
memory by 1
0100 00XB 1101 000w : mod 001 r/m
memory8 by 1
0100 00XB 1101 0000 : mod 001 r/m
memory64 by 1
0100 10XB 1101 0001 : mod 001 r/m
register by CL
0100 000B 1101 001w : 11 001 reg
byteregister by CL
0100 000B 1101 0010 : 11 001 bytereg
qwordregister by CL
0100 100B 1101 0011 : 11 001 qwordreg
memory by CL
0100 00XB 1101 001w : mod 001 r/m
memory8 by CL
0100 00XB 1101 0010 : mod 001 r/m
B-30
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INSTRUCTION FORMATS AND ENCODINGS
Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format
Encoding
memory64 by CL
0100 10XB 1101 0011 : mod 001 r/m
register by immediate count
0100 000B 1100 000w : 11 001 reg : imm8
byteregister by immediate count
0100 000B 1100 0000 : 11 001 reg : imm8
qwordregister by immediate count
0100 100B 1100 0001 : 11 001 qwordreg : imm8
memory by immediate count
0100 00XB 1100 000w : mod 001 r/m : imm8
memory8 by immediate count
0100 00XB 1100 0000 : mod 001 r/m : imm8
memory64 by immediate count
0100 10XB 1100 0001 : mod 001 r/m : imm8
RSM - Resume from System Management Mode
0000 1111 : 1010 1010
SAL - Shift Arithmetic Left
same instruction as SHL
SAR - Shift Arithmetic Right
register by 1
0100 000B 1101 000w : 11 111 reg
byteregister by 1
0100 000B 1101 0000 : 11 111 bytereg
qwordregister by 1
0100 100B 1101 0001 : 11 111 qwordreg
memory by 1
0100 00XB 1101 000w : mod 111 r/m
memory8 by 1
0100 00XB 1101 0000 : mod 111 r/m
memory64 by 1
0100 10XB 1101 0001 : mod 111 r/m
register by CL
0100 000B 1101 001w : 11 111 reg
byteregister by CL
0100 000B 1101 0010 : 11 111 bytereg
qwordregister by CL
0100 100B 1101 0011 : 11 111 qwordreg
memory by CL
0100 00XB 1101 001w : mod 111 r/m
memory8 by CL
0100 00XB 1101 0010 : mod 111 r/m
memory64 by CL
0100 10XB 1101 0011 : mod 111 r/m
register by immediate count
0100 000B 1100 000w : 11 111 reg : imm8
byteregister by immediate count
0100 000B 1100 0000 : 11 111 bytereg : imm8
qwordregister by immediate count
0100 100B 1100 0001 : 11 111 qwordreg : imm8
memory by immediate count
0100 00XB 1100 000w : mod 111 r/m : imm8
memory8 by immediate count
0100 00XB 1100 0000 : mod 111 r/m : imm8
memory64 by immediate count
0100 10XB 1100 0001 : mod 111 r/m : imm8
SBB - Integer Subtraction with Borrow
register1 to register2
0100 0R0B 0001 100w : 11 reg1 reg2
byteregister1 to byteregister2
0100 0R0B 0001 1000 : 11 bytereg1 bytereg2
quadregister1 to quadregister2
0100 1R0B 0001 1001 : 11 quadreg1 quadreg2
register2 to register1
0100 0R0B 0001 101w : 11 reg1 reg2
byteregister2 to byteregister1
0100 0R0B 0001 1010 : 11 reg1 bytereg2
byteregister2 to byteregister1
0100 1R0B 0001 1011 : 11 reg1 bytereg2
memory to register
0100 0RXB 0001 101w : mod reg r/m
memory8 to byteregister
0100 0RXB 0001 1010 : mod bytereg r/m
memory64 to byteregister
0100 1RXB 0001 1011 : mod quadreg r/m
Vol. 2D B-31
INSTRUCTION FORMATS AND ENCODINGS
Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format
Encoding
register to memory
0100 0RXB 0001 100w : mod reg r/m
byteregister to memory8
0100 0RXB 0001 1000 : mod reg r/m
quadregister to memory64
0100 1RXB 0001 1001 : mod reg r/m
immediate to register
0100 000B 1000 00sw : 11 011 reg : imm
immediate8 to byteregister
0100 000B 1000 0000 : 11 011 bytereg : imm8
immediate32 to qwordregister
0100 100B 1000 0001 : 11 011 qwordreg : imm32
immediate8 to qwordregister
0100 100B 1000 0011 : 11 011 qwordreg : imm8
immediate to AL, AX, or EAX
0100 000B 0001 110w : imm
immediate32 to RAL
0100 1000 0001 1101 : imm32
immediate to memory
0100 00XB 1000 00sw : mod 011 r/m : imm
immediate8 to memory8
0100 00XB 1000 0000 : mod 011 r/m : imm8
immediate32 to memory64
0100 10XB 1000 0001 : mod 011 r/m : imm32
immediate8 to memory64
0100 10XB 1000 0011 : mod 011 r/m : imm8
SCAS/SCASB/SCASW/SCASD - Scan String
scan string
1010 111w
scan string (compare AL with byte at RDI)
0100 1000 1010 1110
scan string (compare RAX with qword at RDI)
0100 1000 1010 1111
SETcc - Byte Set on Condition
register
0100 000B 0000 1111 : 1001 tttn : 11 000 reg
register
0100 0000 0000 1111 : 1001 tttn : 11 000 reg
memory
0100 00XB 0000 1111 : 1001 tttn : mod 000 r/m
memory
0100 0000 0000 1111 : 1001 tttn : mod 000 r/m
SGDT - Store Global Descriptor Table Register
0000 1111 : 0000 0001 : modA 000 r/m
SHL - Shift Left
register by 1
0100 000B 1101 000w : 11 100 reg
byteregister by 1
0100 000B 1101 0000 : 11 100 bytereg
qwordregister by 1
0100 100B 1101 0001 : 11 100 qwordreg
memory by 1
0100 00XB 1101 000w : mod 100 r/m
memory8 by 1
0100 00XB 1101 0000 : mod 100 r/m
memory64 by 1
0100 10XB 1101 0001 : mod 100 r/m
register by CL
0100 000B 1101 001w : 11 100 reg
byteregister by CL
0100 000B 1101 0010 : 11 100 bytereg
qwordregister by CL
0100 100B 1101 0011 : 11 100 qwordreg
memory by CL
0100 00XB 1101 001w : mod 100 r/m
memory8 by CL
0100 00XB 1101 0010 : mod 100 r/m
memory64 by CL
0100 10XB 1101 0011 : mod 100 r/m
register by immediate count
0100 000B 1100 000w : 11 100 reg : imm8
byteregister by immediate count
0100 000B 1100 0000 : 11 100 bytereg : imm8
B-32
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format
Encoding
quadregister by immediate count
0100 100B 1100 0001 : 11 100 quadreg : imm8
memory by immediate count
0100 00XB 1100 000w : mod 100 r/m : imm8
memory8 by immediate count
0100 00XB 1100 0000 : mod 100 r/m : imm8
memory64 by immediate count
0100 10XB 1100 0001 : mod 100 r/m : imm8
SHLD - Double Precision Shift Left
register by immediate count
0100 0R0B 0000 1111 : 1010 0100 : 11 reg2 reg1 : imm8
qwordregister by immediate8
0100 1R0B 0000 1111 : 1010 0100 : 11 qworddreg2
qwordreg1 : imm8
memory by immediate count
0100 0RXB 0000 1111 : 1010 0100 : mod reg r/m : imm8
memory64 by immediate8
0100 1RXB 0000 1111 : 1010 0100 : mod qwordreg r/m :
imm8
register by CL
0100 0R0B 0000 1111 : 1010 0101 : 11 reg2 reg1
quadregister by CL
0100 1R0B 0000 1111 : 1010 0101 : 11 quadreg2 quadreg1
memory by CL
0100 00XB 0000 1111 : 1010 0101 : mod reg r/m
memory64 by CL
0100 1RXB 0000 1111 : 1010 0101 : mod quadreg r/m
SHR - Shift Right
register by 1
0100 000B 1101 000w : 11 101 reg
byteregister by 1
0100 000B 1101 0000 : 11 101 bytereg
qwordregister by 1
0100 100B 1101 0001 : 11 101 qwordreg
memory by 1
0100 00XB 1101 000w : mod 101 r/m
memory8 by 1
0100 00XB 1101 0000 : mod 101 r/m
memory64 by 1
0100 10XB 1101 0001 : mod 101 r/m
register by CL
0100 000B 1101 001w : 11 101 reg
byteregister by CL
0100 000B 1101 0010 : 11 101 bytereg
qwordregister by CL
0100 100B 1101 0011 : 11 101 qwordreg
memory by CL
0100 00XB 1101 001w : mod 101 r/m
memory8 by CL
0100 00XB 1101 0010 : mod 101 r/m
memory64 by CL
0100 10XB 1101 0011 : mod 101 r/m
register by immediate count
0100 000B 1100 000w : 11 101 reg : imm8
byteregister by immediate count
0100 000B 1100 0000 : 11 101 reg : imm8
qwordregister by immediate count
0100 100B 1100 0001 : 11 101 reg : imm8
memory by immediate count
0100 00XB 1100 000w : mod 101 r/m : imm8
memory8 by immediate count
0100 00XB 1100 0000 : mod 101 r/m : imm8
memory64 by immediate count
0100 10XB 1100 0001 : mod 101 r/m : imm8
SHRD - Double Precision Shift Right
register by immediate count
0100 0R0B 0000 1111 : 1010 1100 : 11 reg2 reg1 : imm8
qwordregister by immediate8
0100 1R0B 0000 1111 : 1010 1100 : 11 qwordreg2
qwordreg1 : imm8
memory by immediate count
0100 00XB 0000 1111 : 1010 1100 : mod reg r/m : imm8
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INSTRUCTION FORMATS AND ENCODINGS
Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format
Encoding
memory64 by immediate8
0100 1RXB 0000 1111 : 1010 1100 : mod qwordreg r/m :
imm8
register by CL
0100 000B 0000 1111 : 1010 1101 : 11 reg2 reg1
qwordregister by CL
0100 1R0B 0000 1111 : 1010 1101 : 11 qwordreg2
qwordreg1
memory by CL
0000 1111 : 1010 1101 : mod reg r/m
memory64 by CL
0100 1RXB 0000 1111 : 1010 1101 : mod qwordreg r/m
SIDT - Store Interrupt Descriptor Table Register
0000 1111 : 0000 0001 : modA 001 r/m
SLDT - Store Local Descriptor Table Register
to register
0100 000B 0000 1111 : 0000 0000 : 11 000 reg
to memory
0100 00XB 0000 1111 : 0000 0000 : mod 000 r/m
SMSW - Store Machine Status Word
to register
0100 000B 0000 1111 : 0000 0001 : 11 100 reg
to memory
0100 00XB 0000 1111 : 0000 0001 : mod 100 r/m
STC - Set Carry Flag
1111 1001
STD - Set Direction Flag
1111 1101
STI - Set Interrupt Flag
1111 1011
STOS/STOSB/STOSW/STOSD/STOSQ - Store String Data
store string data
1010 101w
store string data (RAX at address RDI)
0100 1000 1010 1011
STR - Store Task Register
to register
0100 000B 0000 1111 : 0000 0000 : 11 001 reg
to memory
0100 00XB 0000 1111 : 0000 0000 : mod 001 r/m
SUB - Integer Subtraction
register1 from register2
0100 0R0B 0010 100w : 11 reg1 reg2
byteregister1 from byteregister2
0100 0R0B 0010 1000 : 11 bytereg1 bytereg2
qwordregister1 from qwordregister2
0100 1R0B 0010 1000 : 11 qwordreg1 qwordreg2
register2 from register1
0100 0R0B 0010 101w : 11 reg1 reg2
byteregister2 from byteregister1
0100 0R0B 0010 1010 : 11 bytereg1 bytereg2
qwordregister2 from qwordregister1
0100 1R0B 0010 1011 : 11 qwordreg1 qwordreg2
memory from register
0100 00XB 0010 101w : mod reg r/m
memory8 from byteregister
0100 0RXB 0010 1010 : mod bytereg r/m
memory64 from qwordregister
0100 1RXB 0010 1011 : mod qwordreg r/m
register from memory
0100 0RXB 0010 100w : mod reg r/m
byteregister from memory8
0100 0RXB 0010 1000 : mod bytereg r/m
qwordregister from memory8
0100 1RXB 0010 1000 : mod qwordreg r/m
immediate from register
0100 000B 1000 00sw : 11 101 reg : imm
immediate8 from byteregister
0100 000B 1000 0000 : 11 101 bytereg : imm8
immediate32 from qwordregister
0100 100B 1000 0001 : 11 101 qwordreg : imm32
B-34
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format
Encoding
immediate8 from qwordregister
0100 100B 1000 0011 : 11 101 qwordreg : imm8
immediate from AL, AX, or EAX
0100 000B 0010 110w : imm
immediate32 from RAX
0100 1000 0010 1101 : imm32
immediate from memory
0100 00XB 1000 00sw : mod 101 r/m : imm
immediate8 from memory8
0100 00XB 1000 0000 : mod 101 r/m : imm8
immediate32 from memory64
0100 10XB 1000 0001 : mod 101 r/m : imm32
immediate8 from memory64
0100 10XB 1000 0011 : mod 101 r/m : imm8
SWAPGS - Swap GS Base Register
Exchanges the current GS base register value for value in MSR
0000 1111 0000 0001 1111 1000
C0000102H
SYSCALL - Fast System Call
fast call to privilege level 0 system procedures
0000 1111 0000 0101
SYSRET - Return From Fast System Call
return from fast system call
0000 1111 0000 0111
TEST - Logical Compare
register1 and register2
0100 0R0B 1000 010w : 11 reg1 reg2
byteregister1 and byteregister2
0100 0R0B 1000 0100 : 11 bytereg1 bytereg2
qwordregister1 and qwordregister2
0100 1R0B 1000 0101 : 11 qwordreg1 qwordreg2
memory and register
0100 0R0B 1000 010w : mod reg r/m
memory8 and byteregister
0100 0RXB 1000 0100 : mod bytereg r/m
memory64 and qwordregister
0100 1RXB 1000 0101 : mod qwordreg r/m
immediate and register
0100 000B 1111 011w : 11 000 reg : imm
immediate8 and byteregister
0100 000B 1111 0110 : 11 000 bytereg : imm8
immediate32 and qwordregister
0100 100B 1111 0111 : 11 000 bytereg : imm8
immediate and AL, AX, or EAX
0100 000B 1010 100w : imm
immediate32 and RAX
0100 1000 1010 1001 : imm32
immediate and memory
0100 00XB 1111 011w : mod 000 r/m : imm
immediate8 and memory8
0100 1000 1111 0110 : mod 000 r/m : imm8
immediate32 and memory64
0100 1000 1111 0111 : mod 000 r/m : imm32
UD2 - Undefined instruction
0000 FFFF : 0000 1011
VERR - Verify a Segment for Reading
register
0100 000B 0000 1111 : 0000 0000 : 11 100 reg
memory
0100 00XB 0000 1111 : 0000 0000 : mod 100 r/m
VERW - Verify a Segment for Writing
register
0100 000B 0000 1111 : 0000 0000 : 11 101 reg
memory
0100 00XB 0000 1111 : 0000 0000 : mod 101 r/m
WAIT - Wait
1001 1011
WBINVD - Writeback and Invalidate Data Cache
0000 1111 : 0000 1001
Vol. 2D
B-35
INSTRUCTION FORMATS AND ENCODINGS
Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format
Encoding
WRMSR - Write to Model-Specific Register
write EDX:EAX to ECX specified MSR
0000 1111 : 0011 0000
write RDX[31:0]:RAX[31:0] to RCX specified MSR
0100 1000 0000 1111 : 0011 0000
XADD - Exchange and Add
register1, register2
0100 0R0B 0000 1111 : 1100 000w : 11 reg2 reg1
byteregister1, byteregister2
0100 0R0B 0000 1111 : 1100 0000 : 11 bytereg2 bytereg1
qwordregister1, qwordregister2
0100 0R0B 0000 1111 : 1100 0001 : 11 qwordreg2
qwordreg1
memory, register
0100 0RXB 0000 1111 : 1100 000w : mod reg r/m
memory8, bytereg
0100 1RXB 0000 1111 : 1100 0000 : mod bytereg r/m
memory64, qwordreg
0100 1RXB 0000 1111 : 1100 0001 : mod qwordreg r/m
XCHG - Exchange Register/Memory with Register
register1 with register2
1000 011w : 11 reg1 reg2
AX or EAX with register
1001 0 reg
memory with register
1000 011w : mod reg r/m
XLAT/XLATB - Table Look-up Translation
AL to byte DS:[(E)BX + unsigned AL]
1101 0111
AL to byte DS:[RBX + unsigned AL]
0100 1000 1101 0111
XOR - Logical Exclusive OR
register1 to register2
0100 0RXB 0011 000w : 11 reg1 reg2
byteregister1 to byteregister2
0100 0R0B 0011 0000 : 11 bytereg1 bytereg2
qwordregister1 to qwordregister2
0100 1R0B 0011 0001 : 11 qwordreg1 qwordreg2
register2 to register1
0100 0R0B 0011 001w : 11 reg1 reg2
byteregister2 to byteregister1
0100 0R0B 0011 0010 : 11 bytereg1 bytereg2
qwordregister2 to qwordregister1
0100 1R0B 0011 0011 : 11 qwordreg1 qwordreg2
memory to register
0100 0RXB 0011 001w : mod reg r/m
memory8 to byteregister
0100 0RXB 0011 0010 : mod bytereg r/m
memory64 to qwordregister
0100 1RXB 0011 0011 : mod qwordreg r/m
register to memory
0100 0RXB 0011 000w : mod reg r/m
byteregister to memory8
0100 0RXB 0011 0000 : mod bytereg r/m
qwordregister to memory8
0100 1RXB 0011 0001 : mod qwordreg r/m
immediate to register
0100 000B 1000 00sw : 11 110 reg : imm
immediate8 to byteregister
0100 000B 1000 0000 : 11 110 bytereg : imm8
immediate32 to qwordregister
0100 100B 1000 0001 : 11 110 qwordreg : imm32
immediate8 to qwordregister
0100 100B 1000 0011 : 11 110 qwordreg : imm8
immediate to AL, AX, or EAX
0100 000B 0011 010w : imm
immediate to RAX
0100 1000 0011 0101 : immediate data
immediate to memory
0100 00XB 1000 00sw : mod 110 r/m : imm
immediate8 to memory8
0100 00XB 1000 0000 : mod 110 r/m : imm8
B-36
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.)
Instruction and Format
Encoding
immediate32 to memory64
0100 10XB 1000 0001 : mod 110 r/m : imm32
immediate8 to memory64
0100 10XB 1000 0011 : mod 110 r/m : imm8
Prefix Bytes
address size
0110 0111
LOCK
1111 0000
operand size
0110 0110
CS segment override
0010 1110
DS segment override
0011 1110
ES segment override
0010 0110
FS segment override
0110 0100
GS segment override
0110 0101
SS segment override
0011 0110
B.3
PENTIUM® PROCESSOR FAMILY INSTRUCTION FORMATS AND ENCODINGS
The following table shows formats and encodings introduced by the Pentium processor family.
Table B-16. Pentium Processor Family Instruction Formats and Encodings, Non-64-Bit Modes
Instruction and Format
Encoding
CMPXCHG8B - Compare and Exchange 8 Bytes
EDX:EAX with memory64
0000 1111 : 1100 0111 : mod 001 r/m
Table B-17. Pentium Processor Family Instruction Formats and Encodings, 64-Bit Mode
Instruction and Format
Encoding
CMPXCHG8B/CMPXCHG16B - Compare and Exchange Bytes
EDX:EAX with memory64
0000 1111 : 1100 0111 : mod 001 r/m
RDX:RAX with memory128
0100 10XB 0000 1111 : 1100 0111 : mod 001 r/m
B.4
64-BIT MODE INSTRUCTION ENCODINGS FOR SIMD INSTRUCTION
EXTENSIONS
Non-64-bit mode instruction encodings for MMX Technology, SSE, SSE2, and SSE3 are covered by applying these
rules to Table B-19 through Table B-31. Table B-34 lists special encodings (instructions that do not follow the rules
below).
1. The REX instruction has no effect:
• On immediates.
• If both operands are MMX registers.
• On MMX registers and XMM registers.
• If an MMX register is encoded in the reg field of the ModR/M byte.
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INSTRUCTION FORMATS AND ENCODINGS
2. If a memory operand is encoded in the r/m field of the ModR/M byte, REX.X and REX.B may be used for
encoding the memory operand.
3. If a general-purpose register is encoded in the r/m field of the ModR/M byte, REX.B may be used for register
encoding and REX.W may be used to encode the 64-bit operand size.
4. If an XMM register operand is encoded in the reg field of the ModR/M byte, REX.R may be used for register
encoding. If an XMM register operand is encoded in the r/m field of the ModR/M byte, REX.B may be used for
register encoding.
B.5
MMX INSTRUCTION FORMATS AND ENCODINGS
MMX instructions, except the EMMS instruction, use a format similar to the 2-byte Intel Architecture integer format.
Details of subfield encodings within these formats are presented below.
B.5.1
Granularity Field (gg)
The granularity field (gg) indicates the size of the packed operands that the instruction is operating on. When this
field is used, it is located in bits 1 and 0 of the second opcode byte. Table B-18 shows the encoding of the gg field.
Table B-18. Encoding of Granularity of Data Field (gg)
gg
Granularity of Data
00
Packed Bytes
01
Packed Words
10
Packed Doublewords
11
Quadword
B.5.2
MMX Technology and General-Purpose Register Fields (mmxreg and reg)
When MMX technology registers (mmxreg) are used as operands, they are encoded in the ModR/M byte in the reg
field (bits 5, 4, and 3) and/or the R/M field (bits 2, 1, and 0).
If an MMX instruction operates on a general-purpose register (reg), the register is encoded in the R/M field of the
ModR/M byte.
B.5.3
MMX Instruction Formats and Encodings Table
Table B-19 shows the formats and encodings of the integer instructions.
Table B-19. MMX Instruction Formats and Encodings
Instruction and Format
Encoding
EMMS - Empty MMX technology state
0000 1111:01110111
MOVD - Move doubleword
reg to mmxreg
0000 1111:0110 1110: 11 mmxreg reg
reg from mmxreg
0000 1111:0111 1110: 11 mmxreg reg
mem to mmxreg
0000 1111:0110 1110: mod mmxreg r/m
mem from mmxreg
0000 1111:0111 1110: mod mmxreg r/m
MOVQ - Move quadword
mmxreg2 to mmxreg1
0000 1111:0110 1111: 11 mmxreg1 mmxreg2
mmxreg2 from mmxreg1
0000 1111:0111 1111: 11 mmxreg1 mmxreg2
B-38
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-19. MMX Instruction Formats and Encodings (Contd.)
Instruction and Format
Encoding
mem to mmxreg
0000 1111:0110 1111: mod mmxreg r/m
mem from mmxreg
0000 1111:0111 1111: mod mmxreg r/m
PACKSSDW1 - Pack dword to word data (signed with saturation)
mmxreg2 to mmxreg1
0000 1111:0110 1011: 11 mmxreg1 mmxreg2
memory to mmxreg
0000 1111:0110 1011: mod mmxreg r/m
PACKSSWB1 - Pack word to byte data (signed with saturation)
mmxreg2 to mmxreg1
0000 1111:0110 0011: 11 mmxreg1 mmxreg2
memory to mmxreg
0000 1111:0110 0011: mod mmxreg r/m
PACKUSWB1 - Pack word to byte data (unsigned with saturation)
mmxreg2 to mmxreg1
0000 1111:0110 0111: 11 mmxreg1 mmxreg2
memory to mmxreg
0000 1111:0110 0111: mod mmxreg r/m
PADD - Add with wrap-around
mmxreg2 to mmxreg1
0000 1111: 1111 11gg: 11 mmxreg1 mmxreg2
memory to mmxreg
0000 1111: 1111 11gg: mod mmxreg r/m
PADDS - Add signed with saturation
mmxreg2 to mmxreg1
0000 1111: 1110 11gg: 11 mmxreg1 mmxreg2
memory to mmxreg
0000 1111: 1110 11gg: mod mmxreg r/m
PADDUS - Add unsigned with saturation
mmxreg2 to mmxreg1
0000 1111: 1101 11gg: 11 mmxreg1 mmxreg2
memory to mmxreg
0000 1111: 1101 11gg: mod mmxreg r/m
PAND - Bitwise And
mmxreg2 to mmxreg1
0000 1111:1101 1011: 11 mmxreg1 mmxreg2
memory to mmxreg
0000 1111:1101 1011: mod mmxreg r/m
PANDN - Bitwise AndNot
mmxreg2 to mmxreg1
0000 1111:1101 1111: 11 mmxreg1 mmxreg2
memory to mmxreg
0000 1111:1101 1111: mod mmxreg r/m
PCMPEQ - Packed compare for equality
mmxreg1 with mmxreg2
0000 1111:0111 01gg: 11 mmxreg1 mmxreg2
mmxreg with memory
0000 1111:0111 01gg: mod mmxreg r/m
PCMPGT - Packed compare greater (signed)
mmxreg1 with mmxreg2
0000 1111:0110 01gg: 11 mmxreg1 mmxreg2
mmxreg with memory
0000 1111:0110 01gg: mod mmxreg r/m
PMADDWD - Packed multiply add
mmxreg2 to mmxreg1
0000 1111:1111 0101: 11 mmxreg1 mmxreg2
memory to mmxreg
0000 1111:1111 0101: mod mmxreg r/m
PMULHUW - Packed multiplication, store high word (unsigned)
mmxreg2 to mmxreg1
0000 1111: 1110 0100: 11 mmxreg1 mmxreg2
memory to mmxreg
0000 1111: 1110 0100: mod mmxreg r/m
Vol. 2D B-39
INSTRUCTION FORMATS AND ENCODINGS
Table B-19. MMX Instruction Formats and Encodings (Contd.)
Instruction and Format
Encoding
PMULHW - Packed multiplication, store high word
mmxreg2 to mmxreg1
0000 1111:1110 0101: 11 mmxreg1 mmxreg2
memory to mmxreg
0000 1111:1110 0101: mod mmxreg r/m
PMULLW - Packed multiplication, store low word
mmxreg2 to mmxreg1
0000 1111:1101 0101: 11 mmxreg1 mmxreg2
memory to mmxreg
0000 1111:1101 0101: mod mmxreg r/m
POR - Bitwise Or
mmxreg2 to mmxreg1
0000 1111:1110 1011: 11 mmxreg1 mmxreg2
memory to mmxreg
0000 1111:1110 1011: mod mmxreg r/m
PSLL2 - Packed shift left logical
mmxreg1 by mmxreg2
0000 1111:1111 00gg: 11 mmxreg1 mmxreg2
mmxreg by memory
0000 1111:1111 00gg: mod mmxreg r/m
mmxreg by immediate
0000 1111:0111 00gg: 11 110 mmxreg: imm8 data
PSRA2 - Packed shift right arithmetic
mmxreg1 by mmxreg2
0000 1111:1110 00gg: 11 mmxreg1 mmxreg2
mmxreg by memory
0000 1111:1110 00gg: mod mmxreg r/m
mmxreg by immediate
0000 1111:0111 00gg: 11 100 mmxreg: imm8 data
PSRL2 - Packed shift right logical
mmxreg1 by mmxreg2
0000 1111:1101 00gg: 11 mmxreg1 mmxreg2
mmxreg by memory
0000 1111:1101 00gg: mod mmxreg r/m
mmxreg by immediate
0000 1111:0111 00gg: 11 010 mmxreg: imm8 data
PSUB - Subtract with wrap-around
mmxreg2 from mmxreg1
0000 1111:1111 10gg: 11 mmxreg1 mmxreg2
memory from mmxreg
0000 1111:1111 10gg: mod mmxreg r/m
PSUBS - Subtract signed with saturation
mmxreg2 from mmxreg1
0000 1111:1110 10gg: 11 mmxreg1 mmxreg2
memory from mmxreg
0000 1111:1110 10gg: mod mmxreg r/m
PSUBUS - Subtract unsigned with saturation
mmxreg2 from mmxreg1
0000 1111:1101 10gg: 11 mmxreg1 mmxreg2
memory from mmxreg
0000 1111:1101 10gg: mod mmxreg r/m
PUNPCKH - Unpack high data to next larger type
mmxreg2 to mmxreg1
0000 1111:0110 10gg: 11 mmxreg1 mmxreg2
memory to mmxreg
0000 1111:0110 10gg: mod mmxreg r/m
PUNPCKL - Unpack low data to next larger type
mmxreg2 to mmxreg1
0000 1111:0110 00gg: 11 mmxreg1 mmxreg2
memory to mmxreg
0000 1111:0110 00gg: mod mmxreg r/m
B-40
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-19. MMX Instruction Formats and Encodings (Contd.)
Instruction and Format
Encoding
PXOR - Bitwise Xor
mmxreg2 to mmxreg1
0000 1111:1110 1111: 11 mmxreg1 mmxreg2
memory to mmxreg
0000 1111:1110 1111: mod mmxreg r/m
NOTES:
1. The pack instructions perform saturation from signed packed data of one type to signed or unsigned data of the next smaller type.
2. The format of the shift instructions has one additional format to support shifting by immediate shift-counts. The shift operations
are not supported equally for all data types.
B.6
PROCESSOR EXTENDED STATE INSTRUCTION FORMATS AND ENCODINGS
Table B-20 shows the formats and encodings for several instructions that relate to processor extended state
management.
Table B-20. Formats and Encodings of XSAVE/XRSTOR/XGETBV/XSETBV Instructions
Instruction and Format
Encoding
XGETBV - Get Value of Extended Control Register
0000 1111:0000 0001: 1101 0000
XRSTOR - Restore Processor Extended States1
0000 1111:1010 1110: modA 101 r/m
XSAVE - Save Processor Extended States1
0000 1111:1010 1110: modA 100 r/m
XSETBV - Set Extended Control Register
0000 1111:0000 0001: 1101 0001
NOTES:
1. For XSAVE and XRSTOR, “mod = 11” is reserved.
B.7
P6 FAMILY INSTRUCTION FORMATS AND ENCODINGS
Table B-20 shows the formats and encodings for several instructions that were introduced into the IA-32 architec-
ture in the P6 family processors.
Table B-21. Formats and Encodings of P6 Family Instructions
Instruction and Format
Encoding
CMOVcc - Conditional Move
register2 to register1
0000 1111: 0100 tttn : 11 reg1 reg2
memory to register
0000 1111 : 0100 tttn : mod reg r/m
FCMOVcc - Conditional Move on EFLAG Register Condition Codes
move if below (B)
11011 010 : 11 000 ST(i)
move if equal (E)
11011 010 : 11 001 ST(i)
move if below or equal (BE)
11011 010 : 11 010 ST(i)
move if unordered (U)
11011 010 : 11 011 ST(i)
move if not below (NB)
11011 011 : 11 000 ST(i)
move if not equal (NE)
11011 011 : 11 001 ST(i)
move if not below or equal (NBE)
11011 011 : 11 010 ST(i)
Vol. 2D B-41
INSTRUCTION FORMATS AND ENCODINGS
Table B-21. Formats and Encodings of P6 Family Instructions (Contd.)
Instruction and Format
Encoding
move if not unordered (NU)
11011 011 : 11 011 ST(i)
FCOMI - Compare Real and Set EFLAGS
11011 011 : 11 110 ST(i)
FXRSTOR - Restore x87 FPU, MMX, SSE, and SSE2 State1
0000 1111:1010 1110: modA 001 r/m
FXSAVE - Save x87 FPU, MMX, SSE, and SSE2 State1
0000 1111:1010 1110: modA 000 r/m
SYSENTER - Fast System Call
0000 1111:0011 0100
SYSEXIT - Fast Return from Fast System Call
0000 1111:0011 0101
NOTES:
1. For FXSAVE and FXRSTOR, “mod = 11” is reserved.
B.8
SSE INSTRUCTION FORMATS AND ENCODINGS
The SSE instructions use the ModR/M format and are preceded by the 0FH prefix byte. In general, operations are
not duplicated to provide two directions (that is, separate load and store variants).
The following three tables (Tables B-22, B-23, and B-24) show the formats and encodings for the SSE SIMD
floating-point, SIMD integer, and cacheability and memory ordering instructions, respectively. Some SSE instruc-
tions require a mandatory prefix (66H, F2H, F3H) as part of the two-byte opcode. Mandatory prefixes are included
in the tables.
Table B-22. Formats and Encodings of SSE Floating-Point Instructions
Instruction and Format
Encoding
ADDPS—Add Packed Single Precision Floating-Point Values
xmmreg2 to xmmreg1
0000 1111:0101 1000:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0101 1000: mod xmmreg r/m
ADDSS—Add Scalar Single Precision Floating-Point Values
xmmreg2 to xmmreg1
1111 0011:0000 1111:01011000:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0011:0000 1111:01011000: mod xmmreg r/m
ANDNPS—Bitwise Logical AND NOT of Packed Single Precision Floating-Point Values
xmmreg2 to xmmreg1
0000 1111:0101 0101:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0101 0101: mod xmmreg r/m
ANDPS—Bitwise Logical AND of Packed Single Precision Floating-Point Values
xmmreg2 to xmmreg1
0000 1111:0101 0100:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0101 0100: mod xmmreg r/m
CMPPS—Compare Packed Single Precision Floating-Point Values
xmmreg2 to xmmreg1, imm8
0000 1111:1100 0010:11 xmmreg1 xmmreg2: imm8
mem to xmmreg, imm8
0000 1111:1100 0010: mod xmmreg r/m: imm8
CMPSS—Compare Scalar Single Precision Floating-Point Values
xmmreg2 to xmmreg1, imm8
1111 0011:0000 1111:1100 0010:11 xmmreg1 xmmreg2: imm8
mem to xmmreg, imm8
1111 0011:0000 1111:1100 0010: mod xmmreg r/m: imm8
COMISS—Compare Scalar Ordered Single Precision Floating-Point Values and Set EFLAGS
xmmreg2 to xmmreg1
0000 1111:0010 1111:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0010 1111: mod xmmreg r/m
B-42
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-22. Formats and Encodings of SSE Floating-Point Instructions (Contd.)
Instruction and Format
Encoding
CVTPI2PS—Convert Packed Doubleword Integers to Packed Single Precision Floating-Point Values
mmreg to xmmreg
0000 1111:0010 1010:11 xmmreg1 mmreg1
mem to xmmreg
0000 1111:0010 1010: mod xmmreg r/m
CVTPS2PI—Convert Packed Single Precision Floating-Point Values to Packed Doubleword Integers
xmmreg to mmreg
0000 1111:0010 1101:11 mmreg1 xmmreg1
mem to mmreg
0000 1111:0010 1101: mod mmreg r/m
CVTSI2SS—Convert Doubleword Integer to Scalar Single Precision Floating-Point Value
r32 to xmmreg1
1111 0011:0000 1111:00101010:11 xmmreg1 r32
mem to xmmreg
1111 0011:0000 1111:00101010: mod xmmreg r/m
CVTSS2SI—Convert Scalar Single Precision Floating-Point Value to Doubleword Integer
xmmreg to r32
1111 0011:0000 1111:0010 1101:11 r32 xmmreg
mem to r32
1111 0011:0000 1111:0010 1101: mod r32 r/m
CVTTPS2PI—Convert with Truncation Packed Single Precision Floating-Point Values to Packed Doubleword Integers
xmmreg to mmreg
0000 1111:0010 1100:11 mmreg1 xmmreg1
mem to mmreg
0000 1111:0010 1100: mod mmreg r/m
CVTTSS2SI—Convert with Truncation Scalar Single Precision Floating-Point Value to Doubleword Integer
xmmreg to r32
1111 0011:0000 1111:0010 1100:11 r32 xmmreg1
mem to r32
1111 0011:0000 1111:0010 1100: mod r32 r/m
DIVPS—Divide Packed Single Precision Floating-Point Values
xmmreg2 to xmmreg1
0000 1111:0101 1110:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0101 1110: mod xmmreg r/m
DIVSS—Divide Scalar Single Precision Floating-Point Values
xmmreg2 to xmmreg1
1111 0011:0000 1111:0101 1110:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0011:0000 1111:0101 1110: mod xmmreg r/m
LDMXCSR—Load MXCSR Register State
m32 to MXCSR
0000 1111:1010 1110:modA 010 mem
MAXPS—Return Maximum Packed Single Precision Floating-Point Values
xmmreg2 to xmmreg1
0000 1111:0101 1111:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0101 1111: mod xmmreg r/m
MAXSS—Return Maximum Scalar Double Precision Floating-Point Value
xmmreg2 to xmmreg1
1111 0011:0000 1111:0101 1111:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0011:0000 1111:0101 1111: mod xmmreg r/m
MINPS—Return Minimum Packed Double Precision Floating-Point Values
xmmreg2 to xmmreg1
0000 1111:0101 1101:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0101 1101: mod xmmreg r/m
MINSS—Return Minimum Scalar Double Precision Floating-Point Value
xmmreg2 to xmmreg1
1111 0011:0000 1111:0101 1101:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0011:0000 1111:0101 1101: mod xmmreg r/m
Vol. 2D B-43
INSTRUCTION FORMATS AND ENCODINGS
Table B-22. Formats and Encodings of SSE Floating-Point Instructions (Contd.)
Instruction and Format
Encoding
MOVAPS—Move Aligned Packed Single Precision Floating-Point Values
xmmreg2 to xmmreg1
0000 1111:0010 1000:11 xmmreg2 xmmreg1
mem to xmmreg1
0000 1111:0010 1000: mod xmmreg r/m
xmmreg1 to xmmreg2
0000 1111:0010 1001:11 xmmreg1 xmmreg2
xmmreg1 to mem
0000 1111:0010 1001: mod xmmreg r/m
MOVHLPS—Move Packed Single Precision Floating-Point Values High to Low
xmmreg2 to xmmreg1
0000 1111:0001 0010:11 xmmreg1 xmmreg2
MOVHPS—Move High Packed Single Precision Floating-Point Values
mem to xmmreg
0000 1111:0001 0110: mod xmmreg r/m
xmmreg to mem
0000 1111:0001 0111: mod xmmreg r/m
MOVLHPS—Move Packed Single Precision Floating-Point Values Low to High
xmmreg2 to xmmreg1
0000 1111:00010110:11 xmmreg1 xmmreg2
MOVLPS—Move Low Packed Single Precision Floating-Point Values
mem to xmmreg
0000 1111:0001 0010: mod xmmreg r/m
xmmreg to mem
0000 1111:0001 0011: mod xmmreg r/m
MOVMSKPS—Extract Packed Single Precision Floating-Point Sign Mask
xmmreg to r32
0000 1111:0101 0000:11 r32 xmmreg
MOVSS—Move Scalar Single Precision Floating-Point Values
xmmreg2 to xmmreg1
1111 0011:0000 1111:0001 0000:11 xmmreg2 xmmreg1
mem to xmmreg1
1111 0011:0000 1111:0001 0000: mod xmmreg r/m
xmmreg1 to xmmreg2
1111 0011:0000 1111:0001 0001:11 xmmreg1 xmmreg2
xmmreg1 to mem
1111 0011:0000 1111:0001 0001: mod xmmreg r/m
MOVUPS—Move Unaligned Packed Single Precision Floating-Point Values
xmmreg2 to xmmreg1
0000 1111:0001 0000:11 xmmreg2 xmmreg1
mem to xmmreg1
0000 1111:0001 0000: mod xmmreg r/m
xmmreg1 to xmmreg2
0000 1111:0001 0001:11 xmmreg1 xmmreg2
xmmreg1 to mem
0000 1111:0001 0001: mod xmmreg r/m
MULPS—Multiply Packed Single Precision Floating-Point Values
xmmreg2 to xmmreg1
0000 1111:0101 1001:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0101 1001: mod xmmreg r/m
MULSS—Multiply Scalar Single Precision Floating-Point Values
xmmreg2 to xmmreg1
1111 0011:0000 1111:0101 1001:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0011:0000 1111:0101 1001: mod xmmreg r/m
ORPS—Bitwise Logical OR of Single Precision Floating-Point Values
xmmreg2 to xmmreg1
0000 1111:0101 0110:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0101 0110: mod xmmreg r/m
RCPPS—Compute Reciprocals of Packed Single Precision Floating-Point Values
xmmreg2 to xmmreg1
0000 1111:0101 0011:11 xmmreg1 xmmreg2
B-44
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-22. Formats and Encodings of SSE Floating-Point Instructions (Contd.)
Instruction and Format
Encoding
mem to xmmreg
0000 1111:0101 0011: mod xmmreg r/m
RCPSS—Compute Reciprocals of Scalar Single Precision Floating-Point Value
xmmreg2 to xmmreg1
1111 0011:0000 1111:01010011:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0011:0000 1111:01010011: mod xmmreg r/m
RSQRTPS—Compute Reciprocals of Square Roots of Packed Single Precision Floating-Point Values
xmmreg2 to xmmreg1
0000 1111:0101 0010:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0101 0010: mode xmmreg r/m
RSQRTSS—Compute Reciprocals of Square Roots of Scalar Single Precision Floating-Point Value
xmmreg2 to xmmreg1
1111 0011:0000 1111:0101 0010:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0011:0000 1111:0101 0010: mod xmmreg r/m
SHUFPS—Shuffle Packed Single Precision Floating-Point Values
xmmreg2 to xmmreg1, imm8
0000 1111:1100 0110:11 xmmreg1 xmmreg2: imm8
mem to xmmreg, imm8
0000 1111:1100 0110: mod xmmreg r/m: imm8
SQRTPS—Compute Square Roots of Packed Single Precision Floating-Point Values
xmmreg2 to xmmreg1
0000 1111:0101 0001:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0101 0001: mod xmmreg r/m
SQRTSS—Compute Square Root of Scalar Single Precision Floating-Point Value
xmmreg2 to xmmreg1
1111 0011:0000 1111:0101 0001:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0011:0000 1111:0101 0001:mod xmmreg r/m
STMXCSR—Store MXCSR Register State
MXCSR to mem
0000 1111:1010 1110:modA 011 mem
SUBPS—Subtract Packed Single Precision Floating-Point Values
xmmreg2 to xmmreg1
0000 1111:0101 1100:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0101 1100:mod xmmreg r/m
SUBSS—Subtract Scalar Single Precision Floating-Point Values
xmmreg2 to xmmreg1
1111 0011:0000 1111:0101 1100:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0011:0000 1111:0101 1100:mod xmmreg r/m
UCOMISS—Unordered Compare Scalar Ordered Single Precision Floating-Point Values and Set EFLAGS
xmmreg2 to xmmreg1
0000 1111:0010 1110:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0010 1110: mod xmmreg r/m
UNPCKHPS—Unpack and Interleave High Packed Single Precision Floating-Point Values
xmmreg2 to xmmreg1
0000 1111:0001 0101:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0001 0101: mod xmmreg r/m
UNPCKLPS—Unpack and Interleave Low Packed Single Precision Floating-Point Values
xmmreg2 to xmmreg1
0000 1111:0001 0100:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0001 0100: mod xmmreg r/m
XORPS—Bitwise Logical XOR of Single Precision Floating-Point Values
xmmreg2 to xmmreg1
0000 1111:0101 0111:11 xmmreg1 xmmreg2
Vol. 2D B-45
INSTRUCTION FORMATS AND ENCODINGS
Table B-22. Formats and Encodings of SSE Floating-Point Instructions (Contd.)
Instruction and Format
Encoding
mem to xmmreg
0000 1111:0101 0111: mod xmmreg r/m
Table B-23. Formats and Encodings of SSE Integer Instructions
Instruction and Format
Encoding
PAVGB/PAVGW—Average Packed Integers
mmreg2 to mmreg1
0000 1111:1110 0000:11 mmreg1 mmreg2
0000 1111:1110 0011:11 mmreg1 mmreg2
mem to mmreg
0000 1111:1110 0000: mod mmreg r/m
0000 1111:1110 0011: mod mmreg r/m
PEXTRW—Extract Word
mmreg to reg32, imm8
0000 1111:1100 0101:11 r32 mmreg: imm8
PINSRW—Insert Word
reg32 to mmreg, imm8
0000 1111:1100 0100:11 mmreg r32: imm8
m16 to mmreg, imm8
0000 1111:1100 0100: mod mmreg r/m: imm8
PMAXSW—Maximum of Packed Signed Word Integers
mmreg2 to mmreg1
0000 1111:1110 1110:11 mmreg1 mmreg2
mem to mmreg
0000 1111:1110 1110: mod mmreg r/m
PMAXUB—Maximum of Packed Unsigned Byte Integers
mmreg2 to mmreg1
0000 1111:1101 1110:11 mmreg1 mmreg2
mem to mmreg
0000 1111:1101 1110: mod mmreg r/m
PMINSW—Minimum of Packed Signed Word Integers
mmreg2 to mmreg1
0000 1111:1110 1010:11 mmreg1 mmreg2
mem to mmreg
0000 1111:1110 1010: mod mmreg r/m
PMINUB—Minimum of Packed Unsigned Byte Integers
mmreg2 to mmreg1
0000 1111:1101 1010:11 mmreg1 mmreg2
mem to mmreg
0000 1111:1101 1010: mod mmreg r/m
PMOVMSKB—Move Byte Mask To Integer
mmreg to reg32
0000 1111:1101 0111:11 r32 mmreg
PMULHUW—Multiply Packed Unsigned Integers and Store High Result
mmreg2 to mmreg1
0000 1111:1110 0100:11 mmreg1 mmreg2
mem to mmreg
0000 1111:1110 0100: mod mmreg r/m
PSADBW—Compute Sum of Absolute Differences
mmreg2 to mmreg1
0000 1111:1111 0110:11 mmreg1 mmreg2
mem to mmreg
0000 1111:1111 0110: mod mmreg r/m
PSHUFW—Shuffle Packed Words
mmreg2 to mmreg1, imm8
0000 1111:0111 0000:11 mmreg1 mmreg2: imm8
mem to mmreg, imm8
0000 1111:0111 0000: mod mmreg r/m: imm8
B-46
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-24. Format and Encoding of SSE Cacheability & Memory Ordering Instructions
Instruction and Format
Encoding
MASKMOVQ—Store Selected Bytes of Quadword
mmreg2 to mmreg1
0000 1111:1111 0111:11 mmreg1 mmreg2
MOVNTPS—Store Packed Single Precision Floating-Point Values Using Non-Temporal Hint
xmmreg to mem
0000 1111:0010 1011: mod xmmreg r/m
MOVNTQ—Store Quadword Using Non-Temporal Hint
mmreg to mem
0000 1111:1110 0111: mod mmreg r/m
PREFETCHT0—Prefetch Temporal to All Cache Levels
0000 1111:0001 1000:modA 001 mem
PREFETCHT1—Prefetch Temporal to First Level Cache
0000 1111:0001 1000:modA 010 mem
PREFETCHT2—Prefetch Temporal to Second Level Cache
0000 1111:0001 1000:modA 011 mem
PREFETCHNTA—Prefetch Non-Temporal to All Cache Levels
0000 1111:0001 1000:modA 000 mem
SFENCE—Store Fence
0000 1111:1010 1110:11 111 000
B.9
SSE2 INSTRUCTION FORMATS AND ENCODINGS
The SSE2 instructions use the ModR/M format and are preceded by the 0FH prefix byte. In general, operations are
not duplicated to provide two directions (that is, separate load and store variants).
The following three tables show the formats and encodings for the SSE2 SIMD floating-point, SIMD integer, and
cacheability instructions, respectively. Some SSE2 instructions require a mandatory prefix (66H, F2H, F3H) as part
of the two-byte opcode. These prefixes are included in the tables.
B.9.1
Granularity Field (gg)
The granularity field (gg) indicates the size of the packed operands that the instruction is operating on. When this
field is used, it is located in bits 1 and 0 of the second opcode byte. Table B-25 shows the encoding of this gg field.
Table B-25. Encoding of Granularity of Data Field (gg)
gg
Granularity of Data
00
Packed Bytes
01
Packed Words
10
Packed Doublewords
11
Quadword
Vol. 2D B-47
INSTRUCTION FORMATS AND ENCODINGS
Table B-26. Formats and Encodings of SSE2 Floating-Point Instructions
Instruction and Format
Encoding
ADDPD—Add Packed Double Precision Floating-Point Values
xmmreg2 to xmmreg1
0110 0110:0000 1111:0101 1000:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0101 1000: mod xmmreg r/m
ADDSD—Add Scalar Double Precision Floating-Point Values
xmmreg2 to xmmreg1
1111 0010:0000 1111:0101 1000:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0010:0000 1111:0101 1000: mod xmmreg r/m
ANDNPD—Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values
xmmreg2 to xmmreg1
0110 0110:0000 1111:0101 0101:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0101 0101: mod xmmreg r/m
ANDPD—Bitwise Logical AND of Packed Double Precision Floating-Point Values
xmmreg2 to xmmreg1
0110 0110:0000 1111:0101 0100:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0101 0100: mod xmmreg r/m
CMPPD—Compare Packed Double Precision Floating-Point Values
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:1100 0010:11 xmmreg1 xmmreg2: imm8
mem to xmmreg, imm8
0110 0110:0000 1111:1100 0010: mod xmmreg r/m: imm8
CMPSD—Compare Scalar Double Precision Floating-Point Values
xmmreg2 to xmmreg1, imm8
1111 0010:0000 1111:1100 0010:11 xmmreg1 xmmreg2: imm8
mem to xmmreg, imm8
11110 010:0000 1111:1100 0010: mod xmmreg r/m: imm8
COMISD—Compare Scalar Ordered Double Precision Floating-Point Values and Set EFLAGS
xmmreg2 to xmmreg1
0110 0110:0000 1111:0010 1111:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0010 1111: mod xmmreg r/m
CVTPI2PD—Convert Packed Doubleword Integers to Packed Double Precision Floating-Point Values
mmreg to xmmreg
0110 0110:0000 1111:0010 1010:11 xmmreg1 mmreg1
mem to xmmreg
0110 0110:0000 1111:0010 1010: mod xmmreg r/m
CVTPD2PI—Convert Packed Double Precision Floating-Point Values to Packed Doubleword Integers
xmmreg to mmreg
0110 0110:0000 1111:0010 1101:11 mmreg1 xmmreg1
mem to mmreg
0110 0110:0000 1111:0010 1101: mod mmreg r/m
CVTSI2SD—Convert Doubleword Integer to Scalar Double Precision Floating-Point Value
r32 to xmmreg1
1111 0010:0000 1111:0010 1010:11 xmmreg r32
mem to xmmreg
1111 0010:0000 1111:0010 1010: mod xmmreg r/m
CVTSD2SI—Convert Scalar Double Precision Floating-Point Value to Doubleword Integer
xmmreg to r32
1111 0010:0000 1111:0010 1101:11 r32 xmmreg
mem to r32
1111 0010:0000 1111:0010 1101: mod r32 r/m
CVTTPD2PI—Convert with Truncation Packed Double Precision Floating-Point Values to Packed Doubleword Integers
xmmreg to mmreg
0110 0110:0000 1111:0010 1100:11 mmreg xmmreg
mem to mmreg
0110 0110:0000 1111:0010 1100: mod mmreg r/m
CVTTSD2SI—Convert with Truncation Scalar Double Precision Floating-Point Value to Doubleword Integer
xmmreg to r32
1111 0010:0000 1111:0010 1100:11 r32 xmmreg
B-48
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-26. Formats and Encodings of SSE2 Floating-Point Instructions (Contd.)
Instruction and Format
Encoding
mem to r32
1111 0010:0000 1111:0010 1100: mod r32 r/m
CVTPD2PS—Covert Packed Double Precision Floating-Point Values to Packed Single Precision Floating-Point Values
xmmreg2 to xmmreg1
0110 0110:0000 1111:0101 1010:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0101 1010: mod xmmreg r/m
CVTPS2PD—Covert Packed Single Precision Floating-Point Values to Packed Double Precision Floating-Point Values
xmmreg2 to xmmreg1
0000 1111:0101 1010:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0101 1010: mod xmmreg r/m
CVTSD2SS—Covert Scalar Double Precision Floating-Point Value to Scalar Single Precision Floating-Point Value
xmmreg2 to xmmreg1
1111 0010:0000 1111:0101 1010:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0010:0000 1111:0101 1010: mod xmmreg r/m
CVTSS2SD—Covert Scalar Single Precision Floating-Point Value to Scalar Double Precision Floating-Point Value
xmmreg2 to xmmreg1
1111 0011:0000 1111:0101 1010:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0011:00001 111:0101 1010: mod xmmreg r/m
CVTPD2DQ—Convert Packed Double Precision Floating-Point Values to Packed Doubleword Integers
xmmreg2 to xmmreg1
1111 0010:0000 1111:1110 0110:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0010:0000 1111:1110 0110: mod xmmreg r/m
CVTTPD2DQ—Convert With Truncation Packed Double Precision Floating-Point Values to Packed Doubleword Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:1110 0110:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:1110 0110: mod xmmreg r/m
CVTDQ2PD—Convert Packed Doubleword Integers to Packed Single Precision Floating-Point Values
xmmreg2 to xmmreg1
1111 0011:0000 1111:1110 0110:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0011:0000 1111:1110 0110: mod xmmreg r/m
CVTPS2DQ—Convert Packed Single Precision Floating-Point Values to Packed Doubleword Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:0101 1011:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0101 1011: mod xmmreg r/m
CVTTPS2DQ—Convert With Truncation Packed Single Precision Floating-Point Values to Packed Doubleword Integers
xmmreg2 to xmmreg1
1111 0011:0000 1111:0101 1011:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0011:0000 1111:0101 1011: mod xmmreg r/m
CVTDQ2PS—Convert Packed Doubleword Integers to Packed Double Precision Floating-Point Values
xmmreg2 to xmmreg1
0000 1111:0101 1011:11 xmmreg1 xmmreg2
mem to xmmreg
0000 1111:0101 1011: mod xmmreg r/m
DIVPD—Divide Packed Double Precision Floating-Point Values
xmmreg2 to xmmreg1
0110 0110:0000 1111:0101 1110:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0101 1110: mod xmmreg r/m
DIVSD—Divide Scalar Double Precision Floating-Point Values
xmmreg2 to xmmreg1
1111 0010:0000 1111:0101 1110:11 xmmreg1 xmmreg2
Vol. 2D
B-49
INSTRUCTION FORMATS AND ENCODINGS
Table B-26. Formats and Encodings of SSE2 Floating-Point Instructions (Contd.)
Instruction and Format
Encoding
mem to xmmreg
1111 0010:0000 1111:0101 1110: mod xmmreg r/m
MAXPD—Return Maximum Packed Double Precision Floating-Point Values
xmmreg2 to xmmreg1
0110 0110:0000 1111:0101 1111:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0101 1111: mod xmmreg r/m
MAXSD—Return Maximum Scalar Double Precision Floating-Point Value
xmmreg2 to xmmreg1
1111 0010:0000 1111:0101 1111:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0010:0000 1111:0101 1111: mod xmmreg r/m
MINPD—Return Minimum Packed Double Precision Floating-Point Values
xmmreg2 to xmmreg1
0110 0110:0000 1111:0101 1101:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0101 1101: mod xmmreg r/m
MINSD—Return Minimum Scalar Double Precision Floating-Point Value
xmmreg2 to xmmreg1
1111 0010:0000 1111:0101 1101:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0010:0000 1111:0101 1101: mod xmmreg r/m
MOVAPD—Move Aligned Packed Double Precision Floating-Point Values
xmmreg1 to xmmreg2
0110 0110:0000 1111:0010 1001:11 xmmreg2 xmmreg1
xmmreg1 to mem
0110 0110:0000 1111:0010 1001: mod xmmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:0010 1000:11 xmmreg1 xmmreg2
mem to xmmreg1
0110 0110:0000 1111:0010 1000: mod xmmreg r/m
MOVHPD—Move High Packed Double Precision Floating-Point Values
xmmreg to mem
0110 0110:0000 1111:0001 0111: mod xmmreg r/m
mem to xmmreg
0110 0110:0000 1111:0001 0110: mod xmmreg r/m
MOVLPD—Move Low Packed Double Precision Floating-Point Values
xmmreg to mem
0110 0110:0000 1111:0001 0011: mod xmmreg r/m
mem to xmmreg
0110 0110:0000 1111:0001 0010: mod xmmreg r/m
MOVMSKPD—Extract Packed Double Precision Floating-Point Sign Mask
xmmreg to r32
0110 0110:0000 1111:0101 0000:11 r32 xmmreg
MOVSD—Move Scalar Double Precision Floating-Point Values
xmmreg1 to xmmreg2
1111 0010:0000 1111:0001 0001:11 xmmreg2 xmmreg1
xmmreg1 to mem
1111 0010:0000 1111:0001 0001: mod xmmreg r/m
xmmreg2 to xmmreg1
1111 0010:0000 1111:0001 0000:11 xmmreg1 xmmreg2
mem to xmmreg1
1111 0010:0000 1111:0001 0000: mod xmmreg r/m
MOVUPD—Move Unaligned Packed Double Precision Floating-Point Values
xmmreg2 to xmmreg1
0110 0110:0000 1111:0001 0001:11 xmmreg2 xmmreg1
mem to xmmreg1
0110 0110:0000 1111:0001 0001: mod xmmreg r/m
xmmreg1 to xmmreg2
0110 0110:0000 1111:0001 0000:11 xmmreg1 xmmreg2
xmmreg1 to mem
0110 0110:0000 1111:0001 0000: mod xmmreg r/m
MULPD—Multiply Packed Double Precision Floating-Point Values
xmmreg2 to xmmreg1
0110 0110:0000 1111:0101 1001:11 xmmreg1 xmmreg2
B-50
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-26. Formats and Encodings of SSE2 Floating-Point Instructions (Contd.)
Instruction and Format
Encoding
mem to xmmreg
0110 0110:0000 1111:0101 1001: mod xmmreg r/m
MULSD—Multiply Scalar Double Precision Floating-Point Values
xmmreg2 to xmmreg1
1111 0010:00001111:01011001:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0010:00001111:01011001: mod xmmreg r/m
ORPD—Bitwise Logical OR of Double Precision Floating-Point Values
xmmreg2 to xmmreg1
0110 0110:0000 1111:0101 0110:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0101 0110: mod xmmreg r/m
SHUFPD—Shuffle Packed Double Precision Floating-Point Values
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:1100 0110:11 xmmreg1 xmmreg2: imm8
mem to xmmreg, imm8
0110 0110:0000 1111:1100 0110: mod xmmreg r/m: imm8
SQRTPD—Compute Square Roots of Packed Double Precision Floating-Point Values
xmmreg2 to xmmreg1
0110 0110:0000 1111:0101 0001:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0101 0001: mod xmmreg r/m
SQRTSD—Compute Square Root of Scalar Double Precision Floating-Point Value
xmmreg2 to xmmreg1
1111 0010:0000 1111:0101 0001:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0010:0000 1111:0101 0001: mod xmmreg r/m
SUBPD—Subtract Packed Double Precision Floating-Point Values
xmmreg2 to xmmreg1
0110 0110:0000 1111:0101 1100:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0101 1100: mod xmmreg r/m
SUBSD—Subtract Scalar Double Precision Floating-Point Values
xmmreg2 to xmmreg1
1111 0010:0000 1111:0101 1100:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0010:0000 1111:0101 1100: mod xmmreg r/m
UCOMISD—Unordered Compare Scalar Ordered Double Precision Floating-Point Values and Set EFLAGS
xmmreg2 to xmmreg1
0110 0110:0000 1111:0010 1110:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0010 1110: mod xmmreg r/m
UNPCKHPD—Unpack and Interleave High Packed Double Precision Floating-Point Values
xmmreg2 to xmmreg1
0110 0110:0000 1111:0001 0101:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0001 0101: mod xmmreg r/m
UNPCKLPD—Unpack and Interleave Low Packed Double Precision Floating-Point Values
xmmreg2 to xmmreg1
0110 0110:0000 1111:0001 0100:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0001 0100: mod xmmreg r/m
XORPD—Bitwise Logical OR of Double Precision Floating-Point Values
xmmreg2 to xmmreg1
0110 0110:0000 1111:0101 0111:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0101 0111: mod xmmreg r/m
Vol. 2D B-51
INSTRUCTION FORMATS AND ENCODINGS
Table B-27. Formats and Encodings of SSE2 Integer Instructions
Instruction and Format
Encoding
MOVD—Move Doubleword
reg to xmmreg
0110 0110:0000 1111:0110 1110: 11 xmmreg reg
reg from xmmreg
0110 0110:0000 1111:0111 1110: 11 xmmreg reg
mem to xmmreg
0110 0110:0000 1111:0110 1110: mod xmmreg r/m
mem from xmmreg
0110 0110:0000 1111:0111 1110: mod xmmreg r/m
MOVDQA—Move Aligned Double Quadword
xmmreg2 to xmmreg1
0110 0110:0000 1111:0110 1111:11 xmmreg1 xmmreg2
xmmreg2 from xmmreg1
0110 0110:0000 1111:0111 1111:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0110 1111: mod xmmreg r/m
mem from xmmreg
0110 0110:0000 1111:0111 1111: mod xmmreg r/m
MOVDQU—Move Unaligned Double Quadword
xmmreg2 to xmmreg1
1111 0011:0000 1111:0110 1111:11 xmmreg1 xmmreg2
xmmreg2 from xmmreg1
1111 0011:0000 1111:0111 1111:11 xmmreg1 xmmreg2
mem to xmmreg
1111 0011:0000 1111:0110 1111: mod xmmreg r/m
mem from xmmreg
1111 0011:0000 1111:0111 1111: mod xmmreg r/m
MOVQ2DQ—Move Quadword from MMX to XMM Register
mmreg to xmmreg
1111 0011:0000 1111:1101 0110:11 mmreg1 mmreg2
MOVDQ2Q—Move Quadword from XMM to MMX Register
xmmreg to mmreg
1111 0010:0000 1111:1101 0110:11 mmreg1 mmreg2
MOVQ—Move Quadword
xmmreg2 to xmmreg1
1111 0011:0000 1111:0111 1110: 11 xmmreg1 xmmreg2
xmmreg2 from xmmreg1
0110 0110:0000 1111:1101 0110: 11 xmmreg1 xmmreg2
mem to xmmreg
1111 0011:0000 1111:0111 1110: mod xmmreg r/m
mem from xmmreg
0110 0110:0000 1111:1101 0110: mod xmmreg r/m
PACKSSDW1—Pack Dword To Word Data (signed with saturation)
xmmreg2 to xmmreg1
0110 0110:0000 1111:0110 1011: 11 xmmreg1 xmmreg2
memory to xmmreg
0110 0110:0000 1111:0110 1011: mod xmmreg r/m
PACKSSWB—Pack Word To Byte Data (signed with saturation)
xmmreg2 to xmmreg1
0110 0110:0000 1111:0110 0011: 11 xmmreg1 xmmreg2
memory to xmmreg
0110 0110:0000 1111:0110 0011: mod xmmreg r/m
PACKUSWB—Pack Word To Byte Data (unsigned with saturation)
xmmreg2 to xmmreg1
0110 0110:0000 1111:0110 0111: 11 xmmreg1 xmmreg2
memory to xmmreg
0110 0110:0000 1111:0110 0111: mod xmmreg r/m
PADDQ—Add Packed Quadword Integers
mmreg2 to mmreg1
0000 1111:1101 0100:11 mmreg1 mmreg2
mem to mmreg
0000 1111:1101 0100: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:1101 0100:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:1101 0100: mod xmmreg r/m
B-52
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-27. Formats and Encodings of SSE2 Integer Instructions (Contd.)
Instruction and Format
Encoding
PADD—Add With Wrap-around
xmmreg2 to xmmreg1
0110 0110:0000 1111: 1111 11gg: 11 xmmreg1 xmmreg2
memory to xmmreg
0110 0110:0000 1111: 1111 11gg: mod xmmreg r/m
PADDS—Add Signed With Saturation
xmmreg2 to xmmreg1
0110 0110:0000 1111: 1110 11gg: 11 xmmreg1 xmmreg2
memory to xmmreg
0110 0110:0000 1111: 1110 11gg: mod xmmreg r/m
PADDUS—Add Unsigned With Saturation
xmmreg2 to xmmreg1
0110 0110:0000 1111: 1101 11gg: 11 xmmreg1 xmmreg2
memory to xmmreg
0110 0110:0000 1111: 1101 11gg: mod xmmreg r/m
PAND—Bitwise And
xmmreg2 to xmmreg1
0110 0110:0000 1111:1101 1011: 11 xmmreg1 xmmreg2
memory to xmmreg
0110 0110:0000 1111:1101 1011: mod xmmreg r/m
PANDN—Bitwise AndNot
xmmreg2 to xmmreg1
0110 0110:0000 1111:1101 1111: 11 xmmreg1 xmmreg2
memory to xmmreg
0110 0110:0000 1111:1101 1111: mod xmmreg r/m
PAVGB—Average Packed Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:11100 000:11 xmmreg1 xmmreg2
mem to xmmreg
01100110:00001111:11100000 mod xmmreg r/m
PAVGW—Average Packed Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:1110 0011:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:1110 0011 mod xmmreg r/m
PCMPEQ—Packed Compare For Equality
xmmreg1 with xmmreg2
0110 0110:0000 1111:0111 01gg: 11 xmmreg1 xmmreg2
xmmreg with memory
0110 0110:0000 1111:0111 01gg: mod xmmreg r/m
PCMPGT—Packed Compare Greater (signed)
xmmreg1 with xmmreg2
0110 0110:0000 1111:0110 01gg: 11 xmmreg1 xmmreg2
xmmreg with memory
0110 0110:0000 1111:0110 01gg: mod xmmreg r/m
PEXTRW—Extract Word
xmmreg to reg32, imm8
0110 0110:0000 1111:1100 0101:11 r32 xmmreg: imm8
PINSRW—Insert Word
reg32 to xmmreg, imm8
0110 0110:0000 1111:1100 0100:11 xmmreg r32: imm8
m16 to xmmreg, imm8
0110 0110:0000 1111:1100 0100: mod xmmreg r/m: imm8
PMADDWD—Packed Multiply Add
xmmreg2 to xmmreg1
0110 0110:0000 1111:1111 0101: 11 xmmreg1 xmmreg2
memory to xmmreg
0110 0110:0000 1111:1111 0101: mod xmmreg r/m
PMAXSW—Maximum of Packed Signed Word Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:1110 1110:11 xmmreg1 xmmreg2
mem to xmmreg
01100110:00001111:11101110: mod xmmreg r/m
Vol. 2D B-53
INSTRUCTION FORMATS AND ENCODINGS
Table B-27. Formats and Encodings of SSE2 Integer Instructions (Contd.)
Instruction and Format
Encoding
PMAXUB—Maximum of Packed Unsigned Byte Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:1101 1110:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:1101 1110: mod xmmreg r/m
PMINSW—Minimum of Packed Signed Word Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:1110 1010:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:1110 1010: mod xmmreg r/m
PMINUB—Minimum of Packed Unsigned Byte Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:1101 1010:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:1101 1010 mod xmmreg r/m
PMOVMSKB—Move Byte Mask To Integer
xmmreg to reg32
0110 0110:0000 1111:1101 0111:11 r32 xmmreg
PMULHUW—Packed multiplication, store high word (unsigned)
xmmreg2 to xmmreg1
0110 0110:0000 1111:1110 0100: 11 xmmreg1 xmmreg2
memory to xmmreg
0110 0110:0000 1111:1110 0100: mod xmmreg r/m
PMULHW—Packed Multiplication, store high word
xmmreg2 to xmmreg1
0110 0110:0000 1111:1110 0101: 11 xmmreg1 xmmreg2
memory to xmmreg
0110 0110:0000 1111:1110 0101: mod xmmreg r/m
PMULLW—Packed Multiplication, store low word
xmmreg2 to xmmreg1
0110 0110:0000 1111:1101 0101: 11 xmmreg1 xmmreg2
memory to xmmreg
0110 0110:0000 1111:1101 0101: mod xmmreg r/m
PMULUDQ—Multiply Packed Unsigned Doubleword Integers
mmreg2 to mmreg1
0000 1111:1111 0100:11 mmreg1 mmreg2
mem to mmreg
0000 1111:1111 0100: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:00001111:1111 0100:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:00001111:1111 0100: mod xmmreg r/m
POR—Bitwise Or
xmmreg2 to xmmreg1
0110 0110:0000 1111:1110 1011: 11 xmmreg1 xmmreg2
memory to xmmreg
0110 0110:0000 1111:1110 1011: mod xmmreg r/m
PSADBW—Compute Sum of Absolute Differences
xmmreg2 to xmmreg1
0110 0110:0000 1111:1111 0110:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:1111 0110: mod xmmreg r/m
PSHUFLW—Shuffle Packed Low Words
xmmreg2 to xmmreg1, imm8
1111 0010:0000 1111:0111 0000:11 xmmreg1 xmmreg2: imm8
mem to xmmreg, imm8
1111 0010:0000 1111:0111 0000:11 mod xmmreg r/m: imm8
PSHUFHW—Shuffle Packed High Words
xmmreg2 to xmmreg1, imm8
1111 0011:0000 1111:0111 0000:11 xmmreg1 xmmreg2: imm8
mem to xmmreg, imm8
1111 0011:0000 1111:0111 0000: mod xmmreg r/m: imm8
PSHUFD—Shuffle Packed Doublewords
B-54
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-27. Formats and Encodings of SSE2 Integer Instructions (Contd.)
Instruction and Format
Encoding
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0111 0000:11 xmmreg1 xmmreg2: imm8
mem to xmmreg, imm8
0110 0110:0000 1111:0111 0000: mod xmmreg r/m: imm8
PSLLDQ—Shift Double Quadword Left Logical
xmmreg, imm8
0110 0110:0000 1111:0111 0011:11 111 xmmreg: imm8
PSLL—Packed Shift Left Logical
xmmreg1 by xmmreg2
0110 0110:0000 1111:1111 00gg: 11 xmmreg1 xmmreg2
xmmreg by memory
0110 0110:0000 1111:1111 00gg: mod xmmreg r/m
xmmreg by immediate
0110 0110:0000 1111:0111 00gg: 11 110 xmmreg: imm8
PSRA—Packed Shift Right Arithmetic
xmmreg1 by xmmreg2
0110 0110:0000 1111:1110 00gg: 11 xmmreg1 xmmreg2
xmmreg by memory
0110 0110:0000 1111:1110 00gg: mod xmmreg r/m
xmmreg by immediate
0110 0110:0000 1111:0111 00gg: 11 100 xmmreg: imm8
PSRLDQ—Shift Double Quadword Right Logical
xmmreg, imm8
0110 0110:00001111:01110011:11 011 xmmreg: imm8
PSRL—Packed Shift Right Logical
xmmreg1 by xmmreg2
0110 0110:0000 1111:1101 00gg: 11 xmmreg1 xmmreg2
xmmreg by memory
0110 0110:0000 1111:1101 00gg: mod xmmreg r/m
xmmreg by immediate
0110 0110:0000 1111:0111 00gg: 11 010 xmmreg: imm8
PSUBQ—Subtract Packed Quadword Integers
mmreg2 to mmreg1
0000 1111:11111 011:11 mmreg1 mmreg2
mem to mmreg
0000 1111:1111 1011: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:1111 1011:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:1111 1011: mod xmmreg r/m
PSUB—Subtract With Wrap-around
xmmreg2 from xmmreg1
0110 0110:0000 1111:1111 10gg: 11 xmmreg1 xmmreg2
memory from xmmreg
0110 0110:0000 1111:1111 10gg: mod xmmreg r/m
PSUBS—Subtract Signed With Saturation
xmmreg2 from xmmreg1
0110 0110:0000 1111:1110 10gg: 11 xmmreg1 xmmreg2
memory from xmmreg
0110 0110:0000 1111:1110 10gg: mod xmmreg r/m
PSUBUS—Subtract Unsigned With Saturation
xmmreg2 from xmmreg1
0000 1111:1101 10gg: 11 xmmreg1 xmmreg2
memory from xmmreg
0000 1111:1101 10gg: mod xmmreg r/m
PUNPCKH—Unpack High Data To Next Larger Type
xmmreg2 to xmmreg1
0110 0110:0000 1111:0110 10gg:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0110 10gg: mod xmmreg r/m
PUNPCKHQDQ—Unpack High Data
xmmreg2 to xmmreg1
0110 0110:0000 1111:0110 1101:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0110 1101: mod xmmreg r/m
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INSTRUCTION FORMATS AND ENCODINGS
Table B-27. Formats and Encodings of SSE2 Integer Instructions (Contd.)
Instruction and Format
Encoding
PUNPCKL—Unpack Low Data To Next Larger Type
xmmreg2 to xmmreg1
0110 0110:0000 1111:0110 00gg:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0110 00gg: mod xmmreg r/m
PUNPCKLQDQ—Unpack Low Data
xmmreg2 to xmmreg1
0110 0110:0000 1111:0110 1100:11 xmmreg1 xmmreg2
mem to xmmreg
0110 0110:0000 1111:0110 1100: mod xmmreg r/m
PXOR—Bitwise Xor
xmmreg2 to xmmreg1
0110 0110:0000 1111:1110 1111: 11 xmmreg1 xmmreg2
memory to xmmreg
0110 0110:0000 1111:1110 1111: mod xmmreg r/m
Table B-28. Format and Encoding of SSE2 Cacheability Instructions
Instruction and Format
Encoding
MASKMOVDQU—Store Selected Bytes of Double Quadword
xmmreg2 to xmmreg1
0110 0110:0000 1111:1111 0111:11 xmmreg1 xmmreg2
CLFLUSH—Flush Cache Line
mem
0000 1111:1010 1110: mod 111 r/m
MOVNTPD—Store Packed Double Precision Floating-Point Values Using Non-Temporal Hint
xmmreg to mem
0110 0110:0000 1111:0010 1011: mod xmmreg r/m
MOVNTDQ—Store Double Quadword Using Non-Temporal Hint
xmmreg to mem
0110 0110:0000 1111:1110 0111: mod xmmreg r/m
MOVNTI—Store Doubleword Using Non-Temporal Hint
reg to mem
0000 1111:1100 0011: mod reg r/m
PAUSE—Spin Loop Hint
1111 0011:1001 0000
LFENCE—Load Fence
0000 1111:1010 1110: 11 101 000
MFENCE—Memory Fence
0000 1111:1010 1110: 11 110 000
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B.10 SSE3 FORMATS AND ENCODINGS TABLE
The tables in this section provide SSE3 formats and encodings. Some SSE3 instructions require a mandatory prefix
(66H, F2H, F3H) as part of the two-byte opcode. These prefixes are included in the tables.
When in IA-32e mode, use of the REX.R prefix permits instructions that use general purpose and XMM registers to
access additional registers. Some instructions require the REX.W prefix to promote the instruction to 64-bit opera-
tion. Instructions that require the REX.W prefix are listed (with their opcodes) in Section B.13.
Table B-29. Formats and Encodings of SSE3 Floating-Point Instructions
Instruction and Format
Encoding
ADDSUBPD—Add /Sub packed DP FP numbers from XMM2/Mem to XMM1
xmmreg2 to xmmreg1
01100110:00001111:11010000:11 xmmreg1 xmmreg2
mem to xmmreg
01100110:00001111:11010000: mod xmmreg r/m
ADDSUBPS—Add /Sub packed SP FP numbers from XMM2/Mem to XMM1
xmmreg2 to xmmreg1
11110010:00001111:11010000:11 xmmreg1 xmmreg2
mem to xmmreg
11110010:00001111:11010000: mod xmmreg r/m
HADDPD—Add horizontally packed DP FP numbers XMM2/Mem to XMM1
xmmreg2 to xmmreg1
01100110:00001111:01111100:11 xmmreg1 xmmreg2
mem to xmmreg
01100110:00001111:01111100: mod xmmreg r/m
HADDPS—Add horizontally packed SP FP numbers XMM2/Mem to XMM1
xmmreg2 to xmmreg1
11110010:00001111:01111100:11 xmmreg1 xmmreg2
mem to xmmreg
11110010:00001111:01111100: mod xmmreg r/m
HSUBPD—Sub horizontally packed DP FP numbers XMM2/Mem to XMM1
xmmreg2 to xmmreg1
01100110:00001111:01111101:11 xmmreg1 xmmreg2
mem to xmmreg
01100110:00001111:01111101: mod xmmreg r/m
HSUBPS—Sub horizontally packed SP FP numbers XMM2/Mem to XMM1
xmmreg2 to xmmreg1
11110010:00001111:01111101:11 xmmreg1 xmmreg2
mem to xmmreg
11110010:00001111:01111101: mod xmmreg r/m
Table B-30. Formats and Encodings for SSE3 Event Management Instructions
Instruction and Format
Encoding
MONITOR—Set up a linear address range to be monitored by hardware
eax, ecx, edx
0000 1111 : 0000 0001:11 001 000
MWAIT—Wait until write-back store performed within the range specified by the instruction MONITOR
eax, ecx
0000 1111 : 0000 0001:11 001 001
Table B-31. Formats and Encodings for SSE3 Integer and Move Instructions
Instruction and Format
Encoding
FISTTP—Store ST in int16 (chop) and pop
m16int
11011 111 : modA 001 r/m
FISTTP—Store ST in int32 (chop) and pop
m32int
11011 011 : modA 001 r/m
FISTTP—Store ST in int64 (chop) and pop
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Table B-31. Formats and Encodings for SSE3 Integer and Move Instructions (Contd.)
Instruction and Format
Encoding
m64int
11011 101 : modA 001 r/m
LDDQU—Load unaligned integer 128-bit
xmm, m128
11110010:00001111:11110000: modA xmmreg r/m
MOVDDUP—Move 64 bits representing one DP data from XMM2/Mem to XMM1 and duplicate
xmmreg2 to xmmreg1
11110010:00001111:00010010:11 xmmreg1 xmmreg2
mem to xmmreg
11110010:00001111:00010010: mod xmmreg r/m
MOVSHDUP—Move 128 bits representing 4 SP data from XMM2/Mem to XMM1 and duplicate high
xmmreg2 to xmmreg1
11110011:00001111:00010110:11 xmmreg1 xmmreg2
mem to xmmreg
11110011:00001111:00010110: mod xmmreg r/m
MOVSLDUP—Move 128 bits representing 4 SP data from XMM2/Mem to XMM1 and duplicate low
xmmreg2 to xmmreg1
11110011:00001111:00010010:11 xmmreg1 xmmreg2
mem to xmmreg
11110011:00001111:00010010: mod xmmreg r/m
B.11 SSSE3 FORMATS AND ENCODING TABLE
The tables in this section provide SSSE3 formats and encodings. Some SSSE3 instructions require a mandatory
prefix (66H) as part of the three-byte opcode. These prefixes are included in the table below.
Table B-32. Formats and Encodings for SSSE3 Instructions
Instruction and Format
Encoding
PABSB—Packed Absolute Value Bytes
mmreg2 to mmreg1
0000 1111:0011 1000: 0001 1100:11 mmreg1 mmreg2
mem to mmreg
0000 1111:0011 1000: 0001 1100: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0001 1100:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0001 1100: mod xmmreg r/m
PABSD—Packed Absolute Value Double Words
mmreg2 to mmreg1
0000 1111:0011 1000: 0001 1110:11 mmreg1 mmreg2
mem to mmreg
0000 1111:0011 1000: 0001 1110: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0001 1110:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0001 1110: mod xmmreg r/m
PABSW—Packed Absolute Value Words
mmreg2 to mmreg1
0000 1111:0011 1000: 0001 1101:11 mmreg1 mmreg2
mem to mmreg
0000 1111:0011 1000: 0001 1101: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0001 1101:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0001 1101: mod xmmreg r/m
PALIGNR—Packed Align Right
mmreg2 to mmreg1, imm8
0000 1111:0011 1010: 0000 1111:11 mmreg1 mmreg2: imm8
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Table B-32. Formats and Encodings for SSSE3 Instructions (Contd.)
Instruction and Format
Encoding
mem to mmreg, imm8
0000 1111:0011 1010: 0000 1111: mod mmreg r/m: imm8
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010: 0000 1111:11 xmmreg1
xmmreg2: imm8
mem to xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0000 1111: mod xmmreg r/m:
imm8
PHADDD—Packed Horizontal Add Double Words
mmreg2 to mmreg1
0000 1111:0011 1000: 0000 0010:11 mmreg1 mmreg2
mem to mmreg
0000 1111:0011 1000: 0000 0010: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0000 0010:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0000 0010: mod xmmreg r/m
PHADDSW—Packed Horizontal Add and Saturate
mmreg2 to mmreg1
0000 1111:0011 1000: 0000 0011:11 mmreg1 mmreg2
mem to mmreg
0000 1111:0011 1000: 0000 0011: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0000 0011:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0000 0011: mod xmmreg r/m
PHADDW—Packed Horizontal Add Words
mmreg2 to mmreg1
0000 1111:0011 1000: 0000 0001:11 mmreg1 mmreg2
mem to mmreg
0000 1111:0011 1000: 0000 0001: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0000 0001:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0000 0001: mod xmmreg r/m
PHSUBD—Packed Horizontal Subtract Double Words
mmreg2 to mmreg1
0000 1111:0011 1000: 0000 0110:11 mmreg1 mmreg2
mem to mmreg
0000 1111:0011 1000: 0000 0110: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0000 0110:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0000 0110: mod xmmreg r/m
PHSUBSW—Packed Horizontal Subtract and Saturate
mmreg2 to mmreg1
0000 1111:0011 1000: 0000 0111:11 mmreg1 mmreg2
mem to mmreg
0000 1111:0011 1000: 0000 0111: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0000 0111:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0000 0111: mod xmmreg r/m
PHSUBW—Packed Horizontal Subtract Words
mmreg2 to mmreg1
0000 1111:0011 1000: 0000 0101:11 mmreg1 mmreg2
mem to mmreg
0000 1111:0011 1000: 0000 0101: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0000 0101:11 xmmreg1
xmmreg2
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INSTRUCTION FORMATS AND ENCODINGS
Table B-32. Formats and Encodings for SSSE3 Instructions (Contd.)
Instruction and Format
Encoding
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0000 0101: mod xmmreg r/m
PMADDUBSW—Multiply and Add Packed Signed and Unsigned Bytes
mmreg2 to mmreg1
0000 1111:0011 1000: 0000 0100:11 mmreg1 mmreg2
mem to mmreg
0000 1111:0011 1000: 0000 0100: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0000 0100:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0000 0100: mod xmmreg r/m
PMULHRSW—Packed Multiply HIgn with Round and Scale
mmreg2 to mmreg1
0000 1111:0011 1000: 0000 1011:11 mmreg1 mmreg2
mem to mmreg
0000 1111:0011 1000: 0000 1011: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0000 1011:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0000 1011: mod xmmreg r/m
PSHUFB—Packed Shuffle Bytes
mmreg2 to mmreg1
0000 1111:0011 1000: 0000 0000:11 mmreg1 mmreg2
mem to mmreg
0000 1111:0011 1000: 0000 0000: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0000 0000:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0000 0000: mod xmmreg r/m
PSIGNB—Packed Sign Bytes
mmreg2 to mmreg1
0000 1111:0011 1000: 0000 1000:11 mmreg1 mmreg2
mem to mmreg
0000 1111:0011 1000: 0000 1000: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0000 1000:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0000 1000: mod xmmreg r/m
PSIGND—Packed Sign Double Words
mmreg2 to mmreg1
0000 1111:0011 1000: 0000 1010:11 mmreg1 mmreg2
mem to mmreg
0000 1111:0011 1000: 0000 1010: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0000 1010:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0000 1010: mod xmmreg r/m
PSIGNW—Packed Sign Words
mmreg2 to mmreg1
0000 1111:0011 1000: 0000 1001:11 mmreg1 mmreg2
mem to mmreg
0000 1111:0011 1000: 0000 1001: mod mmreg r/m
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0000 1001:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0000 1001: mod xmmreg r/m
B.12 AESNI AND PCLMULQDQ INSTRUCTION FORMATS AND ENCODINGS
Table B-33 shows the formats and encodings for AESNI and PCLMULQDQ instructions.
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Table B-33. Formats and Encodings of AESNI and PCLMULQDQ Instructions
Instruction and Format
Encoding
AESDEC—Perform One Round of an AES Decryption Flow
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000:1101 1110:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000:1101 1110: mod xmmreg r/m
AESDECLAST—Perform Last Round of an AES Decryption Flow
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000:1101 1111:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000:1101 1111: mod xmmreg r/m
AESENC—Perform One Round of an AES Encryption Flow
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000:1101 1100:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000:1101 1100: mod xmmreg r/m
AESENCLAST—Perform Last Round of an AES Encryption Flow
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000:1101 1101:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000:1101 1101: mod xmmreg r/m
AESIMC—Perform the AES InvMixColumn Transformation
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000:1101 1011:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000:1101 1011: mod xmmreg r/m
AESKEYGENASSIST—AES Round Key Generation Assist
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010:1101 1111:11 xmmreg1
xmmreg2: imm8
mem to xmmreg, imm8
0110 0110:0000 1111:0011 1010:1101 1111: mod xmmreg r/m:
imm8
PCLMULQDQ—Carry-Less Multiplication Quadword
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010:0100 0100:11 xmmreg1
xmmreg2: imm8
mem to xmmreg, imm8
0110 0110:0000 1111:0011 1010:0100 0100: mod xmmreg r/m:
imm8
B.13 SPECIAL ENCODINGS FOR 64-BIT MODE
The following Pentium, P6, MMX, SSE, SSE2, SSE3 instructions are promoted to 64-bit operation in IA-32e mode
by using REX.W. However, these entries are special cases that do not follow the general rules (specified in Section
B.4).
Table B-34. Special Case Instructions Promoted Using REX.W
Instruction and Format
Encoding
CMOVcc—Conditional Move
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INSTRUCTION FORMATS AND ENCODINGS
Table B-34. Special Case Instructions Promoted Using REX.W (Contd.)
Instruction and Format
Encoding
register2 to register1
0100 0R0B 0000 1111: 0100 tttn : 11 reg1 reg2
qwordregister2 to qwordregister1
0100 1R0B 0000 1111: 0100 tttn : 11 qwordreg1 qwordreg2
memory to register
0100 0RXB 0000 1111 : 0100 tttn : mod reg r/m
memory64 to qwordregister
0100 1RXB 0000 1111 : 0100 tttn : mod qwordreg r/m
CVTSD2SI—Convert Scalar Double Precision Floating-Point Value to Doubleword Integer
xmmreg to r32
0100 0R0B 1111 0010:0000 1111:0010 1101:11 r32
xmmreg
xmmreg to r64
0100 1R0B 1111 0010:0000 1111:0010 1101:11 r64
xmmreg
mem64 to r32
0100 0R0XB 1111 0010:0000 1111:0010 1101: mod r32 r/m
mem64 to r64
0100 1RXB 1111 0010:0000 1111:0010 1101: mod r64 r/m
CVTSI2SS—Convert Doubleword Integer to Scalar Single Precision Floating-Point Value
r32 to xmmreg1
0100 0R0B 1111 0011:0000 1111:0010 1010:11 xmmreg
r32
r64 to xmmreg1
0100 1R0B 1111 0011:0000 1111:0010 1010:11 xmmreg
r64
mem to xmmreg
0100 0RXB 1111 0011:0000 1111:0010 1010: mod xmmreg
r/m
mem64 to xmmreg
0100 1RXB 1111 0011:0000 1111:0010 1010: mod xmmreg
r/m
CVTSI2SD—Convert Doubleword Integer to Scalar Double Precision Floating-Point Value
r32 to xmmreg1
0100 0R0B 1111 0010:0000 1111:0010 1010:11 xmmreg
r32
r64 to xmmreg1
0100 1R0B 1111 0010:0000 1111:0010 1010:11 xmmreg
r64
mem to xmmreg
0100 0RXB 1111 0010:0000 1111:00101 010: mod xmmreg
r/m
mem64 to xmmreg
0100 1RXB 1111 0010:0000 1111:0010 1010: mod xmmreg
r/m
CVTSS2SI—Convert Scalar Single Precision Floating-Point Value to Doubleword Integer
xmmreg to r32
0100 0R0B 1111 0011:0000 1111:0010 1101:11 r32
xmmreg
xmmreg to r64
0100 1R0B 1111 0011:0000 1111:0010 1101:11 r64
xmmreg
mem to r32
0100 0RXB 11110011:00001111:00101101: mod r32 r/m
mem32 to r64
0100 1RXB 1111 0011:0000 1111:0010 1101: mod r64 r/m
CVTTSD2SI—Convert with Truncation Scalar Double Precision Floating-Point Value to Doubleword Integer
xmmreg to r32
0100 0R0B 11110010:00001111:00101100:11 r32 xmmreg
xmmreg to r64
0100 1R0B 1111 0010:0000 1111:0010 1100:11 r64
xmmreg
mem64 to r32
0100 0RXB 1111 0010:0000 1111:0010 1100: mod r32 r/m
mem64 to r64
0100 1RXB 1111 0010:0000 1111:0010 1100: mod r64 r/m
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Table B-34. Special Case Instructions Promoted Using REX.W (Contd.)
Instruction and Format
Encoding
CVTTSS2SI—Convert with Truncation Scalar Single Precision Floating-Point Value to Doubleword Integer
xmmreg to r32
0100 0R0B 1111 0011:0000 1111:0010 1100:11 r32
xmmreg1
xmmreg to r64
0100 1R0B 1111 0011:0000 1111:0010 1100:11 r64
xmmreg1
mem to r32
0100 0RXB 1111 0011:0000 1111:0010 1100: mod r32 r/m
mem32 to r64
0100 1RXB 1111 0011:0000 1111:0010 1100: mod r64 r/m
MOVD/MOVQ—Move doubleword
reg to mmxreg
0100 0R0B 0000 1111:0110 1110: 11 mmxreg reg
qwordreg to mmxreg
0100 1R0B 0000 1111:0110 1110: 11 mmxreg qwordreg
reg from mmxreg
0100 0R0B 0000 1111:0111 1110: 11 mmxreg reg
qwordreg from mmxreg
0100 1R0B 0000 1111:0111 1110: 11 mmxreg qwordreg
mem to mmxreg
0100 0RXB 0000 1111:0110 1110: mod mmxreg r/m
mem64 to mmxreg
0100 1RXB 0000 1111:0110 1110: mod mmxreg r/m
mem from mmxreg
0100 0RXB 0000 1111:0111 1110: mod mmxreg r/m
mem64 from mmxreg
0100 1RXB 0000 1111:0111 1110: mod mmxreg r/m
mmxreg with memory
0100 0RXB 0000 1111:0110 01gg: mod mmxreg r/m
MOVMSKPS—Extract Packed Single Precision Floating-Point Sign Mask
xmmreg to r32
0100 0R0B 0000 1111:0101 0000:11 r32 xmmreg
xmmreg to r64
0100 1R0B 00001111:01010000:11 r64 xmmreg
PEXTRW—Extract Word
mmreg to reg32, imm8
0100 0R0B 0000 1111:1100 0101:11 r32 mmreg: imm8
mmreg to reg64, imm8
0100 1R0B 0000 1111:1100 0101:11 r64 mmreg: imm8
xmmreg to reg32, imm8
0100 0R0B 0110 0110 0000 1111:1100 0101:11 r32
xmmreg: imm8
xmmreg to reg64, imm8
0100 1R0B 0110 0110 0000 1111:1100 0101:11 r64
xmmreg: imm8
PINSRW—Insert Word
reg32 to mmreg, imm8
0100 0R0B 0000 1111:1100 0100:11 mmreg r32: imm8
reg64 to mmreg, imm8
0100 1R0B 0000 1111:1100 0100:11 mmreg r64: imm8
m16 to mmreg, imm8
0100 0R0B 0000 1111:1100 0100 mod mmreg r/m: imm8
m16 to mmreg, imm8
0100 1RXB 0000 1111:11000100 mod mmreg r/m: imm8
reg32 to xmmreg, imm8
0100 0RXB 0110 0110 0000 1111:1100 0100:11 xmmreg
r32: imm8
reg64 to xmmreg, imm8
0100 0RXB 0110 0110 0000 1111:1100 0100:11 xmmreg
r64: imm8
m16 to xmmreg, imm8
0100 0RXB 0110 0110 0000 1111:1100 0100 mod xmmreg
r/m: imm8
m16 to xmmreg, imm8
0100 1RXB 0110 0110 0000 1111:1100 0100 mod xmmreg
r/m: imm8
PMOVMSKB—Move Byte Mask To Integer
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INSTRUCTION FORMATS AND ENCODINGS
Table B-34. Special Case Instructions Promoted Using REX.W (Contd.)
Instruction and Format
Encoding
mmreg to reg32
0100 0RXB 0000 1111:1101 0111:11 r32 mmreg
mmreg to reg64
0100 1R0B 0000 1111:1101 0111:11 r64 mmreg
xmmreg to reg32
0100 0RXB 0110 0110 0000 1111:1101 0111:11 r32 mmreg
xmmreg to reg64
0110 0110 0000 1111:1101 0111:11 r64 xmmreg
B.14 SSE4.1 FORMATS AND ENCODING TABLE
The tables in this section provide SSE4.1 formats and encodings. Some SSE4.1 instructions require a mandatory
prefix (66H, F2H, F3H) as part of the three-byte opcode. These prefixes are included in the tables.
In 64-bit mode, some instructions requires REX.W, the byte sequence of REX.W prefix in the opcode sequence is
shown.
Table B-35. Encodings of SSE4.1 instructions
Instruction and Format
Encoding
BLENDPD — Blend Packed Double Precision Floats
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1010: 0000 1101:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1010: 0000 1101: mod xmmreg r/m
BLENDPS — Blend Packed Single Precision Floats
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1010: 0000 1100:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1010: 0000 1100: mod xmmreg r/m
BLENDVPD — Variable Blend Packed Double Precision Floats
xmmreg2 to xmmreg1 <xmm0>
0110 0110:0000 1111:0011 1000: 0001 0101:11 xmmreg1
xmmreg2
mem to xmmreg <xmm0>
0110 0110:0000 1111:0011 1000: 0001 0101: mod xmmreg r/m
BLENDVPS — Variable Blend Packed Single Precision Floats
xmmreg2 to xmmreg1 <xmm0>
0110 0110:0000 1111:0011 1000: 0001 0100:11 xmmreg1
xmmreg2
mem to xmmreg <xmm0>
0110 0110:0000 1111:0011 1000: 0001 0100: mod xmmreg r/m
DPPD — Packed Double Precision Dot Products
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010: 0100 0001:11 xmmreg1
xmmreg2: imm8
mem to xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0100 0001: mod xmmreg r/m:
imm8
DPPS — Packed Single Precision Dot Products
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010: 0100 0000:11 xmmreg1
xmmreg2: imm8
mem to xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0100 0000: mod xmmreg r/m:
imm8
EXTRACTPS — Extract From Packed Single Precision Floats
reg from xmmreg , imm8
0110 0110:0000 1111:0011 1010: 0001 0111:11 xmmreg reg:
imm8
B-64
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-35. Encodings of SSE4.1 instructions
Instruction and Format
Encoding
mem from xmmreg , imm8
0110 0110:0000 1111:0011 1010: 0001 0111: mod xmmreg r/m:
imm8
INSERTPS — Insert Into Packed Single Precision Floats
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010: 0010 0001:11 xmmreg1
xmmreg2: imm8
mem to xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0010 0001: mod xmmreg r/m:
imm8
MOVNTDQA — Load Double Quadword Non-temporal Aligned
m128 to xmmreg
0110 0110:0000 1111:0011 1000: 0010 1010:11 r/m xmmreg2
MPSADBW — Multiple Packed Sums of Absolute Difference
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010: 0100 0010:11 xmmreg1
xmmreg2: imm8
mem to xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0100 0010: mod xmmreg r/m:
imm8
PACKUSDW — Pack with Unsigned Saturation
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0010 1011:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0010 1011: mod xmmreg r/m
PBLENDVB — Variable Blend Packed Bytes
xmmreg2 to xmmreg1 <xmm0>
0110 0110:0000 1111:0011 1000: 0001 0000:11 xmmreg1
xmmreg2
mem to xmmreg <xmm0>
0110 0110:0000 1111:0011 1000: 0001 0000: mod xmmreg r/m
PBLENDW — Blend Packed Words
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010: 0001 1110:11 xmmreg1
xmmreg2: imm8
mem to xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0000 1110: mod xmmreg r/m:
imm8
PCMPEQQ — Compare Packed Qword Data of Equal
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0010 1001:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0010 1001: mod xmmreg r/m
PEXTRB — Extract Byte
reg from xmmreg , imm8
0110 0110:0000 1111:0011 1010: 0001 0100:11 xmmreg reg:
imm8
xmmreg to mem, imm8
0110 0110:0000 1111:0011 1010: 0001 0100: mod xmmreg r/m:
imm8
PEXTRD — Extract DWord
reg from xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0001 0110:11 xmmreg reg:
imm8
xmmreg to mem, imm8
0110 0110:0000 1111:0011 1010: 0001 0110: mod
xmmreg r/m: imm8
Vol. 2D B-65
INSTRUCTION FORMATS AND ENCODINGS
Table B-35. Encodings of SSE4.1 instructions
Instruction and Format
Encoding
PEXTRQ — Extract QWord
r64 from xmmreg, imm8
0110 0110:REX.W:0000 1111:0011 1010: 0001 0110:11 xmmreg
reg: imm8
m64 from xmmreg, imm8
0110 0110:REX.W:0000 1111:0011 1010: 0001 0110: mod
xmmreg r/m: imm8
PEXTRW — Extract Word
reg from xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0001 0101:11 reg xmmreg:
imm8
mem from xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0001 0101: mod xmmreg r/m:
imm8
PHMINPOSUW — Packed Horizontal Word Minimum
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0100 0001:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0100 0001: mod xmmreg r/m
PINSRB — Extract Byte
reg to xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0010 0000:11 xmmreg reg:
imm8
mem to xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0010 0000: mod xmmreg r/m:
imm8
PINSRD — Extract DWord
reg to xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0010 0010:11 xmmreg reg:
imm8
mem to xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0010 0010: mod xmmreg r/m:
imm8
PINSRQ — Extract QWord
r64 to xmmreg, imm8
0110 0110:REX.W:0000 1111:0011 1010: 0010 0010:11 xmmreg
reg: imm8
m64 to xmmreg, imm8
0110 0110:REX.W:0000 1111:0011 1010: 0010 0010: mod
xmmreg r/m: imm8
PMAXSB — Maximum of Packed Signed Byte Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0011 1100:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0011 1100: mod xmmreg r/m
PMAXSD — Maximum of Packed Signed Dword Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0011 1101:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0011 1101: mod xmmreg r/m
PMAXUD — Maximum of Packed Unsigned Dword Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0011 1111:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0011 1111: mod xmmreg r/m
PMAXUW — Maximum of Packed Unsigned Word Integers
B-66
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-35. Encodings of SSE4.1 instructions
Instruction and Format
Encoding
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0011 1110:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0011 1110: mod xmmreg r/m
PMINSB — Minimum of Packed Signed Byte Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0011 1000:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0011 1000: mod xmmreg r/m
PMINSD — Minimum of Packed Signed Dword Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0011 1001:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0011 1001: mod xmmreg r/m
PMINUD — Minimum of Packed Unsigned Dword Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0011 1011:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0011 1011: mod xmmreg r/m
PMINUW — Minimum of Packed Unsigned Word Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0011 1010:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0011 1010: mod xmmreg r/m
PMOVSXBD — Packed Move Sign Extend - Byte to Dword
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0010 0001:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0010 0001: mod xmmreg r/m
PMOVSXBQ — Packed Move Sign Extend - Byte to Qword
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0010 0010:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0010 0010: mod xmmreg r/m
PMOVSXBW — Packed Move Sign Extend - Byte to Word
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0010 0000:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0010 0000: mod xmmreg r/m
PMOVSXWD — Packed Move Sign Extend - Word to Dword
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0010 0011:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0010 0011: mod xmmreg r/m
PMOVSXWQ — Packed Move Sign Extend - Word to Qword
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0010 0100:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0010 0100: mod xmmreg r/m
PMOVSXDQ — Packed Move Sign Extend - Dword to Qword
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0010 0101:11 xmmreg1
xmmreg2
Vol. 2D B-67
INSTRUCTION FORMATS AND ENCODINGS
Table B-35. Encodings of SSE4.1 instructions
Instruction and Format
Encoding
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0010 0101: mod xmmreg r/m
PMOVZXBD — Packed Move Zero Extend - Byte to Dword
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0011 0001:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0011 0001: mod xmmreg r/m
PMOVZXBQ — Packed Move Zero Extend - Byte to Qword
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0011 0010:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0011 0010: mod xmmreg r/m
PMOVZXBW — Packed Move Zero Extend - Byte to Word
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0011 0000:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0011 0000: mod xmmreg r/m
PMOVZXWD — Packed Move Zero Extend - Word to Dword
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0011 0011:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0011 0011: mod xmmreg r/m
PMOVZXWQ — Packed Move Zero Extend - Word to Qword
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0011 0100:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0011 0100: mod xmmreg r/m
PMOVZXDQ — Packed Move Zero Extend - Dword to Qword
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0011 0101:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0011 0101: mod xmmreg r/m
PMULDQ — Multiply Packed Signed Dword Integers
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0010 1000:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0010 1000: mod xmmreg r/m
PMULLD — Multiply Packed Signed Dword Integers, Store low Result
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0100 0000:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0100 0000: mod xmmreg r/m
PTEST — Logical Compare
xmmreg2 to xmmreg1
0110 0110:0000 1111:0011 1000: 0001 0111:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0001 0111: mod xmmreg r/m
ROUNDPD — Round Packed Double Precision Values
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010: 0000 1001:11 xmmreg1
xmmreg2: imm8
mem to xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0000 1001: mod xmmreg r/m:
imm8
B-68
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-35. Encodings of SSE4.1 instructions
Instruction and Format
Encoding
ROUNDPS — Round Packed Single Precision Values
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010: 0000 1000:11 xmmreg1
xmmreg2: imm8
mem to xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0000 1000: mod xmmreg r/m:
imm8
ROUNDSD — Round Scalar Double Precision Value
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010: 0000 1011:11 xmmreg1
xmmreg2: imm8
mem to xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0000 1011: mod xmmreg r/m:
imm8
ROUNDSS — Round Scalar Single Precision Value
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010: 0000 1010:11 xmmreg1
xmmreg2: imm8
mem to xmmreg, imm8
0110 0110:0000 1111:0011 1010: 0000 1010: mod xmmreg r/m:
imm8
B.15 SSE4.2 FORMATS AND ENCODING TABLE
The tables in this section provide SSE4.2 formats and encodings. Some SSE4.2 instructions require a mandatory
prefix (66H, F2H, F3H) as part of the three-byte opcode. These prefixes are included in the tables. In 64-bit mode,
some instructions requires REX.W, the byte sequence of REX.W prefix in the opcode sequence is shown.
Table B-36. Encodings of SSE4.2 instructions
Instruction and Format
Encoding
CRC32 — Accumulate CRC32
reg2 to reg1
1111 0010:0000 1111:0011 1000: 1111 000w :11 reg1 reg2
mem to reg
1111 0010:0000 1111:0011 1000: 1111 000w : mod reg r/m
bytereg2 to reg1
1111 0010:0100 WR0B:0000 1111:0011 1000: 1111 0000 :11
reg1 bytereg2
m8 to reg
1111 0010:0100 WR0B:0000 1111:0011 1000: 1111 0000 : mod
reg r/m
qwreg2 to qwreg1
1111 0010:0100 1R0B:0000 1111:0011 1000: 1111 0001 :11
qwreg1 qwreg2
mem64 to qwreg
1111 0010:0100 1R0B:0000 1111:0011 1000: 1111 0001 : mod
qwreg r/m
PCMPESTRI— Packed Compare Explicit-Length Strings To Index
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010: 0110 0001:11 xmmreg1
xmmreg2: imm8
mem to xmmreg
0110 0110:0000 1111:0011 1010: 0110 0001: mod xmmreg r/m
PCMPESTRM— Packed Compare Explicit-Length Strings To Mask
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010: 0110 0000:11 xmmreg1
xmmreg2: imm8
Vol. 2D B-69
INSTRUCTION FORMATS AND ENCODINGS
Table B-36. Encodings of SSE4.2 instructions
Instruction and Format
Encoding
mem to xmmreg
0110 0110:0000 1111:0011 1010: 0110 0000: mod xmmreg r/m
PCMPISTRI— Packed Compare Implicit-Length String To Index
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010: 0110 0011:11 xmmreg1
xmmreg2: imm8
mem to xmmreg
0110 0110:0000 1111:0011 1010: 0110 0011: mod xmmreg r/m
PCMPISTRM— Packed Compare Implicit-Length Strings To Mask
xmmreg2 to xmmreg1, imm8
0110 0110:0000 1111:0011 1010: 0110 0010:11 xmmreg1
xmmreg2: imm8
mem to xmmreg
0110 0110:0000 1111:0011 1010: 0110 0010: mod xmmreg r/m
PCMPGTQ— Packed Compare Greater Than
xmmreg to xmmreg
0110 0110:0000 1111:0011 1000: 0011 0111:11 xmmreg1
xmmreg2
mem to xmmreg
0110 0110:0000 1111:0011 1000: 0011 0111: mod xmmreg r/m
POPCNT— Return Number of Bits Set to 1
reg2 to reg1
1111 0011:0000 1111:1011 1000:11 reg1 reg2
mem to reg1
1111 0011:0000 1111:1011 1000:mod reg1 r/m
qwreg2 to qwreg1
1111 0011:0100 1R0B:0000 1111:1011 1000:11 reg1 reg2
mem64 to qwreg1
1111 0011:0100 1R0B:0000 1111:1011 1000:mod reg1 r/m
B.16 AVX FORMATS AND ENCODING TABLE
The tables in this section provide AVX formats and encodings. A mixed form of bit/hex/symbolic forms are used to
express the various bytes:
The C4/C5 and opcode bytes are expressed in hex notation; the first and second payload byte of VEX, the modR/M
byte is expressed in combination of bit/symbolic form. The first payload byte of C4 is expressed as combination of
bits and hex form, with the hex value preceded by an underscore. The VEX bit field to encode upper register 8-15
uses 1’s complement form, each of those bit field is expressed as lower case notation rxb, instead of RXB.
The hybrid bit-nibble-byte form is depicted below:
hex notation
7 6 ----3 2 1 0
hex notation
7-6
5-3
2-0
C5
R srcreg Lp p
Opcode byte
Mod Reg* R/M
Two-Byte VEX
7 6 5
4 ----- 0
7 6 ----3 2 1 0
hex notation
7-6
5-3
2-0
C4
R X B
0_hex
W srcreg L pp
Opcode byte
Mod Reg R/M
mmmmm
Three-Byte VEX
Figure B-2. Hybrid Notation of VEX-Encoded Key Instruction Bytes
B-70
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-37. Encodings of AVX instructions
Instruction and Format
Encoding
VBLENDPD — Blend Packed Double Precision Floats
xmmreg2 with xmmreg3 into xmmreg1
C4: rxb0_3: w xmmreg2 001:0D:11 xmmreg1 xmmreg3: imm
xmmreg2 with mem to xmmreg1
C4: rxb0_3: w xmmreg2 001:0D:mod xmmreg1 r/m: imm
ymmreg2 with ymmreg3 into ymmreg1
C4: rxb0_3: w ymmreg2 101:0D:11 ymmreg1 ymmreg3: imm
ymmreg2 with mem to ymmreg1
C4: rxb0_3: w ymmreg2 101:0D:mod ymmreg1 r/m: imm
VBLENDPS — Blend Packed Single Precision Floats
xmmreg2 with xmmreg3 into xmmreg1
C4: rxb0_3: w xmmreg2 001:0C:11 xmmreg1 xmmreg3: imm
xmmreg2 with mem to xmmreg1
C4: rxb0_3: w xmmreg2 001:0C:mod xmmreg1 r/m: imm
ymmreg2 with ymmreg3 into ymmreg1
C4: rxb0_3: w ymmreg2 101:0C:11 ymmreg1 ymmreg3: imm
ymmreg2 with mem to ymmreg1
C4: rxb0_3: w ymmreg2 101:0C:mod ymmreg1 r/m: imm
VBLENDVPD — Variable Blend Packed Double Precision Floats
xmmreg2 with xmmreg3 into xmmreg1 using xmmreg4 as
C4: rxb0_3: 0 xmmreg2 001:4B:11 xmmreg1 xmmreg3: xmmreg4
mask
xmmreg2 with mem to xmmreg1 using xmmreg4 as mask
C4: rxb0_3: 0 xmmreg2 001:4B:mod xmmreg1 r/m: xmmreg4
ymmreg2 with ymmreg3 into ymmreg1 using ymmreg4 as
C4: rxb0_3: 0 ymmreg2 101:4B:11 ymmreg1 ymmreg3: ymmreg4
mask
ymmreg2 with mem to ymmreg1 using ymmreg4 as mask
C4: rxb0_3: 0 ymmreg2 101:4B:mod ymmreg1 r/m: ymmreg4
VBLENDVPS — Variable Blend Packed Single Precision Floats
xmmreg2 with xmmreg3 into xmmreg1 using xmmreg4 as
C4: rxb0_3: 0 xmmreg2 001:4A:11 xmmreg1 xmmreg3: xmmreg4
mask
xmmreg2 with mem to xmmreg1 using xmmreg4 as mask
C4: rxb0_3: 0 xmmreg2 001:4A:mod xmmreg1 r/m: xmmreg4
ymmreg2 with ymmreg3 into ymmreg1 using ymmreg4 as
C4: rxb0_3: 0 ymmreg2 101:4A:11 ymmreg1 ymmreg3: ymmreg4
mask
ymmreg2 with mem to ymmreg1 using ymmreg4 as mask
C4: rxb0_3: 0 ymmreg2 101:4A:mod ymmreg1 r/m: ymmreg4
VDPPD — Packed Double Precision Dot Products
xmmreg2 with xmmreg3 into xmmreg1
C4: rxb0_3: w xmmreg2 001:41:11 xmmreg1 xmmreg3: imm
xmmreg2 with mem to xmmreg1
C4: rxb0_3: w xmmreg2 001:41:mod xmmreg1 r/m: imm
VDPPS — Packed Single Precision Dot Products
xmmreg2 with xmmreg3 into xmmreg1
C4: rxb0_3: w xmmreg2 001:40:11 xmmreg1 xmmreg3: imm
xmmreg2 with mem to xmmreg1
C4: rxb0_3: w xmmreg2 001:40:mod xmmreg1 r/m: imm
ymmreg2 with ymmreg3 into ymmreg1
C4: rxb0_3: w ymmreg2 101:40:11 ymmreg1 ymmreg3: imm
ymmreg2 with mem to ymmreg1
C4: rxb0_3: w ymmreg2 101:40:mod ymmreg1 r/m: imm
VEXTRACTPS — Extract From Packed Single Precision Floats
reg from xmmreg1 using imm
C4: rxb0_3: w_F 001:17:11 xmmreg1 reg: imm
mem from xmmreg1 using imm
C4: rxb0_3: w_F 001:17:mod xmmreg1 r/m: imm
VINSERTPS — Insert Into Packed Single Precision Floats
use imm to merge xmmreg3 with xmmreg2 into xmmreg1
C4: rxb0_3: w xmmreg2 001:21:11 xmmreg1 xmmreg3: imm
use imm to merge mem with xmmreg2 into xmmreg1
C4: rxb0_3: w xmmreg2 001:21:mod xmmreg1 r/m: imm
VMOVNTDQA — Load Double Quadword Non-temporal Aligned
m128 to xmmreg1
C4: rxb0_2: w_F 001:2A:11 xmmreg1 r/m
Vol. 2D B-71
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
VMPSADBW — Multiple Packed Sums of Absolute Difference
xmmreg3 with xmmreg2 into xmmreg1
C4: rxb0_3: w xmmreg2 001:42:11 xmmreg1 xmmreg3: imm
m128 with xmmreg2 into xmmreg1
C4: rxb0_3: w xmmreg2 001:42:mod xmmreg1 r/m: imm
VPACKUSDW — Pack with Unsigned Saturation
xmmreg3 and xmmreg2 to xmmreg1
C4: rxb0_2: w xmmreg2 001:2B:11 xmmreg1 xmmreg3: imm
m128 and xmmreg2 to xmmreg1
C4: rxb0_2: w xmmreg2 001:2B:mod xmmreg1 r/m: imm
VPBLENDVB — Variable Blend Packed Bytes
xmmreg2 with xmmreg3 into xmmreg1 using xmmreg4 as
C4: rxb0_3: w xmmreg2 001:4C:11 xmmreg1 xmmreg3: xmmreg4
mask
xmmreg2 with mem to xmmreg1 using xmmreg4 as mask
C4: rxb0_3: w xmmreg2 001:4C:mod xmmreg1 r/m: xmmreg4
VPBLENDW — Blend Packed Words
xmmreg2 with xmmreg3 into xmmreg1
C4: rxb0_3: w xmmreg2 001:0E:11 xmmreg1 xmmreg3: imm
xmmreg2 with mem to xmmreg1
C4: rxb0_3: w xmmreg2 001:0E:mod xmmreg1 r/m: imm
VPCMPEQQ — Compare Packed Qword Data of Equal
xmmreg2 with xmmreg3 into xmmreg1
C4: rxb0_2: w xmmreg2 001:29:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:29:mod xmmreg1 r/m:
VPEXTRB — Extract Byte
reg from xmmreg1 using imm
C4: rxb0_3: 0_F 001:14:11 xmmreg1 reg: imm
mem from xmmreg1 using imm
C4: rxb0_3: 0_F 001:14:mod xmmreg1 r/m: imm
VPEXTRD — Extract DWord
reg from xmmreg1 using imm
C4: rxb0_3: 0_F 001:16:11 xmmreg1 reg: imm
mem from xmmreg1 using imm
C4: rxb0_3: 0_F 001:16:mod xmmreg1 r/m: imm
VPEXTRQ — Extract QWord
reg from xmmreg1 using imm
C4: rxb0_3: 1_F 001:16:11 xmmreg1 reg: imm
mem from xmmreg1 using imm
C4: rxb0_3: 1_F 001:16:mod xmmreg1 r/m: imm
VPEXTRW — Extract Word
reg from xmmreg1 using imm
C4: rxb0_3: 0_F 001:15:11 xmmreg1 reg: imm
mem from xmmreg1 using imm
C4: rxb0_3: 0_F 001:15:mod xmmreg1 r/m: imm
VPHMINPOSUW — Packed Horizontal Word Minimum
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:41:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_2: w_F 001:41:mod xmmreg1 r/m
VPINSRB — Insert Byte
reg with xmmreg2 to xmmreg1, imm8
C4: rxb0_3: 0 xmmreg2 001:20:11 xmmreg1 reg: imm
mem with xmmreg2 to xmmreg1, imm8
C4: rxb0_3: 0 xmmreg2 001:20:mod xmmreg1 r/m: imm
VPINSRD — Insert DWord
reg with xmmreg2 to xmmreg1, imm8
C4: rxb0_3: 0 xmmreg2 001:22:11 xmmreg1 reg: imm
mem with xmmreg2 to xmmreg1, imm8
C4: rxb0_3: 0 xmmreg2 001:22:mod xmmreg1 r/m: imm
VPINSRQ — Insert QWord
r64 with xmmreg2 to xmmreg1, imm8
C4: rxb0_3: 1 xmmreg2 001:22:11 xmmreg1 reg: imm
B-72
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
m64 with xmmreg2 to xmmreg1, imm8
C4: rxb0_3: 1 xmmreg2 001:22:mod xmmreg1 r/m: imm
VPMAXSB — Maximum of Packed Signed Byte Integers
xmmreg2 with xmmreg3 into xmmreg1
C4: rxb0_2: w xmmreg2 001:3C:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:3C:mod xmmreg1 r/m
VPMAXSD — Maximum of Packed Signed Dword Integers
xmmreg2 with xmmreg3 into xmmreg1
C4: rxb0_2: w xmmreg2 001:3D:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:3D:mod xmmreg1 r/m
VPMAXUD — Maximum of Packed Unsigned Dword Integers
xmmreg2 with xmmreg3 into xmmreg1
C4: rxb0_2: w xmmreg2 001:3F:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:3F:mod xmmreg1 r/m
VPMAXUW — Maximum of Packed Unsigned Word Integers
xmmreg2 with xmmreg3 into xmmreg1
C4: rxb0_2: w xmmreg2 001:3E:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:3E:mod xmmreg1 r/m
VPMINSB — Minimum of Packed Signed Byte Integers
xmmreg2 with xmmreg3 into xmmreg1
C4: rxb0_2: w xmmreg2 001:38:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:38:mod xmmreg1 r/m
VPMINSD — Minimum of Packed Signed Dword Integers
xmmreg2 with xmmreg3 into xmmreg1
C4: rxb0_2: w xmmreg2 001:39:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:39:mod xmmreg1 r/m
VPMINUD — Minimum of Packed Unsigned Dword Integers
xmmreg2 with xmmreg3 into xmmreg1
C4: rxb0_2: w xmmreg2 001:3B:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:3B:mod xmmreg1 r/m
VPMINUW — Minimum of Packed Unsigned Word Integers
xmmreg2 with xmmreg3 into xmmreg1
C4: rxb0_2: w xmmreg2 001:3A:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:3A:mod xmmreg1 r/m
VPMOVSXBD — Packed Move Sign Extend - Byte to Dword
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:21:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_2: w_F 001:21:mod xmmreg1 r/m
VPMOVSXBQ — Packed Move Sign Extend - Byte to Qword
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:22:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_2: w_F 001:22:mod xmmreg1 r/m
VPMOVSXBW — Packed Move Sign Extend - Byte to Word
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:20:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_2: w_F 001:20:mod xmmreg1 r/m
VPMOVSXWD — Packed Move Sign Extend - Word to Dword
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:23:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_2: w_F 001:23:mod xmmreg1 r/m
VPMOVSXWQ — Packed Move Sign Extend - Word to Qword
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:24:11 xmmreg1 xmmreg2
Vol. 2D B-73
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
mem to xmmreg1
C4: rxb0_2: w_F 001:24:mod xmmreg1 r/m
VPMOVSXDQ — Packed Move Sign Extend - Dword to Qword
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:25:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_2: w_F 001:25:mod xmmreg1 r/m
VPMOVZXBD — Packed Move Zero Extend - Byte to Dword
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:31:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_2: w_F 001:31:mod xmmreg1 r/m
VPMOVZXBQ — Packed Move Zero Extend - Byte to Qword
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:32:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_2: w_F 001:32:mod xmmreg1 r/m
VPMOVZXBW — Packed Move Zero Extend - Byte to Word
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:30:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_2: w_F 001:30:mod xmmreg1 r/m
VPMOVZXWD — Packed Move Zero Extend - Word to Dword
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:33:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_2: w_F 001:33:mod xmmreg1 r/m
VPMOVZXWQ — Packed Move Zero Extend - Word to Qword
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:34:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_2: w_F 001:34:mod xmmreg1 r/m
VPMOVZXDQ — Packed Move Zero Extend - Dword to Qword
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:35:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_2: w_F 001:35:mod xmmreg1 r/m
VPMULDQ — Multiply Packed Signed Dword Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:28:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:28:mod xmmreg1 r/m
VPMULLD — Multiply Packed Signed Dword Integers, Store low Result
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:40:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:40:mod xmmreg1 r/m
VPTEST — Logical Compare
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:17:11 xmmreg1 xmmreg2
mem to xmmreg
C4: rxb0_2: w_F 001:17:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_2: w_F 101:17:11 ymmreg1 ymmreg2
mem to ymmreg
C4: rxb0_2: w_F 101:17:mod ymmreg1 r/m
VROUNDPD — Round Packed Double Precision Values
xmmreg2 to xmmreg1, imm8
C4: rxb0_3: w_F 001:09:11 xmmreg1 xmmreg2: imm
mem to xmmreg1, imm8
C4: rxb0_3: w_F 001:09:mod xmmreg1 r/m: imm
ymmreg2 to ymmreg1, imm8
C4: rxb0_3: w_F 101:09:11 ymmreg1 ymmreg2: imm
mem to ymmreg1, imm8
C4: rxb0_3: w_F 101:09:mod ymmreg1 r/m: imm
VROUNDPS — Round Packed Single Precision Values
B-74
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreg2 to xmmreg1, imm8
C4: rxb0_3: w_F 001:08:11 xmmreg1 xmmreg2: imm
mem to xmmreg1, imm8
C4: rxb0_3: w_F 001:08:mod xmmreg1 r/m: imm
ymmreg2 to ymmreg1, imm8
C4: rxb0_3: w_F 101:08:11 ymmreg1 ymmreg2: imm
mem to ymmreg1, imm8
C4: rxb0_3: w_F 101:08:mod ymmreg1 r/m: imm
VROUNDSD — Round Scalar Double Precision Value
xmmreg2 and xmmreg3 to xmmreg1, imm8
C4: rxb0_3: w xmmreg2 001:0B:11 xmmreg1 xmmreg3: imm
xmmreg2 and mem to xmmreg1, imm8
C4: rxb0_3: w xmmreg2 001:0B:mod xmmreg1 r/m: imm
VROUNDSS — Round Scalar Single Precision Value
xmmreg2 and xmmreg3 to xmmreg1, imm8
C4: rxb0_3: w xmmreg2 001:0A:11 xmmreg1 xmmreg3: imm
xmmreg2 and mem to xmmreg1, imm8
C4: rxb0_3: w xmmreg2 001:0A:mod xmmreg1 r/m: imm
VPCMPESTRI — Packed Compare Explicit Length Strings, Return Index
xmmreg2 with xmmreg1, imm8
C4: rxb0_3: w_F 001:61:11 xmmreg1 xmmreg2: imm
mem with xmmreg1, imm8
C4: rxb0_3: w_F 001:61:mod xmmreg1 r/m: imm
VPCMPESTRM — Packed Compare Explicit Length Strings, Return Mask
xmmreg2 with xmmreg1, imm8
C4: rxb0_3: w_F 001:60:11 xmmreg1 xmmreg2: imm
mem with xmmreg1, imm8
C4: rxb0_3: w_F 001:60:mod xmmreg1 r/m: imm
VPCMPGTQ — Compare Packed Data for Greater Than
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:28:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:28:mod xmmreg1 r/m
VPCMPISTRI — Packed Compare Implicit Length Strings, Return Index
xmmreg2 with xmmreg1, imm8
C4: rxb0_3: w_F 001:63:11 xmmreg1 xmmreg2: imm
mem with xmmreg1, imm8
C4: rxb0_3: w_F 001:63:mod xmmreg1 r/m: imm
VPCMPISTRM — Packed Compare Implicit Length Strings, Return Mask
xmmreg2 with xmmreg1, imm8
C4: rxb0_3: w_F 001:62:11 xmmreg1 xmmreg2: imm
mem with xmmreg, imm8
C4: rxb0_3: w_F 001:62:mod xmmreg1 r/m: imm
VAESDEC — Perform One Round of an AES Decryption Flow
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:DE:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:DE:mod xmmreg1 r/m
VAESDECLAST — Perform Last Round of an AES Decryption Flow
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:DF:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:DF:mod xmmreg1 r/m
VAESENC — Perform One Round of an AES Encryption Flow
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:DC:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:DC:mod xmmreg1 r/m
VAESENCLAST — Perform Last Round of an AES Encryption Flow
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:DD:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:DD:mod xmmreg1 r/m
VAESIMC — Perform the AES InvMixColumn Transformation
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:DB:11 xmmreg1 xmmreg2
Vol. 2D B-75
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
mem to xmmreg1
C4: rxb0_2: w_F 001:DB:mod xmmreg1 r/m
VAESKEYGENASSIST — AES Round Key Generation Assist
xmmreg2 to xmmreg1, imm8
C4: rxb0_3: w_F 001:DF:11 xmmreg1 xmmreg2: imm
mem to xmmreg, imm8
C4: rxb0_3: w_F 001:DF:mod xmmreg1 r/m: imm
VPABSB — Packed Absolute Value
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:1C:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_2: w_F 001:1C:mod xmmreg1 r/m
VPABSD — Packed Absolute Value
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:1E:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_2: w_F 001:1E:mod xmmreg1 r/m
VPABSW — Packed Absolute Value
xmmreg2 to xmmreg1
C4: rxb0_2: w_F 001:1D:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_2: w_F 001:1D:mod xmmreg1 r/m
VPALIGNR — Packed Align Right
xmmreg2 with xmmreg3 to xmmreg1, imm8
C4: rxb0_3: w xmmreg2 001:DD:11 xmmreg1 xmmreg3: imm
xmmreg2 with mem to xmmreg1, imm8
C4: rxb0_3: w xmmreg2 001:DD:mod xmmreg1 r/m: imm
VPHADDD — Packed Horizontal Add
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:02:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:02:mod xmmreg1 r/m
VPHADDW — Packed Horizontal Add
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:01:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:01:mod xmmreg1 r/m
VPHADDSW — Packed Horizontal Add and Saturate
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:03:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:03:mod xmmreg1 r/m
VPHSUBD — Packed Horizontal Subtract
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:06:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:06:mod xmmreg1 r/m
VPHSUBW — Packed Horizontal Subtract
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:05:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:05:mod xmmreg1 r/m
VPHSUBSW — Packed Horizontal Subtract and Saturate
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:07:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:07:mod xmmreg1 r/m
VPMADDUBSW — Multiply and Add Packed Signed and Unsigned Bytes
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:04:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:04:mod xmmreg1 r/m
VPMULHRSW — Packed Multiply High with Round and Scale
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:0B:11 xmmreg1 xmmreg3
B-76
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:0B:mod xmmreg1 r/m
VPSHUFB — Packed Shuffle Bytes
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:00:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:00:mod xmmreg1 r/m
VPSIGNB — Packed SIGN
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:08:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:08:mod xmmreg1 r/m
VPSIGND — Packed SIGN
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:0A:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:0A:mod xmmreg1 r/m
VPSIGNW — Packed SIGN
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: w xmmreg2 001:09:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: w xmmreg2 001:09:mod xmmreg1 r/m
VADDSUBPD — Packed Double-FP Add/Subtract
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:D0:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:D0:mod xmmreg1 r/m
xmmreglo21 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:D0:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:D0:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:D0:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:D0:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:D0:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:D0:mod ymmreg1 r/m
VADDSUBPS — Packed Single-FP Add/Subtract
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 011:D0:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 011:D0:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 011:D0:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 011:D0:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 111:D0:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 111:D0:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 111:D0:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 111:D0:mod ymmreg1 r/m
VHADDPD — Packed Double-FP Horizontal Add
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:7C:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:7C:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:7C:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:7C:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:7C:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:7C:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:7C:11 ymmreg1 ymmreglo3
Vol. 2D B-77
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:7C:mod ymmreg1 r/m
VHADDPS — Packed Single-FP Horizontal Add
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 011:7C:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 011:7C:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 011:7C:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 011:7C:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 111:7C:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 111:7C:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 111:7C:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 111:7C:mod ymmreg1 r/m
VHSUBPD — Packed Double-FP Horizontal Subtract
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:7D:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:7D:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:7D:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:7D:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:7D:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:7D:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:7D:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:7D:mod ymmreg1 r/m
VHSUBPS — Packed Single-FP Horizontal Subtract
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 011:7D:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 011:7D:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 011:7D:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 011:7D:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 111:7D:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 111:7D:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 111:7D:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 111:7D:mod ymmreg1 r/m
VLDDQU — Load Unaligned Integer 128 Bits
mem to xmmreg1
C4: rxb0_1: w_F 011:F0:mod xmmreg1 r/m
mem to xmmreg1
C5: r_F 011:F0:mod xmmreg1 r/m
mem to ymmreg1
C4: rxb0_1: w_F 111:F0:mod ymmreg1 r/m
mem to ymmreg1
C5: r_F 111:F0:mod ymmreg1 r/m
VMOVDDUP — Move One Double-FP and Duplicate
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 011:12:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 011:12:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 011:12:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 011:12:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 111:12:11 ymmreg1 ymmreg2
B-78
Vol. 2D