Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023)

SAFER MODE EXTENSIONS REFERENCE

Operation

(* The state of the internal flag ACMODEFLAG and SENTERFLAG persist across instruction boundary *)

IF (CR4.SMXE=0)

THEN #UD;

ELSE IF (in VMX non-root operation)

THEN VM Exit (reason=”GETSEC instruction”);

ELSE IF (GETSEC leaf unsupported)

THEN #UD;

ELSE IF ((CR0.PE=0) or (CPL>0) or (EFLAGS.VM=1) or (SENTERFLAG=0) or (ACMODEFLAG=1) or (IN_SMM=0) or (in VMX operation) or

(IA32_APIC_BASE.BSP=0) or (TXT chipset not present))

THEN #GP(0);

ELSE

SignalTXTMsg(WAKEUP);

END;

RLP_SIPI_WAKEUP_FROM_SENTER_ROUTINE: (RLP only)

WHILE (no SignalWAKEUP event);

IF (IA32_SMM_MONITOR_CTL[0] ≠ ILP.IA32_SMM_MONITOR_CTL[0])

THEN TXT-SHUTDOWN(#IllegalEvent)

IF (IA32_SMM_MONITOR_CTL[0] = 0)

THEN Unmask SMI pin event;

ELSE

Mask SMI pin event;

Mask A20M, and NMI external pin events (unmask INIT);

Mask SignalWAKEUP event;

Invalidate processor TLB(s);

Drain outgoing transactions;

TempGDTRLIMIT := LOAD(LT.MLE.JOIN);

TempGDTRBASE := LOAD(LT.MLE.JOIN+4);

TempSegSel := LOAD(LT.MLE.JOIN+8);

TempEIP := LOAD(LT.MLE.JOIN+12);

IF (TempGDTLimit & FFFF0000h)

THEN TXT-SHUTDOWN(#BadJOINFormat);

IF ((TempSegSel > TempGDTRLIMIT-15) or (TempSegSel < 8))

THEN TXT-SHUTDOWN(#BadJOINFormat);

IF ((TempSegSel.TI=1) or (TempSegSel.RPL≠0))

THEN TXT-SHUTDOWN(#BadJOINFormat);

CR0.[PG,CD,NW,AM,WP] := 0;

CR0.[NE,PE] := 1;

CR4 := 00004000h;

EFLAGS := 00000002h;

IA32_EFER := 0;

GDTR.BASE := TempGDTRBASE;

GDTR.LIMIT := TempGDTRLIMIT;

CS.SEL := TempSegSel;

CS.BASE := 0;

CS.LIMIT := FFFFFh;

CS.G := 1;

CS.D := 1;

CS.AR := 9Bh;

DS.SEL := TempSegSel+8;

DS.BASE := 0;

DS.LIMIT := FFFFFh;

DS.G := 1;

GETSEC[WAKEUP]—Wake up sleeping processors in measured environment

Vol. 2D

7-41

SAFER MODE EXTENSIONS REFERENCE

DS.D := 1;

DS.AR := 93h;

SS := DS;

ES := DS;

DR7 := 00000400h;

IA32_DEBUGCTL := 0;

EIP := TempEIP;

END;

Flags Affected

None.

Use of Prefixes

LOCK

Causes #UD.

REP*

Cause #UD (includes REPNE/REPNZ and REP/REPE/REPZ).

Operand size

Causes #UD.

66/F2/F3 prefixes are not allowed.

Segment overrides Ignored.

Address size

Ignored.

REX

Ignored.

Protected Mode Exceptions

#UD

If CR4.SMXE = 0.

If GETSEC[WAKEUP] is not reported as supported by GETSEC[CAPABILITIES].

#GP(0)

If CR0.PE = 0 or CPL > 0 or EFLAGS.VM = 1.

If in VMX operation.

If a protected partition is not already active or the processor is currently in authenticated code

mode.

If the processor is in SMM.

#UD

If CR4.SMXE = 0.

If GETSEC[WAKEUP] is not reported as supported by GETSEC[CAPABILITIES].

#GP(0)

GETSEC[WAKEUP] is not recognized in real-address mode.

Virtual-8086 Mode Exceptions

#UD

If CR4.SMXE = 0.

If GETSEC[WAKEUP] is not reported as supported by GETSEC[CAPABILITIES].

#GP(0)

GETSEC[WAKEUP] is not recognized in virtual-8086 mode.

Compatibility Mode Exceptions

All protected mode exceptions apply.

64-Bit Mode Exceptions

All protected mode exceptions apply.

VM-exit Condition

Reason (GETSEC) IF in VMX non-root operation.

7-42

Vol. 2D

GETSEC[WAKEUP]—Wake up sleeping processors in measured environment

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

PREFETCHWT1—Prefetch Vector Data Into Caches with Intent to Write and T1 Hint

Opcode/

Op/

64/32 bit

CPUID Feature

Description

Instruction

Mode

Flag

Support

0F 0D /2

V/V

PREFETCHWT1

Move data from m8 closer to the processor using T1 hint

PREFETCHWT1 m8

with intent to write.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:r/m (r)

Description

Fetches the line of data from memory that contains the byte specified with the source operand to a location in the

cache hierarchy specified by an intent to write hint (so that data is brought into ‘Exclusive’ state via a request for

ownership) and a locality hint:

• T1 (temporal data with respect to first level cache)—prefetch data into the second level cache.

The source operand is a byte memory location. (The locality hints are encoded into the machine level instruction

using bits 3 through 5 of the ModR/M byte. Use of any ModR/M value other than the specified ones will lead to

unpredictable behavior.)

If the line selected is already present in the cache hierarchy at a level closer to the processor, no data movement

occurs. Prefetches from uncacheable or WC memory are ignored.

The PREFETCHWT1 instruction is merely a hint and does not affect program behavior. If executed, this instruction

moves data closer to the processor in anticipation of future use.

The implementation of prefetch locality hints is implementation-dependent, and can be overloaded or ignored by a

processor implementation. The amount of data prefetched is also processor implementation-dependent. It will,

however, be a minimum of 32 bytes. Additional details of the implementation-dependent locality hints are

described in Section 9.5, “Memory Optimization Using Prefetch” of the Intel® 64 and IA-32 Architectures Optimi-

zation Reference Manual.

It should be noted that processors are free to speculatively fetch and cache data from system memory regions that

are assigned a memory-type that permits speculative reads (that is, the WB, WC, and WT memory types). A

PREFETCHWT1 instruction is considered a hint to this speculative behavior. Because this speculative fetching can

occur at any time and is not tied to instruction execution, a PREFETCHWT1 instruction is not ordered with respect

to the fence instructions (MFENCE, SFENCE, and LFENCE) or locked memory references. A PREFETCHWT1 instruc-

tion is also unordered with respect to CLFLUSH and CLFLUSHOPT instructions, other PREFETCHWT1 instructions, or

any other general instruction. It is ordered with respect to serializing instructions such as CPUID, WRMSR, OUT, and

MOV CR.

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

Operation

PREFETCH(mem, Level, State) Prefetches a byte memory location pointed by ‘mem’ into the cache level specified by ‘Level’; a request

for exclusive/ownership is done if ‘State’ is 1. Note that the memory location ignore cache line splits. This operation is considered a

hint for the processor and may be skipped depending on implementation.

Prefetch (m8, Level = 1, EXCLUSIVE=1);

Flags Affected

All flags are affected

C/C++ Compiler Intrinsic Equivalent

void _mm_prefetch( char const *, int hint= _MM_HINT_ET1);

8-2

Vol. 2D

PREFETCHWT1—Prefetch Vector Data Into Caches with Intent to Write and T1 Hint

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

V4FMADDPS/V4FNMADDPS — Packed Single Precision Floating-Point Fused Multiply-Add

(4-iterations)

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

bit Mode

Flag

Support

EVEX.512.F2.0F38.W0 9A /r

V/V

AVX512_4FMAPS

Multiply packed single-precision floating-point

V4FMADDPS zmm1{k1}{z}, zmm2+3,

values from source register block indicated by

m128

zmm2 by values from m128 and accumulate the

result in zmm1.

EVEX.512.F2.0F38.W0 AA /r

V/V

AVX512_4FMAPS

Multiply and negate packed single-precision

V4FNMADDPS zmm1{k1}{z},

floating-point values from source register block

zmm2+3, m128

indicated by zmm2 by values from m128 and

accumulate the result in zmm1.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

Tuple1_4X

ModRM:reg (r, w)

EVEX.vvvv (r)

ModRM:r/m (r)

Description

This instruction computes 4 sequential packed fused single-precision floating-point multiply-add instructions with a

sequentially selected memory operand in each of the four steps.

In the above box, the notation of “+3” is used to denote that the instruction accesses 4 source registers based on

that operand; sources are consecutive, start in a multiple of 4 boundary, and contain the encoded register operand.

This instruction supports memory fault suppression. The entire memory operand is loaded if any of the 16 lowest

significant mask bits is set to 1 or if a “no masking” encoding is used.

The tuple type Tuple1_4X implies that four 32-bit elements (16 bytes) are referenced by the memory operation

portion of this instruction.

Rounding is performed at every FMA (fused multiply and add) boundary. Exceptions are also taken sequentially.

Pre- and post-computational exceptions of the first FMA take priority over the pre- and post-computational excep-

tions of the second FMA, etc.

8-4

Vol. 2D

V4FMADDPS/V4FNMADDPS — Packed Single Precision Floating-Point Fused Multiply-Add (4-iterations)

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

Operation

src_reg_id is the 5 bit index of the vector register specified in the instruction as the src1 register.

define NFMA_PS(kl, vl, dest, k1, msrc, regs_loaded, src_base, posneg):

tmpdest := dest

// reg[] is an array representing the SIMD register file.

FOR j := 0 to regs_loaded-1:

FOR i := 0 to kl-1:

IF k1[i] or *no writemask*:

IF posneg = 0:

tmpdest.single[i] := RoundFPControl_MXCSR(tmpdest.single[i] - reg[src_base + j ].single[i] * msrc.single[j])

ELSE:

tmpdest.single[i] := RoundFPControl_MXCSR(tmpdest.single[i] + reg[src_base + j ].single[i] * msrc.single[j])

ELSE IF *zeroing*:

tmpdest.single[i] := 0

dest := tmpdst

dest[MAX_VL-1:VL] := 0

V4FMADDPS and V4FNMADDPS dest{k1}, src1, msrc (AVX512)

KL, VL = (16,512)

regs_loaded := 4

src_base := src_reg_id & ~3 // for src1 operand

posneg := 0 if negative form, 1 otherwise

NFMA_PS(kl, vl, dest, k1, msrc, regs_loaded, src_base, posneg)

Intel C/C++ Compiler Intrinsic Equivalent

V4FMADDPS __m512 _mm512_4fmadd_ps( __m512, __m512x4, __m128 *);

V4FMADDPS __m512 _mm512_mask_4fmadd_ps(__m512, __mmask16, __m512x4, __m128 *);

V4FMADDPS __m512 _mm512_maskz_4fmadd_ps(__mmask16, __m512, __m512x4, __m128 *);

V4FNMADDPS __m512 _mm512_4fnmadd_ps(__m512, __m512x4, __m128 *);

V4FNMADDPS __m512 _mm512_mask_4fnmadd_ps(__m512, __mmask16, __m512x4, __m128 *);

V4FNMADDPS __m512 _mm512_maskz_4fnmadd_ps(__mmask16, __m512, __m512x4, __m128 *);

SIMD Floating-Point Exceptions

Overflow, Underflow, Invalid, Precision, Denormal.

Other Exceptions

See Type E2; additionally

#UD

If the EVEX broadcast bit is set to 1.

#UD

If the MODRM.mod = 0b11.

V4FMADDPS/V4FNMADDPS — Packed Single Precision Floating-Point Fused Multiply-Add (4-iterations)

Vol. 2D

8-5

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

V4FMADDSS/V4FNMADDSS —Scalar Single Precision Floating-Point Fused Multiply-Add

(4-iterations)

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

bit Mode

Flag

Support

EVEX.LLIG.F2.0F38.W0 9B /r

V/V

AVX512_4FMAPS

Multiply scalar single-precision floating-point

V4FMADDSS xmm1{k1}{z},

values from source register block indicated by

xmm2+3, m128

xmm2 by values from m128 and accumulate the

result in xmm1.

EVEX.LLIG.F2.0F38.W0 AB /r

V/V

AVX512_4FMAPS

Multiply and negate scalar single-precision

V4FNMADDSS xmm1{k1}{z},

floating-point values from source register block

xmm2+3, m128

indicated by xmm2 by values from m128 and

accumulate the result in xmm1.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

Tuple1_4X

ModRM:reg (r, w)

EVEX.vvvv (r)

ModRM:r/m (r)

Description

This instruction computes 4 sequential scalar fused single-precision floating-point multiply-add instructions with a

sequentially selected memory operand in each of the four steps.

In the above box, the notation of “+3” is used to denote that the instruction accesses 4 source registers based that

operand; sources are consecutive, start in a multiple of 4 boundary, and contain the encoded register operand.

This instruction supports memory fault suppression. The entire memory operand is loaded if the least significant

mask bit is set to 1 or if a “no masking” encoding is used.

The tuple type Tuple1_4X implies that four 32-bit elements (16 bytes) are referenced by the memory operation

portion of this instruction.

Rounding is performed at every FMA boundary. Exceptions are also taken sequentially. Pre- and post-computa-

tional exceptions of the first FMA take priority over the pre- and post-computational exceptions of the second FMA,

etc.

Operation

src_reg_id is the 5 bit index of the vector register specified in the instruction as the src1 register.

define NFMA_SS(vl, dest, k1, msrc, regs_loaded, src_base, posneg):

tmpdest := dest

// reg[] is an array representing the SIMD register file.

IF k1[0] or *no writemask*:

FOR j := 0 to regs_loaded - 1:

IF posneg = 0:

tmpdest.single[0] := RoundFPControl_MXCSR(tmpdest.single[0] - reg[src_base + j ].single[0] * msrc.single[j])

ELSE:

tmpdest.single[0] := RoundFPControl_MXCSR(tmpdest.single[0] + reg[src_base + j ].single[0] * msrc.single[j])

ELSE IF *zeroing*:

tmpdest.single[0] := 0

dest := tmpdst

dest[MAX_VL-1:VL] := 0

8-6

Vol. 2D

V4FMADDSS/V4FNMADDSS —Scalar Single Precision Floating-Point Fused Multiply-Add (4-iterations)

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

V4FMADDSS and V4FNMADDSS dest{k1}, src1, msrc (AVX512)

VL = 128

regs_loaded := 4

src_base := src_reg_id & ~3 // for src1 operand

posneg := 0 if negative form, 1 otherwise

NFMA_SS(vl, dest, k1, msrc, regs_loaded, src_base, posneg)

Intel C/C++ Compiler Intrinsic Equivalent

V4FMADDSS __m128 _mm_4fmadd_ss(__m128, __m128x4, __m128 *);

V4FMADDSS __m128 _mm_mask_4fmadd_ss(__m128, __mmask8, __m128x4, __m128 *);

V4FMADDSS __m128 _mm_maskz_4fmadd_ss(__mmask8, __m128, __m128x4, __m128 *);

V4FNMADDSS __m128 _mm_4fnmadd_ss(__m128, __m128x4, __m128 *);

V4FNMADDSS __m128 _mm_mask_4fnmadd_ss(__m128, __mmask8, __m128x4, __m128 *);

V4FNMADDSS __m128 _mm_maskz_4fnmadd_ss(__mmask8, __m128, __m128x4, __m128 *);

SIMD Floating-Point Exceptions

Overflow, Underflow, Invalid, Precision, Denormal.

Other Exceptions

See Type E2; additionally

#UD

If the EVEX broadcast bit is set to 1.

#UD

If the MODRM.mod = 0b11.

V4FMADDSS/V4FNMADDSS —Scalar Single Precision Floating-Point Fused Multiply-Add (4-iterations)

Vol. 2D

8-7

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VEXP2PD—Approximation to the Exponential 2^x of Packed Double Precision Floating-Point

Values with Less Than 2^-23 Relative Error

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EVEX.512.66.0F38.W1 C8 /r

V/V

AVX512ER

Computes approximations to the exponential 2^x (with less

VEXP2PD zmm1 {k1}{z},

than 2^-23 of maximum relative error) of the packed double

zmm2/m512/m64bcst {sae}

precision floating-point values from zmm2/m512/m64bcst and

stores the floating-point result in zmm1with writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

Full

ModRM:reg (r, w)

ModRM:r/m (r)

Description

Computes the approximate base-2 exponential evaluation of the double precision floating-point values in the

source operand (the second operand) and stores the results to the destination operand (the first operand) using

the writemask k1. The approximate base-2 exponential is evaluated with less than 2^-23 of relative error.

Denormal input values are treated as zeros and do not signal #DE, irrespective of MXCSR.DAZ. Denormal results

are flushed to zeros and do not signal #UE, irrespective of MXCSR.FTZ.

The source operand is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit

memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.

EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

A numerically exact implementation of VEXP2xx can be found at https://software.intel.com/en-us/articles/refer-

ence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation

VEXP2PD

(KL, VL) = (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) AND (SRC *is memory*)

THEN DEST[i+63:i] := EXP2_23_DP(SRC[63:0])

ELSE DEST[i+63:i] := EXP2_23_DP(SRC[i+63:i])

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR;

VEXP2PD—Approximation to the Exponential 2^x of Packed Double Precision Floating-Point Values with Less Than 2^-23 Relative Er-

8-8

Vol. 2D

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

Table 8-1. Special Values Behavior

Source Input

Result

Comments

NaN

QNaN(src)

If (SRC = SNaN) then #I

+∞

+/-0

1.0f

Exact result

-∞

+0.0f

Integral value N

2^ (N)

Exact result

Intel C/C++ Compiler Intrinsic Equivalent

VEXP2PD __m512d _mm512_exp2a23_round_pd (__m512d a, int sae);

VEXP2PD __m512d _mm512_mask_exp2a23_round_pd (__m512d a, __mmask8 m, __m512d b, int sae);

VEXP2PD __m512d _mm512_maskz_exp2a23_round_pd ( __mmask8 m, __m512d b, int sae);

SIMD Floating-Point Exceptions

Invalid (if SNaN input), Overflow

Other Exceptions

See Table 2-46, “Type E2 Class Exception Conditions”.

VEXP2PD—Approximation to the Exponential 2^x of Packed Double Precision Floating-Point Values with Less Than 2^-23 Relative

Vol. 2D

8-9

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VEXP2PS—Approximation to the Exponential 2^x of Packed Single Precision Floating-Point

Values with Less Than 2^-23 Relative Error

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EVEX.512.66.0F38.W0 C8 /r

V/V

AVX512ER

Computes approximations to the exponential 2^x (with less

VEXP2PS zmm1 {k1}{z},

than 2^-23 of maximum relative error) of the packed single-

zmm2/m512/m32bcst {sae}

precision floating-point values from zmm2/m512/m32bcst and

stores the floating-point result in zmm1with writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

Full

ModRM:reg (r, w)

ModRM:r/m (r)

Description

Computes the approximate base-2 exponential evaluation of the single-precision floating-point values in the source

operand (the second operand) and store the results in the destination operand (the first operand) using the

writemask k1. The approximate base-2 exponential is evaluated with less than 2^-23 of relative error.

Denormal input values are treated as zeros and do not signal #DE, irrespective of MXCSR.DAZ. Denormal results

are flushed to zeros and do not signal #UE, irrespective of MXCSR.FTZ.

The source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit

memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.

EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

A numerically exact implementation of VEXP2xx can be found at https://software.intel.com/en-us/articles/refer-

ence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation

VEXP2PS

(KL, VL) = (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) AND (SRC *is memory*)

THEN DEST[i+31:i] := EXP2_23_SP(SRC[31:0])

ELSE DEST[i+31:i] := EXP2_23_SP(SRC[i+31:i])

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR;

VEXP2PS—Approximation to the Exponential 2^x of Packed Single Precision Floating-Point Values with Less Than 2^-23 Relative Error

8-10

Vol. 2D

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

Table 8-2. Special Values Behavior

Source Input

Result

Comments

NaN

QNaN(src)

If (SRC = SNaN) then #I

+∞

+/-0

1.0f

Exact result

-∞

+0.0f

Integral value N

2^ (N)

Exact result

Intel C/C++ Compiler Intrinsic Equivalent

VEXP2PS __m512 _mm512_exp2a23_round_ps (__m512 a, int sae);

VEXP2PS __m512 _mm512_mask_exp2a23_round_ps (__m512 a, __mmask16 m, __m512 b, int sae);

VEXP2PS __m512 _mm512_maskz_exp2a23_round_ps (__mmask16 m, __m512 b, int sae);

SIMD Floating-Point Exceptions

Invalid (if SNaN input), Overflow

Other Exceptions

See Table 2-46, “Type E2 Class Exception Conditions”.

VEXP2PS—Approximation to the Exponential 2^x of Packed Single Precision Floating-Point Values with Less Than 2^-23 Relative Er-

Vol. 2D

8-11

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHERPF0QPD—Sparse Prefetch

Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint

Opcode/

Op/

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EVEX.512.66.0F38.W0 C6 /1 /vsib

V/V

AVX512PF

Using signed dword indices, prefetch sparse byte

VGATHERPF0DPS vm32z {k1}

memory locations containing single-precision data

using opmask k1 and T0 hint.

EVEX.512.66.0F38.W0 C7 /1 /vsib

V/V

AVX512PF

Using signed qword indices, prefetch sparse byte

VGATHERPF0QPS vm64z {k1}

memory locations containing single-precision data

using opmask k1 and T0 hint.

EVEX.512.66.0F38.W1 C6 /1 /vsib

V/V

AVX512PF

Using signed dword indices, prefetch sparse byte

VGATHERPF0DPD vm32y {k1}

memory locations containing double precision data

using opmask k1 and T0 hint.

EVEX.512.66.0F38.W1 C7 /1 /vsib

V/V

AVX512PF

Using signed qword indices, prefetch sparse byte

VGATHERPF0QPD vm64z {k1}

memory locations containing double precision data

using opmask k1 and T0 hint.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

Tuple1 Scalar

BaseReg (R): VSIB:base,

VectorReg(R): VSIB:index

Description

The instruction conditionally prefetches up to sixteen 32-bit or eight 64-bit integer byte data elements. The

elements are specified via the VSIB (i.e., the index register is an zmm, holding packed indices). Elements will only

be prefetched if their corresponding mask bit is one.

Lines prefetched are loaded into to a location in the cache hierarchy specified by a locality hint (T0):

• T0 (temporal data)—prefetch data into the first level cache.

[PS data] For dword indices, the instruction will prefetch sixteen memory locations. For qword indices, the instruc-

tion will prefetch eight values.

[PD data] For dword and qword indices, the instruction will prefetch eight memory locations.

Note that:

(1) The prefetches may happen in any order (or not at all). The instruction is a hint.

(2) The mask is left unchanged.

(3) Not valid with 16-bit effective addresses. Will deliver a #UD fault.

(4) No FP nor memory faults may be produced by this instruction.

(5) Prefetches do not handle cache line splits

(6) A #UD is signaled if the memory operand is encoded without the SIB byte.

Operation

BASE_ADDR stands for the memory operand base address (a GPR); may not exist

VINDEX stands for the memory operand vector of indices (a vector register)

SCALE stands for the memory operand scalar (1, 2, 4 or 8)

DISP is the optional 1, 2 or 4 byte displacement

PREFETCH(mem, Level, State) Prefetches a byte memory location pointed by ‘mem’ into the cache level specified by ‘Level’; a request

for exclusive/ownership is done if ‘State’ is 1. Note that the memory location ignore cache line splits. This operation is considered a

hint for the processor and may be skipped depending on implementation.

VGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHERPF0QPD—Sparse Prefetch Packed SP/DP Data Values with Signed

8-12

Vol. 2D

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VGATHERPF0DPS (EVEX encoded version)

(KL, VL) = (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j]

Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+31:i]) * SCALE + DISP], Level=0, RFO = 0)

FI;

ENDFOR

VGATHERPF0DPD (EVEX encoded version)

(KL, VL) = (8, 512)

FOR j := 0 TO KL-1

i := j * 64

k := j * 32

IF k1[j]

Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+31:k]) * SCALE + DISP], Level=0, RFO = 0)

FI;

ENDFOR

VGATHERPF0QPS (EVEX encoded version)

(KL, VL) = (8, 256)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j]

Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+63:i]) * SCALE + DISP], Level=0, RFO = 0)

FI;

ENDFOR

VGATHERPF0QPD (EVEX encoded version)

(KL, VL) = (8, 512)

FOR j := 0 TO KL-1

i := j * 64

k := j * 64

IF k1[j]

Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+63:k]) * SCALE + DISP], Level=0, RFO = 0)

FI;

ENDFOR

Intel C/C++ Compiler Intrinsic Equivalent

VGATHERPF0DPD void _mm512_mask_prefetch_i32gather_pd(__m256i vdx, __mmask8 m, void * base, int scale, int hint);

VGATHERPF0DPS void _mm512_mask_prefetch_i32gather_ps(__m512i vdx, __mmask16 m, void * base, int scale, int hint);

VGATHERPF0QPD void _mm512_mask_prefetch_i64gather_pd(__m512i vdx, __mmask8 m, void * base, int scale, int hint);

VGATHERPF0QPS void _mm512_mask_prefetch_i64gather_ps(__m512i vdx, __mmask8 m, void * base, int scale, int hint);

SIMD Floating-Point Exceptions

None

Other Exceptions

See Table 2-62, “Type E12NP Class Exception Conditions”.

VGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHERPF0QPD—Sparse Prefetch Packed SP/DP Data Values with Signed

Vol. 2D

8-13

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QPD—Sparse Prefetch

Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint

Opcode/

Op/

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EVEX.512.66.0F38.W0 C6 /2 /vsib

V/V

AVX512PF

Using signed dword indices, prefetch sparse byte

VGATHERPF1DPS vm32z {k1}

memory locations containing single-precision data using

opmask k1 and T1 hint.

EVEX.512.66.0F38.W0 C7 /2 /vsib

V/V

AVX512PF

Using signed qword indices, prefetch sparse byte

VGATHERPF1QPS vm64z {k1}

memory locations containing single-precision data using

opmask k1 and T1 hint.

EVEX.512.66.0F38.W1 C6 /2 /vsib

V/V

AVX512PF

Using signed dword indices, prefetch sparse byte

VGATHERPF1DPD vm32y {k1}

memory locations containing double precision data using

opmask k1 and T1 hint.

EVEX.512.66.0F38.W1 C7 /2 /vsib

V/V

AVX512PF

Using signed qword indices, prefetch sparse byte

VGATHERPF1QPD vm64z {k1}

memory locations containing double precision data using

opmask k1 and T1 hint.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

Tuple1 Scalar

BaseReg (R): VSIB:base,

VectorReg(R): VSIB:index

Description

The instruction conditionally prefetches up to sixteen 32-bit or eight 64-bit integer byte data elements. The

elements are specified via the VSIB (i.e., the index register is an zmm, holding packed indices). Elements will only

be prefetched if their corresponding mask bit is one.

Lines prefetched are loaded into to a location in the cache hierarchy specified by a locality hint (T1):

• T1 (temporal data)—prefetch data into the second level cache.

[PS data] For dword indices, the instruction will prefetch sixteen memory locations. For qword indices, the instruc-

tion will prefetch eight values.

[PD data] For dword and qword indices, the instruction will prefetch eight memory locations.

Note that:

(1) The prefetches may happen in any order (or not at all). The instruction is a hint.

(2) The mask is left unchanged.

(3) Not valid with 16-bit effective addresses. Will deliver a #UD fault.

(4) No FP nor memory faults may be produced by this instruction.

(5) Prefetches do not handle cache line splits

(6) A #UD is signaled if the memory operand is encoded without the SIB byte.

Operation

BASE_ADDR stands for the memory operand base address (a GPR); may not exist

VINDEX stands for the memory operand vector of indices (a vector register)

SCALE stands for the memory operand scalar (1, 2, 4 or 8)

DISP is the optional 1, 2 or 4 byte displacement

PREFETCH(mem, Level, State) Prefetches a byte memory location pointed by ‘mem’ into the cache level specified by ‘Level’; a request

for exclusive/ownership is done if ‘State’ is 1. Note that the memory location ignore cache line splits. This operation is considered a

hint for the processor and may be skipped depending on implementation.

VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QPD—Sparse Prefetch Packed SP/DP Data Values with Signed

8-14

Vol. 2D

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VGATHERPF1DPS (EVEX encoded version)

(KL, VL) = (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j]

Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+31:i]) * SCALE + DISP], Level=1, RFO = 0)

FI;

ENDFOR

VGATHERPF1DPD (EVEX encoded version)

(KL, VL) = (8, 512)

FOR j := 0 TO KL-1

i := j * 64

k := j * 32

IF k1[j]

Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+31:k]) * SCALE + DISP], Level=1, RFO = 0)

FI;

ENDFOR

VGATHERPF1QPS (EVEX encoded version)

(KL, VL) = (8, 256)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j]

Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+63:i]) * SCALE + DISP], Level=1, RFO = 0)

FI;

ENDFOR

VGATHERPF1QPD (EVEX encoded version)

(KL, VL) = (8, 512)

FOR j := 0 TO KL-1

i := j * 64

k := j * 64

IF k1[j]

Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+63:k]) * SCALE + DISP], Level=1, RFO = 0)

FI;

ENDFOR

Intel C/C++ Compiler Intrinsic Equivalent

VGATHERPF1DPD void _mm512_mask_prefetch_i32gather_pd(__m256i vdx, __mmask8 m, void * base, int scale, int hint);

VGATHERPF1DPS void _mm512_mask_prefetch_i32gather_ps(__m512i vdx, __mmask16 m, void * base, int scale, int hint);

VGATHERPF1QPD void _mm512_mask_prefetch_i64gather_pd(__m512i vdx, __mmask8 m, void * base, int scale, int hint);

VGATHERPF1QPS void _mm512_mask_prefetch_i64gather_ps(__m512i vdx, __mmask8 m, void * base, int scale, int hint);

SIMD Floating-Point Exceptions

None

Other Exceptions

See Table 2-62, “Type E12NP Class Exception Conditions”.

VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QPD—Sparse Prefetch Packed SP/DP Data Values with Signed

Vol. 2D

8-15

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VP4DPWSSDS — Dot Product of Signed Words with Dword Accumulation and Saturation

(4-iterations)

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

bit Mode

Flag

Support

EVEX.512.F2.0F38.W0 53 /r

V/V

AVX512_4VNNIW

Multiply signed words from source register block

VP4DPWSSDS zmm1{k1}{z},

indicated by zmm2 by signed words from m128

zmm2+3, m128

and accumulate the resulting dword results with

signed saturation in zmm1.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

Tuple1_4X

ModRM:reg (r, w)

EVEX.vvvv (r)

ModRM:r/m (r)

Description

This instruction computes 4 sequential register source-block dot-products of two signed word operands with

doubleword accumulation and signed saturation. The memory operand is sequentially selected in each of the four

steps.

In the above box, the notation of “+3” is used to denote that the instruction accesses 4 source registers based on

that operand; sources are consecutive, start in a multiple of 4 boundary, and contain the encoded register operand.

This instruction supports memory fault suppression. The entire memory operand is loaded if any bit of the lowest

16-bits of the mask is set to 1 or if a “no masking” encoding is used.

The tuple type Tuple1_4X implies that four 32-bit elements (16 bytes) are referenced by the memory operation

portion of this instruction.

Operation

src_reg_id is the 5 bit index of the vector register specified in the instruction as the src1 register.

VP4DPWSSDS dest, src1, src2

(KL,VL) = (16,512)

N := 4

ORIGDEST := DEST

src_base := src_reg_id & ~ (N-1) // for src1 operand

FOR i := 0 to KL-1:

IF k1[i] or *no writemask*:

FOR m := 0 to N-1:

t := SRC2.dword[m]

p1dword := reg[src_base+m].word[2*i] * t.word[0]

p2dword := reg[src_base+m].word[2*i+1] * t.word[1]

DEST.dword[i] := SIGNED_DWORD_SATURATE(DEST.dword[i] + p1dword + p2dword)

ELSE IF *zeroing*:

DEST.dword[i] := 0

ELSE

DEST.dword[i] := ORIGDEST.dword[i]

DEST[MAX_VL-1:VL] := 0

8-16

Vol. 2D

VP4DPWSSDS — Dot Product of Signed Words with Dword Accumulation and Saturation (4-iterations)

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VP4DPWSSD — Dot Product of Signed Words with Dword Accumulation (4-iterations)

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

bit Mode

Flag

Support

EVEX.512.F2.0F38.W0 52 /r

V/V

AVX512_4VNNIW

Multiply signed words from source register block

VP4DPWSSD zmm1{k1}{z}, zmm2+3,

indicated by zmm2 by signed words from m128

m128

and accumulate resulting signed dwords in zmm1.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

Tuple1_4X

ModRM:reg (r, w)

EVEX.vvvv (r)

ModRM:r/m (r)

Description

This instruction computes 4 sequential register source-block dot-products of two signed word operands with

doubleword accumulation; see Figure 8-1 below. The memory operand is sequentially selected in each of the four

steps.

In the above box, the notation of “+3”' is used to denote that the instruction accesses 4 source registers based on

that operand; sources are consecutive, start in a multiple of 4 boundary, and contain the encoded register operand.

This instruction supports memory fault suppression. The entire memory operand is loaded if any bit of the lowest

16-bits of the mask is set to 1 or if a “no masking” encoding is used.

The tuple type Tuple1_4X implies that four 32-bit elements (16 bytes) are referenced by the memory operation

portion of this instruction.

16b

32b

c1=c1+a2*b0+a3*b1

c0=c0+a0*b0+a1*b1

32b

Figure 8-1. Register Source-Block Dot Product of Two Signed Word Operands with Doubleword Accumulation¹

NOTES:

1. For illustration purposes, one source-block dot product instance is shown out of

the four.

8-18

Vol. 2D

VP4DPWSSD — Dot Product of Signed Words with Dword Accumulation (4-iterations)

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

Operation

src_reg_id is the 5 bit index of the vector register specified in the instruction as the src1 register.

VP4DPWSSD dest, src1, src2

(KL,VL) = (16,512)

N := 4

ORIGDEST := DEST

src_base := src_reg_id & ~ (N-1) // for src1 operand

FOR i := 0 to KL-1:

IF k1[i] or *no writemask*:

FOR m := 0 to N-1:

t := SRC2.dword[m]

p1dword := reg[src_base+m].word[2*i] * t.word[0]

p2dword := reg[src_base+m].word[2*i+1] * t.word[1]

DEST.dword[i] := DEST.dword[i] + p1dword + p2dword

ELSE IF *zeroing*:

DEST.dword[i] := 0

ELSE

DEST.dword[i] := ORIGDEST.dword[i]

DEST[MAX_VL-1:VL] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VP4DPWSSD __m512i _mm512_4dpwssd_epi32(__m512i, __m512ix4, __m128i *);

VP4DPWSSD __m512i _mm512_mask_4dpwssd_epi32(__m512i, __mmask16, __m512ix4, __m128i *);

VP4DPWSSD __m512i _mm512_maskz_4dpwssd_epi32(__mmask16, __m512i, __m512ix4, __m128i *);

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Type E4; additionally

#UD

If the EVEX broadcast bit is set to 1.

#UD

If the MODRM.mod = 0b11.

VP4DPWSSD — Dot Product of Signed Words with Dword Accumulation (4-iterations)

Vol. 2D

8-19

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VRCP28PD—Approximation to the Reciprocal of Packed Double Precision Floating-Point Values

with Less Than 2^-28 Relative Error

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EVEX.512.66.0F38.W1 CA /r

V/V

AVX512ER

Computes the approximate reciprocals ( < 2^-28 relative error)

VRCP28PD zmm1 {k1}{z},

of the packed double precision floating-point values in

zmm2/m512/m64bcst {sae}

zmm2/m512/m64bcst and stores the results in zmm1. Under

writemask.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

Full

ModRM:reg (w)

ModRM:r/m (r)

Description

Computes the reciprocal approximation of the float64 values in the source operand (the second operand) and store

the results to the destination operand (the first operand). The approximate reciprocal is evaluated with less than

2^-28 of maximum relative error.

Denormal input values are treated as zeros and do not signal #DE, irrespective of MXCSR.DAZ. Denormal results

are flushed to zeros and do not signal #UE, irrespective of MXCSR.FTZ.

If any source element is NaN, the quietized NaN source value is returned for that element. If any source element is

±∞, ±0.0 is returned for that element. Also, if any source element is ±0.0, ±∞ is returned for that element.

The source operand is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit

memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.

EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

A numerically exact implementation of VRCP28xx can be found at https://software.intel.com/en-us/articles/refer-

ence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation

VRCP28PD (EVEX encoded versions)

(KL, VL) = (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) AND (SRC *is memory*)

THEN DEST[i+63:i] := RCP_28_DP(1.0/SRC[63:0]);

ELSE DEST[i+63:i] := RCP_28_DP(1.0/SRC[i+63:i]);

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR;

VRCP28PD—Approximation to the Reciprocal of Packed Double Precision Floating-Point Values with Less Than 2^-28 Relative Error

8-20

Vol. 2D

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

Table 8-3. VRCP28PD Special Cases

Input value

Result value

Comments

NAN

QNAN(input)

If (SRC = SNaN) then #I

0 ≤ X < 2^-1022

INF

Positive input denormal or zero; #Z

-2^-1022< X ≤ -0

-INF

Negative input denormal or zero; #Z

X > 2¹⁰²²

+0.0f

X < -2¹⁰²²

-0.0f

X = +∞

+0.0f

X = -∞

-0.0f

X = 2^-n

2ⁿ

Exact result (unless input/output is a denormal)

X = -2^-n

-2ⁿ

Exact result (unless input/output is a denormal)

Intel C/C++ Compiler Intrinsic Equivalent

VRCP28PD __m512d _mm512_rcp28_round_pd ( __m512d a, int sae);

VRCP28PD __m512d _mm512_mask_rcp28_round_pd(__m512d a, __mmask8 m, __m512d b, int sae);

VRCP28PD __m512d _mm512_maskz_rcp28_round_pd( __mmask8 m, __m512d b, int sae);

SIMD Floating-Point Exceptions

Invalid (if SNaN input), Divide-by-zero

Other Exceptions

See Table 2-46, “Type E2 Class Exception Conditions”.

VRCP28PD—Approximation to the Reciprocal of Packed Double Precision Floating-Point Values with Less Than 2^-28 Relative Error

Vol. 2D

8-21

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VRCP28SD—Approximation to the Reciprocal of Scalar Double Precision Floating-Point Value

with Less Than 2^-28 Relative Error

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EVEX.LLIG.66.0F38.W1 CB /r

V/V

AVX512ER

Computes the approximate reciprocal ( < 2^-28 relative

VRCP28SD xmm1 {k1}{z}, xmm2,

error) of the scalar double precision floating-point value in

xmm3/m64 {sae}

xmm3/m64 and stores the results in xmm1. Under

writemask. Also, upper double precision floating-point

value (bits[127:64]) from xmm2 is copied to

xmm1[127:64].

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

Description

Computes the reciprocal approximation of the low float64 value in the second source operand (the third operand)

and store the result to the destination operand (the first operand). The approximate reciprocal is evaluated with

less than 2^-28 of maximum relative error. The result is written into the low float64 element of the destination

operand according to the writemask k1. Bits 127:64 of the destination is copied from the corresponding bits of the

first source operand (the second operand).

A denormal input value is treated as zero and does not signal #DE, irrespective of MXCSR.DAZ. A denormal result

is flushed to zero and does not signal #UE, irrespective of MXCSR.FTZ.

If any source element is NaN, the quietized NaN source value is returned for that element. If any source element is

±∞, ±0.0 is returned for that element. Also, if any source element is ±0.0, ±∞ is returned for that element.

The first source operand is an XMM register. The second source operand is an XMM register or a 64-bit memory

location. The destination operand is a XMM register, conditionally updated using writemask k1.

A numerically exact implementation of VRCP28xx can be found at https://software.intel.com/en-us/articles/refer-

ence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation

VRCP28SD ((EVEX encoded versions)

IF k1[0] OR *no writemask* THEN

DEST[63: 0] := RCP_28_DP(1.0/SRC2[63: 0]);

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[63: 0] remains unchanged*

ELSE

; zeroing-masking

DEST[63: 0] := 0

FI;

ENDFOR;

DEST[127:64] := SRC1[127: 64]

DEST[MAXVL-1:128] := 0

VRCP28SD—Approximation to the Reciprocal of Scalar Double Precision Floating-Point Value with Less Than 2^-28 Relative Error

8-22

Vol. 2D

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

Table 8-4. VRCP28SD Special Cases

Input value

Result value

Comments

NAN

QNAN(input)

If (SRC = SNaN) then #I

0 ≤ X < 2^-1022

INF

Positive input denormal or zero; #Z

-2^-1022< X ≤ -0

-INF

Negative input denormal or zero; #Z

X > 2¹⁰²²

+0.0f

X < -2¹⁰²²

-0.0f

X = +∞

+0.0f

X = -∞

-0.0f

X = 2^-n

2ⁿ

Exact result (unless input/output is a denormal)

X = -2^-n

-2ⁿ

Exact result (unless input/output is a denormal)

Intel C/C++ Compiler Intrinsic Equivalent

VRCP28SD __m128d _mm_rcp28_round_sd ( __m128d a, __m128d b, int sae);

VRCP28SD __m128d _mm_mask_rcp28_round_sd(__m128d s, __mmask8 m, __m128d a, __m128d b, int sae);

VRCP28SD __m128d _mm_maskz_rcp28_round_sd(__mmask8 m, __m128d a, __m128d b, int sae);

SIMD Floating-Point Exceptions

Invalid (if SNaN input), Divide-by-zero

Other Exceptions

See Table 2-47, “Type E3 Class Exception Conditions”.

VRCP28SD—Approximation to the Reciprocal of Scalar Double Precision Floating-Point Value with Less Than 2^-28 Relative Error

Vol. 2D

8-23

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VRCP28PS—Approximation to the Reciprocal of Packed Single Precision Floating-Point Values

with Less Than 2^-28 Relative Error

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EVEX.512.66.0F38.W0 CA /r

V/V

AVX512ER

Computes the approximate reciprocals ( < 2^-28 relative

VRCP28PS zmm1 {k1}{z},

error) of the packed single-precision floating-point values in

zmm2/m512/m32bcst {sae}

zmm2/m512/m32bcst and stores the results in zmm1. Under

writemask.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

Full

ModRM:reg (w)

ModRM:r/m (r)

Description

Computes the reciprocal approximation of the float32 values in the source operand (the second operand) and store

the results to the destination operand (the first operand) using the writemask k1. The approximate reciprocal is

evaluated with less than 2^-28 of maximum relative error prior to final rounding. The final results are rounded to

< 2^-23 relative error before written to the destination.

Denormal input values are treated as zeros and do not signal #DE, irrespective of MXCSR.DAZ. Denormal results

are flushed to zeros and do not signal #UE, irrespective of MXCSR.FTZ.

If any source element is NaN, the quietized NaN source value is returned for that element. If any source element is

±∞, ±0.0 is returned for that element. Also, if any source element is ±0.0, ±∞ is returned for that element.

The source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit

memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.

EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

A numerically exact implementation of VRCP28xx can be found at https://software.intel.com/en-us/articles/refer-

ence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation

VRCP28PS (EVEX encoded versions)

(KL, VL) = (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) AND (SRC *is memory*)

THEN DEST[i+31:i] := RCP_28_SP(1.0/SRC[31:0]);

ELSE DEST[i+31:i] := RCP_28_SP(1.0/SRC[i+31:i]);

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR;

VRCP28PS—Approximation to the Reciprocal of Packed Single Precision Floating-Point Values with Less Than 2^-28 Relative Error

8-24

Vol. 2D

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

Table 8-5. VRCP28PS Special Cases

Input value

Result value

Comments

NAN

QNAN(input)

If (SRC = SNaN) then #I

0 ≤ X < 2^-126

INF

Positive input denormal or zero; #Z

-2^-126< X ≤ -0

-INF

Negative input denormal or zero; #Z

X > 2¹²⁶

+0.0f

X < -2¹²⁶

-0.0f

X = +∞

+0.0f

X = -∞

-0.0f

X = 2^-n

2ⁿ

Exact result (unless input/output is a denormal)

X = -2^-n

-2ⁿ

Exact result (unless input/output is a denormal)

Intel C/C++ Compiler Intrinsic Equivalent

VRCP28PS _mm512_rcp28_round_ps ( __m512 a, int sae);

VRCP28PS __m512 _mm512_mask_rcp28_round_ps(__m512 s, __mmask16 m, __m512 a, int sae);

VRCP28PS __m512 _mm512_maskz_rcp28_round_ps( __mmask16 m, __m512 a, int sae);

SIMD Floating-Point Exceptions

Invalid (if SNaN input), Divide-by-zero

Other Exceptions

See Table 2-46, “Type E2 Class Exception Conditions”.

VRCP28PS—Approximation to the Reciprocal of Packed Single Precision Floating-Point Values with Less Than 2^-28 Relative Error

Vol. 2D

8-25

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VRCP28SS—Approximation to the Reciprocal of Scalar Single Precision Floating-Point Value

with Less Than 2^-28 Relative Error

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EVEX.LLIG.66.0F38.W0 CB /r

V/V

AVX512ER

Computes the approximate reciprocal ( < 2^-28 relative

VRCP28SS xmm1 {k1}{z},

error) of the scalar single-precision floating-point value in

xmm2, xmm3/m32 {sae}

xmm3/m32 and stores the results in xmm1. Under

writemask. Also, upper 3 single-precision floating-point

values (bits[127:32]) from xmm2 is copied to

xmm1[127:32].

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

Description

Computes the reciprocal approximation of the low float32 value in the second source operand (the third operand)

and store the result to the destination operand (the first operand). The approximate reciprocal is evaluated with

less than 2^-28 of maximum relative error prior to final rounding. The final result is rounded to < 2^-23 relative

error before written into the low float32 element of the destination according to writemask k1. Bits 127:32 of the

destination is copied from the corresponding bits of the first source operand (the second operand).

A denormal input value is treated as zero and does not signal #DE, irrespective of MXCSR.DAZ. A denormal result

is flushed to zero and does not signal #UE, irrespective of MXCSR.FTZ.

If any source element is NaN, the quietized NaN source value is returned for that element. If any source element is

±∞, ±0.0 is returned for that element. Also, if any source element is ±0.0, ±∞ is returned for that element.

The first source operand is an XMM register. The second source operand is an XMM register or a 32-bit memory

location. The destination operand is a XMM register, conditionally updated using writemask k1.

A numerically exact implementation of VRCP28xx can be found at https://software.intel.com/en-us/articles/refer-

ence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation

VRCP28SS ((EVEX encoded versions)

IF k1[0] OR *no writemask* THEN

DEST[31: 0] := RCP_28_SP(1.0/SRC2[31: 0]);

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[31: 0] remains unchanged*

ELSE

; zeroing-masking

DEST[31: 0] := 0

FI;

ENDFOR;

DEST[127:32] := SRC1[127: 32]

DEST[MAXVL-1:128] := 0

VRCP28SS—Approximation to the Reciprocal of Scalar Single Precision Floating-Point Value with Less Than 2^-28 Relative Error

8-26

Vol. 2D

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

Table 8-6. VRCP28SS Special Cases

Input value

Result value

Comments

NAN

QNAN(input)

If (SRC = SNaN) then #I

0 ≤ X < 2^-126

INF

Positive input denormal or zero; #Z

-2^-126< X ≤ -0

-INF

Negative input denormal or zero; #Z

X > 2¹²⁶

+0.0f

X < -2¹²⁶

-0.0f

X = +∞

+0.0f

X = -∞

-0.0f

X = 2^-n

2ⁿ

Exact result (unless input/output is a denormal)

X = -2^-n

-2ⁿ

Exact result (unless input/output is a denormal)

Intel C/C++ Compiler Intrinsic Equivalent

VRCP28SS __m128 _mm_rcp28_round_ss ( __m128 a, __m128 b, int sae);

VRCP28SS __m128 _mm_mask_rcp28_round_ss(__m128 s, __mmask8 m, __m128 a, __m128 b, int sae);

VRCP28SS __m128 _mm_maskz_rcp28_round_ss(__mmask8 m, __m128 a, __m128 b, int sae);

SIMD Floating-Point Exceptions

Invalid (if SNaN input), Divide-by-zero

Other Exceptions

See Table 2-47, “Type E3 Class Exception Conditions”.

VRCP28SS—Approximation to the Reciprocal of Scalar Single Precision Floating-Point Value with Less Than 2^-28 Relative Error

Vol. 2D

8-27

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VRSQRT28PD—Approximation to the Reciprocal Square Root of Packed Double Precision

Floating-Point Values with Less Than 2^-28 Relative Error

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EVEX.512.66.0F38.W1 CC /r

V/V

AVX512ER

Computes approximations to the Reciprocal square root (<2^-

VRSQRT28PD zmm1 {k1}{z},

28 relative error) of the packed double precision floating-point

zmm2/m512/m64bcst {sae}

values from zmm2/m512/m64bcst and stores result in

zmm1with writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

Full

ModRM:reg (w)

ModRM:r/m (r)

Description

Computes the reciprocal square root of the float64 values in the source operand (the second operand) and store

the results to the destination operand (the first operand). The approximate reciprocal is evaluated with less than

2^-28 of maximum relative error.

If any source element is NaN, the quietized NaN source value is returned for that element. Negative (non-zero)

source numbers, as well as -∞, return the canonical NaN and set the Invalid Flag (#I).

A value of -0 must return -∞ and set the DivByZero flags (#Z). Negative numbers should return NaN and set the

Invalid flag (#I). Note however that the instruction flush input denormals to zero of the same sign, so negative

denormals return -∞ and set the DivByZero flag.

The source operand is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit

memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.

EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

A numerically exact implementation of VRSQRT28xx can be found at https://software.intel.com/en-us/arti-

cles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation

VRSQRT28PD (EVEX encoded versions)

(KL, VL) = (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) AND (SRC *is memory*)

THEN DEST[i+63:i] := (1.0/ SQRT(SRC[63:0]));

ELSE DEST[i+63:i] := (1.0/ SQRT(SRC[i+63:i]));

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR;

VRSQRT28PD—Approximation to the Reciprocal Square Root of Packed Double Precision Floating-Point Values with Less Than 2^-28

8-28

Vol. 2D

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

Table 8-7. VRSQRT28PD Special Cases

Input value

Result value

Comments

NAN

QNAN(input)

If (SRC = SNaN) then #I

X = 2^-2n

2ⁿ

X < 0

QNaN_Indefinite

Including -INF

X = -0 or negative denormal

-INF

X = +0 or positive denormal

+INF

X = +INF

Intel C/C++ Compiler Intrinsic Equivalent

VRSQRT28PD __m512d _mm512_rsqrt28_round_pd(__m512d a, int sae);

VRSQRT28PD __m512d _mm512_mask_rsqrt28_round_pd(__m512d s, __mmask8 m,__m512d a, int sae);

VRSQRT28PD __m512d _mm512_maskz_rsqrt28_round_pd(__mmask8 m,__m512d a, int sae);

SIMD Floating-Point Exceptions

Invalid (if SNaN input), Divide-by-zero

Other Exceptions

See Table 2-46, “Type E2 Class Exception Conditions”.

VRSQRT28PD—Approximation to the Reciprocal Square Root of Packed Double Precision Floating-Point Values with Less Than 2^-28

Vol. 2D

8-29

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VRSQRT28SD—Approximation to the Reciprocal Square Root of Scalar Double Precision

Floating-Point Value with Less Than 2^-28 Relative Error

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EVEX.LLIG.66.0F38.W1 CD /r

V/V

AVX512ER

Computes approximate reciprocal square root (<2^-28

VRSQRT28SD xmm1 {k1}{z},

relative error) of the scalar double precision floating-point

xmm2, xmm3/m64 {sae}

value from xmm3/m64 and stores result in xmm1with

writemask k1. Also, upper double precision floating-point

value (bits[127:64]) from xmm2 is copied to

xmm1[127:64].

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

Description

Computes the reciprocal square root of the low float64 value in the second source operand (the third operand) and

store the result to the destination operand (the first operand). The approximate reciprocal square root is evaluated

with less than 2^-28 of maximum relative error. The result is written into the low float64 element of xmm1

according to the writemask k1. Bits 127:64 of the destination is copied from the corresponding bits of the first source operand (the

second operand).

If any source element is NaN, the quietized NaN source value is returned for that element. Negative (non-zero)

source numbers, as well as -∞, return the canonical NaN and set the Invalid Flag (#I).

A value of -0 must return -∞ and set the DivByZero flags (#Z). Negative numbers should return NaN and set the

Invalid flag (#I). Note however that the instruction flush input denormals to zero of the same sign, so negative

denormals return -∞ and set the DivByZero flag.

The first source operand is an XMM register. The second source operand is an XMM register or a 64-bit memory

location. The destination operand is a XMM register.

A numerically exact implementation of VRSQRT28xx can be found at https://software.intel.com/en-us/arti-

cles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation

VRSQRT28SD (EVEX encoded versions)

IF k1[0] OR *no writemask* THEN

DEST[63: 0] := (1.0/ SQRT(SRC[63: 0]));

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[63: 0] remains unchanged*

ELSE

; zeroing-masking

DEST[63: 0] := 0

FI;

ENDFOR;

DEST[127:64] := SRC1[127: 64]

DEST[MAXVL-1:128] := 0

VRSQRT28SD—Approximation to the Reciprocal Square Root of Scalar Double Precision Floating-Point Value with Less Than 2^-28

8-30

Vol. 2D

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

Table 8-8. VRSQRT28SD Special Cases

Input value

Result value

Comments

NAN

QNAN(input)

If (SRC = SNaN) then #I

X = 2^-2n

2ⁿ

X < 0

QNaN_Indefinite

Including -INF

X = -0 or negative denormal

-INF

X = +0 or positive denormal

+INF

X = +INF

Intel C/C++ Compiler Intrinsic Equivalent

VRSQRT28SD __m128d _mm_rsqrt28_round_sd(__m128d a, __m128d b, int rounding);

VRSQRT28SD __m128d _mm_mask_rsqrt28_round_sd(__m128d s, __mmask8 m,__m128d a, __m128d b, int rounding);

VRSQRT28SD __m128d _mm_maskz_rsqrt28_round_sd( __mmask8 m,__m128d a, __m128d b, int rounding);

SIMD Floating-Point Exceptions

Invalid (if SNaN input), Divide-by-zero

Other Exceptions

See Table 2-47, “Type E3 Class Exception Conditions”.

VRSQRT28SD—Approximation to the Reciprocal Square Root of Scalar Double Precision Floating-Point Value with Less Than 2^-28

Vol. 2D

8-31

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VRSQRT28PS—Approximation to the Reciprocal Square Root of Packed Single Precision

Floating-Point Values with Less Than 2^-28 Relative Error

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EVEX.512.66.0F38.W0 CC /r

V/V

AVX512ER

Computes approximations to the Reciprocal square root

VRSQRT28PS zmm1 {k1}{z},

(<2^-28 relative error) of the packed single-precision

zmm2/m512/m32bcst {sae}

floating-point values from zmm2/m512/m32bcst and stores

result in zmm1with writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

Full

ModRM:reg (w)

ModRM:r/m (r)

Description

Computes the reciprocal square root of the float32 values in the source operand (the second operand) and store

the results to the destination operand (the first operand). The approximate reciprocal is evaluated with less than

2^-28 of maximum relative error prior to final rounding. The final results is rounded to < 2^-23 relative error

before written to the destination.

If any source element is NaN, the quietized NaN source value is returned for that element. Negative (non-zero)

source numbers, as well as -∞, return the canonical NaN and set the Invalid Flag (#I).

A value of -0 must return -∞ and set the DivByZero flags (#Z). Negative numbers should return NaN and set the

Invalid flag (#I). Note however that the instruction flush input denormals to zero of the same sign, so negative

denormals return -∞ and set the DivByZero flag.

The source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit

memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.

EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

A numerically exact implementation of VRSQRT28xx can be found at https://software.intel.com/en-us/arti-

cles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation

VRSQRT28PS (EVEX encoded versions)

(KL, VL) = (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) AND (SRC *is memory*)

THEN DEST[i+31:i] := (1.0/ SQRT(SRC[31:0]));

ELSE DEST[i+31:i] := (1.0/ SQRT(SRC[i+31:i]));

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR;

VRSQRT28PS—Approximation to the Reciprocal Square Root of Packed Single Precision Floating-Point Values with Less Than 2^-28

8-32

Vol. 2D

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

Table 8-9. VRSQRT28PS Special Cases

Input value

Result value

Comments

NAN

QNAN(input)

If (SRC = SNaN) then #I

X = 2^-2n

2ⁿ

X < 0

QNaN_Indefinite

Including -INF

X = -0 or negative denormal

-INF

X = +0 or positive denormal

+INF

X = +INF

Intel C/C++ Compiler Intrinsic Equivalent

VRSQRT28PS __m512 _mm512_rsqrt28_round_ps(__m512 a, int sae);

VRSQRT28PS __m512 _mm512_mask_rsqrt28_round_ps(__m512 s, __mmask16 m,__m512 a, int sae);

VRSQRT28PS __m512 _mm512_maskz_rsqrt28_round_ps(__mmask16 m,__m512 a, int sae);

SIMD Floating-Point Exceptions

Invalid (if SNaN input), Divide-by-zero

Other Exceptions

See Table 2-46, “Type E2 Class Exception Conditions”.

VRSQRT28PS—Approximation to the Reciprocal Square Root of Packed Single Precision Floating-Point Values with Less Than 2^-28

Vol. 2D

8-33

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VRSQRT28SS—Approximation to the Reciprocal Square Root of Scalar Single Precision Floating-

Point Value with Less Than 2^-28 Relative Error

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EVEX.LLIG.66.0F38.W0 CD /r

V/V

AVX512ER

Computes approximate reciprocal square root (<2^-28

VRSQRT28SS xmm1 {k1}{z},

relative error) of the scalar single-precision floating-point

xmm2, xmm3/m32 {sae}

value from xmm3/m32 and stores result in xmm1with

writemask k1. Also, upper 3 single-precision floating-point

value (bits[127:32]) from xmm2 is copied to

xmm1[127:32].

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

Description

Computes the reciprocal square root of the low float32 value in the second source operand (the third operand) and

store the result to the destination operand (the first operand). The approximate reciprocal square root is evaluated

with less than 2^-28 of maximum relative error prior to final rounding. The final result is rounded to < 2^-23 rela-

tive error before written to the low float32 element of the destination according to the writemask k1. Bits 127:32 of

the destination is copied from the corresponding bits of the first source operand (the second operand).

If any source element is NaN, the quietized NaN source value is returned for that element. Negative (non-zero)

source numbers, as well as -∞, return the canonical NaN and set the Invalid Flag (#I).

A value of -0 must return -∞ and set the DivByZero flags (#Z). Negative numbers should return NaN and set the

Invalid flag (#I). Note however that the instruction flush input denormals to zero of the same sign, so negative

denormals return -∞ and set the DivByZero flag.

The first source operand is an XMM register. The second source operand is an XMM register or a 32-bit memory

location. The destination operand is a XMM register.

A numerically exact implementation of VRSQRT28xx can be found at https://software.intel.com/en-us/arti-

cles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation

VRSQRT28SS (EVEX encoded versions)

IF k1[0] OR *no writemask* THEN

DEST[31: 0] := (1.0/ SQRT(SRC[31: 0]));

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[31: 0] remains unchanged*

ELSE

; zeroing-masking

DEST[31: 0] := 0

FI;

ENDFOR;

DEST[127:32] := SRC1[127: 32]

DEST[MAXVL-1:128] := 0

VRSQRT28SS—Approximation to the Reciprocal Square Root of Scalar Single Precision Floating-Point Value with Less Than 2^-28 Rel-

8-34

Vol. 2D

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

Table 8-10. VRSQRT28SS Special Cases

Input value

Result value

Comments

NAN

QNAN(input)

If (SRC = SNaN) then #I

X = 2^-2n

2ⁿ

X < 0

QNaN_Indefinite

Including -INF

X = -0 or negative denormal

-INF

X = +0 or positive denormal

+INF

X = +INF

Intel C/C++ Compiler Intrinsic Equivalent

VRSQRT28SS __m128 _mm_rsqrt28_round_ss(__m128 a, __m128 b, int rounding);

VRSQRT28SS __m128 _mm_mask_rsqrt28_round_ss(__m128 s, __mmask8 m,__m128 a,__m128 b, int rounding);

VRSQRT28SS __m128 _mm_maskz_rsqrt28_round_ss(__mmask8 m,__m128 a,__m128 b, int rounding);

SIMD Floating-Point Exceptions

Invalid (if SNaN input), Divide-by-zero

Other Exceptions

See Table 2-47, “Type E3 Class Exception Conditions”.

VRSQRT28SS—Approximation to the Reciprocal Square Root of Scalar Single Precision Floating-Point Value with Less Than 2^-28 Rel-

Vol. 2D

8-35

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF0QPD—Sparse Prefetch

Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint with Intent

to Write

Opcode/

Op/

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EVEX.512.66.0F38.W0 C6 /5 /vsib

V/V

AVX512PF

Using signed dword indices, prefetch sparse byte

VSCATTERPF0DPS vm32z {k1}

memory locations containing single-precision data using

writemask k1 and T0 hint with intent to write.

EVEX.512.66.0F38.W0 C7 /5 /vsib

V/V

AVX512PF

Using signed qword indices, prefetch sparse byte

VSCATTERPF0QPS vm64z {k1}

memory locations containing single-precision data using

writemask k1 and T0 hint with intent to write.

EVEX.512.66.0F38.W1 C6 /5 /vsib

V/V

AVX512PF

Using signed dword indices, prefetch sparse byte

VSCATTERPF0DPD vm32y {k1}

memory locations containing double precision data

using writemask k1 and T0 hint with intent to write.

EVEX.512.66.0F38.W1 C7 /5 /vsib

V/V

AVX512PF

Using signed qword indices, prefetch sparse byte

VSCATTERPF0QPD vm64z {k1}

memory locations containing double precision data

using writemask k1 and T0 hint with intent to write.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

Tuple1 Scalar

BaseReg (R): VSIB:base,

VectorReg(R): VSIB:index

Description

The instruction conditionally prefetches up to sixteen 32-bit or eight 64-bit integer byte data elements. The

elements are specified via the VSIB (i.e., the index register is an zmm, holding packed indices). Elements will only

be prefetched if their corresponding mask bit is one.

cache lines will be brought into exclusive state (RFO) specified by a locality hint (T0):

• T0 (temporal data)—prefetch data into the first level cache.

[PS data] For dword indices, the instruction will prefetch sixteen memory locations. For qword indices, the instruc-

tion will prefetch eight values.

[PD data] For dword and qword indices, the instruction will prefetch eight memory locations.

Note that:

(1) The prefetches may happen in any order (or not at all). The instruction is a hint.

(2) The mask is left unchanged.

(3) Not valid with 16-bit effective addresses. Will deliver a #UD fault.

(4) No FP nor memory faults may be produced by this instruction.

(5) Prefetches do not handle cache line splits

(6) A #UD is signaled if the memory operand is encoded without the SIB byte.

Operation

BASE_ADDR stands for the memory operand base address (a GPR); may not exist

VINDEX stands for the memory operand vector of indices (a vector register)

SCALE stands for the memory operand scalar (1, 2, 4 or 8)

DISP is the optional 1, 2 or 4 byte displacement

PREFETCH(mem, Level, State) Prefetches a byte memory location pointed by ‘mem’ into the cache level specified by ‘Level’; a request

for exclusive/ownership is done if ‘State’ is 1. Note that the memory location ignore cache line splits. This operation is considered a

hint for the processor and may be skipped depending on implementation.

VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF0QPD—Sparse Prefetch Packed SP/DP Data Values with

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Vol. 2D

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VSCATTERPF0DPS (EVEX encoded version)

(KL, VL) = (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j]

Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+31:i]) * SCALE + DISP], Level=0, RFO = 1)

FI;

ENDFOR

VSCATTERPF0DPD (EVEX encoded version)

(KL, VL) = (8, 512)

FOR j := 0 TO KL-1

i := j * 64

k := j * 32

IF k1[j]

Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+31:k]) * SCALE + DISP], Level=0, RFO = 1)

FI;

ENDFOR

VSCATTERPF0QPS (EVEX encoded version)

(KL, VL) = (8, 256)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j]

Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+63:i]) * SCALE + DISP], Level=0, RFO = 1)

FI;

ENDFOR

VSCATTERPF0QPD (EVEX encoded version)

(KL, VL) = (8, 512)

FOR j := 0 TO KL-1

i := j * 64

k := j * 64

IF k1[j]

Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+63:k]) * SCALE + DISP], Level=0, RFO = 1)

FI;

ENDFOR

Intel C/C++ Compiler Intrinsic Equivalent

VSCATTERPF0DPD void _mm512_prefetch_i32scatter_pd(void *base, __m256i vdx, int scale, int hint);

VSCATTERPF0DPD void _mm512_mask_prefetch_i32scatter_pd(void *base, __mmask8 m, __m256i vdx, int scale, int hint);

VSCATTERPF0DPS void _mm512_prefetch_i32scatter_ps(void *base, __m512i vdx, int scale, int hint);

VSCATTERPF0DPS void _mm512_mask_prefetch_i32scatter_ps(void *base, __mmask16 m, __m512i vdx, int scale, int hint);

VSCATTERPF0QPD void _mm512_prefetch_i64scatter_pd(void * base, __m512i vdx, int scale, int hint);

VSCATTERPF0QPD void _mm512_mask_prefetch_i64scatter_pd(void * base, __mmask8 m, __m512i vdx, int scale, int hint);

VSCATTERPF0QPS void _mm512_prefetch_i64scatter_ps(void * base, __m512i vdx, int scale, int hint);

VSCATTERPF0QPS void _mm512_mask_prefetch_i64scatter_ps(void * base, __mmask8 m, __m512i vdx, int scale, int hint);

SIMD Floating-Point Exceptions

None

Other Exceptions

See Table 2-62, “Type E12NP Class Exception Conditions”.

VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF0QPD—Sparse Prefetch Packed SP/DP Data Values with

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INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VSCATTERPF1DPS/VSCATTERPF1QPS/VSCATTERPF1DPD/VSCATTERPF1QPD—Sparse Prefetch

Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint with Intent

to Write

Opcode/

Op/

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EVEX.512.66.0F38.W0 C6 /6 /vsib

V/V

AVX512PF

Using signed dword indices, prefetch sparse byte memory

VSCATTERPF1DPS vm32z {k1}

locations containing single-precision data using writemask

k1 and T1 hint with intent to write.

EVEX.512.66.0F38.W0 C7 /6 /vsib

V/V

AVX512PF

Using signed qword indices, prefetch sparse byte memory

VSCATTERPF1QPS vm64z {k1}

locations containing single-precision data using writemask

k1 and T1 hint with intent to write.

EVEX.512.66.0F38.W1 C6 /6 /vsib

V/V

AVX512PF

Using signed dword indices, prefetch sparse byte memory

VSCATTERPF1DPD vm32y {k1}

locations containing double precision data using

writemask k1 and T1 hint with intent to write.

EVEX.512.66.0F38.W1 C7 /6 /vsib

V/V

AVX512PF

Using signed qword indices, prefetch sparse byte memory

VSCATTERPF1QPD vm64z {k1}

locations containing double precision data using

writemask k1 and T1 hint with intent to write.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

Tuple1 Scalar

BaseReg (R): VSIB:base,

VectorReg(R): VSIB:index

Description

The instruction conditionally prefetches up to sixteen 32-bit or eight 64-bit integer byte data elements. The

elements are specified via the VSIB (i.e., the index register is an zmm, holding packed indices). Elements will only

be prefetched if their corresponding mask bit is one.

cache lines will be brought into exclusive state (RFO) specified by a locality hint (T1):

• T1 (temporal data)—prefetch data into the second level cache.

[PS data] For dword indices, the instruction will prefetch sixteen memory locations. For qword indices, the instruc-

tion will prefetch eight values.

[PD data] For dword and qword indices, the instruction will prefetch eight memory locations.

Note that:

(1) The prefetches may happen in any order (or not at all). The instruction is a hint.

(2) The mask is left unchanged.

(3) Not valid with 16-bit effective addresses. Will deliver a #UD fault.

(4) No FP nor memory faults may be produced by this instruction.

(5) Prefetches do not handle cache line splits

(6) A #UD is signaled if the memory operand is encoded without the SIB byte.

Operation

BASE_ADDR stands for the memory operand base address (a GPR); may not exist

VINDEX stands for the memory operand vector of indices (a vector register)

SCALE stands for the memory operand scalar (1, 2, 4 or 8)

DISP is the optional 1, 2 or 4 byte displacement

PREFETCH(mem, Level, State) Prefetches a byte memory location pointed by ‘mem’ into the cache level specified by ‘Level’; a request

for exclusive/ownership is done if ‘State’ is 1. Note that the memory location ignore cache line splits. This operation is considered a

hint for the processor and may be skipped depending on implementation.

VSCATTERPF1DPS/VSCATTERPF1QPS/VSCATTERPF1DPD/VSCATTERPF1QPD—Sparse Prefetch Packed SP/DP Data Values with

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Vol. 2D

INSTRUCTION SET REFERENCE UNIQUE TO INTEL® XEON PHI™ PROCESSORS

VSCATTERPF1DPS (EVEX encoded version)

(KL, VL) = (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j]

Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+31:i]) * SCALE + DISP], Level=1, RFO = 1)

FI;

ENDFOR

VSCATTERPF1DPD (EVEX encoded version)

(KL, VL) = (8, 512)

FOR j := 0 TO KL-1

i := j * 64

k := j * 32

IF k1[j]

Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+31:k]) * SCALE + DISP], Level=1, RFO = 1)

FI;

ENDFOR

VSCATTERPF1QPS (EVEX encoded version)

(KL, VL) = (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j]

Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+63:i]) * SCALE + DISP], Level=1, RFO = 1)

FI;

ENDFOR

VSCATTERPF1QPD (EVEX encoded version)

(KL, VL) = (8, 512)

FOR j := 0 TO KL-1

i := j * 64

k := j * 64

IF k1[j]

Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+63:k]) * SCALE + DISP], Level=1, RFO = 1)

FI;

ENDFOR

Intel C/C++ Compiler Intrinsic Equivalent

VSCATTERPF1DPD void _mm512_prefetch_i32scatter_pd(void *base, __m256i vdx, int scale, int hint);

VSCATTERPF1DPD void _mm512_mask_prefetch_i32scatter_pd(void *base, __mmask8 m, __m256i vdx, int scale, int hint);

VSCATTERPF1DPS void _mm512_prefetch_i32scatter_ps(void *base, __m512i vdx, int scale, int hint);

VSCATTERPF1DPS void _mm512_mask_prefetch_i32scatter_ps(void *base, __mmask16 m, __m512i vdx, int scale, int hint);

VSCATTERPF1QPD void _mm512_prefetch_i64scatter_pd(void * base, __m512i vdx, int scale, int hint);

VSCATTERPF1QPD void _mm512_mask_prefetch_i64scatter_pd(void * base, __mmask8 m, __m512i vdx, int scale, int hint);

VSCATTERPF1QPS void _mm512_prefetch_i64scatter_ps(void *base, __m512i vdx, int scale, int hint);

VSCATTERPF1QPS void _mm512_mask_prefetch_i64scatter_ps(void *base, __mmask8 m, __m512i vdx, int scale, int hint);

SIMD Floating-Point Exceptions

None

Other Exceptions

See Table 2-62, “Type E12NP Class Exception Conditions”.

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APPENDIX A

OPCODE MAP

Use the opcode tables in this chapter to interpret IA-32 and Intel 64 architecture object code. Instructions are

divided into encoding groups:

•

1-byte, 2-byte and 3-byte opcode encodings are used to encode integer, system, MMX technology,

SSE/SSE2/SSE3/SSSE3/SSE4, and VMX instructions. Maps for these instructions are given in Table A-2

through Table A-6.

• Escape opcodes (in the format: ESC character, opcode, ModR/M byte) are used for floating-point instructions.

The maps for these instructions are provided in Table A-7 through Table A-22.

NOTE

All blanks in opcode maps are reserved and must not be used. Do not depend on the operation of

undefined or blank opcodes.

A.1

USING OPCODE TABLES

Tables in this appendix list opcodes of instructions (including required instruction prefixes, opcode extensions in

associated ModR/M byte). Blank cells in the tables indicate opcodes that are reserved or undefined. Cells marked

“Reserved-NOP” are also reserved but may behave as NOP on certain processors. Software should not use opcodes

corresponding blank cells or cells marked “Reserved-NOP” nor depend on the current behavior of those opcodes.

The opcode map tables are organized by hex values of the upper and lower 4 bits of an opcode byte. For 1-byte

encodings (Table A-2), use the four high-order bits of an opcode to index a row of the opcode table; use the four

low-order bits to index a column of the table. For 2-byte opcodes beginning with 0FH (Table A-3), skip any instruc-

tion prefixes, the 0FH byte (0FH may be preceded by 66H, F2H, or F3H) and use the upper and lower 4-bit values

of the next opcode byte to index table rows and columns. Similarly, for 3-byte opcodes beginning with 0F38H or

0F3AH (Table A-4), skip any instruction prefixes, 0F38H or 0F3AH and use the upper and lower 4-bit values of the

third opcode byte to index table rows and columns. See Section A.2.4, “Opcode Look-up Examples for One, Two,

and Three-Byte Opcodes.”

When a ModR/M byte provides opcode extensions, this information qualifies opcode execution. For information on

how an opcode extension in the ModR/M byte modifies the opcode map in Table A-2 and Table A-3, see Section A.4.

The escape (ESC) opcode tables for floating-point instructions identify the eight high order bits of opcodes at the

top of each page. See Section A.5. If the accompanying ModR/M byte is in the range of 00H-BFH, bits 3-5 (the top

row of the third table on each page) along with the reg bits of ModR/M determine the opcode. ModR/M bytes

outside the range of 00H-BFH are mapped by the bottom two tables on each page of the section.

A.2

KEY TO ABBREVIATIONS

Operands are identified by a two-character code of the form Zz. The first character, an uppercase letter, specifies

the addressing method; the second character, a lowercase letter, specifies the type of operand.

A.2.1

Codes for Addressing Method

The following abbreviations are used to document addressing methods:

Direct address: the instruction has no ModR/M byte; the address of the operand is encoded in the instruc-

tion. No base register, index register, or scaling factor can be applied (for example, far JMP (EA)).

The VEX.vvvv field of the VEX prefix selects a general purpose register.

Vol. 2D A-1

OPCODE MAP

The reg field of the ModR/M byte selects a control register (for example, MOV (0F20, 0F22)).

The reg field of the ModR/M byte selects a debug register (for example,

MOV (0F21,0F23)).

A ModR/M byte follows the opcode and specifies the operand. The operand is either a general-purpose

and any of the following values: a base register, an index register, a scaling factor, a displacement.

EFLAGS/RFLAGS Register.

The reg field of the ModR/M byte selects a general register (for example, AX (000)).

The VEX.vvvv field of the VEX prefix selects a 128-bit XMM register or a 256-bit YMM register, determined

by operand type. For legacy SSE encodings this operand does not exist, changing the instruction to

destructive form.

Immediate data: the operand value is encoded in subsequent bytes of the instruction.

The instruction contains a relative offset to be added to the instruction pointer register (for example, JMP

(0E9), LOOP).

The upper 4 bits of the 8-bit immediate selects a 128-bit XMM register or a 256-bit YMM register, deter-

mined by operand type. (the MSB is ignored in 32-bit mode)

The ModR/M byte may refer only to memory (for example, BOUND, LES, LDS, LSS, LFS, LGS,

CMPXCHG8B).

The R/M field of the ModR/M byte selects a packed-quadword, MMX technology register.

The instruction has no ModR/M byte. The offset of the operand is coded as a word or double word

(depending on address size attribute) in the instruction. No base register, index register, or scaling factor

can be applied (for example, MOV (A0-A3)).

The reg field of the ModR/M byte selects a packed quadword MMX technology register.

A ModR/M byte follows the opcode and specifies the operand. The operand is either an MMX technology

and any of the following values: a base register, an index register, a scaling factor, and a displacement.

The R/M field of the ModR/M byte may refer only to a general register (for example, MOV (0F20-0F23)).

The reg field of the ModR/M byte selects a segment register (for example, MOV (8C,8E)).

The R/M field of the ModR/M byte selects a 128-bit XMM register or a 256-bit YMM register, determined by

operand type.

The reg field of the ModR/M byte selects a 128-bit XMM register or a 256-bit YMM register, determined by

operand type.

A ModR/M byte follows the opcode and specifies the operand. The operand is either a 128-bit XMM register,

a 256-bit YMM register (determined by operand type), or a memory address. If it is a memory address, the

address is computed from a segment register and any of the following values: a base register, an index

Memory addressed by the DS:rSI register pair (for example, MOVS, CMPS, OUTS, or LODS).

Memory addressed by the ES:rDI register pair (for example, MOVS, CMPS, INS, STOS, or SCAS).

A.2.2

Codes for Operand Type

The following abbreviations are used to document operand types:

Two one-word operands in memory or two double-word operands in memory, depending on operand-size

attribute (used only by the BOUND instruction).

Byte, regardless of operand-size attribute.

Byte or word, depending on operand-size attribute.

Doubleword, regardless of operand-size attribute.

A-2

Vol. 2D

OPCODE MAP

Double-quadword, regardless of operand-size attribute.

32-bit, 48-bit, or 80-bit pointer, depending on operand-size attribute.

128-bit or 256-bit packed double precision floating-point data.

Quadword MMX technology register (for example: mm0).

128-bit or 256-bit packed single-precision floating-point data.

Quadword, regardless of operand-size attribute.

Quad-Quadword (256-bits), regardless of operand-size attribute.

6-byte or 10-byte pseudo-descriptor.

Scalar element of a 128-bit double precision floating data.

Scalar element of a 128-bit single-precision floating data.

Doubleword integer register (for example: eax).

Word, doubleword or quadword (in 64-bit mode), depending on operand-size attribute.

Word, regardless of operand-size attribute.

dq or qq based on the operand-size attribute.

Doubleword or quadword (in 64-bit mode), depending on operand-size attribute.

Word for 16-bit operand-size or doubleword for 32 or 64-bit operand-size.

A.2.3

When an opcode requires a specific register as an operand, the register is identified by name (for example, AX, CL,

or ESI). The name indicates whether the register is 64, 32, 16, or 8 bits wide.

A register identifier of the form eXX or rXX is used when register width depends on the operand-size attribute. eXX

is used when 16 or 32-bit sizes are possible; rXX is used when 16, 32, or 64-bit sizes are possible. For example:

eAX indicates that the AX register is used when the operand-size attribute is 16 and the EAX register is used when

the operand-size attribute is 32. rAX can indicate AX, EAX or RAX.

When the REX.B bit is used to modify the register specified in the reg field of the opcode, this fact is indicated by

adding “/x” to the register name to indicate the additional possibility. For example, rCX/r9 is used to indicate that

the register could either be rCX or r9. Note that the size of r9 in this case is determined by the operand size attri-

bute (just as for rCX).

A.2.4

Opcode Look-up Examples for One, Two, and Three-Byte Opcodes

This section provides examples that demonstrate how opcode maps are used.

A.2.4.1

One-Byte Opcode Instructions

The opcode map for 1-byte opcodes is shown in Table A-2. The opcode map for 1-byte opcodes is arranged by row

(the least-significant 4 bits of the hexadecimal value) and column (the most-significant 4 bits of the hexadecimal

value). Each entry in the table lists one of the following types of opcodes:

• Instruction mnemonics and operand types using the notations listed in Section A.2

• Opcodes used as an instruction prefix

For each entry in the opcode map that corresponds to an instruction, the rules for interpreting the byte following

the primary opcode fall into one of the following cases:

• A ModR/M byte is required and is interpreted according to the abbreviations listed in Section A.1 and Chapter

2, “Instruction Format,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.

Operand types are listed according to notations listed in Section A.2.

Vol. 2D A-3

OPCODE MAP

• A ModR/M byte is required and includes an opcode extension in the reg field in the ModR/M byte. Use Table A-6

when interpreting the ModR/M byte.

• Use of the ModR/M byte is reserved or undefined. This applies to entries that represent an instruction prefix or

entries for instructions without operands that use ModR/M (for example: 60H, PUSHA; 06H, PUSH ES).

Example A-1. Look-up Example for 1-Byte Opcodes

Opcode 030500000000H for an ADD instruction is interpreted using the 1-byte opcode map (Table A-2) as follows:

• The first digit (0) of the opcode indicates the table row and the second digit (3) indicates the table column. This

locates an opcode for ADD with two operands.

• The first operand (type Gv) indicates a general register that is a word or doubleword depending on the operand-

size attribute. The second operand (type Ev) indicates a ModR/M byte follows that specifies whether the

operand is a word or doubleword general-purpose register or a memory address.

• The ModR/M byte for this instruction is 05H, indicating that a 32-bit displacement follows (00000000H). The

reg/opcode portion of the ModR/M byte (bits 3-5) is 000, indicating the EAX register.

The instruction for this opcode is ADD EAX, mem_op, and the offset of mem_op is 00000000H.

Some 1- and 2-byte opcodes point to group numbers (shaded entries in the opcode map table). Group numbers

indicate that the instruction uses the reg/opcode bits in the ModR/M byte as an opcode extension (refer to Section

A.4).

A.2.4.2

Two-Byte Opcode Instructions

The two-byte opcode map shown in Table A-3 includes primary opcodes that are either two bytes or three bytes in

length. Primary opcodes that are 2 bytes in length begin with an escape opcode 0FH. The upper and lower four bits

of the second opcode byte are used to index a particular row and column in Table A-3.

Two-byte opcodes that are 3 bytes in length begin with a mandatory prefix (66H, F2H, or F3H) and the escape

opcode (0FH). The upper and lower four bits of the third byte are used to index a particular row and column in Table

A-3 (except when the second opcode byte is the 3-byte escape opcodes 38H or 3AH; in this situation refer to

Section A.2.4.3).

For each entry in the opcode map, the rules for interpreting the byte following the primary opcode fall into one of

the following cases:

• A ModR/M byte is required and is interpreted according to the abbreviations listed in Section A.1 and Chapter

2, “Instruction Format,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.

The operand types are listed according to notations listed in Section A.2.

• A ModR/M byte is required and includes an opcode extension in the reg field in the ModR/M byte. Use Table A-6

when interpreting the ModR/M byte.

• Use of the ModR/M byte is reserved or undefined. This applies to entries that represent an instruction without

operands that are encoded using ModR/M (for example: 0F77H, EMMS).

Example A-2. Look-up Example for 2-Byte Opcodes

Look-up opcode 0FA4050000000003H for a SHLD instruction using Table A-3.

• The opcode is located in row A, column 4. The location indicates a SHLD instruction with operands Ev, Gv, and

Ib. Interpret the operands as follows:

— Ev: The ModR/M byte follows the opcode to specify a word or doubleword operand.

— Gv: The reg field of the ModR/M byte selects a general-purpose register.

— Ib: Immediate data is encoded in the subsequent byte of the instruction.

• The third byte is the ModR/M byte (05H). The mod and opcode/reg fields of ModR/M indicate that a 32-bit

displacement is used to locate the first operand in memory and eAX as the second operand.

• The next part of the opcode is the 32-bit displacement for the destination memory operand (00000000H). The

last byte stores immediate byte that provides the count of the shift (03H).

A-4

Vol. 2D

OPCODE MAP

• By this breakdown, it has been shown that this opcode represents the instruction: SHLD DS:00000000H, EAX,

A.2.4.3

Three-Byte Opcode Instructions

The three-byte opcode maps shown in Table A-4 and Table A-5 includes primary opcodes that are either 3 or 4

bytes in length. Primary opcodes that are 3 bytes in length begin with two escape bytes 0F38H or 0F3A. The upper

and lower four bits of the third opcode byte are used to index a particular row and column in Table A-4 or Table A-5.

Three-byte opcodes that are 4 bytes in length begin with a mandatory prefix (66H, F2H, or F3H) and two escape

bytes (0F38H or 0F3AH). The upper and lower four bits of the fourth byte are used to index a particular row and

column in Table A-4 or Table A-5.

For each entry in the opcode map, the rules for interpreting the byte following the primary opcode fall into the

following case:

• A ModR/M byte is required and is interpreted according to the abbreviations listed in A.1 and Chapter 2,

“Instruction Format,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A. The

operand types are listed according to notations listed in Section A.2.

Example A-3. Look-up Example for 3-Byte Opcodes

Look-up opcode 660F3A0FC108H for a PALIGNR instruction using Table A-5.

•

66H is a prefix and 0F3AH indicate to use Table A-5. The opcode is located in row 0, column F indicating a

PALIGNR instruction with operands Vdq, Wdq, and Ib. Interpret the operands as follows:

— Vdq: The reg field of the ModR/M byte selects a 128-bit XMM register.

— Wdq: The R/M field of the ModR/M byte selects either a 128-bit XMM register or memory location.

— Ib: Immediate data is encoded in the subsequent byte of the instruction.

• The next byte is the ModR/M byte (C1H). The reg field indicates that the first operand is XMM0. The mod shows

that the R/M field specifies a register and the R/M indicates that the second operand is XMM1.

• The last byte is the immediate byte (08H).

• By this breakdown, it has been shown that this opcode represents the instruction: PALIGNR XMM0, XMM1, 8.

A.2.4.4

VEX Prefix Instructions

Instructions that include a VEX prefix are organized relative to the 2-byte and 3-byte opcode maps, based on the

VEX.mmmmm field encoding of implied 0F, 0F38H, 0F3AH, respectively. Each entry in the opcode map of a VEX-

encoded instruction is based on the value of the opcode byte, similar to non-VEX-encoded instructions.

A VEX prefix includes several bit fields that encode implied 66H, F2H, F3H prefix functionality (VEX.pp) and

operand size/opcode information (VEX.L). See chapter 4 for details.

Opcode tables A2-A6 include both instructions with a VEX prefix and instructions without a VEX prefix. Many entries

are only made once, but represent both the VEX and non-VEX forms of the instruction. If the VEX prefix is present

all the operands are valid and the mnemonic is usually prefixed with a “v”. If the VEX prefix is not present the

VEX.vvvv operand is not available and the prefix “v” is dropped from the mnemonic.

A few instructions exist only in VEX form and these are marked with a superscript “v”.

Operand size of VEX prefix instructions can be determined by the operand type code. 128-bit vectors are indicated

by 'dq', 256-bit vectors are indicated by 'qq', and instructions with operands supporting either 128 or 256-bit,

determined by VEX.L, are indicated by 'x'. For example, the entry "VMOVUPD Vx,Wx" indicates both VEX.L=0 and

VEX.L=1 are supported.

Vol. 2D A-5

OPCODE MAP

A.2.5

Superscripts Utilized in Opcode Tables

Table A-1 contains notes on particular encodings. These notes are indicated in the following opcode maps by super-

scripts. Gray cells indicate instruction groupings.

Table A-1. Superscripts Utilized in Opcode Tables

Superscript

Meaning of Symbol

Symbol

Bits 5, 4, and 3 of ModR/M byte used as an opcode extension (refer to Section A.4, “Opcode Extensions For One-Byte

And Two-byte Opcodes”).

Use the 0F0B opcode (UD2 instruction), the 0FB9H opcode (UD1 instruction), or the 0FFFH opcode (UD0 instruction)

when deliberately trying to generate an invalid opcode exception (#UD).

Some instructions use the same two-byte opcode. If the instruction has variations, or the opcode represents

different instructions, the ModR/M byte will be used to differentiate the instruction. For the value of the ModR/M

byte needed to decode the instruction, see Table A-6.

i64

The instruction is invalid or not encodable in 64-bit mode. 40 through 4F (single-byte INC and DEC) are REX prefix

combinations when in 64-bit mode (use FE/FF Grp 4 and 5 for INC and DEC).

o64

Instruction is only available when in 64-bit mode.

d64

When in 64-bit mode, instruction defaults to 64-bit operand size and cannot encode 32-bit operand size.

f64

The operand size is forced to a 64-bit operand size when in 64-bit mode (prefixes that change operand size are

ignored for this instruction in 64-bit mode).

VEX form only exists. There is no legacy SSE form of the instruction. For Integer GPR instructions it means VEX

prefix required.

VEX128 & SSE forms only exist (no VEX256), when can’t be inferred from the data size.

A.3

ONE, TWO, AND THREE-BYTE OPCODE MAPS

See Table A-2 through Table A-5 below. The tables are multiple page presentations. Rows and columns with

sequential relationships are placed on facing pages to make look-up tasks easier. Note that table footnotes are not

presented on each page. Table footnotes for each table are presented on the last page of the table.

A-6

Vol. 2D

OPCODE MAP

Table A-2. One-byte Opcode Map: (00H — F7H) *

ADD

PUSH

POP

ESⁱ⁶⁴

Eb, Gb

Ev, Gv

Gb, Eb

Gv, Ev

AL, Ib

rAX, Iz

ADC

PUSH

POP

SSⁱ⁶⁴

Eb, Gb

Ev, Gv

Gb, Eb

Gv, Ev

AL, Ib

rAX, Iz

AND

SEG=ES

DAAⁱ⁶⁴

(Prefix)

Eb, Gb

Ev, Gv

Gb, Eb

Gv, Ev

AL, Ib

rAX, Iz

XOR

SEG=SS

AAAⁱ⁶⁴

(Prefix)

Eb, Gb

Ev, Gv

Gb, Eb

Gv, Ev

AL, Ib

rAX, Iz

INCⁱ⁶⁴ general register / REX^o64 Prefixes

eAX

eCX

eDX

eBX

eSP

eBP

eSI

eDI

REX

REX.B

REX.X

REX.XB

REX.R

REX.RB

REX.RX

REX.RXB

PUSH^d64 general register

rAX/r8

rCX/r9

rDX/r10

rBX/r11

rSP/r12

rBP/r13

rSI/r14

rDI/r15

PUSHAⁱ⁶⁴/

POPAⁱ⁶⁴/

BOUNDⁱ⁶⁴

ARPLⁱ⁶⁴

SEG=FS

SEG=GS

Operand

Address

PUSHADⁱ⁶⁴

POPADⁱ⁶⁴

Gv, Ma

Ew, Gw

(Prefix)

Size

MOVSXD^o64

(Prefix)

Gv, Ev

Jcc^f64, Jb - Short-displacement jump on condition

B/NAE/C

NB/AE/NC

Z/E

NZ/NE

BE/NA

NBE/A

Immediate Grp 1^1A

TEST

XCHG

Eb, Ib

Ev, Iz

Eb, Ibⁱ⁶⁴

Ev, Ib

Eb, Gb

Ev, Gv

Eb, Gb

Ev, Gv

NOP

XCHG word, double-word or quad-word register with rAX

PAUSE(F3)

rCX/r9

rDX/r10

rBX/r11

rSP/r12

rBP/r13

rSI/r14

rDI/r15

XCHG r8, rAX

MOV

MOVS/B

MOVS/W/D/Q

CMPS/B

CMPS/W/D

Yb, Xb

Yv, Xv

Xb, Yb

Xv, Yv

AL, Ob

rAX, Ov

Ob, AL

Ov, rAX

MOV immediate byte into byte register

AL/R8B, Ib

CL/R9B, Ib

DL/R10B, Ib

BL/R11B, Ib

AH/R12B, Ib

CH/R13B, Ib

DH/R14B, Ib

BH/R15B, Ib

Shift Grp 2

near RET^f64

LESⁱ⁶⁴

LDSⁱ⁶⁴

Grp 11^1A - MOV

Gz, Mp

Eb, Ib

Ev, Ib

Eb, Ib

Ev, Iz

VEX+2byte

VEX+1byte

Shift Grp 2^1A

AAMⁱ⁶⁴

AADⁱ⁶⁴

XLAT/

XLATB

Eb, 1

Ev, 1

Eb, CL

Ev, CL

LOOPNE^f64/

LOOPE^f64/

LOOP^f64

JrCXZ^f64/

OUT

LOOPNZ^f64

LOOPZ^f64

AL, Ib

eAX, Ib

Ib, AL

Ib, eAX

LOCK

INT1

REPNE

REP/REPE

HLT

CMC

Unary Grp 3^1A

(Prefix)

XACQUIRE

XRELEASE

(Prefix)

Vol. 2D A-7

OPCODE MAP

Table A-2. One-byte Opcode Map: (08H — FFH) *

PUSH

2-byte

CSⁱ⁶⁴

escape

Eb, Gb

Ev, Gv

Gb, Eb

Gv, Ev

AL, Ib

rAX, Iz

(Table A-3)

SBB

PUSH

POP

DSⁱ⁶⁴

Eb, Gb

Ev, Gv

Gb, Eb

Gv, Ev

AL, Ib

rAX, Iz

SUB

SEG=CS

DASⁱ⁶⁴

(Prefix)

Eb, Gb

Ev, Gv

Gb, Eb

Gv, Ev

AL, Ib

rAX, Iz

CMP

SEG=DS

AASⁱ⁶⁴

(Prefix)

Eb, Gb

Ev, Gv

Gb, Eb

Gv, Ev

AL, Ib

rAX, Iz

DECⁱ⁶⁴ general register / REX^o64 Prefixes

eAX

eCX

eDX

eBX

eSP

eBP

eSI

eDI

REX.W

REX.WB

REX.WX

REX.WXB

REX.WR

REX.WRB

REX.WRX

REX.WRXB

POP^d64 into general register

rAX/r8

rCX/r9

rDX/r10

rBX/r11

rSP/r12

rBP/r13

rSI/r14

rDI/r15

PUSH^d64

IMUL

PUSH^d64

IMUL

INS/

OUTS/

Gv, Ev, Iz

Gv, Ev, Ib

INSB

INSW/

OUTSB

OUTSW/

Yb, DX

INSD

DX, Xb

OUTSD

Yz, DX

DX, Xz

Jcc^f64, Jb- Short displacement jump on condition

P/PE

NP/PO

L/NGE

NL/GE

LE/NG

NLE/G

MOV

LEA

MOV

Grp 1A^1A POP^d64

Ev, Sw

Gv, M

Sw, Ew

Eb, Gb

Ev, Gv

Gb, Eb

Gv, Ev

CBW/

CWD/

far CALLⁱ⁶⁴

FWAIT/

PUSHF/D/Q ^d64/

POPF/D/Q ^d64/

SAHF

LAHF

CWDE/

CDQ/

WAIT

CDQE

CQO

TEST

STOS/B

STOS/W/D/Q

LODS/B

LODS/W/D/Q

SCAS/B

SCAS/W/D/Q

Yb, AL

Yv, rAX

AL, Xb

rAX, Xv

AL, Yb

rAX, Yv

AL, Ib

rAX, Iz

MOV immediate word or double into word, double, or quad register

rAX/r8, Iv

rCX/r9, Iv

rDX/r10, Iv

rBX/r11, Iv

rSP/r12, Iv

rBP/r13, Iv

rSI/r14, Iv

rDI/r15 , Iv

ENTER

LEAVE^d64

far RET

INT3

INT

INTOⁱ⁶⁴

IRET/D/Q

Iw, Ib

ESC (Escape to coprocessor instruction set)

near CALL^f64

JMP

OUT

near^f64

farⁱ⁶⁴

short^f64

AL, DX

eAX, DX

DX, AL

DX, eAX

CLC

STC

CLI

STI

CLD

STD

INC/DEC

Grp 4^1A

Grp 5^1A

NOTES:

* All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locations.

A-8

Vol. 2D

Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 109