Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023)

INSTRUCTION SET REFERENCE, M-U

UD—Undefined Instruction

Opcode

Instruction

Op/

64-Bit

Compat/

Description

Mode

Leg Mode

0F FF /r

UD0¹ r32, r/m32

Valid

Raise invalid opcode exception.

0F B9 /r

UD1 r32, r/m32

Valid

Raise invalid opcode exception.

0F 0B

UD2

Valid

Raise invalid opcode exception.

NOTES:

1. Some processors decode the UD0 instruction without a ModR/M byte. As a result, those processors would deliver an invalid-opcode

exception instead of a fault on instruction fetch when the instruction with a ModR/M byte (and any implied bytes) would cross a page

or segment boundary.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r)

ModRM:r/m (r)

N/A

Description

Generates an invalid opcode exception. This instruction is provided for software testing to explicitly generate an

invalid opcode exception. The opcodes for this instruction are reserved for this purpose.

Other than raising the invalid opcode exception, this instruction has no effect on processor state or memory.

Even though it is the execution of the UD instruction that causes the invalid opcode exception, the instruction

pointer saved by delivery of the exception references the UD instruction (and not the following instruction).

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

Operation

#UD (* Generates invalid opcode exception *);

Flags Affected

None.

Exceptions (All Operating Modes)

#UD

Raises an invalid opcode exception in all operating modes.

UD—Undefined Instruction

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INSTRUCTION SET REFERENCE, M-U

UIRET—User-Interrupt Return

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

bit Mode

Flag

Support

F3 0F 01 EC

V/I

UINTR

Return from handling a user interrupt.

UIRET

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

N/A

Description

UIRET returns from the handling of a user interrupt. It can be executed regardless of CPL.

Execution of UIRET inside a transactional region causes a transactional abort; the abort loads EAX as it would have

had it been due to an execution of IRET.

UIRET can be tracked by Architectural Last Branch Records (LBRs), Intel Processor Trace (Intel PT), and Perfor-

mance Monitoring. For both Intel PT and LBRs, UIRET is recorded in precisely the same manner as IRET. Hence for

LBRs, UIRETs fall into the OTHER_BRANCH category, which implies that IA32_LBR_CTL.OTHER_BRANCH[bit 22]

must be set to record user-interrupt delivery, and that the IA32_LBR_x_INFO.BR_TYPE field will indicate

OTHER_BRANCH for any recorded user interrupt. For Intel PT, control flow tracing must be enabled by setting

IA32_RTIT_CTL.BranchEn[bit 13].

UIRET will also increment performance counters for which counting BR_INST_RETIRED.FAR_BRANCH is enabled.

Operation

Pop tempRIP;

Pop tempRFLAGS; // see below for how this is used to load RFLAGS

Pop tempRSP;

IF tempRIP is not canonical in current paging mode

THEN #GP(0);

FI;

IF ShadowStackEnabled(CPL)

THEN

PopShadowStack SSRIP;

IF SSRIP ≠ tempRIP

THEN #CP (FAR-RET/IRET);

FI;

RIP := tempRIP;

// update in RFLAGS only CF, PF, AF, ZF, SF, TF, DF, OF, NT, RF, AC, and ID

RFLAGS := (RFLAGS & ~254DD5H) | (tempRFLAGS & 254DD5H);

RSP := tempRSP;

UIF := 1;

Clear any cache-line monitoring established by MONITOR or UMONITOR;

Flags Affected

See the Operation section.

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UIRET—User-Interrupt Return

INSTRUCTION SET REFERENCE, M-U

Protected Mode Exceptions

#UD

The UIRET instruction is not recognized in protected mode.

Real-Address Mode Exceptions

#UD

The UIRET instruction is not recognized in real-address mode.

Virtual-8086 Mode Exceptions

#UD

The UIRET instruction is not recognized in virtual-8086 mode.

Compatibility Mode Exceptions

#UD

The UIRET instruction is not recognized in compatibility mode.

64-Bit Mode Exceptions

#GP(0)

If the return instruction pointer is non-canonical.

#SS(0)

If an attempt to pop a value off the stack causes a non-canonical address to be referenced.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#CP

If return instruction pointer from stack and shadow stack do not match.

#UD

If the LOCK prefix is used.

If executed inside an enclave.

If CR4.UINTR = 0.

If CPUID.07H.0H:EDX.UINTR[bit 5] = 0.

UIRET—User-Interrupt Return

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INSTRUCTION SET REFERENCE, M-U

UMONITOR—User Level Set Up Monitor Address

Opcode /

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

F3 0F AE /6

V/V

WAITPKG

Sets up a linear address range to be monitored by

hardware and activates the monitor. The address range

UMONITOR r16/r32/r64

should be a write-back memory caching type. The

address is contained in r16/r32/r64.

Instruction Operand Encoding¹

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:r/m (r)

N/A

Description

The UMONITOR instruction arms address monitoring hardware using an address specified in the source register

(the address range that the monitoring hardware checks for store operations can be determined by using the

CPUID monitor leaf function, EAX=05H). A store to an address within the specified address range triggers the

monitoring hardware. The state of monitor hardware is used by UMWAIT.

The content of the source register is an effective address. By default, the DS segment is used to create a linear

address that is monitored. Segment overrides can be used. The address range must use memory of the write-back

type. Only write-back memory is guaranteed to correctly trigger the monitoring hardware. Additional information

on determining what address range to use in order to prevent false wake-ups is described in Chapter 9, “Multiple-

Processor Management” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

The UMONITOR instruction is ordered as a load operation with respect to other memory transactions. The instruc-

tion is subject to the permission checking and faults associated with a byte load. Like a load, UMONITOR sets the

A-bit but not the D-bit in page tables.

UMONITOR and UMWAIT are available when CPUID.7.0:ECX.WAITPKG[bit 5] is enumerated as 1. UMONITOR and

UMWAIT may be executed at any privilege level. Except for the width of the source register, the instruction’s oper-

ation is the same in non-64-bit modes and in 64-bit mode.

UMONITOR does not interoperate with the legacy MWAIT instruction. If UMONITOR was executed prior to executing

MWAIT and following the most recent execution of the legacy MONITOR instruction, MWAIT will not enter an opti-

mized state. Execution will continue to the instruction following MWAIT.

The UMONITOR instruction causes a transactional abort when used inside a transactional region.

The width of the source register (16b, 32b or 64b) is determined by the effective addressing width, which is

affected in the standard way by the machine mode settings and 67 prefix.

Operation

UMONITOR sets up an address range for the monitor hardware using the content of source register as an effective

address and puts the monitor hardware in armed state. A store to the specified address range will trigger the

monitor hardware.

Intel C/C++ Compiler Intrinsic Equivalent

UMONITOR void _umonitor(void *address);

Numeric Exceptions

None

1. The Mod field of the ModR/M byte must have value 11B.

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INSTRUCTION SET REFERENCE, M-U

Protected Mode Exceptions

#GP(0)

If the specified segment is not SS and the source register is outside the specified segment

limit.

If the specified segment register contains a NULL segment selector.

#SS(0)

If the specified segment is SS and the source register is outside the SS segment limit.

#PF(fault-code)

For a page fault.

#UD

If CPUID.7.0:ECX.WAITPKG[bit 5]=0.

Real Address Mode Exceptions

#GP

If the specified segment is not SS and the source register is outside of the effective address

space from 0 to FFFFH.

#SS

If the specified segment is SS and the source register is outside of the effective address space

from 0 to FFFFH.

#UD

If CPUID.7.0:ECX.WAITPKG[bit 5]=0.

Virtual 8086 Mode Exceptions

Same exceptions as in real address mode; additionally:

#PF(fault-code)

For a page fault.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#GP(0)

If the specified segment is not SS and the linear address is in non-canonical form.

#SS(0)

If the specified segment is SS and the source register is in non-canonical form.

#PF(fault-code)

For a page fault.

#UD

If CPUID.7.0:ECX.WAITPKG[bit 5]=0.

UMONITOR—User Level Set Up Monitor Address

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INSTRUCTION SET REFERENCE, M-U

UMWAIT—User Level Monitor Wait

Opcode /

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

F2 0F AE /6

V/V

WAITPKG

A hint that allows the processor to stop instruction

execution and enter an implementation-dependent

UMWAIT r32, <edx>, <eax>

optimized state until occurrence of a class of events.

Instruction Operand Encoding¹

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:r/m (r)

N/A

Description

UMWAIT instructs the processor to enter an implementation-dependent optimized state while monitoring a range

of addresses. The optimized state may be either a light-weight power/performance optimized state or an improved

power/performance optimized state. The selection between the two states is governed by the explicit input register

bit[0] source operand.

UMWAIT is available when CPUID.7.0:ECX.WAITPKG[bit 5] is enumerated as 1. UMWAIT may be executed at any

privilege level. This instruction’s operation is the same in non-64-bit modes and in 64-bit mode.

The input register contains information such as the preferred optimized state the processor should enter as

described in the following table. Bits other than bit 0 are reserved and will result in #GP if nonzero.

Table 4-26. UMWAIT Input Register Bit Definitions

Bit Value

State Name

Wakeup Time

Power Savings

Other Benefits

bit[0] = 0

C0.2

Slower

Larger

Improves performance of the other SMT thread(s) on the same core.

bit[0] = 1

C0.1

Faster

Smaller

N/A

bits[31:1]

N/A

Reserved

The instruction wakes up when the time-stamp counter reaches or exceeds the implicit EDX:EAX 64-bit input value

(if the monitoring hardware did not trigger beforehand).

Prior to executing the UMWAIT instruction, an operating system may specify the maximum delay it allows the

processor to suspend its operation. It can do so by writing TSC-quanta value to the following 32bit MSR

(IA32_UMWAIT_CONTROL at MSR index E1H):

• IA32_UMWAIT_CONTROL[31:2] — Determines the maximum time in TSC-quanta that the processor can reside

in either C0.1 or C0.2. A zero value indicates no maximum time. The maximum time value is a 32-bit value

where the upper 30 bits come from this field and the lower two bits are zero.

• IA32_UMWAIT_CONTROL[1] — Reserved.

• IA32_UMWAIT_CONTROL[0] — C0.2 is not allowed by the OS. Value of “1” means all C0.2 requests revert to

C0.1.

If the processor that executed a UMWAIT instruction wakes due to the expiration of the operating system time-

limit, the instructions sets RFLAGS.CF; otherwise, that flag is cleared.

The UMWAIT instruction causes a transactional abort when used inside a transactional region.

The UMWAIT instruction operates with the UMONITOR instruction. The two instructions allow the definition of an

address at which to wait (UMONITOR) and an implementation-dependent optimized operation to perform while

waiting (UMWAIT). The execution of UMWAIT is a hint to the processor that it can enter an implementation-depen-

dent-optimized state while waiting for an event or a store operation to the address range armed by UMONITOR. The

UMWAIT instruction will not wait (will not enter an implementation-dependent optimized state) if any of the

1. The Mod field of the ModR/M byte must have value 11B.

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UMWAIT—User Level Monitor Wait

INSTRUCTION SET REFERENCE, M-U

following instructions were executed before UMWAIT and after the most recent execution of UMONITOR: IRET,

MONITOR, SYSEXIT, SYSRET, and far RET (the last if it is changing CPL).

The following additional events cause the processor to exit the implementation-dependent optimized state: a store

to the address range armed by the UMONITOR instruction, an NMI or SMI, a debug exception, a machine check

exception, the BINIT# signal, the INIT# signal, and the RESET# signal. Other implementation-dependent events

may also cause the processor to exit the implementation-dependent optimized state.

In addition, an external interrupt causes the processor to exit the implementation-dependent optimized state

regardless of whether maskable-interrupts are inhibited (EFLAGS.IF =0).

Following exit from the implementation-dependent-optimized state, control passes to the instruction after the

UMWAIT instruction. A pending interrupt that is not masked (including an NMI or an SMI) may be delivered before

execution of that instruction.

Unlike the HLT instruction, the UMWAIT instruction does not restart at the UMWAIT instruction following the

handling of an SMI.

If the preceding UMONITOR instruction did not successfully arm an address range or if UMONITOR was not

executed prior to executing UMWAIT and following the most recent execution of the legacy MONITOR instruction

(UMWAIT does not interoperate with MONITOR), then the processor will not enter an optimized state. Execution

will continue to the instruction following UMWAIT.

A store to the address range armed by the UMONITOR instruction will cause the processor to exit UMWAIT if either

the store was originated by other processor agents or the store was originated by a non-processor agent.

Operation

os_deadline := TSC+(IA32_UMWAIT_CONTROL[31:2]<<2)

instr_deadline := UINT64(EDX:EAX)

IF os_deadline < instr_deadline:

deadline := os_deadline

using_os_deadline := 1

ELSE:

deadline := instr_deadline

using_os_deadline := 0

WHILE monitor hardware armed AND TSC < deadline:

implementation_dependent_optimized_state(Source register, deadline, IA32_UMWAIT_CONTROL[0] )

IF using_os_deadline AND TSC > deadline:

RFLAGS.CF := 1

ELSE:

RFLAGS.CF := 0

RFLAGS.AF,PF,SF,ZF,OF := 0

Intel C/C++ Compiler Intrinsic Equivalent

UMWAIT uint8_t _umwait(uint32_t control, uint64_t counter);

Numeric Exceptions

None

Exceptions (All Operating Modes)

#GP(0)

If src[31:1] != 0.

If CR4.TSD = 1 and CPL != 0.

#UD

If CPUID.7.0:ECX.WAITPKG[bit 5]=0.

UMWAIT—User Level Monitor Wait

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INSTRUCTION SET REFERENCE, M-U

UNPCKHPD—Unpack and Interleave High Packed Double Precision Floating-Point Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

66 0F 15 /r

V/V

SSE2

Unpacks and Interleaves double precision floating-point

UNPCKHPD xmm1, xmm2/m128

values from high quadwords of xmm1 and

xmm2/m128.

VEX.128.66.0F.WIG 15 /r

V/V

AVX

Unpacks and Interleaves double precision floating-point

VUNPCKHPD xmm1,xmm2,

values from high quadwords of xmm2 and

xmm3/m128

xmm3/m128.

VEX.256.66.0F.WIG 15 /r

V/V

AVX

Unpacks and Interleaves double precision floating-point

VUNPCKHPD ymm1,ymm2,

values from high quadwords of ymm2 and

ymm3/m256

ymm3/m256.

EVEX.128.66.0F.W1 15 /r

V/V

AVX512VL

Unpacks and Interleaves double precision floating-point

VUNPCKHPD xmm1 {k1}{z}, xmm2,

AVX512F

values from high quadwords of xmm2 and

xmm3/m128/m64bcst

xmm3/m128/m64bcst subject to writemask k1.

EVEX.256.66.0F.W1 15 /r

V/V

AVX512VL

Unpacks and Interleaves double precision floating-point

VUNPCKHPD ymm1 {k1}{z}, ymm2,

AVX512F

values from high quadwords of ymm2 and

ymm3/m256/m64bcst

ymm3/m256/m64bcst subject to writemask k1.

EVEX.512.66.0F.W1 15 /r

V/V

AVX512F

Unpacks and Interleaves double precision floating-point

VUNPCKHPD zmm1 {k1}{z}, zmm2,

values from high quadwords of zmm2 and

zmm3/m512/m64bcst

zmm3/m512/m64bcst subject to writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs an interleaved unpack of the high double precision floating-point values from the first source operand and

the second source operand. See Figure 4-15 in the Intel® 64 and IA-32 Architectures Software Developer’s

Manual, Volume 2B.

128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-

nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding

ZMM register destination are unmodified. When unpacking from a memory operand, an implementation may fetch

only the appropriate 64 bits; however, alignment to 16-byte boundary and normal segment checking will still be

enforced.

VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM

the corresponding ZMM register destination are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM

EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM

tion operand is a ZMM register, conditionally updated using writemask k1.

EVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM

tion operand is a YMM register, conditionally updated using writemask k1.

EVEX.128 encoded version: The first source operand is a XMM register. The second source operand is a XMM

tion operand is a XMM register, conditionally updated using writemask k1.

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UNPCKHPD—Unpack and Interleave High Packed Double Precision Floating-Point Values

INSTRUCTION SET REFERENCE, M-U

Operation

VUNPCKHPD (EVEX encoded versions when SRC2 is a register)

(KL, VL) = (2, 128), (4, 256), (8, 512)

IF VL >= 128

TMP_DEST[63:0] := SRC1[127:64]

TMP_DEST[127:64] := SRC2[127:64]

FI;

IF VL >= 256

TMP_DEST[191:128] := SRC1[255:192]

TMP_DEST[255:192] := SRC2[255:192]

FI;

IF VL >= 512

TMP_DEST[319:256] := SRC1[383:320]

TMP_DEST[383:320] := SRC2[383:320]

TMP_DEST[447:384] := SRC1[511:448]

TMP_DEST[511:448] := SRC2[511:448]

FI;

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i] := TMP_DEST[i+63:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

UNPCKHPD—Unpack and Interleave High Packed Double Precision Floating-Point Values

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INSTRUCTION SET REFERENCE, M-U

VUNPCKHPD (EVEX encoded version when SRC2 is memory)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF (EVEX.b = 1)

THEN TMP_SRC2[i+63:i] := SRC2[63:0]

ELSE TMP_SRC2[i+63:i] := SRC2[i+63:i]

FI;

ENDFOR;

IF VL >= 128

TMP_DEST[63:0] := SRC1[127:64]

TMP_DEST[127:64] := TMP_SRC2[127:64]

FI;

IF VL >= 256

TMP_DEST[191:128] := SRC1[255:192]

TMP_DEST[255:192] := TMP_SRC2[255:192]

FI;

IF VL >= 512

TMP_DEST[319:256] := SRC1[383:320]

TMP_DEST[383:320] := TMP_SRC2[383:320]

TMP_DEST[447:384] := SRC1[511:448]

TMP_DEST[511:448] := TMP_SRC2[511:448]

FI;

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i] := TMP_DEST[i+63:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VUNPCKHPD (VEX.256 encoded version)

DEST[63:0] := SRC1[127:64]

DEST[127:64] := SRC2[127:64]

DEST[191:128] := SRC1[255:192]

DEST[255:192] := SRC2[255:192]

DEST[MAXVL-1:256] := 0

VUNPCKHPD (VEX.128 encoded version)

DEST[63:0] := SRC1[127:64]

DEST[127:64] := SRC2[127:64]

DEST[MAXVL-1:128] := 0

UNPCKHPD (128-bit Legacy SSE version)

DEST[63:0] := SRC1[127:64]

DEST[127:64] := SRC2[127:64]

DEST[MAXVL-1:128] (Unmodified)

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INSTRUCTION SET REFERENCE, M-U

Intel C/C++ Compiler Intrinsic Equivalent

VUNPCKHPD __m512d _mm512_unpackhi_pd( __m512d a, __m512d b);

VUNPCKHPD __m512d _mm512_mask_unpackhi_pd(__m512d s, __mmask8 k, __m512d a, __m512d b);

VUNPCKHPD __m512d _mm512_maskz_unpackhi_pd(__mmask8 k, __m512d a, __m512d b);

VUNPCKHPD __m256d _mm256_unpackhi_pd(__m256d a, __m256d b)

VUNPCKHPD __m256d _mm256_mask_unpackhi_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);

VUNPCKHPD __m256d _mm256_maskz_unpackhi_pd(__mmask8 k, __m256d a, __m256d b);

UNPCKHPD __m128d _mm_unpackhi_pd(__m128d a, __m128d b)

VUNPCKHPD __m128d _mm_mask_unpackhi_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);

VUNPCKHPD __m128d _mm_maskz_unpackhi_pd(__mmask8 k, __m128d a, __m128d b);

SIMD Floating-Point Exceptions

None

Other Exceptions

Non-EVEX-encoded instructions, see Table 2-21, “Type 4 Class Exception Conditions”.

EVEX-encoded instructions, see Table 2-50, “Type E4NF Class Exception Conditions”.

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INSTRUCTION SET REFERENCE, M-U

UNPCKHPS—Unpack and Interleave High Packed Single Precision Floating-Point Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

NP 0F 15 /r

V/V

SSE

Unpacks and Interleaves single precision floating-point

UNPCKHPS xmm1, xmm2/m128

values from high quadwords of xmm1 and xmm2/m128.

VEX.128.0F.WIG 15 /r

V/V

AVX

Unpacks and Interleaves single precision floating-point

VUNPCKHPS xmm1, xmm2,

values from high quadwords of xmm2 and xmm3/m128.

xmm3/m128

VEX.256.0F.WIG 15 /r

V/V

AVX

Unpacks and Interleaves single precision floating-point

VUNPCKHPS ymm1, ymm2,

values from high quadwords of ymm2 and ymm3/m256.

ymm3/m256

EVEX.128.0F.W0 15 /r

V/V

AVX512VL

Unpacks and Interleaves single precision floating-point

VUNPCKHPS xmm1 {k1}{z}, xmm2,

AVX512F

values from high quadwords of xmm2 and

xmm3/m128/m32bcst

xmm3/m128/m32bcst and write result to xmm1 subject to

writemask k1.

EVEX.256.0F.W0 15 /r

V/V

AVX512VL

Unpacks and Interleaves single precision floating-point

VUNPCKHPS ymm1 {k1}{z}, ymm2,

AVX512F

values from high quadwords of ymm2 and

ymm3/m256/m32bcst

ymm3/m256/m32bcst and write result to ymm1 subject to

writemask k1.

EVEX.512.0F.W0 15 /r

V/V

AVX512F

Unpacks and Interleaves single precision floating-point

VUNPCKHPS zmm1 {k1}{z}, zmm2,

values from high quadwords of zmm2 and

zmm3/m512/m32bcst

zmm3/m512/m32bcst and write result to zmm1 subject to

writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs an interleaved unpack of the high single precision floating-point values from the first source operand and

the second source operand.

128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-

nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding

ZMM register destination are unmodified. When unpacking from a memory operand, an implementation may fetch

only the appropriate 64 bits; however, alignment to 16-byte boundary and normal segment checking will still be

enforced.

VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM

the corresponding ZMM register destination are zeroed.

VEX.256 encoded version: The second source operand is an YMM register or an 256-bit memory location. The first

source operand and destination operands are YMM registers.

4-738

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UNPCKHPS—Unpack and Interleave High Packed Single Precision Floating-Point Values

INSTRUCTION SET REFERENCE, M-U

SRC1

SRC2

DEST

Figure 4-27. VUNPCKHPS Operation

EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM

tion operand is a ZMM register, conditionally updated using writemask k1.

EVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM

tion operand is a YMM register, conditionally updated using writemask k1.

EVEX.128 encoded version: The first source operand is a XMM register. The second source operand is a XMM

tion operand is a XMM register, conditionally updated using writemask k1.

Operation

VUNPCKHPS (EVEX encoded version when SRC2 is a register)

(KL, VL) = (4, 128), (8, 256), (16, 512)

IF VL >= 128

TMP_DEST[31:0] := SRC1[95:64]

TMP_DEST[63:32] := SRC2[95:64]

TMP_DEST[95:64] := SRC1[127:96]

TMP_DEST[127:96] := SRC2[127:96]

FI;

IF VL >= 256

TMP_DEST[159:128] := SRC1[223:192]

TMP_DEST[191:160] := SRC2[223:192]

TMP_DEST[223:192] := SRC1[255:224]

TMP_DEST[255:224] := SRC2[255:224]

FI;

IF VL >= 512

TMP_DEST[287:256] := SRC1[351:320]

TMP_DEST[319:288] := SRC2[351:320]

TMP_DEST[351:320] := SRC1[383:352]

TMP_DEST[383:352] := SRC2[383:352]

TMP_DEST[415:384] := SRC1[479:448]

TMP_DEST[447:416] := SRC2[479:448]

TMP_DEST[479:448] := SRC1[511:480]

TMP_DEST[511:480] := SRC2[511:480]

FI;

UNPCKHPS—Unpack and Interleave High Packed Single Precision Floating-Point Values

Vol. 2B

4-739

INSTRUCTION SET REFERENCE, M-U

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] := TMP_DEST[i+31:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VUNPCKHPS (EVEX encoded version when SRC2 is memory)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF (EVEX.b = 1)

THEN TMP_SRC2[i+31:i] := SRC2[31:0]

ELSE TMP_SRC2[i+31:i] := SRC2[i+31:i]

FI;

ENDFOR;

IF VL >= 128

TMP_DEST[31:0] := SRC1[95:64]

TMP_DEST[63:32] := TMP_SRC2[95:64]

TMP_DEST[95:64] := SRC1[127:96]

TMP_DEST[127:96] := TMP_SRC2[127:96]

FI;

IF VL >= 256

TMP_DEST[159:128] := SRC1[223:192]

TMP_DEST[191:160] := TMP_SRC2[223:192]

TMP_DEST[223:192] := SRC1[255:224]

TMP_DEST[255:224] := TMP_SRC2[255:224]

FI;

IF VL >= 512

TMP_DEST[287:256] := SRC1[351:320]

TMP_DEST[319:288] := TMP_SRC2[351:320]

TMP_DEST[351:320] := SRC1[383:352]

TMP_DEST[383:352] := TMP_SRC2[383:352]

TMP_DEST[415:384] := SRC1[479:448]

TMP_DEST[447:416] := TMP_SRC2[479:448]

TMP_DEST[479:448] := SRC1[511:480]

TMP_DEST[511:480] := TMP_SRC2[511:480]

FI;

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] := TMP_DEST[i+31:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+31:i] := 0

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INSTRUCTION SET REFERENCE, M-U

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VUNPCKHPS (VEX.256 encoded version)

DEST[31:0] := SRC1[95:64]

DEST[63:32] := SRC2[95:64]

DEST[95:64] := SRC1[127:96]

DEST[127:96] := SRC2[127:96]

DEST[159:128] := SRC1[223:192]

DEST[191:160] := SRC2[223:192]

DEST[223:192] := SRC1[255:224]

DEST[255:224] := SRC2[255:224]

DEST[MAXVL-1:256] := 0

VUNPCKHPS (VEX.128 encoded version)

DEST[31:0] := SRC1[95:64]

DEST[63:32] := SRC2[95:64]

DEST[95:64] := SRC1[127:96]

DEST[127:96] := SRC2[127:96]

DEST[MAXVL-1:128] := 0

UNPCKHPS (128-bit Legacy SSE version)

DEST[31:0] := SRC1[95:64]

DEST[63:32] := SRC2[95:64]

DEST[95:64] := SRC1[127:96]

DEST[127:96] := SRC2[127:96]

DEST[MAXVL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

VUNPCKHPS __m512 _mm512_unpackhi_ps( __m512 a, __m512 b);

VUNPCKHPS __m512 _mm512_mask_unpackhi_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);

VUNPCKHPS __m512 _mm512_maskz_unpackhi_ps(__mmask16 k, __m512 a, __m512 b);

VUNPCKHPS __m256 _mm256_unpackhi_ps (__m256 a, __m256 b);

VUNPCKHPS __m256 _mm256_mask_unpackhi_ps(__m256 s, __mmask8 k, __m256 a, __m256 b);

VUNPCKHPS __m256 _mm256_maskz_unpackhi_ps(__mmask8 k, __m256 a, __m256 b);

UNPCKHPS __m128 _mm_unpackhi_ps (__m128 a, __m128 b);

VUNPCKHPS __m128 _mm_mask_unpackhi_ps(__m128 s, __mmask8 k, __m128 a, __m128 b);

VUNPCKHPS __m128 _mm_maskz_unpackhi_ps(__mmask8 k, __m128 a, __m128 b);

SIMD Floating-Point Exceptions

None

Other Exceptions

Non-EVEX-encoded instructions, see Table 2-21, “Type 4 Class Exception Conditions”.

EVEX-encoded instructions, see Table 2-50, “Type E4NF Class Exception Conditions”.

UNPCKHPS—Unpack and Interleave High Packed Single Precision Floating-Point Values

Vol. 2B

4-741

INSTRUCTION SET REFERENCE, M-U

UNPCKLPD—Unpack and Interleave Low Packed Double Precision Floating-Point Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

66 0F 14 /r

V/V

SSE2

Unpacks and Interleaves double precision floating-point

UNPCKLPD xmm1, xmm2/m128

values from low quadwords of xmm1 and xmm2/m128.

VEX.128.66.0F.WIG 14 /r

V/V

AVX

Unpacks and Interleaves double precision floating-point

VUNPCKLPD xmm1,xmm2,

values from low quadwords of xmm2 and xmm3/m128.

xmm3/m128

VEX.256.66.0F.WIG 14 /r

V/V

AVX

Unpacks and Interleaves double precision floating-point

VUNPCKLPD ymm1,ymm2,

values from low quadwords of ymm2 and ymm3/m256.

ymm3/m256

EVEX.128.66.0F.W1 14 /r

V/V

AVX512VL

Unpacks and Interleaves double precision floating-point

VUNPCKLPD xmm1 {k1}{z}, xmm2,

AVX512F

values from low quadwords of xmm2 and

xmm3/m128/m64bcst

xmm3/m128/m64bcst subject to write mask k1.

EVEX.256.66.0F.W1 14 /r

V/V

AVX512VL

Unpacks and Interleaves double precision floating-point

VUNPCKLPD ymm1 {k1}{z}, ymm2,

AVX512F

values from low quadwords of ymm2 and

ymm3/m256/m64bcst

ymm3/m256/m64bcst subject to write mask k1.

EVEX.512.66.0F.W1 14 /r

V/V

AVX512F

Unpacks and Interleaves double precision floating-point

VUNPCKLPD zmm1 {k1}{z}, zmm2,

values from low quadwords of zmm2 and

zmm3/m512/m64bcst

zmm3/m512/m64bcst subject to write mask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs an interleaved unpack of the low double precision floating-point values from the first source operand and

the second source operand.

128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-

nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding

ZMM register destination are unmodified. When unpacking from a memory operand, an implementation may fetch

only the appropriate 64 bits; however, alignment to 16-byte boundary and normal segment checking will still be

enforced.

VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM

the corresponding ZMM register destination are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM

EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM

tion operand is a ZMM register, conditionally updated using writemask k1.

EVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM

tion operand is a YMM register, conditionally updated using writemask k1.

EVEX.128 encoded version: The first source operand is an XMM register. The second source operand is a XMM

tion operand is a XMM register, conditionally updated using writemask k1.

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INSTRUCTION SET REFERENCE, M-U

Operation

VUNPCKLPD (EVEX encoded versions when SRC2 is a register)

(KL, VL) = (2, 128), (4, 256), (8, 512)

IF VL >= 128

TMP_DEST[63:0] := SRC1[63:0]

TMP_DEST[127:64] := SRC2[63:0]

FI;

IF VL >= 256

TMP_DEST[191:128] := SRC1[191:128]

TMP_DEST[255:192] := SRC2[191:128]

FI;

IF VL >= 512

TMP_DEST[319:256] := SRC1[319:256]

TMP_DEST[383:320] := SRC2[319:256]

TMP_DEST[447:384] := SRC1[447:384]

TMP_DEST[511:448] := SRC2[447:384]

FI;

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i] := TMP_DEST[i+63:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

UNPCKLPD—Unpack and Interleave Low Packed Double Precision Floating-Point Values

Vol. 2B

4-743

INSTRUCTION SET REFERENCE, M-U

VUNPCKLPD (EVEX encoded version when SRC2 is memory)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF (EVEX.b = 1)

THEN TMP_SRC2[i+63:i] := SRC2[63:0]

ELSE TMP_SRC2[i+63:i] := SRC2[i+63:i]

FI;

ENDFOR;

IF VL >= 128

TMP_DEST[63:0] := SRC1[63:0]

TMP_DEST[127:64] := TMP_SRC2[63:0]

FI;

IF VL >= 256

TMP_DEST[191:128] := SRC1[191:128]

TMP_DEST[255:192] := TMP_SRC2[191:128]

FI;

IF VL >= 512

TMP_DEST[319:256] := SRC1[319:256]

TMP_DEST[383:320] := TMP_SRC2[319:256]

TMP_DEST[447:384] := SRC1[447:384]

TMP_DEST[511:448] := TMP_SRC2[447:384]

FI;

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i] := TMP_DEST[i+63:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VUNPCKLPD (VEX.256 encoded version)

DEST[63:0] := SRC1[63:0]

DEST[127:64] := SRC2[63:0]

DEST[191:128] := SRC1[191:128]

DEST[255:192] := SRC2[191:128]

DEST[MAXVL-1:256] := 0

VUNPCKLPD (VEX.128 encoded version)

DEST[63:0] := SRC1[63:0]

DEST[127:64] := SRC2[63:0]

DEST[MAXVL-1:128] := 0

UNPCKLPD (128-bit Legacy SSE version)

DEST[63:0] := SRC1[63:0]

DEST[127:64] := SRC2[63:0]

DEST[MAXVL-1:128] (Unmodified)

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UNPCKLPD—Unpack and Interleave Low Packed Double Precision Floating-Point Values

INSTRUCTION SET REFERENCE, M-U

Intel C/C++ Compiler Intrinsic Equivalent

VUNPCKLPD __m512d _mm512_unpacklo_pd( __m512d a, __m512d b);

VUNPCKLPD __m512d _mm512_mask_unpacklo_pd(__m512d s, __mmask8 k, __m512d a, __m512d b);

VUNPCKLPD __m512d _mm512_maskz_unpacklo_pd(__mmask8 k, __m512d a, __m512d b);

VUNPCKLPD __m256d _mm256_unpacklo_pd(__m256d a, __m256d b)

VUNPCKLPD __m256d _mm256_mask_unpacklo_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);

VUNPCKLPD __m256d _mm256_maskz_unpacklo_pd(__mmask8 k, __m256d a, __m256d b);

UNPCKLPD __m128d _mm_unpacklo_pd(__m128d a, __m128d b)

VUNPCKLPD __m128d _mm_mask_unpacklo_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);

VUNPCKLPD __m128d _mm_maskz_unpacklo_pd(__mmask8 k, __m128d a, __m128d b);

SIMD Floating-Point Exceptions

None

Other Exceptions

Non-EVEX-encoded instructions, see Table 2-21, “Type 4 Class Exception Conditions”.

EVEX-encoded instructions, see Table 2-50, “Type E4NF Class Exception Conditions”.

UNPCKLPD—Unpack and Interleave Low Packed Double Precision Floating-Point Values

Vol. 2B

4-745

INSTRUCTION SET REFERENCE, M-U

UNPCKLPS—Unpack and Interleave Low Packed Single Precision Floating-Point Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

NP 0F 14 /r

V/V

SSE

Unpacks and Interleaves single precision floating-point

UNPCKLPS xmm1, xmm2/m128

values from low quadwords of xmm1 and xmm2/m128.

VEX.128.0F.WIG 14 /r

V/V

AVX

Unpacks and Interleaves single precision floating-point

VUNPCKLPS xmm1,xmm2,

values from low quadwords of xmm2 and xmm3/m128.

xmm3/m128

VEX.256.0F.WIG 14 /r

V/V

AVX

Unpacks and Interleaves single precision floating-point

VUNPCKLPS

values from low quadwords of ymm2 and ymm3/m256.

ymm1,ymm2,ymm3/m256

EVEX.128.0F.W0 14 /r

V/V

AVX512VL

Unpacks and Interleaves single precision floating-point

VUNPCKLPS xmm1 {k1}{z}, xmm2,

AVX512F

values from low quadwords of xmm2 and xmm3/mem and

xmm3/m128/m32bcst

write result to xmm1 subject to write mask k1.

EVEX.256.0F.W0 14 /r

V/V

AVX512VL

Unpacks and Interleaves single precision floating-point

VUNPCKLPS ymm1 {k1}{z}, ymm2,

AVX512F

values from low quadwords of ymm2 and ymm3/mem and

ymm3/m256/m32bcst

write result to ymm1 subject to write mask k1.

EVEX.512.0F.W0 14 /r

V/V

AVX512F

Unpacks and Interleaves single precision floating-point

VUNPCKLPS zmm1 {k1}{z}, zmm2,

values from low quadwords of zmm2 and

zmm3/m512/m32bcst

zmm3/m512/m32bcst and write result to zmm1 subject

to write mask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs an interleaved unpack of the low single precision floating-point values from the first source operand and

the second source operand.

128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-

nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding

ZMM register destination are unmodified. When unpacking from a memory operand, an implementation may fetch

only the appropriate 64 bits; however, alignment to 16-byte boundary and normal segment checking will still be

enforced.

VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM

the corresponding ZMM register destination are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM

4-746

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UNPCKLPS—Unpack and Interleave Low Packed Single Precision Floating-Point Values

INSTRUCTION SET REFERENCE, M-U

SRC1

SRC2

DEST

Figure 4-28. VUNPCKLPS Operation

EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM

tion operand is a ZMM register, conditionally updated using writemask k1.

EVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM

tion operand is a YMM register, conditionally updated using writemask k1.

EVEX.128 encoded version: The first source operand is an XMM register. The second source operand is a XMM

tion operand is a XMM register, conditionally updated using writemask k1.

Operation

VUNPCKLPS (EVEX encoded version when SRC2 is a ZMM register)

(KL, VL) = (4, 128), (8, 256), (16, 512)

IF VL >= 128

TMP_DEST[31:0] := SRC1[31:0]

TMP_DEST[63:32] := SRC2[31:0]

TMP_DEST[95:64] := SRC1[63:32]

TMP_DEST[127:96] := SRC2[63:32]

FI;

IF VL >= 256

TMP_DEST[159:128] := SRC1[159:128]

TMP_DEST[191:160] := SRC2[159:128]

TMP_DEST[223:192] := SRC1[191:160]

TMP_DEST[255:224] := SRC2[191:160]

FI;

IF VL >= 512

TMP_DEST[287:256] := SRC1[287:256]

TMP_DEST[319:288] := SRC2[287:256]

TMP_DEST[351:320] := SRC1[319:288]

TMP_DEST[383:352] := SRC2[319:288]

TMP_DEST[415:384] := SRC1[415:384]

TMP_DEST[447:416] := SRC2[415:384]

TMP_DEST[479:448] := SRC1[447:416]

TMP_DEST[511:480] := SRC2[447:416]

FI;

FOR j := 0 TO KL-1

i := j * 32

UNPCKLPS—Unpack and Interleave Low Packed Single Precision Floating-Point Values

Vol. 2B

4-747

INSTRUCTION SET REFERENCE, M-U

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] := TMP_DEST[i+31:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VUNPCKLPS (EVEX encoded version when SRC2 is memory)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 31

IF (EVEX.b = 1)

THEN TMP_SRC2[i+31:i] := SRC2[31:0]

ELSE TMP_SRC2[i+31:i] := SRC2[i+31:i]

FI;

ENDFOR;

IF VL >= 128

TMP_DEST[31:0] := SRC1[31:0]

TMP_DEST[63:32] := TMP_SRC2[31:0]

TMP_DEST[95:64] := SRC1[63:32]

TMP_DEST[127:96] := TMP_SRC2[63:32]

FI;

IF VL >= 256

TMP_DEST[159:128] := SRC1[159:128]

TMP_DEST[191:160] := TMP_SRC2[159:128]

TMP_DEST[223:192] := SRC1[191:160]

TMP_DEST[255:224] := TMP_SRC2[191:160]

FI;

IF VL >= 512

TMP_DEST[287:256] := SRC1[287:256]

TMP_DEST[319:288] := TMP_SRC2[287:256]

TMP_DEST[351:320] := SRC1[319:288]

TMP_DEST[383:352] := TMP_SRC2[319:288]

TMP_DEST[415:384] := SRC1[415:384]

TMP_DEST[447:416] := TMP_SRC2[415:384]

TMP_DEST[479:448] := SRC1[447:416]

TMP_DEST[511:480] := TMP_SRC2[447:416]

FI;

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] := TMP_DEST[i+31:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+31:i] := 0

FI;

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UNPCKLPS—Unpack and Interleave Low Packed Single Precision Floating-Point Values

INSTRUCTION SET REFERENCE, M-U

ENDFOR

DEST[MAXVL-1:VL] := 0

UNPCKLPS (VEX.256 encoded version)

DEST[31:0] := SRC1[31:0]

DEST[63:32] := SRC2[31:0]

DEST[95:64] := SRC1[63:32]

DEST[127:96] := SRC2[63:32]

DEST[159:128] := SRC1[159:128]

DEST[191:160] := SRC2[159:128]

DEST[223:192] := SRC1[191:160]

DEST[255:224] := SRC2[191:160]

DEST[MAXVL-1:256] := 0

VUNPCKLPS (VEX.128 encoded version)

DEST[31:0] := SRC1[31:0]

DEST[63:32] := SRC2[31:0]

DEST[95:64] := SRC1[63:32]

DEST[127:96] := SRC2[63:32]

DEST[MAXVL-1:128] := 0

UNPCKLPS (128-bit Legacy SSE version)

DEST[31:0] := SRC1[31:0]

DEST[63:32] := SRC2[31:0]

DEST[95:64] := SRC1[63:32]

DEST[127:96] := SRC2[63:32]

DEST[MAXVL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

VUNPCKLPS __m512 _mm512_unpacklo_ps(__m512 a, __m512 b);

VUNPCKLPS __m512 _mm512_mask_unpacklo_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);

VUNPCKLPS __m512 _mm512_maskz_unpacklo_ps(__mmask16 k, __m512 a, __m512 b);

VUNPCKLPS __m256 _mm256_unpacklo_ps (__m256 a, __m256 b);

VUNPCKLPS __m256 _mm256_mask_unpacklo_ps(__m256 s, __mmask8 k, __m256 a, __m256 b);

VUNPCKLPS __m256 _mm256_maskz_unpacklo_ps(__mmask8 k, __m256 a, __m256 b);

UNPCKLPS __m128 _mm_unpacklo_ps (__m128 a, __m128 b);

VUNPCKLPS __m128 _mm_mask_unpacklo_ps(__m128 s, __mmask8 k, __m128 a, __m128 b);

VUNPCKLPS __m128 _mm_maskz_unpacklo_ps(__mmask8 k, __m128 a, __m128 b);

SIMD Floating-Point Exceptions

None

Other Exceptions

Non-EVEX-encoded instructions, see Table 2-21, “Type 4 Class Exception Conditions”.

EVEX-encoded instructions, see Table 2-50, “Type E4NF Class Exception Conditions”.

UNPCKLPS—Unpack and Interleave Low Packed Single Precision Floating-Point Values

Vol. 2B

4-749

CHAPTER 5

INSTRUCTION SET REFERENCE, V

5.1

TERNARY BIT VECTOR LOGIC TABLE

VPTERNLOGD/VPTERNLOGQ instructions operate on dword/qword elements and take three bit vectors of the

respective input data elements to form a set of 32/64 indices, where each 3-bit value provides an index into an 8-

bit lookup table represented by the imm8 byte of the instruction. The 256 possible values of the imm8 byte is

constructed as a 16x16 boolean logic table. The 16 rows of the table uses the lower 4 bits of imm8 as row index.

The 16 columns are referenced by imm8[7:4]. The 16 columns of the table are present in two halves, with 8

columns shown in Table 5-1 for the column index value between 0:7, followed by Table 5-2 showing the 8 columns

corresponding to column index 8:15. This section presents the two-halves of the 256-entry table using a short-

hand notation representing simple or compound boolean logic expressions with three input bit source data.

The three input bit source data will be denoted with the capital letters: A, B, C; where A represents a bit from the

first source operand (also the destination operand), B and C represent a bit from the 2nd and 3rd source operands.

Each map entry takes the form of a logic expression consisting of one of more component expressions. Each

component expression consists of either a unary or binary boolean operator and associated operands. Each binary

boolean operator is expressed in lowercase letters, and operands concatenated after the logic operator. The unary

operator ‘not’ is expressed using ‘!’. Additionally, the conditional expression “A?B:C” expresses a result returning B

if A is set, returning C otherwise.

A binary boolean operator is followed by two operands, e.g., andAB. For a compound binary expression that contain

commutative components and comprising the same logic operator, the 2nd logic operator is omitted and three

operands can be concatenated in sequence, e.g., andABC. When the 2nd operand of the first binary boolean

expression comes from the result of another boolean expression, the 2nd boolean expression is concatenated after

the uppercase operand of the first logic expression, e.g., norBnandAC. When the result is independent of an

operand, that operand is omitted in the logic expression, e.g., zeros or norCB.

The 3-input expression “majorABC” returns 0 if two or more input bits are 0, returns 1 if two or more input bits are

1. The 3-input expression “minorABC” returns 1 if two or more input bits are 0, returns 0 if two or more input bits

are 1.

The building-block bit logic functions used in Table 5-1 and Table 5-2 include:

• Constants: TRUE (1), FALSE (0);

• Unary function: Not (!);

• Binary functions: and, nand, or, nor, xor, xnor;

• Conditional function: Select (?:);

• Tertiary functions: major, minor.

Vol. 2C

5-1

INSTRUCTION SET REFERENCE, V

Table 5-1. Lower 8 columns of the 16x16 Map of VPTERNLOG Boolean Logic Operations

Imm

[7:4]

[3:0]

00H

FALSE

andAnorBC

norBnandAC

andA!B

norCnandBA

andA!C

andAxorBC

andAnandBC

01H

norABC

norCB

norBxorAC

A?!B:norBC

norCxorBA

A?!C:norBC

A?xorBC:norB

A?nandBC:no

rBC

02H

andCnorBA

norBxnorAC

andC!B

norBnorAC

C?norBA:and

C?norBA:A

C?!B:andBA

C?!B:A

03H

norBA

norBandAC

C?!B:norBA

C?norBA:xnor

A?!C:!B

A?xorBC:!B

A?nandBC:!B

04H

andBnorAC

norCxnorBA

B?norAC:and

B?norAC:A

andB!C

norCnorBA

B?!C:andAC

B?!C:A

05H

norCA

norCandBA

B?norAC:xnor

A?!B:!C

B?!C:norAC

A?xorBC:!C

A?nandBC:!C

06H

norAxnorBC

A?norBC:xorB

B?norAC:C

xorBorAC

C?norBA:B

xorCorBA

xorCB

B?!C:orAC

07H

norAandBC

minorABC

C?!B:!A

nandBorAC

B?!C:!A

nandCorBA

A?xorBC:nan

nandCB

dBC

08H

norAnandBC

A?norBC:and

andCxorBA

A?!B:andBC

andBxorAC

A?!C:andBC

A?xorBC:and

xorAandBC

09H

norAxorBC

A?norBC:xnor

C?xorBA:norB

A?!B:xnorBC

B?xorAC:norA

A?!C:xnorBC

xnorABC

A?nandBC:xn

orBC

0AH

andC!A

A?norBC:C

andCnandBA

A?!B:C

C?!A:andBA

xorCA

xorCandBA

A?nandBC:C

0BH

C?!A:norBA

C?!A:!B

C?nandBA:no

C?nandBA:!B

B?xorAC:!A

B?xorAC:nan

C?nandBA:xn

nandBxnorAC

rBA

dAC

orBA

0CH

andB!A

A?norBC:B

B?!A:andAC

xorBA

andBnandAC

A?!C:B

xorBandAC

A?nandBC:B

0DH

B?!A:norAC

B?!A:!C

B?!A:xnorAC

C?xorBA:nan

B?nandAC:no

B?nandAC:!C

B?nandAC:xn

nandCxnorBA

dBA

rAC

orAC

0EH

norAnorBC

xorAorBC

B?!A:C

A?!B:orBC

C?!A:B

A?!C:orBC

B?nandAC:C

A?nandBC:or

0FH

nandAorBC

C?nandBA:!A

nandBA

B?nandAC:!A

nandCA

nandAxnorBC

nandABC

Table 5-2 shows the half of 256-entry map corresponding to column index values 8:15.

5-2

Vol. 2C

INSTRUCTION SET REFERENCE, V

Table 5-2. Upper 8 columns of the 16x16 Map of VPTERNLOG Boolean Logic Operations

Imm

[7:4]

[3:0]

08H

09H

0AH

0BH

0CH

0DH

0EH

0FH

00H

andABC

andAxnorBC

andCA

B?andAC:A

andBA

C?andBA:A

andAorBC

01H

A?andBC:nor

B?andAC:!C

A?C:norBC

C?A:!B

A?B:norBC

B?A:!C

xnorAorBC

orAnorBC

02H

andCxnorBA

B?andAC:xor

B?andAC:C

B?andAC:orA

C?xnorBA:an

B?A:xorAC

B?A:C

B?A:orAC

dBA

03H

A?andBC:!B

xnorBandAC

A?C:!B

nandBnandA

xnorBA

B?A:nandAC

A?orBC:!B

orA!B

04H

andBxnorAC

C?andBA:xor

B?xnorAC:an

B?xnorAC:A

C?andBA:B

C?andBA:orB

C?A:B

C?A:orBA

dAC

05H

A?andBC:!C

xnorCandBA

xnorCA

C?A:nandBA

A?B:!C

nandCnandB

A?orBC:!C

orA!C

06H

A?andBC:xor

xorABC

A?C:xorBC

B?xnorAC:orA

A?B:xorBC

C?xnorBA:orB

A?orBC:xorBC

orAxorBC

07H

xnorAandBC

A?xnorBC:na

A?C:nandBC

nandBxorAC

A?B:nandBC

nandCxorBA

A?orBCnandB

orAnandBC

ndBC

08H

andCB

A?xnorBC:an

andCorAB

B?C:A

andBorAC

C?B:A

majorABC

orAandBC

dBC

09H

B?C:norAC

xnorCB

xnorCorBA

C?orBA:!B

xnorBorAC

B?orAC:!C

A?orBC:xnorB

orAxnorBC

0AH

A?andBC:C

A?xnorBC:C

B?C:orAC

A?B:C

B?orAC:xorAC

orCandBA

orCA

0BH

B?C:!A

B?C:nandAC

orCnorBA

orC!B

B?orAC:!A

B?orAC:nand

orCxnorBA

nandBnorAC

0CH

A?andBC:B

A?xnorBC:B

A?C:B

C?orBA:xorBA

C?B:orBA

orBandAC

orBA

0DH

C?B!A

C?B:nandBA

C?orBA:!A

C?orBA:nand

orBnorAC

orB!C

orBxnorAC

nandCnorBA

0EH

A?andBC:orB

A?xnorBC:orB

A?C:orBC

orCxorBA

A?B:orBC

orBxorAC

orCB

orABC

0FH

nandAnandB

nandAxorBC

orC!A

orCnandBA

orB!A

orBnandAC

nandAnorBC

TRUE

Table 5-1 and Table 5-2 translate each of the possible value of the imm8 byte to a Boolean expression. These tables

can also be used by software to translate Boolean expressions to numerical constants to form the imm8 value

needed to construct the VPTERNLOG syntax. There is a unique set of three byte constants (F0H, CCH, AAH) that

can be used for this purpose as input operands in conjunction with the Boolean expressions defined in those tables.

The reverse mapping can be expressed as:

Result_imm8 = Table_Lookup_Entry( 0F0H, 0CCH, 0AAH)

Table_Lookup_Entry is the Boolean expression defined in Table 5-1 and Table 5-2.

Vol. 2C

5-3

INSTRUCTION SET REFERENCE, V

VADDPH—Add Packed FP16 Values

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

bit Mode

Flag

Support

EVEX.128.NP.MAP5.W0 58 /r

V/V

AVX512-FP16

Add packed FP16 value from xmm3/m128/

VADDPH xmm1{k1}{z}, xmm2,

AVX512VL

m16bcst to xmm2, and store result in xmm1

xmm3/m128/m16bcst

subject to writemask k1.

EVEX.256.NP.MAP5.W0 58 /r

V/V

AVX512-FP16

Add packed FP16 value from ymm3/m256/

VADDPH ymm1{k1}{z}, ymm2,

AVX512VL

m16bcst to ymm2, and store result in ymm1

ymm3/m256/m16bcst

subject to writemask k1.

EVEX.512.NP.MAP5.W0 58 /r

V/V

AVX512-FP16

Add packed FP16 value from zmm3/m512/

VADDPH zmm1{k1}{z}, zmm2, zmm3/

m16bcst to zmm2, and store result in zmm1

m512/m16bcst {er}

subject to writemask k1.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

Full

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

This instruction adds packed FP16 values from source operands and stores the packed FP16 result in the destina-

tion operand. The destination elements are updated according to the writemask.

Operation

VADDPH (EVEX encoded versions) when src2 operand is a register

VL = 128, 256 or 512

KL := VL/16

IF (VL = 512) AND (EVEX.b = 1):

SET_RM(EVEX.RC)

ELSE

SET_RM(MXCSR.RC)

FOR j := 0 TO KL-1:

IF k1[j] OR *no writemask*:

DEST.fp16[j] := SRC1.fp16[j] + SRC2.fp16[j]

ELSEIF *zeroing*:

DEST.fp16[j] := 0

// else dest.fp16[j] remains unchanged

DEST[MAXVL-1:VL] := 0

VADDPH (EVEX encoded versions) when src2 operand is a memory source

VL = 128, 256 or 512

KL := VL/16

FOR j := 0 TO KL-1:

IF k1[j] OR *no writemask*:

IF EVEX.b = 1:

DEST.fp16[j] := SRC1.fp16[j] + SRC2.fp16[0]

ELSE:

DEST.fp16[j] := SRC1.fp16[j] + SRC2.fp16[j]

ELSE IF *zeroing*:

DEST.fp16[j] := 0

// else dest.fp16[j] remains unchanged

DEST[MAXVL-1:VL] := 0

VADDPH—Add Packed FP16 Values

Vol. 2C

5-5

INSTRUCTION SET REFERENCE, V

Intel C/C++ Compiler Intrinsic Equivalent

VADDPH __m128h _mm_add_ph (__m128h a, __m128h b);

VADDPH __m128h _mm_mask_add_ph (__m128h src, __mmask8 k, __m128h a, __m128h b);

VADDPH __m128h _mm_maskz_add_ph (__mmask8 k, __m128h a, __m128h b);

VADDPH __m256h _mm256_add_ph (__m256h a, __m256h b);

VADDPH __m256h _mm256_mask_add_ph (__m256h src, __mmask16 k, __m256h a, __m256h b);

VADDPH __m256h _mm256_maskz_add_ph (__mmask16 k, __m256h a, __m256h b);

VADDPH __m512h _mm512_add_ph (__m512h a, __m512h b);

VADDPH __m512h _mm512_mask_add_ph (__m512h src, __mmask32 k, __m512h a, __m512h b);

VADDPH __m512h _mm512_maskz_add_ph (__mmask32 k, __m512h a, __m512h b);

VADDPH __m512h _mm512_add_round_ph (__m512h a, __m512h b, int rounding);

VADDPH __m512h _mm512_mask_add_round_ph (__m512h src, __mmask32 k, __m512h a, __m512h b, int rounding);

VADDPH __m512h _mm512_maskz_add_round_ph (__mmask32 k, __m512h a, __m512h b, int rounding);

SIMD Floating-Point Exceptions

Invalid, Underflow, Overflow, Precision, Denormal

Other Exceptions

EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”

5-6

Vol. 2C

VADDPH—Add Packed FP16 Values

INSTRUCTION SET REFERENCE, V

VADDSH—Add Scalar FP16 Values

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

bit Mode

Flag

Support

EVEX.LLIG.F3.MAP5.W0 58 /r

V/V

AVX512-FP16

Add the low FP16 value from xmm3/m16 to

VADDSH xmm1{k1}{z}, xmm2,

xmm2, and store the result in xmm1 subject to

xmm3/m16 {er}

writemask k1. Bits 127:16 of xmm2 are copied

to xmm1[127:16].

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

Scalar

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

This instruction adds the low FP16 value from the source operands and stores the FP16 result in the destination

operand.

Bits 127:16 of the destination operand are copied from the corresponding bits of the first source operand. Bits

MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the destination is updated according

to the writemask.

Operation

VADDSH (EVEX encoded versions)

IF EVEX.b = 1 and SRC2 is a register:

SET_RM(EVEX.RC)

ELSE

SET_RM(MXCSR.RC)

IF k1[0] OR *no writemask*:

DEST.fp16[0] := SRC1.fp16[0] + SRC2.fp16[0]

ELSEIF *zeroing*:

DEST.fp16[0] := 0

// else dest.fp16[0] remains unchanged

DEST[127:16] := SRC1[127:16]

DEST[MAXVL-1:128] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VADDSH __m128h _mm_add_round_sh (__m128h a, __m128h b, int rounding);

VADDSH ___m128h _mm_mask_add_round_sh (__m128h src, __mmask8 k, __m128h a, __m128h b, int rounding);

VADDSH ___m128h _mm_maskz_add_round_sh (__mmask8 k, __m128h a, __m128h b, int rounding);

VADDSH ___m128h _mm_add_sh (__m128h a, __m128h b);

VADDSH ___m128h _mm_mask_add_sh (__m128h src, __mmask8 k, __m128h a, __m128h b);

VADDSH ___m128h _mm_maskz_add_sh (__mmask8 k, __m128h a, __m128h b);

SIMD Floating-Point Exceptions

Invalid, Underflow, Overflow, Precision, Denormal

Other Exceptions

EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”

VADDSH—Add Scalar FP16 Values

Vol. 2C

5-7

INSTRUCTION SET REFERENCE, V

VALIGND/VALIGNQ—Align Doubleword/Quadword Vectors

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EVEX.128.66.0F3A.W0 03 /r ib

V/V

AVX512VL

Shift right and merge vectors xmm2 and

VALIGND xmm1 {k1}{z}, xmm2,

AVX512F

xmm3/m128/m32bcst with double-word granularity

xmm3/m128/m32bcst, imm8

using imm8 as number of elements to shift, and store the

final result in xmm1, under writemask.

EVEX.128.66.0F3A.W1 03 /r ib

V/V

AVX512VL

Shift right and merge vectors xmm2 and

VALIGNQ xmm1 {k1}{z}, xmm2,

AVX512F

xmm3/m128/m64bcst with quad-word granularity using

xmm3/m128/m64bcst, imm8

imm8 as number of elements to shift, and store the final

result in xmm1, under writemask.

EVEX.256.66.0F3A.W0 03 /r ib

V/V

AVX512VL

Shift right and merge vectors ymm2 and

VALIGND ymm1 {k1}{z}, ymm2,

AVX512F

ymm3/m256/m32bcst with double-word granularity

ymm3/m256/m32bcst, imm8

using imm8 as number of elements to shift, and store the

final result in ymm1, under writemask.

EVEX.256.66.0F3A.W1 03 /r ib

V/V

AVX512VL

Shift right and merge vectors ymm2 and

VALIGNQ ymm1 {k1}{z}, ymm2,

AVX512F

ymm3/m256/m64bcst with quad-word granularity using

ymm3/m256/m64bcst, imm8

imm8 as number of elements to shift, and store the final

result in ymm1, under writemask.

EVEX.512.66.0F3A.W0 03 /r ib

V/V

AVX512F

Shift right and merge vectors zmm2 and

VALIGND zmm1 {k1}{z}, zmm2,

zmm3/m512/m32bcst with double-word granularity

zmm3/m512/m32bcst, imm8

using imm8 as number of elements to shift, and store the

final result in zmm1, under writemask.

EVEX.512.66.0F3A.W1 03 /r ib

V/V

AVX512F

Shift right and merge vectors zmm2 and

VALIGNQ zmm1 {k1}{z}, zmm2,

zmm3/m512/m64bcst with quad-word granularity using

zmm3/m512/m64bcst, imm8

imm8 as number of elements to shift, and store the final

result in zmm1, under writemask.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Concatenates and shifts right doubleword/quadword elements of the first source operand (the second operand)

and the second source operand (the third operand) into a 1024/512/256-bit intermediate vector. The low

512/256/128-bit of the intermediate vector is written to the destination operand (the first operand) using the

writemask k1. The destination and first source operands are ZMM/YMM/XMM registers. The second source operand

can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted

from a 32/64-bit memory location.

This instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1

are computed and stored into zmm1. Elements in zmm1 with the corresponding bit clear in k1 retain their previous

values (merging-masking) or are set to 0 (zeroing-masking).

5-8

Vol. 2C

VALIGND/VALIGNQ—Align Doubleword/Quadword Vectors

INSTRUCTION SET REFERENCE, V

Operation

VALIGND (EVEX encoded versions)

(KL, VL) = (4, 128), (8, 256), (16, 512)

IF (SRC2 *is memory*) (AND EVEX.b = 1)

THEN

FOR j := 0 TO KL-1

i := j * 32

src[i+31:i] := SRC2[31:0]

ENDFOR;

ELSE src := SRC2

; Concatenate sources

tmp[VL-1:0] := src[VL-1:0]

tmp[2VL-1:VL] := SRC1[VL-1:0]

; Shift right doubleword elements

IF VL = 128

THEN SHIFT = imm8[1:0]

ELSE

IF VL = 256

THEN SHIFT = imm8[2:0]

ELSE SHIFT = imm8[3:0]

FI;

tmp[2VL-1:0] := tmp[2VL-1:0] >> (32*SHIFT)

; Apply writemask

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] := tmp[i+31:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

VALIGNQ (EVEX encoded versions)

(KL, VL) = (2, 128), (4, 256),(8, 512)

IF (SRC2 *is memory*) (AND EVEX.b = 1)

THEN

FOR j := 0 TO KL-1

i := j * 64

src[i+63:i] := SRC2[63:0]

ENDFOR;

ELSE src := SRC2

; Concatenate sources

tmp[VL-1:0] := src[VL-1:0]

tmp[2VL-1:VL] := SRC1[VL-1:0]

; Shift right quadword elements

VALIGND/VALIGNQ—Align Doubleword/Quadword Vectors

Vol. 2C

5-9

INSTRUCTION SET REFERENCE, V

IF VL = 128

THEN SHIFT = imm8[0]

ELSE

IF VL = 256

THEN SHIFT = imm8[1:0]

ELSE SHIFT = imm8[2:0]

FI;

tmp[2VL-1:0] := tmp[2VL-1:0] >> (64*SHIFT)

; Apply writemask

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i] := tmp[i+63:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VALIGND __m512i _mm512_alignr_epi32( __m512i a, __m512i b, int cnt);

VALIGND __m512i _mm512_mask_alignr_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b, int cnt);

VALIGND __m512i _mm512_maskz_alignr_epi32( __mmask16 k, __m512i a, __m512i b, int cnt);

VALIGND __m256i _mm256_mask_alignr_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b, int cnt);

VALIGND __m256i _mm256_maskz_alignr_epi32( __mmask8 k, __m256i a, __m256i b, int cnt);

VALIGND __m128i _mm_mask_alignr_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b, int cnt);

VALIGND __m128i _mm_maskz_alignr_epi32( __mmask8 k, __m128i a, __m128i b, int cnt);

VALIGNQ __m512i _mm512_alignr_epi64( __m512i a, __m512i b, int cnt);

VALIGNQ __m512i _mm512_mask_alignr_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b, int cnt);

VALIGNQ __m512i _mm512_maskz_alignr_epi64( __mmask8 k, __m512i a, __m512i b, int cnt);

VALIGNQ __m256i _mm256_mask_alignr_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b, int cnt);

VALIGNQ __m256i _mm256_maskz_alignr_epi64( __mmask8 k, __m256i a, __m256i b, int cnt);

VALIGNQ __m128i _mm_mask_alignr_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b, int cnt);

VALIGNQ __m128i _mm_maskz_alignr_epi64( __mmask8 k, __m128i a, __m128i b, int cnt);

Exceptions

See Table 2-50, “Type E4NF Class Exception Conditions.”

5-10

Vol. 2C

VALIGND/VALIGNQ—Align Doubleword/Quadword Vectors

INSTRUCTION SET REFERENCE, V

VBLENDMPD/VBLENDMPS—Blend Float64/Float32 Vectors Using an OpMask Control

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EVEX.128.66.0F38.W1 65 /r

V/V

AVX512VL

Blend double precision vector xmm2 and double precision

VBLENDMPD xmm1 {k1}{z},

AVX512F

vector xmm3/m128/m64bcst and store the result in xmm1,

xmm2, xmm3/m128/m64bcst

under control mask.

EVEX.256.66.0F38.W1 65 /r

V/V

AVX512VL

Blend double precision vector ymm2 and double precision

VBLENDMPD ymm1 {k1}{z},

AVX512F

vector ymm3/m256/m64bcst and store the result in ymm1,

ymm2, ymm3/m256/m64bcst

under control mask.

EVEX.512.66.0F38.W1 65 /r

V/V

AVX512F

Blend double precision vector zmm2 and double precision

VBLENDMPD zmm1 {k1}{z},

vector zmm3/m512/m64bcst and store the result in zmm1,

zmm2, zmm3/m512/m64bcst

under control mask.

EVEX.128.66.0F38.W0 65 /r

V/V

AVX512VL

Blend single precision vector xmm2 and single precision

VBLENDMPS xmm1 {k1}{z},

AVX512F

vector xmm3/m128/m32bcst and store the result in xmm1,

xmm2, xmm3/m128/m32bcst

under control mask.

EVEX.256.66.0F38.W0 65 /r

V/V

AVX512VL

Blend single precision vector ymm2 and single precision

VBLENDMPS ymm1 {k1}{z},

AVX512F

vector ymm3/m256/m32bcst and store the result in ymm1,

ymm2, ymm3/m256/m32bcst

under control mask.

EVEX.512.66.0F38.W0 65 /r

V/V

AVX512F

Blend single precision vector zmm2 and single precision

VBLENDMPS zmm1 {k1}{z},

vector zmm3/m512/m32bcst using k1 as select control and

zmm2, zmm3/m512/m32bcst

store the result in zmm1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs an element-by-element blending between float64/float32 elements in the first source operand (the

second operand) with the elements in the second source operand (the third operand) using an opmask register as

select control. The blended result is written to the destination register.

The destination and first source operands are ZMM/YMM/XMM registers. The second source operand can be a

ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-

bit memory location.

The opmask register is not used as a writemask for this instruction. Instead, the mask is used as an element

selector: every element of the destination is conditionally selected between first source or second source using the

value of the related mask bit (0 for first source operand, 1 for second source operand).

If EVEX.z is set, the elements with corresponding mask bit value of 0 in the destination operand are zeroed.

Operation

VBLENDMPD (EVEX encoded versions)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no controlmask*

THEN

IF (EVEX.b = 1) AND (SRC2 *is memory*)

THEN

DEST[i+63:i] := SRC2[63:0]

ELSE

DEST[i+63:i] := SRC2[i+63:i]

FI;

VBLENDMPD/VBLENDMPS—Blend Float64/Float32 Vectors Using an OpMask Control

Vol. 2C

5-11

INSTRUCTION SET REFERENCE, V

ELSE

IF *merging-masking*

; merging-masking

THEN DEST[i+63:i] := SRC1[i+63:i]

ELSE

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VBLENDMPS (EVEX encoded versions)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no controlmask*

THEN

IF (EVEX.b = 1) AND (SRC2 *is memory*)

THEN

DEST[i+31:i] := SRC2[31:0]

ELSE

DEST[i+31:i] := SRC2[i+31:i]

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN DEST[i+31:i] := SRC1[i+31:i]

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VBLENDMPD __m512d _mm512_mask_blend_pd(__mmask8 k, __m512d a, __m512d b);

VBLENDMPD __m256d _mm256_mask_blend_pd(__mmask8 k, __m256d a, __m256d b);

VBLENDMPD __m128d _mm_mask_blend_pd(__mmask8 k, __m128d a, __m128d b);

VBLENDMPS __m512 _mm512_mask_blend_ps(__mmask16 k, __m512 a, __m512 b);

VBLENDMPS __m256 _mm256_mask_blend_ps(__mmask8 k, __m256 a, __m256 b);

VBLENDMPS __m128 _mm_mask_blend_ps(__mmask8 k, __m128 a, __m128 b);

SIMD Floating-Point Exceptions

None

Other Exceptions

See Table 2-49, “Type E4 Class Exception Conditions.”

5-12

Vol. 2C

VBLENDMPD/VBLENDMPS—Blend Float64/Float32 Vectors Using an OpMask Control

INSTRUCTION SET REFERENCE, V

VBROADCAST—Load with Broadcast Floating-Point Data

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit

Feature

Mode

Flag

Support

VEX.128.66.0F38.W0 18 /r

V/V

AVX

Broadcast single precision floating-point element in

VBROADCASTSS xmm1, m32

mem to four locations in xmm1.

VEX.256.66.0F38.W0 18 /r

V/V

AVX

Broadcast single precision floating-point element in

VBROADCASTSS ymm1, m32

mem to eight locations in ymm1.

VEX.256.66.0F38.W0 19 /r

V/V

AVX

Broadcast double precision floating-point element in

VBROADCASTSD ymm1, m64

mem to four locations in ymm1.

VEX.256.66.0F38.W0 1A /r

V/V

AVX

Broadcast 128 bits of floating-point data in mem to

VBROADCASTF128 ymm1, m128

low and high 128-bits in ymm1.

VEX.128.66.0F38.W0 18/r

V/V

AVX2

Broadcast the low single precision floating-point

element in the source operand to four locations in

VBROADCASTSS xmm1, xmm2

xmm1.

VEX.256.66.0F38.W0 18 /r

V/V

AVX2

Broadcast low single precision floating-point element

in the source operand to eight locations in ymm1.

VBROADCASTSS ymm1, xmm2

VEX.256.66.0F38.W0 19 /r

V/V

AVX2

Broadcast low double precision floating-point element

in the source operand to four locations in ymm1.

VBROADCASTSD ymm1, xmm2

EVEX.256.66.0F38.W1 19 /r

V/V

AVX512VL

Broadcast low double precision floating-point element

VBROADCASTSD ymm1 {k1}{z},

AVX512F

in xmm2/m64 to four locations in ymm1 using

xmm2/m64

writemask k1.

EVEX.512.66.0F38.W1 19 /r

V/V

AVX512F

Broadcast low double precision floating-point element

VBROADCASTSD zmm1 {k1}{z},

in xmm2/m64 to eight locations in zmm1 using

xmm2/m64

writemask k1.

EVEX.256.66.0F38.W0 19 /r

V/V

AVX512VL

Broadcast two single precision floating-point elements

VBROADCASTF32X2 ymm1 {k1}{z},

AVX512DQ

in xmm2/m64 to locations in ymm1 using writemask

xmm2/m64

k1.

EVEX.512.66.0F38.W0 19 /r

V/V

AVX512DQ

Broadcast two single precision floating-point elements

VBROADCASTF32X2 zmm1 {k1}{z},

in xmm2/m64 to locations in zmm1 using writemask

xmm2/m64

k1.

EVEX.128.66.0F38.W0 18 /r

V/V

AVX512VL

Broadcast low single precision floating-point element

VBROADCASTSS xmm1 {k1}{z},

AVX512F

in xmm2/m32 to all locations in xmm1 using

xmm2/m32

writemask k1.

EVEX.256.66.0F38.W0 18 /r

V/V

AVX512VL

Broadcast low single precision floating-point element

VBROADCASTSS ymm1 {k1}{z},

AVX512F

in xmm2/m32 to all locations in ymm1 using

xmm2/m32

writemask k1.

EVEX.512.66.0F38.W0 18 /r

V/V

AVX512F

Broadcast low single precision floating-point element

VBROADCASTSS zmm1 {k1}{z},

in xmm2/m32 to all locations in zmm1 using

xmm2/m32

writemask k1.

EVEX.256.66.0F38.W0 1A /r

V/V

AVX512VL

Broadcast 128 bits of 4 single precision floating-point

VBROADCASTF32X4 ymm1 {k1}{z},

AVX512F

data in mem to locations in ymm1 using writemask k1.

m128

EVEX.512.66.0F38.W0 1A /r

V/V

AVX512F

Broadcast 128 bits of 4 single precision floating-point

VBROADCASTF32X4 zmm1 {k1}{z},

data in mem to locations in zmm1 using writemask k1.

m128

EVEX.256.66.0F38.W1 1A /r

V/V

AVX512VL

Broadcast 128 bits of 2 double precision floating-point

VBROADCASTF64X2 ymm1 {k1}{z},

AVX512DQ

data in mem to locations in ymm1 using writemask k1.

m128

VBROADCAST—Load with Broadcast Floating-Point Data

Vol. 2C

5-13

INSTRUCTION SET REFERENCE, V

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit

Feature

Mode

Flag

Support

EVEX.512.66.0F38.W1 1A /r

V/V

AVX512DQ

Broadcast 128 bits of 2 double precision floating-point

VBROADCASTF64X2 zmm1 {k1}{z},

data in mem to locations in zmm1 using writemask k1.

m128

EVEX.512.66.0F38.W0 1B /r

V/V

AVX512DQ

Broadcast 256 bits of 8 single precision floating-point

VBROADCASTF32X8 zmm1 {k1}{z},

data in mem to locations in zmm1 using writemask k1.

m256

EVEX.512.66.0F38.W1 1B /r

V/V

AVX512F

Broadcast 256 bits of 4 double precision floating-point

VBROADCASTF64X4 zmm1 {k1}{z},

data in mem to locations in zmm1 using writemask k1.

m256

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

Tuple1 Scalar

ModRM:reg (w)

ModRM:r/m (r)

N/A

Tuple2

ModRM:reg (w)

ModRM:r/m (r)

N/A

Tuple4

ModRM:reg (w)

ModRM:r/m (r)

N/A

Tuple8

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

VBROADCASTSD/VBROADCASTSS/VBROADCASTF128 load floating-point values as one tuple from the source

operand (second operand) in memory and broadcast to all elements of the destination operand (first operand).

VEX256-encoded versions: The destination operand is a YMM register. The source operand is either a 32-bit, 64-bit,

or 128-bit memory location. Register source encodings are reserved and will #UD. Bits (MAXVL-1:256) of the desti-

nation register are zeroed.

EVEX-encoded versions: The destination operand is a ZMM/YMM/XMM register and updated according to the

writemask k1. The source operand is either a 32-bit, 64-bit memory location or the low doubleword/quadword

element of an XMM register.

VBROADCASTF32X2/VBROADCASTF32X4/VBROADCASTF64X2/VBROADCASTF32X8/VBROADCASTF64X4 load

floating-point values as tuples from the source operand (the second operand) in memory or register and broadcast

to all elements of the destination operand (the first operand). The destination operand is a YMM/ZMM register

updated according to the writemask k1. The source operand is either a register or 64-bit/128-bit/256-bit memory

location.

VBROADCASTSD and VBROADCASTF128,F32x4 and F64x2 are only supported as 256-bit and 512-bit wide

versions and up. VBROADCASTSS is supported in 128-bit, 256-bit and 512-bit wide versions. F32x8 and F64x4 are

only supported as 512-bit wide versions.

VBROADCASTF32X2/VBROADCASTF32X4/VBROADCASTF32X8 have 32-bit granularity. VBROADCASTF64X2 and

VBROADCASTF64X4 have 64-bit granularity.

Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.

If VBROADCASTSD or VBROADCASTF128 is encoded with VEX.L= 0, an attempt to execute the instruction encoded

with VEX.L= 0 will cause an #UD exception.

5-14

Vol. 2C

VBROADCAST—Load with Broadcast Floating-Point Data

INSTRUCTION SET REFERENCE, V

m256

DEST

Figure 5-5. VBROADCASTF64X4 Operation (512-bit version with writemask all 1s)

Operation

VBROADCASTSS (128 bit version VEX and legacy)

temp := SRC[31:0]

DEST[31:0] := temp

DEST[63:32] := temp

DEST[95:64] := temp

DEST[127:96] := temp

DEST[MAXVL-1:128] := 0

VBROADCASTSS (VEX.256 encoded version)

temp := SRC[31:0]

DEST[31:0] := temp

DEST[63:32] := temp

DEST[95:64] := temp

DEST[127:96] := temp

DEST[159:128] := temp

DEST[191:160] := temp

DEST[223:192] := temp

DEST[255:224] := temp

DEST[MAXVL-1:256] := 0

VBROADCASTSS (EVEX encoded versions)

(KL, VL) (4, 128), (8, 256),= (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] := SRC[31:0]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

5-16

Vol. 2C

VBROADCAST—Load with Broadcast Floating-Point Data

INSTRUCTION SET REFERENCE, V

VBROADCASTSD (VEX.256 encoded version)

temp := SRC[63:0]

DEST[63:0] := temp

DEST[127:64] := temp

DEST[191:128] := temp

DEST[255:192] := temp

DEST[MAXVL-1:256] := 0

VBROADCASTSD (EVEX encoded versions)

(KL, VL) = (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i] := SRC[63:0]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VBROADCASTF32x2 (EVEX encoded versions)

(KL, VL) = (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

n := (j mod 2) * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] := SRC[n+31:n]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VBROADCASTF128 (VEX.256 encoded version)

temp := SRC[127:0]

DEST[127:0] := temp

DEST[255:128] := temp

DEST[MAXVL-1:256] := 0

VBROADCAST—Load with Broadcast Floating-Point Data

Vol. 2C

5-17

INSTRUCTION SET REFERENCE, V

VBROADCASTF32X4 (EVEX encoded versions)

(KL, VL) = (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j* 32

n := (j modulo 4) * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] := SRC[n+31:n]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VBROADCASTF64X2 (EVEX encoded versions)

(KL, VL) = (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

n := (j modulo 2) * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i] := SRC[n+63:n]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] = 0

FI;

ENDFOR;

VBROADCASTF32X8 (EVEX.U1.512 encoded version)

FOR j := 0 TO 15

i := j * 32

n := (j modulo 8) * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] := SRC[n+31:n]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

5-18

Vol. 2C

VBROADCAST—Load with Broadcast Floating-Point Data

INSTRUCTION SET REFERENCE, V

VBROADCASTF64X4 (EVEX.512 encoded version)

FOR j := 0 TO 7

i := j * 64

n := (j modulo 4) * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i] := SRC[n+63:n]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VBROADCASTF32x2 __m512 _mm512_broadcast_f32x2( __m128 a);

VBROADCASTF32x2 __m512 _mm512_mask_broadcast_f32x2(__m512 s, __mmask16 k, __m128 a);

VBROADCASTF32x2 __m512 _mm512_maskz_broadcast_f32x2( __mmask16 k, __m128 a);

VBROADCASTF32x2 __m256 _mm256_broadcast_f32x2( __m128 a);

VBROADCASTF32x2 __m256 _mm256_mask_broadcast_f32x2(__m256 s, __mmask8 k, __m128 a);

VBROADCASTF32x2 __m256 _mm256_maskz_broadcast_f32x2( __mmask8 k, __m128 a);

VBROADCASTF32x4 __m512 _mm512_broadcast_f32x4( __m128 a);

VBROADCASTF32x4 __m512 _mm512_mask_broadcast_f32x4(__m512 s, __mmask16 k, __m128 a);

VBROADCASTF32x4 __m512 _mm512_maskz_broadcast_f32x4( __mmask16 k, __m128 a);

VBROADCASTF32x4 __m256 _mm256_broadcast_f32x4( __m128 a);

VBROADCASTF32x4 __m256 _mm256_mask_broadcast_f32x4(__m256 s, __mmask8 k, __m128 a);

VBROADCASTF32x4 __m256 _mm256_maskz_broadcast_f32x4( __mmask8 k, __m128 a);

VBROADCASTF32x8 __m512 _mm512_broadcast_f32x8( __m256 a);

VBROADCASTF32x8 __m512 _mm512_mask_broadcast_f32x8(__m512 s, __mmask16 k, __m256 a);

VBROADCASTF32x8 __m512 _mm512_maskz_broadcast_f32x8( __mmask16 k, __m256 a);

VBROADCASTF64x2 __m512d _mm512_broadcast_f64x2( __m128d a);

VBROADCASTF64x2 __m512d _mm512_mask_broadcast_f64x2(__m512d s, __mmask8 k, __m128d a);

VBROADCASTF64x2 __m512d _mm512_maskz_broadcast_f64x2( __mmask8 k, __m128d a);

VBROADCASTF64x2 __m256d _mm256_broadcast_f64x2( __m128d a);

VBROADCASTF64x2 __m256d _mm256_mask_broadcast_f64x2(__m256d s, __mmask8 k, __m128d a);

VBROADCASTF64x2 __m256d _mm256_maskz_broadcast_f64x2( __mmask8 k, __m128d a);

VBROADCASTF64x4 __m512d _mm512_broadcast_f64x4( __m256d a);

VBROADCASTF64x4 __m512d _mm512_mask_broadcast_f64x4(__m512d s, __mmask8 k, __m256d a);

VBROADCASTF64x4 __m512d _mm512_maskz_broadcast_f64x4( __mmask8 k, __m256d a);

VBROADCASTSD __m512d _mm512_broadcastsd_pd( __m128d a);

VBROADCASTSD __m512d _mm512_mask_broadcastsd_pd(__m512d s, __mmask8 k, __m128d a);

VBROADCASTSD __m512d _mm512_maskz_broadcastsd_pd(__mmask8 k, __m128d a);

VBROADCASTSD __m256d _mm256_broadcastsd_pd(__m128d a);

VBROADCASTSD __m256d _mm256_mask_broadcastsd_pd(__m256d s, __mmask8 k, __m128d a);

VBROADCASTSD __m256d _mm256_maskz_broadcastsd_pd( __mmask8 k, __m128d a);

VBROADCASTSD __m256d _mm256_broadcast_sd(double *a);

VBROADCASTSS __m512 _mm512_broadcastss_ps( __m128 a);

VBROADCASTSS __m512 _mm512_mask_broadcastss_ps(__m512 s, __mmask16 k, __m128 a);

VBROADCASTSS __m512 _mm512_maskz_broadcastss_ps( __mmask16 k, __m128 a);

VBROADCASTSS __m256 _mm256_broadcastss_ps(__m128 a);

VBROADCASTSS __m256 _mm256_mask_broadcastss_ps(__m256 s, __mmask8 k, __m128 a);

VBROADCASTSS __m256 _mm256_maskz_broadcastss_ps( __mmask8 k, __m128 a);

VBROADCAST—Load with Broadcast Floating-Point Data

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5-19

INSTRUCTION SET REFERENCE, V

VBROADCASTSS __m128 _mm_broadcastss_ps(__m128 a);

VBROADCASTSS __m128 _mm_mask_broadcastss_ps(__m128 s, __mmask8 k, __m128 a);

VBROADCASTSS __m128 _mm_maskz_broadcastss_ps( __mmask8 k, __m128 a);

VBROADCASTSS __m128 _mm_broadcast_ss(float *a);

VBROADCASTSS __m256 _mm256_broadcast_ss(float *a);

VBROADCASTF128 __m256 _mm256_broadcast_ps(__m128 * a);

VBROADCASTF128 __m256d _mm256_broadcast_pd(__m128d * a);

Exceptions

VEX-encoded instructions, see Table 2-23, “Type 6 Class Exception Conditions.”

EVEX-encoded instructions, see Table 2-53, “Type E6 Class Exception Conditions.”

Additionally:

#UD

If VEX.L = 0 for VBROADCASTSD or VBROADCASTF128.

If EVEX.L’L = 0 for VBROADCASTSD/VBROADCASTF32X2/VBROADCASTF32X4/VBROADCASTF64X2.

If EVEX.L’L < 10b for VBROADCASTF32X8/VBROADCASTF64X4.

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Vol. 2C

VBROADCAST—Load with Broadcast Floating-Point Data

INSTRUCTION SET REFERENCE, V

VCMPPH—Compare Packed FP16 Values

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

bit Mode

Flag

Support

EVEX.128.NP.0F3A.W0 C2 /r /ib

V/V

AVX512-FP16

Compare packed FP16 values in xmm3/m128/

VCMPPH k1{k2}, xmm2, xmm3/

AVX512VL

m16bcst and xmm2 using bits 4:0 of imm8 as a

m128/m16bcst, imm8

comparison predicate subject to writemask k2, and

store the result in mask register k1.

EVEX.256.NP.0F3A.W0 C2 /r /ib

V/V

AVX512-FP16

Compare packed FP16 values in ymm3/m256/

VCMPPH k1{k2}, ymm2, ymm3/

AVX512VL

m16bcst and ymm2 using bits 4:0 of imm8 as a

m256/m16bcst, imm8

comparison predicate subject to writemask k2, and

store the result in mask register k1.

EVEX.512.NP.0F3A.W0 C2 /r /ib

V/V

AVX512-FP16

Compare packed FP16 values in zmm3/m512/

VCMPPH k1{k2}, zmm2, zmm3/

m16bcst and zmm2 using bits 4:0 of imm8 as a

m512/m16bcst {sae}, imm8

comparison predicate subject to writemask k2, and

store the result in mask register k1.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

Full

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

imm8 (r)

Description

This instruction compares packed FP16 values from source operands and stores the result in the destination mask

operand. The comparison predicate operand (immediate byte bits 4:0) specifies the type of comparison performed

on each of the pairs of packed values. The destination elements are updated according to the writemask.

Operation

CASE (imm8 & 0x1F) OF

0: CMP_OPERATOR := EQ_OQ;

1: CMP_OPERATOR := LT_OS;

2: CMP_OPERATOR := LE_OS;

3: CMP_OPERATOR := UNORD_Q;

4: CMP_OPERATOR := NEQ_UQ;

5: CMP_OPERATOR := NLT_US;

6: CMP_OPERATOR := NLE_US;

7: CMP_OPERATOR := ORD_Q;

8: CMP_OPERATOR := EQ_UQ;

9: CMP_OPERATOR := NGE_US;

10: CMP_OPERATOR := NGT_US;

11: CMP_OPERATOR := FALSE_OQ;

12: CMP_OPERATOR := NEQ_OQ;

13: CMP_OPERATOR := GE_OS;

14: CMP_OPERATOR := GT_OS;

15: CMP_OPERATOR := TRUE_UQ;

16: CMP_OPERATOR := EQ_OS;

17: CMP_OPERATOR := LT_OQ;

18: CMP_OPERATOR := LE_OQ;

19: CMP_OPERATOR := UNORD_S;

20: CMP_OPERATOR := NEQ_US;

21: CMP_OPERATOR := NLT_UQ;

22: CMP_OPERATOR := NLE_UQ;

23: CMP_OPERATOR := ORD_S;

VCMPPH—Compare Packed FP16 Values

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INSTRUCTION SET REFERENCE, V

24: CMP_OPERATOR := EQ_US;

25: CMP_OPERATOR := NGE_UQ;

26: CMP_OPERATOR := NGT_UQ;

27: CMP_OPERATOR := FALSE_OS;

28: CMP_OPERATOR := NEQ_OS;

29: CMP_OPERATOR := GE_OQ;

30: CMP_OPERATOR := GT_OQ;

31: CMP_OPERATOR := TRUE_US;

ESAC

VCMPPH (EVEX encoded versions)

VL = 128, 256 or 512

KL := VL/16

FOR j := 0 TO KL-1:

IF k2[j] OR *no writemask*:

IF EVEX.b = 1:

tsrc2 := SRC2.fp16[0]

ELSE:

tsrc2 := SRC2.fp16[j]

DEST.bit[j] := SRC1.fp16[j] CMP_OPERATOR tsrc2

ELSE

DEST.bit[j] := 0

DEST[MAXKL-1:KL] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VCMPPH ___mmask8 _mm_cmp_ph_mask (__m128h a, __m128h b, const int imm8);

VCMPPH ___mmask8 _mm_mask_cmp_ph_mask (__mmask8 k1, __m128h a, __m128h b, const int imm8);

VCMPPH ___mmask16 _mm256_cmp_ph_mask (__m256h a, __m256h b, const int imm8);

VCMPPH ___mmask16 _mm256_mask_cmp_ph_mask (__mmask16 k1, __m256h a, __m256h b, const int imm8);

VCMPPH ___mmask32 _mm512_cmp_ph_mask (__m512h a, __m512h b, const int imm8);

VCMPPH ___mmask32 _mm512_mask_cmp_ph_mask (__mmask32 k1, __m512h a, __m512h b, const int imm8);

VCMPPH ___mmask32 _mm512_cmp_round_ph_mask (__m512h a, __m512h b, const int imm8, const int sae);

VCMPPH ___mmask32 _mm512_mask_cmp_round_ph_mask (__mmask32 k1, __m512h a, __m512h b, const int imm8, const int sae);

SIMD Floating-Point Exceptions

Invalid, Denormal

Other Exceptions

EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”

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Vol. 2C

VCMPPH—Compare Packed FP16 Values

INSTRUCTION SET REFERENCE, V

VCMPSH—Compare Scalar FP16 Values

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

bit Mode

Flag

Support

EVEX.LLIG.F3.0F3A.W0 C2 /r /ib

V/V

AVX512-FP16

Compare low FP16 values in xmm3/m16 and

VCMPSH k1{k2}, xmm2, xmm3/m16

xmm2 using bits 4:0 of imm8 as a comparison

{sae}, imm8

predicate subject to writemask k2, and store the

result in mask register k1.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

Scalar

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

imm8 (r)

Description

This instruction compares the FP16 values from the lowest element of the source operands and stores the result in

the destination mask operand. The comparison predicate operand (immediate byte bits 4:0) specifies the type of

comparison performed on the pair of packed FP16 values. The low destination bit is updated according to the

writemask. Bits MAXKL-1:1 of the destination operand are zeroed.

Operation

CASE (imm8 & 0x1F) OF

0: CMP_OPERATOR := EQ_OQ;

1: CMP_OPERATOR := LT_OS;

2: CMP_OPERATOR := LE_OS;

3: CMP_OPERATOR := UNORD_Q;

4: CMP_OPERATOR := NEQ_UQ;

5: CMP_OPERATOR := NLT_US;

6: CMP_OPERATOR := NLE_US;

7: CMP_OPERATOR := ORD_Q;

8: CMP_OPERATOR := EQ_UQ;

9: CMP_OPERATOR := NGE_US;

10: CMP_OPERATOR := NGT_US;

11: CMP_OPERATOR := FALSE_OQ;

12: CMP_OPERATOR := NEQ_OQ;

13: CMP_OPERATOR := GE_OS;

14: CMP_OPERATOR := GT_OS;

15: CMP_OPERATOR := TRUE_UQ;

16: CMP_OPERATOR := EQ_OS;

17: CMP_OPERATOR := LT_OQ;

18: CMP_OPERATOR := LE_OQ;

19: CMP_OPERATOR := UNORD_S;

20: CMP_OPERATOR := NEQ_US;

21: CMP_OPERATOR := NLT_UQ;

22: CMP_OPERATOR := NLE_UQ;

23: CMP_OPERATOR := ORD_S;

24: CMP_OPERATOR := EQ_US;

25: CMP_OPERATOR := NGE_UQ;

26: CMP_OPERATOR := NGT_UQ;

27: CMP_OPERATOR := FALSE_OS;

28: CMP_OPERATOR := NEQ_OS;

29: CMP_OPERATOR := GE_OQ;

30: CMP_OPERATOR := GT_OQ;

VCMPSH—Compare Scalar FP16 Values

Vol. 2C

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INSTRUCTION SET REFERENCE, V

31: CMP_OPERATOR := TRUE_US;

ESAC

VCMPSH (EVEX encoded versions)

IF k2[0] OR *no writemask*:

DEST.bit[0] := SRC1.fp16[0] CMP_OPERATOR SRC2.fp16[0]

ELSE

DEST.bit[0] := 0

DEST[MAXKL-1:1] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VCMPSH __mmask8 _mm_cmp_round_sh_mask (__m128h a, __m128h b, const int imm8, const int sae);

VCMPSH __mmask8 _mm_mask_cmp_round_sh_mask (__mmask8 k1, __m128h a, __m128h b, const int imm8, const int sae);

VCMPSH __mmask8 _mm_cmp_sh_mask (__m128h a, __m128h b, const int imm8);

VCMPSH __mmask8 _mm_mask_cmp_sh_mask (__mmask8 k1, __m128h a, __m128h b, const int imm8);

SIMD Floating-Point Exceptions

Invalid, Denormal

Other Exceptions

EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”

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VCMPSH—Compare Scalar FP16 Values

INSTRUCTION SET REFERENCE, V

VCOMISH—Compare Scalar Ordered FP16 Values and Set EFLAGS

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

bit Mode

Flag

Support

EVEX.LLIG.NP.MAP5.W0 2F /r

V/V

AVX512-FP16

Compare low FP16 values in xmm1 and xmm2/

VCOMISH xmm1, xmm2/m16 {sae}

m16, and set the EFLAGS flags accordingly.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

Scalar

ModRM:reg (r)

ModRM:r/m (r)

N/A

Description

This instruction compares the FP16 values in the low word of operand 1 (first operand) and operand 2 (second

operand), and sets the ZF, PF, and CF flags in the EFLAGS register according to the result (unordered, greater than,

less than, or equal). The OF, SF and AF flags in the EFLAGS register are set to 0. The unordered result is returned

if either source operand is a NaN (QNaN or SNaN).

Operand 1 is an XMM register; operand 2 can be an XMM register or a 16-bit memory location.

The VCOMISH instruction differs from the VUCOMISH instruction in that it signals a SIMD floating-point invalid oper-

ation exception (#I) when a source operand is either a QNaN or SNaN. The VUCOMISH instruction signals an invalid

numeric exception only if a source operand is an SNaN.

The EFLAGS register is not updated if an unmasked SIMD floating-point exception is generated. EVEX.vvvv is

reserved and must be 1111b, otherwise instructions will #UD.

Operation

VCOMISH src1, src2

RESULT := OrderedCompare(SRC1.fp16[0],SRC2.fp16[0])

IF RESULT is UNORDERED:

ZF, PF, CF := 1, 1, 1

ELSE IF RESULT is GREATER_THAN:

ZF, PF, CF := 0, 0, 0

ELSE IF RESULT is LESS_THAN:

ZF, PF, CF := 0, 0, 1

ELSE: // RESULT is EQUALS

ZF, PF, CF := 1, 0, 0

OF, AF, SF := 0, 0, 0

Intel C/C++ Compiler Intrinsic Equivalent

VCOMISH int _mm_comi_round_sh (__m128h a, __m128h b, const int imm8, const int sae);

VCOMISH int _mm_comi_sh (__m128h a, __m128h b, const int imm8);

VCOMISH int _mm_comieq_sh (__m128h a, __m128h b);

VCOMISH int _mm_comige_sh (__m128h a, __m128h b);

VCOMISH int _mm_comigt_sh (__m128h a, __m128h b);

VCOMISH int _mm_comile_sh (__m128h a, __m128h b);

VCOMISH int _mm_comilt_sh (__m128h a, __m128h b);

VCOMISH int _mm_comineq_sh (__m128h a, __m128h b);

SIMD Floating-Point Exceptions

Invalid, Denormal

VCOMISH—Compare Scalar Ordered FP16 Values and Set EFLAGS

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Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 92