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Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 90

INSTRUCTION SET REFERENCE, M-U

SHA1NEXTE—Calculate SHA1 State Variable E After Four Rounds

Opcode/

Op/En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

NP 0F 38 C8 /r

RM

V/V

SHA

Calculates SHA1 state variable E after four rounds of operation

SHA1NEXTE xmm1,

from the current SHA1 state variable A in xmm1. The calculated

xmm2/m128

value of the SHA1 state variable E is added to the scheduled

dwords in xmm2/m128, and stored with some of the scheduled

dwords in xmm1.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

RM

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

Description

The SHA1NEXTE calculates the SHA1 state variable E after four rounds of operation from the current SHA1 state

variable A in the destination operand. The calculated value of the SHA1 state variable E is added to the source

operand, which contains the scheduled dwords.

Operation

SHA1NEXTE

TMP := (SRC1[127:96] ROL 30);

DEST[127:96] := SRC2[127:96] + TMP;

DEST[95:64] := SRC2[95:64];

DEST[63:32] := SRC2[63:32];

DEST[31:0] := SRC2[31:0];

Intel C/C++ Compiler Intrinsic Equivalent

SHA1NEXTE: __m128i _mm_sha1nexte_epu32(__m128i, __m128i);

Flags Affected

None

SIMD Floating-Point Exceptions

None

Other Exceptions

See Table 2-21, “Type 4 Class Exception Conditions”.

4-628

Vol. 2B

SHA1NEXTE—Calculate SHA1 State Variable E After Four Rounds

INSTRUCTION SET REFERENCE, M-U

SHA1MSG1—Perform an Intermediate Calculation for the Next Four SHA1 Message Dwords

Opcode/

Op/En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

NP 0F 38 C9 /r

RM

V/V

SHA

Performs an intermediate calculation for the next four SHA1

SHA1MSG1 xmm1,

message dwords using previous message dwords from xmm1 and

xmm2/m128

xmm2/m128, storing the result in xmm1.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

RM

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

Description

The SHA1MSG1 instruction is one of two SHA1 message scheduling instructions. The instruction performs an inter-

mediate calculation for the next four SHA1 message dwords.

Operation

SHA1MSG1

W0 := SRC1[127:96] ;

W1 := SRC1[95:64] ;

W2 := SRC1[63: 32] ;

W3 := SRC1[31: 0] ;

W4 := SRC2[127:96] ;

W5 := SRC2[95:64] ;

DEST[127:96] := W2 XOR W0;

DEST[95:64] := W3 XOR W1;

DEST[63:32] := W4 XOR W2;

DEST[31:0] := W5 XOR W3;

Intel C/C++ Compiler Intrinsic Equivalent

SHA1MSG1: __m128i _mm_sha1msg1_epu32(__m128i, __m128i);

Flags Affected

None

SIMD Floating-Point Exceptions

None

Other Exceptions

See Table 2-21, “Type 4 Class Exception Conditions”.

SHA1MSG1—Perform an Intermediate Calculation for the Next Four SHA1 Message Dwords

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4-629

INSTRUCTION SET REFERENCE, M-U

SHA1MSG2—Perform a Final Calculation for the Next Four SHA1 Message Dwords

Opcode/

Op/En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

NP 0F 38 CA /r

RM

V/V

SHA

Performs the final calculation for the next four SHA1 message

SHA1MSG2 xmm1,

dwords using intermediate results from xmm1 and the previous

xmm2/m128

message dwords from xmm2/m128, storing the result in xmm1.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

RM

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

Description

The SHA1MSG2 instruction is one of two SHA1 message scheduling instructions. The instruction performs the final

calculation to derive the next four SHA1 message dwords.

Operation

SHA1MSG2

W13 := SRC2[95:64] ;

W14 := SRC2[63: 32] ;

W15 := SRC2[31: 0] ;

W16 := (SRC1[127:96] XOR W13 ) ROL 1;

W17 := (SRC1[95:64] XOR W14) ROL 1;

W18 := (SRC1[63: 32] XOR W15) ROL 1;

W19 := (SRC1[31: 0] XOR W16) ROL 1;

DEST[127:96] := W16;

DEST[95:64] := W17;

DEST[63:32] := W18;

DEST[31:0] := W19;

Intel C/C++ Compiler Intrinsic Equivalent

SHA1MSG2: __m128i _mm_sha1msg2_epu32(__m128i, __m128i);

Flags Affected

None

SIMD Floating-Point Exceptions

None

Other Exceptions

See Table 2-21, “Type 4 Class Exception Conditions”.

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Vol. 2B

SHA1MSG2—Perform a Final Calculation for the Next Four SHA1 Message Dwords

INSTRUCTION SET REFERENCE, M-U

SHA256RNDS2—Perform Two Rounds of SHA256 Operation

Opcode/

Op/En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

NP 0F 38 CB /r

RMI

V/V

SHA

Perform 2 rounds of SHA256 operation using an initial SHA256

SHA256RNDS2 xmm1,

state (C,D,G,H) from xmm1, an initial SHA256 state (A,B,E,F) from

xmm2/m128, <XMM0>

xmm2/m128, and a pre-computed sum of the next 2 round mes-

sage dwords and the corresponding round constants from the

implicit operand XMM0, storing the updated SHA256 state

(A,B,E,F) result in xmm1.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

RMI

ModRM:reg (r, w)

ModRM:r/m (r)

Implicit XMM0 (r)

Description

The SHA256RNDS2 instruction performs 2 rounds of SHA256 operation using an initial SHA256 state (C,D,G,H)

from the first operand, an initial SHA256 state (A,B,E,F) from the second operand, and a pre-computed sum of the

next 2 round message dwords and the corresponding round constants from the implicit operand xmm0. Note that

only the two lower dwords of XMM0 are used by the instruction.

The updated SHA256 state (A,B,E,F) is written to the first operand, and the second operand can be used as the

updated state (C,D,G,H) in later rounds.

Operation

SHA256RNDS2

A_0 := SRC2[127:96];

B_0 := SRC2[95:64];

C_0 := SRC1[127:96];

D_0 := SRC1[95:64];

E_0 := SRC2[63:32];

F_0 := SRC2[31:0];

G_0 := SRC1[63:32];

H_0 := SRC1[31:0];

WK₀ := XMM0[31: 0];

WK₁ := XMM0[63: 32];

FOR i = 0 to 1

A_(i +1) := Ch (E_i, F_i, G_i) +Σ₁( E_i) +WK_i+ H_i + Maj(A_i , B_i, C_i) +Σ₀( A_i);

B_(i +1) := A_i;

C_(i +1) := B_i ;

D_(i +1) := C_i;

E_(i +1) := Ch (E_i, F_i, G_i) +Σ₁( E_i) +WK_i+ H_i + D_i;

F_(i +1) := E_i ;

G_(i +1) := F_i;

H_(i +1) := G_i;

ENDFOR

DEST[127:96] := A_2;

DEST[95:64] := B_2;

DEST[63:32] := E_2;

DEST[31:0] := F_2;

SHA256RNDS2—Perform Two Rounds of SHA256 Operation

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4-631

INSTRUCTION SET REFERENCE, M-U

SHA256MSG1—Perform an Intermediate Calculation for the Next Four SHA256 Message

Dwords

Opcode/

Op/En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

NP 0F 38 CC /r

RM

V/V

SHA

Performs an intermediate calculation for the next four SHA256

SHA256MSG1 xmm1,

message dwords using previous message dwords from xmm1 and

xmm2/m128

xmm2/m128, storing the result in xmm1.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

RM

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

Description

The SHA256MSG1 instruction is one of two SHA256 message scheduling instructions. The instruction performs an

intermediate calculation for the next four SHA256 message dwords.

Operation

SHA256MSG1

W4 := SRC2[31: 0] ;

W3 := SRC1[127:96] ;

W2 := SRC1[95:64] ;

W1 := SRC1[63: 32] ;

W0 := SRC1[31: 0] ;

DEST[127:96] := W3 + σ₀( W4);

DEST[95:64] := W2 + σ₀( W3);

DEST[63:32] := W1 + σ₀( W2);

DEST[31:0] := W0 + σ₀( W1);

Intel C/C++ Compiler Intrinsic Equivalent

SHA256MSG1: __m128i _mm_sha256msg1_epu32(__m128i, __m128i);

Flags Affected

None

SIMD Floating-Point Exceptions

None

Other Exceptions

See Table 2-21, “Type 4 Class Exception Conditions”.

SHA256MSG1—Perform an Intermediate Calculation for the Next Four SHA256 Message Dwords

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4-633

INSTRUCTION SET REFERENCE, M-U

SHA256MSG2—Perform a Final Calculation for the Next Four SHA256 Message Dwords

Opcode/

Op/En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

NP 0F 38 CD /r

RM

V/V

SHA

Performs the final calculation for the next four SHA256 message

SHA256MSG2 xmm1,

dwords using previous message dwords from xmm1 and

xmm2/m128

xmm2/m128, storing the result in xmm1.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

RM

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

Description

The SHA256MSG2 instruction is one of two SHA2 message scheduling instructions. The instruction performs the

final calculation for the next four SHA256 message dwords.

Operation

SHA256MSG2

W14 := SRC2[95:64] ;

W15 := SRC2[127:96] ;

W16 := SRC1[31: 0] + σ₁( W14) ;

W17 := SRC1[63: 32] + σ₁( W15) ;

W18 := SRC1[95: 64] + σ₁( W16) ;

W19 := SRC1[127: 96] + σ₁( W17) ;

DEST[127:96] := W19 ;

DEST[95:64] := W18 ;

DEST[63:32] := W17 ;

DEST[31:0] := W16;

Intel C/C++ Compiler Intrinsic Equivalent

SHA256MSG2 : __m128i _mm_sha256msg2_epu32(__m128i, __m128i);

Flags Affected

None

SIMD Floating-Point Exceptions

None

Other Exceptions

See Table 2-21, “Type 4 Class Exception Conditions”.

4-634

Vol. 2B

SHA256MSG2—Perform a Final Calculation for the Next Four SHA256 Message Dwords

INSTRUCTION SET REFERENCE, M-U

SHLD—Double Precision Shift Left

Opcode*

Instruction

Op/

64-Bit

Compat/

Description

En

Mode

Leg Mode

0F A4 /r ib

SHLD r/m16, r16, imm8

MRI

Valid

Valid

Shift r/m16 to left imm8 places while shifting

bits from r16 in from the right.

0F A5 /r

SHLD r/m16, r16, CL

MRC

Valid

Valid

Shift r/m16 to left CL places while shifting bits

from r16 in from the right.

0F A4 /r ib

SHLD r/m32, r32, imm8

MRI

Valid

Valid

Shift r/m32 to left imm8 places while shifting

bits from r32 in from the right.

REX.W + 0F A4 /r ib

SHLD r/m64, r64, imm8

MRI

Valid

N.E.

Shift r/m64 to left imm8 places while shifting

bits from r64 in from the right.

0F A5 /r

SHLD r/m32, r32, CL

MRC

Valid

Valid

Shift r/m32 to left CL places while shifting bits

from r32 in from the right.

REX.W + 0F A5 /r

SHLD r/m64, r64, CL

MRC

Valid

N.E.

Shift r/m64 to left CL places while shifting bits

from r64 in from the right.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

MRI

ModRM:r/m (w)

ModRM:reg (r)

imm8

N/A

MRC

ModRM:r/m (w)

ModRM:reg (r)

CL

N/A

Description

The SHLD instruction is used for multi-precision shifts of 64 bits or more.

The instruction shifts the first operand (destination operand) to the left the number of bits specified by the third

operand (count operand). The second operand (source operand) provides bits to shift in from the right (starting

with bit 0 of the destination operand).

The destination operand can be a register or a memory location; the source operand is a register. The count

operand is an unsigned integer that can be stored in an immediate byte or in the CL register. If the count operand

is CL, the shift count is the logical AND of CL and a count mask. In non-64-bit modes and default 64-bit mode; only

bits 0 through 4 of the count are used. This masks the count to a value between 0 and 31. If a count is greater than

the operand size, the result is undefined.

If the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand. For a 1-bit

shift, the OF flag is set if a sign change occurred; otherwise, it is cleared. If the count operand is 0, flags are not

affected.

In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits

access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits

(upgrading the count mask to 6 bits). See the summary chart at the beginning of this section for encoding data and

limits.

SHLD—Double Precision Shift Left

Vol. 2B

4-635

INSTRUCTION SET REFERENCE, M-U

SHRD—Double Precision Shift Right

Opcode*

Instruction

Op/

64-Bit

Compat/

Description

En

Mode

Leg Mode

0F AC /r ib

SHRD r/m16, r16, imm8

MRI

Valid

Valid

Shift r/m16 to right imm8 places while

shifting bits from r16 in from the left.

0F AD /r

SHRD r/m16, r16, CL

MRC

Valid

Valid

Shift r/m16 to right CL places while shifting

bits from r16 in from the left.

0F AC /r ib

SHRD r/m32, r32, imm8

MRI

Valid

Valid

Shift r/m32 to right imm8 places while

shifting bits from r32 in from the left.

REX.W + 0F AC /r ib

SHRD r/m64, r64, imm8

MRI

Valid

N.E.

Shift r/m64 to right imm8 places while

shifting bits from r64 in from the left.

0F AD /r

SHRD r/m32, r32, CL

MRC

Valid

Valid

Shift r/m32 to right CL places while shifting

bits from r32 in from the left.

REX.W + 0F AD /r

SHRD r/m64, r64, CL

MRC

Valid

N.E.

Shift r/m64 to right CL places while shifting

bits from r64 in from the left.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

MRI

ModRM:r/m (w)

ModRM:reg (r)

imm8

N/A

MRC

ModRM:r/m (w)

ModRM:reg (r)

CL

N/A

Description

The SHRD instruction is useful for multi-precision shifts of 64 bits or more.

The instruction shifts the first operand (destination operand) to the right the number of bits specified by the third

operand (count operand). The second operand (source operand) provides bits to shift in from the left (starting with

the most significant bit of the destination operand).

The destination operand can be a register or a memory location; the source operand is a register. The count

operand is an unsigned integer that can be stored in an immediate byte or the CL register. If the count operand is

CL, the shift count is the logical AND of CL and a count mask. In non-64-bit modes and default 64-bit mode, the

width of the count mask is 5 bits. Only bits 0 through 4 of the count register are used (masking the count to a value

between 0 and 31). If the count is greater than the operand size, the result is undefined.

If the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand. For a 1-bit

shift, the OF flag is set if a sign change occurred; otherwise, it is cleared. If the count operand is 0, flags are not

affected.

In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits

access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits

(upgrading the count mask to 6 bits). See the summary chart at the beginning of this section for encoding data and

limits.

4-638

Vol. 2B

SHRD—Double Precision Shift Right

INSTRUCTION SET REFERENCE, M-U

SHUFPD—Packed Interleave Shuffle of Pairs of Double Precision Floating-Point Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

66 0F C6 /r ib

A

V/V

SSE2

Shuffle two pairs of double precision floating-point

SHUFPD xmm1, xmm2/m128, imm8

values from xmm1 and xmm2/m128 using imm8 to

select from each pair, interleaved result is stored in

xmm1.

VEX.128.66.0F.WIG C6 /r ib

B

V/V

AVX

Shuffle two pairs of double precision floating-point

VSHUFPD xmm1, xmm2, xmm3/m128,

values from xmm2 and xmm3/m128 using imm8 to

imm8

select from each pair, interleaved result is stored in

xmm1.

VEX.256.66.0F.WIG C6 /r ib

B

V/V

AVX

Shuffle four pairs of double precision floating-point

VSHUFPD ymm1, ymm2, ymm3/m256,

values from ymm2 and ymm3/m256 using imm8 to

imm8

select from each pair, interleaved result is stored in

xmm1.

EVEX.128.66.0F.W1 C6 /r ib

C

V/V

AVX512VL

Shuffle two paris of double precision floating-point

VSHUFPD xmm1{k1}{z}, xmm2,

AVX512F

values from xmm2 and xmm3/m128/m64bcst using

xmm3/m128/m64bcst, imm8

imm8 to select from each pair. store interleaved

results in xmm1 subject to writemask k1.

EVEX.256.66.0F.W1 C6 /r ib

C

V/V

AVX512VL

Shuffle four paris of double precision floating-point

VSHUFPD ymm1{k1}{z}, ymm2,

AVX512F

values from ymm2 and ymm3/m256/m64bcst using

ymm3/m256/m64bcst, imm8

imm8 to select from each pair. store interleaved

results in ymm1 subject to writemask k1.

EVEX.512.66.0F.W1 C6 /r ib

C

V/V

AVX512F

Shuffle eight paris of double precision floating-point

VSHUFPD zmm1{k1}{z}, zmm2,

values from zmm2 and zmm3/m512/m64bcst using

zmm3/m512/m64bcst, imm8

imm8 to select from each pair. store interleaved

results in zmm1 subject to writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

imm8

N/A

B

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

imm8

C

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

imm8

Description

Selects a double precision floating-point value of an input pair using a bit control and move to a designated element

of the destination operand. The low-to-high order of double precision element of the destination operand is inter-

leaved between the first source operand and the second source operand at the granularity of input pair of 128 bits.

Each bit in the imm8 byte, starting from bit 0, is the select control of the corresponding element of the destination

to received the shuffled result of an input pair.

EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be

a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a

64-bit memory location The destination operand is a ZMM/YMM/XMM register updated according to the writemask.

The select controls are the lower 8/4/2 bits of the imm8 byte.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM

register or a 256-bit memory location. The destination operand is a YMM register. The select controls are the bit 3:0

of the imm8 byte, imm8[7:4) are ignored.

VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM

register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAXVL-1:128) of

the corresponding ZMM register destination are zeroed. The select controls are the bit 1:0 of the imm8 byte,

imm8[7:2) are ignored.

SHUFPD—Packed Interleave Shuffle of Pairs of Double Precision Floating-Point Values

Vol. 2B

4-641

INSTRUCTION SET REFERENCE, M-U

128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-

nation operand and the first source operand is the same and is an XMM register. The upper bits (MAXVL-1:128) of

the corresponding ZMM register destination are unmodified. The select controls are the bit 1:0 of the imm8 byte,

imm8[7:2) are ignored.

SRC1

X3

X2

X1

X0

SRC2

Y3

Y2

Y1

Y0

DEST

Y2 or Y3

X2 or X3

Y0 or Y1

X0 or X1

Figure 4-25. 256-bit VSHUFPD Operation of Four Pairs of Double Precision Floating-Point Values

Operation

VSHUFPD (EVEX encoded versions when SRC2 is a vector register)

(KL, VL) = (2, 128), (4, 256), (8, 512)

IF IMM0[0] = 0

THEN TMP_DEST[63:0] := SRC1[63:0]

ELSE TMP_DEST[63:0] := SRC1[127:64] FI;

IF IMM0[1] = 0

THEN TMP_DEST[127:64] := SRC2[63:0]

ELSE TMP_DEST[127:64] := SRC2[127:64] FI;

IF VL >= 256

IF IMM0[2] = 0

THEN TMP_DEST[191:128] := SRC1[191:128]

ELSE TMP_DEST[191:128] := SRC1[255:192] FI;

IF IMM0[3] = 0

THEN TMP_DEST[255:192] := SRC2[191:128]

ELSE TMP_DEST[255:192] := SRC2[255:192] FI;

FI;

IF VL >= 512

IF IMM0[4] = 0

THEN TMP_DEST[319:256] := SRC1[319:256]

ELSE TMP_DEST[319:256] := SRC1[383:320] FI;

IF IMM0[5] = 0

THEN TMP_DEST[383:320] := SRC2[319:256]

ELSE TMP_DEST[383:320] := SRC2[383:320] FI;

IF IMM0[6] = 0

THEN TMP_DEST[447:384] := SRC1[447:384]

ELSE TMP_DEST[447:384] := SRC1[511:448] FI;

IF IMM0[7] = 0

THEN TMP_DEST[511:448] := SRC2[447:384]

ELSE TMP_DEST[511:448] := SRC2[511:448] FI;

FI;

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i] := TMP_DEST[i+63:i]

ELSE

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Vol. 2B

SHUFPD—Packed Interleave Shuffle of Pairs of Double Precision Floating-Point Values

INSTRUCTION SET REFERENCE, M-U

SHUFPS—Packed Interleave Shuffle of Quadruplets of Single Precision Floating-Point Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

NP 0F C6 /r ib

A

V/V

SSE

Select from quadruplet of single precision floating-

SHUFPS xmm1, xmm3/m128, imm8

point values in xmm1 and xmm2/m128 using imm8,

interleaved result pairs are stored in xmm1.

VEX.128.0F.WIG C6 /r ib

B

V/V

AVX

Select from quadruplet of single precision floating-

VSHUFPS xmm1, xmm2,

point values in xmm1 and xmm2/m128 using imm8,

xmm3/m128, imm8

interleaved result pairs are stored in xmm1.

VEX.256.0F.WIG C6 /r ib

B

V/V

AVX

Select from quadruplet of single precision floating-

VSHUFPS ymm1, ymm2,

point values in ymm2 and ymm3/m256 using imm8,

ymm3/m256, imm8

interleaved result pairs are stored in ymm1.

EVEX.128.0F.W0 C6 /r ib

C

V/V

AVX512VL

Select from quadruplet of single precision floating-

VSHUFPS xmm1{k1}{z}, xmm2,

AVX512F

point values in xmm1 and xmm2/m128 using imm8,

xmm3/m128/m32bcst, imm8

interleaved result pairs are stored in xmm1, subject to

writemask k1.

EVEX.256.0F.W0 C6 /r ib

C

V/V

AVX512VL

Select from quadruplet of single precision floating-

VSHUFPS ymm1{k1}{z}, ymm2,

AVX512F

point values in ymm2 and ymm3/m256 using imm8,

ymm3/m256/m32bcst, imm8

interleaved result pairs are stored in ymm1, subject to

writemask k1.

EVEX.512.0F.W0 C6 /r ib

C

V/V

AVX512F

Select from quadruplet of single precision floating-

VSHUFPS zmm1{k1}{z}, zmm2,

point values in zmm2 and zmm3/m512 using imm8,

zmm3/m512/m32bcst, imm8

interleaved result pairs are stored in zmm1, subject to

writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

imm8

N/A

B

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

imm8

C

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

imm8

Description

Selects a single precision floating-point value of an input quadruplet using a two-bit control and move to a desig-

nated element of the destination operand. Each 64-bit element-pair of a 128-bit lane of the destination operand is

interleaved between the corresponding lane of the first source operand and the second source operand at the gran-

ularity 128 bits. Each two bits in the imm8 byte, starting from bit 0, is the select control of the corresponding

element of a 128-bit lane of the destination to received the shuffled result of an input quadruplet. The two lower

elements of a 128-bit lane in the destination receives shuffle results from the quadruple of the first source operand.

The next two elements of the destination receives shuffle results from the quadruple of the second source operand.

EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be

a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a

32-bit memory location. The destination operand is a ZMM/YMM/XMM register updated according to the writemask.

imm8[7:0] provides 4 select controls for each applicable 128-bit lane of the destination.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM

register or a 256-bit memory location. The destination operand is a YMM register. Imm8[7:0] provides 4 select

controls for the high and low 128-bit of the destination.

VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM

register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAXVL-1:128) of

the corresponding ZMM register destination are zeroed. Imm8[7:0] provides 4 select controls for each element of

the destination.

4-646

Vol. 2B

SHUFPS—Packed Interleave Shuffle of Quadruplets of Single Precision Floating-Point Values

INSTRUCTION SET REFERENCE, M-U

128-bit Legacy SSE version: The source can be an XMM register or an 128-bit memory location. The destination is

not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding ZMM

register destination are unmodified. Imm8[7:0] provides 4 select controls for each element of the destination.

SRC1

X7

X6

X5

X4

X3

X2

X1

X0

SRC2

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

DEST

Y7 .. Y4

Y7 .. Y4

X7 .. X4

X7 .. X4

Y3 ..Y0

Y3 ..Y0

X3 .. X0

X3 .. X0

Figure 4-26. 256-bit VSHUFPS Operation of Selection from Input Quadruplet and Pair-wise Interleaved Result

Operation

Select4(SRC, control) {

CASE (control[1:0]) OF

0: TMP := SRC[31:0];

1: TMP := SRC[63:32];

2: TMP := SRC[95:64];

3: TMP := SRC[127:96];

ESAC;

RETURN TMP

}

VPSHUFPS (EVEX encoded versions when SRC2 is a vector register)

(KL, VL) = (4, 128), (8, 256), (16, 512)

TMP_DEST[31:0] := Select4(SRC1[127:0], imm8[1:0]);

TMP_DEST[63:32] := Select4(SRC1[127:0], imm8[3:2]);

TMP_DEST[95:64] := Select4(SRC2[127:0], imm8[5:4]);

TMP_DEST[127:96] := Select4(SRC2[127:0], imm8[7:6]);

IF VL >= 256

TMP_DEST[159:128] := Select4(SRC1[255:128], imm8[1:0]);

TMP_DEST[191:160] := Select4(SRC1[255:128], imm8[3:2]);

TMP_DEST[223:192] := Select4(SRC2[255:128], imm8[5:4]);

TMP_DEST[255:224] := Select4(SRC2[255:128], imm8[7:6]);

FI;

IF VL >= 512

TMP_DEST[287:256] := Select4(SRC1[383:256], imm8[1:0]);

TMP_DEST[319:288] := Select4(SRC1[383:256], imm8[3:2]);

TMP_DEST[351:320] := Select4(SRC2[383:256], imm8[5:4]);

TMP_DEST[383:352] := Select4(SRC2[383:256], imm8[7:6]);

TMP_DEST[415:384] := Select4(SRC1[511:384], imm8[1:0]);

TMP_DEST[447:416] := Select4(SRC1[511:384], imm8[3:2]);

TMP_DEST[479:448] := Select4(SRC2[511:384], imm8[5:4]);

TMP_DEST[511:480] := Select4(SRC2[511:384], imm8[7:6]);

FI;

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

SHUFPS—Packed Interleave Shuffle of Quadruplets of Single Precision Floating-Point Values

Vol. 2B

4-647

INSTRUCTION SET REFERENCE, M-U

SIDT—Store Interrupt Descriptor Table Register

Opcode¹

Instruction

Op/

64-Bit

Compat/

Description

En

Mode

Leg Mode

0F 01 /1

SIDT m

M

Valid

Valid

Store IDTR to m.

NOTES:

1. See the IA-32 Architecture Compatibility section below.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

M

ModRM:r/m (w)

N/A

N/A

N/A

Description

Stores the content the interrupt descriptor table register (IDTR) in the destination operand. The destination

operand specifies a 6-byte memory location.

In non-64-bit modes, the 16-bit limit field of the register is stored in the low 2 bytes of the memory location and

the 32-bit base address is stored in the high 4 bytes.

In 64-bit mode, the operand size fixed at 8+2 bytes. The instruction stores 8-byte base and 2-byte limit values.

SIDT is only useful in operating-system software; however, it can be used in application programs without causing

an exception to be generated if CR4.UMIP = 0. See “LGDT/LIDT—Load Global/Interrupt Descriptor Table Register”

in Chapter 3, Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A, for information on

loading the GDTR and IDTR.

IA-32 Architecture Compatibility

The 16-bit form of SIDT is compatible with the Intel 286 processor if the upper 8 bits are not referenced. The Intel

286 processor fills these bits with 1s; processor generations later than the Intel 286 processor fill these bits with

0s.

Operation

IF instruction is SIDT

THEN

IF OperandSize =16 or OperandSize = 32 (* Legacy or Compatibility Mode *)

THEN

DEST[0:15] := IDTR(Limit);

DEST[16:47] := IDTR(Base); FI; (* Full 32-bit base address stored *)

ELSE (* 64-bit Mode *)

DEST[0:15] := IDTR(Limit);

DEST[16:79] := IDTR(Base); (* Full 64-bit base address stored *)

FI;

FI;

Flags Affected

None.

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SIDT—Store Interrupt Descriptor Table Register

INSTRUCTION SET REFERENCE, M-U

SLDT—Store Local Descriptor Table Register

Opcode*

Instruction

Op/

64-Bit

Compat/

Description

En

Mode

Leg Mode

0F 00 /0

SLDT r/m16

M

Valid

Valid

Stores segment selector from LDTR in r/m16.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

M

ModRM:r/m (w)

N/A

N/A

N/A

Description

Stores the segment selector from the local descriptor table register (LDTR) in the destination operand. The desti-

nation operand can be a general-purpose register or a memory location. The segment selector stored with this

instruction points to the segment descriptor (located in the GDT) for the current LDT. This instruction can only be

executed in protected mode.

Outside IA-32e mode, when the destination operand is a 32-bit register, the 16-bit segment selector is copied into

the low-order 16 bits of the register. The high-order 16 bits of the register are cleared for the Pentium 4, Intel Xeon,

and P6 family processors. They are undefined for Pentium, Intel486, and Intel386 processors. When the destina-

tion operand is a memory location, the segment selector is written to memory as a 16-bit quantity, regardless of

the operand size.

In compatibility mode, when the destination operand is a 32-bit register, the 16-bit segment selector is copied into

the low-order 16 bits of the register. The high-order 16 bits of the register are cleared. When the destination

operand is a memory location, the segment selector is written to memory as a 16-bit quantity, regardless of the

operand size.

In 64-bit mode, using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). The

behavior of SLDT with a 64-bit register is to zero-extend the 16-bit selector and store it in the register. If the desti-

nation is memory and operand size is 64, SLDT will write the 16-bit selector to memory as a 16-bit quantity,

regardless of the operand size.

Operation

DEST := LDTR(SegmentSelector);

Flags Affected

None.

Protected Mode Exceptions

#GP(0)

If the destination is located in a non-writable segment.

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment

selector.

If CR4.UMIP = 1 and CPL > 0.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while CPL = 3.

#UD

If the LOCK prefix is used.

Real-Address Mode Exceptions

#UD

The SLDT instruction is not recognized in real-address mode.

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SLDT—Store Local Descriptor Table Register

INSTRUCTION SET REFERENCE, M-U

SMSW—Store Machine Status Word

Opcode*

Instruction

Op/

64-Bit

Compat/

Description

En

Mode

Leg Mode

0F 01 /4

SMSW r/m16

M

Valid

Valid

Store machine status word to r/m16.

0F 01 /4

SMSW r32/m16

M

Valid

Valid

Store machine status word in low-order 16

bits of r32/m16; high-order 16 bits of r32 are

undefined.

REX.W + 0F 01 /4

SMSW r64/m16

M

Valid

Valid

Store machine status word in low-order 16

bits of r64/m16; high-order 16 bits of r32 are

undefined.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

M

ModRM:r/m (w)

N/A

N/A

N/A

Description

Stores the machine status word (bits 0 through 15 of control register CR0) into the destination operand. The desti-

nation operand can be a general-purpose register or a memory location.

In non-64-bit modes, when the destination operand is a 32-bit register, the low-order 16 bits of register CR0 are

copied into the low-order 16 bits of the register and the high-order 16 bits are undefined. When the destination

operand is a memory location, the low-order 16 bits of register CR0 are written to memory as a 16-bit quantity,

regardless of the operand size.

In 64-bit mode, the behavior of the SMSW instruction is defined by the following examples:

• SMSW r16 operand size 16, store CR0[15:0] in r16

• SMSW r32 operand size 32, zero-extend CR0[31:0], and store in r32

• SMSW r64 operand size 64, zero-extend CR0[63:0], and store in r64

• SMSW m16 operand size 16, store CR0[15:0] in m16

• SMSW m16 operand size 32, store CR0[15:0] in m16 (not m32)

• SMSW m16 operands size 64, store CR0[15:0] in m16 (not m64)

SMSW is only useful in operating-system software. However, it is not a privileged instruction and can be used in

application programs if CR4.UMIP = 0. It is provided for compatibility with the Intel 286 processor. Programs and

procedures intended to run on IA-32 and Intel 64 processors beginning with the Intel386 processors should use the

MOV CR instruction to load the machine status word.

See “Changes to Instruction Behavior in VMX Non-Root Operation” in Chapter 26 of the Intel® 64 and IA-32 Archi-

tectures Software Developer’s Manual, Volume 3C, for more information about the behavior of this instruction in

VMX non-root operation.

Operation

DEST := CR0[15:0];

(* Machine status word *)

Flags Affected

None.

4-654

Vol. 2B

SMSW—Store Machine Status Word

INSTRUCTION SET REFERENCE, M-U

SQRTPD—Square Root of Double Precision Floating-Point Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

66 0F 51 /r

A

V/V

SSE2

Computes Square Roots of the packed double precision

SQRTPD xmm1, xmm2/m128

floating-point values in xmm2/m128 and stores the result

in xmm1.

VEX.128.66.0F.WIG 51 /r

A

V/V

AVX

Computes Square Roots of the packed double precision

VSQRTPD xmm1, xmm2/m128

floating-point values in xmm2/m128 and stores the result

in xmm1.

VEX.256.66.0F.WIG 51 /r

A

V/V

AVX

Computes Square Roots of the packed double precision

VSQRTPD ymm1, ymm2/m256

floating-point values in ymm2/m256 and stores the result

in ymm1.

EVEX.128.66.0F.W1 51 /r

B

V/V

AVX512VL

Computes Square Roots of the packed double precision

VSQRTPD xmm1 {k1}{z},

AVX512F

floating-point values in xmm2/m128/m64bcst and stores

xmm2/m128/m64bcst

the result in xmm1 subject to writemask k1.

EVEX.256.66.0F.W1 51 /r

B

V/V

AVX512VL

Computes Square Roots of the packed double precision

VSQRTPD ymm1 {k1}{z},

AVX512F

floating-point values in ymm2/m256/m64bcst and stores

ymm2/m256/m64bcst

the result in ymm1 subject to writemask k1.

EVEX.512.66.0F.W1 51 /r

B

V/V

AVX512F

Computes Square Roots of the packed double precision

VSQRTPD zmm1 {k1}{z},

floating-point values in zmm2/m512/m64bcst and stores

zmm2/m512/m64bcst{er}

the result in zmm1 subject to writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

B

Full

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

Description

Performs a SIMD computation of the square roots of the two, four or eight packed double precision floating-point

values in the source operand (the second operand) stores the packed double precision floating-point results in the

destination operand (the first operand).

EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or

a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a

ZMM/YMM/XMM register updated according to the writemask.

VEX.256 encoded version: The source operand is a YMM register or a 256-bit memory location. The destination

operand is a YMM register. The upper bits (MAXVL-1:256) of the corresponding ZMM register destination are

zeroed.

VEX.128 encoded version: the source operand second source operand or a 128-bit memory location. The destina-

tion operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are

zeroed.

128-bit Legacy SSE version: The second source can be an XMM register or 128-bit memory location. The destina-

tion is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding ZMM

register destination are unmodified.

Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.

4-656

Vol. 2B

SQRTPD—Square Root of Double Precision Floating-Point Values

INSTRUCTION SET REFERENCE, M-U

SQRTPS—Square Root of Single Precision Floating-Point Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

NP 0F 51 /r

A

V/V

SSE

Computes Square Roots of the packed single precision

SQRTPS xmm1, xmm2/m128

floating-point values in xmm2/m128 and stores the result in

xmm1.

VEX.128.0F.WIG 51 /r

A

V/V

AVX

Computes Square Roots of the packed single precision

VSQRTPS xmm1, xmm2/m128

floating-point values in xmm2/m128 and stores the result in

xmm1.

VEX.256.0F.WIG 51/r

A

V/V

AVX

Computes Square Roots of the packed single precision

VSQRTPS ymm1, ymm2/m256

floating-point values in ymm2/m256 and stores the result in

ymm1.

EVEX.128.0F.W0 51 /r

B

V/V

AVX512VL

Computes Square Roots of the packed single precision

VSQRTPS xmm1 {k1}{z},

AVX512F

floating-point values in xmm2/m128/m32bcst and stores

xmm2/m128/m32bcst

the result in xmm1 subject to writemask k1.

EVEX.256.0F.W0 51 /r

B

V/V

AVX512VL

Computes Square Roots of the packed single precision

VSQRTPS ymm1 {k1}{z},

AVX512F

floating-point values in ymm2/m256/m32bcst and stores

ymm2/m256/m32bcst

the result in ymm1 subject to writemask k1.

EVEX.512.0F.W0 51/r

B

V/V

AVX512F

Computes Square Roots of the packed single precision

VSQRTPS zmm1 {k1}{z},

floating-point values in zmm2/m512/m32bcst and stores

zmm2/m512/m32bcst{er}

the result in zmm1 subject to writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

B

Full

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

Description

Performs a SIMD computation of the square roots of the four, eight or sixteen packed single precision floating-point

values in the source operand (second operand) stores the packed single precision floating-point results in the desti-

nation operand.

EVEX.512 encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location

or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a

ZMM/YMM/XMM register updated according to the writemask.

VEX.256 encoded version: The source operand is a YMM register or a 256-bit memory location. The destination

operand is a YMM register. The upper bits (MAXVL-1:256) of the corresponding ZMM register destination are

zeroed.

VEX.128 encoded version: the source operand second source operand or a 128-bit memory location. The destina-

tion operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are

zeroed.

128-bit Legacy SSE version: The second source can be an XMM register or 128-bit memory location. The destina-

tion is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding ZMM

register destination are unmodified.

Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.

SQRTPS—Square Root of Single Precision Floating-Point Values

Vol. 2B

4-659

INSTRUCTION SET REFERENCE, M-U

SQRTSD—Compute Square Root of Scalar Double Precision Floating-Point Value

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

F2 0F 51/r

A

V/V

SSE2

Computes square root of the low double precision floating-

SQRTSD xmm1,xmm2/m64

point value in xmm2/m64 and stores the results in xmm1.

VEX.LIG.F2.0F.WIG 51/r

B

V/V

AVX

Computes square root of the low double precision floating-

VSQRTSD xmm1,xmm2,

point value in xmm3/m64 and stores the results in xmm1.

xmm3/m64

Also, upper double precision floating-point value

(bits[127:64]) from xmm2 is copied to xmm1[127:64].

EVEX.LLIG.F2.0F.W1 51/r

C

V/V

AVX512F

Computes square root of the low double precision floating-

VSQRTSD xmm1 {k1}{z}, xmm2,

point value in xmm3/m64 and stores the results in xmm1

xmm3/m64{er}

under writemask k1. Also, upper double precision floating-

point value (bits[127:64]) from xmm2 is copied to

xmm1[127:64].

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

B

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

C

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Computes the square root of the low double precision floating-point value in the second source operand and stores

the double precision floating-point result in the destination operand. The second source operand can be an XMM

register or a 64-bit memory location. The first source and destination operands are XMM registers.

128-bit Legacy SSE version: The first source operand and the destination operand are the same. The quadword at

bits 127:64 of the destination operand remains unchanged. Bits (MAXVL-1:64) of the corresponding destination

register remain unchanged.

VEX.128 and EVEX encoded versions: Bits 127:64 of the destination operand are copied from the corresponding

bits of the first source operand. Bits (MAXVL-1:128) of the destination register are zeroed.

EVEX encoded version: The low quadword element of the destination operand is updated according to the

writemask.

Software should ensure VSQRTSD is encoded with VEX.L=0. Encoding VSQRTSD with VEX.L=1 may encounter

unpredictable behavior across different processor generations.

4-662

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SQRTSD—Compute Square Root of Scalar Double Precision Floating-Point Value

INSTRUCTION SET REFERENCE, M-U

SQRTSS—Compute Square Root of Scalar Single Precision Value

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

F3 0F 51 /r

A

V/V

SSE

Computes square root of the low single precision floating-point

SQRTSS xmm1, xmm2/m32

value in xmm2/m32 and stores the results in xmm1.

VEX.LIG.F3.0F.WIG 51 /r

B

V/V

AVX

Computes square root of the low single precision floating-point

VSQRTSS xmm1, xmm2,

value in xmm3/m32 and stores the results in xmm1. Also,

xmm3/m32

upper single precision floating-point values (bits[127:32]) from

xmm2 are copied to xmm1[127:32].

EVEX.LLIG.F3.0F.W0 51 /r

C

V/V

AVX512F

Computes square root of the low single precision floating-point

VSQRTSS xmm1 {k1}{z}, xmm2,

value in xmm3/m32 and stores the results in xmm1 under

xmm3/m32{er}

writemask k1. Also, upper single precision floating-point values

(bits[127:32]) from xmm2 are copied to xmm1[127:32].

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

B

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

C

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Computes the square root of the low single precision floating-point value in the second source operand and stores

the single precision floating-point result in the destination operand. The second source operand can be an XMM

register or a 32-bit memory location. The first source and destination operands is an XMM register.

128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAXVL-

1:32) of the corresponding YMM destination register remain unchanged.

VEX.128 and EVEX encoded versions: Bits 127:32 of the destination operand are copied from the corresponding

bits of the first source operand. Bits (MAXVL-1:128) of the destination ZMM register are zeroed.

EVEX encoded version: The low doubleword element of the destination operand is updated according to the

writemask.

Software should ensure VSQRTSS is encoded with VEX.L=0. Encoding VSQRTSS with VEX.L=1 may encounter

unpredictable behavior across different processor generations.

4-664

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SQRTSS—Compute Square Root of Scalar Single Precision Value

INSTRUCTION SET REFERENCE, M-U

STAC—Set AC Flag in EFLAGS Register

Opcode/

Op /

64/32 bit

CPUID

Description

Instruction

En

Mode

Feature

Support

Flag

NP 0F 01 CB

ZO

V/V

SMAP

Set the AC flag in the EFLAGS register.

STAC

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ZO

N/A

N/A

N/A

N/A

Description

Sets the AC flag bit in EFLAGS register. This may enable alignment checking of user-mode data accesses. This

allows explicit supervisor-mode data accesses to user-mode pages even if the SMAP bit is set in the CR4 register.

This instruction's operation is the same in non-64-bit modes and 64-bit mode. Attempts to execute STAC when

CPL > 0 cause #UD.

Operation

EFLAGS.AC := 1;

Flags Affected

AC set. Other flags are unaffected.

Protected Mode Exceptions

#UD

If the LOCK prefix is used.

If the CPL > 0.

If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.

Real-Address Mode Exceptions

#UD

If the LOCK prefix is used.

If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.

Virtual-8086 Mode Exceptions

#UD

The STAC instruction is not recognized in virtual-8086 mode.

Compatibility Mode Exceptions

#UD

If the LOCK prefix is used.

If the CPL > 0.

If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.

64-Bit Mode Exceptions

#UD

If the LOCK prefix is used.

If the CPL > 0.

If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.

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STAC—Set AC Flag in EFLAGS Register

INSTRUCTION SET REFERENCE, M-U

STC—Set Carry Flag

Opcode

Instruction

Op/

64-Bit

Compat/

Description

En

Mode

Leg Mode

F9

STC

ZO

Valid

Valid

Set CF flag.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ZO

N/A

N/A

N/A

N/A

Description

Sets the CF flag in the EFLAGS register. Operation is the same in all modes.

Operation

CF := 1;

Flags Affected

The CF flag is set. The OF, ZF, SF, AF, and PF flags are unaffected.

Exceptions (All Operating Modes)

#UD

If the LOCK prefix is used.

STC—Set Carry Flag

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4-667

INSTRUCTION SET REFERENCE, M-U

STD—Set Direction Flag

Opcode

Instruction

Op/

64-bit

Compat/

Description

En

Mode

Leg Mode

FD

STD

ZO

Valid

Valid

Set DF flag.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ZO

N/A

N/A

N/A

N/A

Description

Sets the DF flag in the EFLAGS register. When the DF flag is set to 1, string operations decrement the index regis-

ters (ESI and/or EDI). Operation is the same in all modes.

Operation

DF := 1;

Flags Affected

The DF flag is set. The CF, OF, ZF, SF, AF, and PF flags are unaffected.

Exceptions (All Operating Modes)

#UD

If the LOCK prefix is used.

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STD—Set Direction Flag

INSTRUCTION SET REFERENCE, M-U

STI—Set Interrupt Flag

Opcode

Instruction

Op/

64-Bit

Compat/

Description

En

Mode

Leg Mode

FB

STI

ZO

Valid

Valid

Set interrupt flag; external, maskable

interrupts enabled at the end of the next

instruction.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ZO

N/A

N/A

N/A

N/A

Description

In most cases, STI sets the interrupt flag (IF) in the EFLAGS register. This allows the processor to respond to mask-

able hardware interrupts.

If IF = 0, maskable hardware interrupts remain inhibited on the instruction boundary following an execution of STI.

(The delayed effect of this instruction is provided to allow interrupts to be enabled just before returning from a

procedure or subroutine. For instance, if an STI instruction is followed by an RET instruction, the RET instruction is

allowed to execute before external interrupts are recognized. No interrupts can be recognized if an execution of CLI

immediately follow such an execution of STI.) The inhibition ends after delivery of another event (e.g., exception)

or the execution of the next instruction.

The IF flag and the STI and CLI instructions do not prohibit the generation of exceptions and nonmaskable inter-

rupts (NMIs). However, NMIs (and system-management interrupts) may be inhibited on the instruction boundary

following an execution of STI that begins with IF = 0.

Operation is different in two modes defined as follows:

• PVI mode (protected-mode virtual interrupts): CR0.PE = 1, EFLAGS.VM = 0, CPL = 3, and CR4.PVI = 1;

• VME mode (virtual-8086 mode extensions): CR0.PE = 1, EFLAGS.VM = 1, and CR4.VME = 1.

If IOPL < 3, EFLAGS.VIP = 1, and either VME mode or PVI mode is active, STI sets the VIF flag in the EFLAGS

register, leaving IF unaffected.

Table 4-24 indicates the action of the STI instruction depending on the processor operating mode, IOPL, CPL, and

EFLAGS.VIP.

Table 4-24. Decision Table for STI Results

Mode

IOPL

EFLAGS.VIP

STI Result

Real-address

X¹

X

IF = 1

≥ CPL

X

IF = 1

Protected, not PVI²

< CPL

X

#GP fault

3

X

IF = 1

Protected, PVI³

0

VIF = 1

0-2

1

#GP fault

3

X

IF = 1

Virtual-8086, not VME³

0-2

X

#GP fault

3

X

IF = 1

Virtual-8086, VME³

0

VIF = 1

0-2

1

#GP fault

NOTES:

1. X = This setting has no effect on instruction operation.

STI—Set Interrupt Flag

Vol. 2B

4-669

INSTRUCTION SET REFERENCE, M-U

STMXCSR—Store MXCSR Register State

Opcode*/

Op/

64/32 bit

CPUID

Description

Instruction

En

Mode

Feature

Support

Flag

NP 0F AE /3

M

V/V

SSE

Store contents of MXCSR register to m32.

STMXCSR m32

VEX.LZ.0F.WIG AE /3

M

V/V

AVX

Store contents of MXCSR register to m32.

VSTMXCSR m32

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

M

ModRM:r/m (w)

N/A

N/A

N/A

Description

Stores the contents of the MXCSR control and status register to the destination operand. The destination operand

is a 32-bit memory location. The reserved bits in the MXCSR register are stored as 0s.

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

VEX.L must be 0, otherwise instructions will #UD.

Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation

m32 := MXCSR;

Intel C/C++ Compiler Intrinsic Equivalent

_mm_getcsr(void)

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-22, “Type 5 Class Exception Conditions”; additionally:

#UD

If VEX.L= 1,

If VEX.vvvv ≠ 1111B.

STMXCSR—Store MXCSR Register State

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4-671

INSTRUCTION SET REFERENCE, M-U

STOS/STOSB/STOSW/STOSD/STOSQ—Store String

Opcode

Instruction

Op/

64-Bit

Compat/

Description

En

Mode

Leg Mode

AA

STOS m8

ZO

Valid

Valid

For legacy mode, store AL at address ES:(E)DI;

For 64-bit mode store AL at address RDI or EDI.

AB

STOS m16

ZO

Valid

Valid

For legacy mode, store AX at address ES:(E)DI;

For 64-bit mode store AX at address RDI or EDI.

AB

STOS m32

ZO

Valid

Valid

For legacy mode, store EAX at address ES:(E)DI;

For 64-bit mode store EAX at address RDI or

EDI.

REX.W + AB

STOS m64

ZO

Valid

N.E.

Store RAX at address RDI or EDI.

AA

STOSB

ZO

Valid

Valid

For legacy mode, store AL at address ES:(E)DI;

For 64-bit mode store AL at address RDI or EDI.

AB

STOSW

ZO

Valid

Valid

For legacy mode, store AX at address ES:(E)DI;

For 64-bit mode store AX at address RDI or EDI.

AB

STOSD

ZO

Valid

Valid

For legacy mode, store EAX at address ES:(E)DI;

For 64-bit mode store EAX at address RDI or

EDI.

REX.W + AB

STOSQ

ZO

Valid

N.E.

Store RAX at address RDI or EDI.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ZO

N/A

N/A

N/A

N/A

Description

In non-64-bit and default 64-bit mode; stores a byte, word, or doubleword from the AL, AX, or EAX register

(respectively) into the destination operand. The destination operand is a memory location, the address of which is

read from either the ES:EDI or ES:DI register (depending on the address-size attribute of the instruction and the

mode of operation). The ES segment cannot be overridden with a segment override prefix.

At the assembly-code level, two forms of the instruction are allowed: the “explicit-operands” form and the “no-

operands” form. The explicit-operands form (specified with the STOS mnemonic) allows the destination operand to

be specified explicitly. Here, the destination operand should be a symbol that indicates the size and location of the

destination value. The source operand is then automatically selected to match the size of the destination operand

(the AL register for byte operands, AX for word operands, EAX for doubleword operands). The explicit-operands

form is provided to allow documentation; however, note that the documentation provided by this form can be

misleading. That is, the destination operand symbol must specify the correct type (size) of the operand (byte,

word, or doubleword), but it does not have to specify the correct location. The location is always specified by the

ES:(E)DI register. These must be loaded correctly before the store string instruction is executed.

The no-operands form provides “short forms” of the byte, word, doubleword, and quadword versions of the STOS

instructions. Here also ES:(E)DI is assumed to be the destination operand and AL, AX, or EAX is assumed to be the

source operand. The size of the destination and source operands is selected by the mnemonic: STOSB (byte read

from register AL), STOSW (word from AX), STOSD (doubleword from EAX).

After the byte, word, or doubleword is transferred from the register to the memory location, the (E)DI register is

incremented or decremented according to the setting of the DF flag in the EFLAGS register. If the DF flag is 0, the

register is incremented; if the DF flag is 1, the register is decremented (the register is incremented or decremented

by 1 for byte operations, by 2 for word operations, by 4 for doubleword operations).

NOTE: To improve performance, more recent processors support modifications to the processor’s operation during

the string store operations initiated with STOS and STOSB. See Section 7.3.9.3 in the Intel® 64 and IA-32 Archi-

tectures Software Developer’s Manual, Volume 1 for additional information on fast-string operation.

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Vol. 2B

STOS/STOSB/STOSW/STOSD/STOSQ—Store String

INSTRUCTION SET REFERENCE, M-U

STR—Store Task Register

Opcode

Instruction

Op/

64-Bit

Compat/

Description

En

Mode

Leg Mode

0F 00 /1

STR r/m16

M

Valid

Valid

Stores segment selector from TR in r/m16.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

M

ModRM:r/m (w)

N/A

N/A

N/A

Description

Stores the segment selector from the task register (TR) in the destination operand. The destination operand can be

a general-purpose register or a memory location. The segment selector stored with this instruction points to the

task state segment (TSS) for the currently running task.

When the destination operand is a 32-bit register, the 16-bit segment selector is copied into the lower 16 bits of the

register and the upper 16 bits of the register are cleared. When the destination operand is a memory location, the

segment selector is written to memory as a 16-bit quantity, regardless of operand size.

In 64-bit mode, operation is the same. The size of the memory operand is fixed at 16 bits. In register stores, the 2-

byte TR is zero extended if stored to a 64-bit register.

The STR instruction is useful only in operating-system software. It can only be executed in protected mode.

Operation

DEST := TR(SegmentSelector);

Flags Affected

None.

Protected Mode Exceptions

#GP(0)

If the destination is a memory operand that is located in a non-writable segment or if the

effective address is outside the CS, DS, ES, FS, or GS segment limit.

If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment

selector.

If CR4.UMIP = 1 and CPL > 0.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If the LOCK prefix is used.

Real-Address Mode Exceptions

#UD

The STR instruction is not recognized in real-address mode.

Virtual-8086 Mode Exceptions

#UD

The STR instruction is not recognized in virtual-8086 mode.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

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STR—Store Task Register

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