Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 93
INSTRUCTION SET REFERENCE, V
VCOMPRESSPD—Store Sparse Packed Double Precision Floating-Point Values Into Dense
Memory
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F38.W1 8A /r
A
V/V
AVX512VL
Compress packed double precision floating-point
VCOMPRESSPD xmm1/m128 {k1}{z},
AVX512F
values from xmm2 to xmm1/m128 using writemask
xmm2
k1.
EVEX.256.66.0F38.W1 8A /r
A
V/V
AVX512VL
Compress packed double precision floating-point
VCOMPRESSPD ymm1/m256 {k1}{z},
AVX512F
values from ymm2 to ymm1/m256 using writemask
ymm2
k1.
EVEX.512.66.0F38.W1 8A /r
A
V/V
AVX512F
Compress packed double precision floating-point
VCOMPRESSPD zmm1/m512 {k1}{z},
values from zmm2 using control mask k1 to
zmm2
zmm1/m512.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Scalar
ModRM:r/m (w)
ModRM:reg (r)
N/A
N/A
Description
Compress (store) up to 8 double precision floating-point values from the source operand (the second operand) as
a contiguous vector to the destination operand (the first operand) The source operand is a ZMM/YMM/XMM register,
the destination operand can be a ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The opmask register k1 selects the active elements (partial vector or possibly non-contiguous if less than 8 active
elements) from the source operand to compress into a contiguous vector. The contiguous vector is written to the
destination starting from the low element of the destination operand.
Memory destination version: Only the contiguous vector is written to the destination memory location. EVEX.z
must be zero.
Register destination version: If the vector length of the contiguous vector is less than that of the input vector in the
source operand, the upper bits of the destination register are unmodified if EVEX.z is not set, otherwise the upper
bits are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element
instead of the size of the full vector.
Operation
VCOMPRESSPD (EVEX encoded versions) store form
(KL, VL) = (2, 128), (4, 256), (8, 512)
SIZE := 64
k := 0
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN
DEST[k+SIZE-1:k] := SRC[i+63:i]
k := k + SIZE
FI;
ENDFOR
VCOMPRESSPD—Store Sparse Packed Double Precision Floating-Point Values Into Dense Memory
Vol. 2C
5-27
INSTRUCTION SET REFERENCE, V
VCOMPRESSPD (EVEX encoded versions) reg-reg form
(KL, VL) = (2, 128), (4, 256), (8, 512)
SIZE := 64
k := 0
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN
DEST[k+SIZE-1:k] := SRC[i+63:i]
k := k + SIZE
FI;
ENDFOR
IF *merging-masking*
THEN *DEST[VL-1:k] remains unchanged*
ELSE DEST[VL-1:k] := 0
FI
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCOMPRESSPD __m512d _mm512_mask_compress_pd( __m512d s, __mmask8 k, __m512d a);
VCOMPRESSPD __m512d _mm512_maskz_compress_pd( __mmask8 k, __m512d a);
VCOMPRESSPD void _mm512_mask_compressstoreu_pd( void * d, __mmask8 k, __m512d a);
VCOMPRESSPD __m256d _mm256_mask_compress_pd( __m256d s, __mmask8 k, __m256d a);
VCOMPRESSPD __m256d _mm256_maskz_compress_pd( __mmask8 k, __m256d a);
VCOMPRESSPD void _mm256_mask_compressstoreu_pd( void * d, __mmask8 k, __m256d a);
VCOMPRESSPD __m128d _mm_mask_compress_pd( __m128d s, __mmask8 k, __m128d a);
VCOMPRESSPD __m128d _mm_maskz_compress_pd( __mmask8 k, __m128d a);
VCOMPRESSPD void _mm_mask_compressstoreu_pd( void * d, __mmask8 k, __m128d a);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instructions, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
5-28
Vol. 2C
VCOMPRESSPD—Store Sparse Packed Double Precision Floating-Point Values Into Dense Memory
INSTRUCTION SET REFERENCE, V
VCOMPRESSPS—Store Sparse Packed Single Precision Floating-Point Values Into Dense Memory
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F38.W0 8A /r
A
V/V
AVX512VL
Compress packed single precision floating-point
VCOMPRESSPS xmm1/m128 {k1}{z},
AVX512F
values from xmm2 to xmm1/m128 using writemask
xmm2
k1.
EVEX.256.66.0F38.W0 8A /r
A
V/V
AVX512VL
Compress packed single precision floating-point
VCOMPRESSPS ymm1/m256 {k1}{z},
AVX512F
values from ymm2 to ymm1/m256 using writemask
ymm2
k1.
EVEX.512.66.0F38.W0 8A /r
A
V/V
AVX512F
Compress packed single precision floating-point
VCOMPRESSPS zmm1/m512 {k1}{z},
values from zmm2 using control mask k1 to
zmm2
zmm1/m512.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Scalar
ModRM:r/m (w)
ModRM:reg (r)
N/A
N/A
Description
Compress (stores) up to 16 single precision floating-point values from the source operand (the second operand) to
the destination operand (the first operand). The source operand is a ZMM/YMM/XMM register, the destination
operand can be a ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The opmask register k1 selects the active elements (a partial vector or possibly non-contiguous if less than 16
active elements) from the source operand to compress into a contiguous vector. The contiguous vector is written to
the destination starting from the low element of the destination operand.
Memory destination version: Only the contiguous vector is written to the destination memory location. EVEX.z
must be zero.
Register destination version: If the vector length of the contiguous vector is less than that of the input vector in the
source operand, the upper bits of the destination register are unmodified if EVEX.z is not set, otherwise the upper
bits are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element
instead of the size of the full vector.
Operation
VCOMPRESSPS (EVEX encoded versions) store form
(KL, VL) = (4, 128), (8, 256), (16, 512)
SIZE := 32
k := 0
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN
DEST[k+SIZE-1:k] := SRC[i+31:i]
k := k + SIZE
FI;
ENDFOR;
VCOMPRESSPS—Store Sparse Packed Single Precision Floating-Point Values Into Dense Memory
Vol. 2C
5-29
INSTRUCTION SET REFERENCE, V
VCOMPRESSPS (EVEX encoded versions) reg-reg form
(KL, VL) = (4, 128), (8, 256), (16, 512)
SIZE := 32
k := 0
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN
DEST[k+SIZE-1:k] := SRC[i+31:i]
k := k + SIZE
FI;
ENDFOR
IF *merging-masking*
THEN *DEST[VL-1:k] remains unchanged*
ELSE DEST[VL-1:k] := 0
FI
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCOMPRESSPS __m512 _mm512_mask_compress_ps( __m512 s, __mmask16 k, __m512 a);
VCOMPRESSPS __m512 _mm512_maskz_compress_ps( __mmask16 k, __m512 a);
VCOMPRESSPS void _mm512_mask_compressstoreu_ps( void * d, __mmask16 k, __m512 a);
VCOMPRESSPS __m256 _mm256_mask_compress_ps( __m256 s, __mmask8 k, __m256 a);
VCOMPRESSPS __m256 _mm256_maskz_compress_ps( __mmask8 k, __m256 a);
VCOMPRESSPS void _mm256_mask_compressstoreu_ps( void * d, __mmask8 k, __m256 a);
VCOMPRESSPS __m128 _mm_mask_compress_ps( __m128 s, __mmask8 k, __m128 a);
VCOMPRESSPS __m128 _mm_maskz_compress_ps( __mmask8 k, __m128 a);
VCOMPRESSPS void _mm_mask_compressstoreu_ps( void * d, __mmask8 k, __m128 a);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instructions, see Exceptions Type E4.nb. in Table 2-49, “Type E4 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
5-30
Vol. 2C
VCOMPRESSPS—Store Sparse Packed Single Precision Floating-Point Values Into Dense Memory
INSTRUCTION SET REFERENCE, V
VCVTDQ2PH—Convert Packed Signed Doubleword Integers to Packed FP16 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.NP.MAP5.W0 5B /r
A
V/V
AVX512-FP16
Convert four packed signed doubleword integers
VCVTDQ2PH xmm1{k1}{z}, xmm2/
AVX512VL
from xmm2/m128/m32bcst to four packed FP16
m128/m32bcst
values, and store the result in xmm1 subject to
writemask k1.
EVEX.256.NP.MAP5.W0 5B /r
A
V/V
AVX512-FP16
Convert eight packed signed doubleword integers
VCVTDQ2PH xmm1{k1}{z}, ymm2/
AVX512VL
from ymm2/m256/m32bcst to eight packed
m256/m32bcst
FP16 values, and store the result in xmm1
subject to writemask k1.
EVEX.512.NP.MAP5.W0 5B /r
A
V/V
AVX512-FP16
Convert sixteen packed signed doubleword
VCVTDQ2PH ymm1{k1}{z}, zmm2/
integers from zmm2/m512/m32bcst to sixteen
m512/m32bcst {er}
packed FP16 values, and store the result in
ymm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts four, eight, or sixteen packed signed doubleword integers in the source operand to four,
eight, or sixteen packed FP16 values in the destination operand.
EVEX encoded versions: The source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-
tion or a 512/256/128-bit vector broadcast from a 32-bit memory location. The destination operand is a YMM/XMM
register conditionally updated with writemask k1.
EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
If the result of the convert operation is overflow and MXCSR.OM=0 then a SIMD exception will be raised with OE=1,
PE=1.
Operation
VCVTDQ2PH dest, src
VL = 128, 256 or 512
KL := VL / 32
IF *SRC is a register* and (VL = 512) AND (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.dword[0]
ELSE
tsrc := SRC.dword[j]
DEST.fp16[j] := Convert_integer32_to_fp16(tsrc)
ELSE IF *zeroing*:
DEST.fp16[j] := 0
// else dest.fp16[j] remains unchanged
VCVTDQ2PH—Convert Packed Signed Doubleword Integers to Packed FP16 Values
Vol. 2C
5-31
INSTRUCTION SET REFERENCE, V
DEST[MAXVL-1:VL/2] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTDQ2PH __m256h _mm512_cvt_roundepi32_ph (__m512i a, int rounding);
VCVTDQ2PH __m256h _mm512_mask_cvt_roundepi32_ph (__m256h src, __mmask16 k, __m512i a, int rounding);
VCVTDQ2PH __m256h _mm512_maskz_cvt_roundepi32_ph (__mmask16 k, __m512i a, int rounding);
VCVTDQ2PH __m128h _mm_cvtepi32_ph (__m128i a);
VCVTDQ2PH __m128h _mm_mask_cvtepi32_ph (__m128h src, __mmask8 k, __m128i a);
VCVTDQ2PH __m128h _mm_maskz_cvtepi32_ph (__mmask8 k, __m128i a);
VCVTDQ2PH __m128h _mm256_cvtepi32_ph (__m256i a);
VCVTDQ2PH __m128h _mm256_mask_cvtepi32_ph (__m128h src, __mmask8 k, __m256i a);
VCVTDQ2PH __m128h _mm256_maskz_cvtepi32_ph (__mmask8 k, __m256i a);
VCVTDQ2PH __m256h _mm512_cvtepi32_ph (__m512i a);
VCVTDQ2PH __m256h _mm512_mask_cvtepi32_ph (__m256h src, __mmask16 k, __m512i a);
VCVTDQ2PH __m256h _mm512_maskz_cvtepi32_ph (__mmask16 k, __m512i a);
SIMD Floating-Point Exceptions
Overflow, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
5-32
Vol. 2C
VCVTDQ2PH—Convert Packed Signed Doubleword Integers to Packed FP16 Values
INSTRUCTION SET REFERENCE, V
VCVTNE2PS2BF16—Convert Two Packed Single Data to One Packed BF16 Data
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.F2.0F38.W0 72 /r
A
V/V
AVX512VL
Convert packed single data from xmm2 and
VCVTNE2PS2BF16 xmm1{k1}{z},
AVX512_BF16
xmm3/m128/m32bcst to packed BF16 data in
xmm2, xmm3/m128/m32bcst
xmm1 with writemask k1.
EVEX.256.F2.0F38.W0 72 /r
A
V/V
AVX512VL
Convert packed single data from ymm2 and
VCVTNE2PS2BF16 ymm1{k1}{z},
AVX512_BF16
ymm3/m256/m32bcst to packed BF16 data in
ymm2, ymm3/m256/m32bcst
ymm1 with writemask k1.
EVEX.512.F2.0F38.W0 72 /r
A
V/V
AVX512F
Convert packed single data from zmm2 and
VCVTNE2PS2BF16 zmm1{k1}{z},
AVX512_BF16
zmm3/m512/m32bcst to packed BF16 data in
zmm2, zmm3/m512/m32bcst
zmm1 with writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Converts two SIMD registers of packed single data into a single register of packed BF16 data.
This instruction does not support memory fault suppression.
This instruction uses “Round to nearest (even)” rounding mode. Output denormals are always flushed to zero and
input denormals are always treated as zero. MXCSR is not consulted nor updated. No floating-point exceptions are
generated.
Operation
VCVTNE2PS2BF16 dest, src1, src2
VL = (128, 256, 512)
KL = VL/16
origdest := dest
FOR i := 0 to KL-1:
IF k1[ i ] or *no writemask*:
IF i < KL/2:
IF src2 is memory and evex.b == 1:
t := src2.fp32[0]
ELSE:
t := src2.fp32[ i ]
ELSE:
t := src1.fp32[ i-KL/2]
// See VCVTNEPS2BF16 for definition of convert helper function
dest.word[i] := convert_fp32_to_bfloat16(t)
ELSE IF *zeroing*:
dest.word[ i ] := 0
ELSE: // Merge masking, dest element unchanged
dest.word[ i ] := origdest.word[ i ]
DEST[MAXVL-1:VL] := 0
VCVTNE2PS2BF16—Convert Two Packed Single Data to One Packed BF16 Data
Vol. 2C
5-33
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VCVTNE2PS2BF16 __m128bh _mm_cvtne2ps_pbh (__m128, __m128);
VCVTNE2PS2BF16 __m128bh _mm_mask_cvtne2ps_pbh (__m128bh, __mmask8, __m128, __m128);
VCVTNE2PS2BF16 __m128bh _mm_maskz_cvtne2ps_pbh (__mmask8, __m128, __m128);
VCVTNE2PS2BF16 __m256bh _mm256_cvtne2ps_pbh (__m256, __m256);
VCVTNE2PS2BF16 __m256bh _mm256_mask_cvtne2ps_pbh (__m256bh, __mmask16, __m256, __m256);
VCVTNE2PS2BF16 __m256bh _mm256_maskz_cvtne2ps_ pbh (__mmask16, __m256, __m256);
VCVTNE2PS2BF16 __m512bh _mm512_cvtne2ps_pbh (__m512, __m512);
VCVTNE2PS2BF16 __m512bh _mm512_mask_cvtne2ps_pbh (__m512bh, __mmask32, __m512, __m512);
VCVTNE2PS2BF16 __m512bh _mm512_maskz_cvtne2ps_pbh (__mmask32, __m512, __m512);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-50, “Type E4NF Class Exception Conditions.”
5-34
Vol. 2C
VCVTNE2PS2BF16—Convert Two Packed Single Data to One Packed BF16 Data
INSTRUCTION SET REFERENCE, V
VCVTNEPS2BF16—Convert Packed Single Data to Packed BF16 Data
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.F3.0F38.W0 72 /r
A
V/V
AVX512VL
Convert packed single data from xmm2/m128
VCVTNEPS2BF16 xmm1{k1}{z},
AVX512_BF16
to packed BF16 data in xmm1 with writemask
xmm2/m128/m32bcst
k1.
EVEX.256.F3.0F38.W0 72 /r
A
V/V
AVX512VL
Convert packed single data from ymm2/m256
VCVTNEPS2BF16 xmm1{k1}{z},
AVX512_BF16
to packed BF16 data in xmm1 with writemask
ymm2/m256/m32bcst
k1.
EVEX.512.F3.0F38.W0 72 /r
A
V/V
AVX512F
Convert packed single data from zmm2/m512
VCVTNEPS2BF16 ymm1{k1}{z},
AVX512_BF16
to packed BF16 data in ymm1 with writemask
zmm2/m512/m32bcst
k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts one SIMD register of packed single data into a single register of packed BF16 data.
This instruction uses “Round to nearest (even)” rounding mode. Output denormals are always flushed to zero and
input denormals are always treated as zero. MXCSR is not consulted nor updated.
As the instruction operand encoding table shows, the EVEX.vvvv field is not used for encoding an operand.
EVEX.vvvv is reserved and must be 0b1111 otherwise instructions will #UD.
Operation
Define convert_fp32_to_bfloat16(x):
IF x is zero or denormal:
dest[15] := x[31] // sign preserving zero (denormal go to zero)
dest[14:0] := 0
ELSE IF x is infinity:
dest[15:0] := x[31:16]
ELSE IF x is NAN:
dest[15:0] := x[31:16] // truncate and set MSB of the mantissa to force QNAN
dest[6] := 1
ELSE // normal number
LSB := x[16]
rounding_bias := 0x00007FFF + LSB
temp[31:0] := x[31:0] + rounding_bias // integer add
dest[15:0] := temp[31:16]
RETURN dest
VCVTNEPS2BF16—Convert Packed Single Data to Packed BF16 Data
Vol. 2C
5-35
INSTRUCTION SET REFERENCE, V
VCVTNEPS2BF16 dest, src
VL = (128, 256, 512)
KL = VL/16
origdest := dest
FOR i := 0 to KL/2-1:
IF k1[ i ] or *no writemask*:
IF src is memory and evex.b == 1:
t := src.fp32[0]
ELSE:
t := src.fp32[ i ]
dest.word[i] := convert_fp32_to_bfloat16(t)
ELSE IF *zeroing*:
dest.word[ i ] := 0
ELSE: // Merge masking, dest element unchanged
dest.word[ i ] := origdest.word[ i ]
DEST[MAXVL-1:VL/2] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTNEPS2BF16 __m128bh _mm_cvtneps_pbh (__m128);
VCVTNEPS2BF16 __m128bh _mm_mask_cvtneps_pbh (__m128bh, __mmask8, __m128);
VCVTNEPS2BF16 __m128bh _mm_maskz_cvtneps_pbh (__mmask8, __m128);
VCVTNEPS2BF16 __m128bh _mm256_cvtneps_pbh (__m256);
VCVTNEPS2BF16 __m128bh _mm256_mask_cvtneps_pbh (__m128bh, __mmask8, __m256);
VCVTNEPS2BF16 __m128bh _mm256_maskz_cvtneps_pbh (__mmask8, __m256);
VCVTNEPS2BF16 __m256bh _mm512_cvtneps_pbh (__m512);
VCVTNEPS2BF16 __m256bh _mm512_mask_cvtneps_pbh (__m256bh, __mmask16, __m512);
VCVTNEPS2BF16 __m256bh _mm512_maskz_cvtneps_pbh (__mmask16, __m512);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-49, “Type E4 Class Exception Conditions.”
5-36
Vol. 2C
VCVTNEPS2BF16—Convert Packed Single Data to Packed BF16 Data
INSTRUCTION SET REFERENCE, V
VCVTPD2PH—Convert Packed Double Precision FP Values to Packed FP16 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.66.MAP5.W1 5A /r
A
V/V
AVX512-FP16
Convert two packed double precision floating-
VCVTPD2PH xmm1{k1}{z}, xmm2/
AVX512VL
point values in xmm2/m128/m64bcst to two
m128/m64bcst
packed FP16 values, and store the result in xmm1
subject to writemask k1.
EVEX.256.66.MAP5.W1 5A /r
A
V/V
AVX512-FP16
Convert four packed double precision floating-
VCVTPD2PH xmm1{k1}{z}, ymm2/
AVX512VL
point values in ymm2/m256/m64bcst to four
m256/m64bcst
packed FP16 values, and store the result in xmm1
subject to writemask k1.
EVEX.512.66.MAP5.W1 5A /r
A
V/V
AVX512-FP16
Convert eight packed double precision floating-
VCVTPD2PH xmm1{k1}{z}, zmm2/
point values in zmm2/m512/m64bcst to eight
m512/m64bcst {er}
packed FP16 values, and store the result in ymm1
subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts two, four, or eight packed double precision floating-point values in the source operand
(second operand) to two, four, or eight packed FP16 values in the destination operand (first operand). When a
conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or
the embedded rounding control bits.
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or
a 512/256/128-bit vector broadcasts from a 64-bit memory location. The destination operand is a XMM register
conditionally updated with writemask k1. The upper bits (MAXVL-1:128/64/32) of the corresponding destination
are zeroed.
EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
This instruction uses MXCSR.DAZ for handling FP64 inputs. FP16 outputs can be normal or denormal, and are not
conditionally flushed to zero.
VCVTPD2PH—Convert Packed Double Precision FP Values to Packed FP16 Values
Vol. 2C
5-37
INSTRUCTION SET REFERENCE, V
Operation
VCVTPD2PH dest, src
VL = 128, 256 or 512
KL := VL / 64
IF *SRC is a register* and (VL = 512) AND (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.double[0]
ELSE
tsrc := SRC.double[j]
DEST.fp16[j] := Convert_fp64_to_fp16(tsrc)
ELSE IF *zeroing*:
DEST.fp16[j] := 0
// else dest.fp16[j] remains unchanged
DEST[MAXVL-1:VL/4] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPD2PH __m128h _mm512_cvt_roundpd_ph (__m512d a, int rounding);
VCVTPD2PH __m128h _mm512_mask_cvt_roundpd_ph (__m128h src, __mmask8 k, __m512d a, int rounding);
VCVTPD2PH __m128h _mm512_maskz_cvt_roundpd_ph (__mmask8 k, __m512d a, int rounding);
VCVTPD2PH __m128h _mm_cvtpd_ph (__m128d a);
VCVTPD2PH __m128h _mm_mask_cvtpd_ph (__m128h src, __mmask8 k, __m128d a);
VCVTPD2PH __m128h _mm_maskz_cvtpd_ph (__mmask8 k, __m128d a);
VCVTPD2PH __m128h _mm256_cvtpd_ph (__m256d a);
VCVTPD2PH __m128h _mm256_mask_cvtpd_ph (__m128h src, __mmask8 k, __m256d a);
VCVTPD2PH __m128h _mm256_maskz_cvtpd_ph (__mmask8 k, __m256d a);
VCVTPD2PH __m128h _mm512_cvtpd_ph (__m512d a);
VCVTPD2PH __m128h _mm512_mask_cvtpd_ph (__m128h src, __mmask8 k, __m512d a);
VCVTPD2PH __m128h _mm512_maskz_cvtpd_ph (__mmask8 k, __m512d a);
SIMD Floating-Point Exceptions
Invalid, Underflow, Overflow, Precision, Denormal
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
5-38
Vol. 2C
VCVTPD2PH—Convert Packed Double Precision FP Values to Packed FP16 Values
INSTRUCTION SET REFERENCE, V
VCVTPD2QQ—Convert Packed Double Precision Floating-Point Values to Packed Quadword
Integers
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F.W1 7B /r
A
V/V
AVX512VL
Convert two packed double precision floating-point values from
VCVTPD2QQ xmm1 {k1}{z},
AVX512DQ
xmm2/m128/m64bcst to two packed quadword integers in
xmm2/m128/m64bcst
xmm1 with writemask k1.
EVEX.256.66.0F.W1 7B /r
A
V/V
AVX512VL
Convert four packed double precision floating-point values from
VCVTPD2QQ ymm1 {k1}{z},
AVX512DQ
ymm2/m256/m64bcst to four packed quadword integers in
ymm2/m256/m64bcst
ymm1 with writemask k1.
EVEX.512.66.0F.W1 7B /r
A
V/V
AVX512DQ
Convert eight packed double precision floating-point values
VCVTPD2QQ zmm1 {k1}{z},
from zmm2/m512/m64bcst to eight packed quadword integers
zmm2/m512/m64bcst{er}
in zmm1 with writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts packed double precision floating-point values in the source operand (second operand) to packed quad-
word integers in the destination operand (first operand).
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The destination operation is a ZMM/YMM/XMM register conditionally updated with writemask k1.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value
(2w-1, where w represents the number of bits in the destination format) is returned.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VCVTPD2QQ (EVEX encoded version) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL == 512) AND (EVEX.b == 1)
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
ELSE
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
FI;
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] :=
Convert_Double_Precision_Floating_Point_To_QuadInteger(SRC[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
VCVTPD2QQ—Convert Packed Double Precision Floating-Point Values to Packed Quadword Integers
Vol. 2C
5-39
INSTRUCTION SET REFERENCE, V
ENDFOR
DEST[MAXVL-1:VL] := 0
VCVTPD2QQ (EVEX encoded version) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[i+63:i] :=
Convert_Double_Precision_Floating_Point_To_QuadInteger(SRC[63:0])
ELSE
DEST[i+63:i] := Convert_Double_Precision_Floating_Point_To_QuadInteger(SRC[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPD2QQ __m512i _mm512_cvtpd_epi64( __m512d a);
VCVTPD2QQ __m512i _mm512_mask_cvtpd_epi64( __m512i s, __mmask8 k, __m512d a);
VCVTPD2QQ __m512i _mm512_maskz_cvtpd_epi64( __mmask8 k, __m512d a);
VCVTPD2QQ __m512i _mm512_cvt_roundpd_epi64( __m512d a, int r);
VCVTPD2QQ __m512i _mm512_mask_cvt_roundpd_epi64( __m512i s, __mmask8 k, __m512d a, int r);
VCVTPD2QQ __m512i _mm512_maskz_cvt_roundpd_epi64( __mmask8 k, __m512d a, int r);
VCVTPD2QQ __m256i _mm256_mask_cvtpd_epi64( __m256i s, __mmask8 k, __m256d a);
VCVTPD2QQ __m256i _mm256_maskz_cvtpd_epi64( __mmask8 k, __m256d a);
VCVTPD2QQ __m128i _mm_mask_cvtpd_epi64( __m128i s, __mmask8 k, __m128d a);
VCVTPD2QQ __m128i _mm_maskz_cvtpd_epi64( __mmask8 k, __m128d a);
VCVTPD2QQ __m256i _mm256_cvtpd_epi64 (__m256d src)
VCVTPD2QQ __m128i _mm_cvtpd_epi64 (__m128d src)
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
5-40
Vol. 2C
VCVTPD2QQ—Convert Packed Double Precision Floating-Point Values to Packed Quadword Integers
INSTRUCTION SET REFERENCE, V
VCVTPD2UDQ—Convert Packed Double Precision Floating-Point Values to Packed Unsigned
Doubleword Integers
Opcode
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.0F.W1 79 /r
A
V/V
AVX512VL
Convert two packed double precision floating-point
VCVTPD2UDQ xmm1 {k1}{z},
AVX512F
values in xmm2/m128/m64bcst to two unsigned
xmm2/m128/m64bcst
doubleword integers in xmm1 subject to writemask k1.
EVEX.256.0F.W1 79 /r
A
V/V
AVX512VL
Convert four packed double precision floating-point
VCVTPD2UDQ xmm1 {k1}{z},
AVX512F
values in ymm2/m256/m64bcst to four unsigned
ymm2/m256/m64bcst
doubleword integers in xmm1 subject to writemask k1.
EVEX.512.0F.W1 79 /r
A
V/V
AVX512F
Convert eight packed double precision floating-point
VCVTPD2UDQ ymm1 {k1}{z},
values in zmm2/m512/m64bcst to eight unsigned
zmm2/m512/m64bcst{er}
doubleword integers in ymm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts packed double precision floating-point values in the source operand (the second operand) to packed
unsigned doubleword integers in the destination operand (the first operand).
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w - 1 is
returned, where w represents the number of bits in the destination format.
The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector
broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1. The upper bits (MAXVL-1:256) of the corresponding destination are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VCVTPD2UDQ (EVEX encoded versions) when src2 operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
ELSE
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
FI;
FOR j := 0 TO KL-1
i := j * 32
k := j * 64
IF k1[j] OR *no writemask*
THEN
DEST[i+31:i] :=
Convert_Double_Precision_Floating_Point_To_UInteger(SRC[k+63:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
VCVTPD2UDQ—Convert Packed Double Precision Floating-Point Values to Packed Unsigned Doubleword Integers
Vol. 2C
5-41
INSTRUCTION SET REFERENCE, V
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0
VCVTPD2UDQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 32
k := j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i] :=
Convert_Double_Precision_Floating_Point_To_UInteger(SRC[63:0])
ELSE
DEST[i+31:i] :=
Convert_Double_Precision_Floating_Point_To_UInteger(SRC[k+63:k])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPD2UDQ __m256i _mm512_cvtpd_epu32( __m512d a);
VCVTPD2UDQ __m256i _mm512_mask_cvtpd_epu32( __m256i s, __mmask8 k, __m512d a);
VCVTPD2UDQ __m256i _mm512_maskz_cvtpd_epu32( __mmask8 k, __m512d a);
VCVTPD2UDQ __m256i _mm512_cvt_roundpd_epu32( __m512d a, int r);
VCVTPD2UDQ __m256i _mm512_mask_cvt_roundpd_epu32( __m256i s, __mmask8 k, __m512d a, int r);
VCVTPD2UDQ __m256i _mm512_maskz_cvt_roundpd_epu32( __mmask8 k, __m512d a, int r);
VCVTPD2UDQ __m128i _mm256_mask_cvtpd_epu32( __m128i s, __mmask8 k, __m256d a);
VCVTPD2UDQ __m128i _mm256_maskz_cvtpd_epu32( __mmask8 k, __m256d a);
VCVTPD2UDQ __m128i _mm_mask_cvtpd_epu32( __m128i s, __mmask8 k, __m128d a);
VCVTPD2UDQ __m128i _mm_maskz_cvtpd_epu32( __mmask8 k, __m128d a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
5-42
Vol. 2C
VCVTPD2UDQ—Convert Packed Double Precision Floating-Point Values to Packed Unsigned Doubleword Integers
INSTRUCTION SET REFERENCE, V
VCVTPD2UQQ—Convert Packed Double Precision Floating-Point Values to Packed Unsigned
Quadword Integers
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F.W1 79 /r
A
V/V
AVX512VL
Convert two packed double precision floating-point values from
VCVTPD2UQQ xmm1 {k1}{z},
AVX512DQ
xmm2/mem to two packed unsigned quadword integers in
xmm2/m128/m64bcst
xmm1 with writemask k1.
EVEX.256.66.0F.W1 79 /r
A
V/V
AVX512VL
Convert fourth packed double precision floating-point values
VCVTPD2UQQ ymm1 {k1}{z},
AVX512DQ
from ymm2/mem to four packed unsigned quadword integers
ymm2/m256/m64bcst
in ymm1 with writemask k1.
EVEX.512.66.0F.W1 79 /r
A
V/V
AVX512DQ
Convert eight packed double precision floating-point values
VCVTPD2UQQ zmm1 {k1}{z},
from zmm2/mem to eight packed unsigned quadword integers
zmm2/m512/m64bcst{er}
in zmm1 with writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts packed double precision floating-point values in the source operand (second operand) to packed unsigned
quadword integers in the destination operand (first operand).
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w - 1 is
returned, where w represents the number of bits in the destination format.
The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operation
is a ZMM/YMM/XMM register conditionally updated with writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VCVTPD2UQQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL == 512) AND (EVEX.b == 1)
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
ELSE
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
FI;
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] :=
Convert_Double_Precision_Floating_Point_To_UQuadInteger(SRC[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
VCVTPD2UQQ—Convert Packed Double Precision Floating-Point Values to Packed Unsigned Quadword Integers
Vol. 2C
5-43
INSTRUCTION SET REFERENCE, V
ENDFOR
DEST[MAXVL-1:VL] := 0
VCVTPD2UQQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[i+63:i] :=
Convert_Double_Precision_Floating_Point_To_UQuadInteger(SRC[63:0])
ELSE
DEST[i+63:i] :=
Convert_Double_Precision_Floating_Point_To_UQuadInteger(SRC[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPD2UQQ __m512i _mm512_cvtpd_epu64( __m512d a);
VCVTPD2UQQ __m512i _mm512_mask_cvtpd_epu64( __m512i s, __mmask8 k, __m512d a);
VCVTPD2UQQ __m512i _mm512_maskz_cvtpd_epu64( __mmask8 k, __m512d a);
VCVTPD2UQQ __m512i _mm512_cvt_roundpd_epu64( __m512d a, int r);
VCVTPD2UQQ __m512i _mm512_mask_cvt_roundpd_epu64( __m512i s, __mmask8 k, __m512d a, int r);
VCVTPD2UQQ __m512i _mm512_maskz_cvt_roundpd_epu64( __mmask8 k, __m512d a, int r);
VCVTPD2UQQ __m256i _mm256_mask_cvtpd_epu64( __m256i s, __mmask8 k, __m256d a);
VCVTPD2UQQ __m256i _mm256_maskz_cvtpd_epu64( __mmask8 k, __m256d a);
VCVTPD2UQQ __m128i _mm_mask_cvtpd_epu64( __m128i s, __mmask8 k, __m128d a);
VCVTPD2UQQ __m128i _mm_maskz_cvtpd_epu64( __mmask8 k, __m128d a);
VCVTPD2UQQ __m256i _mm256_cvtpd_epu64 (__m256d src)
VCVTPD2UQQ __m128i _mm_cvtpd_epu64 (__m128d src)
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
5-44
Vol. 2C
VCVTPD2UQQ—Convert Packed Double Precision Floating-Point Values to Packed Unsigned Quadword Integers
INSTRUCTION SET REFERENCE, V
VCVTPH2DQ—Convert Packed FP16 Values to Signed Doubleword Integers
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.66.MAP5.W0 5B /r
A
V/V
AVX512-FP16
Convert four packed FP16 values in xmm2/m64/
VCVTPH2DQ xmm1{k1}{z}, xmm2/
AVX512VL
m16bcst to four signed doubleword integers, and
m64/m16bcst
store the result in xmm1 subject to writemask
k1.
EVEX.256.66.MAP5.W0 5B /r
A
V/V
AVX512-FP16
Convert eight packed FP16 values in xmm2/
VCVTPH2DQ ymm1{k1}{z}, xmm2/
AVX512VL
m128/m16bcst to eight signed doubleword
m128/m16bcst
integers, and store the result in ymm1 subject to
writemask k1.
EVEX.512.66.MAP5.W0 5B /r
A
V/V
AVX512-FP16
Convert sixteen packed FP16 values in ymm2/
VCVTPH2DQ zmm1{k1}{z}, ymm2/
m256/m16bcst to sixteen signed doubleword
m256/m16bcst {er}
integers, and store the result in zmm1 subject to
writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Half
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed FP16 values in the source operand to signed doubleword integers in destination
operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value is
returned.
The destination elements are updated according to the writemask.
Operation
VCVTPH2DQ dest, src
VL = 128, 256 or 512
KL := VL / 32
IF *SRC is a register* and (VL = 512) and (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.fp16[0]
ELSE
tsrc := SRC.fp16[j]
DEST.dword[j] := Convert_fp16_to_integer32(tsrc)
ELSE IF *zeroing*:
DEST.dword[j] := 0
// else dest.dword[j] remains unchanged
DEST[MAXVL-1:VL] := 0
VCVTPH2DQ—Convert Packed FP16 Values to Signed Doubleword Integers
Vol. 2C
5-45
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPH2DQ __m512i _mm512_cvt_roundph_epi32 (__m256h a, int rounding);
VCVTPH2DQ __m512i _mm512_mask_cvt_roundph_epi32 (__m512i src, __mmask16 k, __m256h a, int rounding);
VCVTPH2DQ __m512i _mm512_maskz_cvt_roundph_epi32 (__mmask16 k, __m256h a, int rounding);
VCVTPH2DQ __m128i _mm_cvtph_epi32 (__m128h a);
VCVTPH2DQ __m128i _mm_mask_cvtph_epi32 (__m128i src, __mmask8 k, __m128h a);
VCVTPH2DQ __m128i _mm_maskz_cvtph_epi32 (__mmask8 k, __m128h a);
VCVTPH2DQ __m256i _mm256_cvtph_epi32 (__m128h a);
VCVTPH2DQ __m256i _mm256_mask_cvtph_epi32 (__m256i src, __mmask8 k, __m128h a);
VCVTPH2DQ __m256i _mm256_maskz_cvtph_epi32 (__mmask8 k, __m128h a);
VCVTPH2DQ __m512i _mm512_cvtph_epi32 (__m256h a);
VCVTPH2DQ __m512i _mm512_mask_cvtph_epi32 (__m512i src, __mmask16 k, __m256h a);
VCVTPH2DQ __m512i _mm512_maskz_cvtph_epi32 (__mmask16 k, __m256h a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
5-46
Vol. 2C
VCVTPH2DQ—Convert Packed FP16 Values to Signed Doubleword Integers
INSTRUCTION SET REFERENCE, V
VCVTPH2PD—Convert Packed FP16 Values to FP64 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.NP.MAP5.W0 5A /r
A
V/V
AVX512-FP16
Convert packed FP16 values in xmm2/m32/
VCVTPH2PD xmm1{k1}{z}, xmm2/
AVX512VL
m16bcst to FP64 values, and store result in
m32/m16bcst
xmm1 subject to writemask k1.
EVEX.256.NP.MAP5.W0 5A /r
A
V/V
AVX512-FP16
Convert packed FP16 values in xmm2/m64/
VCVTPH2PD ymm1{k1}{z}, xmm2/
AVX512VL
m16bcst to FP64 values, and store result in
m64/m16bcst
ymm1 subject to writemask k1.
EVEX.512.NP.MAP5.W0 5A /r
A
V/V
AVX512-FP16
Convert packed FP16 values in xmm2/m128/
VCVTPH2PD zmm1{k1}{z}, xmm2/
m16bcst to FP64 values, and store result in
m128/m16bcst {sae}
zmm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Quarter
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed FP16 values to FP64 values in the destination register. The destination elements
are updated according to the writemask.
This instruction handles both normal and denormal FP16 inputs.
Operation
VCVTPH2PD dest, src
VL = 128, 256, or 512
KL := VL/64
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.fp16[0]
ELSE
tsrc := SRC.fp16[j]
DEST.fp64[j] := Convert_fp16_to_fp64(tsrc)
ELSE IF *zeroing*:
DEST.fp64[j] := 0
// else dest.fp64[j] remains unchanged
DEST[MAXVL-1:VL] := 0
VCVTPH2PD—Convert Packed FP16 Values to FP64 Values
Vol. 2C
5-47
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPH2PD __m512d _mm512_cvt_roundph_pd (__m128h a, int sae);
VCVTPH2PD __m512d _mm512_mask_cvt_roundph_pd (__m512d src, __mmask8 k, __m128h a, int sae);
VCVTPH2PD __m512d _mm512_maskz_cvt_roundph_pd (__mmask8 k, __m128h a, int sae);
VCVTPH2PD __m128d _mm_cvtph_pd (__m128h a);
VCVTPH2PD __m128d _mm_mask_cvtph_pd (__m128d src, __mmask8 k, __m128h a);
VCVTPH2PD __m128d _mm_maskz_cvtph_pd (__mmask8 k, __m128h a);
VCVTPH2PD __m256d _mm256_cvtph_pd (__m128h a);
VCVTPH2PD __m256d _mm256_mask_cvtph_pd (__m256d src, __mmask8 k, __m128h a);
VCVTPH2PD __m256d _mm256_maskz_cvtph_pd (__mmask8 k, __m128h a);
VCVTPH2PD __m512d _mm512_cvtph_pd (__m128h a);
VCVTPH2PD __m512d _mm512_mask_cvtph_pd (__m512d src, __mmask8 k, __m128h a);
VCVTPH2PD __m512d _mm512_maskz_cvtph_pd (__mmask8 k, __m128h a);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
5-48
Vol. 2C
VCVTPH2PD—Convert Packed FP16 Values to FP64 Values
INSTRUCTION SET REFERENCE, V
VCVTPH2PS/VCVTPH2PSX—Convert Packed FP16 Values to Single Precision Floating-Point
Values
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature Flag
Support
VEX.128.66.0F38.W0 13 /r
A
V/V
F16C
Convert four packed FP16 values in xmm2/m64 to
VCVTPH2PS xmm1, xmm2/m64
packed single precision floating-point value in xmm1.
VEX.256.66.0F38.W0 13 /r
A
V/V
F16C
Convert eight packed FP16 values in xmm2/m128 to
VCVTPH2PS ymm1, xmm2/m128
packed single precision floating-point value in ymm1.
EVEX.128.66.0F38.W0 13 /r
B
V/V
AVX512VL
Convert four packed FP16 values in xmm2/m64 to
VCVTPH2PS xmm1 {k1}{z},
AVX512F
packed single precision floating-point values in xmm1
xmm2/m64
subject to writemask k1.
EVEX.256.66.0F38.W0 13 /r
B
V/V
AVX512VL
Convert eight packed FP16 values in xmm2/m128 to
VCVTPH2PS ymm1 {k1}{z},
AVX512F
packed single precision floating-point values in ymm1
xmm2/m128
subject to writemask k1.
EVEX.512.66.0F38.W0 13 /r
B
V/V
AVX512F
Convert sixteen packed FP16 values in ymm2/m256
VCVTPH2PS zmm1 {k1}{z},
to packed single precision floating-point values in
ymm2/m256 {sae}
zmm1 subject to writemask k1.
EVEX.128.66.MAP6.W0 13 /r
C
V/V
AVX512-FP16
Convert four packed FP16 values in
VCVTPH2PSX xmm1{k1}{z},
AVX512VL
xmm2/m64/m16bcst to four packed single precision
xmm2/m64/m16bcst
floating-point values, and store result in xmm1
subject to writemask k1.
EVEX.256.66.MAP6.W0 13 /r
C
V/V
AVX512-FP16
Convert eight packed FP16 values in
VCVTPH2PSX ymm1{k1}{z},
AVX512VL
xmm2/m128/m16bcst to eight packed single
xmm2/m128/m16bcst
precision floating-point values, and store result in
ymm1 subject to writemask k1.
EVEX.512.66.MAP6.W0 13 /r
C
V/V
AVX512-FP16
Convert sixteen packed FP16 values in
VCVTPH2PSX zmm1{k1}{z},
ymm2/m256/m16bcst to sixteen packed single
ymm2/m256/m16bcst {sae}
precision floating-point values, and store result in
zmm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
B
Half Mem
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
C
Half
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed half precision (16-bits) floating-point values in the low-order bits of the source
operand (the second operand) to packed single precision floating-point values and writes the converted values into
the destination operand (the first operand).
If case of a denormal operand, the correct normal result is returned. MXCSR.DAZ is ignored and is treated as if it
0. No denormal exception is reported on MXCSR.
VEX.128 version: The source operand is a XMM register or 64-bit memory location. The destination operand is a
XMM register. The upper bits (MAXVL-1:128) of the corresponding destination register are zeroed.
VEX.256 version: The source operand is a XMM register or 128-bit memory location. The destination operand is a
YMM register. Bits (MAXVL-1:256) of the corresponding destination register are zeroed.
EVEX encoded versions: The source operand is a YMM/XMM/XMM (low 64-bits) register or a 256/128/64-bit
memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.
The diagram below illustrates how data is converted from four packed half precision (in 64 bits) to four single preci-
sion (in 128 bits) floating-point values.
VCVTPH2PS/VCVTPH2PSX—Convert Packed FP16 Values to Single Precision Floating-Point Values
Vol. 2C
5-49
INSTRUCTION SET REFERENCE, V
Note: VEX.vvvv and EVEX.vvvv are reserved (must be 1111b).
VCVTPH2PS xmm1, xmm2/mem64, imm8
127
96
95
64
63
48
47
32
31
16
15
0
VH3
VH2
VH1
VH0
xmm2/mem64
convert
convert
convert
convert
127
96
95
64
63
32
31
0
VS3
VS2
VS1
VS0
xmm1
Figure 5-6. VCVTPH2PS (128-bit Version)
The VCVTPH2PSX instruction is a new form of the PH to PS conversion instruction, encoded in map 6. The previous
version of the instruction, VCVTPH2PS, that is present in AVX512F (encoded in map 2, 0F38) does not support
embedded broadcasting. The VCVTPH2PSX instruction has the embedded broadcasting option available.
The instructions associated with AVX512_FP16 always handle FP16 denormal number inputs; denormal inputs are
not treated as zero.
Operation
vCvt_h2s(SRC1[15:0])
{
RETURN Cvt_Half_Precision_To_Single_Precision(SRC1[15:0]);
}
VCVTPH2PS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
k := j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] :=
vCvt_h2s(SRC[k+15:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
5-50
Vol. 2C
VCVTPH2PS/VCVTPH2PSX—Convert Packed FP16 Values to Single Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V
VCVTPH2PS (VEX.256 encoded version)
DEST[31:0] := vCvt_h2s(SRC1[15:0]);
DEST[63:32] := vCvt_h2s(SRC1[31:16]);
DEST[95:64] := vCvt_h2s(SRC1[47:32]);
DEST[127:96] := vCvt_h2s(SRC1[63:48]);
DEST[159:128] := vCvt_h2s(SRC1[79:64]);
DEST[191:160] := vCvt_h2s(SRC1[95:80]);
DEST[223:192] := vCvt_h2s(SRC1[111:96]);
DEST[255:224] := vCvt_h2s(SRC1[127:112]);
DEST[MAXVL-1:256] := 0
VCVTPH2PS (VEX.128 encoded version)
DEST[31:0] := vCvt_h2s(SRC1[15:0]);
DEST[63:32] := vCvt_h2s(SRC1[31:16]);
DEST[95:64] := vCvt_h2s(SRC1[47:32]);
DEST[127:96] := vCvt_h2s(SRC1[63:48]);
DEST[MAXVL-1:128] := 0
VCVTPH2PSX dest, src
VL = 128, 256, or 512
KL := VL/32
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.fp16[0]
ELSE
tsrc := SRC.fp16[j]
DEST.fp32[j] := Convert_fp16_to_fp32(tsrc)
ELSE IF *zeroing*:
DEST.fp32[j] := 0
// else dest.fp32[j] remains unchanged
DEST[MAXVL-1:VL] := 0
Flags Affected
None
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPH2PS __m512 _mm512_cvtph_ps( __m256i a);
VCVTPH2PS __m512 _mm512_mask_cvtph_ps(__m512 s, __mmask16 k, __m256i a);
VCVTPH2PS __m512 _mm512_maskz_cvtph_ps(__mmask16 k, __m256i a);
VCVTPH2PS __m512 _mm512_cvt_roundph_ps( __m256i a, int sae);
VCVTPH2PS __m512 _mm512_mask_cvt_roundph_ps(__m512 s, __mmask16 k, __m256i a, int sae);
VCVTPH2PS __m512 _mm512_maskz_cvt_roundph_ps( __mmask16 k, __m256i a, int sae);
VCVTPH2PS __m256 _mm256_mask_cvtph_ps(__m256 s, __mmask8 k, __m128i a);
VCVTPH2PS __m256 _mm256_maskz_cvtph_ps(__mmask8 k, __m128i a);
VCVTPH2PS __m128 _mm_mask_cvtph_ps(__m128 s, __mmask8 k, __m128i a);
VCVTPH2PS __m128 _mm_maskz_cvtph_ps(__mmask8 k, __m128i a);
VCVTPH2PS __m128 _mm_cvtph_ps ( __m128i m1);
VCVTPH2PS __m256 _mm256_cvtph_ps ( __m128i m1)
VCVTPH2PS/VCVTPH2PSX—Convert Packed FP16 Values to Single Precision Floating-Point Values
Vol. 2C
5-51
INSTRUCTION SET REFERENCE, V
VCVTPH2PSX __m512 _mm512_cvtx_roundph_ps (__m256h a, int sae);
VCVTPH2PSX __m512 _mm512_mask_cvtx_roundph_ps (__m512 src, __mmask16 k, __m256h a, int sae);
VCVTPH2PSX __m512 _mm512_maskz_cvtx_roundph_ps (__mmask16 k, __m256h a, int sae);
VCVTPH2PSX __m128 _mm_cvtxph_ps (__m128h a);
VCVTPH2PSX __m128 _mm_mask_cvtxph_ps (__m128 src, __mmask8 k, __m128h a);
VCVTPH2PSX __m128 _mm_maskz_cvtxph_ps (__mmask8 k, __m128h a);
VCVTPH2PSX __m256 _mm256_cvtxph_ps (__m128h a);
VCVTPH2PSX __m256 _mm256_mask_cvtxph_ps (__m256 src, __mmask8 k, __m128h a);
VCVTPH2PSX __m256 _mm256_maskz_cvtxph_ps (__mmask8 k, __m128h a);
VCVTPH2PSX __m512 _mm512_cvtxph_ps (__m256h a);
VCVTPH2PSX __m512 _mm512_mask_cvtxph_ps (__m512 src, __mmask16 k, __m256h a);
VCVTPH2PSX __m512 _mm512_maskz_cvtxph_ps (__mmask16 k, __m256h a);
SIMD Floating-Point Exceptions
VEX-encoded instructions: Invalid.
EVEX-encoded instructions: Invalid.
EVEX-encoded instructions with broadcast (VCVTPH2PSX): Invalid, Denormal.
Other Exceptions
VEX-encoded instructions, see Table 2-26, “Type 11 Class Exception Conditions” (do not report #AC).
EVEX-encoded instructions, see Table 2-60, “Type E11 Class Exception Conditions.”
EVEX-encoded instructions with broadcast (VCVTPH2PSX), see Table 2-46, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If VEX.W=1.
#UD
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
5-52
Vol. 2C
VCVTPH2PS/VCVTPH2PSX—Convert Packed FP16 Values to Single Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V
VCVTPH2QQ—Convert Packed FP16 Values to Signed Quadword Integer Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.66.MAP5.W0 7B /r
A
V/V
AVX512-FP16
Convert two packed FP16 values in xmm2/m32/
VCVTPH2QQ xmm1{k1}{z}, xmm2/
AVX512VL
m16bcst to two signed quadword integers, and
m32/m16bcst
store the result in xmm1 subject to writemask k1.
EVEX.256.66.MAP5.W0 7B /r
A
V/V
AVX512-FP16
Convert four packed FP16 values in xmm2/m64/
VCVTPH2QQ ymm1{k1}{z}, xmm2/
AVX512VL
m16bcst to four signed quadword integers, and
m64/m16bcst
store the result in ymm1 subject to writemask k1.
EVEX.512.66.MAP5.W0 7B /r
A
V/V
AVX512-FP16
Convert eight packed FP16 values in xmm2/
VCVTPH2QQ zmm1{k1}{z}, xmm2/
m128/m16bcst to eight signed quadword
m128/m16bcst {er}
integers, and store the result in zmm1 subject to
writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Quarter
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed FP16 values in the source operand to signed quadword integers in destination
operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value is
returned.
The destination elements are updated according to the writemask.
Operation
VCVTPH2QQ dest, src
VL = 128, 256 or 512
KL := VL / 64
IF *SRC is a register* and (VL = 512) and (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.fp16[0]
ELSE
tsrc := SRC.fp16[j]
DEST.qword[j] := Convert_fp16_to_integer64(tsrc)
ELSE IF *zeroing*:
DEST.qword[j] := 0
// else dest.qword[j] remains unchanged
DEST[MAXVL-1:VL] := 0
VCVTPH2QQ—Convert Packed FP16 Values to Signed Quadword Integer Values
Vol. 2C
5-53
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPH2QQ __m512i _mm512_cvt_roundph_epi64 (__m128h a, int rounding);
VCVTPH2QQ __m512i _mm512_mask_cvt_roundph_epi64 (__m512i src, __mmask8 k, __m128h a, int rounding);
VCVTPH2QQ __m512i _mm512_maskz_cvt_roundph_epi64 (__mmask8 k, __m128h a, int rounding);
VCVTPH2QQ __m128i _mm_cvtph_epi64 (__m128h a);
VCVTPH2QQ __m128i _mm_mask_cvtph_epi64 (__m128i src, __mmask8 k, __m128h a);
VCVTPH2QQ __m128i _mm_maskz_cvtph_epi64 (__mmask8 k, __m128h a);
VCVTPH2QQ __m256i _mm256_cvtph_epi64 (__m128h a);
VCVTPH2QQ __m256i _mm256_mask_cvtph_epi64 (__m256i src, __mmask8 k, __m128h a);
VCVTPH2QQ __m256i _mm256_maskz_cvtph_epi64 (__mmask8 k, __m128h a);
VCVTPH2QQ __m512i _mm512_cvtph_epi64 (__m128h a);
VCVTPH2QQ __m512i _mm512_mask_cvtph_epi64 (__m512i src, __mmask8 k, __m128h a);
VCVTPH2QQ __m512i _mm512_maskz_cvtph_epi64 (__mmask8 k, __m128h a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
5-54
Vol. 2C
VCVTPH2QQ—Convert Packed FP16 Values to Signed Quadword Integer Values
INSTRUCTION SET REFERENCE, V
VCVTPH2UDQ—Convert Packed FP16 Values to Unsigned Doubleword Integers
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.NP.MAP5.W0 79 /r
A
V/V
AVX512-FP16
Convert four packed FP16 values in xmm2/m64/
VCVTPH2UDQ xmm1{k1}{z}, xmm2/
AVX512VL
m16bcst to four unsigned doubleword integers,
m64/m16bcst
and store the result in xmm1 subject to
writemask k1.
EVEX.256.NP.MAP5.W0 79 /r
A
V/V
AVX512-FP16
Convert eight packed FP16 values in xmm2/
VCVTPH2UDQ ymm1{k1}{z}, xmm2/
AVX512VL
m128/m16bcst to eight unsigned doubleword
m128/m16bcst
integers, and store the result in ymm1 subject to
writemask k1.
EVEX.512.NP.MAP5.W0 79 /r
A
V/V
AVX512-FP16
Convert sixteen packed FP16 values in ymm2/
VCVTPH2UDQ zmm1{k1}{z}, ymm2/
m256/m16bcst to sixteen unsigned doubleword
m256/m16bcst {er}
integers, and store the result in zmm1 subject to
writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Half
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed FP16 values in the source operand to unsigned doubleword integers in destination
operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value is
returned.
The destination elements are updated according to the writemask.
Operation
VCVTPH2UDQ dest, src
VL = 128, 256 or 512
KL := VL / 32
IF *SRC is a register* and (VL = 512) and (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.fp16[0]
ELSE
tsrc := SRC.fp16[j]
DEST.dword[j] := Convert_fp16_to_unsigned_integer32(tsrc)
ELSE IF *zeroing*:
DEST.dword[j] := 0
// else dest.dword[j] remains unchanged
DEST[MAXVL-1:VL] := 0
VCVTPH2UDQ—Convert Packed FP16 Values to Unsigned Doubleword Integers
Vol. 2C
5-55
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPH2UDQ __m512i _mm512_cvt_roundph_epu32 (__m256h a, int rounding);
VCVTPH2UDQ __m512i _mm512_mask_cvt_roundph_epu32 (__m512i src, __mmask16 k, __m256h a, int rounding);
VCVTPH2UDQ __m512i _mm512_maskz_cvt_roundph_epu32 (__mmask16 k, __m256h a, int rounding);
VCVTPH2UDQ __m128i _mm_cvtph_epu32 (__m128h a);
VCVTPH2UDQ __m128i _mm_mask_cvtph_epu32 (__m128i src, __mmask8 k, __m128h a);
VCVTPH2UDQ __m128i _mm_maskz_cvtph_epu32 (__mmask8 k, __m128h a);
VCVTPH2UDQ __m256i _mm256_cvtph_epu32 (__m128h a);
VCVTPH2UDQ __m256i _mm256_mask_cvtph_epu32 (__m256i src, __mmask8 k, __m128h a);
VCVTPH2UDQ __m256i _mm256_maskz_cvtph_epu32 (__mmask8 k, __m128h a);
VCVTPH2UDQ __m512i _mm512_cvtph_epu32 (__m256h a);
VCVTPH2UDQ __m512i _mm512_mask_cvtph_epu32 (__m512i src, __mmask16 k, __m256h a);
VCVTPH2UDQ __m512i _mm512_maskz_cvtph_epu32 (__mmask16 k, __m256h a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
5-56
Vol. 2C
VCVTPH2UDQ—Convert Packed FP16 Values to Unsigned Doubleword Integers
INSTRUCTION SET REFERENCE, V
VCVTPH2UQQ—Convert Packed FP16 Values to Unsigned Quadword Integers
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.66.MAP5.W0 79 /r
A
V/V
AVX512-FP16
Convert two packed FP16 values in xmm2/m32/
VCVTPH2UQQ xmm1{k1}{z}, xmm2/
AVX512VL
m16bcst to two unsigned quadword integers, and
m32/m16bcst
store the result in xmm1 subject to writemask k1.
EVEX.256.66.MAP5.W0 79 /r
A
V/V
AVX512-FP16
Convert four packed FP16 values in xmm2/m64/
VCVTPH2UQQ ymm1{k1}{z}, xmm2/
AVX512VL
m16bcst to four unsigned quadword integers,
m64/m16bcst
and store the result in ymm1 subject to
writemask k1.
EVEX.512.66.MAP5.W0 79 /r
A
V/V
AVX512-FP16
Convert eight packed FP16 values in xmm2/
VCVTPH2UQQ zmm1{k1}{z}, xmm2/
m128/m16bcst to eight unsigned quadword
m128/m16bcst {er}
integers, and store the result in zmm1 subject to
writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Quarter
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed FP16 values in the source operand to unsigned quadword integers in destination
operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value is
returned.
The destination elements are updated according to the writemask.
Operation
VCVTPH2UQQ dest, src
VL = 128, 256 or 512
KL := VL / 64
IF *SRC is a register* and (VL = 512) and (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.fp16[0]
ELSE
tsrc := SRC.fp16[j]
DEST.qword[j] := Convert_fp16_to_unsigned_integer64(tsrc)
ELSE IF *zeroing*:
DEST.qword[j] := 0
// else dest.qword[j] remains unchanged
DEST[MAXVL-1:VL] := 0
VCVTPH2UQQ—Convert Packed FP16 Values to Unsigned Quadword Integers
Vol. 2C
5-57
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPH2UQQ __m512i _mm512_cvt_roundph_epu64 (__m128h a, int rounding);
VCVTPH2UQQ __m512i _mm512_mask_cvt_roundph_epu64 (__m512i src, __mmask8 k, __m128h a, int rounding);
VCVTPH2UQQ __m512i _mm512_maskz_cvt_roundph_epu64 (__mmask8 k, __m128h a, int rounding);
VCVTPH2UQQ __m128i _mm_cvtph_epu64 (__m128h a);
VCVTPH2UQQ __m128i _mm_mask_cvtph_epu64 (__m128i src, __mmask8 k, __m128h a);
VCVTPH2UQQ __m128i _mm_maskz_cvtph_epu64 (__mmask8 k, __m128h a);
VCVTPH2UQQ __m256i _mm256_cvtph_epu64 (__m128h a);
VCVTPH2UQQ __m256i _mm256_mask_cvtph_epu64 (__m256i src, __mmask8 k, __m128h a);
VCVTPH2UQQ __m256i _mm256_maskz_cvtph_epu64 (__mmask8 k, __m128h a);
VCVTPH2UQQ __m512i _mm512_cvtph_epu64 (__m128h a);
VCVTPH2UQQ __m512i _mm512_mask_cvtph_epu64 (__m512i src, __mmask8 k, __m128h a);
VCVTPH2UQQ __m512i _mm512_maskz_cvtph_epu64 (__mmask8 k, __m128h a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
5-58
Vol. 2C
VCVTPH2UQQ—Convert Packed FP16 Values to Unsigned Quadword Integers
INSTRUCTION SET REFERENCE, V
VCVTPH2UW—Convert Packed FP16 Values to Unsigned Word Integers
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.NP.MAP5.W0 7D /r
A
V/V
AVX512-FP16
Convert packed FP16 values in xmm2/m128/
VCVTPH2UW xmm1{k1}{z}, xmm2/
AVX512VL
m16bcst to unsigned word integers, and store the
m128/m16bcst
result in xmm1.
EVEX.256.NP.MAP5.W0 7D /r
A
V/V
AVX512-FP16
Convert packed FP16 values in ymm2/m256/
VCVTPH2UW ymm1{k1}{z}, ymm2/
AVX512VL
m16bcst to unsigned word integers, and store the
m256/m16bcst
result in ymm1.
EVEX.512.NP.MAP5.W0 7D /r
A
V/V
AVX512-FP16
Convert packed FP16 values in zmm2/m512/
VCVTPH2UW zmm1{k1}{z}, zmm2/
m16bcst to unsigned word integers, and store the
m512/m16bcst {er}
result in zmm1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed FP16 values in the source operand to unsigned word integers in the destination
operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value is
returned.
The destination elements are updated according to the writemask.
Operation
VCVTPH2UW dest, src
VL = 128, 256 or 512
KL := VL / 16
IF *SRC is a register* and (VL = 512) and (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.fp16[0]
ELSE
tsrc := SRC.fp16[j]
DEST.word[j] := Convert_fp16_to_unsigned_integer16(tsrc)
ELSE IF *zeroing*:
DEST.word[j] := 0
// else dest.word[j] remains unchanged
DEST[MAXVL-1:VL] := 0
VCVTPH2UW—Convert Packed FP16 Values to Unsigned Word Integers
Vol. 2C
5-59
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPH2UW __m512i _mm512_cvt_roundph_epu16 (__m512h a, int sae);
VCVTPH2UW __m512i _mm512_mask_cvt_roundph_epu16 (__m512i src, __mmask32 k, __m512h a, int sae);
VCVTPH2UW __m512i _mm512_maskz_cvt_roundph_epu16 (__mmask32 k, __m512h a, int sae);
VCVTPH2UW __m128i _mm_cvtph_epu16 (__m128h a);
VCVTPH2UW __m128i _mm_mask_cvtph_epu16 (__m128i src, __mmask8 k, __m128h a);
VCVTPH2UW __m128i _mm_maskz_cvtph_epu16 (__mmask8 k, __m128h a);
VCVTPH2UW __m256i _mm256_cvtph_epu16 (__m256h a);
VCVTPH2UW __m256i _mm256_mask_cvtph_epu16 (__m256i src, __mmask16 k, __m256h a);
VCVTPH2UW __m256i _mm256_maskz_cvtph_epu16 (__mmask16 k, __m256h a);
VCVTPH2UW __m512i _mm512_cvtph_epu16 (__m512h a);
VCVTPH2UW __m512i _mm512_mask_cvtph_epu16 (__m512i src, __mmask32 k, __m512h a);
VCVTPH2UW __m512i _mm512_maskz_cvtph_epu16 (__mmask32 k, __m512h a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
5-60
Vol. 2C
VCVTPH2UW—Convert Packed FP16 Values to Unsigned Word Integers
INSTRUCTION SET REFERENCE, V
VCVTPH2W—Convert Packed FP16 Values to Signed Word Integers
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.66.MAP5.W0 7D /r
A
V/V
AVX512-FP16
Convert packed FP16 values in xmm2/m128/
VCVTPH2W xmm1{k1}{z}, xmm2/
AVX512VL
m16bcst to signed word integers, and store the
m128/m16bcst
result in xmm1.
EVEX.256.66.MAP5.W0 7D /r
A
V/V
AVX512-FP16
Convert packed FP16 values in ymm2/m256/
VCVTPH2W ymm1{k1}{z}, ymm2/
AVX512VL
m16bcst to signed word integers, and store the
m256/m16bcst
result in ymm1.
EVEX.512.66.MAP5.W0 7D /r
A
V/V
AVX512-FP16
Convert packed FP16 values in zmm2/m512/
VCVTPH2W zmm1{k1}{z}, zmm2/
m16bcst to signed word integers, and store the
m512/m16bcst {er}
result in zmm1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed FP16 values in the source operand to signed word integers in the destination
operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value is
returned.
The destination elements are updated according to the writemask.
Operation
VCVTPH2W dest, src
VL = 128, 256 or 512
KL := VL / 16
IF *SRC is a register* and (VL = 512) and (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.fp16[0]
ELSE
tsrc := SRC.fp16[j]
DEST.word[j] := Convert_fp16_to_integer16(tsrc)
ELSE IF *zeroing*:
DEST.word[j] := 0
// else dest.word[j] remains unchanged
DEST[MAXVL-1:VL] := 0
VCVTPH2W—Convert Packed FP16 Values to Signed Word Integers
Vol. 2C
5-61
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPH2W __m512i _mm512_cvt_roundph_epi16 (__m512h a, int rounding);
VCVTPH2W __m512i _mm512_mask_cvt_roundph_epi16 (__m512i src, __mmask32 k, __m512h a, int rounding);
VCVTPH2W __m512i _mm512_maskz_cvt_roundph_epi16 (__mmask32 k, __m512h a, int rounding);
VCVTPH2W __m128i _mm_cvtph_epi16 (__m128h a);
VCVTPH2W __m128i _mm_mask_cvtph_epi16 (__m128i src, __mmask8 k, __m128h a);
VCVTPH2W __m128i _mm_maskz_cvtph_epi16 (__mmask8 k, __m128h a);
VCVTPH2W __m256i _mm256_cvtph_epi16 (__m256h a);
VCVTPH2W __m256i _mm256_mask_cvtph_epi16 (__m256i src, __mmask16 k, __m256h a);
VCVTPH2W __m256i _mm256_maskz_cvtph_epi16 (__mmask16 k, __m256h a);
VCVTPH2W __m512i _mm512_cvtph_epi16 (__m512h a);
VCVTPH2W __m512i _mm512_mask_cvtph_epi16 (__m512i src, __mmask32 k, __m512h a);
VCVTPH2W __m512i _mm512_maskz_cvtph_epi16 (__mmask32 k, __m512h a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
5-62
Vol. 2C
VCVTPH2W—Convert Packed FP16 Values to Signed Word Integers
INSTRUCTION SET REFERENCE, V
VCVTPS2PH—Convert Single-Precision FP Value to 16-bit FP Value
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
VEX.128.66.0F3A.W0 1D /r ib
A
V/V
F16C
Convert four packed single-precision floating-point values
VCVTPS2PH xmm1/m64, xmm2,
in xmm2 to packed half-precision (16-bit) floating-point
imm8
values in xmm1/m64. Imm8 provides rounding controls.
VEX.256.66.0F3A.W0 1D /r ib
A
V/V
F16C
Convert eight packed single-precision floating-point values
VCVTPS2PH xmm1/m128, ymm2,
in ymm2 to packed half-precision (16-bit) floating-point
imm8
values in xmm1/m128. Imm8 provides rounding controls.
EVEX.128.66.0F3A.W0 1D /r ib
B
V/V
AVX512VL
Convert four packed single-precision floating-point values
VCVTPS2PH xmm1/m64 {k1}{z},
AVX512F
in xmm2 to packed half-precision (16-bit) floating-point
xmm2, imm8
values in xmm1/m64. Imm8 provides rounding controls.
EVEX.256.66.0F3A.W0 1D /r ib
B
V/V
AVX512VL
Convert eight packed single-precision floating-point values
VCVTPS2PH xmm1/m128 {k1}{z},
AVX512F
in ymm2 to packed half-precision (16-bit) floating-point
ymm2, imm8
values in xmm1/m128. Imm8 provides rounding controls.
EVEX.512.66.0F3A.W0 1D /r ib
B
V/V
AVX512F
Convert sixteen packed single-precision floating-point
VCVTPS2PH ymm1/m256 {k1}{z},
values in zmm2 to packed half-precision (16-bit) floating-
zmm2{sae}, imm8
point values in ymm1/m256. Imm8 provides rounding
controls.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
NA
ModRM:r/m (w)
ModRM:reg (r)
Imm8
NA
B
Half Mem
ModRM:r/m (w)
ModRM:reg (r)
Imm8
NA
Description
Convert packed single-precision floating values in the source operand to half-precision (16-bit) floating-point
values and store to the destination operand. The rounding mode is specified using the immediate field (imm8).
Underflow results (i.e., tiny results) are converted to denormals. MXCSR.FTZ is ignored. If a source element is
denormal relative to the input format with DM masked and at least one of PM or UM unmasked; a SIMD exception
will be raised with DE, UE and PE set.
VCVTPS2PH xmm1/mem64, xmm2, imm8
127
96
95
64
63
32
31
0
VS3
VS2
VS1
VS0
xmm2
convert
convert
convert
convert
127
96
95
64
63
48
47
32
31
16
15
0
VH3
VH2
VH1
VH0
xmm1/mem64
Figure 5-7. VCVTPS2PH (128-bit Version)
The immediate byte defines several bit fields that control rounding operation. The effect and encoding of the RC
field are listed in Table 5-3.
VCVTPS2PH—Convert Single-Precision FP Value to 16-bit FP Value
Vol. 2C
5-63
INSTRUCTION SET REFERENCE, V
Table 5-3. Immediate Byte Encoding for 16-bit Floating-Point Conversion Instructions
Bits
Field Name/value
Description
Comment
Imm[1:0]
RC=00B
Round to nearest even
If Imm[2] = 0
RC=01B
Round down
RC=10B
Round up
RC=11B
Truncate
Imm[2]
MS1=0
Use imm[1:0] for rounding
Ignore MXCSR.RC
MS1=1
Use MXCSR.RC for rounding
Imm[7:3]
Ignored
Ignored by processor
VEX.128 version: The source operand is a XMM register. The destination operand is a XMM register or 64-bit
memory location. If the destination operand is a register then the upper bits (MAXVL-1:64) of corresponding
register are zeroed.
VEX.256 version: The source operand is a YMM register. The destination operand is a XMM register or 128-bit
memory location. If the destination operand is a register, the upper bits (MAXVL-1:128) of the corresponding desti-
nation register are zeroed.
Note: VEX.vvvv and EVEX.vvvv are reserved (must be 1111b).
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register. The destination operand is a
YMM/XMM/XMM (low 64-bits) register or a 256/128/64-bit memory location, conditionally updated with writemask
k1. Bits (MAXVL-1:256/128/64) of the corresponding destination register are zeroed.
Operation
vCvt_s2h(SRC1[31:0])
{
IF Imm[2] = 0
THEN
; using Imm[1:0] for rounding control, see Table 5-3
RETURN Cvt_Single_Precision_To_Half_Precision_FP_Imm(SRC1[31:0]);
ELSE
; using MXCSR.RC for rounding control
RETURN Cvt_Single_Precision_To_Half_Precision_FP_Mxcsr(SRC1[31:0]);
FI;
}
VCVTPS2PH (EVEX encoded versions) when dest is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 16
k := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] :=
vCvt_s2h(SRC[k+31:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+15:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0
5-64
Vol. 2C
VCVTPS2PH—Convert Single-Precision FP Value to 16-bit FP Value
INSTRUCTION SET REFERENCE, V
VCVTPS2PH (EVEX encoded versions) when dest is memory
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 16
k := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] :=
vCvt_s2h(SRC[k+31:k])
ELSE
*DEST[i+15:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VCVTPS2PH (VEX.256 encoded version)
DEST[15:0] := vCvt_s2h(SRC1[31:0]);
DEST[31:16] := vCvt_s2h(SRC1[63:32]);
DEST[47:32] := vCvt_s2h(SRC1[95:64]);
DEST[63:48] := vCvt_s2h(SRC1[127:96]);
DEST[79:64] := vCvt_s2h(SRC1[159:128]);
DEST[95:80] := vCvt_s2h(SRC1[191:160]);
DEST[111:96] := vCvt_s2h(SRC1[223:192]);
DEST[127:112] := vCvt_s2h(SRC1[255:224]);
DEST[MAXVL-1:128] := 0
VCVTPS2PH (VEX.128 encoded version)
DEST[15:0] := vCvt_s2h(SRC1[31:0]);
DEST[31:16] := vCvt_s2h(SRC1[63:32]);
DEST[47:32] := vCvt_s2h(SRC1[95:64]);
DEST[63:48] := vCvt_s2h(SRC1[127:96]);
DEST[MAXVL-1:64] := 0
Flags Affected
None
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPS2PH __m256i _mm512_cvtps_ph(__m512 a);
VCVTPS2PH __m256i _mm512_mask_cvtps_ph(__m256i s, __mmask16 k,__m512 a);
VCVTPS2PH __m256i _mm512_maskz_cvtps_ph(__mmask16 k,__m512 a);
VCVTPS2PH __m256i _mm512_cvt_roundps_ph(__m512 a, const int imm);
VCVTPS2PH __m256i _mm512_mask_cvt_roundps_ph(__m256i s, __mmask16 k,__m512 a, const int imm);
VCVTPS2PH __m256i _mm512_maskz_cvt_roundps_ph(__mmask16 k,__m512 a, const int imm);
VCVTPS2PH __m128i _mm256_mask_cvtps_ph(__m128i s, __mmask8 k,__m256 a);
VCVTPS2PH __m128i _mm256_maskz_cvtps_ph(__mmask8 k,__m256 a);
VCVTPS2PH __m128i _mm_mask_cvtps_ph(__m128i s, __mmask8 k,__m128 a);
VCVTPS2PH __m128i _mm_maskz_cvtps_ph(__mmask8 k,__m128 a);
VCVTPS2PH __m128i _mm_cvtps_ph ( __m128 m1, const int imm);
VCVTPS2PH __m128i _mm256_cvtps_ph(__m256 m1, const int imm);
SIMD Floating-Point Exceptions
Invalid, Underflow, Overflow, Precision, Denormal (if MXCSR.DAZ=0);
VCVTPS2PH—Convert Single-Precision FP Value to 16-bit FP Value
Vol. 2C
5-65
INSTRUCTION SET REFERENCE, V
Other Exceptions
VEX-encoded instructions, see Table 2-26, “Type 11 Class Exception Conditions” (do not report #AC);
EVEX-encoded instructions, see Table 2-60, “Type E11 Class Exception Conditions.”
Additionally:
#UD
If VEX.W=1.
#UD
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
5-66
Vol. 2C
VCVTPS2PH—Convert Single-Precision FP Value to 16-bit FP Value
INSTRUCTION SET REFERENCE, V
VCVTPS2PHX—Convert Packed Single Precision Floating-Point Values to Packed FP16 Values
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.66.MAP5.W0 1D /r
A
V/V
AVX512-FP16
Convert four packed single precision floating-
VCVTPS2PHX xmm1{k1}{z},
AVX512VL
point values in xmm2/m128/m32bcst to packed
xmm2/m128/m32bcst
FP16 values, and store the result in xmm1
subject to writemask k1.
EVEX.256.66.MAP5.W0 1D /r
A
V/V
AVX512-FP16
Convert eight packed single precision floating-
VCVTPS2PHX xmm1{k1}{z},
AVX512VL
point values in ymm2/m256/m32bcst to packed
ymm2/m256/m32bcst
FP16 values, and store the result in xmm1
subject to writemask k1.
EVEX.512.66.MAP5.W0 1D /r
A
V/V
AVX512-FP16
Convert sixteen packed single precision floating-
VCVTPS2PHX ymm1{k1}{z},
point values in zmm2 /m512/m32bcst to packed
zmm2/m512/m32bcst {er}
FP16 values, and store the result in ymm1
subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed single precision floating values in the source operand to FP16 values and stores to
the destination operand.
The VCVTPS2PHX instruction supports broadcasting.
This instruction uses MXCSR.DAZ for handling FP32 inputs. FP16 outputs can be normal or denormal numbers, and
are not conditionally flushed based on MXCSR settings.
Operation
VCVTPS2PHX dest, src (AVX512_FP16 load version with broadcast support)
VL = 128, 256, or 512
KL := VL / 32
IF *SRC is a register* and (VL == 512) and (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.fp32[0]
ELSE
tsrc := SRC.fp32[j]
DEST.fp16[j] := Convert_fp32_to_fp16(tsrc)
ELSE IF *zeroing*:
DEST.fp16[j] := 0
// else dest.fp16[j] remains unchanged
DEST[MAXVL-1:VL/2] := 0
VCVTPS2PHX—Convert Packed Single Precision Floating-Point Values to Packed FP16 Values
Vol. 2C
5-67
INSTRUCTION SET REFERENCE, V
Flags Affected
None
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPS2PHX __m256h _mm512_cvtx_roundps_ph (__m512 a, int rounding);
VCVTPS2PHX __m256h _mm512_mask_cvtx_roundps_ph (__m256h src, __mmask16 k, __m512 a, int rounding);
VCVTPS2PHX __m256h _mm512_maskz_cvtx_roundps_ph (__mmask16 k, __m512 a, int rounding);
VCVTPS2PHX __m128h _mm_cvtxps_ph (__m128 a);
VCVTPS2PHX __m128h _mm_mask_cvtxps_ph (__m128h src, __mmask8 k, __m128 a);
VCVTPS2PHX __m128h _mm_maskz_cvtxps_ph (__mmask8 k, __m128 a);
VCVTPS2PHX __m128h _mm256_cvtxps_ph (__m256 a);
VCVTPS2PHX __m128h _mm256_mask_cvtxps_ph (__m128h src, __mmask8 k, __m256 a);
VCVTPS2PHX __m128h _mm256_maskz_cvtxps_ph (__mmask8 k, __m256 a);
VCVTPS2PHX __m256h _mm512_cvtxps_ph (__m512 a);
VCVTPS2PHX __m256h _mm512_mask_cvtxps_ph (__m256h src, __mmask16 k, __m512 a);
VCVTPS2PHX __m256h _mm512_maskz_cvtxps_ph (__mmask16 k, __m512 a);
SIMD Floating-Point Exceptions
Invalid, Underflow, Overflow, Precision, Denormal (if MXCSR.DAZ=0);
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If VEX.W=1.
#UD
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
5-68
Vol. 2C
VCVTPS2PHX—Convert Packed Single Precision Floating-Point Values to Packed FP16 Values
INSTRUCTION SET REFERENCE, V
VCVTPS2UDQ—Convert Packed Single Precision Floating-Point Values to Packed Unsigned
Doubleword Integer Values
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.0F.W0 79 /r
A
V/V
AVX512VL
Convert four packed single precision floating-point
VCVTPS2UDQ xmm1 {k1}{z},
AVX512F
values from xmm2/m128/m32bcst to four packed
xmm2/m128/m32bcst
unsigned doubleword values in xmm1 subject to
writemask k1.
EVEX.256.0F.W0 79 /r
A
V/V
AVX512VL
Convert eight packed single precision floating-point
VCVTPS2UDQ ymm1 {k1}{z},
AVX512F
values from ymm2/m256/m32bcst to eight packed
ymm2/m256/m32bcst
unsigned doubleword values in ymm1 subject to
writemask k1.
EVEX.512.0F.W0 79 /r
A
V/V
AVX512F
Convert sixteen packed single precision floating-point
VCVTPS2UDQ zmm1 {k1}{z},
values from zmm2/m512/m32bcst to sixteen packed
zmm2/m512/m32bcst{er}
unsigned doubleword values in zmm1 subject to
writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts sixteen packed single precision floating-point values in the source operand to sixteen unsigned double-
word integers in the destination operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w - 1 is
returned, where w represents the number of bits in the destination format.
The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector
broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
VCVTPS2UDQ—Convert Packed Single Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values
Vol. 2C
5-69
INSTRUCTION SET REFERENCE, V
Operation
VCVTPS2UDQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
ELSE
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
FI;
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] :=
Convert_Single_Precision_Floating_Point_To_UInteger(SRC[i+31:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VCVTPS2UDQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no *
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i] :=
Convert_Single_Precision_Floating_Point_To_UInteger(SRC[31:0])
ELSE
DEST[i+31:i] :=
Convert_Single_Precision_Floating_Point_To_UInteger(SRC[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
5-70
Vol. 2C
VCVTPS2UDQ—Convert Packed Single Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPS2UDQ __m512i _mm512_cvtps_epu32( __m512 a);
VCVTPS2UDQ __m512i _mm512_mask_cvtps_epu32( __m512i s, __mmask16 k, __m512 a);
VCVTPS2UDQ __m512i _mm512_maskz_cvtps_epu32( __mmask16 k, __m512 a);
VCVTPS2UDQ __m512i _mm512_cvt_roundps_epu32( __m512 a, int r);
VCVTPS2UDQ __m512i _mm512_mask_cvt_roundps_epu32( __m512i s, __mmask16 k, __m512 a, int r);
VCVTPS2UDQ __m512i _mm512_maskz_cvt_roundps_epu32( __mmask16 k, __m512 a, int r);
VCVTPS2UDQ __m256i _mm256_cvtps_epu32( __m256d a);
VCVTPS2UDQ __m256i _mm256_mask_cvtps_epu32( __m256i s, __mmask8 k, __m256 a);
VCVTPS2UDQ __m256i _mm256_maskz_cvtps_epu32( __mmask8 k, __m256 a);
VCVTPS2UDQ __m128i _mm_cvtps_epu32( __m128 a);
VCVTPS2UDQ __m128i _mm_mask_cvtps_epu32( __m128i s, __mmask8 k, __m128 a);
VCVTPS2UDQ __m128i _mm_maskz_cvtps_epu32( __mmask8 k, __m128 a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VCVTPS2UDQ—Convert Packed Single Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values
Vol. 2C
5-71
INSTRUCTION SET REFERENCE, V
VCVTPS2QQ—Convert Packed Single Precision Floating-Point Values to Packed Signed
Quadword Integer Values
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F.W0 7B /r
A
V/V
AVX512VL
Convert two packed single precision floating-point values from
VCVTPS2QQ xmm1 {k1}{z},
AVX512DQ
xmm2/m64/m32bcst to two packed signed quadword values in
xmm2/m64/m32bcst
xmm1 subject to writemask k1.
EVEX.256.66.0F.W0 7B /r
A
V/V
AVX512VL
Convert four packed single precision floating-point values from
VCVTPS2QQ ymm1 {k1}{z},
AVX512DQ
xmm2/m128/m32bcst to four packed signed quadword values
xmm2/m128/m32bcst
in ymm1 subject to writemask k1.
EVEX.512.66.0F.W0 7B /r
A
V/V
AVX512DQ
Convert eight packed single precision floating-point values from
VCVTPS2QQ zmm1 {k1}{z},
ymm2/m256/m32bcst to eight packed signed quadword values
ymm2/m256/m32bcst{er}
in zmm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Half
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts eight packed single precision floating-point values in the source operand to eight signed quadword inte-
gers in the destination operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value
(2w-1, where w represents the number of bits in the destination format) is returned.
The source operand is a YMM/XMM/XMM (low 64- bits) register or a 256/128/64-bit memory location. The destina-
tion operation is a ZMM/YMM/XMM register conditionally updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VCVTPS2QQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL == 512) AND (EVEX.b == 1)
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
ELSE
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
FI;
FOR j := 0 TO KL-1
i := j * 64
k := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] :=
Convert_Single_Precision_To_QuadInteger(SRC[k+31:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
5-72
Vol. 2C
VCVTPS2QQ—Convert Packed Single Precision Floating-Point Values to Packed Signed Quadword Integer Values
INSTRUCTION SET REFERENCE, V
ENDFOR
DEST[MAXVL-1:VL] := 0
VCVTPS2QQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
k := j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[i+63:i] :=
Convert_Single_Precision_To_QuadInteger(SRC[31:0])
ELSE
DEST[i+63:i] :=
Convert_Single_Precision_To_QuadInteger(SRC[k+31:k])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPS2QQ __m512i _mm512_cvtps_epi64( __m512 a);
VCVTPS2QQ __m512i _mm512_mask_cvtps_epi64( __m512i s, __mmask16 k, __m512 a);
VCVTPS2QQ __m512i _mm512_maskz_cvtps_epi64( __mmask16 k, __m512 a);
VCVTPS2QQ __m512i _mm512_cvt_roundps_epi64( __m512 a, int r);
VCVTPS2QQ __m512i _mm512_mask_cvt_roundps_epi64( __m512i s, __mmask16 k, __m512 a, int r);
VCVTPS2QQ __m512i _mm512_maskz_cvt_roundps_epi64( __mmask16 k, __m512 a, int r);
VCVTPS2QQ __m256i _mm256_cvtps_epi64( __m256 a);
VCVTPS2QQ __m256i _mm256_mask_cvtps_epi64( __m256i s, __mmask8 k, __m256 a);
VCVTPS2QQ __m256i _mm256_maskz_cvtps_epi64( __mmask8 k, __m256 a);
VCVTPS2QQ __m128i _mm_cvtps_epi64( __m128 a);
VCVTPS2QQ __m128i _mm_mask_cvtps_epi64( __m128i s, __mmask8 k, __m128 a);
VCVTPS2QQ __m128i _mm_maskz_cvtps_epi64( __mmask8 k, __m128 a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VCVTPS2QQ—Convert Packed Single Precision Floating-Point Values to Packed Signed Quadword Integer Values
Vol. 2C
5-73
INSTRUCTION SET REFERENCE, V
VCVTPS2UQQ—Convert Packed Single Precision Floating-Point Values to Packed Unsigned
Quadword Integer Values
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F.W0 79 /r
A
V/V
AVX512VL
Convert two packed single precision floating-point values from
VCVTPS2UQQ xmm1 {k1}{z},
AVX512DQ
zmm2/m64/m32bcst to two packed unsigned quadword values
xmm2/m64/m32bcst
in zmm1 subject to writemask k1.
EVEX.256.66.0F.W0 79 /r
A
V/V
AVX512VL
Convert four packed single precision floating-point values from
VCVTPS2UQQ ymm1 {k1}{z},
AVX512DQ
xmm2/m128/m32bcst to four packed unsigned quadword
xmm2/m128/m32bcst
values in ymm1 subject to writemask k1.
EVEX.512.66.0F.W0 79 /r
A
V/V
AVX512DQ
Convert eight packed single precision floating-point values from
VCVTPS2UQQ zmm1 {k1}{z},
ymm2/m256/m32bcst to eight packed unsigned quadword
ymm2/m256/m32bcst{er}
values in zmm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Half
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts up to eight packed single precision floating-point values in the source operand to unsigned quadword
integers in the destination operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w - 1 is
returned, where w represents the number of bits in the destination format.
The source operand is a YMM/XMM/XMM (low 64- bits) register or a 256/128/64-bit memory location. The destina-
tion operation is a ZMM/YMM/XMM register conditionally updated with writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VCVTPS2UQQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL == 512) AND (EVEX.b == 1)
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
ELSE
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
FI;
FOR j := 0 TO KL-1
i := j * 64
k := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] :=
Convert_Single_Precision_To_UQuadInteger(SRC[k+31:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
5-74
Vol. 2C
VCVTPS2UQQ—Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values
INSTRUCTION SET REFERENCE, V
ENDFOR
DEST[MAXVL-1:VL] := 0
VCVTPS2UQQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
k := j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[i+63:i] :=
Convert_Single_Precision_To_UQuadInteger(SRC[31:0])
ELSE
DEST[i+63:i] :=
Convert_Single_Precision_To_UQuadInteger(SRC[k+31:k])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPS2UQQ __m512i _mm512_cvtps_epu64( __m512 a);
VCVTPS2UQQ __m512i _mm512_mask_cvtps_epu64( __m512i s, __mmask16 k, __m512 a);
VCVTPS2UQQ __m512i _mm512_maskz_cvtps_epu64( __mmask16 k, __m512 a);
VCVTPS2UQQ __m512i _mm512_cvt_roundps_epu64( __m512 a, int r);
VCVTPS2UQQ __m512i _mm512_mask_cvt_roundps_epu64( __m512i s, __mmask16 k, __m512 a, int r);
VCVTPS2UQQ __m512i _mm512_maskz_cvt_roundps_epu64( __mmask16 k, __m512 a, int r);
VCVTPS2UQQ __m256i _mm256_cvtps_epu64( __m256 a);
VCVTPS2UQQ __m256i _mm256_mask_cvtps_epu64( __m256i s, __mmask8 k, __m256 a);
VCVTPS2UQQ __m256i _mm256_maskz_cvtps_epu64( __mmask8 k, __m256 a);
VCVTPS2UQQ __m128i _mm_cvtps_epu64( __m128 a);
VCVTPS2UQQ __m128i _mm_mask_cvtps_epu64( __m128i s, __mmask8 k, __m128 a);
VCVTPS2UQQ __m128i _mm_maskz_cvtps_epu64( __mmask8 k, __m128 a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VCVTPS2UQQ—Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values
Vol. 2C
5-75
INSTRUCTION SET REFERENCE, V
VCVTQQ2PD—Convert Packed Quadword Integers to Packed Double Precision Floating-Point
Values
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.F3.0F.W1 E6 /r
A
V/V
AVX512VL
Convert two packed quadword integers from
VCVTQQ2PD xmm1 {k1}{z},
AVX512DQ
xmm2/m128/m64bcst to packed double precision floating-
xmm2/m128/m64bcst
point values in xmm1 with writemask k1.
EVEX.256.F3.0F.W1 E6 /r
A
V/V
AVX512VL
Convert four packed quadword integers from
VCVTQQ2PD ymm1 {k1}{z},
AVX512DQ
ymm2/m256/m64bcst to packed double precision floating-
ymm2/m256/m64bcst
point values in ymm1 with writemask k1.
EVEX.512.F3.0F.W1 E6 /r
A
V/V
AVX512DQ
Convert eight packed quadword integers from
VCVTQQ2PD zmm1 {k1}{z},
zmm2/m512/m64bcst to eight packed double precision
zmm2/m512/m64bcst{er}
floating-point values in zmm1 with writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts packed quadword integers in the source operand (second operand) to packed double precision floating-
point values in the destination operand (first operand).
The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operation
is a ZMM/YMM/XMM register conditionally updated with writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VCVTQQ2PD (EVEX2 encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL == 512) AND (EVEX.b == 1)
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
ELSE
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
FI;
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] :=
Convert_QuadInteger_To_Double_Precision_Floating_Point(SRC[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
5-76
Vol. 2C
VCVTQQ2PD—Convert Packed Quadword Integers to Packed Double Precision Floating-Point Values