Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023)

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

0, 1, 2, 3, 4, 6

Shared

The IA32_MC0_MISC MSR is either not implemented or does not contain additional information if the

MISCV flag in the IA32_MC0_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-

protection exception.

IA32_MC1_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

0, 1, 2, 3, 4, 6

Shared

IA32_MC1_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

0, 1, 2, 3, 4, 6

Shared

IA32_MC1_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

0, 1, 2, 3, 4, 6

Shared

The IA32_MC1_ADDR register is either not implemented or contains no address if the ADDRV flag in

the IA32_MC1_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-

protection exception.

IA32_MC1_MISC

See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Shared

The IA32_MC1_MISC MSR is either not implemented or does not contain additional information if the

MISCV flag in the IA32_MC1_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-

protection exception.

IA32_MC2_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

0, 1, 2, 3, 4, 6

Shared

IA32_MC2_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

0, 1, 2, 3, 4, 6

Shared

IA32_MC2_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in

the IA32_MC2_STATUS register is clear. When not implemented in the processor, all reads and writes

to this MSR will cause a general-protection exception.

IA32_MC2_MISC

See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

The IA32_MC2_MISC MSR is either not implemented or does not contain additional information if the

MISCV flag in the IA32_MC2_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-

protection exception.

IA32_MC3_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

0, 1, 2, 3, 4, 6

Shared

IA32_MC3_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

0, 1, 2, 3, 4, 6

Shared

IA32_MC3_ADDR

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

0, 1, 2, 3, 4, 6

Shared

The IA32_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in

the IA32_MC3_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-

protection exception.

IA32_MC3_MISC

See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

0, 1, 2, 3, 4, 6

Shared

The IA32_MC3_MISC MSR is either not implemented or does not contain additional information if the

MISCV flag in the IA32_MC3_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-

protection exception.

IA32_MC4_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

0, 1, 2, 3, 4, 6

Shared

IA32_MC4_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

0, 1, 2, 3, 4, 6

Shared

IA32_MC4_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in

the IA32_MC4_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-

protection exception.

IA32_MC4_MISC

See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

The IA32_MC2_MISC MSR is either not implemented or does not contain additional information if the

MISCV flag in the IA32_MC4_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-

protection exception.

IA32_VMX_BASIC

Reporting Register of Basic VMX Capabilities (R/O)

3, 4, 6

Unique

See Table 2-2 and Appendix A.1, “Basic VMX Information.”

IA32_VMX_PINBASED_CTLS

Capability Reporting Register of Pin-Based VM-Execution Controls (R/O)

3, 4, 6

Unique

See Table 2-2 and Appendix A.3, “VM-Execution Controls.”

IA32_VMX_PROCBASED_CTLS

Capability Reporting Register of Primary Processor-Based VM-Execution Controls (R/O)

3, 4, 6

Unique

See Appendix A.3, “VM-Execution Controls,” and Table 2-2.

IA32_VMX_EXIT_CTLS

Capability Reporting Register of VM-Exit Controls (R/O)

3, 4, 6

Unique

See Appendix A.4, “VM-Exit Controls,” and Table 2-2.

IA32_VMX_ENTRY_CTLS

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

Capability Reporting Register of VM-Entry Controls (R/O)

3, 4, 6

Unique

See Appendix A.5, “VM-Entry Controls,” and Table 2-2.

IA32_VMX_MISC

Reporting Register of Miscellaneous VMX Capabilities (R/O)

3, 4, 6

Unique

See Appendix A.6, “Miscellaneous Data,” and Table 2-2.

IA32_VMX_CR0_FIXED0

Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)

3, 4, 6

Unique

See Appendix A.7, “VMX-Fixed Bits in CR0,” and Table 2-2.

IA32_VMX_CR0_FIXED1

Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)

3, 4, 6

Unique

See Appendix A.7, “VMX-Fixed Bits in CR0,” and Table 2-2.

IA32_VMX_CR4_FIXED0

Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)

3, 4, 6

Unique

See Appendix A.8, “VMX-Fixed Bits in CR4,” and Table 2-2.

IA32_VMX_CR4_FIXED1

Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)

3, 4, 6

Unique

See Appendix A.8, “VMX-Fixed Bits in CR4,” and Table 2-2.

IA32_VMX_VMCS_ENUM

Capability Reporting Register of VMCS Field Enumeration (R/O)

3, 4, 6

Unique

See Appendix A.9, “VMCS Enumeration,” and Table 2-2.

IA32_VMX_PROCBASED_CTLS2

Capability Reporting Register of Secondary Processor-Based VM-Execution Controls (R/O)

3, 4, 6

Unique

See Appendix A.3, “VM-Execution Controls,” and Table 2-2.

IA32_DS_AREA

DS Save Area (R/W)

0, 1, 2, 3, 4, 6

Unique

See Table 2-2 and Section 20.6.3.4, “Debug Store (DS) Mechanism.”

MSR_LASTBRANCH_0_FROM_IP

Last Branch Record 0 (R/W)

3, 4, 6

Unique

One of 16 pairs of last branch record registers on the last branch record stack (680H-68FH). This part

of the stack contains pointers to the source instruction for one of the last 16 branches, exceptions, or

interrupts taken by the processor.

The MSRs at 680H-68FH, 6C0H-6CfH are not available in processor releases before family 0FH, model

03H. These MSRs replace MSRs previously located at 1DBH-1DEH. which performed the same function

for early releases.

See Section 18.12, “Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based

on Skylake Microarchitecture.”

MSR_LASTBRANCH_1_FROM_IP

Last Branch Record 1

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 680H.

MSR_LASTBRANCH_2_FROM_IP

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

Last Branch Record 2

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 680H.

MSR_LASTBRANCH_3_FROM_IP

Last Branch Record 3

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 680H.

MSR_LASTBRANCH_4_FROM_IP

Last Branch Record 4

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 680H.

MSR_LASTBRANCH_5_FROM_IP

Last Branch Record 5

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 680H.

MSR_LASTBRANCH_6_FROM_IP

Last Branch Record 6

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 680H.

MSR_LASTBRANCH_7_FROM_IP

Last Branch Record 7

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 680H.

MSR_LASTBRANCH_8_FROM_IP

Last Branch Record 8

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 680H.

MSR_LASTBRANCH_9_FROM_IP

Last Branch Record 9

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 680H.

MSR_LASTBRANCH_10_FROM_IP

Last Branch Record 10

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 680H.

MSR_LASTBRANCH_11_FROM_IP

Last Branch Record 11

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 680H.

MSR_LASTBRANCH_12_FROM_IP

Last Branch Record 12

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 680H.

MSR_LASTBRANCH_13_FROM_IP

Last Branch Record 13

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 680H.

MSR_LASTBRANCH_14_FROM_IP

Last Branch Record 14

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 680H.

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Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

MSR_LASTBRANCH_15_FROM_IP

Last Branch Record 15

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 680H.

MSR_LASTBRANCH_0_TO_IP

Last Branch Record 0 (R/W)

3, 4, 6

Unique

One of 16 pairs of last branch record registers on the last branch record stack (6C0H-6CFH). This part

of the stack contains pointers to the destination instruction for one of the last 16 branches,

exceptions, or interrupts that the processor took.

See Section 18.12, “Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based

on Skylake Microarchitecture.”

MSR_LASTBRANCH_1_TO_IP

Last Branch Record 1

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 6C0H.

MSR_LASTBRANCH_2_TO_IP

Last Branch Record 2

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 6C0H.

MSR_LASTBRANCH_3_TO_IP

Last Branch Record 3

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 6C0H.

MSR_LASTBRANCH_4_TO_IP

Last Branch Record 4

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 6C0H.

MSR_LASTBRANCH_5_TO_IP

Last Branch Record 5

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 6C0H.

MSR_LASTBRANCH_6_TO_IP

Last Branch Record 6

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 6C0H.

MSR_LASTBRANCH_7_TO_IP

Last Branch Record 7

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 6C0H.

MSR_LASTBRANCH_8_TO_IP

Last Branch Record 8

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 6C0H.

MSR_LASTBRANCH_9_TO_IP

Last Branch Record 9

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 6C0H.

MSR_LASTBRANCH_10_TO_IP

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

Last Branch Record 10

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 6C0H.

MSR_LASTBRANCH_11_TO_IP

Last Branch Record 11

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 6C0H.

MSR_LASTBRANCH_12_TO_IP

Last Branch Record 12

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 6C0H.

MSR_LASTBRANCH_13_TO_IP

Last Branch Record 13

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 6C0H.

MSR_LASTBRANCH_14_TO_IP

Last Branch Record 14

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 6C0H.

MSR_LASTBRANCH_15_TO_IP

Last Branch Record 15

3, 4, 6

Unique

See description of MSR_LASTBRANCH_0 at 6C0H.

IA32_EFER

Extended Feature Enables

3, 4, 6

Unique

See Table 2-2.

IA32_STAR

System Call Target Address (R/W)

3, 4, 6

Unique

See Table 2-2.

IA32_LSTAR

IA-32e Mode System Call Target Address (R/W)

3, 4, 6

Unique

See Table 2-2.

IA32_FMASK

System Call Flag Mask (R/W)

3, 4, 6

Unique

See Table 2-2.

IA32_FS_BASE

Map of BASE Address of FS (R/W)

3, 4, 6

Unique

See Table 2-2.

IA32_GS_BASE

Map of BASE Address of GS (R/W)

3, 4, 6

Unique

See Table 2-2.

IA32_KERNEL_GS_BASE

Swap Target of BASE Address of GS (R/W)

3, 4, 6

Unique

See Table 2-2.

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Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)

Model

Shared/

Bit Description

Availability

Unique¹

NOTES

1. For HT-enabled processors, there may be more than one logical processors per physical unit. If an MSR is Shared, this means that

one MSR is shared between logical processors. If an MSR is unique, this means that each logical processor has its own MSR.

2.19.1 MSRs Unique to Intel^® Xeon^® Processor MP with L3 Cache

The MSRs listed in Table 2-59 apply to Intel^® Xeon^® Processor MP with up to 8MB level three cache. These proces-

sors can be detected by enumerating the deterministic cache parameter leaf of CPUID instruction (with EAX = 4 as

input) to detect the presence of the third level cache, and with CPUID reporting family encoding 0FH, model

encoding 3 or 4 (see CPUID instruction for more details).

Table 2-59. MSRs Unique to 64-bit Intel® Xeon® Processor MP with Up to an 8 MB L3 Cache

Model

Shared/

Availability

Unique

MSR_IFSB_BUSQ0

IFSB BUSQ Event Control and Counter Register (R/W)

3, 4

Shared

See Section 20.6.6, “Performance Monitoring on 64-bit Intel® Xeon® Processor MP with Up to 8-MByte

L3 Cache.”

MSR_IFSB_BUSQ1

IFSB BUSQ Event Control and Counter Register (R/W)

3, 4

Shared

MSR_IFSB_SNPQ0

IFSB SNPQ Event Control and Counter Register (R/W)

3, 4

Shared

See Section 20.6.6, “Performance Monitoring on 64-bit Intel® Xeon® Processor MP with Up to 8-MByte

L3 Cache.”

MSR_IFSB_SNPQ1

IFSB SNPQ Event Control and Counter Register (R/W)

3, 4

Shared

MSR_EFSB_DRDY0

EFSB DRDY Event Control and Counter Register (R/W)

3, 4

Shared

See Section 20.6.6, “Performance Monitoring on 64-bit Intel® Xeon® Processor MP with Up to 8-MByte

L3 Cache.”

MSR_EFSB_DRDY1

EFSB DRDY Event Control and Counter Register (R/W)

3, 4

Shared

MSR_IFSB_CTL6

IFSB Latency Event Control Register (R/W)

3, 4

Shared

See Section 20.6.6, “Performance Monitoring on 64-bit Intel® Xeon® Processor MP with Up to 8-MByte

L3 Cache.”

MSR_IFSB_CNTR7

IFSB Latency Event Counter Register (R/W)

3, 4

Shared

See Section 20.6.6, “Performance Monitoring on 64-bit Intel® Xeon® Processor MP with Up to 8-MByte

L3 Cache.”

The MSRs listed in Table 2-60 apply to Intel^® Xeon^® Processor 7100 series. These processors can be detected by

enumerating the deterministic cache parameter leaf of CPUID instruction (with EAX = 4 as input) to detect the

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MODEL-SPECIFIC REGISTERS (MSRS)

presence of the third level cache, and with CPUID reporting family encoding 0FH, model encoding 6 (See CPUID

instruction for more details.). The performance monitoring MSRs listed in Table 2-60 are shared between logical

processors in the same core, but are replicated for each core.

Table 2-60. MSRs Unique to Intel® Xeon® Processor 7100 Series

Model

Shared/

Availability

Unique

MSR_EMON_L3_CTR_CTL0

GBUSQ Event Control and Counter Register (R/W)

Shared

See Section 20.6.6, “Performance Monitoring on 64-bit Intel® Xeon® Processor MP with Up to 8-MByte L3

Cache.”

MSR_EMON_L3_CTR_CTL1

GBUSQ Event Control and Counter Register (R/W)

Shared

MSR_EMON_L3_CTR_CTL2

GSNPQ Event Control and Counter Register (R/W)

Shared

See Section 20.6.6, “Performance Monitoring on 64-bit Intel® Xeon® Processor MP with Up to 8-MByte L3

Cache.”

MSR_EMON_L3_CTR_CTL3

GSNPQ Event Control and Counter Register (R/W)

Shared

MSR_EMON_L3_CTR_CTL4

FSB Event Control and Counter Register (R/W)

Shared

See Section 20.6.6, “Performance Monitoring on 64-bit Intel® Xeon® Processor MP with Up to 8-MByte L3

Cache.”

MSR_EMON_L3_CTR_CTL5

FSB Event Control and Counter Register (R/W)

Shared

MSR_EMON_L3_CTR_CTL6

FSB Event Control and Counter Register (R/W)

Shared

MSR_EMON_L3_CTR_CTL7

FSB Event Control and Counter Register (R/W)

Shared

2.20

MSRS IN INTEL® CORE™ SOLO AND INTEL® CORE™ DUO PROCESSORS

Model-specific registers (MSRs) for Intel Core Solo, Intel Core Duo processors, and Dual-core Intel Xeon processor

LV are listed in Table 2-61. The column “Shared/Unique” applies to Intel Core Duo processor. “Unique” means each

processor core has a separate MSR, or a bit field in an MSR governs only a core independently. “Shared” means the

MSR or the bit field in an MSR address governs the operation of both processor cores.

Table 2-61. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV

Shared/

Bit Description

Unique

P5_MC_ADDR

See Section 2.23, “MSRs in Pentium Processors,” and Table 2-2.

Unique

P5_MC_TYPE

See Section 2.23, “MSRs in Pentium Processors,” and Table 2-2.

Unique

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Table 2-61. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)

Shared/

Bit Description

Unique

IA32_MONITOR_FILTER_SIZE

See Section 9.10.5, “Monitor/Mwait Address Range Determination,” and Table 2-2.

Unique

IA32_TIME_STAMP_COUNTER

See Section 18.17, “Time-Stamp Counter,” and Table 2-2.

Unique

IA32_PLATFORM_ID

Platform ID (R)

Shared

See Table 2-2. The operating system can use this MSR to determine “slot” information for the processor and the proper

microcode update to load.

IA32_APIC_BASE

See Section 11.4.4, “Local APIC Status and Location,” and Table 2-2.

Unique

MSR_EBL_CR_POWERON

Processor Hard Power-On Configuration (R/W)

Shared

Enables and disables processor features; (R) indicates current processor configuration.

Reserved.

Data Error Checking Enable (R/W)

1 = Enabled; 0 = Disabled.

Note: Not all processor implements R/W.

Response Error Checking Enable (R/W)

1 = Enabled; 0 = Disabled.

Note: Not all processor implements R/W.

MCERR# Drive Enable (R/W)

1 = Enabled; 0 = Disabled.

Note: Not all processor implements R/W.

Address Parity Enable (R/W)

1 = Enabled; 0 = Disabled.

Note: Not all processor implements R/W.

6: 5

Reserved.

BINIT# Driver Enable (R/W)

1 = Enabled; 0 = Disabled.

Note: Not all processor implements R/W.

Output Tri-state Enabled (R/O)

1 = Enabled; 0 = Disabled.

Execute BIST (R/O)

1 = Enabled; 0 = Disabled.

MCERR# Observation Enabled (R/O)

1 = Enabled; 0 = Disabled.

Reserved.

BINIT# Observation Enabled (R/O)

1 = Enabled; 0 = Disabled.

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-61. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)

Shared/

Bit Description

Unique

Reserved

1 MByte Power on Reset Vector (R/O)

1 = 1 MByte; 0 = 4 GBytes

Reserved.

17:16

APIC Cluster ID (R/O)

System Bus Frequency (R/O)

0 = 100 MHz.

1 = Reserved.

Reserved.

21: 20

Symmetric Arbitration ID (R/O)

26:22

Clock Frequency Ratio (R/O)

IA32_FEATURE_CONTROL

Control Features in IA-32 Processor (R/W)

Unique

See Table 2-2.

MSR_LASTBRANCH_0

Last Branch Record 0 (R/W)

Unique

One of 8 last branch record registers on the last branch record stack: bits 31-0 hold the ‘from’ address and bits 63-32

hold the ‘to’ address. See also:

• Last Branch Record Stack TOS at 1C9H.

• Section 18.15, “Last Branch, Interrupt, and Exception Recording (Pentium M Processors).”

MSR_LASTBRANCH_1

Last Branch Record 1 (R/W)

Unique

See description of MSR_LASTBRANCH_0.

MSR_LASTBRANCH_2

Last Branch Record 2 (R/W)

Unique

See description of MSR_LASTBRANCH_0.

MSR_LASTBRANCH_3

Last Branch Record 3 (R/W)

Unique

See description of MSR_LASTBRANCH_0.

MSR_LASTBRANCH_4

Last Branch Record 4 (R/W)

Unique

See description of MSR_LASTBRANCH_0.

MSR_LASTBRANCH_5

Last Branch Record 5 (R/W)

Unique

See description of MSR_LASTBRANCH_0.

MSR_LASTBRANCH_6

Last Branch Record 6 (R/W)

Unique

See description of MSR_LASTBRANCH_0.

MSR_LASTBRANCH_7

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Table 2-61. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)

Shared/

Bit Description

Unique

Last Branch Record 7 (R/W)

Unique

See description of MSR_LASTBRANCH_0.

IA32_BIOS_UPDT_TRIG

BIOS Update Trigger Register (W)

Unique

See Table 2-2.

IA32_BIOS_SIGN_ID

BIOS Update Signature ID (R/W)

Unique

See Table 2-2.

IA32_PMC0

Performance Counter Register

Unique

See Table 2-2.

IA32_PMC1

Performance Counter Register

Unique

See Table 2-2.

MSR_FSB_FREQ

Scaleable Bus Speed (R/O)

Shared

This field indicates the scalable bus clock speed.

2:0

•

101B: 100 MHz (FSB 400)

•

001B: 133 MHz (FSB 533)

•

011B: 167 MHz (FSB 667)

133.33 MHz should be utilized if performing calculation with System Bus Speed

when encoding is 101B.

166.67 MHz should be utilized if performing calculation with System Bus Speed

when encoding is 001B.

63:3

Reserved.

IA32_MPERF

Maximum Performance Frequency Clock Count (R/W)

Unique

See Table 2-2.

IA32_APERF

Actual Performance Frequency Clock Count (R/W)

Unique

See Table 2-2.

IA32_MTRRCAP

See Table 2-2.

Unique

MSR_BBL_CR_CTL3

Control Register 3

Shared

Used to configure the L2 Cache.

L2 Hardware Enabled (R/O)

1 = If the L2 is hardware-enabled.

0 = Indicates if the L2 is hardware-disabled.

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Table 2-61. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)

Shared/

Bit Description

Unique

7:1

Reserved.

L2 Enabled (R/W)

1 = L2 cache has been initialized.

0 = Disabled (default).

Until this bit is set the processor will not respond to the WBINVD instruction or

the assertion of the FLUSH# input.

22:9

Reserved.

L2 Not Present (R/O)

0 = L2 Present.

1 = L2 Not Present.

63:24

Reserved.

IA32_SYSENTER_CS

See Table 2-2.

Unique

IA32_SYSENTER_ESP

See Table 2-2.

Unique

IA32_SYSENTER_EIP

See Table 2-2.

Unique

IA32_MCG_CAP

See Table 2-2.

Unique

IA32_MCG_STATUS

Global Machine Check Status

Unique

RIPV

When set, this bit indicates that the instruction addressed by the instruction

pointer pushed on the stack (when the machine check was generated) can be

used to restart the program. If this bit is cleared, the program cannot be reliably

restarted.

EIPV

When set, this bit indicates that the instruction addressed by the instruction

pointer pushed on the stack (when the machine check was generated) is directly

associated with the error.

MCIP

When set, this bit indicates that a machine check has been generated. If a second

machine check is detected while this bit is still set, the processor enters a

shutdown state. Software should write this bit to 0 after processing a machine

check exception.

63:3

Reserved

IA32_PERFEVTSEL0

See Table 2-2.

Unique

IA32_PERFEVTSEL1

See Table 2-2.

Unique

IA32_PERF_STATUS

2-484 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-61. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)

Shared/

Bit Description

Unique

See Table 2-2.

Shared

IA32_PERF_CTL

See Table 2-2.

Unique

IA32_CLOCK_MODULATION

Clock Modulation (R/W)

Unique

See Table 2-2.

IA32_THERM_INTERRUPT

Thermal Interrupt Control (R/W)

Unique

See Table 2-2 and Section 15.8.2, “Thermal Monitor.”

IA32_THERM_STATUS

Thermal Monitor Status (R/W)

Unique

See Table 2-2 and Section 15.8.2, “Thermal Monitor”.

MSR_THERM2_CTL

Thermal Monitor 2 Control

Unique

15:0

Reserved.

TM_SELECT (R/W)

Mode of automatic thermal monitor:

0 = Thermal Monitor 1 (thermally-initiated on-die modulation of the stop-clock

duty cycle)

1 = Thermal Monitor 2 (thermally-initiated frequency transitions)

If bit 3 of the IA32_MISC_ENABLE register is cleared, TM_SELECT has no effect.

Neither TM1 nor TM2 will be enabled.

63:16

Reserved.

IA32_MISC_ENABLE

Enable Miscellaneous Processor Features (R/W)

Allows a variety of processor functions to be enabled and disabled.

2:0

Reserved.

Automatic Thermal Control Circuit Enable (R/W)

Unique

See Table 2-2.

6:4

Reserved.

Performance Monitoring Available (R)

Shared

See Table 2-2.

9:8

Reserved.

FERR# Multiplexing Enable (R/W)

Shared

1 = FERR# asserted by the processor to indicate a pending break event within

the processor

0 = Indicates compatible FERR# signaling behavior

This bit must be set to 1 to support XAPIC interrupt model usage.

Branch Trace Storage Unavailable (R/O)

Shared

See Table 2-2.

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Table 2-61. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)

Shared/

Bit Description

Unique

Reserved.

TM2 Enable (R/W)

Shared

When this bit is set (1) and the thermal sensor indicates that the die temperature

is at the pre-determined threshold, the Thermal Monitor 2 mechanism is

engaged. TM2 will reduce the bus to core ratio and voltage according to the value

last written to MSR_THERM2_CTL bits 15:0.

When this bit is clear (0, default), the processor does not change the VID signals

or the bus to core ratio when the processor enters a thermal managed state.

If the TM2 feature flag (ECX[8]) is not set to 1 after executing CPUID with EAX =

1, then this feature is not supported and BIOS must not alter the contents of this

bit location. The processor is operating out of spec if both this bit and the TM1

bit are set to disabled states.

15:14

Reserved.

Enhanced Intel SpeedStep Technology Enable (R/W)

Shared

1 = Enhanced Intel SpeedStep Technology enabled

ENABLE MONITOR FSM (R/W)

Shared

See Table 2-2.

Reserved.

Limit CPUID Maxval (R/W)

Shared

See Table 2-2.

Setting this bit may cause behavior in software that depends on the availability

of CPUID leaves greater than 2.

33:23

Reserved.

XD Bit Disable (R/W)

Shared

See Table 2-3.

63:35

Reserved.

MSR_LASTBRANCH_TOS

Last Branch Record Stack TOS (R/W)

Unique

Contains an index (bits 0-3) that points to the MSR containing the most recent branch record.

See MSR_LASTBRANCH_0_FROM_IP (at 40H).

IA32_DEBUGCTL

Debug Control (R/W)

Unique

Controls how several debug features are used. Bit definitions are discussed in Table 2-2.

MSR_LER_FROM_LIP

Last Exception Record From Linear IP (R)

Unique

Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was

generated or the last interrupt that was handled.

MSR_LER_TO_LIP

Last Exception Record To Linear IP (R)

Unique

This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last

exception that was generated or the last interrupt that was handled.

MTRRphysBase0

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-61. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)

Shared/

Bit Description

Unique

Memory Type Range Registers

Unique

MTRRphysMask0

Memory Type Range Registers

Unique

MTRRphysBase1

Memory Type Range Registers

Unique

MTRRphysMask1

Memory Type Range Registers

Unique

MTRRphysBase2

Memory Type Range Registers

Unique

MTRRphysMask2

Memory Type Range Registers

Unique

MTRRphysBase3

Memory Type Range Registers

Unique

MTRRphysMask3

Memory Type Range Registers

Unique

MTRRphysBase4

Memory Type Range Registers

Unique

MTRRphysMask4

Memory Type Range Registers

Unique

MTRRphysBase5

Memory Type Range Registers

Unique

MTRRphysMask5

Memory Type Range Registers

Unique

MTRRphysBase6

Memory Type Range Registers

Unique

MTRRphysMask6

Memory Type Range Registers

Unique

MTRRphysBase7

Memory Type Range Registers

Unique

MTRRphysMask7

Memory Type Range Registers

Unique

MTRRfix64K_00000

Memory Type Range Registers

Unique

MTRRfix16K_80000

Memory Type Range Registers

Unique

MTRRfix16K_A0000

Memory Type Range Registers

Unique

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-61. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)

Shared/

Bit Description

Unique

MTRRfix4K_C0000

Memory Type Range Registers

Unique

MTRRfix4K_C8000

Memory Type Range Registers

Unique

MTRRfix4K_D0000

Memory Type Range Registers

Unique

MTRRfix4K_D8000

Memory Type Range Registers

Unique

MTRRfix4K_E0000

Memory Type Range Registers

Unique

MTRRfix4K_E8000

Memory Type Range Registers

Unique

MTRRfix4K_F0000

Memory Type Range Registers

Unique

MTRRfix4K_F8000

Memory Type Range Registers

Unique

IA32_MTRR_DEF_TYPE

Default Memory Types (R/W)

Unique

See Table 2-2 and Section 12.11.2.1, “IA32_MTRR_DEF_TYPE MSR.”

IA32_MC0_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Unique

IA32_MC0_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

Unique

IA32_MC0_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

Unique

The IA32_MC0_ADDR register is either not implemented or contains no address if the ADDRV flag in the

IA32_MC0_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will

cause a general-protection exception.

IA32_MC1_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Unique

IA32_MC1_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

Unique

IA32_MC1_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

Unique

The IA32_MC1_ADDR register is either not implemented or contains no address if the ADDRV flag in the

IA32_MC1_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will

cause a general-protection exception.

IA32_MC2_CTL

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-61. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)

Shared/

Bit Description

Unique

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Unique

IA32_MC2_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

Unique

IA32_MC2_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

Unique

The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in the

IA32_MC2_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will

cause a general-protection exception.

MSR_MC4_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Unique

MSR_MC4_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

Unique

MSR_MC4_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

Unique

The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the

MSR_MC4_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause

a general-protection exception.

IA32_MC3_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

IA32_MC3_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

MSR_MC3_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

Unique

The MSR_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in the

MSR_MC3_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause

a general-protection exception.

MSR_MC3_MISC

Machine Check Error Reporting Register - contains additional information describing the machine-check error if the

Unique

MISCV flag in the IA32_MCi_STATUS register is set.

MSR_MC5_CTL

Machine Check Error Reporting Register - controls signaling of #MC for errors produced by a particular hardware unit

Unique

(or group of hardware units).

MSR_MC5_STATUS

Machine Check Error Reporting Register - contains information related to a machine-check error if its VAL (valid) flag is

Unique

set. Software is responsible for clearing IA32_MCi_STATUS MSRs by explicitly writing 0s to them; writing 1s to them

causes a general-protection exception.

MSR_MC5_ADDR

Machine Check Error Reporting Register - contains the address of the code or data memory location that produced the

Unique

machine-check error if the ADDRV flag in the IA32_MCi_STATUS register is set.

MSR_MC5_MISC

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Table 2-61. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)

Shared/

Bit Description

Unique

Machine Check Error Reporting Register - contains additional information describing the machine-check error if the

Unique

MISCV flag in the IA32_MCi_STATUS register is set.

IA32_VMX_BASIC

Reporting Register of Basic VMX Capabilities (R/O)

Unique

See Table 2-2 and Appendix A.1, “Basic VMX Information.” (If CPUID.01H:ECX.[bit 5])

IA32_VMX_PINBASED_CTLS

Capability Reporting Register of Pin-Based VM-Execution Controls (R/O)

Unique

See Appendix A.3, “VM-Execution Controls.” (If CPUID.01H:ECX.[bit 5])

IA32_VMX_PROCBASED_CTLS

Capability Reporting Register of Primary Processor-Based VM-Execution Controls (R/O)

Unique

See Appendix A.3, “VM-Execution Controls.” (If CPUID.01H:ECX.[bit 5])

IA32_VMX_EXIT_CTLS

Capability Reporting Register of VM-Exit Controls (R/O)

Unique

See Appendix A.4, “VM-Exit Controls.” (If CPUID.01H:ECX.[bit 5])

IA32_VMX_ENTRY_CTLS

Capability Reporting Register of VM-Entry Controls (R/O)

Unique

See Appendix A.5, “VM-Entry Controls.” (If CPUID.01H:ECX.[bit 5])

IA32_VMX_MISC

Reporting Register of Miscellaneous VMX Capabilities (R/O)

Unique

See Appendix A.6, “Miscellaneous Data.” (If CPUID.01H:ECX.[bit 5])

IA32_VMX_CR0_FIXED0

Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)

Unique

See Appendix A.7, “VMX-Fixed Bits in CR0.” (If CPUID.01H:ECX.[bit 5])

IA32_VMX_CR0_FIXED1

Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)

Unique

See Appendix A.7, “VMX-Fixed Bits in CR0.” (If CPUID.01H:ECX.[bit 5])

IA32_VMX_CR4_FIXED0

Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)

Unique

See Appendix A.8, “VMX-Fixed Bits in CR4.” (If CPUID.01H:ECX.[bit 5])

IA32_VMX_CR4_FIXED1

Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)

Unique

See Appendix A.8, “VMX-Fixed Bits in CR4.” (If CPUID.01H:ECX.[bit 5])

IA32_VMX_VMCS_ENUM

Capability Reporting Register of VMCS Field Enumeration (R/O)

Unique

See Appendix A.9, “VMCS Enumeration.” (If CPUID.01H:ECX.[bit 5])

IA32_VMX_PROCBASED_CTLS2

Capability Reporting Register of Secondary Processor-Based VM-Execution Controls (R/O)

Unique

See Appendix A.3, “VM-Execution Controls.” (If CPUID.01H:ECX.[bit 5] and IA32_VMX_PROCBASED_CTLS[bit 63])

IA32_DS_AREA

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-61. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)

Shared/

Bit Description

Unique

DS Save Area (R/W)

Unique

See Table 2-2 and Section 20.6.3.4, “Debug Store (DS) Mechanism.”

31:0

DS Buffer Management Area

Linear address of the first byte of the DS buffer management area.

63:32

Reserved.

IA32_EFER

See Table 2-2.

Unique

10:0

Reserved.

Execute Disable Bit Enable

63:12

Reserved.

2.21

MSRS IN THE PENTIUM M PROCESSOR

Model-specific registers (MSRs) for the Pentium M processor are similar to those described in Section 2.22 for P6

family processors. The following table describes new MSRs and MSRs whose behavior has changed on the Pentium

M processor.

Table 2-62. MSRs in Pentium M Processors

Bit Description

P5_MC_ADDR

See Section 2.23, “MSRs in Pentium Processors.”

P5_MC_TYPE

See Section 2.23, “MSRs in Pentium Processors.”

IA32_TIME_STAMP_COUNTER

See Section 18.17, “Time-Stamp Counter,” and see Table 2-2.

IA32_PLATFORM_ID

Platform ID (R)

See Table 2-2.

The operating system can use this MSR to determine “slot” information for the processor and the proper microcode update to load.

MSR_EBL_CR_POWERON

Processor Hard Power-On Configuration

(R/W) Enables and disables processor features.

(R) Indicates current processor configuration.

Reserved.

Data Error Checking Enable (R)

0 = Disabled.

Always 0 on the Pentium M processor.

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-62. MSRs in Pentium M Processors (Contd.)

Bit Description

Response Error Checking Enable (R)

0 = Disabled.

Always 0 on the Pentium M processor.

MCERR# Drive Enable (R)

0 = Disabled.

Always 0 on the Pentium M processor.

Address Parity Enable (R)

0 = Disabled.

Always 0 on the Pentium M processor.

6:5

Reserved.

BINIT# Driver Enable (R)

1 = Enabled; 0 = Disabled.

Always 0 on the Pentium M processor.

Output Tri-state Enabled (R/O)

1 = Enabled; 0 = Disabled.

Execute BIST (R/O)

1 = Enabled; 0 = Disabled.

MCERR# Observation Enabled (R/O)

1 = Enabled; 0 = Disabled.

Always 0 on the Pentium M processor.

Reserved.

BINIT# Observation Enabled (R/O)

1 = Enabled; 0 = Disabled.

Always 0 on the Pentium M processor.

Reserved.

1 MByte Power on Reset Vector (R/O)

1 = 1 MByte; 0 = 4 GBytes.

Always 0 on the Pentium M processor.

Reserved.

17:16

APIC Cluster ID (R/O)

Always 00B on the Pentium M processor.

System Bus Frequency (R/O)

0 = 100 MHz.

1 = Reserved.

Always 0 on the Pentium M processor.

Reserved.

21: 20

Symmetric Arbitration ID (R/O)

Always 00B on the Pentium M processor.

26:22

Clock Frequency Ratio (R/O)

MSR_LASTBRANCH_0

2-492 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-62. MSRs in Pentium M Processors (Contd.)

Bit Description

Last Branch Record 0 (R/W)

One of 8 last branch record registers on the last branch record stack: bits 31-0 hold the ‘from’ address and bits 63-32 hold the to

address.

See also:

• Last Branch Record Stack TOS at 1C9H.

• Section 18.15, “Last Branch, Interrupt, and Exception Recording (Pentium M Processors).”

MSR_LASTBRANCH_1

Last Branch Record 1 (R/W)

See description of MSR_LASTBRANCH_0.

MSR_LASTBRANCH_2

Last Branch Record 2 (R/W)

See description of MSR_LASTBRANCH_0.

MSR_LASTBRANCH_3

Last Branch Record 3 (R/W)

See description of MSR_LASTBRANCH_0.

MSR_LASTBRANCH_4

Last Branch Record 4 (R/W)

See description of MSR_LASTBRANCH_0.

MSR_LASTBRANCH_5

Last Branch Record 5 (R/W)

See description of MSR_LASTBRANCH_0.

MSR_LASTBRANCH_6

Last Branch Record 6 (R/W)

See description of MSR_LASTBRANCH_0.

MSR_LASTBRANCH_7

Last Branch Record 7 (R/W)

See description of MSR_LASTBRANCH_0.

MSR_BBL_CR_CTL

Control Register

Used to program L2 commands to be issued via cache configuration accesses mechanism. Also receives L2 lookup response.

63:0

Reserved.

MSR_BBL_CR_CTL3

Control Register 3

Used to configure the L2 Cache.

L2 Hardware Enabled (R/O)

1 = If the L2 is hardware-enabled.

0 = Indicates if the L2 is hardware-disabled.

4:1

Reserved.

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-62. MSRs in Pentium M Processors (Contd.)

Bit Description

ECC Check Enable (R/O)

This bit enables ECC checking on the cache data bus. ECC is always generated on

write cycles.

0 = Disabled (default).

1 = Enabled.

For the Pentium M processor, ECC checking on the cache data bus is always enabled.

7:6

Reserved.

L2 Enabled (R/W)

1 = L2 cache has been initialized.

0 = Disabled (default).

Until this bit is set the processor will not respond to the WBINVD instruction or the

assertion of the FLUSH# input.

22:9

Reserved.

L2 Not Present (R/O)

0 = L2 Present.

1 = L2 Not Present.

63:24

Reserved.

IA32_MCG_CAP

Read-only register that provides information about the machine-check architecture of the processor.

7:0

Count (R/O)

Indicates the number of hardware unit error reporting banks available in the

processor.

IA32_MCG_CTL Present (R/O)

1 = Indicates that the processor implements the MSR_MCG_CTL register found at

MSR 17BH.

0 = Not supported.

63:9

Reserved.

IA32_MCG_STATUS

Global Machine Check Status

RIPV

When set, this bit indicates that the instruction addressed by the instruction pointer

pushed on the stack (when the machine check was generated) can be used to restart

the program. If this bit is cleared, the program cannot be reliably restarted.

EIPV

When set, this bit indicates that the instruction addressed by the instruction pointer

pushed on the stack (when the machine check was generated) is directly associated

with the error.

MCIP

When set, this bit indicates that a machine check has been generated. If a second

machine check is detected while this bit is still set, the processor enters a shutdown

state. Software should write this bit to 0 after processing a machine check exception.

63:3

Reserved.

IA32_PERF_STATUS

2-494 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-62. MSRs in Pentium M Processors (Contd.)

Bit Description

See Table 2-2.

IA32_PERF_CTL

See Table 2-2.

IA32_CLOCK_MODULATION

Clock Modulation (R/W).

See Table 2-2 and Section 15.8.3, “Software Controlled Clock Modulation.”

IA32_THERM_INTERRUPT

Thermal Interrupt Control (R/W)

See Table 2-2 and Section 15.8.2, “Thermal Monitor.”

IA32_THERM_STATUS

Thermal Monitor Status (R/W)

See Table 2-2 and Section 15.8.2, “Thermal Monitor.”

MSR_THERM2_CTL

Thermal Monitor 2 Control

15:0

Reserved.

TM_SELECT (R/W)

Mode of automatic thermal monitor:

0 = Thermal Monitor 1 (thermally-initiated on-die modulation of the stop-clock duty

cycle)

1 = Thermal Monitor 2 (thermally-initiated frequency transitions)

If bit 3 of the IA32_MISC_ENABLE register is cleared, TM_SELECT has no effect.

Neither TM1 nor TM2 will be enabled.

63:16

Reserved.

IA32_MISC_ENABLE

Enable Miscellaneous Processor Features (R/W)

Allows a variety of processor functions to be enabled and disabled.

2:0

Reserved.

Automatic Thermal Control Circuit Enable (R/W)

1 = Setting this bit enables the thermal control circuit (TCC) portion of the Intel

Thermal Monitor feature. This allows processor clocks to be automatically

modulated based on the processor's thermal sensor operation.

0 = Disabled (default).

The automatic thermal control circuit enable bit determines if the thermal control

circuit (TCC) will be activated when the processor's internal thermal sensor

determines the processor is about to exceed its maximum operating temperature.

When the TCC is activated and TM1 is enabled, the processors clocks will be forced to

a 50% duty cycle. BIOS must enable this feature.

The bit should not be confused with the on-demand thermal control circuit enable bit.

6:4

Reserved.

Performance Monitoring Available (R)

1 = Performance monitoring enabled.

0 = Performance monitoring disabled.

Vol. 4

2-495

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-62. MSRs in Pentium M Processors (Contd.)

Bit Description

9:8

Reserved.

FERR# Multiplexing Enable (R/W)

1 = FERR# asserted by the processor to indicate a pending break event within the

processor.

0 = Indicates compatible FERR# signaling behavior.

This bit must be set to 1 to support XAPIC interrupt model usage.

Branch Trace Storage Unavailable (R/O)

1 = Processor doesn’t support branch trace storage (BTS)

0 = BTS is supported

Processor Event Based Sampling Unavailable (R/O)

1 = Processor does not support processor event based sampling (PEBS);

0 = PEBS is supported.

The Pentium M processor does not support PEBS.

15:13

Reserved.

Enhanced Intel SpeedStep Technology Enable (R/W)

1 = Enhanced Intel SpeedStep Technology enabled.

On the Pentium M processor, this bit may be configured to be read-only.

22:17

Reserved.

xTPR Message Disable (R/W)

When set to 1, xTPR messages are disabled. xTPR messages are optional messages

that allow the processor to inform the chipset of its priority. The default is processor

specific.

63:24

Reserved.

MSR_LASTBRANCH_TOS

Last Branch Record Stack TOS (R/W)

Contains an index (bits 0-3) that points to the MSR containing the most recent branch record. See also:

• MSR_LASTBRANCH_0_FROM_IP (at 40H).

• Section 18.15, “Last Branch, Interrupt, and Exception Recording (Pentium M Processors).”

MSR_DEBUGCTLB

Debug Control (R/W)

Controls how several debug features are used. Bit definitions are discussed in the referenced section.

See Section 18.15, “Last Branch, Interrupt, and Exception Recording (Pentium M Processors).”

MSR_LER_TO_LIP

Last Exception Record To Linear IP (R)

This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last exception that

was generated or the last interrupt that was handled.

See Section 18.15, “Last Branch, Interrupt, and Exception Recording (Pentium M Processors),” and Section 18.16.2, “Last Branch and

Last Exception MSRs.”

MSR_LER_FROM_LIP

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-62. MSRs in Pentium M Processors (Contd.)

Bit Description

Last Exception Record From Linear IP (R)

Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was generated or the

last interrupt that was handled.

See Section 18.15, “Last Branch, Interrupt, and Exception Recording (Pentium M Processors),” and Section 18.16.2, “Last Branch and

Last Exception MSRs.”

IA32_MTRR_DEF_TYPE

Default Memory Types (R/W)

Sets the memory type for the regions of physical memory that are not mapped by the MTRRs.

See Section 12.11.2.1, “IA32_MTRR_DEF_TYPE MSR.”

IA32_MC0_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

IA32_MC0_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

IA32_MC0_ADDR

See Section 14.3.2.3., “IA32_MCi_ADDR MSRs”.

The IA32_MC0_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC0_STATUS register

is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

IA32_MC1_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

IA32_MC1_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

IA32_MC1_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

The IA32_MC1_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC1_STATUS register

is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

IA32_MC2_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

IA32_MC2_STATUS

See Chapter 16.3.2.2, “IA32_MCi_STATUS MSRS.”

IA32_MC2_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC2_STATUS register

is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

MSR_MC4_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

MSR_MC4_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

MSR_MC4_ADDR

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Table 2-62. MSRs in Pentium M Processors (Contd.)

Bit Description

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC4_STATUS register

is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

MSR_MC3_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

MSR_MC3_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

MSR_MC3_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

The MSR_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC3_STATUS register

is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

IA32_DS_AREA

DS Save Area (R/W)

See Table 2-2.

Points to the DS buffer management area, which is used to manage the BTS and PEBS buffers. See Section 20.6.3.4, “Debug Store

(DS) Mechanism.”

31:0

DS Buffer Management Area

Linear address of the first byte of the DS buffer management area.

63:32

Reserved.

2.22

MSRS IN THE P6 FAMILY PROCESSORS

The following MSRs are defined for the P6 family processors. The MSRs in this table that are shaded are available

only in the Pentium II and Pentium III processors. Beginning with the Pentium 4 processor, some of the MSRs in this

list have been designated as “architectural” and have had their names changed. See Table 2-2 for a list of the archi-

tectural MSRs.

Table 2-63. MSRs in the P6 Family Processors

Bit Description

P5_MC_ADDR

See Section 2.23, “MSRs in Pentium Processors.”

P5_MC_TYPE

See Section 2.23, “MSRs in Pentium Processors.”

TSC

See Section 18.17, “Time-Stamp Counter.”

IA32_PLATFORM_ID

Platform ID (R)

The operating system can use this MSR to determine “slot” information for the processor and the proper microcode update to load.

49:0

Reserved.

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Table 2-63. MSRs in the P6 Family Processors (Contd.)

Bit Description

52:50

Platform Id (R)

Contains information concerning the intended platform for the processor.

52 51

0 Processor Flag 0

1 Processor Flag 1

0 Processor Flag 2

1 Processor Flag 3

0 Processor Flag 4

1 Processor Flag 5

0 Processor Flag 6

1 Processor Flag 7

56:53

L2 Cache Latency Read.

59:57

Reserved.

Clock Frequency Ratio Read.

63:61

Reserved.

APIC_BASE

Section 11.4.4, “Local APIC Status and Location.”

7:0

Reserved.

Boot Strap Processor Indicator Bit

1 = BSP

10:9

Reserved.

APIC Global Enable Bit - Permanent till reset

1 = Enabled.

0 = Disabled.

31:12

APIC Base Address.

63:32

Reserved.

EBL_CR_POWERON

Processor Hard Power-On Configuration

(R/W) Enables and disables processor features, and (R) indicates current processor configuration.

Reserved¹

Data Error Checking Enable (R/W)

1 = Enabled.

0 = Disabled.

Response Error Checking Enable FRCERR Observation Enable (R/W)

1 = Enabled.

0 = Disabled.

AERR# Drive Enable (R/W)

1 = Enabled.

0 = Disabled.

BERR# Enable for Initiator Bus Requests (R/W)

1 = Enabled.

0 = Disabled.

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Table 2-63. MSRs in the P6 Family Processors (Contd.)

Bit Description

Reserved.

BERR# Driver Enable for Initiator Internal Errors (R/W)

1 = Enabled.

0 = Disabled.

BINIT# Driver Enable (R/W)

1 = Enabled.

0 = Disabled.

Output Tri-state Enabled (R)

1 = Enabled.

0 = Disabled.

Execute BIST (R)

1 = Enabled.

0 = Disabled.

AERR# Observation Enabled (R)

1 = Enabled.

0 = Disabled.

Reserved.

BINIT# Observation Enabled (R)

1 = Enabled.

0 = Disabled.

In Order Queue Depth (R)

1 = 1.

0 = 8.

1-MByte Power on Reset Vector (R)

1 = 1MByte.

0 = 4GBytes.

FRC Mode Enable (R)

1 = Enabled.

0 = Disabled.

17:16

APIC Cluster ID (R)

19:18

System Bus Frequency (R)

00 = 66MHz.

10 = 100Mhz.

01 = 133MHz.

11 = Reserved.

21: 20

Symmetric Arbitration ID (R)

25:22

Clock Frequency Ratio (R)

Low Power Mode Enable (R/W)

Clock Frequency Ratio

63:28

Reserved.¹

MSR_TEST_CTRL

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Table 2-63. MSRs in the P6 Family Processors (Contd.)

Bit Description

Test Control Register

29:0

Reserved.

Streaming Buffer Disable

Disable LOCK#

Assertion for split locked access.

BIOS_UPDT_TRIG

BIOS Update Trigger Register.

BBL_CR_D0[63:0]

Chunk 0 data register D[63:0]: used to write to and read from the L2.

BBL_CR_D1

Chunk 1 data register D[63:0]: used to write to and read from the L2.

BBL_CR_D2

Chunk 2 data register D[63:0]: used to write to and read from the L2.

BIOS_SIGN/BBL_CR_D3

BIOS Update Signature Register or Chunk 3 data register D[63:0].

Used to write to and read from the L2 depending on the usage model.

PerfCtr0 (PERFCTR0)

Performance Counter Register

See Table 2-2.

PerfCtr1 (PERFCTR1)

Performance Counter Register

See Table 2-2.

MTRRcap

Memory Type Range Registers

BBL_CR_ADDR

Address register: used to send specified address (A31-A3) to L2 during cache initialization accesses.

2:0

Reserved; set to 0.

31:3

Address bits [35:3].

63:32

Reserved.

BBL_CR_DECC

Data ECC register D[7:0]: used to write ECC and read ECC to/from L2.

BBL_CR_CTL

Control register: used to program L2 commands to be issued via cache configuration accesses mechanism. Also receives L2 lookup

response.

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Table 2-63. MSRs in the P6 Family Processors (Contd.)

Bit Description

4:0

L2 Command:

01100 = Data Read w/ LRU update (RLU).

01110 = Tag Read w/ Data Read (TRR).

01111 = Tag Inquire (TI).

00010 = L2 Control Register Read (CR).

00011 = L2 Control Register Write (CW).

010 + MESI encode = Tag Write w/ Data Read (TWR).

111 + MESI encode = Tag Write w/ Data Write (TWW).

100 + MESI encode = Tag Write (TW).

6:5

State to L2

9:8

Reserved.

11:10

Way 0 - 00, Way 1 - 01, Way 2 - 10, Way 3 - 11

Way to L2

13:12

Modified - 11,Exclusive - 10, Shared - 01, Invalid - 00

Way from L2

15:14

State from L2.

Reserved.

L2 Hit.

Reserved.

20:19

User supplied ECC.

Processor number: ²

Disable = 1.

Enable = 0.

Reserved.

63:22

Reserved.

BBL_CR_TRIG

Trigger register: used to initiate a cache configuration accesses access, Write only with Data = 0.

BBL_CR_BUSY

Busy register: indicates when a cache configuration accesses L2 command is in progress. D[0] = 1 = BUSY.

BBL_CR_CTL3

Control register 3: used to configure the L2 Cache.

L2 Configured (read/write).

4:1

L2 Cache Latency (read/write).

ECC Check Enable (read/write).

Address Parity Check Enable (read/write).

CRTN Parity Check Enable (read/write).

L2 Enabled (read/write).

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Table 2-63. MSRs in the P6 Family Processors (Contd.)

Bit Description

10:9

L2 Associativity (read only):

00 = Direct Mapped.

01 = 2 Way.

10 = 4 Way.

11 = Reserved.

12:11

Number of L2 banks (read only).

17:13

Cache size per bank (read/write):

00001 = 256 KBytes.

00010 = 512 KBytes.

00100 = 1 MByte.

01000 = 2 MBytes.

10000 = 4 MBytes.

Cache State error checking enable (read/write).

Reserved.

22:20

L2 Physical Address Range support:

111 = 64 GBytes.

110 = 32 GBytes.

101 = 16 GBytes.

100 = 8 GBytes.

011 = 4 GBytes.

010 = 2 GBytes.

001 = 1 GByte.

000 = 512 MBytes.

L2 Hardware Disable (read only).

Reserved.

Cache bus fraction (read only).

63:26

Reserved.

SYSENTER_CS_MSR

CS register target for CPL 0 code

SYSENTER_ESP_MSR

Stack pointer for CPL 0 stack

SYSENTER_EIP_MSR

CPL 0 code entry point

MCG_CAP

Machine Check Global Control Register

MCG_STATUS

Machine Check Error Reporting Register - contains information related to a machine-check error if its VAL (valid) flag is set. Software

is responsible for clearing IA32_MCi_STATUS MSRs by explicitly writing 0s to them; writing 1s to them causes a general-protection

exception.

MCG_CTL

Machine Check Error Reporting Register - controls signaling of #MC for errors produced by a particular hardware unit (or group of

hardware units).

PerfEvtSel0 (EVNTSEL0)

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Table 2-63. MSRs in the P6 Family Processors (Contd.)

Bit Description

Performance Event Select Register 0 (R/W)

7:0

Event Select

Refer to Performance Counter section for a list of event encodings.

15:8

UMASK (Unit Mask)

Unit mask register set to 0 to enable all count options.

USER

Controls the counting of events at Privilege levels of 1, 2, and 3.

Controls the counting of events at Privilege level of 0.

Occurrence/Duration Mode Select:

1 = Occurrence.

0 = Duration.

Enabled the signaling of performance counter overflow via BP0 pin.

INT

Enables the signaling of counter overflow via input to APIC:

1 = Enable.

0 = Disable.

ENABLE

Enables the counting of performance events in both counters:

1 = Enable.

0 = Disable.

INV

Inverts the result of the CMASK condition:

1 = Inverted.

0 = Non-Inverted.

31:24

CMASK (Counter Mask)

PerfEvtSel1 (EVNTSEL1)

Performance Event Select for Counter 1 (R/W)

7:0

Event Select

Refer to Performance Counter section for a list of event encodings.

15:8

UMASK (Unit Mask)

Unit mask register set to 0 to enable all count options.

USER

Controls the counting of events at Privilege levels of 1, 2, and 3.

Controls the counting of events at Privilege level of 0.

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Table 2-63. MSRs in the P6 Family Processors (Contd.)

Bit Description

Occurrence/Duration Mode Select:

1 = Occurrence.

0 = Duration.

Enabled the signaling of performance counter overflow via BP0 pin.

INT

Enables the signaling of counter overflow via input to APIC.

1 = Enable.

0 = Disable.

INV

Inverts the result of the CMASK condition.

1 = Inverted.

0 = Non-Inverted.

31:24

CMASK (Counter Mask)

DEBUGCTLMSR

Enables last branch, interrupt, and exception recording; taken branch breakpoints; the breakpoint reporting pins; and trace messages.

This register can be written to using the WRMSR instruction, when operating at privilege level 0 or when in real-address mode.

Enable/Disable Last Branch Records

Branch Trap Flag

Performance Monitoring/Break Point Pins

Enable/Disable Execution Trace Messages

31:7

Reserved.

LASTBRANCHFROMIP

32-bit register for recording the instruction pointers for the last branch, interrupt, or exception that the processor took prior to a

debug exception being generated.

LASTBRANCHTOIP

32-bit register for recording the instruction pointers for the last branch, interrupt, or exception that the processor took prior to a

debug exception being generated.

LASTINTFROMIP

Last INT from IP

LASTINTTOIP

Last INT to IP

MTRRphysBase0

Memory Type Range Registers

MTRRphysMask0

Memory Type Range Registers

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Table 2-63. MSRs in the P6 Family Processors (Contd.)

Bit Description

MTRRphysBase1

Memory Type Range Registers

MTRRphysMask1

Memory Type Range Registers

MTRRphysBase2

Memory Type Range Registers

MTRRphysMask2

Memory Type Range Registers

MTRRphysBase3

Memory Type Range Registers

MTRRphysMask3

Memory Type Range Registers

MTRRphysBase4

Memory Type Range Registers

MTRRphysMask4

Memory Type Range Registers

MTRRphysBase5

Memory Type Range Registers

MTRRphysMask5

Memory Type Range Registers

MTRRphysBase6

Memory Type Range Registers

MTRRphysMask6

Memory Type Range Registers

MTRRphysBase7

Memory Type Range Registers

MTRRphysMask7

Memory Type Range Registers

MTRRfix64K_00000

Memory Type Range Registers

MTRRfix16K_80000

Memory Type Range Registers

MTRRfix16K_A0000

Memory Type Range Registers

MTRRfix4K_C0000

Memory Type Range Registers

MTRRfix4K_C8000

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Table 2-63. MSRs in the P6 Family Processors (Contd.)

Bit Description

Memory Type Range Registers

MTRRfix4K_D0000

Memory Type Range Registers

MTRRfix4K_D8000

Memory Type Range Registers

MTRRfix4K_E0000

Memory Type Range Registers

MTRRfix4K_E8000

Memory Type Range Registers

MTRRfix4K_F0000

Memory Type Range Registers

MTRRfix4K_F8000

Memory Type Range Registers

MTRRdefType

Memory Type Range Registers

2:0

Default memory type

Fixed MTRR enable

MTRR Enable

MC0_CTL

Machine Check Error Reporting Register - controls signaling of #MC for errors produced by a particular hardware unit (or group of

hardware units).

MC0_STATUS

Machine Check Error Reporting Register - contains information related to a machine-check error if its VAL (valid) flag is set. Software

is responsible for clearing IA32_MCi_STATUS MSRs by explicitly writing 0s to them; writing 1s to them causes a general-protection

exception.

15:0

MC_STATUS_MCACOD

31:16

MC_STATUS_MSCOD

MC_STATUS_DAM

MC_STATUS_ADDRV

MC_STATUS_MISCV

MC_STATUS_EN. (Note: For MC0_STATUS only, this bit is hardcoded to 1.)

MC_STATUS_UC

MC_STATUS_O

MC_STATUS_V

MC0_ADDR

MC0_MISC

Defined in MCA architecture but not implemented in the P6 family processors.

MC1_CTL

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Table 2-63. MSRs in the P6 Family Processors (Contd.)

Bit Description

MC1_STATUS

Bit definitions same as MC0_STATUS.

MC1_ADDR

MC1_MISC

Defined in MCA architecture but not implemented in the P6 family processors.

MC2_CTL

MC2_STATUS

Bit definitions same as MC0_STATUS.

MC2_ADDR

MC2_MISC

Defined in MCA architecture but not implemented in the P6 family processors.

MC4_CTL

MC4_STATUS

Bit definitions same as MC0_STATUS, except bits 0, 4, 57, and 61 are hardcoded to 1.

MC4_ADDR

Defined in MCA architecture but not implemented in P6 Family processors.

MC4_MISC

Defined in MCA architecture but not implemented in the P6 family processors.

MC3_CTL

MC3_STATUS

Bit definitions same as MC0_STATUS.

MC3_ADDR

MC3_MISC

Defined in MCA architecture but not implemented in the P6 family processors.

NOTES

1. Bit 0 of this register has been redefined several times, and is no longer used in P6 family processors.

2. The processor number feature may be disabled by setting bit 21 of the BBL_CR_CTL MSR (model-specific register address 119h) to

“1”. Once set, bit 21 of the BBL_CR_CTL may not be cleared. This bit is write-once. The processor number feature will be disabled

until the processor is reset.

3. The Pentium III processor will prevent FSB frequency overclocking with a new shutdown mechanism. If the FSB frequency selected

is greater than the internal FSB frequency the processor will shutdown. If the FSB selected is less than the internal FSB frequency

the BIOS may choose to use bit 11 to implement its own shutdown policy.

2.23

MSRS IN PENTIUM PROCESSORS

The following MSRs are defined for the Pentium processors. The P5_MC_ADDR, P5_MC_TYPE, and TSC MSRs

(named IA32_P5_MC_ADDR, IA32_P5_MC_TYPE, and IA32_TIME_STAMP_COUNTER in the Pentium 4 processor)

are architectural; that is, code that accesses these registers will run on Pentium 4 and P6 family processors without

generating exceptions (see Section 2.1, “Architectural MSRs”). The CESR, CTR0, and CTR1 MSRs are unique to

Pentium processors; code that accesses these registers will generate exceptions on Pentium 4 and P6 family

processors.

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-64. MSRs in the Pentium Processor

P5_MC_ADDR

See Section 16.10.2, “Pentium Processor Machine-Check Exception Handling.”

P5_MC_TYPE

See Section 16.10.2, “Pentium Processor Machine-Check Exception Handling.”

TSC

See Section 18.17, “Time-Stamp Counter.”

CESR

See Section 20.6.9.1, “Control and Event Select Register (CESR).”

CTR0

Section 20.6.9.3, “Events Counted.”

CTR1

Section 20.6.9.3, “Events Counted.”

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Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 14