Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 13
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
DRAM RAPL Parameters (R/W)
Package
See Section 15.10.5, “DRAM RAPL Domain.”
Register Address: 620H, 1568
MSR_UNCORE_RATIO_LIMIT
Uncore Ratio Limit (R/W)
Package
Out of reset, the min_ratio and max_ratio fields represent the widest possible range of uncore frequencies. Writing to
these fields allows software to control the minimum and the maximum frequency that hardware will select.
63:15
Reserved.
14:8
MIN_RATIO
Writing to this field controls the minimum possible ratio of the LLC/Ring.
7
Reserved.
6:0
MAX_RATIO
This field is used to limit the max ratio of the LLC/Ring.
Register Address: 639H, 1593
MSR_PP0_ENERGY_STATUS
Reserved (R/O)
Package
Reads return 0.
Register Address: C8DH, 3213
IA32_QM_EVTSEL
Monitoring Event Select Register (R/W)
Thread
If CPUID.(EAX=07H, ECX=0):EBX.RDT-M[bit 12] = 1.
7:0
EventID (R/W)
Event encoding:
0x00: No monitoring.
0x01: L3 occupancy monitoring.
0x02: Total memory bandwidth monitoring.
0x03: Local memory bandwidth monitoring.
All other encoding reserved.
31:8
Reserved.
41:32
RMID (R/W)
63:42
Reserved.
Register Address: C8FH, 3215
IA32_PQR_ASSOC
Resource Association Register (R/W)
Thread
9:0
RMID
31:10
Reserved.
51:32
COS (R/W)
63: 52
Reserved.
Register Address: C90H, 3216
IA32_L3_QOS_MASK_0
L3 Class Of Service Mask - COS 0 (R/W)
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=0.
0:19
CBM: Bit vector of available L3 ways for COS 0 enforcement.
63:20
Reserved.
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
Register Address: C91H, 3217
IA32_L3_QOS_MASK_1
L3 Class Of Service Mask - COS 1 (R/W)
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=1.
0:19
CBM: Bit vector of available L3 ways for COS 1 enforcement.
63:20
Reserved.
Register Address: C92H, 3218
IA32_L3_QOS_MASK_2
L3 Class Of Service Mask - COS 2 (R/W)
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=2.
0:19
CBM: Bit vector of available L3 ways for COS 2 enforcement.
63:20
Reserved.
Register Address: C93H, 3219
IA32_L3_QOS_MASK_3
L3 Class Of Service Mask - COS 3 (R/W).
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=3.
0:19
CBM: Bit vector of available L3 ways for COS 3 enforcement.
63:20
Reserved.
Register Address: C94H, 3220
IA32_L3_QOS_MASK_4
L3 Class Of Service Mask - COS 4 (R/W)
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=4.
0:19
CBM: Bit vector of available L3 ways for COS 4 enforcement.
63:20
Reserved.
Register Address: C95H, 3221
IA32_L3_QOS_MASK_5
L3 Class Of Service Mask - COS 5 (R/W)
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=5.
0:19
CBM: Bit vector of available L3 ways for COS 5 enforcement.
63:20
Reserved.
Register Address: C96H, 3222
IA32_L3_QOS_MASK_6
L3 Class Of Service Mask - COS 6 (R/W)
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=6.
0:19
CBM: Bit vector of available L3 ways for COS 6 enforcement.
63:20
Reserved.
Register Address: C97H, 3223
IA32_L3_QOS_MASK_7
L3 Class Of Service Mask - COS 7 (R/W)
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=7.
0:19
CBM: Bit vector of available L3 ways for COS 7 enforcement.
63:20
Reserved.
Register Address: C98H, 3224
IA32_L3_QOS_MASK_8
L3 Class Of Service Mask - COS 8 (R/W)
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=8.
2-394 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
0:19
CBM: Bit vector of available L3 ways for COS 8 enforcement.
63:20
Reserved.
Register Address: C99H, 3225
IA32_L3_QOS_MASK_9
L3 Class Of Service Mask - COS 9 (R/W)
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=9.
0:19
CBM: Bit vector of available L3 ways for COS 9 enforcement.
63:20
Reserved.
Register Address: C9AH, 3226
IA32_L3_QOS_MASK_10
L3 Class Of Service Mask - COS 10 (R/W)
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=10.
0:19
CBM: Bit vector of available L3 ways for COS 10 enforcement.
63:20
Reserved.
Register Address: C9BH, 3227
IA32_L3_QOS_MASK_11
L3 Class Of Service Mask - COS 11 (R/W)
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=11.
0:19
CBM: Bit vector of available L3 ways for COS 11 enforcement.
63:20
Reserved.
Register Address: C9CH, 3228
IA32_L3_QOS_MASK_12
L3 Class Of Service Mask - COS 12 (R/W)
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=12.
0:19
CBM: Bit vector of available L3 ways for COS 12 enforcement.
63:20
Reserved.
Register Address: C9DH, 3229
IA32_L3_QOS_MASK_13
L3 Class Of Service Mask - COS 13 (R/W)
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=13.
0:19
CBM: Bit vector of available L3 ways for COS 13 enforcement.
63:20
Reserved.
Register Address: C9EH, 3230
IA32_L3_QOS_MASK_14
L3 Class Of Service Mask - COS 14 (R/W)
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=14.
0:19
CBM: Bit vector of available L3 ways for COS 14 enforcement.
63:20
Reserved.
Register Address: C9FH, 3231
IA32_L3_QOS_MASK_15
L3 Class Of Service Mask - COS 15 (R/W)
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=15.
0:19
CBM: Bit vector of available L3 ways for COS 15 enforcement.
63:20
Reserved.
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MODEL-SPECIFIC REGISTERS (MSRS)
2.17.7 MSRs Specific to the 3rd Generation Intel® Xeon® Scalable Processor Family Based on
Ice Lake Microarchitecture
The 3rd generation Intel® Xeon® Scalable Processor Family based on Ice Lake microarchitecture (CPUID Signature
DisplayFamily_DisplayModel value of 06_6AH or 06_6CH) support the MSRs listed in Table 2-51.
Table 2-51. MSRs Supported by the 3rd Generation Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_6AH or 06_6CH
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 612H, 1554
MSR_PACKAGE_ENERGY_TIME_STATUS
Package energy consumed by the entire CPU (R/W)
Package
31:0
Total amount of energy consumed since last reset.
63:32
Total time elapsed when the energy was last updated. This is a monotonic
increment counter with auto wrap back to zero after overflow. Unit is
10ns.
Register Address: 618H, 1560
MSR_DRAM_POWER_LIMIT
Allows software to set power limits for the DRAM domain and measurement attributes associated with each limit.
Package
14:0
DRAM_PP_PWR_LIM:
Power Limit[0] for DDR domain. Units = Watts, Format = 11.3, Resolution =
0.125W, Range = 0-2047.875W.
15
PWR_LIM_CTRL_EN:
Power Limit[0] enable bit for DDR domain.
16
Reserved.
23:17
CTRL_TIME_WIN:
Power Limit[0] time window Y value, for DDR domain. Actual time_window
for RAPL is:
(1/1024 seconds) * (1+(x/4)) * (2^y)
62:24
Reserved.
63
PP_PWR_LIM_LOCK:
When set, this entire register becomes read-only. This bit will typically be
set by BIOS during boot.
Register Address: 619H, 1561
MSR_DRAM_ENERGY_STATUS
DRAM Energy Status (R/O)
Package
See Section 15.10.5, “DRAM RAPL Domain.”
31:0
Energy in 15.3 micro-joules. Requires BIOS configuration to enable DRAM
RAPL mode 0 (Direct VR).
63:32
Reserved.
Register Address: 61BH, 1563
MSR_DRAM_PERF_STATUS
DRAM Performance Throttling Status (R/O)
Package
See Section 15.10.5, “DRAM RAPL Domain.”
Register Address: 61CH, 1564
MSR_DRAM_POWER_INFO
DRAM Power Parameters (R/W)
Package
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-51. MSRs Supported by the 3rd Generation Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_6AH or 06_6CH (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
14:0
Spec DRAM Power (DRAM_TDP):
The Spec power allowed for DRAM. The TDP setting is
typical (not guaranteed).
The units for this value are defined in
MSR_DRAM_POWER_INFO_UNIT[PWR_UNIT].
15
Reserved.
30:16
Minimal DRAM Power (DRAM_MIN_PWR):
The minimal power setting allowed for DRAM. Lower
values will be clamped to this value. The minimum
setting is typical (not guaranteed).
The units for this value are defined in
MSR_DRAM_POWER_INFO_UNIT[PWR_UNIT].
31
Reserved.
46:32
Maximal Package Power (DRAM_MAX_PWR):
The maximal power setting allowed for DRAM. Higher
values will be clamped to this value. The maximum
setting is typical (not guaranteed).
The units for this value are defined in
MSR_DRAM_POWER_INFO_UNIT[PWR_UNIT].
47
Reserved.
54:48
Maximal Time Window (DRAM_MAX_WIN):
The maximal time window allowed for the DRAM.
Higher values will be clamped to this value.
x = PKG_MAX_WIN[54:53]
y = PKG_MAX_WIN[52:48]
The timing interval window is a floating-point number given by 1.x
*power(2,y).
The unit of measurement is defined in
MSR_DRAM_POWER_INFO_UNIT[TIME_UNIT].
62:55
Reserved.
63
LOCK:
Lock bit to lock the register.
Register Address: 981H, 2433
IA32_TME_CAPABILITY
See Table 2-2.
Register Address: 982H, 2434
IA32_TME_ACTIVATE
See Table 2-2.
Register Address: 983H, 2435
IA32_TME_EXCLUDE_MASK
See Table 2-2.
Register Address: 984H, 2436
IA32_TME_EXCLUDE_BASE
See Table 2-2.
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MODEL-SPECIFIC REGISTERS (MSRS)
2.17.8 MSRs Specific to the 4th and 5th Generation Intel® Xeon® Scalable Processor Families
The 4th generation Intel® Xeon® Scalable Processor Family based on Sapphire Rapids microarchitecture (CPUID
Signature DisplayFamily_DisplayModel value of 06_8FH) and the 5th generation Intel® Xeon® Scalable Processor
Family based on Emerald Rapids microarchitecture (CPUID Signature DisplayFamily_DisplayModel value of
06_CFH) both support the MSRs listed in Section 2.17, “MSRs In the 6th-13th Generation Intel® Core™ Proces-
sors, 1st-5th Generation Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Gener-
ation Intel® Core™ i3 Processors, and Intel® Xeon® E Processors,” including Table 2-52. For an MSR listed in Table
2-52 that also appears in the model-specific tables of prior generations, Table 2-52 supersedes prior generation
tables.
Table 2-52. Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon® Scalable Processor Families
(CPUID Signature DisplayFamily_DisplayModel Values of 06_8FH and 06_CFH)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 33H, 51
MSR_MEMORY_CTRL
Memory Control Register (R/W)
Core
27:0
Reserved.
28
UC_LOCK_DISABLE
If set to 1, a UC lock will cause a #GP(0) exception.
See Section 9.1.2.3, “Features to Disable Bus Locks.”
29
SPLIT_LOCK_DISABLE
If set to 1, a split lock will cause an #AC(0) exception.
See Section 9.1.2.3, “Features to Disable Bus Locks.”
31:30
Reserved.
Register Address: A7H, 167
MSR_BIOS_DEBUG
BIOS DEBUG (R/O)
Thread
See Table 2-45.
Register Address: BCH, 188
IA32_MISC_PACKAGE_CTLS
Power Filtering Control (R/W)
Package
IA32_ARCH_CAPABILITIES[bit 10] enumerates support for this MSR.
See Table 2-2.
Register Address: CFH, 207
IA32_CORE_CAPABILITIES
IA32 Core Capabilities Register (R/W)
Core
If CPUID.(EAX=07H, ECX=0):EDX[30] = 1.
This MSR provides an architectural enumeration function for model-specific behavior.
0
Reserved: returns zero.
1
Reserved: returns zero.
2
INTEGRITY_CAPABILITIES
When set to 1, the processor supports MSR_INTEGRITY_CAPABILITIES.
3
RSM_IN_CPL0_ONLY
Indicates that RSM will only be allowed in CPL0 and will #GP for all non-
CPL0 privilege levels.
4
UC_LOCK_DISABLE_SUPPORTED
When read as 1, software can set bit 28 of MSR_MEMORY_CTRL (MSR
address 33H).
2-398 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-52. Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon® Scalable Processor Families
(CPUID Signature DisplayFamily_DisplayModel Values of 06_8FH and 06_CFH) (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
5
SPLIT_LOCK_DISABLE_SUPPORTED
When read as 1, software can set bit 29 of MSR_MEMORY_CTRL.
6
Reserved: returns zero.
7
UC_STORE_THROTTLING_SUPPORTED
Indicates that the snoop filter quality of service MSRs are supported on
this core. This is based on the existence of a non-inclusive cache and the
L2/MLC QoS feature supported.
63:8
Reserved: returns zero.
Register Address: E1H, 225
IA32_UMWAIT_CONTROL
UMWAIT Control (R/W)
See Table 2-2.
Register Address: EDH, 237
MSR_RAR_CONTROL
RAR Control (R/W)
Thread
63:32
Reserved.
31
ENABLE
RAR events are recognized. When RAR is not enabled, RARs are dropped.
30
IGNORE_IF
Allow RAR servicing at the RLP regardless of the value of RFLAGS.IF.
29:0
Reserved.
Register Address: EEH, 238
MSR_RAR_ACTION_VECTOR_BASE
Pointer to RAR Action Vector (R/W)
Thread
63:MAXPHYADDR
Reserved.
MAXPHYADDR-1:6
VECTOR_PHYSICAL_ADDRESS
Pointer to the physical address of the 64B aligned RAR action vector.
5:0
Reserved.
Register Address: EFH, 239
MSR_RAR_PAYLOAD_TABLE_BASE
Pointer to Base of RAR Payload Table (R/W)
Thread
63:MAXPHYADDR
Reserved.
MAXPHYADDR-1:12
TABLE_PHYSICAL_ADDRESS
Pointer to the base physical address of the 4K aligned RAR payload table.
11:0
Reserved.
Register Address: F0H, 240
MSR_RAR_INFO
Read Only RAR Information (RO)
Thread
63:38
Always zero.
37:32
Table Max Index
Maximum supported payload table index.
31:0
Supported payload type bitmap. A value of 1 in bit position [i] indicates
that payload type [i] is supported.
Register Address: 105H, 261
MSR_CORE_BIST
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-52. Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon® Scalable Processor Families
(CPUID Signature DisplayFamily_DisplayModel Values of 06_8FH and 06_CFH) (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Core BIST (R/W)
Core
Controls Array BIST activation and status checking as part of FUSA.
31:0
BIST_ARRAY
Bitmap indicating which arrays to run BIST on (WRITE).
Bitmap indicating which arrays were not processed, i.e., completion mask
(READ).
39:32
BANK
Array bank of the [least significant set bit] array indicated in EAX to start
BIST(WRITE).
Array bank interrupted or failed (READ).
47:40
DWORD
Array dword of the [least significant set bit] array indicated in EAX to
start BIST (WRITE).
Array dword interrupted or failed (READ).
62:48
Reserved.
63
CTRL_RESULT
Indicates whether WRMSR should signal Machine-Check upon BIST-error
(WRITE).
BIST result PASS(0)/FAIL(1) of the (least significant set bit) array
indicated in EAX (READ).
Register Address: 10AH, 266
IA32_ARCH_CAPABILITIES
Enumeration of Architectural Features (R/O)
See Table 2-2.
Register Address: 1A4H, 420
MSR_PREFETCH_CONTROL
Prefetch Disable Bits (R/W)
0
L2_HARDWARE_PREFETCHER_DISABLE
If 1, disables the L2 hardware prefetcher, which fetches additional lines of
code or data into the L2 cache.
1
L2_ADJACENT_CACHE_LINE_PREFETCHER_DISABLE
If 1, disables the adjacent cache line prefetcher, which fetches the cache
line that comprises a cache line pair (128 bytes).
2
DCU_HARDWARE_PREFETCHER_DISABLE
If 1, disables the L1 data cache prefetcher, which fetches the next cache
line into L1 data cache.
3
DCU_IP_PREFETCHER_DISABLE
If 1, disables the L1 data cache IP prefetcher, which uses sequential load
history (based on instruction pointer of previous loads) to determine
whether to prefetch additional lines.
4
Reserved.
5
AMP_PREFETCH_DISABLE
If 1, disables the L2 Adaptive Multipath Probability (AMP) prefetcher.
63:6
Reserved.
2-400 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-52. Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon® Scalable Processor Families
(CPUID Signature DisplayFamily_DisplayModel Values of 06_8FH and 06_CFH) (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 1ADH, 429
MSR_PRIMARY_TURBO_RATIO_LIMIT
Primary Maximum Turbo Ratio Limit (R/W)
Package
See Table 2-46.
Register Address: 1AEH, 430
MSR_TURBO_RATIO_LIMIT_CORES
See Table 2-50.
Package
Register Address: 1C4H, 452
IA32_XFD
Extended Feature Detect (R/W)
See Table 2-2.
Register Address: 1C5H, 453
IA32_XFD_ERR
XFD Error Code (R/W)
See Table 2-2.
Register Address: 2C2H, 706
MSR_COPY_SCAN_HASHES
COPY_SCAN_HASHES (W)
Die
63:0
SCAN_HASH_ADDR
Contains the linear address of the SCAN Test HASH Binary loaded into
memory.
Register Address: 2C3H, 707
MSR_SCAN_HASHES_STATUS
SCAN_HASHES_STATUS (R/O)
15:0
CHUNK_SIZE
Die
Chunk size of the test in KB.
23:16
NUM_CHUNKS
Die
Total number of chunks.
31:24
Reserved: all zeros.
39:32
ERROR_CODE
Thread
The error-code refers to the LP that runs WRMSR(2C2H).
0x0: No error reported.
0x1: Attempt to copy scan-hashes when copy already in progress.
0x2: Secure Memory not set up correctly.
0x3: Scan-image header Image_info.ProgramID doesn't match
RDMSR(2D9H)[31:24], or scan-image header Processor-Signature doesn't
match F/M/S, or scan-image header Processor-Flags doesn't match
PlatformID.
0x4: Reserved
0x5: Integrity check failed.
0x6: Re-install of scan test image attempted when current scan test
image is in use by other LPs.
50:40
Reserved: set to all zeros.
62:51
MAX_CORE_LIMIT
Die
Maximum Number of cores that can run Intel® In-field Scan simultaneously
minus 1.
0 means 1 core at a time.
Vol. 4
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-52. Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon® Scalable Processor Families
(CPUID Signature DisplayFamily_DisplayModel Values of 06_8FH and 06_CFH) (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
63
Valid
Die
Valid bit is set when COPY_SCAN_HASHES has completed successfully.
Register Address: 2C4H, 708
MSR_AUTHENTICATE_AND_COPY_CHUNK
AUTHENTICATE_AND_COPY_CHUNK (W)
Die
7:0
CHUNK_INDEX
Chunk Index, should be less than the total number of chunks defined by
NUM_CHUNKS (MSR_SCAN_HASHES_STATUS[23:16]).
63:8
CHUNK_ADDR
Bits 63:8 of 256B aligned Linear address of scan chunk in memory.
Register Address: 2C5H, 709
MSR_CHUNKS_AUTHENTICATION_STATUS
CHUNKS_AUTHENTICATION_STATUS (R/O)
7:0
VALID_CHUNKS
Die
Total number of Valid (authenticated) chunks.
15:8
TOTAL_CHUNKS
Die
Total number of chunks.
31:16
Reserved: all zeros.
39:32
ERROR_CODE
Thread
The error code refers to the LP that runs WRMSR(2C4H).
0x0: No error reported.
0x1: Attempt to authenticate a CHUNK which is already marked as
authentic or is currently being installed by another core.
0x2: CHUNK authentication error. HASH of chunk did not match expected
value.
63:40
Reserved: set to all zeros.
Register Address: 2C6H, 710
MSR_ACTIVATE_SCAN
ACTIVATE_SCAN (W)
Thread
7:0
CHUNK_START_INDEX
Indicates chunk index to start from.
15:8
CHUNK_STOP_INDEX
Indicates what chunk index to stop at (inclusive).
31:16
Reserved: all zeros.
62:32
THREAD_WAIT_DELAY
TSC based delay to allow threads to rendezvous.
63
SIGNAL_MCE
If 1, then on scan-error log MC in MC4_STATUS and signal MCE if machine
check signaling enabled in MC4_CTL[0].
If 0, then no logging/no signaling.
Register Address: 2C7H, 711
MSR_SCAN_STATUS
SCAN_STATUS (R/O)
2-402 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-52. Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon® Scalable Processor Families
(CPUID Signature DisplayFamily_DisplayModel Values of 06_8FH and 06_CFH) (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
7:0
CHUNK_NUM
Core
SCAN Chunk that was reached.
15:8
CHUNK_STOP_INDEX
Core
Indicates what chunk index to stop at (inclusive). Maps to same field in
WRMSR(ACTIVATE_SCAN).
31:16
Reserved: return all zeros.
39:32
ERROR_CODE
Thread
0x0: No error.
0x1: SCAN operation did not start. Other thread did not join in time.
0x2: SCAN operation did not start. Interrupt occurred prior to threads
rendezvous.
0x3: SCAN operation did not start. Power Management conditions are
inadequate to run Intel In-field Scan.
0x4: SCAN operation did not start. Non-valid chunks in the range
CHUNK_STOP_INDEX : CHUNK_START_INDEX.
0x5: SCAN operation did not start. Mismatch in arguments between
threads T0/T1.
0x6: SCAN operation did not start. Core not capable of performing SCAN
currently.
0x8: SCAN operation did not start. Exceeded number of Logical
Processors (LP) allowed to run Intel In-field Scan concurrently.
MAX_CORE_LIMIT exceeded.
0x9: Interrupt occurred. Scan operation aborted prematurely, not all
chunks requested have been executed.
61:40
Reserved: return all zeros.
62
SCAN_CONTROL_ERROR
Core
Scan-System-Controller malfunction.
63
SCAN_SIGNATURE_ERROR
Core
Core failed SCAN-SIGNATURE checking for this chunk.
Register Address: 2C8H, 712
MSR_SCAN_MODULE_ID
SCAN_MODULE_ID (R/O)
Module
31:0
RevID of the currently installed scan test image. Maps to Revision field in
external header (offset 4).
63:32
Reserved: return all zeros.
Register Address: 2C9H, 713
MSR_LAST_SAF_WP
LAST_SAF_WP (R/O)
Core
31:0
LAST_WP
Provides information about the core when the last
WRMSR(ACTIVATE_SCAN) was executed. Available only if enumerated in
MSR_INTEGRITY_CAPABILITIES[10:9].
63:32
Reserved: return all zeros.
Register Address: 2D9H, 729
MSR_INTEGRITY_CAPABILITIES
Vol. 4
2-403
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-52. Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon® Scalable Processor Families
(CPUID Signature DisplayFamily_DisplayModel Values of 06_8FH and 06_CFH) (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
INTEGRITY_CAPABILITIES (R/O)
Module
0
STARTUP_SCAN_BIST
When set, supports Intel In-field Scan.
3:1
Reserved: return all zeros.
4
PERIODIC_SCAN_BIST
When set, supports Intel In-field Scan.
23:5
Reserved: return all zeros.
31:24
ID of the scan programs supported for this part. WRMSR(2C2H) verifies
this value against the corresponding value in the scan-image header, i.e.,
Image_info.
Register Address: 410H, 1040
IA32_MC4_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC4 reports MC errors from the PCU module.
If SIGNAL_MCE is set, a Scan Status is logged in MC4_STATUS and MC4_MISC.
Register Address: 411H, 1041
IA32_MC4_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC4 reports MC errors from the PCU module.
If SIGNAL_MCE is set, a Scan Status is logged in MC4_STATUS and MC4_MISC.
Register Address: 412H, 1042
IA32_MC4_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC4 reports MC errors from the PCU module.
If SIGNAL_MCE is set, a Scan Status is logged in MC4_STATUS and MC4_MISC.
Register Address: 413H, 1043
IA32_MC4_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC4 reports MC errors from the PCU module.
If SIGNAL_MCE is set, a Scan Status is logged in MC4_STATUS and MC4_MISC.
Register Address: 492H, 1170
IA32_VMX_PROCBASED_CTLS3
Capability Reporting Register of Tertiary Processor-Based VM-Execution Controls (R/O)
See Table 2-2.
Register Address: 493H, 1171
IA32_VMX_EXIT_CTLS2
Capability Reporting Register of Secondary VM-Exit Controls (R/O)
See Table 2-2.
Register Address: 540H, 1344
MSR_THREAD_UARCH_CTL
Thread Microarchitectural Control (R/W)
Thread
See Table 2-47.
Register Address: 64DH, 1613
MSR_PLATFORM_ENERGY_STATUS
Platform Energy Status (R/O)
Package
31:0
TOTAL_ENERGY_CONSUMED
Total energy consumption in J (32.0), in 10nsec units.
2-404 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-52. Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon® Scalable Processor Families
(CPUID Signature DisplayFamily_DisplayModel Values of 06_8FH and 06_CFH) (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
63:32
TIME_STAMP
Time stamp (U32.0).
Register Address: 65CH, 1628
MSR_PLATFORM_POWER_LIMIT
Platform Power Limit Control (R/W-L)
Package
16:0
POWER_LIMIT_1
The average power limit value that the platform must not exceed over a
time window as specified by the Power_Limit_1_TIME field.
The default value is the Thermal Design Power (TDP) and varies with
product skus. The unit is specified in MSR_RAPL_POWER_UNIT.
17
POWER_LIMIT_1_EN
When set, the processor can apply control policies such that the platform
average power does not exceed the Power_Limit_1 value over an
exponential weighted moving average of the time window.
18
CRITICAL_POWER_CLAMP_1
When set, the processor can go below the OS-requested P States to
maintain the power below the specified Power_Limit_1 value.
25:19
POWER_LIMIT_1_TIME
This indicates the time window over which the Power_Limit_1 value
should be maintained.
This field is made up of two numbers from the following equation:
Time Window = (float) ((1+(X/4))*(2^Y)), where:
X = POWER_LIMIT_1_TIME[23:22]
Y = POWER_LIMIT_1_TIME[21:17]
The maximum allowed value in this field is defined in
MSR_PKG_POWER_INFO[PKG_MAX_WIN].
The default value is 0DH, and the unit is specified in
MSR_RAPL_POWER_UNIT[Time Unit].
31:26
Reserved.
48:32
POWER_LIMIT_2
This is the Duration Power limit value that the platform must not exceed.
The unit is specified in MSR_RAPL_POWER_UNIT.
49
Enable Platform Power Limit #2
When set, enables the processor to apply control policy such that the
platform power does not exceed Platform Power limit #2 over the Short
Duration time window.
50
Platform Clamping Limitation #2
When set, allows the processor to go below the OS requested P states in
order to maintain the power below specified Platform Power Limit #2
value.
57:51
POWER_LIMIT_2_TIME
This indicates the time window over which the Power_Limit_2 value
should be maintained.
This field has the same format as the POWER_LIMIT_1_TIME field.
Vol. 4
2-405
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-52. Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon® Scalable Processor Families
(CPUID Signature DisplayFamily_DisplayModel Values of 06_8FH and 06_CFH) (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
62:58
Reserved.
63
LOCK
Setting this bit will lock all other bits of this MSR until system RESET.
Register Address: 665H, 1637
MSR_PLATFORM_POWER_INFO
Platform Power Information (R/W)
Package
16:0
MAX_PPL1
Maximum PP L1 value.
The unit is specified in MSR_RAPL_POWER_UNIT.
31:17
MIN_PPL1
Minimum PP L1 value.
The unit is specified in MSR_RAPL_POWER_UNIT.
48:32
MAX_PPL2
Maximum PP L2 value.
The unit is specified in MSR_RAPL_POWER_UNIT.
55:49
MAX_TW
Maximum time window.
The unit is specified in MSR_RAPL_POWER_UNIT.
62:56
Reserved.
63
LOCK
Setting this bit will lock all other bits of this MSR until system RESET.
Register Address: 666H, 1638
MSR_PLATFORM_RAPL_SOCKET_PERF_STATUS
Platform RAPL Socket Performance Status (R/O)
Package
31:0
Count of limited performance due to platform RAPL limit.
Register Address: 6A0H, 1696
IA32_U_CET
Configure User Mode CET (R/W)
See Table 2-2.
Register Address: 6A2H, 1698
IA32_S_CET
Configure Supervisor Mode CET (R/W)
See Table 2-2.
Register Address: 6A4H, 1700
IA32_PL0_SSP
Linear address to be loaded into SSP on transition to privilege level 0. (R/W)
See Table 2-2.
Register Address: 6A5H, 1701
IA32_PL1_SSP
Linear address to be loaded into SSP on transition to privilege level 1. (R/W)
See Table 2-2.
Register Address: 6A6H, 1702
IA32_PL2_SSP
Linear address to be loaded into SSP on transition to privilege level 2. (R/W)
See Table 2-2.
Register Address: 6A7H, 1703
IA32_PL3_SSP
2-406 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-52. Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon® Scalable Processor Families
(CPUID Signature DisplayFamily_DisplayModel Values of 06_8FH and 06_CFH) (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Linear address to be loaded into SSP on transition to privilege level 3. (R/W)
See Table 2-2.
Register Address: 6A8H, 1704
IA32_INTERRUPT_SSP_TABLE_ADDR
Linear address of a table of seven shadow stack pointers that are selected in IA-32e mode using the IST index (when
not 0) from the interrupt gate descriptor. (R/W)
See Table 2-2.
Register Address: 6E1H, 1761
IA32_PKRS
Specifies the PK permissions associated with each protection domain for supervisor pages (R/W)
See Table 2-2.
Register Address: 776H, 1910
IA32_HWP_CTL
See Table 2-2.
Register Address: 981H, 2433
IA32_TME_CAPABILITY
Memory Encryption Capability MSR
See Table 2-2.
Register Address: 985H, 2437
IA32_UINTR_RR
User Interrupt Request Register (R/W)
See Table 2-2.
Register Address: 986H, 2438
IA32_UINTR_HANDLER
User Interrupt Handler Address (R/W)
See Table 2-2.
Register Address: 987H, 2439
IA32_UINTR_STACKADJUST
User Interrupt Stack Adjustment (R/W)
See Table 2-2.
Register Address: 988H, 2440
IA32_UINTR_MISC
User-Interrupt Target-Table Size and Notification Vector (R/W)
See Table 2-2.
Register Address: 989H, 2441
IA32_UINTR_PD
User Interrupt PID Address (R/W)
See Table 2-2.
Register Address: 98AH, 2442
IA32_UINTR_TT
User-Interrupt Target Table (R/W)
See Table 2-2.
Register Address: C70H, 3184
MSR_B1_PMON_EVNT_SEL0
Uncore B-box 1 perfmon event select MSR.
Package
Register Address: C71H, 3185
MSR_B1_PMON_CTR0
Uncore B-box 1 perfmon counter MSR.
Package
Register Address: C72H, 3186
MSR_B1_PMON_EVNT_SEL1
Uncore B-box 1 perfmon event select MSR.
Package
Vol. 4
2-407
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-52. Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon® Scalable Processor Families
(CPUID Signature DisplayFamily_DisplayModel Values of 06_8FH and 06_CFH) (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: C73H, 3187
MSR_B1_PMON_CTR1
Uncore B-box 1 perfmon counter MSR.
Package
Register Address: C74H, 3188
MSR_B1_PMON_EVNT_SEL2
Uncore B-box 1 perfmon event select MSR.
Package
Register Address: C75H, 3189
MSR_B1_PMON_CTR2
Uncore B-box 1 perfmon counter MSR.
Package
Register Address: C76H, 3190
MSR_B1_PMON_EVNT_SEL3
Uncore B-box 1vperfmon event select MSR.
Package
Register Address: C77H, 3191
MSR_B1_PMON_CTR3
Uncore B-box 1 perfmon counter MSR.
Package
Register Address: C82H, 3122
MSR_W_PMON_BOX_OVF_CTRL
Uncore W-box perfmon local box overflow control MSR.
Package
Register Address: C8FH, 3215
IA32_PQR_ASSOC
See Table 2-2.
Register Address: C90H-C9EH, 3216-
IA32_L3_QOS_MASK_0 through IA32_L3_QOS_MASK_14
3230
See Table 2-50.
Package
Register Address: D10H-D17H, 3344-
IA32_L2_QOS_MASK_[0-7]
3351
IA32_CR_L2_QOS_MASK_[0-7]
Core
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] ≥ 0. See Table 2-2.
Register Address: D93H, 3475
IA32_PASID
See Table 2-2.
Register Address: 1200H-121FH, 4608-
IA32_LBR_x_INFO
4639
Last Branch Record Entry X Info Register (R/W)
See Table 2-2.
Register Address: 1406H, 5126
IA32_MCU_CONTROL
See Table 2-2.
Register Address: 14CEH, 5326
IA32_LBR_CTL
Last Branch Record Enabling and Configuration Register (R/W)
See Table 2-2.
Register Address: 14CFH, 5327
IA32_LBR_DEPTH
Last Branch Record Maximum Stack Depth Register (R/W)
See Table 2-2.
Register Address: 1500H-151FH, 5376-
IA32_LBR_x_FROM_IP
5407
Last Branch Record Entry X Source IP Register (R/W)
See Table 2-2.
2-408 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-52. Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon® Scalable Processor Families
(CPUID Signature DisplayFamily_DisplayModel Values of 06_8FH and 06_CFH) (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 1600H-161FH, 5632-
IA32_LBR_x_TO_IP
5663
Last Branch Record Entry X Destination IP Register (R/W)
See Table 2-2.
2.17.9 MSRs Introduced in the Intel® Core™ Ultra 7 Processor Supporting Performance Hybrid
Architecture
Table 2-53 lists additional MSRs for the Intel Core Ultra 7 processor with a CPUID Signature DisplayFamily_Display-
Model value of 06_AAH. Table 2-54 lists the MSRs unique to the processor P-core. Table 2-55 lists the MSRs unique
to the processor E-core.
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 33H, 51
MSR_MEMORY_CTRL
Memory Control Register
Core
26:0
Reserved.
27
UC_STORE_THROTTLE
If set to 1, when enabled, the processor will only allow one in-
progress UC store at a time.
28
UC_LOCK_DISABLE
If set to 1, a UC lock will cause a #GP(0) exception.
See Section 9.1.2.3, “Features to Disable Bus Locks.”
29
SPLIT_LOCK_DISABLE
If set to 1, a split lock will cause an #AC(0) exception.
See Section 9.1.2.3, “Features to Disable Bus Locks.”
63:30
Reserved.
Register Address: 7AH, 122
IA32_FEATURE_ACTIVATION
Feature Activation (R/W)
Implements Feature Activation command. WRMSR to this address activates all 'activatable' features on this thread.
See Table 2-2.
Register Address: 80H, 128
MSR_TRACE_HUB_STH_ACPIBAR_BASE
MSR_TRACE_HUB_STH_ACPIBAR_BASE (R/W)
Thread
This register is used by BIOS to program Trace Hub STH base address that will be used by AET messages.
0
LOCK
Lock bit. If set, this MSR cannot be re-written anymore. The lock
bit has to be set in order for the AET packets to be directed to
Trace Hub MMIO.
17:1
Reserved.
Vol. 4
2-409
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
45:18
ADDRESS
AET target address in Trace Hub MMIO space.
63:46
Reserved.
Register Address: E2H, 226
MSR_PKG_CST_CONFIG_CONTROL
C-State Configuration (R/W)
Core
3:0
PKG_C_STATE_LIMIT
Specifies the lowest processor-specific C-state code name
(consuming the least power) for the package.
The default is set as factory-configured package C-state limit.
The following C-state code name encodings may be supported:
0000b: C0/C1 (no package C-state support)
0001b: C2
0010b: C3
0011b: C6
0100b: C7
0101b: C7s
0110b: C8
0111b: C9
1000b: C10
7:4
MAX_CORE_C_STATE
Possible values are: 0000-reserved; 0001-C1; 0010-C3,
0011-C6.
9:8
Reserved.
10
IO_MWAIT_REDIRECTION_ENABLE
When set, will map IO_read instructions sent to IO registers
PMG_IO_BASE_ADDR.PMB0+0/1/2 to MWAIT(C2,3,4) instructions;
applies to deepc4 too.
14:11
Reserved.
15
CFG_LOCK
When set, locks bits 15:0 of this register for further writes, until
the next reset occurs.
24:16
Reserved.
25
C3_STATE_AUTO_DEMOTION_ENABLE
When set, processor will conditionally demote C6/C7 requests to
C3 based on uncore auto-demote information.
26
C1_STATE_AUTO_DEMOTION_ENABLE
When set, processor will conditionally demote C3/C6/C7 requests
to C1 based on uncore auto-demote information.
27
ENABLE_C3_UNDEMOTION
Enable Un-Demotion from Demoted C3.
2-410 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
28
ENABLE_C1_UNDEMOTION
Enable Un-Demotion from Demoted C1.
29
ENABLE_PKGC_AUTODEMOTION
Enable Package C-State Auto-Demotion. It enables use of the
history of past package C-state depth and residence, as a factor in
determining C-State depth.
30
ENABLE_PKGC_UNDEMOTION
Enable Package C-State Un-Demotion. It enables considering
cases where demotion was the incorrect decision in determining
C-State depth.
31
TIMED_MWAIT_ENABLE
When set, enables Timed MWAIT feature. MWAIT would #GP on
attempts to do setup MWAIT timer if this bit is not set.
63:32
Reserved.
Register Address: E4H, 228
MSR_IO_CAPTURE_BASE
IO Capture Base (R/W)
Core
Power Management IO Redirection in C-state. See http://biosbits.org.
15:0
LVL_2_BASE_ADDRESS
Specifies the base address visible to software for IO redirection. If
MSR_PKG_CST_CONFIG_CONTROL.IO_MWAIT_REDIRECTION_ENA
BLE, reads to this address will be consumed by the power
management logic and decoded to MWAIT instructions. When IO
port address redirection is enabled, this is the IO port address
reported to the OS/software.
18:16
CST_RANGE
Specifies the encoding value of the maximum C-State code name
to be included when IO read to MWAIT redirection is enabled by
MSR_PKG_CST_CONFIG_CONTROL.IO_MWAIT_REDIRECTION_ENA
BLE:
000b-C3 is the max C-State to include.
001b-C6 is the max C-State to include.
010b-C7 is the max C-State to include.
63:19
Reserved.
Register Address: 13CH, 316
MSR_FEATURE_CONFIG
AES Feature Configuration (R/W)
Core
0
AESNI_LOCK
Once this bit is set, writes to this register will not be allowed.
1
AESNI_DISABLE
This bit disables Advanced Encryption Standard feature on this
processor core. To disable AES, BIOS will write '11 to this MSR on
every core.
63:2
Reserved.
Register Address: 140H, 320
MSR_FEATURE_ENABLES
Vol. 4
2-411
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Feature Enable (R/W)
Thread
Miscellaneous enables for thread specific features.
0
CPUID_GP_ON_CPL_GT_0
Causes CPUID to #GP if CPL greater than 0 and not in SMM.
63:1
Reserved.
Register Address: 1A2H, 418
MSR_TEMPERATURE_TARGET
Temperature Target (R/W)
Package
Legacy register holding temperature related constants for Platform use.
6:0
TCC Offset Time Window
Describes the RATL averaging time window.
7
TCC Offset Clamping Bit
When enabled will allow RATL throttling below P1.
15:8
Temperature Control Offset
Fan Temperature Target Offset (a.k.a. T-Control) indicates the
relative offset from the Thermal Monitor Trip Temperature at
which fans should be engaged.
23:16
TCC Activation Temperature
The minimum temperature at which PROCHOT# will be asserted.
The value is degrees C.
30:24
TCC Activation Offset
Specifies a temperature offset in degrees C from the temperature
target (bits 23:16). PROCHOT# will assert at the offset target
temperature. Write is permitted only if
MSR_PLATFORM_INFO[30] is set.
31
LOCKED
When set, this entire register becomes read-only.
63:2
Reserved.
Register Address: 1A4H, 420
MSR_PREFETCH_CONTROL
PREFETCH Control (R/W)
Thread
Prefetch disable bits.
0
L2_HARDWARE_PREFETCHER_DISABLE
If 1, disables the L2 hardware prefetcher, which fetches
additional lines of code or data into the L2 cache.
1
L2_ADJACENT_CACHE_LINE_PREFETCHER_DISABLE
If 1, disables the adjacent cache line prefetcher, which fetches the
cache line that comprises a cache line pair (128 bytes).
2
DCU_HARDWARE_PREFETCHER_DISABLE
If 1, disables the L1 data cache prefetcher, which fetches the next
cache line into L1 data cache.
2-412 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
3
DCU_IP_PREFETCHER_DISABLE
If 1, disables the L1 data cache IP prefetcher, which uses
sequential load history (based on instruction pointer of previous
loads) to determine whether to prefetch additional lines.
4
DCU_NEXT_PAGE_PREFETCH_DISABLE
If 1, disables Next Page prefetcher.
5
AMP_PREFETCH_DISABLE
If 1, disables L2 Adaptive Multipath Probability (AMP) prefetcher.
6
LLC_PAGE_PREFETCH_DISABLE
If 1, disables the LLC Page prefetcher.
7
AOP_PREFETCH_DISABLE
8
STREAM_PREFETCH_CODE_FETCH_DISABLE
63:9
Reserved.
Register Address: 1A6H, 422
MSR_OFFCORE_RSP_0
OFFCORE_RSP_0 (R/W)
Thread
Offcore Response Event Select Register
0
TRUE_DEMAND_CACHE_LOAD
Demand Data Rd = DCU reads (includes partials) that is not tagged
homeless.
1
DEMAND_RFO
Demand Instruction fetch = IFU Fetches. ItoM or RFO that is not
tagged homeless.
2
DEMAND_CODE_READ
Demand Instruction fetch = IFU Fetches. CRd or CRd_UC.
3
CORE_MODIFIED_WRITEBACK
WBMtoI or WBMtoE.
4
HW_PREFETCH_MLC_LOAD
L2 prefetcher requests triggered by reads from MEC (except
those triggered by I-side).
5
HW_PREFETCH_MLC_RFO
L2 prefetcher requests triggered by RFOs.
6
HW_PREFETCH_MLC_CODE
L2 prefetcher requests triggered by I-side requests.
7
HW_PREFETCH_LLC_LOAD
LLC prefetch requests triggered by DRd.
8
HW_PREFETCH_LLC_RFO
LLC prefetch requests triggered by RFO.
9
HW_PREFETCH_LLC_CODE
LLC prefetch requests triggered by CRd.
Vol. 4
2-413
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
10
L1_HWPREFETCH
Covers Hardware PFRFO, PFNEAR, PFMED, PFFAR, PFHW, PFNTA,
PFNPP, PFIPP including the homeless versions.
11
ALL_STREAMING_STORE
Write Combining. WCiL or WCiLF.
12
CORE_NON_MODIFIED_WB
WBEFtoI or WBEFtoE.
13
LLC_PREFETCH
LLC prefetch of load/code/RFO.
14
L1_SWPREFETCH
Covers Software PFRFO, PFNEAR, PFMED, PFFAR, PFHW, PFNTA,
PFNPP, PFIPP including the homeless versions.
15
OTHER
Includes CLFlush, CLFlushOPT, CLDemote, CLWB, Enqueue
SetMonitor, PortIn, IntA, Lock, SplitLock, Unlock, SpCyc, ClrMonitor,
PortOut, IntPriUp, IntLog, IntPhy, EOI, RdCurr, WbStoI, LLCWBInv,
LLCInv, NOP, PCOMMIT.
16
ANY_RESP
Match on any response.
17
SUPPLIER_NONE
No Supplier Details. DATA_PRE [6:3] = 0.
18
LLC_HIT_M_STATE
LLC/L3, M-state, DATA_PRE [6:3] = 2.
19
LLC_HIT_E_STATE
LLC/L3, E-state, DATA_PRE [6:3] = 4.
20
LLC_HIT_S_STATE
LLC/L3, S-state, DATA_PRE [6:3] = 6.
21
LLC_HIT_F_STATE
LLC/L3, F-state, DATA_PRE [6:3] = 8.
22
FAR_MEM_LOCAL
Far Memory, Local, DATA_PRE [6:3] = 1.
23
FAR_MEM_REMOTE_0_HOP
Far Memory, Remote 0-hop, DATA_PRE [6:3] = 3.
24
FAR_MEM_REMOTE_1_HOP
Far Memory, Remote 1-hop, DATA_PRE [6:3] = 5.
25
FAR_MEM_REMOTE_2_PLUS_HOP
Far Memory, Rem 2+ hop, DATA_PRE [6:3] = 7.
26
NEAR_MEM_MISS_LOCAL_NODE
LLC Miss Local Node. Near Memory, Local DATA_PRE [6:3] = E.
27
NEAR_MEM_REMOTE_0_HOP
Near Memory, Remote 0-hop, DATA_PRE [6:3] = B
2-414 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
28
NEAR_MEM_REMOTE_1_HOP
Near Memory, Remote 1-hop, DATA_PRE [6:3] = D.
29
NEAR_MEM_REMOTE_2_PLUS_HOP
Near Memory, Remote 2+ hop, DATA_PRE [6:3] = F.
30
SPL_HIT
Snoop Info: SPL-hit, DATA_PRE [2:0] = 6.
31
SNOOP_NONE
No details as to Snoop-related info. Snoop Info: None, DATA_PRE
[2:0] = 0.
32
NOT_NEEDED
No snoop was needed to satisfy the request. Snoop Info: Not
needed, DATA_PRE [2:0] = 1.
33
MISS
No snoop was needed to satisfy the request. Snoop Info: Miss,
DATA_PRE [2:0] = 2.
34
HIT_NO_FWD
A snoop was needed and it Hits in at least one snooped cache. Hit
denotes a cache-line was valid before snoop effect. Snoop Info:
Hit No Fwd, DATA_PRE [2:0] = 3.
35
HIT_EF_WITH_FWD
A snoop was needed and data was Forwarded from a remote
socket. Snoop Info: Hit EF w/Fwd, DATA_PRE [2:0] = 4.
36
HITM
A snoop was needed and it HitMed in local or remote cache. HitM
denotes a cache-line was modified before snoop effect. Snoop
Info: HitM, DATA_PRE [2:0] = 5.
37
NON_DRAM
Target was non-DRAM system address. Snoop Info: HitM,
DATA_PRE [2:0] = 5.
38
GO_ERR
GO-ERR, RspData[3:0] = 0100.
39
GO_NO_GO
GO-NoGO, RspData[3:0] = 0111.
40
INPKG_MEM_LOCAL
In-package Memory, Local, DATA_PRE [6:3] = 9.
41
INPKG_MEM_NONLOCAL
In-package Memory, Non-Local, DATA_PRE [6:3] = C.
43:42
Reserved.
44
UC_LOAD
PRd or UCRdF.
45
UC_STORE
WiL.
Vol. 4
2-415
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
46
PARTIAL_STREAMING_STORES
WCiL.
47
FULL_STREAMING_STORES
WCiLF.
48
L1_MODIFIED_WB
EVICTION EXTTYPE from MEC.
49
L2_MODIFIED_WB
WBMtoI or WBMtoE.
50
PSMI
MemPushWr_NS (PSMI only).
51
ITOM
ItoM.
63:52
Reserved.
Register Address: 1A7H, 423
MSR_OFFCORE_RSP_1
OFFCORE_RSP_1 (R/W)
Thread
Offcore Response Event Select Register. See MSR_OFFCORE_RSP_0 (at1A6H).
Register Address: 1AAH, 426
MSR_MISC_PWR_MGMT
Miscellaneous Power Management Control (R/W)
Package
Various model-specific features enumeration. See http://biosbits.org.
0
Reserved.
1
ENABLE_HWP_VOTING_RIGHT
When set (1), The CPU will take into account thread HWP requests
for threads that have voting rights only (ignores thread requests
if they do not have voting rights). When reset(0), The CPU will
take into account all thread HWP requests, even for threads that
don't have voting rights. Setting this bit will cause the HWP Base
feature bit to be reported in CPUID as present; clearing will cause
it to be reported as non-present.
5:2
Reserved.
6
ENABLE_HWP
Setting this bit will cause the HWP Base feature bit to report as
present in CPUID; clearing this bit will cause CPUID to report the
feature as non-present.
7
ENABLE_HWP_INTERRUPT
Setting this bit will cause the HWP Interrupt feature
CPUID[6].EAX[8] bit to report as present; clearing will report as
non-present.
8
ENABLE_OUT_OF_BAND_AUTONOMOUS
Setting this bit will cause the HWP Autonomous feature bit to
report as present; clearing will report as non-present.
11:9
Reserved.
2-416 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
12
ENABLE_HWP_EPP
Enable HWP EPP. Setting this bit (1) will cause the HWP
CPUID[6].EAX[10] Energy Performance Preference bit to report
as present (1); clearing will report as non-present (0).
13
LOCK
Setting this bit will prevent the BIOS specific bits from changing
until the next reset. i.e., only Bits [0,22] which are meant for OS
use can be changed once the LOCK bit is set.
63:14
Reserved.
Register Address: 1ADH, 429
MSR_PRIMARY_TURBO_RATIO_LIMIT
Primary Maximum Turbo Ratio Limit (R/W)
Package
Software can configure these limits when MSR_PLATFORM_INFO[28] = 1. Specifies Maximum Ratio Limit for each
group. Maximum ratio for groups with more cores must decrease monotonically.
7:0
MAX_TURBO_GROUP_0:
Maximum turbo ratio limit with 1 core active.
15:8
MAX_TURBO_GROUP_1:
Maximum turbo ratio limit with 2 cores active.
23:16
MAX_TURBO_GROUP_2:
Maximum turbo ratio limit with 3 cores active.
31:24
MAX_TURBO_GROUP_3:
Maximum turbo ratio limit with 4 cores active.
39:32
MAX_TURBO_GROUP_4:
Maximum turbo ratio limit with 5 cores active.
47:40
MAX_TURBO_GROUP_5:
Maximum turbo ratio limit with 6 cores active.
55:48
MAX_TURBO_GROUP_6:
Maximum turbo ratio limit with 7 cores active.
63:56
MAX_TURBO_GROUP_7:
Maximum turbo ratio limit with 8 cores active.
Register Address: 1F1H, 497
MSR_CRASHLOG_CONTROL
Crash Log Control (R/W)
Thread
Write data to a Crash Log configuration.
0
CDDIS
CrashDump_Disable: If set, indicates that Crash Dump is disabled.
1
EN_GPRS
Collect GPRs on a crash dump. Only meaningful when CDDIS is
zero.
2
EN_GPRS_IN_SMM
Collect GPRs in SMM on a crash dump. Only meaningful when
CDDIS is zero. EN_GPRS will override this control,
Vol. 4
2-417
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
3
TRIPLE_FAULT_SHUTDOWN
Collect a crash log on a triple fault shutdown. Only meaningful
when CDDIS is zero.
63:4
Reserved.
Register Address: 1F5H, 501
MSR_PRMRR_PHYS_MASK
Processor Reserved Memory Range Register - Physical Mask (R/W)
Core
9:0
Reserved.
10
LOCK
Once set, this bit prevents software from modifying the PRMRR.
11
VALID
This bit serves as the enable for the PRMRR; the PRMRR must be
LOCKed before it can be enabled.
19:12
Reserved.
45:20
MASK
PRMRR Address Mask.
63:46
Reserved.
Register Address: 1FCH, 508
MSR_POWER_CTL
Power Control Register (R/W)
Package
0
ENABLE_BIDIR_PROCHOT
Used to enable or disable the response to PROCHOT# input.
When set/enabled, the platform can force the CPU to throttle to a
lower power condition such as Pn/Pm by asserting prochot#.
When clear/disabled (default), the CPU ignores the status of the
prochot input signal.
1
C1E_ENABLE
When set to '1', will enable the CPU to switch to the Minimum
Enhanced Intel SpeedStep Technology operating point when all
execution cores enter MWAIT (C1).
2
SAPM_IMC_C2_POLICY
This bit determines if self-refresh activation is allowed when
entering Package C2 State. If it is set to 0b, PCODE will keep the
FORCE_SR_OFF bit asserted in Package C2 State and allow its
negation according to the defined latency negotiations with the
PCH and Display Engine in Package C3 and deeper states.
Otherwise, self-refresh is allowed in Package C2 State.
3
FAST_BRK_SNP_EN
This bit controls the VID swing rate for the OTHER_SNP_WAKE
events that are detected by the iMPH. This is the event that is
detected by the iMPH when a non-DMI snoopable request is
observed while UCLK domain is not functional.
0b: Use slow VID swing rate.
1b: Use fast VID swing rate.
2-418 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
17:4
Reserved.
18
PWR_PERF_PLTFRM_OVR
Power performance platform override.
19
EE_TURBO_DISABLE
Setting this bit disables the P-States energy efficiency
optimization. Default value is 0. Disable/enable the energy
efficiency optimization in P-State legacy mode (when
IA32_PM_ENABLE[HWP_ENABLE] = 0), has an effect only in the
turbo range or into PERF_MIN_CTL value if it is not zero set. In
HWP mode (IA32_PM_ENABLE[HWP_ENABLE] == 1), has an
effect between the OS desired or OS maximize to the OS minimize
performance setting.
20
RTH_DISABLE
Setting this bit disables the Race to Halt optimization and avoids
this optimization limitation to execute below the most efficient
frequency ratio. Default value is 0 for processors that support
Race to Halt optimization.
21
DIS_PROCHOT_OUT
Prochot output disable.
22
PROCHOT_RESPONSE
Prochhot configurable response enable.
23
VR_THERM_ALERT_DISABLE_LOCK
When set to 1, locks PROCHOT related bits of this MSR. Once set,
a reset is required to clear this bit.
24
VR_THERM_ALERT_DISABLE
When set to 1, disables the VR_THERMAL_ALERT signaling.
25
DISABLE_RING_EE
Disable Ring EE.
26
DISABLE_SA_OPTIMIZATION
Disable SA optimization.
27
DISABLE_OOK
Disable OOK.
28
DISABLE_AUTONOMOUS
Disable HWP autonomous mode.
29
Reserved.
30
CSTATE_PREWAKE_DISABLE
C-state pre-wake disable.
63:31
Reserved.
Register Address: 2A0H, 672
MSR_PRMRR_BASE_0
Processor Reserved Memory Range Register - Physical Base Control Register (R/W)
Core
2:0
MEMTYPE
Memory type for PRMRR accesses.
Vol. 4
2-419
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
3
CONFIGURED
PRMRR base configured.
19:4
Reserved.
45:20
BASE
PRMRR base address.
63:46
Reserved.
Register Address: 474H, 1140
IA32_MC29_CTL
MC29_CTL. See Table 2-2.
Package
Register Address: 475H, 1141
IA32_MC29_STATUS
MC29_STATUS. See Table 2-2.
Package
Register Address: 476H, 1142
IA32_MC29_ADDR
MC29_ADDR. See Table 2-2.
Package
Register Address: 477H, 1143
IA32_MC29_MISC
MC29_MISC. See Table 2-2.
Package
Register Address: 478H, 1144
IA32_MC30_CTL
MC30_CTL. See Table 2-2.
Package
Register Address: 479H, 1145
IA32_MC30_STATUS
MC30_STATUS. See Table 2-2.
Package
Register Address: 47AH, 1146
IA32_MC30_ADDR
MC30_ADDR. See Table 2-2.
Package
Register Address: 47BH, 1147
IA32_MC30_MISC
MC30_MISC. See Table 2-2.
Package
Register Address: 47CH, 1148
IA32_MC31_CTL
MC31_CTL. See Table 2-2.
Package
Register Address: 47DH, 1149
IA32_MC31_STATUS
MC31_STATUS. See Table 2-2.
Package
Register Address: 47EH, 1150
IA32_MC31_ADDR
MC31_ADDR. See Table 2-2.
Package
Register Address: 47FH, 1151
IA32_MC31_MISC
MC31_MISC. See Table 2-2.
Package
Register Address: 4E0H, 1248
MSR_SMM_FEATURE_CONTROL
Enhanced SMM Feature Control (R/W)
Package
Reports SMM capability enhancement.
0
LOCK
When set, locks this register from further changes.
2-420 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
1
SMM_CPU_SAVE_EN
If 0, SMI/RSM will save/restore state in SMRAM
If 1, SMI/RSM will save/restore state from SRAM.
2
SMM_CODE_CHK_EN
When clear (default) none of the logical processors are prevented
from executing SMM code outside the ranges defined by the
SMRR. When set, any logical processor in the package that
attempts to execute SMM code not within the ranges defined by
the SMRR will assert an unrecoverable MCE.
63:3
Reserved.
Register Address: 601H, 1537
MSR_VR_CURRENT_CONFIG
Power Limit 4 (PL4) (R/W)
Package
Package-level maximum power limit (in Watts). It is a proactive, instantaneous limit.
15:0
CURRENT_LIMIT
PL4 Value in 0.125 A increments. This field is locked by
MSR_VR_CURRENT_CONFIG.LOCK. When the LOCK bit is set to 1,
this field becomes Read Only.
30:16
Reserved.
31
LOCK
This bit will lock the CURRENT_LIMIT settings in this register and
will also lock this setting. This means that once set to 1, the
CURRENT_LIMIT setting and this bit become Read Only until the
next Warm Reset.
63:32
Reserved.
Register Address: 620H, 1568
MSR_UNCORE_RATIO_LIMIT
Uncore Ratio Limit (R/W)
Package
Min/Max Ratio Limits for Uncore LLC and Ring.
6:0
MAX_CLR_RATIO
Maximum allowed ratio for the Ring and Last Level Cache (LLC).
7
Reserved.
14:8
MIN_CLR_RATIO
Minimum allowed ratio for the Ring and Last Level Cache (LLC).
63:15
Reserved.
Register Address: 638H, 1592
MSR_PP0_POWER_LIMIT
MSR_PP0_POWER_LIMIT (R/W)
Package
PP0 RAPL power unit control.
14:0
IA_PP_PWR_LIM
This is the power limitation on the IA cores power plane.
The unit of measurement is defined in
PACKAGE_POWER_SKU_UNIT_MSR[PWR_UNIT].
Vol. 4
2-421
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
15
PWR_LIM_CTRL_EN
This bit must be set in order to limit the power of the IA cores
power plane.
0b: IA cores power plane power limitation is disabled.
1b: IA cores power plane power limitation is enabled.
16
PP_CLAMP_LIM
Power Plane Clamping limitation; allow going below P1.
0b: PBM is limited between P1 and P0.
1b: PBM can go below P1.
23:17
CTRL_TIME_WIN
x = CTRL_TIME_WIN[23:22]
y = CTRL_TIME_WIN[21:17]
The timing interval window is Floating Point number given by 1.x
* power(2,y).
The unit of measurement is defined in
PACKAGE_POWER_SKU_UNIT_MSR[TIME_UNIT].
The maximal time window is bounded by
PACKAGE_POWER_SKU_MSR[PKG_MAX_WIN]. The minimum time
window is 1 unit of measurement (as defined above).
30:24
Reserved.
31
PP_PWR_LIM_LOCK
When set, all settings in this register are locked and are treated as
Read Only.
63:32
Reserved.
Register Address: 64FH, 1615
MSR_CORE_PERF_LIMIT_REASONS
Core Performance Limit Reasons
Package
Indicator of Frequency Clipping in Processor Cores. (Frequency refers to processor core frequency.)
0
PROCHOT (R/O)
PROCHOT Status. When set, frequency is reduced below the
operating system request due to assertion of external PROCHOT.
1
THERMAL (R/O)
Thermal Status. When set, frequency is reduced below the
operating system request due to a thermal event.
3:2
Reserved.
4
RSR_LIMIT (R/O)
Residency State Regulation Status. When set, frequency is
reduced below the operating system request due to residency
state regulation limit.
5
RATL (R/O)
Running Average Thermal Limit Status. When set, frequency is
reduced below the operating system request due to Running
Average Thermal Limit (RATL).
2-422 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
6
VR_THERMALERT (R/O)
VR Therm Alert Status. When set, frequency is reduced below the
operating system request due to a thermal alert from a processor
Voltage Regulator (VR).
7
VR_TDC (R/O)
VR Therm Design Current Status. When set, frequency is reduced
below the operating system request due to VR thermal design
current limit.
8
OTHER (R/O)
Other Status. When set, frequency is reduced below the operating
system request due to electrical or other constraints.
9
Reserved.
10
PBM_PL1 (R/O)
Package/Platform-Level Power Limiting PL1 Status. When set,
frequency is reduced below the operating system request due to
package/platform-level power limiting PL1.
11
PBM_PL2 (R/O)
Package/Platform-Level PL2 Power Limiting Status. When set,
frequency is reduced below the operating system request due to
package/platform-level power limiting PL2/PL3.
12
MAX_TURBO_LIMIT (R/O)
Max Turbo Limit Status. When set, frequency is reduced below
the operating system request due to multi-core turbo limits.
13
TURBO_ATTEN (R/O)
Turbo Transition Attenuation Status. When set, frequency is
reduced below the operating system request due to Turbo
transition attenuation. This prevents performance degradation
due to frequent operating ratio changes.
15:14
Reserved.
16
PROCHOT_LOG (R/W)
PROCHOT Log. When set, indicates that the PROCHOT Status bit
has asserted since the log bit was last cleared. This log bit will
remain set until cleared by software writing 0.
17
THERMAL_LOG (R/W)
Thermal Log When set, indicates that the Thermal Status bit has
asserted since the log bit was last cleared. This log bit will remain
set until cleared by software writing 0.
19:18
Reserved.
20
RSR_LIMIT_LOG (R/W)
Residency State Regulation Log. When set, indicates that the
Residency State Regulation Status bit has asserted since the log
bit was last cleared. This log bit will remain set until cleared by
software writing 0.
Vol. 4
2-423
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
21
RATL_LOG (R/W)
Running average thermal limit Log, RW, When set by PCODE
indicates that Running average thermal limit has cause IA
frequency clipping. Software should write to this bit to clear the
status in this bit.
22
VR_THERMALERT_LOG (R/W)
VR Therm Alert Log. When set, indicates that the VR Therm Alert
Status bit has asserted since the log bit was last cleared. This log
bit will remain set until cleared by software writing 0.
23
VR_TDC_LOG (R/W)
VR Thermal Design Current Log. When set, indicates that the VR
TDC Status bit has asserted since the log bit was last cleared. This
log bit will remain set until cleared by software writing 0.
24
OTHER_LOG (R/W)
Other Log. When set, indicates that the Other Status bit has
asserted since the log bit was last cleared. This log bit will remain
set until cleared by software writing 0.
25
Reserved.
26
PBM_PL1_LOG (R/W)
Package/Platform-Level PL1 Power Limiting Log. When set,
indicates that the Package or Platform Level PL1 Power Limiting
Status bit has asserted since the log bit was last cleared. This log
bit will remain set until cleared by software writing 0.
27
PBM_PL2_LOG (R/W)
Package/Platform-Level PL2 Power Limiting Log. When set,
indicates that the Package or Platform Level PL2/PL3 Power
Limiting Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
28
MAX_TURBO_LIMIT_LOG (R/W)
Max Turbo Limit Log. When set, indicates that the Max Turbo Limit
Status bit has asserted since the log bit was last cleared. This log
bit will remain set until cleared by software writing 0.
29
TURBO_ATTEN_LOG (R/W)
Turbo Transition Attenuation Log. When set, indicates that the
Turbo Transition Attenuation Status bit has asserted since the log
bit was last cleared. This log bit will remain set until cleared by
software writing 0.
63:30
Reserved.
Register Address: 650H, 1616
MSR_SECONDARY_TURBO_RATIO_LIMIT
Secondary Maximum Turbo Ratio Limit (R/W)
Package
Software can configure these limits when MSR_PLATFORM_INFO[28] = 1.
Specifies Maximum Ratio Limit for each group. Maximum ratio for groups with more cores must decrease
monotonically.
7:0
MAX_TURBO_GROUP_0:
Maximum turbo ratio limit with 1 core active.
2-424 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
15:8
MAX_TURBO_GROUP_1:
Maximum turbo ratio limit with 2 cores active.
23:16
MAX_TURBO_GROUP_2:
Maximum turbo ratio limit with 3 cores active.
31:24
MAX_TURBO_GROUP_3:
Maximum turbo ratio limit with 4 cores active.
39:32
MAX_TURBO_GROUP_4:
Maximum turbo ratio limit with 5 cores active.
47:40
MAX_TURBO_GROUP_5:
Maximum turbo ratio limit with 6 cores active.
55:48
MAX_TURBO_GROUP_6:
Maximum turbo ratio limit with 7 cores active.
63:56
MAX_TURBO_GROUP_7:
Maximum turbo ratio limit with 8 cores active.
Register Address: 65CH, 1628
MSR_PLATFORM_POWER_LIMIT
Platform Power Limit Control (R/W)
Package
Allows platform BIOS to limit power consumption of the platform devices to the specified values. The Long Duration
power consumption is specified via Platform_Power_Limit_1 and Platform_Power_Limit_1_Time. The Short Duration
power consumption limit is specified via the Platform_Power_Limit_2 with duration chosen by the processor. The
processor implements an exponential-weighted algorithm in the placement of the time windows.
14:0
POWER_LIMIT_1
Average Power limit value which the platform must not exceed
over a time window as specified by Power_Limit_1_TIME field.
The default value is the Thermal Design Power (a.k.a TDP) and
varies with product skus. The unit is specified in
MSR_RAPLPOWER_UNIT.
15
POWER_LIMIT_1_EN
When set, enables the processor to apply control policy such that
the platform power does not exceed Platform Power limit 1 over
the time window specified by Power Limit 1 Time Window.
16
CRITICAL_POWER_CLAMP_1
When set, allows the processor to go below the OS requested P
states in order to maintain the power below specified Platform
Power Limit 1 value.
Vol. 4
2-425
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
23:17
POWER_LIMIT_1_TIME
Specifies the duration of the time window over which Platform
Power Limit 1 value should be maintained for sustained long
duration. This field is made up of two numbers from the following
equation:
Time Window = (float) ((1+(X/4))*(2^Y)), where:
X = POWER_LIMIT_1_TIME[23:22]
Y = POWER_LIMIT_1_TIME[21:17]
The maximum allowed value in this field is defined in
MSR_PKG_POWER_INFO[PKG_MAX_WIN].
The default value is 0DH, The unit is specified in
MSR_RAPLPOWER_UNIT[Time Unit]
31:24
Reserved.
46:32
POWER_LIMIT_2
Average Power limit value which the platform must not exceed
over the Short Duration time window chosen by the processor.
The recommended default value is 1.25 times the Long Duration
Power Limit (i.e., Platform Power Limit 1).
47
POWER_LIMIT_2_EN
When set, enables the processor to apply control policy such that
the platform power does not exceed Platform Power limit 2 over
the Short Duration time window.
48
CRITICAL_POWER_CLAMP_2
When set, allows the processor to go below the OS requested P
states in order to maintain the power below specified Platform
Power Limit 2 value.
62:49
Reserved.
63
LOCK
Setting this bit will lock all other bits of this MSR until system
RESET.
Register Address: 6BOH, 1712
MSR_GRAPHICS_PERF_LIMIT_REASONS
MSR_GRAPHICS_PERF_LIMIT_REASONS
Package
Indicator of Frequency Clipping in the Processor Graphics. (Frequency refers to processor graphics frequency.)
0
PROCHOT (R/O)
PROCHOT Status. When set, frequency is reduced due to
assertion of external PROCHOT.
1
THERMAL (R/O)
Thermal Status. When set, frequency is reduced due to a thermal
event.
4:2
Reserved.
5
RATL (R/O)
Running Average Thermal Limit Status. When set, frequency is
reduced due to running average thermal limit.
2-426 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
6
VR_THERMALERT (R/O)
VR Therm Alert Status. When set, frequency is reduced due to a
thermal alert from a processor Voltage Regulator.
7
VR_TDC (R/O)
VR Thermal Design Current Status. When set, frequency is
reduced due to VR TDC limit.
8
OTHER (R/O)
Other Status. When set, frequency is reduced due to electrical or
other constraints.
9
Reserved.
10
PBM_PL1 (R/O)
Package/Platform-Level Power Limiting PL1 Status. When set,
frequency is reduced due to package/platform-level power
limiting PL1.
11
PBM_PL2 (R/O)
Package/Platform-Level PL2 Power Limiting Status. When set,
frequency is reduced due to package/platform-level power
limiting PL2/PL3.
12
INEFFICIENT_OPERATION (R/O)
Inefficient Operation Status. When set, processor graphics
frequency is operating below target frequency.
15:13
Reserved.
16
PROCHOT_LOG (R/W)
PROCHOT Log. When set, indicates that the PROCHOT Status bit
has asserted since the log bit was last cleared. This log bit will
remain set until cleared by software writing 0.
17
THERMAL_LOG (R/W)
Thermal Log. When set, indicates that the Thermal Status bit has
asserted since the log bit was last cleared. This log bit will remain
set until cleared by software writing 0.
20:18
Reserved.
21
RATL_LOG (R/W)
Running Average Thermal Limit Log. When set, indicates that the
RATL Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
22
VR_THERMALERT_LOG (R/W)
VR Therm Alert Log. When set, indicates that the VR Therm Alert
Status bit has asserted since the log bit was last cleared. This log
bit will remain set until cleared by software writing 0.
23
VR_TDC_LOG (R/W)
VR Thermal Design Current Log. When set, indicates that the VR
Therm Alert Status bit has asserted since the log bit was last
cleared. This log bit will remain set until cleared by software
writing 0.
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
24
OTHER_LOG (R/W)
Other Log. When set, indicates that the OTHER Status bit has
asserted since the log bit was last cleared. This log bit will remain
set until cleared by software writing 0.
25
Reserved.
26
PBM_PL1_LOG (R/W)
Package/Platform-Level PL1 Power Limiting Log. When set,
indicates that the Package/Platform Level PL1 Power Limiting
Status bit has asserted since the log bit was last cleared. This log
bit will remain set until cleared by software writing 0.
27
PBM_PL2_LOG (R/W)
Package/Platform-Level PL2 Power Limiting Log. When set,
indicates that the Package/Platform Level PL2 Power Limiting
Status bit has asserted since the log bit was last cleared. This log
bit will remain set until cleared by software writing 0.
28
INEFFICIENT_OPERATION_LOG (R/W)
Inefficient Operation Log. When set, indicates that the Inefficient
Operation Status bit has asserted since the log bit was last
cleared. This log bit will remain set until cleared by software
writing 0.
63:29
Reserved.
Register Address: 6B1H, 1713
MSR_RING_PERF_LIMIT_REASONS
MSR_RING_PERF_LIMIT_REASONS
Package
Indicator of Frequency Clipping in the Ring Interconnect. (Frequency refers to ring interconnect in the uncore.)
0
PROCHOT (R/O)
PROCHOT Status. When set, frequency is reduced due to
assertion of external PROCHOT.
1
THERMAL (R/O)
Thermal Status. When set, frequency is reduced due to a thermal
event.
4:2
Reserved.
5
RATL (R/O)
Running Average Thermal Limit Status. When set, frequency is
reduced due to running average thermal limit.
6
VR_THERMALERT (R/O)
VR Therm Alert Status. When set, frequency is reduced due to a
thermal alert from a processor Voltage Regulator.
7
VR_TDC (R/O)
VR Thermal Design Current Status. When set, frequency is
reduced due to VR TDC limit.
8
OTHER (R/O)
Other Status. When set, frequency is reduced due to electrical or
other constraints.
2-428 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
9
Reserved.
10
PBM_PL1 (R/O)
Package/Platform-Level Power Limiting PL1 Status. When set,
frequency is reduced due to package/platform-level power
limiting PL1.
11
PBM_PL2 (R/O)
Package/Platform-Level PL2 Power Limiting Status. When set,
frequency is reduced due to package/platform-level power
limiting PL2/PL3.
15:12
Reserved.
16
PROCHOT_LOG (R/W)
PROCHOT Log. When set, indicates that the PROCHOT Status bit
has asserted since the log bit was last cleared. This log bit will
remain set until cleared by software writing 0.
17
THERMAL_LOG (R/W)
Thermal Log. When set, indicates that the Thermal Status bit has
asserted since the log bit was last cleared. This log bit will remain
set until cleared by software writing 0.
20:18
Reserved.
21
RATL_LOG (R/W)
Running Average Thermal Limit Log. When set, indicates that the
RATL Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
22
VR_THERMALERT_LOG (R/W)
VR Therm Alert Log. When set, indicates that the VR Therm Alert
Status bit has asserted since the log bit was last cleared. This log
bit will remain set until cleared by software writing 0.
23
VR_TDC_LOG (R/W)
VR Thermal Design Current Log. When set, indicates that the VR
Therm Alert Status bit has asserted since the log bit was last
cleared. This log bit will remain set until cleared by software
writing 0.
24
OTHER_LOG (R/W)
Other Log. When set, indicates that the OTHER Status bit has
asserted since the log bit was last cleared. This log bit will remain
set until cleared by software writing 0.
25
Reserved.
26
PBM_PL1_LOG (R/W)
Package/Platform-Level PL1 Power Limiting Log. When set,
indicates that the Package/Platform Level PL1 Power Limiting
Status bit has asserted since the log bit was last cleared. This log
bit will remain set until cleared by software writing 0.
Vol. 4
2-429
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
27
PBM_PL2_LOG (R/W)
Package/Platform-Level PL2 Power Limiting Log. When set,
indicates that the Package/Platform Level PL2 Power Limiting
Status bit has asserted since the log bit was last cleared. This log
bit will remain set until cleared by software writing 0.
63:28
Reserved.
Register Address: 9FBH, 2555
IA32_TME_CLEAR_SAVED_KEY
IA32_TME_CLEAR_SAVED_KEY (R/W)
Package
See Table 2-2.
Register Address: 9FFH, 2559
MSR_CORE_MKTME_ACTIVATE
MSR_CORE_MKTME_ACTIVATE (R/O)
Core
MSR to read TME_ACTIVATE[MK_TME_KEYID_BITS].
31:0
Reserved.
35:32
READ_MK_TME_KEYID_BITS
This value will be returned on a RDMSR, but must be zero on a
WRMSR.
63:36
Reserved.
The MSRs listed in Table 2-54 are unique to the Intel Core Ultra 7 processor P-core. These MSRs are not supported
on the processor E-core.
Table 2-54. MSRs Supported by the Intel® Core™ Ultra 7 Processor P-core
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 30CH, 780
IA32_FIXED_CTR3
Fixed-Function Performance Counter 3 (R/W)
Thread
47:0
FIXED_COUNTER
Top-down Microarchitecture Analysis unhalted number of available
slots counter.
63:48
Reserved.
Register Address: 329H, 809
MSR_PERF_METRICS
Performance Metrics (R/W)
Thread
This register provides built-in support for Top-down Micro-architecture Analysis (TMA) metrics. It exposes the four
TMA Level 1 metrics where the lower 32 bits are divided into four 8 bit fields, each of which is an integer percentage
of the total TOPDOWN.SLOTS (as reported by fixed counter 3).
7:0
RETIRING
Percent of utilized by uops that eventually retire (commit).
15:8
BAD_SPECULATION
Percent of Wasted due to incorrect speculation, covering Utilized by
uops that do not retire, or Recovery Bubbles (unutilized slots).
2-430 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-54. MSRs Supported by the Intel® Core™ Ultra 7 Processor P-core (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
23:16
FRONTEND_BOUND
Percent of Unutilized slots where Front-end did not deliver a uop
while Back-end is ready.
31:24
BACKEND_BOUND
Percent of Unutilized slots where a uop was not delivered to Back-
end due to lack of Back-end resources.
39:32
MULTI_UOPS
Frontend bound.
47:40
BRANCH_MISPREDICTS
Frontend bound.
55:48
FRONTEND_LATENCY
Frontend bound.
63:56
MEMORY_BOUND
Frontend bound.
Register Address: 540H, 1344
MSR_THREAD_UARCH_CTL
Thread Microarchitectural Control (R/W)
Thread
See Table 2-47.
Register Address: 541H, 1345
MSR_CORE_UARCH_CTL
Core Microarchitecture Control MSR (R/W)
Core
See Table 2-44.
The MSRs listed in Table 2-48 are unique to the Intel Core Ultra 7 processor E-core. These MSRs are not supported
on the processor P-core.
Table 2-55. MSRs Supported by the Intel® Core™ Ultra 7 Processor E-core
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 4F0H, 1264
MSR_SAF_CTRL
SAF Control (W/O)
Package
Extension to SAF.
0
INVALIDATE_CURRENT_STRIDE
Invalidate all chunks in current stride.
63:1
Reserved.
Register Address: D18H-D1FH, 3352-3359
IA32_L2_MASK_[8-15]
IA32_L2_MASK_[8-15] (R/W)
Module
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] ≥ 0.
Controls MLC (L2) Intel RDT allocation. For more details on CAT/RDT, see Chapter 18, “Debug, Branch Profile, TSC, and
Intel® Resource Director Technology (Intel® RDT) Features.”
15:0
WAY_MASK
Capacity Bit Mask. Available ways vectors for class of service of
IA core. '1 in bit indicates allocation to the way is allowed. '0
indicates allocation to the way is not allowed.
Vol. 4
2-431
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-55. MSRs Supported by the Intel® Core™ Ultra 7 Processor E-core (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
31:16
Reserved.
Register Address: 1309H-130BH, 4873
MSR_RELOAD_FIXED_CTRx
-4875
Reload value for IA32_FIXED_CTRx (R/W)
Thread
47:0
Value loaded into IA32_FIXED_CTRx when a PEBS record is
generated while PEBS_EN_FIXEDx = 1 and PEBS_OUTPUT =
01B in IA32_PEBS_ENABLE, and FIXED_CTRx is overflowed.
63:48
Reserved.
Register Address: 14C1H-14C8H, 5313 -5320
MSR_RELOAD_PMCx
Reload value for IA32_PMCx (R/W)
Thread
47:0
Value loaded into IA32_PMCx when a PEBS record is generated
while PEBS_EN_PMCx = 1 and PEBS_OUTPUT = 01B in
IA32_PEBS_ENABLE, and PMCx is overflowed.
63:48
Reserved.
Register Address: 1A8EH, 6798
MSR_STLB_FILL_TRANSLATION
STLB Fill Translation (W/O)
Core
STLB QoS MSR to fill translations into STLB.
3:0
CLOS
Class of service to use for the fill.
9:4
Reserved.
10
X
Set to 1 when LA is to an executable page.
11
RW
Set to 1 when LA is to a writeable page.
63:12
LA
Logical address to use for fill.
2.18
MSRS IN THE INTEL® XEON PHI™ PROCESSOR 3200/5200/7200 SERIES
AND THE INTEL® XEON PHI™ PROCESSOR 7215/7285/7295 SERIES
The Intel® Xeon Phi™ processor 3200, 5200, 7200 series, with a CPUID Signature DisplayFamily_DisplayModel
value of 06_57H, supports the MSR interfaces listed in Table 2-56. These processors are based on the Knights
Landing microarchitecture. The Intel® Xeon Phi™ processor 7215, 7285, 7295 series, with a CPUID Signature
DisplayFamily_DisplayModel value of 06_85H, supports the MSR interfaces listed in Table 2-56 and Table 2-57.
These processors are based on the Knights Mill microarchitecture. Some MSRs are shared between a pair of
processor cores, and the scope is marked as module.
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 0H, 0
IA32_P5_MC_ADDR
2-432 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
See Section 2.23, “MSRs in Pentium Processors.”
Module
Register Address: 1H, 1
IA32_P5_MC_TYPE
See Section 2.23, “MSRs in Pentium Processors.”
Module
Register Address: 6H, 6
IA32_MONITOR_FILTER_SIZE
See Section 9.10.5, “Monitor/Mwait Address Range Determination.” See Table 2-2.
Thread
Register Address: 10H, 16
IA32_TIME_STAMP_COUNTER
See Section 18.17, “Time-Stamp Counter,” and Table 2-2.
Thread
Register Address: 17H, 23
IA32_PLATFORM_ID
Platform ID (R)
Package
See Table 2-2.
Register Address: 1BH, 27
IA32_APIC_BASE
See Section 11.4.4, “Local APIC Status and Location,” and Table 2-2.
Thread
Register Address: 34H, 52
MSR_SMI_COUNT
SMI Counter (R/O)
Thread
31:0
SMI Count (R/O)
63:32
Reserved.
Register Address: 3AH, 58
IA32_FEATURE_CONTROL
Control Features in Intel 64Processor (R/W)
Thread
See Table 2-2.
0
Lock. (R/WL)
1
Reserved.
2
Enable VMX outside SMX operation. (R/WL)
Register Address: 3BH, 59
IA32_TSC_ADJUST
Per-Logical-Processor TSC ADJUST (R/W)
Thread
See Table 2-2.
Register Address: 4EH, 78
IA32_PPIN_CTL (MSR_PPIN_CTL)
Protected Processor Inventory Number Enable Control (R/W)
Package
0
LockOut (R/WO)
See Table 2-2.
1
Enable_PPIN (R/W)
See Table 2-2.
63:2
Reserved
Register Address: 4FH, 79
IA32_PPIN (MSR_PPIN)
Protected Processor Inventory Number (R/O)
Package
63:0
Protected Processor Inventory Number (R/O)
See Table 2-2.
Register Address: 79H, 121
IA32_BIOS_UPDT_TRIG
Vol. 4
2-433
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
BIOS Update Trigger Register (W)
Core
See Table 2-2.
Register Address: 8BH, 139
IA32_BIOS_SIGN_ID
BIOS Update Signature ID (R/W)
Thread
See Table 2-2.
Register Address: C1H, 193
IA32_PMC0
Performance Counter Register
Thread
See Table 2-2.
Register Address: C2H, 194
IA32_PMC1
Performance Counter Register
Thread
See Table 2-2.
Register Address: CEH, 206
MSR_PLATFORM_INFO
Platform Information
Package
Contains power management and other model specific features enumeration. See http://biosbits.org.
7:0
Reserved.
15:8
Maximum Non-Turbo Ratio (R/O)
Package
This is the ratio of the frequency that invariant TSC runs at. Frequency
= ratio * 100 MHz.
27:16
Reserved.
28
Programmable Ratio Limit for Turbo Mode (R/O)
Package
When set to 1, indicates that Programmable Ratio Limit for Turbo mode
is enabled. When set to 0, indicates Programmable Ratio Limit for Turbo
mode is disabled.
29
Programmable TDP Limit for Turbo Mode (R/O)
Package
When set to 1, indicates that TDP Limit for Turbo mode is
programmable. When set to 0, indicates TDP Limit for Turbo mode is
not programmable.
39:30
Reserved.
47:40
Maximum Efficiency Ratio (R/O)
Package
This is the minimum ratio (maximum efficiency) that the processor can
operate, in units of 100MHz.
63:48
Reserved.
Register Address: E2H, 226
MSR_PKG_CST_CONFIG_CONTROL
C-State Configuration Control (R/W)
Package
2-434 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
2:0
Package C-State Limit (R/W)
Specifies the lowest C-state for the package. This feature does not limit
the processor core C-state. The power-on default value from bit[2:0] of
this register reports the deepest package C-state the processor is
capable to support when manufactured. It is recommended that BIOS
always read the power-on default value reported from this bit field to
determine the supported deepest C-state on the processor and leave it
as default without changing it.
000b - C0/C1 (No package C-state support)
001b - C2
010b - C6 (non retention)*
011b - C6 (Retention)*
100b - Reserved
101b - Reserved
110b - Reserved
111b - No package C-state limit. All C-States supported by the
processor are available.
Note: C6 retention mode provides more power saving than C6 non-
retention mode. Limiting the package to C6 non retention mode does
prevent the MSR_PKG_C6_RESIDENCY counter (MSR 3F9h) from being
incremented.
9:3
Reserved.
10
I/O MWAIT Redirection Enable (R/W)
When set, will map IO_read instructions sent to IO registers at
MSR_PMG_IO_CAPTURE_BASE[15:0] to MWAIT instructions.
14:11
Reserved.
15
CFG Lock (R/O)
When set, locks bits [15:0] of this register for further writes until the
next reset occurs.
25
Reserved.
26
C1 State Auto Demotion Enable (R/W)
When set, the processor will conditionally demote C3/C6/C7 requests
to C1 based on uncore auto-demote information.
27
Reserved.
28
C1 State Auto Undemotion Enable (R/W)
When set, enables Undemotion from Demoted C1.
29
PKG C-State Auto Demotion Enable (R/W)
When set, enables Package C state demotion.
63:30
Reserved.
Register Address: E4H, 228
MSR_PMG_IO_CAPTURE_BASE
Power Management IO Capture Base (R/W)
Tile
Vol. 4
2-435
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
15:0
LVL_2 Base Address (R/W)
Microcode will compare IO-read zone to this base address to determine
if an MWAIT(C2/3/4) needs to be issued instead of the IO-read. Should
be programmed to the chipset Plevel_2 IO address.
22:16
C-State Range (R/W)
The IO-port block size in which IO-redirection will be executed (0-127).
Should be programmed based on the number of LVLx registers existing
in the chipset.
63:23
Reserved.
Register Address: E7H, 231
IA32_MPERF
Maximum Performance Frequency Clock Count (R/W)
Thread
See Table 2-2.
Register Address: E8H, 232
IA32_APERF
Actual Performance Frequency Clock Count (R/W)
Thread
See Table 2-2.
Register Address: FEH, 254
IA32_MTRRCAP
Memory Type Range Register (R)
Core
See Table 2-2.
Register Address: 13CH, 316
MSR_FEATURE_CONFIG
AES Configuration (RW-L)
Core
Privileged post-BIOS agent must provide a #GP handler to handle unsuccessful read of this MSR.
1:0
AES Configuration (RW-L)
Upon a successful read of this MSR, the configuration of AES
instruction set availability is as follows:
11b: AES instructions are not available until next RESET.
Otherwise, AES instructions are available.
Note, the AES instruction set is not available if read is unsuccessful. If
the configuration is not 01b, AES instructions can be mis-configured if a
privileged agent unintentionally writes 11b.
63:2
Reserved.
Register Address: 140H, 320
MISC_FEATURE_ENABLES
MISC_FEATURE_ENABLES
Thread
0
Reserved.
1
User Mode MONITOR and MWAIT (R/W)
If set to 1, the MONITOR and MWAIT instructions do not cause invalid-
opcode exceptions when executed with CPL > 0 or in virtual-8086
mode. If MWAIT is executed when CPL > 0 or in virtual-8086 mode, and
if EAX indicates a C-state other than C0 or C1, the instruction operates
as if EAX indicated the C-state C1.
63:2
Reserved.
Register Address: 174H, 372
IA32_SYSENTER_CS
See Table 2-2.
Thread
2-436 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 175H, 373
IA32_SYSENTER_ESP
See Table 2-2.
Thread
Register Address: 176H, 374
IA32_SYSENTER_EIP
See Table 2-2.
Thread
Register Address: 179H, 377
IA32_MCG_CAP
See Table 2-2.
Thread
Register Address: 17AH, 378
IA32_MCG_STATUS
See Table 2-2.
Thread
Register Address: 17DH, 381
MSR_SMM_MCA_CAP
Enhanced SMM Capabilities (SMM-RO)
Thread
Reports SMM capability Enhancement. Accessible only while in SMM.
31:0
Bank Support (SMM-RO)
One bit per MCA bank. If the bit is set, that bank supports Enhanced
MCA (Default all 0; does not support EMCA).
55:32
Reserved.
56
Targeted SMI (SMM-RO)
Set if targeted SMI is supported.
57
SMM_CPU_SVRSTR (SMM-RO)
Set if SMM SRAM save/restore feature is supported.
58
SMM_CODE_ACCESS_CHK (SMM-RO)
Set if SMM code access check feature is supported.
59
Long_Flow_Indication (SMM-RO)
If set to 1, indicates that the SMM long flow indicator is supported and a
host-space interface available to SMM handler.
63:60
Reserved.
Register Address: 186H, 390
IA32_PERFEVTSEL0
Performance Monitoring Event Select Register (R/W)
Thread
See Table 2-2.
7:0
Event Select.
15:8
UMask.
16
USR.
17
OS.
18
Edge.
19
PC.
20
INT.
21
AnyThread.
22
EN.
23
INV.
Vol. 4
2-437
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
31:24
CMASK.
63:32
Reserved.
Register Address: 187H, 391
IA32_PERFEVTSEL1
See Table 2-2.
Thread
Register Address: 198H, 408
IA32_PERF_STATUS
See Table 2-2.
Package
Register Address: 199H, 409
IA32_PERF_CTL
See Table 2-2.
Thread
Register Address: 19AH, 410
IA32_CLOCK_MODULATION
Clock Modulation (R/W)
Thread
See Table 2-2.
Register Address: 19BH, 411
IA32_THERM_INTERRUPT
Thermal Interrupt Control (R/W)
Module
See Table 2-2.
Register Address: 19CH, 412
IA32_THERM_STATUS
Thermal Monitor Status (R/W)
Module
See Table 2-2.
0
Thermal Status (R/O)
1
Thermal Status Log (R/WC0)
2
PROTCHOT # or FORCEPR# Status (R/O)
3
PROTCHOT # or FORCEPR# Log (R/WC0)
4
Critical Temperature Status (R/O)
5
Critical Temperature Status Log (R/WC0)
6
Thermal Threshold #1 Status (R/O)
7
Thermal Threshold #1 Log (R/WC0)
8
Thermal Threshold #2 Status (R/O)
9
Thermal Threshold #2 Log (R/WC0)
10
Power Limitation Status (R/O)
11
Power Limitation Log (RWC0)
15:12
Reserved.
22:16
Digital Readout (R/O)
26:23
Reserved.
30:27
Resolution in Degrees Celsius (R/O)
31
Reading Valid (R/O)
63:32
Reserved.
Register Address: 1A0H, 416
IA32_MISC_ENABLE
2-438 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Enable Misc. Processor Features (R/W)
Thread
Allows a variety of processor functions to be enabled and disabled.
0
Fast-Strings Enable
2:1
Reserved.
3
Automatic Thermal Control Circuit Enable (R/W)
6:4
Reserved.
7
Performance Monitoring Available (R)
10:8
Reserved.
11
Branch Trace Storage Unavailable (R/O)
12
Processor Event Based Sampling Unavailable (R/O)
15:13
Reserved.
16
Enhanced Intel SpeedStep Technology Enable (R/W)
18
ENABLE MONITOR FSM (R/W)
21:19
Reserved.
22
Limit CPUID Maxval (R/W)
23
xTPR Message Disable (R/W)
33:24
Reserved.
34
XD Bit Disable (R/W)
See Table 2-3.
37:35
Reserved.
38
Turbo Mode Disable (R/W)
63:39
Reserved.
Register Address: 1A2H, 418
MSR_TEMPERATURE_TARGET
Temperature Target
Package
15:0
Reserved.
23:16
Temperature Target (R)
29:24
Target Offset (R/W)
63:30
Reserved.
Register Address: 1A4H, 420
MSR_MISC_FEATURE_CONTROL
Miscellaneous Feature Control (R/W)
0
DCU Hardware Prefetcher Disable (R/W)
Core
If 1, disables the L1 data cache prefetcher.
1
L2 Hardware Prefetcher Disable (R/W)
Core
If 1, disables the L2 hardware prefetcher.
63:2
Reserved.
Register Address: 1A6H, 422
MSR_OFFCORE_RSP_0
Offcore Response Event Select Register (R/W)
Shared
Vol. 4
2-439
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 1A7H, 423
MSR_OFFCORE_RSP_1
Offcore Response Event Select Register (R/W)
Shared
Register Address: 1ADH, 429
MSR_TURBO_RATIO_LIMIT
Maximum Ratio Limit of Turbo Mode for Groups of Cores (R/W)
Package
0
Reserved.
7:1
Maximum Number of Cores in Group 0
Package
Number active processor cores which operates under the maximum
ratio limit for group 0.
15:8
Maximum Ratio Limit for Group 0
Package
Maximum turbo ratio limit when the number of active cores are not
more than the group 0 maximum core count.
20:16
Number of Incremental Cores Added to Group 1
Package
Group 1, which includes the specified number of additional cores plus
the cores in group 0, operates under the group 1 turbo max ratio limit =
“group 0 Max ratio limit” - “group ratio delta for group 1”.
23:21
Group Ratio Delta for Group 1
Package
An unsigned integer specifying the ratio decrement relative to the Max
ratio limit to Group 0.
28:24
Number of Incremental Cores Added to Group 2
Package
Group 2, which includes the specified number of additional cores plus all
the cores in group 1, operates under the group 2 turbo max ratio limit =
“group 1 Max ratio limit” - “group ratio delta for group 2”.
31:29
Group Ratio Delta for Group 2
Package
An unsigned integer specifying the ratio decrement relative to the Max
ratio limit for Group 1.
36:32
Number of Incremental Cores Added to Group 3
Package
Group 3, which includes the specified number of additional cores plus all
the cores in group 2, operates under the group 3 turbo max ratio limit =
“group 2 Max ratio limit” - “group ratio delta for group 3”.
39:37
Group Ratio Delta for Group 3
Package
An unsigned integer specifying the ratio decrement relative to the Max
ratio limit for Group 2.
44:40
Number of Incremental Cores Added to Group 4
Package
Group 4, which includes the specified number of additional cores plus all
the cores in group 3, operates under the group 4 turbo max ratio limit =
“group 3 Max ratio limit” - “group ratio delta for group 4”.
47:45
Group Ratio Delta for Group 4
Package
An unsigned integer specifying the ratio decrement relative to the Max
ratio limit for Group 3.
52:48
Number of Incremental Cores Added to Group 5
Package
Group 5, which includes the specified number of additional cores plus all
the cores in group 4, operates under the group 5 turbo max ratio limit =
“group 4 Max ratio limit” - “group ratio delta for group 5”.
2-440 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
55:53
Group Ratio Delta for Group 5
Package
An unsigned integer specifying the ratio decrement relative to the Max
ratio limit for Group 4.
60:56
Number of Incremental Cores Added to Group 6
Package
Group 6, which includes the specified number of additional cores plus all
the cores in group 5, operates under the group 6 turbo max ratio limit =
“group 5 Max ratio limit” - “group ratio delta for group 6”.
63:61
Group Ratio Delta for Group 6
Package
An unsigned integer specifying the ratio decrement relative to the Max
ratio limit for Group 5.
Register Address: 1B0H, 432
IA32_ENERGY_PERF_BIAS
See Table 2-2.
Thread
Register Address: 1B1H, 433
IA32_PACKAGE_THERM_STATUS
See Table 2-2.
Package
Register Address: 1B2H, 434
IA32_PACKAGE_THERM_INTERRUPT
See Table 2-2.
Package
Register Address: 1C8H, 456
MSR_LBR_SELECT
Last Branch Record Filtering Select Register (R/W)
Thread
See Section 18.9.2, “Filtering of Last Branch Records.”
0
CPL_EQ_0
1
CPL_NEQ_0
2
JCC
3
NEAR_REL_CALL
4
NEAR_IND_CALL
5
NEAR_RET
6
NEAR_IND_JMP
7
NEAR_REL_JMP
8
FAR_BRANCH
63:9
Reserved.
Register Address: 1C9H, 457
MSR_LASTBRANCH_TOS
Last Branch Record Stack TOS (R/W)
Thread
Contains an index (bits 0-2) that points to the MSR containing the most recent branch record.
See MSR_LASTBRANCH_0_FROM_IP.
Register Address: 1D9H, 473
IA32_DEBUGCTL
Debug Control (R/W)
Thread
0
LBR
Setting this bit to 1 enables the processor to record a running trace of
the most recent branches taken by the processor in the LBR stack.
Vol. 4
2-441
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
1
BTF
Setting this bit to 1 enables the processor to treat EFLAGS.TF as single-
step on branches instead of single-step on instructions.
5:2
Reserved.
6
TR
Setting this bit to 1 enables branch trace messages to be sent.
7
BTS
Setting this bit enables branch trace messages (BTMs) to be logged in a
BTS buffer.
8
BTINT
When clear, BTMs are logged in a BTS buffer in circular fashion. When
this bit is set, an interrupt is generated by the BTS facility when the
BTS buffer is full.
9
BTS_OFF_OS
When set, BTS or BTM is skipped if CPL = 0.
10
BTS_OFF_USR
When set, BTS or BTM is skipped if CPL > 0.
11
FREEZE_LBRS_ON_PMI
When set, the LBR stack is frozen on a PMI request.
12
FREEZE_PERFMON_ON_PMI
When set, each ENABLE bit of the global counter control MSR are frozen
(address 3BFH) on a PMI request.
13
Reserved.
14
FREEZE_WHILE_SMM
When set, freezes perfmon and trace messages while in SMM.
31:15
Reserved.
Register Address: 1DDH, 477
MSR_LER_FROM_LIP
Last Exception Record from Linear IP (R)
Thread
Register Address: 1DEH, 478
MSR_LER_TO_LIP
Last Exception Record to Linear IP (R)
Thread
Register Address: 1F2H, 498
IA32_SMRR_PHYSBASE
See Table 2-2.
Core
Register Address: 1F3H, 499
IA32_SMRR_PHYSMASK
See Table 2-2.
Core
Register Address: 200H, 512
IA32_MTRR_PHYSBASE0
See Table 2-2.
Core
Register Address: 201H, 513
IA32_MTRR_PHYSMASK0
See Table 2-2.
Core
Register Address: 202H, 514
IA32_MTRR_PHYSBASE1
2-442 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
See Table 2-2.
Core
Register Address: 203H, 515
IA32_MTRR_PHYSMASK1
See Table 2-2.
Core
Register Address: 204H, 516
IA32_MTRR_PHYSBASE2
See Table 2-2.
Core
Register Address: 205H, 517
IA32_MTRR_PHYSMASK2
See Table 2-2.
Core
Register Address: 206H, 518
IA32_MTRR_PHYSBASE3
See Table 2-2.
Core
Register Address: 207H, 519
IA32_MTRR_PHYSMASK3
See Table 2-2.
Core
Register Address: 208H, 520
IA32_MTRR_PHYSBASE4
See Table 2-2.
Core
Register Address: 209H, 521
IA32_MTRR_PHYSMASK4
See Table 2-2.
Core
Register Address: 20AH, 522
IA32_MTRR_PHYSBASE5
See Table 2-2.
Core
Register Address: 20BH, 523
IA32_MTRR_PHYSMASK5
See Table 2-2.
Core
Register Address: 20CH, 524
IA32_MTRR_PHYSBASE6
See Table 2-2.
Core
Register Address: 20DH, 525
IA32_MTRR_PHYSMASK6
See Table 2-2.
Core
Register Address: 20EH, 526
IA32_MTRR_PHYSBASE7
See Table 2-2.
Core
Register Address: 20FH, 527
IA32_MTRR_PHYSMASK7
See Table 2-2.
Core
Register Address: 250H, 592
IA32_MTRR_FIX64K_00000
See Table 2-2.
Core
Register Address: 258H, 600
IA32_MTRR_FIX16K_80000
See Table 2-2.
Core
Register Address: 259H, 601
IA32_MTRR_FIX16K_A0000
See Table 2-2.
Core
Register Address: 268H, 616
IA32_MTRR_FIX4K_C0000
See Table 2-2.
Core
Register Address: 269H, 617
IA32_MTRR_FIX4K_C8000
See Table 2-2.
Core
Vol. 4
2-443
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 26AH, 618
IA32_MTRR_FIX4K_D0000
See Table 2-2.
Core
Register Address: 26BH, 619
IA32_MTRR_FIX4K_D8000
See Table 2-2.
Core
Register Address: 26CH, 620
IA32_MTRR_FIX4K_E0000
See Table 2-2.
Core
Register Address: 26DH, 621
IA32_MTRR_FIX4K_E8000
See Table 2-2.
Core
Register Address: 26EH, 622
IA32_MTRR_FIX4K_F0000
See Table 2-2.
Core
Register Address: 26FH, 623
IA32_MTRR_FIX4K_F8000
See Table 2-2.
Core
Register Address: 277H, 631
IA32_PAT
See Table 2-2.
Core
Register Address: 2FFH, 767
IA32_MTRR_DEF_TYPE
Default Memory Types (R/W)
Core
See Table 2-2.
Register Address: 309H, 777
IA32_FIXED_CTR0
Fixed-Function Performance Counter Register 0 (R/W)
Thread
See Table 2-2.
Register Address: 30AH, 778
IA32_FIXED_CTR1
Fixed-Function Performance Counter Register 1 (R/W)
Thread
See Table 2-2.
Register Address: 30BH, 779
IA32_FIXED_CTR2
Fixed-Function Performance Counter Register 2 (R/W)
Thread
See Table 2-2.
Register Address: 345H, 837
IA32_PERF_CAPABILITIES
See Table 2-2. See Section 18.4.1, “IA32_DEBUGCTL MSR.”
Package
Register Address: 38DH, 909
IA32_FIXED_CTR_CTRL
Fixed-Function-Counter Control Register (R/W)
Thread
See Table 2-2.
Register Address: 38EH, 910
IA32_PERF_GLOBAL_STATUS
See Table 2-2.
Thread
Register Address: 38FH, 911
IA32_PERF_GLOBAL_CTRL
See Table 2-2.
Thread
Register Address: 390H, 912
IA32_PERF_GLOBAL_OVF_CTRL
See Table 2-2.
Thread
2-444 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 3F1H, 1009
IA32_PEBS_ENABLE (MSR_PEBS_ENABLE)
See Table 2-2.
Thread
Register Address: 3F8H, 1016
MSR_PKG_C3_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state
Package
parameters or ACPI C-states.
63:0
Package C3 Residency Counter (R/O)
Register Address: 3F9H, 1017
MSR_PKG_C6_RESIDENCY
63:0
Package C6 Residency Counter (R/O)
Package
Register Address: 3FAH, 1018
MSR_PKG_C7_RESIDENCY
63:0
Package C7 Residency Counter (R/O)
Package
Register Address: 3FCH, 1020
MSR_MC0_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state
Module
parameters or ACPI C-states.
63:0
Module C0 Residency Counter (R/O)
Register Address: 3FDH, 1021
MSR_MC6_RESIDENCY
63:0
Module C6 Residency Counter (R/O)
Module
Register Address: 3FFH, 1023
MSR_CORE_C6_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state
Core
parameters or ACPI C-states.
63:0
CORE C6 Residency Counter (R/O)
Register Address: 400H, 1024
IA32_MC0_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
Core
Register Address: 401H, 1025
IA32_MC0_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”
Core
Register Address: 402H, 1026
IA32_MC0_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
Core
Register Address: 404H, 1028
IA32_MC1_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
Core
Register Address: 405H, 1029
IA32_MC1_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”
Core
Register Address: 408H, 1032
IA32_MC2_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
Core
Register Address: 409H, 1033
IA32_MC2_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”
Core
Register Address: 40AH, 1034
IA32_MC2_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
Core
Register Address: 40CH, 1036
IA32_MC3_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
Core
Vol. 4
2-445
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 40DH, 1037
IA32_MC3_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”
Core
Register Address: 40EH, 1038
IA32_MC3_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
Core
Register Address: 410H, 1040
IA32_MC4_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
Core
Register Address: 411H, 1041
IA32_MC4_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”
Core
Register Address: 412H, 1042
IA32_MC4_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
Core
The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the
MSR_MC4_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-protection
exception.
Register Address: 414H, 1044
IA32_MC5_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
Package
Register Address: 415H, 1045
IA32_MC5_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”
Package
Register Address: 416H, 1046
IA32_MC5_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
Package
Register Address: 4C1H, 1217
IA32_A_PMC0
See Table 2-2.
Thread
Register Address: 4C2H, 1218
IA32_A_PMC1
See Table 2-2.
Thread
Register Address: 600H, 1536
IA32_DS_AREA
DS Save Area (R/W)
Thread
See Table 2-2.
Register Address: 606H, 1542
MSR_RAPL_POWER_UNIT
Unit Multipliers Used in RAPL Interfaces (R/O)
Package
3:0
Power Units
Package
See Section 15.10.1, “RAPL Interfaces.”
7:4
Reserved.
Package
12:8
Energy Status Units
Package
Energy related information (in Joules) is based on the multiplier,
1/2^ESU; where ESU is an unsigned integer represented by bits 12:8.
Default value is 0EH (or 61 micro-joules).
15:13
Reserved.
Package
19:16
Time Units
Package
See Section 15.10.1, “RAPL Interfaces.”
2-446 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
63:20
Reserved.
Register Address: 60DH, 1549
MSR_PKG_C2_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state
Package
parameters or ACPI C-states.
63:0
Package C2 Residency Counter (R/O)
Register Address: 610H, 1552
MSR_PKG_POWER_LIMIT
PKG RAPL Power Limit Control (R/W)
Package
See Section 15.10.3, “Package RAPL Domain.”
Register Address: 611H, 1553
MSR_PKG_ENERGY_STATUS
PKG Energy Status (R/O)
Package
See Section 15.10.3, “Package RAPL Domain.”
Register Address: 613H, 1555
MSR_PKG_PERF_STATUS
PKG Perf Status (R/O)
Package
See Section 15.10.3, “Package RAPL Domain.”
Register Address: 614H, 1556
MSR_PKG_POWER_INFO
PKG RAPL Parameters (R/W)
Package
See Section 15.10.3, “Package RAPL Domain.”
Register Address: 618H, 1560
MSR_DRAM_POWER_LIMIT
DRAM RAPL Power Limit Control (R/W)
Package
See Section 15.10.5, “DRAM RAPL Domain.”
Register Address: 619H, 1561
MSR_DRAM_ENERGY_STATUS
DRAM Energy Status (R/O)
Package
See Section 15.10.5, “DRAM RAPL Domain.”
Register Address: 61BH, 1563
MSR_DRAM_PERF_STATUS
DRAM Performance Throttling Status (R/O)
Package
See Section 15.10.5, “DRAM RAPL Domain.”
Register Address: 61CH, 1564
MSR_DRAM_POWER_INFO
DRAM RAPL Parameters (R/W)
Package
See Section 15.10.5, “DRAM RAPL Domain.”
Register Address: 638H, 1592
MSR_PP0_POWER_LIMIT
PP0 RAPL Power Limit Control (R/W)
Package
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
Register Address: 639H, 1593
MSR_PP0_ENERGY_STATUS
PP0 Energy Status (R/O)
Package
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
Register Address: 648H, 1608
MSR_CONFIG_TDP_NOMINAL
Base TDP Ratio (R/O)
Package
See Table 2-25.
Vol. 4
2-447
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 649H, 1609
MSR_CONFIG_TDP_LEVEL1
ConfigTDP Level 1 ratio and power level (R/O)
Package
See Table 2-25.
Register Address: 64AH, 1610
MSR_CONFIG_TDP_LEVEL2
ConfigTDP Level 2 ratio and power level (R/O)
Package
See Table 2-25.
Register Address: 64BH, 1611
MSR_CONFIG_TDP_CONTROL
ConfigTDP Control (R/W)
Package
See Table 2-25.
Register Address: 64CH, 1612
MSR_TURBO_ACTIVATION_RATIO
ConfigTDP Control (R/W)
Package
See Table 2-25.
Register Address: 690H, 1680
MSR_CORE_PERF_LIMIT_REASONS
Indicator of Frequency Clipping in Processor Cores (R/W)
Package
(Frequency refers to processor core frequency.)
0
PROCHOT Status (R0)
1
Thermal Status (R0)
5:2
Reserved.
6
VR Therm Alert Status (R0)
7
Reserved.
8
Electrical Design Point Status (R0)
63:9
Reserved.
Register Address: 6E0H, 1760
IA32_TSC_DEADLINE
TSC Target of Local APIC’s TSC Deadline Mode (R/W)
Core
See Table 2-2.
Register Address: 802H, 2050
IA32_X2APIC_APICID
x2APIC ID Register (R/O)
Thread
Register Address: 803H, 2051
IA32_X2APIC_VERSION
x2APIC Version Register (R/O)
Thread
Register Address: 808H, 2056
IA32_X2APIC_TPR
x2APIC Task Priority Register (R/W)
Thread
Register Address: 80AH, 2058
IA32_X2APIC_PPR
x2APIC Processor Priority Register (R/O)
Thread
Register Address: 80BH, 2059
IA32_X2APIC_EOI
x2APIC EOI Register (W/O)
Thread
Register Address: 80DH, 2061
IA32_X2APIC_LDR
x2APIC Logical Destination Register (R/O)
Thread
2-448 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 80FH, 2063
IA32_X2APIC_SIVR
x2APIC Spurious Interrupt Vector Register (R/W)
Thread
Register Address: 810H, 2064
IA32_X2APIC_ISR0
x2APIC In-Service Register Bits [31:0] (R/O)
Thread
Register Address: 811H, 2065
IA32_X2APIC_ISR1
x2APIC In-Service Register Bits [63:32] (R/O)
Thread
Register Address: 812H, 2066
IA32_X2APIC_ISR2
x2APIC In-Service Register Bits [95:64] (R/O)
Thread
Register Address: 813H, 2067
IA32_X2APIC_ISR3
x2APIC In-Service Register Bits [127:96] (R/O)
Thread
Register Address: 814H, 2068
IA32_X2APIC_ISR4
x2APIC In-Service Register Bits [159:128] (R/O)
Thread
Register Address: 815H, 2069
IA32_X2APIC_ISR5
x2APIC In-Service Register Bits [191:160] (R/O)
Thread
Register Address: 816H, 2070
IA32_X2APIC_ISR6
x2APIC In-Service Register Bits [223:192] (R/O)
Thread
Register Address: 817H, 2071
IA32_X2APIC_ISR7
x2APIC In-Service Register Bits [255:224] (R/O)
Thread
Register Address: 818H, 2072
IA32_X2APIC_TMR0
x2APIC Trigger Mode Register Bits [31:0] (R/O)
Thread
Register Address: 819H, 2073
IA32_X2APIC_TMR1
x2APIC Trigger Mode Register Bits [63:32] (R/O)
Thread
Register Address: 81AH, 2074
IA32_X2APIC_TMR2
x2APIC Trigger Mode Register Bits [95:64] (R/O)
Thread
Register Address: 81BH, 2075
IA32_X2APIC_TMR3
x2APIC Trigger Mode Register Bits [127:96] (R/O)
Thread
Register Address: 81CH, 2076
IA32_X2APIC_TMR4
x2APIC Trigger Mode Register Bits [159:128] (R/O)
Thread
Register Address: 81DH, 2077
IA32_X2APIC_TMR5
x2APIC Trigger Mode Register Bits [191:160] (R/O)
Thread
Register Address: 81EH, 2078
IA32_X2APIC_TMR6
x2APIC Trigger Mode Register Bits [223:192] (R/O)
Thread
Register Address: 81FH, 2079
IA32_X2APIC_TMR7
x2APIC Trigger Mode Register Bits [255:224] (R/O)
Thread
Register Address: 820H, 2080
IA32_X2APIC_IRR0
x2APIC Interrupt Request Register Bits [31:0] (R/O)
Thread
Register Address: 821H, 2081
IA32_X2APIC_IRR1
Vol. 4
2-449
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
x2APIC Interrupt Request Register Bits [63:32] (R/O)
Thread
Register Address: 822H, 2082
IA32_X2APIC_IRR2
x2APIC Interrupt Request Register Bits [95:64] (R/O)
Thread
Register Address: 823H, 2083
IA32_X2APIC_IRR3
x2APIC Interrupt Request Register Bits [127:96] (R/O)
Thread
Register Address: 824H, 2084
IA32_X2APIC_IRR4
x2APIC Interrupt Request Register Bits [159:128] (R/O)
Thread
Register Address: 825H, 2085
IA32_X2APIC_IRR5
x2APIC Interrupt Request Register Bits [191:160] (R/O)
Thread
Register Address: 826H, 2086
IA32_X2APIC_IRR6
x2APIC Interrupt Request Register Bits [223:192] (R/O)
Thread
Register Address: 827H, 2087
IA32_X2APIC_IRR7
x2APIC Interrupt Request Register Bits [255:224] (R/O)
Thread
Register Address: 828H, 2088
IA32_X2APIC_ESR
x2APIC Error Status Register (R/W)
Thread
Register Address: 82FH, 2095
IA32_X2APIC_LVT_CMCI
x2APIC LVT Corrected Machine Check Interrupt Register (R/W)
Thread
Register Address: 830H, 2096
IA32_X2APIC_ICR
x2APIC Interrupt Command Register (R/W)
Thread
Register Address: 832H, 2098
IA32_X2APIC_LVT_TIMER
x2APIC LVT Timer Interrupt Register (R/W)
Thread
Register Address: 833H, 2099
IA32_X2APIC_LVT_THERMAL
x2APIC LVT Thermal Sensor Interrupt Register (R/W)
Thread
Register Address: 834H, 2100
IA32_X2APIC_LVT_PMI
x2APIC LVT Performance Monitor Register (R/W)
Thread
Register Address: 835H, 2101
IA32_X2APIC_LVT_LINT0
x2APIC LVT LINT0 Register (R/W)
Thread
Register Address: 836H, 2102
IA32_X2APIC_LVT_LINT1
x2APIC LVT LINT1 Register (R/W)
Thread
Register Address: 837H, 2103
IA32_X2APIC_LVT_ERROR
x2APIC LVT Error Register (R/W)
Thread
Register Address: 838H, 2104
IA32_X2APIC_INIT_COUNT
x2APIC Initial Count Register (R/W)
Thread
Register Address: 839H, 2105
IA32_X2APIC_CUR_COUNT
x2APIC Current Count Register (R/O)
Thread
Register Address: 83EH, 2110
IA32_X2APIC_DIV_CONF
x2APIC Divide Configuration Register (R/W)
Thread
2-450 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 83FH, 2111
IA32_X2APIC_SELF_IPI
x2APIC Self IPI Register (W/O)
Thread
Register Address: C000_0080H
IA32_EFER
Extended Feature Enables
Thread
See Table 2-2.
Register Address: C000_0081H
IA32_STAR
System Call Target Address (R/W)
Thread
See Table 2-2.
Register Address: C000_0082H
IA32_LSTAR
IA-32e Mode System Call Target Address (R/W)
Thread
See Table 2-2.
Register Address: C000_0084H
IA32_FMASK
System Call Flag Mask (R/W)
Thread
See Table 2-2.
Register Address: C000_0100H
IA32_FS_BASE
Map of BASE Address of FS (R/W)
Thread
See Table 2-2.
Register Address: C000_0101H
IA32_GS_BASE
Map of BASE Address of GS (R/W)
Thread
See Table 2-2.
Register Address: C000_0102H
IA32_KERNEL_GS_BASE
Swap Target of BASE Address of GS (R/W)
Thread
See Table 2-2.
Register Address: C000_0103H
IA32_TSC_AUX
AUXILIARY TSC Signature (R/W)
Thread
See Table 2-2
Table 2-57 lists model-specific registers that are supported by the Intel® Xeon Phi™ processor 7215, 7285, 7295
series based on the Knights Mill microarchitecture.
Table 2-57. Additional MSRs Supported by the Intel® Xeon Phi™ Processor 7215, 7285, 7295 Series
with a CPUID Signature DisplayFamily_DisplayModel Value of 06_85H
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 9BH, 155
IA32_SMM_MONITOR_CTL
SMM Monitor Configuration (R/W)
Core
This MSR is readable only if VMX is enabled, and writeable only if VMX is enabled and in SMM mode, and is used to
configure the VMX MSEG base address. See Table 2-2.
Register Address: 480H, 1152
IA32_VMX_BASIC
Vol. 4
2-451
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-57. Additional MSRs Supported by the Intel® Xeon Phi™ Processor 7215, 7285, 7295 Series
with a CPUID Signature DisplayFamily_DisplayModel Value of 06_85H (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Reporting Register of Basic VMX Capabilities (R/O)
Core
See Table 2-2.
Register Address: 481H, 1153
IA32_VMX_PINBASED_CTLS
Capability Reporting Register of Pin-based VM-execution Controls (R/O)
Core
See Table 2-2.
Register Address: 482H, 1154
IA32_VMX_PROCBASED_CTLS
Capability Reporting Register of Primary Processor-based VM-execution Controls (R/O)
Core
Register Address: 483H, 1155
IA32_VMX_EXIT_CTLS
Capability Reporting Register of VM-exit Controls (R/O)
Core
See Table 2-2.
Register Address: 484H, 1156
IA32_VMX_ENTRY_CTLS
Capability Reporting Register of VM-entry Controls (R/O)
Core
See Table 2-2.
Register Address: 485H, 1157
IA32_VMX_MISC
Reporting Register of Miscellaneous VMX Capabilities (R/O)
Core
See Table 2-2.
Register Address: 486H, 1158
IA32_VMX_CR0_FIXED0
Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)
Core
See Table 2-2.
Register Address: 487H, 1159
IA32_VMX_CR0_FIXED1
Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)
Core
See Table 2-2.
Register Address: 488H, 1160
IA32_VMX_CR4_FIXED0
Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)
Core
See Table 2-2.
Register Address: 489H, 1161
IA32_VMX_CR4_FIXED1
Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)
Core
See Table 2-2.
Register Address: 48AH, 1162
IA32_VMX_VMCS_ENUM
Capability Reporting Register of VMCS Field Enumeration (R/O)
Core
See Table 2-2.
Register Address: 48BH, 1163
IA32_VMX_PROCBASED_CTLS2
Capability Reporting Register of Secondary Processor-Based VM-Execution Controls (R/O)
Core
See Table 2-2.
Register Address: 48CH, 1164
IA32_VMX_EPT_VPID_ENUM
Capability Reporting Register of EPT and VPID (R/O)
Core
See Table 2-2.
Register Address: 48DH, 1165
IA32_VMX_TRUE_PINBASED_CTLS
2-452 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-57. Additional MSRs Supported by the Intel® Xeon Phi™ Processor 7215, 7285, 7295 Series
with a CPUID Signature DisplayFamily_DisplayModel Value of 06_85H (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Capability Reporting Register of Pin-Based VM-Execution Flex Controls (R/O)
Core
See Table 2-2.
Register Address: 48EH, 1166
IA32_VMX_TRUE_PROCBASED_CTLS
Capability Reporting Register of Primary Processor-Based VM-Execution Flex Controls (R/O)
Core
See Table 2-2.
Register Address: 48FH, 1167
IA32_VMX_TRUE_EXIT_CTLS
Capability Reporting Register of VM-Exit Flex Controls (R/O)
Core
See Table 2-2.
Register Address: 490H, 1168
IA32_VMX_TRUE_ENTRY_CTLS
Capability Reporting Register of VM-Entry Flex Controls (R/O)
Core
See Table 2-2.
Register Address: 491H, 1169
IA32_VMX_FMFUNC
Capability Reporting Register of VM-Function Controls (R/O)
Core
See Table 2-2.
2.19
MSRS IN THE PENTIUM® 4 AND INTEL® XEON® PROCESSORS
Table 2-58 lists MSRs (architectural and model-specific) that are defined across processor generations based on
Intel NetBurst microarchitecture. The processor can be identified by its CPUID signatures of DisplayFamily
encoding of 0FH, see Table 2-1.
• MSRs with an “IA32_” prefix are designated as “architectural.” This means that the functions of these MSRs and
their addresses remain the same for succeeding families of IA-32 processors.
• MSRs with an “MSR_” prefix are model specific with respect to address functionalities. The column “Model
Availability” lists the model encoding value(s) within the Pentium 4 and Intel Xeon processor family at the
specified register address. The model encoding value of a processor can be queried using CPUID. See
“CPUID-CPU Identification” in Chapter 3 of the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 2A.
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors
Register Address: Hex, Decimal
Register Name
Model
Shared/
Register Information / Bit Fields
Bit Description
Availability
Unique1
Register Address: 0H, 0
IA32_P5_MC_ADDR
See Section 2.23, “MSRs in Pentium Processors.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 1H, 1
IA32_P5_MC_TYPE
See Section 2.23, “MSRs in Pentium Processors.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 6H, 6
IA32_MONITOR_FILTER_LINE_SIZE
See Section 9.10.5, “Monitor/Mwait Address Range Determination.”
3, 4, 6
Shared
Register Address: 10H, 16
IA32_TIME_STAMP_COUNTER
Time Stamp Counter
0, 1, 2, 3, 4, 6
Unique
See Table 2-2.
Vol. 4
2-453
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Model
Shared/
Register Information / Bit Fields
Bit Description
Availability
Unique1
On earlier processors, only the lower 32 bits are writable. On any write to the lower 32 bits, the upper
32 bits are cleared. For processor family 0FH, models 3 and 4: all 64 bits are writable.
Register Address: 17H, 23
IA32_PLATFORM_ID
Platform ID (R)
0, 1, 2, 3, 4, 6
Shared
See Table 2-2.
The operating system can use this MSR to determine “slot” information for the processor and the
proper microcode update to load.
Register Address: 1BH, 27
IA32_APIC_BASE
APIC Location and Status (R/W)
0, 1, 2, 3, 4, 6
Unique
See Table 2-2. See Section 11.4.4, “Local APIC Status and Location.”
Register Address: 2AH, 42
MSR_EBC_HARD_POWERON
Processor Hard Power-On Configuration
0, 1, 2, 3, 4, 6
Shared
(R/W) Enables and disables processor features.
(R) Indicates current processor configuration.
0
Output Tri-state Enabled (R)
Indicates whether tri-state output is enabled (1) or disabled (0) as
set by the strapping of SMI#. The value in this bit is written on
the deassertion of RESET#; the bit is set to 1 when the address
bus signal is asserted.
1
Execute BIST (R)
Indicates whether the execution of the BIST is enabled (1) or
disabled (0) as set by the strapping of INIT#. The value in this bit
is written on the deassertion of RESET#; the bit is set to 1 when
the address bus signal is asserted.
2
In Order Queue Depth (R)
Indicates whether the in order queue depth for the system bus is
1 (1) or up to 12 (0) as set by the strapping of A7#. The value in
this bit is written on the deassertion of RESET#; the bit is set to
1 when the address bus signal is asserted.
3
MCERR# Observation Disabled (R)
Indicates whether MCERR# observation is enabled (0) or disabled
(1) as determined by the strapping of A9#. The value in this bit is
written on the deassertion of RESET#; the bit is set to 1 when
the address bus signal is asserted.
4
BINIT# Observation Enabled (R)
Indicates whether BINIT# observation is enabled (0) or disabled
(1) as determined by the strapping of A10#. The value in this bit
is written on the deassertion of RESET#; the bit is set to 1 when
the address bus signal is asserted.
6:5
APIC Cluster ID (R)
Contains the logical APIC cluster ID value as set by the strapping
of A12# and A11#. The logical cluster ID value is written into the
field on the deassertion of RESET#; the field is set to 1 when the
address bus signal is asserted.
2-454 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Model
Shared/
Register Information / Bit Fields
Bit Description
Availability
Unique1
7
Bus Park Disable (R)
Indicates whether bus park is enabled (0) or disabled (1) as set by
the strapping of A15#. The value in this bit is written on the
deassertion of RESET#; the bit is set to 1 when the address bus
signal is asserted.
11:8
Reserved.
13:12
Agent ID (R)
Contains the logical agent ID value as set by the strapping of
BR[3:0]. The logical ID value is written into the field on the
deassertion of RESET#; the field is set to 1 when the address bus
signal is asserted.
63:14
Reserved.
Register Address: 2BH, 43
MSR_EBC_SOFT_POWERON
Processor Soft Power-On Configuration (R/W)
0, 1, 2, 3, 4, 6
Shared
Enables and disables processor features.
0
RCNT/SCNT On Request Encoding Enable (R/W)
Controls the driving of RCNT/SCNT on the request encoding. Set
to enable (1); clear to disabled (0, default).
1
Data Error Checking Disable (R/W)
Set to disable system data bus parity checking; clear to enable
parity checking.
2
Response Error Checking Disable (R/W)
Set to disable (default); clear to enable.
3
Address/Request Error Checking Disable (R/W)
Set to disable (default); clear to enable.
4
Initiator MCERR# Disable (R/W)
Set to disable MCERR# driving for initiator bus requests (default);
clear to enable.
5
Internal MCERR# Disable (R/W)
Set to disable MCERR# driving for initiator internal errors
(default); clear to enable.
6
BINIT# Driver Disable (R/W)
Set to disable BINIT# driver (default); clear to enable driver.
63:7
Reserved.
Register Address: 2CH, 44
MSR_EBC_FREQUENCY_ID
Processor Frequency Configuration
2,3, 4, 6
Shared
The bit field layout of this MSR varies according to the MODEL value in the CPUID version information.
The following bit field layout applies to Pentium 4 and Xeon Processors with MODEL encoding equal or
greater than 2.
(R) The field Indicates the current processor frequency configuration.
15:0
Reserved.
Vol. 4
2-455
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Model
Shared/
Register Information / Bit Fields
Bit Description
Availability
Unique1
18:16
Scalable Bus Speed (R/W)
Indicates the intended scalable bus speed:
EncodingScalable Bus Speed
000B
100 MHz (Model 2)
000B
266 MHz (Model 3 or 4)
001B
133 MHz
010B
200 MHz
011B
166 MHz
100B
333 MHz (Model 6)
133.33 MHz should be utilized if performing calculation with
System Bus Speed when encoding is 001B.
166.67 MHz should be utilized if performing calculation with
System Bus Speed when encoding is 011B.
266.67 MHz should be utilized if performing calculation with
System Bus Speed when encoding is 000B and model encoding =
3 or 4.
333.33 MHz should be utilized if performing calculation with
System Bus Speed when encoding is 100B and model encoding =
6.
All other values are reserved.
23:19
Reserved.
31:24
Core Clock Frequency to System Bus Frequency Ratio (R)
The processor core clock frequency to system bus frequency
ratio observed at the de-assertion of the reset pin.
63:25
Reserved.
Register Address: 2CH, 44
MSR_EBC_FREQUENCY_ID
Processor Frequency Configuration (R)
0, 1
Shared
The bit field layout of this MSR varies according to the MODEL value of the CPUID version information.
This bit field layout applies to Pentium 4 and Xeon Processors with MODEL encoding less than 2.
Indicates current processor frequency configuration.
20:0
Reserved.
23:21
Scalable Bus Speed (R/W)
Indicates the intended scalable bus speed:
Encoding Scalable Bus Speed
000B
100 MHz
All others values reserved.
63:24
Reserved.
Register Address: 3AH, 58
IA32_FEATURE_CONTROL
Control Features in IA-32 Processor (R/W)
3, 4, 6
Unique
See Table 2-2.
(If CPUID.01H:ECX.[bit 5])
Register Address: 79H, 121
IA32_BIOS_UPDT_TRIG
2-456 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Model
Shared/
Register Information / Bit Fields
Bit Description
Availability
Unique1
BIOS Update Trigger Register (W)
0, 1, 2, 3, 4, 6
Shared
See Table 2-2.
Register Address: 8BH, 139
IA32_BIOS_SIGN_ID
BIOS Update Signature ID (R/W)
0, 1, 2, 3, 4, 6
Unique
See Table 2-2.
Register Address: 9BH, 155
IA32_SMM_MONITOR_CTL
SMM Monitor Configuration (R/W)
3, 4, 6
Unique
See Table 2-2.
Register Address: FEH, 254
IA32_MTRRCAP
MTRR Information
0, 1, 2, 3, 4, 6
Unique
See Section 12.11.1, “MTRR Feature Identification.”
Register Address: 174H, 372
IA32_SYSENTER_CS
CS Register Target for CPL 0 Code (R/W)
0, 1, 2, 3, 4, 6
Unique
See Table 2-2 and Section 5.8.7, “Performing Fast Calls to System Procedures with the SYSENTER and
SYSEXIT Instructions.”
Register Address: 175H, 373
IA32_SYSENTER_ESP
Stack Pointer for CPL 0 Stack (R/W)
0, 1, 2, 3, 4, 6
Unique
See Table 2-2 and Section 5.8.7, “Performing Fast Calls to System Procedures with the SYSENTER and
SYSEXIT Instructions.”
Register Address: 176H, 374
IA32_SYSENTER_EIP
CPL 0 Code Entry Point (R/W)
0, 1, 2, 3, 4, 6
Unique
See Table 2-2 and Section 5.8.7, “Performing Fast Calls to System Procedures with the SYSENTER and
SYSEXIT Instructions.”
Register Address: 179H, 377
IA32_MCG_CAP
Machine Check Capabilities (R)
0, 1, 2, 3, 4, 6
Unique
See Table 2-2 and Section 16.3.1.1, “IA32_MCG_CAP MSR.”
Register Address: 17AH, 378
IA32_MCG_STATUS
Machine Check Status (R)
0, 1, 2, 3, 4, 6
Unique
See Table 2-2 and Section 16.3.1.2, “IA32_MCG_STATUS MSR.”
Register Address: 17BH, 379
IA32_MCG_CTL
Machine Check Feature Enable (R/W)
See Table 2-2 and Section 16.3.1.3, “IA32_MCG_CTL MSR.”
Register Address: 180H, 384
MSR_MCG_RAX
Machine Check EAX/RAX Save State
0, 1, 2, 3, 4, 6
Unique
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
63:0
Contains register state at time of machine check error. When in
non-64-bit modes at the time of the error, bits 63-32 do not
contain valid data.
Register Address: 181H, 385
MSR_MCG_RBX
Vol. 4
2-457
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Model
Shared/
Register Information / Bit Fields
Bit Description
Availability
Unique1
Machine Check EBX/RBX Save State
0, 1, 2, 3, 4, 6
Unique
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
63:0
Contains register state at time of machine check error. When in
non-64-bit modes at the time of the error, bits 63-32 do not
contain valid data.
Register Address: 182H, 386
MSR_MCG_RCX
Machine Check ECX/RCX Save State
0, 1, 2, 3, 4, 6
Unique
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
63:0
Contains register state at time of machine check error. When in
non-64-bit modes at the time of the error, bits 63-32 do not
contain valid data.
Register Address: 183H, 387
MSR_MCG_RDX
Machine Check EDX/RDX Save State
0, 1, 2, 3, 4, 6
Unique
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
63:0
Contains register state at time of machine check error. When in
non-64-bit modes at the time of the error, bits 63-32 do not
contain valid data.
Register Address: 184H, 388
MSR_MCG_RSI
Machine Check ESI/RSI Save State
0, 1, 2, 3, 4, 6
Unique
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
63:0
Contains register state at time of machine check error. When in
non-64-bit modes at the time of the error, bits 63-32 do not
contain valid data.
Register Address: 185H, 389
MSR_MCG_RDI
Machine Check EDI/RDI Save State
0, 1, 2, 3, 4, 6
Unique
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
63:0
Contains register state at time of machine check error. When in
non-64-bit modes at the time of the error, bits 63-32 do not
contain valid data.
Register Address: 186H, 390
MSR_MCG_RBP
Machine Check EBP/RBP Save State
0, 1, 2, 3, 4, 6
Unique
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
63:0
Contains register state at time of machine check error. When in
non-64-bit modes at the time of the error, bits 63-32 do not
contain valid data.
Register Address: 187H, 391
MSR_MCG_RSP
Machine Check ESP/RSP Save State
0, 1, 2, 3, 4, 6
Unique
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
63:0
Contains register state at time of machine check error. When in
non-64-bit modes at the time of the error, bits 63-32 do not
contain valid data.
Register Address: 188H, 392
MSR_MCG_RFLAGS
2-458 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Model
Shared/
Register Information / Bit Fields
Bit Description
Availability
Unique1
Machine Check EFLAGS/RFLAG Save State
0, 1, 2, 3, 4, 6
Unique
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
63:0
Contains register state at time of machine check error. When in
non-64-bit modes at the time of the error, bits 63-32 do not
contain valid data.
Register Address: 189H, 393
MSR_MCG_RIP
Machine Check EIP/RIP Save State
0, 1, 2, 3, 4, 6
Unique
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
63:0
Contains register state at time of machine check error. When in
non-64-bit modes at the time of the error, bits 63-32 do not
contain valid data.
Register Address: 18AH, 394
MSR_MCG_MISC
Machine Check Miscellaneous
0, 1, 2, 3, 4, 6
Unique
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
0
DS
When set, the bit indicates that a page assist or page fault
occurred during DS normal operation. The processors response is
to shut down.
The bit is used as an aid for debugging DS handling code. It is the
responsibility of the user (BIOS or operating system) to clear this
bit for normal operation.
63:1
Reserved.
Register Address: 18BH-18FH,
MSR_MCG_RESERVED1-MSR_MCG_RESERVED5
395-399
Reserved.
Register Address: 190H, 400
MSR_MCG_R8
Machine Check R8
0, 1, 2, 3, 4, 6
Unique
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
63:0
Registers R8-15 (and the associated state-save MSRs) exist only
in Intel 64 processors. These registers contain valid information
only when the processor is operating in 64-bit mode at the time
of the error.
Register Address: 191H, 401
MSR_MCG_R9
Machine Check R9D/R9
0, 1, 2, 3, 4, 6
Unique
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
63:0
Registers R8-15 (and the associated state-save MSRs) exist only
in Intel 64 processors. These registers contain valid information
only when the processor is operating in 64-bit mode at the time
of the error.
Register Address: 192H, 402
MSR_MCG_R10
Machine Check R10
0, 1, 2, 3, 4, 6
Unique
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
Vol. 4
2-459
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Model
Shared/
Register Information / Bit Fields
Bit Description
Availability
Unique1
63:0
Registers R8-15 (and the associated state-save MSRs) exist only
in Intel 64 processors. These registers contain valid information
only when the processor is operating in 64-bit mode at the time
of the error.
Register Address: 193H, 403
MSR_MCG_R11
Machine Check R11
0, 1, 2, 3, 4, 6
Unique
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
63:0
Registers R8-15 (and the associated state-save MSRs) exist only
in Intel 64 processors. These registers contain valid information
only when the processor is operating in 64-bit mode at the time
of the error.
Register Address: 194H, 404
MSR_MCG_R12
Machine Check R12
0, 1, 2, 3, 4, 6
Unique
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
63:0
Registers R8-15 (and the associated state-save MSRs) exist only
in Intel 64 processors. These registers contain valid information
only when the processor is operating in 64-bit mode at the time
of the error.
Register Address: 195H, 405
MSR_MCG_R13
Machine Check R13
0, 1, 2, 3, 4, 6
Unique
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
63:0
Registers R8-15 (and the associated state-save MSRs) exist only
in Intel 64 processors. These registers contain valid information
only when the processor is operating in 64-bit mode at the time
of the error.
Register Address: 196H, 406
MSR_MCG_R14
Machine Check R14
0, 1, 2, 3, 4, 6
Unique
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
63:0
Registers R8-15 (and the associated state-save MSRs) exist only
in Intel 64 processors. These registers contain valid information
only when the processor is operating in 64-bit mode at the time
of the error.
Register Address: 197H, 407
MSR_MCG_R15
Machine Check R15
0, 1, 2, 3, 4, 6
Unique
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
63:0
Registers R8-15 (and the associated state-save MSRs) exist only
in Intel 64 processors. These registers contain valid information
only when the processor is operating in 64-bit mode at the time
of the error.
Register Address: 198H, 408
IA32_PERF_STATUS
See Table 2-2. See Section 15.1, “Enhanced Intel Speedstep® Technology.”
3, 4, 6
Unique
Register Address: 199H, 409
IA32_PERF_CTL
See Table 2-2. See Section 15.1, “Enhanced Intel Speedstep® Technology.”
3, 4, 6
Unique
2-460 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Model
Shared/
Register Information / Bit Fields
Bit Description
Availability
Unique1
Register Address: 19AH, 410
IA32_CLOCK_MODULATION
Thermal Monitor Control (R/W)
0, 1, 2, 3, 4, 6
Unique
See Table 2-2 and Section 15.8.3, “Software Controlled Clock Modulation.”
Register Address: 19BH, 411
IA32_THERM_INTERRUPT
Thermal Interrupt Control (R/W)
0, 1, 2, 3, 4, 6
Unique
See Section 15.8.2, “Thermal Monitor,” and Table 2-2.
Register Address: 19CH, 412
IA32_THERM_STATUS
Thermal Monitor Status (R/W)
0, 1, 2, 3, 4, 6
Shared
See Section 15.8.2, “Thermal Monitor,” and Table 2-2.
Register Address: 19DH, 413
MSR_THERM2_CTL
Thermal Monitor 2 Control
For Family F, Model 3 processors: When read, specifies the value of the target TM2 transition last
3
Shared
written. When set, it sets the next target value for TM2 transition.
For Family F, Model 4 and Model 6 processors: When read, specifies the value of the target TM2
4, 6
Shared
transition last written. Writes may cause #GP exceptions.
Register Address: 1A0H, 416
IA32_MISC_ENABLE
Enable Miscellaneous Processor Features (R/W)
0, 1, 2, 3, 4, 6
Shared
0
Fast-Strings Enable. See Table 2-2.
1
Reserved.
2
x87 FPU Fopcode Compatibility Mode Enable
3
Thermal Monitor 1 Enable
See Section 15.8.2, “Thermal Monitor,” and Table 2-2.
4
Split-Lock Disable
When set, the bit causes an #AC exception to be issued instead
of a split-lock cycle. Operating systems that set this bit must align
system structures to avoid split-lock scenarios.
When the bit is clear (default), normal split-locks are issued to the
bus.
This debug feature is specific to the Pentium 4 processor.
5
Reserved.
6
Third-Level Cache Disable (R/W)
When set, the third-level cache is disabled; when clear (default)
the third-level cache is enabled. This flag is reserved for
processors that do not have a third-level cache.
Note that the bit controls only the third-level cache; and only if
overall caching is enabled through the CD flag of control register
CR0, the page-level cache controls, and/or the MTRRs.
See Section 12.5.4, “Disabling and Enabling the L3 Cache.”
7
Performance Monitoring Available (R)
See Table 2-2.
Vol. 4
2-461
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Model
Shared/
Register Information / Bit Fields
Bit Description
Availability
Unique1
8
Suppress Lock Enable
When set, assertion of LOCK on the bus is suppressed during a
Split Lock access. When clear (default), LOCK is not suppressed.
9
Prefetch Queue Disable
When set, disables the prefetch queue. When clear (default),
enables the prefetch queue.
10
FERR# Interrupt Reporting Enable (R/W)
When set, interrupt reporting through the FERR# pin is enabled;
when clear, this interrupt reporting function is disabled.
When this flag is set and the processor is in the stop-clock state
(STPCLK# is asserted), asserting the FERR# pin signals to the
processor that an interrupt (such as, INIT#, BINIT#, INTR, NMI,
SMI#, or RESET#) is pending and that the processor should return
to normal operation to handle the interrupt.
This flag does not affect the normal operation of the FERR# pin
(to indicate an unmasked floating-point error) when the STPCLK#
pin is not asserted.
11
Branch Trace Storage Unavailable (BTS_UNAVILABLE) (R)
See Table 2-2.
When set, the processor does not support branch trace storage
(BTS); when clear, BTS is supported.
12
PEBS_UNAVILABLE: Processor Event Based Sampling Unavailable
(R)
See Table 2-2.
When set, the processor does not support processor event-based
sampling (PEBS); when clear, PEBS is supported.
13
TM2 Enable (R/W)
3
When this bit is set (1) and the thermal sensor indicates that the
die temperature is at the pre-determined threshold, the Thermal
Monitor 2 mechanism is engaged. TM2 will reduce the bus to core
ratio and voltage according to the value last written to
MSR_THERM2_CTL bits 15:0.
When this bit is clear (0, default), the processor does not change
the VID signals or the bus to core ratio when the processor
enters a thermal managed state.
If the TM2 feature flag (ECX[8]) is not set to 1 after executing
CPUID with EAX = 1, then this feature is not supported and BIOS
must not alter the contents of this bit location. The processor is
operating out of spec if both this bit and the TM1 bit are set to
disabled states.
17:14
Reserved.
18
ENABLE MONITOR FSM (R/W)
3, 4, 6
See Table 2-2.
2-462 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Model
Shared/
Register Information / Bit Fields
Bit Description
Availability
Unique1
19
Adjacent Cache Line Prefetch Disable (R/W)
When set to 1, the processor fetches the cache line of the 128-
byte sector containing currently required data. When set to 0, the
processor fetches both cache lines in the sector.
Single processor platforms should not set this bit. Server
platforms should set or clear this bit based on platform
performance observed in validation and testing.
BIOS may contain a setup option that controls the setting of this
bit.
21:20
Reserved.
22
Limit CPUID MAXVAL (R/W)
3, 4, 6
See Table 2-2.
Setting this can cause unexpected behavior to software that
depends on the availability of CPUID leaves greater than 3.
23
xTPR Message Disable (R/W)
Shared
See Table 2-2.
24
L1 Data Cache Context Mode (R/W)
When set, the L1 data cache is placed in shared mode; when clear
(default), the cache is placed in adaptive mode. This bit is only
enabled for IA-32 processors that support Intel Hyper-Threading
Technology. See Section 12.5.6, “L1 Data Cache Context Mode.”
When L1 is running in adaptive mode and CR3s are identical, data
in L1 is shared across logical processors. Otherwise, L1 is not
shared and cache use is competitive.
If the Context ID feature flag (ECX[10]) is set to 0 after executing
CPUID with EAX = 1, the ability to switch modes is not supported.
BIOS must not alter the contents of IA32_MISC_ENABLE[24].
33:25
Reserved.
34
XD Bit Disable (R/W)
Unique
See Table 2-3.
63:35
Reserved.
Register Address: 1A1H, 417
MSR_PLATFORM_BRV
Platform Feature Requirements (R)
3, 4, 6
Shared
17:0
Reserved.
18
PLATFORM Requirements
When set to 1, indicates the processor has specific platform
requirements. The details of the platform requirements are listed
in the respective data sheets of the processor.
63:19
Reserved.
Register Address: 1D7H, 471
MSR_LER_FROM_LIP
Vol. 4
2-463
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Model
Shared/
Register Information / Bit Fields
Bit Description
Availability
Unique1
Last Exception Record From Linear IP (R)
0, 1, 2, 3, 4, 6
Unique
Contains a pointer to the last branch instruction that the processor executed prior to the last
exception that was generated or the last interrupt that was handled.
See Section 18.13.3, “Last Exception Records.”
31:0
From Linear IP
Linear address of the last branch instruction.
63:32
Reserved.
Register Address: 1D7H, 471
MSR_LER_FROM_LIP
63:0
From Linear IP
Unique
Linear address of the last branch instruction (If IA-32e mode is
active).
Register Address: 1D8H, 472
MSR_LER_TO_LIP
Last Exception Record To Linear IP (R)
0, 1, 2, 3, 4, 6
Unique
This area contains a pointer to the target of the last branch instruction that the processor executed
prior to the last exception that was generated or the last interrupt that was handled.
See Section 18.13.3, “Last Exception Records.”
31:0
From Linear IP
Linear address of the target of the last branch instruction.
63:32
Reserved.
Register Address: 1D8H, 472
MSR_LER_TO_LIP
63:0
From Linear IP
Unique
Linear address of the target of the last branch instruction (If IA-
32e mode is active).
Register Address: 1D9H, 473
MSR_DEBUGCTLA
Debug Control (R/W)
0, 1, 2, 3, 4, 6
Unique
Controls how several debug features are used. Bit definitions are discussed in the referenced section.
See Section 18.13.1, “MSR_DEBUGCTLA MSR.”
Register Address: 1DAH, 474
MSR_LASTBRANCH_TOS
Last Branch Record Stack TOS (R/O)
0, 1, 2, 3, 4, 6
Unique
Contains an index (0-3 or 0-15) that points to the top of the last branch record stack (that is, that
points the index of the MSR containing the most recent branch record).
See Section 18.13.2, “LBR Stack for Processors Based on Intel NetBurst® Microarchitecture,” and
addresses 1DBH-1DEH and 680H-68FH.
Register Address: 1DBH, 475
MSR_LASTBRANCH_0
Last Branch Record 0 (R/O)
0, 1, 2
Unique
One of four last branch record registers on the last branch record stack. It contains pointers to the
source and destination instruction for one of the last four branches, exceptions, or interrupts that the
processor took.
MSR_LASTBRANCH_0 through MSR_LASTBRANCH_3 at 1DBH-1DEH are available only on family 0FH,
models 0H-02H. They have been replaced by the MSRs at 680H-68FH and 6C0H-6CFH.
See Section 18.12, “Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based
on Skylake Microarchitecture.”
2-464 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Model
Shared/
Register Information / Bit Fields
Bit Description
Availability
Unique1
Register Address: 1DCH, 476
MSR_LASTBRANCH_1
Last Branch Record 1
0, 1, 2
Unique
See description of the MSR_LASTBRANCH_0 MSR at 1DBH.
Register Address: 1DDH, 477
MSR_LASTBRANCH_2
Last Branch Record 2
0, 1, 2
Unique
See description of the MSR_LASTBRANCH_0 MSR at 1DBH.
Register Address: 1DEH, 478
MSR_LASTBRANCH_3
Last Branch Record 3
0, 1, 2
Unique
See description of the MSR_LASTBRANCH_0 MSR at 1DBH.
Register Address: 200H, 512
IA32_MTRR_PHYSBASE0
Variable Range Base MTRR
0, 1, 2, 3, 4, 6
Shared
See Section 12.11.2.3, “Variable Range MTRRs.”
Register Address: 201H, 513
IA32_MTRR_PHYSMASK0
Variable Range Mask MTRR
0, 1, 2, 3, 4, 6
Shared
See Section 12.11.2.3, “Variable Range MTRRs.”
Register Address: 202H, 514
IA32_MTRR_PHYSBASE1
Variable Range Mask MTRR
0, 1, 2, 3, 4, 6
Shared
See Section 12.11.2.3, “Variable Range MTRRs.”
Register Address: 203H, 515
IA32_MTRR_PHYSMASK1
Variable Range Mask MTRR
0, 1, 2, 3, 4, 6
Shared
See Section 12.11.2.3, “Variable Range MTRRs.”
Register Address: 204H, 516
IA32_MTRR_PHYSBASE2
Variable Range Mask MTRR
0, 1, 2, 3, 4, 6
Shared
See Section 12.11.2.3, “Variable Range MTRRs.”
Register Address: 205H, 517
IA32_MTRR_PHYSMASK2
Variable Range Mask MTRR
0, 1, 2, 3, 4, 6
Shared
See Section 12.11.2.3, “Variable Range MTRRs”.
Register Address: 206H, 518
IA32_MTRR_PHYSBASE3
Variable Range Mask MTRR
0, 1, 2, 3, 4, 6
Shared
See Section 12.11.2.3, “Variable Range MTRRs.”
Register Address: 207H, 519
IA32_MTRR_PHYSMASK3
Variable Range Mask MTRR
0, 1, 2, 3, 4, 6
Shared
See Section 12.11.2.3, “Variable Range MTRRs.”
Register Address: 208H, 520
IA32_MTRR_PHYSBASE4
Variable Range Mask MTRR
0, 1, 2, 3, 4, 6
Shared
See Section 12.11.2.3, “Variable Range MTRRs.”
Register Address: 209H, 521
IA32_MTRR_PHYSMASK4
Vol. 4
2-465
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Model
Shared/
Register Information / Bit Fields
Bit Description
Availability
Unique1
Variable Range Mask MTRR
0, 1, 2, 3, 4, 6
Shared
See Section 12.11.2.3, “Variable Range MTRRs.”
Register Address: 20AH, 522
IA32_MTRR_PHYSBASE5
Variable Range Mask MTRR
0, 1, 2, 3, 4, 6
Shared
See Section 12.11.2.3, “Variable Range MTRRs.”
Register Address: 20BH, 523
IA32_MTRR_PHYSMASK5
Variable Range Mask MTRR
0, 1, 2, 3, 4, 6
Shared
See Section 12.11.2.3, “Variable Range MTRRs.”
Register Address: 20CH, 524
IA32_MTRR_PHYSBASE6
Variable Range Mask MTRR
0, 1, 2, 3, 4, 6
Shared
See Section 12.11.2.3, “Variable Range MTRRs.”
Register Address: 20DH, 525
IA32_MTRR_PHYSMASK6
Variable Range Mask MTRR
0, 1, 2, 3, 4, 6
Shared
See Section 12.11.2.3, “Variable Range MTRRs.”
Register Address: 20EH, 526
IA32_MTRR_PHYSBASE7
Variable Range Mask MTRR
0, 1, 2, 3, 4, 6
Shared
See Section 12.11.2.3, “Variable Range MTRRs.”
Register Address: 20FH, 527
IA32_MTRR_PHYSMASK7
Variable Range Mask MTRR
0, 1, 2, 3, 4, 6
Shared
See Section 12.11.2.3, “Variable Range MTRRs.”
Register Address: 250H, 592
IA32_MTRR_FIX64K_00000
Fixed Range MTRR
0, 1, 2, 3, 4, 6
Shared
See Section 12.11.2.2, “Fixed Range MTRRs.”
Register Address: 258H, 600
IA32_MTRR_FIX16K_80000
Fixed Range MTRR
0, 1, 2, 3, 4, 6
Shared
See Section 12.11.2.2, “Fixed Range MTRRs.”
Register Address: 259H, 601
IA32_MTRR_FIX16K_A0000
Fixed Range MTRR
0, 1, 2, 3, 4, 6
Shared
See Section 12.11.2.2, “Fixed Range MTRRs.”
Register Address: 268H, 616
IA32_MTRR_FIX4K_C0000
Fixed Range MTRR
0, 1, 2, 3, 4, 6
Shared
See Section 12.11.2.2, “Fixed Range MTRRs.”
Register Address: 269H, 617
IA32_MTRR_FIX4K_C8000
Fixed Range MTRR
0, 1, 2, 3, 4, 6
Shared
See Section 12.11.2.2, “Fixed Range MTRRs”.
Register Address: 26AH, 618
IA32_MTRR_FIX4K_D0000
Fixed Range MTRR
0, 1, 2, 3, 4, 6
Shared
See Section 12.11.2.2, “Fixed Range MTRRs”.
2-466 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Model
Shared/
Register Information / Bit Fields
Bit Description
Availability
Unique1
Register Address: 26BH, 619
IA32_MTRR_FIX4K_D8000
Fixed Range MTRR
0, 1, 2, 3, 4, 6
Shared
See Section 12.11.2.2, “Fixed Range MTRRs.”
Register Address: 26CH, 620
IA32_MTRR_FIX4K_E0000
Fixed Range MTRR
0, 1, 2, 3, 4, 6
Shared
See Section 12.11.2.2, “Fixed Range MTRRs.”
Register Address: 26DH, 621
IA32_MTRR_FIX4K_E8000
Fixed Range MTRR
0, 1, 2, 3, 4, 6
Shared
See Section 12.11.2.2, “Fixed Range MTRRs.”
Register Address: 26EH, 622
IA32_MTRR_FIX4K_F0000
Fixed Range MTRR
0, 1, 2, 3, 4, 6
Shared
See Section 12.11.2.2, “Fixed Range MTRRs.”
Register Address: 26FH, 623
IA32_MTRR_FIX4K_F8000
Fixed Range MTRR
0, 1, 2, 3, 4, 6
Shared
See Section 12.11.2.2, “Fixed Range MTRRs.”
Register Address: 277H, 631
IA32_PAT
Page Attribute Table
0, 1, 2, 3, 4, 6
Unique
See Section 12.11.2.2, “Fixed Range MTRRs.”
Register Address: 2FFH, 767
IA32_MTRR_DEF_TYPE
Default Memory Types (R/W)
0, 1, 2, 3, 4, 6
Shared
See Table 2-2 and Section 12.11.2.1, “IA32_MTRR_DEF_TYPE MSR.”
Register Address: 300H, 768
MSR_BPU_COUNTER0
See Section 20.6.3.2, “Performance Counters.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 301H, 769
MSR_BPU_COUNTER1
See Section 20.6.3.2, “Performance Counters.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 302H, 770
MSR_BPU_COUNTER2
See Section 20.6.3.2, “Performance Counters.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 303H, 771
MSR_BPU_COUNTER3
See Section 20.6.3.2, “Performance Counters.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 304H, 772
MSR_MS_COUNTER0
See Section 20.6.3.2, “Performance Counters.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 305H, 773
MSR_MS_COUNTER1
See Section 20.6.3.2, “Performance Counters.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 306H, 774
MSR_MS_COUNTER2
See Section 20.6.3.2, “Performance Counters.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 307H, 775
MSR_MS_COUNTER3
See Section 20.6.3.2, “Performance Counters.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 308H, 776
MSR_FLAME_COUNTER0
Vol. 4
2-467
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Model
Shared/
Register Information / Bit Fields
Bit Description
Availability
Unique1
See Section 20.6.3.2, “Performance Counters.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 309H, 777
MSR_FLAME_COUNTER1
See Section 20.6.3.2, “Performance Counters.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 30AH, 778
MSR_FLAME_COUNTER2
See Section 20.6.3.2, “Performance Counters.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 30BH, 779
MSR_FLAME_COUNTER3
See Section 20.6.3.2, “Performance Counters.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 30CH, 780
MSR_IQ_COUNTER0
See Section 20.6.3.2, “Performance Counters.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 30DH, 781
MSR_IQ_COUNTER1
See Section 20.6.3.2, “Performance Counters.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 30EH, 782
MSR_IQ_COUNTER2
See Section 20.6.3.2, “Performance Counters.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 30FH, 783
MSR_IQ_COUNTER3
See Section 20.6.3.2, “Performance Counters.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 310H, 784
MSR_IQ_COUNTER4
See Section 20.6.3.2, “Performance Counters.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 311H, 785
MSR_IQ_COUNTER5
See Section 20.6.3.2, “Performance Counters.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 360H, 864
MSR_BPU_CCCR0
See Section 20.6.3.3, “CCCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 361H, 865
MSR_BPU_CCCR1
See Section 20.6.3.3, “CCCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 362H, 866
MSR_BPU_CCCR2
See Section 20.6.3.3, “CCCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 363H, 867
MSR_BPU_CCCR3
See Section 20.6.3.3, “CCCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 364H, 868
MSR_MS_CCCR0
See Section 20.6.3.3, “CCCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 365H, 869
MSR_MS_CCCR1
See Section 20.6.3.3, “CCCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 366H, 870
MSR_MS_CCCR2
See Section 20.6.3.3, “CCCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 367H, 871
MSR_MS_CCCR3
See Section 20.6.3.3, “CCCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 368H, 872
MSR_FLAME_CCCR0
See Section 20.6.3.3, “CCCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
2-468 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Model
Shared/
Register Information / Bit Fields
Bit Description
Availability
Unique1
Register Address: 369H, 873
MSR_FLAME_CCCR1
See Section 20.6.3.3, “CCCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 36AH, 874
MSR_FLAME_CCCR2
See Section 20.6.3.3, “CCCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 36BH, 875
MSR_FLAME_CCCR3
See Section 20.6.3.3, “CCCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 36CH, 876
MSR_IQ_CCCR0
See Section 20.6.3.3, “CCCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 36DH, 877
MSR_IQ_CCCR1
See Section 20.6.3.3, “CCCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 36EH, 878
MSR_IQ_CCCR2
See Section 20.6.3.3, “CCCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 36FH, 879
MSR_IQ_CCCR3
See Section 20.6.3.3, “CCCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 370H, 880
MSR_IQ_CCCR4
See Section 20.6.3.3, “CCCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 371H, 881
MSR_IQ_CCCR5
See Section 20.6.3.3, “CCCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3A0H, 928
MSR_BSU_ESCR0
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3A1H, 929
MSR_BSU_ESCR1
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3A2H, 930
MSR_FSB_ESCR0
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3A3H, 931
MSR_FSB_ESCR1
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3A4H, 932
MSR_FIRM_ESCR0
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3A5H, 933
MSR_FIRM_ESCR1
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3A6H, 934
MSR_FLAME_ESCR0
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3A7H, 935
MSR_FLAME_ESCR1
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3A8H, 936
MSR_DAC_ESCR0
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3A9H, 937
MSR_DAC_ESCR1
Vol. 4
2-469
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Model
Shared/
Register Information / Bit Fields
Bit Description
Availability
Unique1
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3AAH, 938
MSR_MOB_ESCR0
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3ABH, 939
MSR_MOB_ESCR1
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3ACH, 940
MSR_PMH_ESCR0
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3ADH, 941
MSR_PMH_ESCR1
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3AEH, 942
MSR_SAAT_ESCR0
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3AFH, 943
MSR_SAAT_ESCR1
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3B0H, 944
MSR_U2L_ESCR0
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3B1H, 945
MSR_U2L_ESCR1
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3B2H, 946
MSR_BPU_ESCR0
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3B3H, 947
MSR_BPU_ESCR1
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3B4H, 948
MSR_IS_ESCR0
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3B5H, 949
MSR_IS_ESCR1
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3B6H, 950
MSR_ITLB_ESCR0
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3B7H, 951
MSR_ITLB_ESCR1
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3B8H, 952
MSR_CRU_ESCR0
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3B9H, 953
MSR_CRU_ESCR1
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3BAH, 954
MSR_IQ_ESCR0
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2
Shared
This MSR is not available on later processors. It is only available on processor family 0FH, models 01H-
02H.
2-470 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Model
Shared/
Register Information / Bit Fields
Bit Description
Availability
Unique1
Register Address: 3BBH, 955
MSR_IQ_ESCR1
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2
Shared
This MSR is not available on later processors. It is only available on processor family 0FH, models 01H-
02H.
Register Address: 3BCH, 956
MSR_RAT_ESCR0
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3BDH, 957
MSR_RAT_ESCR1
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3BEH, 958
MSR_SSU_ESCR0
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3C0H, 960
MSR_MS_ESCR0
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3C1H, 961
MSR_MS_ESCR1
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3C2H, 962
MSR_TBPU_ESCR0
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3C3H, 963
MSR_TBPU_ESCR1
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3C4H, 964
MSR_TC_ESCR0
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3C5H, 965
MSR_TC_ESCR1
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3C8H, 968
MSR_IX_ESCR0
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3C9H, 969
MSR_IX_ESCR1
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3CAH, 970
MSR_ALF_ESCR0
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3CBH, 971
MSR_ALF_ESCR1
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3CCH, 972
MSR_CRU_ESCR2
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3CDH, 973
MSR_CRU_ESCR3
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3E0H, 992
MSR_CRU_ESCR4
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3E1H, 993
MSR_CRU_ESCR5
Vol. 4
2-471
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal
Register Name
Model
Shared/
Register Information / Bit Fields
Bit Description
Availability
Unique1
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3F0H, 1008
MSR_TC_PRECISE_EVENT
See Section 20.6.3.1, “ESCR MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 3F1H, 1009
IA32_PEBS_ENABLE (MSR_PEBS_ENABLE)
Processor Event Based Sampling (PEBS) (R/W)
0, 1, 2, 3, 4, 6
Shared
Controls the enabling of processor event sampling and replay tagging.
12:0
See https://perfmon-events.intel.com/.
23:13
Reserved.
24
UOP Tag
Enables replay tagging when set.
25
ENABLE_PEBS_MY_THR (R/W)
Enables PEBS for the target logical processor when set; disables
PEBS when clear (default).
See Section 20.6.4.3, “IA32_PEBS_ENABLE MSR,” for an
explanation of the target logical processor.
This bit is called ENABLE_PEBS in IA-32 processors that do not
support Intel Hyper-Threading Technology.
26
ENABLE_PEBS_OTH_THR (R/W)
Enables PEBS for the target logical processor when set; disables
PEBS when clear (default).
See Section 20.6.4.3, “IA32_PEBS_ENABLE MSR,” for an
explanation of the target logical processor.
This bit is reserved for IA-32 processors that do not support Intel
Hyper-Threading Technology.
63:27
Reserved.
Register Address: 3F2H, 1010
MSR_PEBS_MATRIX_VERT
See https://perfmon-events.intel.com/.
0, 1, 2, 3, 4, 6
Shared
Register Address: 400H, 1024
IA32_MC0_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 401H, 1025
IA32_MC0_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”
0, 1, 2, 3, 4, 6
Shared
Register Address: 402H, 1026
IA32_MC0_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
0, 1, 2, 3, 4, 6
Shared
The IA32_MC0_ADDR register is either not implemented or contains no address if the ADDRV flag in
the IA32_MC0_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-
protection exception.
Register Address: 403H, 1027
IA32_MC0_MISC
2-472 Vol. 4