Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 12
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family
Based on Broadwell Microarchitecture (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
63:28
Reserved.
Register Address: 1ADH, 429
MSR_TURBO_RATIO_LIMIT
Maximum Ratio Limit of Turbo Mode
Package
R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1.
7:0
Maximum Ratio Limit for 1C
Package
15:8
Maximum Ratio Limit for 2C
Package
23:16
Maximum Ratio Limit for 3C
Package
31:24
Maximum Ratio Limit for 4C
Package
39:32
Maximum Ratio Limit for 5C
Package
47:40
Maximum Ratio Limit for 6C
Package
55:48
Maximum Ratio Limit for 7C
Package
63:56
Maximum Ratio Limit for 8C
Package
Register Address: 1AEH, 430
MSR_TURBO_RATIO_LIMIT1
Maximum Ratio Limit of Turbo Mode
Package
R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1.
7:0
Maximum Ratio Limit for 9C
Package
15:8
Maximum Ratio Limit for 10C
Package
23:16
Maximum Ratio Limit for 11C
Package
31:24
Maximum Ratio Limit for 12C
Package
39:32
Maximum Ratio Limit for 13C
Package
47:40
Maximum Ratio Limit for 14C
Package
55:48
Maximum Ratio Limit for 15C
Package
63:56
Maximum Ratio Limit for 16C
Package
Register Address: 606H, 1542
MSR_RAPL_POWER_UNIT
Unit Multipliers Used in RAPL Interfaces (R/O)
Package
3:0
Power Units
Package
See Section 15.10.1, “RAPL Interfaces.”
7:4
Reserved.
Package
12:8
Energy Status Units
Package
Energy related information (in Joules) is based on the multiplier, 1/2^ESU;
where ESU is an unsigned integer represented by bits 12:8. Default value
is 0EH (or 61 micro-joules).
15:13
Reserved.
Package
19:16
Time Units
Package
See Section 15.10.1, “RAPL Interfaces.”
63:20
Reserved.
Register Address: 618H, 1560
MSR_DRAM_POWER_LIMIT
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2-313
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family
Based on Broadwell Microarchitecture (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
DRAM RAPL Power Limit Control (R/W)
Package
See Section 15.10.5, “DRAM RAPL Domain.”
Register Address: 619H, 1561
MSR_DRAM_ENERGY_STATUS
DRAM Energy Status (R/O)
Package
Energy consumed by DRAM devices.
31:0
Energy in 15.3 micro-joules. Requires BIOS configuration to enable DRAM
RAPL mode 0 (Direct VR).
63:32
Reserved.
Register Address: 61BH, 1563
MSR_DRAM_PERF_STATUS
DRAM Performance Throttling Status (R/O)
Package
See Section 15.10.5, “DRAM RAPL Domain.”
Register Address: 61CH, 1564
MSR_DRAM_POWER_INFO
DRAM RAPL Parameters (R/W)
Package
See Section 15.10.5, “DRAM RAPL Domain.”
Register Address: 620H, 1568
MSR_UNCORE_RATIO_LIMIT
Uncore Ratio Limit (R/W)
Package
Out of reset, the min_ratio and max_ratio fields represent the widest possible range of uncore frequencies. Writing
to these fields allows software to control the minimum and the maximum frequency that hardware will select.
63:15
Reserved.
14:8
MIN_RATIO
Writing to this field controls the minimum possible ratio of the LLC/Ring.
7
Reserved.
6:0
MAX_RATIO
This field is used to limit the max ratio of the LLC/Ring.
Register Address: 639H, 1593
MSR_PP0_ENERGY_STATUS
Reserved (R/O)
Package
Reads return 0.
Register Address: 690H, 1680
MSR_CORE_PERF_LIMIT_REASONS
Indicator of Frequency Clipping in Processor Cores (R/W)
Package
(Frequency refers to processor core frequency.)
0
PROCHOT Status (R0)
When set, processor core frequency is reduced below the operating
system request due to assertion of external PROCHOT.
1
Thermal Status (R0)
When set, frequency is reduced below the operating system request due
to a thermal event.
2
Power Budget Management Status (R0)
When set, frequency is reduced below the operating system request due
to PBM limit.
2-314 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family
Based on Broadwell Microarchitecture (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
3
Platform Configuration Services Status (R0)
When set, frequency is reduced below the operating system request due
to PCS limit.
4
Reserved.
5
Autonomous Utilization-Based Frequency Control Status (R0)
When set, frequency is reduced below the operating system request
because the processor has detected that utilization is low.
6
VR Therm Alert Status (R0)
When set, frequency is reduced below the operating system request due
to a thermal alert from the Voltage Regulator.
7
Reserved.
8
Electrical Design Point Status (R0)
When set, frequency is reduced below the operating system request due
to electrical design point constraints (e.g., maximum electrical current
consumption).
9
Reserved.
10
Multi-Core Turbo Status (R0)
When set, frequency is reduced below the operating system request due
to Multi-Core Turbo limits.
12:11
Reserved.
13
Core Frequency P1 Status (R0)
When set, frequency is reduced below max non-turbo P1.
14
Core Max N-Core Turbo Frequency Limiting Status (R0)
When set, frequency is reduced below max n-core turbo frequency.
15
Core Frequency Limiting Status (R0)
When set, frequency is reduced below the operating system request.
16
PROCHOT Log
When set, indicates that the PROCHOT Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
17
Thermal Log
When set, indicates that the Thermal Status bit has asserted since the log
bit was last cleared.
This log bit will remain set until cleared by software writing 0.
18
Power Budget Management Log
When set, indicates that the PBM Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software writing 0.
19
Platform Configuration Services Log
When set, indicates that the PCS Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software writing 0.
Vol. 4
2-315
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family
Based on Broadwell Microarchitecture (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
20
Reserved.
21
Autonomous Utilization-Based Frequency Control Log
When set, indicates that the AUBFC Status bit has asserted since the log
bit was last cleared.
This log bit will remain set until cleared by software writing 0.
22
VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
23
Reserved.
24
Electrical Design Point Log
When set, indicates that the EDP Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software writing 0.
25
Reserved.
26
Multi-Core Turbo Log
When set, indicates that the Multi-Core Turbo Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
28:27
Reserved.
29
Core Frequency P1 Log
When set, indicates that the Core Frequency P1 Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
30
Core Max N-Core Turbo Frequency Limiting Log
When set, indicates that the Core Max n-core Turbo Frequency Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
31
Core Frequency Limiting Log
When set, indicates that the Core Frequency Limiting Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
63:32
Reserved.
Register Address: 770H, 1904
IA32_PM_ENABLE
See Section 15.4.2, “Enabling HWP.”
Package
Register Address: 771H, 1905
IA32_HWP_CAPABILITIES
See Section 15.4.3, “HWP Performance Range and Dynamic Capabilities.”
Thread
Register Address: 774H, 1908
IA32_HWP_REQUEST
See Section 15.4.4, “Managing HWP.”
Thread
7:0
Minimum Performance (R/W)
15:8
Maximum Performance (R/W)
2-316 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family
Based on Broadwell Microarchitecture (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
23:16
Desired Performance (R/W)
63:24
Reserved.
Register Address: 777H, 1911
IA32_HWP_STATUS
See Section 15.4.5, “HWP Feedback.”
Thread
1:0
Reserved.
2
Excursion to Minimum (R/O)
63:3
Reserved.
Register Address: C8DH, 3213
IA32_QM_EVTSEL
Monitoring Event Select Register (R/W)
Thread
If CPUID.(EAX=07H, ECX=0):EBX.RDT-M[bit 12] = 1.
7:0
EventID (R/W)
Event encoding:
0x00: No monitoring.
0x01: L3 occupancy monitoring.
0x02: Total memory bandwidth monitoring.
0x03: Local memory bandwidth monitoring.
All other encoding reserved.
31:8
Reserved.
41:32
RMID (R/W)
63:42
Reserved.
Register Address: C8FH, 3215
IA32_PQR_ASSOC
Resource Association Register (R/W)
Thread
9:0
RMID
31:10
Reserved.
51:32
COS (R/W)
63: 52
Reserved.
Register Address: C90H, 3216
IA32_L3_QOS_MASK_0
L3 Class Of Service Mask - COS 0 (R/W)
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=0.
0:19
CBM: Bit vector of available L3 ways for COS 0 enforcement.
63:20
Reserved.
Register Address: C91H, 3217
IA32_L3_QOS_MASK_1
L3 Class Of Service Mask - COS 1 (R/W)
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=1.
0:19
CBM: Bit vector of available L3 ways for COS 1 enforcement.
63:20
Reserved.
Register Address: C92H, 3218
IA32_L3_QOS_MASK_2
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2-317
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family
Based on Broadwell Microarchitecture (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
L3 Class Of Service Mask - COS 2 (R/W)
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=2.
0:19
CBM: Bit vector of available L3 ways for COS 2 enforcement.
63:20
Reserved.
Register Address: C93H, 3219
IA32_L3_QOS_MASK_3
L3 Class Of Service Mask - COS 3 (R/W)
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=3.
0:19
CBM: Bit vector of available L3 ways for COS 3 enforcement.
63:20
Reserved.
Register Address: C94H, 3220
IA32_L3_QOS_MASK_4
L3 Class Of Service Mask - COS 4 (R/W)
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=4.
0:19
CBM: Bit vector of available L3 ways for COS 4 enforcement.
63:20
Reserved.
Register Address: C95H, 3221
IA32_L3_QOS_MASK_5
L3 Class Of Service Mask - COS 5 (R/W)
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=5.
0:19
CBM: Bit vector of available L3 ways for COS 5 enforcement.
63:20
Reserved.
Register Address: C96H, 3222
IA32_L3_QOS_MASK_6
L3 Class Of Service Mask - COS 6 (R/W)
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=6.
0:19
CBM: Bit vector of available L3 ways for COS 6 enforcement.
63:20
Reserved.
Register Address: C97H, 3223
IA32_L3_QOS_MASK_7
L3 Class Of Service Mask - COS 7 (R/W)
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=7.
0:19
CBM: Bit vector of available L3 ways for COS 7 enforcement.
63:20
Reserved.
Register Address: C98H, 3224
IA32_L3_QOS_MASK_8
L3 Class Of Service Mask - COS 8 (R/W)
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=8.
0:19
CBM: Bit vector of available L3 ways for COS 8 enforcement.
63:20
Reserved.
Register Address: C99H, 3225
IA32_L3_QOS_MASK_9
L3 Class Of Service Mask - COS 9 (R/W)
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=9.
0:19
CBM: Bit vector of available L3 ways for COS 9 enforcement.
2-318 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family
Based on Broadwell Microarchitecture (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
63:20
Reserved.
Register Address: C9AH, 3226
IA32_L3_QOS_MASK_10
L3 Class Of Service Mask - COS 10 (R/W)
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=10.
0:19
CBM: Bit vector of available L3 ways for COS 10 enforcement.
63:20
Reserved.
Register Address: C9BH, 3227
IA32_L3_QOS_MASK_11
L3 Class Of Service Mask - COS 11 (R/W)
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=11.
0:19
CBM: Bit vector of available L3 ways for COS 11 enforcement.
63:20
Reserved.
Register Address: C9CH, 3228
IA32_L3_QOS_MASK_12
L3 Class Of Service Mask - COS 12 (R/W)
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=12.
0:19
CBM: Bit vector of available L3 ways for COS 12 enforcement.
63:20
Reserved.
Register Address: C9DH, 3229
IA32_L3_QOS_MASK_13
L3 Class Of Service Mask - COS 13 (R/W)
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=13.
0:19
CBM: Bit vector of available L3 ways for COS 13 enforcement.
63:20
Reserved.
Register Address: C9EH, 3230
IA32_L3_QOS_MASK_14
L3 Class Of Service Mask - COS 14 (R/W)
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=14.
0:19
CBM: Bit vector of available L3 ways for COS 14 enforcement.
63:20
Reserved.
Register Address: C9FH, 3231
IA32_L3_QOS_MASK_15
L3 Class Of Service Mask - COS 15 (R/W)
Package
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=15.
0:19
CBM: Bit vector of available L3 ways for COS 15 enforcement.
63:20
Reserved.
2.16.1 Additional MSRs Supported in the Intel® Xeon® Processor D Product Family
The MSRs listed in Table 2-37 are available to Intel® Xeon® Processor D Product Family (CPUID Signature
DisplayFamily_DisplayModel value of 06_56H). The Intel® Xeon® processor D product family is based on Broadwell
microarchitecture and supports the MSR interfaces listed in Table 2-20, Table 2-29, Table 2-34, Table 2-36, and
Table 2-37.
Vol. 4
2-319
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-37. Additional MSRs Supported by Intel® Xeon® Processor D with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_56H
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 1ACH, 428
MSR_TURBO_RATIO_LIMIT3
Config Ratio Limit of Turbo Mode
Package
R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1.
62:0
Reserved.
Package
63
Semaphore for Turbo Ratio Limit Configuration
Package
If 1, the processor uses override configuration1 specified in
MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1.
If 0, the processor uses factory-set configuration (Default).
Register Address: 286H, 646
IA32_MC6_CTL2
See Table 2-2.
Package
Register Address: 287H, 647
IA32_MC7_CTL2
See Table 2-2.
Package
Register Address: 289H, 649
IA32_MC9_CTL2
See Table 2-2.
Package
Register Address: 28AH, 650
IA32_MC10_CTL2
See Table 2-2.
Package
Register Address: 291H, 657
IA32_MC17_CTL2
See Table 2-2.
Package
Register Address: 292H, 658
IA32_MC18_CTL2
See Table 2-2.
Package
Register Address: 293H, 659
IA32_MC19_CTL2
See Table 2-2.
Package
Register Address: 418H, 1048
IA32_MC6_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC6 reports MC errors from the integrated I/O module.
Register Address: 419H, 1049
IA32_MC6_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC6 reports MC errors from the integrated I/O module.
Register Address: 41AH, 1050
IA32_MC6_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC6 reports MC errors from the integrated I/O module.
Register Address: 41BH, 1051
IA32_MC6_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC6 reports MC errors from the integrated I/O module.
Register Address: 41CH, 1052
IA32_MC7_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC7 reports MC errors from the home agent HA 0.
2-320 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-37. Additional MSRs Supported by Intel® Xeon® Processor D with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_56H
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 41DH, 1053
IA32_MC7_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC7 reports MC errors from the home agent HA 0.
Register Address: 41EH, 1054
IA32_MC7_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC7 reports MC errors from the home agent HA 0.
Register Address: 41FH, 1055
IA32_MC7_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC7 reports MC errors from the home agent HA 0.
Register Address: 424H, 1060
IA32_MC9_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 10 report MC errors from each channel of the integrated memory controllers.
Register Address: 425H, 1061
IA32_MC9_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 10 report MC errors from each channel of the integrated memory controllers.
Register Address: 426H, 1062
IA32_MC9_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 10 report MC errors from each channel of the integrated memory controllers.
Register Address: 427H, 1063
IA32_MC9_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 10 report MC errors from each channel of the integrated memory controllers.
Register Address: 428H, 1064
IA32_MC10_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 10 report MC errors from each channel of the integrated memory controllers.
Register Address: 429H, 1065
IA32_MC10_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 10 report MC errors from each channel of the integrated memory controllers.
Register Address: 42AH, 1066
IA32_MC10_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 10 report MC errors from each channel of the integrated memory controllers.
Register Address: 42BH, 1067
IA32_MC10_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 10 report MC errors from each channel of the integrated memory controllers.
Register Address: 444H, 1092
IA32_MC17_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Register Address: 445H, 1093
IA32_MC17_STATUS
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-37. Additional MSRs Supported by Intel® Xeon® Processor D with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_56H
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Register Address: 446H, 1094
IA32_MC17_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Register Address: 447H, 1095
IA32_MC17_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Register Address: 448H, 1096
IA32_MC18_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
Register Address: 449H, 1097
IA32_MC18_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
Register Address: 44AH, 1098
IA32_MC18_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
Register Address: 44BH, 1099
IA32_MC18_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
Register Address: 44CH, 1100
IA32_MC19_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
Register Address: 44DH, 1101
IA32_MC19_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
Register Address: 44EH, 1102
IA32_MC19_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
Register Address: 44FH, 1103
IA32_MC19_MISC
2-322 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-37. Additional MSRs Supported by Intel® Xeon® Processor D with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_56H
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
See Table 2-20, Table 2-29, Table 2-34, and Table 2-36 for other MSR definitions applicable to processors with a CPUID Signature
DisplayFamily_DisplayModel value of 06_56H.
NOTES:
1. An override configuration lower than the factory-set configuration is always supported. An override configuration higher than the
factory-set configuration is dependent on features specific to the processor and the platform.
2.16.2 Additional MSRs Supported in Intel® Xeon® Processors E5 v4 and E7 v4 Families
The MSRs listed in Table 2-37 are available to the Intel® Xeon® Processor E5 v4 and E7 v4 Families (CPUID
Signature DisplayFamily_DisplayModel value of 06_4FH). The Intel® Xeon® processor E5 v4 family is based on
Broadwell microarchitecture and supports the MSR interfaces listed in Table 2-20, Table 2-21, Table 2-29, Table
2-34, Table 2-36, and Table 2-38.
Table 2-38. Additional MSRs Supported by Intel® Xeon® Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_4FH
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 1ACH, 428
MSR_TURBO_RATIO_LIMIT3
Config Ratio Limit of Turbo Mode
Package
R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1.
62:0
Reserved.
Package
63
Semaphore for Turbo Ratio Limit Configuration
Package
If 1, the processor uses override configuration1 specified in
MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1, and
MSR_TURBO_RATIO_LIMIT2.
If 0, the processor uses factory-set configuration (Default).
Register Address: 285H, 645
IA32_MC5_CTL2
See Table 2-2.
Package
Register Address: 286H, 646
IA32_MC6_CTL2
See Table 2-2.
Package
Register Address: 287H, 647
IA32_MC7_CTL2
See Table 2-2.
Package
Register Address: 288H, 648
IA32_MC8_CTL2
See Table 2-2.
Package
Register Address: 289H, 649
IA32_MC9_CTL2
See Table 2-2.
Package
Register Address: 28AH, 650
IA32_MC10_CTL2
See Table 2-2.
Package
Vol. 4
2-323
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-38. Additional MSRs Supported by Intel® Xeon® Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_4FH
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 28BH, 651
IA32_MC11_CTL2
See Table 2-2.
Package
Register Address: 28CH, 652
IA32_MC12_CTL2
See Table 2-2.
Package
Register Address: 28DH, 653
IA32_MC13_CTL2
See Table 2-2.
Package
Register Address: 28EH, 654
IA32_MC14_CTL2
See Table 2-2.
Package
Register Address: 28FH, 655
IA32_MC15_CTL2
See Table 2-2.
Package
Register Address: 290H, 656
IA32_MC16_CTL2
See Table 2-2.
Package
Register Address: 291H, 657
IA32_MC17_CTL2
See Table 2-2.
Package
Register Address: 292H, 658
IA32_MC18_CTL2
See Table 2-2.
Package
Register Address: 293H, 659
IA32_MC19_CTL2
See Table 2-2.
Package
Register Address: 294H, 660
IA32_MC20_CTL2
See Table 2-2.
Package
Register Address: 295H, 661
IA32_MC21_CTL2
See Table 2-2.
Package
Register Address: 414H, 1044
IA32_MC5_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC5 reports MC errors from the Intel QPI 0 module.
Register Address: 415H, 1045
IA32_MC5_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC5 reports MC errors from the Intel QPI 0 module.
Register Address: 416H, 1046
IA32_MC5_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC5 reports MC errors from the Intel QPI 0 module.
Register Address: 417H, 1047
IA32_MC5_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC5 reports MC errors from the Intel QPI 0 module.
Register Address: 418H, 1048
IA32_MC6_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC6 reports MC errors from the integrated I/O module.
2-324 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-38. Additional MSRs Supported by Intel® Xeon® Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_4FH
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 419H, 1049
IA32_MC6_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC6 reports MC errors from the integrated I/O module.
Register Address: 41AH, 1050
IA32_MC6_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC6 reports MC errors from the integrated I/O module.
Register Address: 41BH, 1051
IA32_MC6_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC6 reports MC errors from the integrated I/O module.
Register Address: 41CH, 1052
IA32_MC7_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC7 reports MC errors from the home agent HA 0.
Register Address: 41DH, 1053
IA32_MC7_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC7 reports MC errors from the home agent HA 0.
Register Address: 41EH, 1054
IA32_MC7_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC7 reports MC errors from the home agent HA 0.
Register Address: 41FH, 1055
IA32_MC7_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC7 reports MC errors from the home agent HA 0.
Register Address: 420H, 1056
IA32_MC8_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC8 reports MC errors from the home agent HA 1.
Register Address: 421H, 1057
IA32_MC8_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC8 reports MC errors from the home agent HA 1.
Register Address: 422H, 1058
IA32_MC8_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC8 reports MC errors from the home agent HA 1.
Register Address: 423H, 1059
IA32_MC8_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC8 reports MC errors from the home agent HA 1.
Register Address: 424H, 1060
IA32_MC9_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 425H, 1061
IA32_MC9_STATUS
Vol. 4
2-325
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-38. Additional MSRs Supported by Intel® Xeon® Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_4FH
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 426H, 1062
IA32_MC9_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 427H, 1063
IA32_MC9_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 428H, 1064
IA32_MC10_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 429H, 1065
IA32_MC10_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 42AH, 1066
IA32_MC10_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 42BH, 1067
IA32_MC10_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 42CH, 1068
IA32_MC11_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 42DH, 1069
IA32_MC11_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 42EH, 1070
IA32_MC11_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 42FH, 1071
IA32_MC11_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 430H, 1072
IA32_MC12_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 431H, 1073
IA32_MC12_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
2-326 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-38. Additional MSRs Supported by Intel® Xeon® Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_4FH
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 432H, 1074
IA32_MC12_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 433H, 1075
IA32_MC12_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 434H, 1076
IA32_MC13_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 435H, 1077
IA32_MC13_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 436H, 1078
IA32_MC13_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 437H, 1079
IA32_MC13_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 438H, 1080
IA32_MC14_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 439H, 1081
IA32_MC14_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 43AH, 1082
IA32_MC14_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 43BH, 1083
IA32_MC14_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 43CH, 1084
IA32_MC15_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 43DH, 1085
IA32_MC15_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 43EH, 1086
IA32_MC15_ADDR
Vol. 4
2-327
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-38. Additional MSRs Supported by Intel® Xeon® Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_4FH
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 43FH, 1087
IA32_MC15_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 440H, 1088
IA32_MC16_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 441H, 1089
IA32_MC16_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 442H, 1090
IA32_MC16_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 443H, 1091
IA32_MC16_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Register Address: 444H, 1092
IA32_MC17_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Register Address: 445H, 1093
IA32_MC17_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Register Address: 446H, 1094
IA32_MC17_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Register Address: 447H, 1095
IA32_MC17_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Register Address: 448H, 1096
IA32_MC18_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
Register Address: 449H, 1097
IA32_MC18_STATUS
2-328 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-38. Additional MSRs Supported by Intel® Xeon® Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_4FH
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
Register Address: 44AH, 1098
IA32_MC18_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
Register Address: 44BH, 1099
IA32_MC18_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
Register Address: 44CH, 1100
IA32_MC19_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
Register Address: 44DH, 1101
IA32_MC19_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
Register Address: 44EH, 1102
IA32_MC19_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
Register Address: 44FH, 1103
IA32_MC19_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
Register Address: 450H, 1104
IA32_MC20_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC20 reports MC errors from the Intel QPI 1 module.
Register Address: 451H, 1105
IA32_MC20_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC20 reports MC errors from the Intel QPI 1 module.
Register Address: 452H, 1106
IA32_MC20_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC20 reports MC errors from the Intel QPI 1 module.
Register Address: 453H, 1107
IA32_MC20_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC20 reports MC errors from the Intel QPI 1 module.
Register Address: 454H, 1108
IA32_MC21_CTL
Vol. 4
2-329
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-38. Additional MSRs Supported by Intel® Xeon® Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_4FH
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC21 reports MC errors from the Intel QPI 2 module.
Register Address: 455H, 1109
IA32_MC21_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC21 reports MC errors from the Intel QPI 2 module.
Register Address: 456H, 1110
IA32_MC21_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC21 reports MC errors from the Intel QPI 2 module.
Register Address: 457H, 1111
IA32_MC21_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC21 reports MC errors from the Intel QPI 2 module.
Register Address: C81H, 3201
IA32_L3_QOS_CFG
Cache Allocation Technology Configuration (R/W)
Package
0
CAT Enable. Set 1 to enable Cache Allocation Technology.
63:1
Reserved.
See Table 2-20, Table 2-21, Table 2-29, and Table 2-30 for other MSR definitions applicable to processors with a CPUID Signature
DisplayFamily_DisplayModel value of 06_45H.
NOTES:
1. An override configuration lower than the factory-set configuration is always supported. An override configuration higher than the fac-
tory-set configuration is dependent on features specific to the processor and the platform.
2.17
MSRS IN THE 6TH-13TH GENERATION INTEL® CORE™ PROCESSORS,
1ST-5TH GENERATION INTEL® XEON® SCALABLE PROCESSOR FAMILIES,
INTEL® CORE™ ULTRA 7 PROCESSORS, 8TH GENERATION INTEL® CORE™ I3
PROCESSORS, AND INTEL® XEON® E PROCESSORS
6th generation Intel® Core™ processors are based on Skylake microarchitecture and have a CPUID Signature
DisplayFamily_DisplayModel value of 06_4EH or 06_5EH.
The Intel® Xeon® Scalable Processor Family based on the Skylake microarchitecture, the 2nd generation Intel®
Xeon® Scalable Processor Family based on the Cascade Lake product, and the 3rd generation Intel® Xeon® Scal-
able Processor Family based on the Cooper Lake product all have a CPUID Signature DisplayFamily_DisplayModel
value of 06_55H.
7th generation Intel® Core™ processors are based on the Kaby Lake microarchitecture, 8th generation and 9th
generation Intel® Core™ processors, and Intel® Xeon® E processors are based on Coffee Lake microarchitecture;
these processors have a CPUID Signature DisplayFamily_DisplayModel value of 06_8EH or 06_9EH.
8th generation Intel® Core™ i3 processors are based on Cannon Lake microarchitecture and have a CPUID Signa-
ture DisplayFamily_DisplayModel value of 06_66H.
10th generation Intel® Core™ processors are based on Comet Lake microarchitecture (with a CPUID Signature
DisplayFamily_DisplayModel value of 06_A5H or 06_A6H) and Ice Lake microarchitecture (with a CPUID Signature
DisplayFamily_DisplayModel value of 06_7DH or 06_7EH).
2-330 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
11th generation Intel® Core™ processors are based on Tiger Lake microarchitecture and have a CPUID Signature
DisplayFamily_DisplayModel value of 06_8CH or 06_8DH.
The 3rd generation Intel® Xeon® Scalable Processor Family is based on Ice Lake microarchitecture and has a
CPUID Signature DisplayFamily_DisplayModel value of 06_6AH or 06_6CH.
12th generation Intel® Core™ processors supporting the Alder Lake performance hybrid architecture have a CPUID
Signature DisplayFamily_DisplayModel value of 06_97H or 06_9AH.
13th generation Intel® Core™ processors supporting the Raptor Lake performance hybrid architecture have a
CPUID Signature DisplayFamily_DisplayModel value of 06_BAH, 06_B7H, or 06_BFH.
The 4th generation Intel® Xeon® Scalable Processor Family is based on Sapphire Rapids microarchitecture and has
a CPUID Signature DisplayFamily_DisplayModel value of 06_8FH.
The 5th generation Intel® Xeon® Scalable Processor Family is based on Emerald Rapids microarchitecture and has
a CPUID Signature DisplayFamily_DisplayModel value of 06_CFH.
The Intel® Core™ Ultra 7 processor is based on Meteor Lake hybrid architecture and has a CPUID Signature
DisplayFamily_DisplayModel value of 06_AAH.
These processors support the MSR interfaces listed in Table 2-20, Table 2-21, Table 2-25, Table 2-29, Table 2-35,
and Table 2-391. For an MSR listed in Table 2-39 that also appears in the model-specific tables of prior generations,
Table 2-39 supersede prior generation tables.
Tables 2-40 through 2-52 list additional supported MSR interfaces for specific processors; see each table for addi-
tional details.
The notation of “Platform” in the Scope column (with respect to MSR_PLATFORM_ENERGY_COUNTER and
MSR_PLATFORM_POWER_LIMIT) is limited to the power-delivery domain and the specifics of the power delivery
integration may vary by platform vendor’s implementation.
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors, 1st-5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 3AH, 58
IA32_FEATURE_CONTROL
Control Features in Intel 64 Processor (R/W)
Thread
See Table 2-2.
Register Address: FEH, 254
IA32_MTRRCAP
MTRR Capability (R/O, Architectural)
Thread
See Table 2-2
Register Address: 19CH, 412
IA32_THERM_STATUS
Thermal Monitor Status (R/W)
Core
See Table 2-2.
0
Thermal Status (R/O)
See Table 2-2.
1
Thermal Status Log (R/WC0)
See Table 2-2.
2
PROTCHOT # or FORCEPR# Status (R/O)
See Table 2-2.
1. MSRs at the following addresses are not supported in the 12th generation Intel Core processor E-core: 3F7H. MSRs at the following
addresses are not supported in the 12th generation Intel Core processor E-core or P-core: 652H, 653H, 655H, 656H, DB0H, DB1H,
DB2H, and D90H.
Vol. 4
2-331
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors, 1st-5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
3
PROTCHOT # or FORCEPR# Log (R/WC0)
See Table 2-2.
4
Critical Temperature Status (R/O)
See Table 2-2.
5
Critical Temperature Status Log (R/WC0)
See Table 2-2.
6
Thermal threshold #1 Status (R/O)
See Table 2-2.
7
Thermal threshold #1 Log (R/WC0)
See Table 2-2.
8
Thermal Threshold #2 Status (R/O)
See Table 2-2.
9
Thermal Threshold #2 Log (R/WC0)
See Table 2-2.
10
Power Limitation Status (R/O)
See Table 2-2.
11
Power Limitation Log (R/WC0)
See Table 2-2.
12
Current Limit Status (R/O)
See Table 2-2.
13
Current Limit Log (R/WC0)
See Table 2-2.
14
Cross Domain Limit Status (R/O)
See Table 2-2.
15
Cross Domain Limit Log (R/WC0)
See Table 2-2.
22:16
Digital Readout (R/O)
See Table 2-2.
26:23
Reserved.
30:27
Resolution in Degrees Celsius (R/O)
See Table 2-2.
31
Reading Valid (R/O)
See Table 2-2.
63:32
Reserved.
Register Address: 1ADH, 429
MSR_TURBO_RATIO_LIMIT
Maximum Ratio Limit of Turbo Mode
Package
R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1
2-332 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors, 1st-5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
7:0
Maximum Ratio Limit for 1C
Package
Maximum turbo ratio limit of 1 core active.
15:8
Maximum Ratio Limit for 2C
Package
Maximum turbo ratio limit of 2 core active.
23:16
Maximum Ratio Limit for 3C
Package
Maximum turbo ratio limit of 3 core active.
31:24
Maximum Ratio Limit for 4C
Package
Maximum turbo ratio limit of 4 core active.
63:32
Reserved.
Register Address: 1C9H, 457
MSR_LASTBRANCH_TOS
Last Branch Record Stack TOS (R/W)
Thread
Contains an index (bits 0-4) that points to the MSR containing the most recent branch record.
Register Address: 1FCH, 508
MSR_POWER_CTL
Power Control Register
Core
0
Reserved.
1
C1E Enable (R/W)
Package
When set to ‘1’, will enable the CPU to switch to the Minimum Enhanced
Intel SpeedStep Technology operating point when all execution cores enter
MWAIT (C1).
18:2
Reserved.
19
Disable Energy Efficiency Optimization (R/W)
Setting this bit disables the P-States energy efficiency optimization.
Default value is 0. Disable/enable the energy efficiency optimization in P-
State legacy mode (when IA32_PM_ENABLE[HWP_ENABLE] = 0), has an
effect only in the turbo range or into PERF_MIN_CTL value if it is not zero
set. In HWP mode (IA32_PM_ENABLE[HWP_ENABLE] == 1), has an effect
between the OS desired or OS maximize to the OS minimize performance
setting.
20
Disable Race to Halt Optimization (R/W)
Setting this bit disables the Race to Halt optimization and avoids this
optimization limitation to execute below the most efficient frequency ratio.
Default value is 0 for processors that support Race to Halt optimization.
63:21
Reserved.
Register Address: 300H, 768
MSR_SGXOWNEREPOCH0
Lower 64 Bit CR_SGXOWNEREPOCH (W)
Package
Writes do not update CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in the package.
63:0
Lower 64 bits of an 128-bit external entropy value for key derivation of an
enclave.
Register Address: 301H, 769
MSR_SGXOWNEREPOCH1
Vol. 4
2-333
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors, 1st-5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Upper 64 Bit CR_SGXOWNEREPOCH (W)
Package
Writes do not update CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in the package.
63:0
Upper 64 bits of an 128-bit external entropy value for key derivation of an
enclave.
Register Address: 38EH, 910
IA32_PERF_GLOBAL_STATUS
See Table 2-2 and Section 20.2.4, “Architectural Performance Monitoring Version 4.”
0
Ovf_PMC0
Thread
1
Ovf_PMC1
Thread
2
Ovf_PMC2
Thread
3
Ovf_PMC3
Thread
4
Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4)
Thread
5
Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5)
Thread
6
Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6)
Thread
7
Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7)
Thread
31:8
Reserved.
32
Ovf_FixedCtr0
Thread
33
Ovf_FixedCtr1
Thread
34
Ovf_FixedCtr2
Thread
54:35
Reserved
55
Trace_ToPA_PMI
Thread
57:56
Reserved.
58
LBR_Frz
Thread
59
CTR_Frz
Thread
60
ASCI
Thread
61
Ovf_Uncore
Thread
62
Ovf_BufDSSAVE
Thread
63
CondChgd
Thread
Register Address: 390H, 912
IA32_PERF_GLOBAL_STATUS_RESET
See Table 2-2 and Section 20.2.4, “Architectural Performance Monitoring Version 4.”
0
Set 1 to clear Ovf_PMC0.
Thread
1
Set 1 to clear Ovf_PMC1.
Thread
2
Set 1 to clear Ovf_PMC2.
Thread
3
Set 1 to clear Ovf_PMC3.
Thread
4
Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
Thread
5
Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
Thread
6
Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
Thread
2-334 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors, 1st-5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
7
Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
Thread
31:8
Reserved.
32
Set 1 to clear Ovf_FixedCtr0.
Thread
33
Set 1 to clear Ovf_FixedCtr1.
Thread
34
Set 1 to clear Ovf_FixedCtr2.
Thread
54:35
Reserved.
55
Set 1 to clear Trace_ToPA_PMI.
Thread
57:56
Reserved.
58
Set 1 to clear LBR_Frz.
Thread
59
Set 1 to clear CTR_Frz.
Thread
60
Set 1 to clear ASCI.
Thread
61
Set 1 to clear Ovf_Uncore.
Thread
62
Set 1 to clear Ovf_BufDSSAVE.
Thread
63
Set 1 to clear CondChgd.
Thread
Register Address: 391H, 913
IA32_PERF_GLOBAL_STATUS_SET
See Table 2-2 and Section 20.2.4, “Architectural Performance Monitoring Version 4.”
0
Set 1 to cause Ovf_PMC0 = 1.
Thread
1
Set 1 to cause Ovf_PMC1 = 1.
Thread
2
Set 1 to cause Ovf_PMC2 = 1.
Thread
3
Set 1 to cause Ovf_PMC3 = 1.
Thread
4
Set 1 to cause Ovf_PMC4=1 (if CPUID.0AH:EAX[15:8] > 4).
Thread
5
Set 1 to cause Ovf_PMC5=1 (if CPUID.0AH:EAX[15:8] > 5).
Thread
6
Set 1 to cause Ovf_PMC6=1 (if CPUID.0AH:EAX[15:8] > 6).
Thread
7
Set 1 to cause Ovf_PMC7=1 (if CPUID.0AH:EAX[15:8] > 7).
Thread
31:8
Reserved.
32
Set 1 to cause Ovf_FixedCtr0 = 1.
Thread
33
Set 1 to cause Ovf_FixedCtr1 = 1.
Thread
34
Set 1 to cause Ovf_FixedCtr2 = 1.
Thread
54:35
Reserved.
55
Set 1 to cause Trace_ToPA_PMI = 1.
Thread
57:56
Reserved.
58
Set 1 to cause LBR_Frz = 1.
Thread
59
Set 1 to cause CTR_Frz = 1.
Thread
60
Set 1 to cause ASCI = 1.
Thread
61
Set 1 to cause Ovf_Uncore.
Thread
62
Set 1 to cause Ovf_BufDSSAVE.
Thread
Vol. 4
2-335
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors, 1st-5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
63
Reserved.
Register Address: 392H, 914
IA32_PERF_GLOBAL_INUSE
See Table 2-2.
Thread
Register Address: 3F7H, 1015
MSR_PEBS_FRONTEND
FrontEnd Precise Event Condition Select (R/W)
Thread
2:0
Event Code Select
3
Reserved
4
Event Code Select High
7:5
Reserved.
19:8
IDQ_Bubble_Length Specifier
22:20
IDQ_Bubble_Width Specifier
63:23
Reserved.
Register Address: 500H, 1280
IA32_SGX_SVN_STATUS
Status and SVN Threshold of SGX Support for ACM (R/O)
Thread
0
Lock
See Section 39.11.3, “Interactions with Authenticated Code Modules
(ACMs).”
15:1
Reserved.
23:16
SGX_SVN_SINIT
See Section 39.11.3, “Interactions with Authenticated Code Modules
(ACMs).”
63:24
Reserved.
Register Address: 560H, 1376
IA32_RTIT_OUTPUT_BASE
Trace Output Base Register (R/W)
Thread
See Table 2-2.
Register Address: 561H, 1377
IA32_RTIT_OUTPUT_MASK_PTRS
Trace Output Mask Pointers Register (R/W)
Thread
See Table 2-2.
Register Address: 570H, 1392
IA32_RTIT_CTL
Trace Control Register (R/W)
Thread
0
TraceEn
1
CYCEn
2
OS
3
User
6:4
Reserved, must be zero.
7
CR3Filter
2-336 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors, 1st-5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
8
ToPA
Writing 0 will #GP if also setting TraceEn.
9
MTCEn
10
TSCEn
11
DisRETC
12
Reserved, must be zero.
13
BranchEn
17:14
MTCFreq
18
Reserved, must be zero.
22:19
CycThresh
23
Reserved, must be zero.
27:24
PSBFreq
31:28
Reserved, must be zero.
35:32
ADDR0_CFG
39:36
ADDR1_CFG
63:40
Reserved, must be zero.
Register Address: 571H, 1393
IA32_RTIT_STATUS
Tracing Status Register (R/W)
Thread
0
FilterEn, writes ignored.
1
ContexEn, writes ignored.
2
TriggerEn, writes ignored.
3
Reserved
4
Error (R/W)
5
Stopped
31:6
Reserved, must be zero.
48:32
PacketByteCnt
63:49
Reserved, must be zero.
Register Address: 572H, 1394
IA32_RTIT_CR3_MATCH
Trace Filter CR3 Match Register (R/W)
Thread
4:0
Reserved
63:5
CR3[63:5] value to match
Register Address: 580H, 1408
IA32_RTIT_ADDR0_A
Region 0 Start Address (R/W)
Thread
63:0
See Table 2-2.
Register Address: 581H, 1409
IA32_RTIT_ADDR0_B
Region 0 End Address (R/W)
Thread
Vol. 4
2-337
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors, 1st-5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
63:0
See Table 2-2.
Register Address: 582H, 1410
IA32_RTIT_ADDR1_A
Region 1 Start Address (R/W)
Thread
63:0
See Table 2-2.
Register Address: 583H, 1411
IA32_RTIT_ADDR1_B
Region 1 End Address (R/W)
Thread
63:0
See Table 2-2.
Register Address: 639H, 1593
MSR_PP0_ENERGY_STATUS
PP0 Energy Status (R/O)
Package
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
Register Address: 64DH, 1613
MSR_PLATFORM_ENERGY_COUNTER
Platform Energy Counter (R/O)
Platform
This MSR is valid only if both platform vendor hardware implementation and BIOS enablement support it. This MSR
will read 0 if not valid.
31:0
Total energy consumed by all devices in the platform that receive power
from integrated power delivery mechanism, included platform devices are
processor cores, SOC, memory, add-on or peripheral devices that get
powered directly from the platform power delivery means. The energy
units are specified in the MSR_RAPL_POWER_UNIT.Enery_Status_Unit.
63:32
Reserved.
Register Address: 64EH, 1614
MSR_PPERF
Productive Performance Count (R/O)
Thread
63:0
Hardware’s view of workload scalability. See Section 15.4.5.1.
Register Address: 64FH, 1615
MSR_CORE_PERF_LIMIT_REASONS
Indicator of Frequency Clipping in Processor Cores (R/W)
Package
(Frequency refers to processor core frequency.)
0
PROCHOT Status (R0)
When set, frequency is reduced below the operating system request due
to assertion of external PROCHOT.
1
Thermal Status (R0)
When set, frequency is reduced below the operating system request due
to a thermal event.
3:2
Reserved.
4
Residency State Regulation Status (R0)
When set, frequency is reduced below the operating system request due
to residency state regulation limit.
5
Running Average Thermal Limit Status (R0)
When set, frequency is reduced below the operating system request due
to Running Average Thermal Limit (RATL).
2-338 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors, 1st-5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
6
VR Therm Alert Status (R0)
When set, frequency is reduced below the operating system request due
to a thermal alert from a processor Voltage Regulator (VR).
7
VR Therm Design Current Status (R0)
When set, frequency is reduced below the operating system request due
to VR thermal design current limit.
8
Other Status (R0)
When set, frequency is reduced below the operating system request due
to electrical or other constraints.
9
Reserved.
10
Package/Platform-Level Power Limiting PL1 Status (R0)
When set, frequency is reduced below the operating system request due
to package/platform-level power limiting PL1.
11
Package/Platform-Level PL2 Power Limiting Status (R0)
When set, frequency is reduced below the operating system request due
to package/platform-level power limiting PL2/PL3.
12
Max Turbo Limit Status (R0)
When set, frequency is reduced below the operating system request due
to multi-core turbo limits.
13
Turbo Transition Attenuation Status (R0)
When set, frequency is reduced below the operating system request due
to Turbo transition attenuation. This prevents performance degradation
due to frequent operating ratio changes.
15:14
Reserved.
16
PROCHOT Log
When set, indicates that the PROCHOT Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
17
Thermal Log
When set, indicates that the Thermal Status bit has asserted since the log
bit was last cleared.
This log bit will remain set until cleared by software writing 0.
19:18
Reserved.
20
Residency State Regulation Log
When set, indicates that the Residency State Regulation Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
21
Running Average Thermal Limit Log
When set, indicates that the RATL Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software writing 0.
Vol. 4
2-339
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors, 1st-5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
22
VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
23
VR Thermal Design Current Log
When set, indicates that the VR TDC Status bit has asserted since the log
bit was last cleared.
This log bit will remain set until cleared by software writing 0.
24
Other Log
When set, indicates that the Other Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software writing 0.
25
Reserved.
26
Package/Platform-Level PL1 Power Limiting Log
When set, indicates that the Package or Platform Level PL1 Power Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
27
Package/Platform-Level PL2 Power Limiting Log
When set, indicates that the Package or Platform Level PL2/PL3 Power
Limiting Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
28
Max Turbo Limit Log
When set, indicates that the Max Turbo Limit Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
29
Turbo Transition Attenuation Log
When set, indicates that the Turbo Transition Attenuation Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
63:30
Reserved.
Register Address: 652H, 1618
MSR_PKG_HDC_CONFIG
HDC Configuration (R/W)
Package
2:0
PKG_Cx_Monitor
Configures Package Cx state threshold for
MSR_PKG_HDC_DEEP_RESIDENCY.
63: 3
Reserved.
Register Address: 653H, 1619
MSR_CORE_HDC_RESIDENCY
Core HDC Idle Residency (R/O)
Core
63:0
Core_Cx_Duty_Cycle_Cnt
Register Address: 655H, 1621
MSR_PKG_HDC_SHALLOW_RESIDENCY
2-340 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors, 1st-5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Accumulate the cycles the package was in C2 state and at least one logical processor was in forced idle (R/O)
Package
63:0
Pkg_C2_Duty_Cycle_Cnt
Register Address: 656H, 1622
MSR_PKG_HDC_DEEP_RESIDENCY
Package Cx HDC Idle Residency (R/O)
Package
63:0
Pkg_Cx_Duty_Cycle_Cnt
Register Address: 658H, 1624
MSR_WEIGHTED_CORE_C0
Core-count Weighted C0 Residency (R/O)
Package
63:0
Increment at the same rate as the TSC. The increment each cycle is
weighted by the number of processor cores in the package that reside in
C0. If N cores are simultaneously in C0, then each cycle the counter
increments by N.
Register Address: 659H, 1625
MSR_ANY_CORE_C0
Any Core C0 Residency (R/O)
Package
63:0
Increment at the same rate as the TSC. The increment each cycle is one if
any processor core in the package is in C0.
Register Address: 65AH, 1626
MSR_ANY_GFXE_C0
Any Graphics Engine C0 Residency (R/O)
Package
63:0
Increment at the same rate as the TSC. The increment each cycle is one if
any processor graphic device’s compute engines are in C0.
Register Address: 65BH, 1627
MSR_CORE_GFXE_OVERLAP_C0
Core and Graphics Engine Overlapped C0 Residency (R/O)
Package
63:0
Increment at the same rate as the TSC. The increment each cycle is one if
at least one compute engine of the processor graphics is in C0 and at least
one processor core in the package is also in C0.
Register Address: 65CH, 1628
MSR_PLATFORM_POWER_LIMIT
Platform Power Limit Control (R/W-L)
Platform
Allows platform BIOS to limit power consumption of the platform devices to the specified values. The Long Duration
power consumption is specified via Platform_Power_Limit_1 and Platform_Power_Limit_1_Time. The Short Duration
power consumption limit is specified via the Platform_Power_Limit_2 with duration chosen by the processor.
The processor implements an exponential-weighted algorithm in the placement of the time windows.
14:0
Platform Power Limit #1
Average Power limit value which the platform must not exceed over a time
window as specified by Power_Limit_1_TIME field.
The default value is the Thermal Design Power (TDP) and varies with
product skus. The unit is specified in MSR_RAPLPOWER_UNIT.
15
Enable Platform Power Limit #1
When set, enables the processor to apply control policy such that the
platform power does not exceed Platform Power limit #1 over the time
window specified by Power Limit #1 Time Window.
Vol. 4
2-341
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors, 1st-5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
16
Platform Clamping Limitation #1
When set, allows the processor to go below the OS requested P states in
order to maintain the power below specified Platform Power Limit #1
value.
This bit is writeable only when CPUID (EAX=6):EAX[4] is set.
23:17
Time Window for Platform Power Limit #1
Specifies the duration of the time window over which Platform Power
Limit 1 value should be maintained for sustained long duration. This field is
made up of two numbers from the following equation:
Time Window = (float) ((1+(X/4))*(2^Y)), where:
X = POWER_LIMIT_1_TIME[23:22]
Y = POWER_LIMIT_1_TIME[21:17]
The maximum allowed value in this field is defined in
MSR_PKG_POWER_INFO[PKG_MAX_WIN].
The default value is 0DH, and the unit is specified in
MSR_RAPL_POWER_UNIT[Time Unit].
31:24
Reserved.
46:32
Platform Power Limit #2
Average Power limit value which the platform must not exceed over the
Short Duration time window chosen by the processor.
The recommended default value is 1.25 times the Long Duration Power
Limit (i.e., Platform Power Limit # 1).
47
Enable Platform Power Limit #2
When set, enables the processor to apply control policy such that the
platform power does not exceed Platform Power limit #2 over the Short
Duration time window.
48
Platform Clamping Limitation #2
When set, allows the processor to go below the OS requested P states in
order to maintain the power below specified Platform Power Limit #2
value.
62:49
Reserved.
63
Lock. Setting this bit will lock all other bits of this MSR until system RESET.
Register Address: 690H, 1680
MSR_LASTBRANCH_16_FROM_IP
Last Branch Record 16 From IP (R/W)
Thread
One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains
pointers to the source instruction. See also:
• Last Branch Record Stack TOS at 1C9H.
• Section 18.12.
Register Address: 691H, 1681
MSR_LASTBRANCH_17_FROM_IP
Last Branch Record 17 From IP (R/W)
Thread
See description of MSR_LASTBRANCH_0_FROM_IP.
Register Address: 692H, 1682
MSR_LASTBRANCH_18_FROM_IP
2-342 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors, 1st-5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Last Branch Record 18 From IP (R/W)
Thread
See description of MSR_LASTBRANCH_0_FROM_IP.
Register Address: 693H, 1683
MSR_LASTBRANCH_19_FROM_IP
Last Branch Record 19From IP (R/W)
Thread
See description of MSR_LASTBRANCH_0_FROM_IP.
Register Address: 694H, 1684
MSR_LASTBRANCH_20_FROM_IP
Last Branch Record 20 From IP (R/W)
Thread
See description of MSR_LASTBRANCH_0_FROM_IP.
Register Address: 695H, 1685
MSR_LASTBRANCH_21_FROM_IP
Last Branch Record 21 From IP (R/W)
Thread
See description of MSR_LASTBRANCH_0_FROM_IP.
Register Address: 696H, 1686
MSR_LASTBRANCH_22_FROM_IP
Last Branch Record 22 From IP (R/W)
Thread
See description of MSR_LASTBRANCH_0_FROM_IP.
Register Address: 697H, 1687
MSR_LASTBRANCH_23_FROM_IP
Last Branch Record 23 From IP (R/W)
Thread
See description of MSR_LASTBRANCH_0_FROM_IP.
Register Address: 698H, 1688
MSR_LASTBRANCH_24_FROM_IP
Last Branch Record 24 From IP (R/W)
Thread
See description of MSR_LASTBRANCH_0_FROM_IP.
Register Address: 699H, 1689
MSR_LASTBRANCH_25_FROM_IP
Last Branch Record 25 From IP (R/W)
Thread
See description of MSR_LASTBRANCH_0_FROM_IP.
Register Address: 69AH, 1690
MSR_LASTBRANCH_26_FROM_IP
Last Branch Record 26 From IP (R/W)
Thread
See description of MSR_LASTBRANCH_0_FROM_IP.
Register Address: 69BH, 1691
MSR_LASTBRANCH_27_FROM_IP
Last Branch Record 27 From IP (R/W)
Thread
See description of MSR_LASTBRANCH_0_FROM_IP.
Register Address: 69CH, 1692
MSR_LASTBRANCH_28_FROM_IP
Last Branch Record 28 From IP (R/W)
Thread
See description of MSR_LASTBRANCH_0_FROM_IP.
Register Address: 69DH, 1693
MSR_LASTBRANCH_29_FROM_IP
Last Branch Record 29 From IP (R/W)
Thread
See description of MSR_LASTBRANCH_0_FROM_IP.
Register Address: 69EH, 1694
MSR_LASTBRANCH_30_FROM_IP
Last Branch Record 30 From IP (R/W)
Thread
See description of MSR_LASTBRANCH_0_FROM_IP.
Vol. 4
2-343
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors, 1st-5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 69FH, 1695
MSR_LASTBRANCH_31_FROM_IP
Last Branch Record 31 From IP (R/W)
Thread
See description of MSR_LASTBRANCH_0_FROM_IP.
Register Address: 6B0H, 1712
MSR_GRAPHICS_PERF_LIMIT_REASONS
Indicator of Frequency Clipping in the Processor Graphics (R/W)
Package
(Frequency refers to processor graphics frequency.)
0
PROCHOT Status (R0)
When set, frequency is reduced due to assertion of external PROCHOT.
1
Thermal Status (R0)
When set, frequency is reduced due to a thermal event.
4:2
Reserved.
5
Running Average Thermal Limit Status (R0)
When set, frequency is reduced due to running average thermal limit.
6
VR Therm Alert Status (R0)
When set, frequency is reduced due to a thermal alert from a processor
Voltage Regulator.
7
VR Thermal Design Current Status (R0)
When set, frequency is reduced due to VR TDC limit.
8
Other Status (R0)
When set, frequency is reduced due to electrical or other constraints.
9
Reserved.
10
Package/Platform-Level Power Limiting PL1 Status (R0)
When set, frequency is reduced due to package/platform-level power
limiting PL1.
11
Package/Platform-Level PL2 Power Limiting Status (R0)
When set, frequency is reduced due to package/platform-level power
limiting PL2/PL3.
12
Inefficient Operation Status (R0)
When set, processor graphics frequency is operating below target
frequency.
15:13
Reserved.
16
PROCHOT Log
When set, indicates that the PROCHOT Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
17
Thermal Log
When set, indicates that the Thermal Status bit has asserted since the log
bit was last cleared.
This log bit will remain set until cleared by software writing 0.
20:18
Reserved.
2-344 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors, 1st-5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
21
Running Average Thermal Limit Log
When set, indicates that the RATL Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software writing 0.
22
VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
23
VR Thermal Design Current Log
When set, indicates that the VR Therm Alert Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
24
Other Log
When set, indicates that the OTHER Status bit has asserted since the log
bit was last cleared.
This log bit will remain set until cleared by software writing 0.
25
Reserved.
26
Package/Platform-Level PL1 Power Limiting Log
When set, indicates that the Package/Platform Level PL1 Power Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
27
Package/Platform-Level PL2 Power Limiting Log
When set, indicates that the Package/Platform Level PL2 Power Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
28
Inefficient Operation Log
When set, indicates that the Inefficient Operation Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
63:29
Reserved.
Register Address: 6B1H, 1713
MSR_RING_PERF_LIMIT_REASONS
Indicator of Frequency Clipping in the Ring Interconnect (R/W)
Package
(Frequency refers to ring interconnect in the uncore.)
0
PROCHOT Status (R0)
When set, frequency is reduced due to assertion of external PROCHOT.
1
Thermal Status (R0)
When set, frequency is reduced due to a thermal event.
4:2
Reserved.
5
Running Average Thermal Limit Status (R0)
When set, frequency is reduced due to running average thermal limit.
Vol. 4
2-345
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors, 1st-5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
6
VR Therm Alert Status (R0)
When set, frequency is reduced due to a thermal alert from a processor
Voltage Regulator.
7
VR Thermal Design Current Status (R0)
When set, frequency is reduced due to VR TDC limit.
8
Other Status (R0)
When set, frequency is reduced due to electrical or other constraints.
9
Reserved.
10
Package/Platform-Level Power Limiting PL1 Status (R0)
When set, frequency is reduced due to package/Platform-level power
limiting PL1.
11
Package/Platform-Level PL2 Power Limiting Status (R0)
When set, frequency is reduced due to package/Platform-level power
limiting PL2/PL3.
15:12
Reserved
16
PROCHOT Log
When set, indicates that the PROCHOT Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
17
Thermal Log
When set, indicates that the Thermal Status bit has asserted since the log
bit was last cleared.
This log bit will remain set until cleared by software writing 0.
20:18
Reserved.
21
Running Average Thermal Limit Log
When set, indicates that the RATL Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software writing 0.
22
VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
23
VR Thermal Design Current Log
When set, indicates that the VR Therm Alert Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
24
Other Log
When set, indicates that the OTHER Status bit has asserted since the log
bit was last cleared.
This log bit will remain set until cleared by software writing 0.
25
Reserved.
2-346 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors, 1st-5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
26
Package/Platform-Level PL1 Power Limiting Log
When set, indicates that the Package/Platform Level PL1 Power Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
27
Package/Platform-Level PL2 Power Limiting Log
When set, indicates that the Package/Platform Level PL2 Power Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
63:28
Reserved.
Register Address: 6D0H, 1744
MSR_LASTBRANCH_16_TO_IP
Last Branch Record 16 To IP (R/W)
Thread
One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains
pointers to the destination instruction. See also:
• Last Branch Record Stack TOS at 1C9H.
• Section 18.12.
Register Address: 6D1H, 1745
MSR_LASTBRANCH_17_TO_IP
Last Branch Record 17 To IP (R/W)
Thread
See description of MSR_LASTBRANCH_0_TO_IP.
Register Address: 6D2H, 1746
MSR_LASTBRANCH_18_TO_IP
Last Branch Record 18 To IP (R/W)
Thread
See description of MSR_LASTBRANCH_0_TO_IP.
Register Address: 6D3H, 1747
MSR_LASTBRANCH_19_TO_IP
Last Branch Record 19To IP (R/W)
Thread
See description of MSR_LASTBRANCH_0_TO_IP.
Register Address: 6D4H, 1748
MSR_LASTBRANCH_20_TO_IP
Last Branch Record 20 To IP (R/W)
Thread
See description of MSR_LASTBRANCH_0_TO_IP.
Register Address: 6D5H, 1749
MSR_LASTBRANCH_21_TO_IP
Last Branch Record 21 To IP (R/W)
Thread
See description of MSR_LASTBRANCH_0_TO_IP.
Register Address: 6D6H, 1750
MSR_LASTBRANCH_22_TO_IP
Last Branch Record 22 To IP (R/W)
Thread
See description of MSR_LASTBRANCH_0_TO_IP.
Register Address: 6D7H, 1751
MSR_LASTBRANCH_23_TO_IP
Last Branch Record 23 To IP (R/W)
Thread
See description of MSR_LASTBRANCH_0_TO_IP.
Register Address: 6D8H, 1752
MSR_LASTBRANCH_24_TO_IP
Last Branch Record 24 To IP (R/W)
Thread
See description of MSR_LASTBRANCH_0_TO_IP.
Vol. 4
2-347
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors, 1st-5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 6D9H, 1753
MSR_LASTBRANCH_25_TO_IP
Last Branch Record 25 To IP (R/W)
Thread
See description of MSR_LASTBRANCH_0_TO_IP.
Register Address: 6DAH, 1754
MSR_LASTBRANCH_26_TO_IP
Last Branch Record 26 To IP (R/W)
Thread
See description of MSR_LASTBRANCH_0_TO_IP.
Register Address: 6DBH, 1755
MSR_LASTBRANCH_27_TO_IP
Last Branch Record 27 To IP (R/W)
Thread
See description of MSR_LASTBRANCH_0_TO_IP.
Register Address: 6DCH, 1756
MSR_LASTBRANCH_28_TO_IP
Last Branch Record 28 To IP (R/W)
Thread
See description of MSR_LASTBRANCH_0_TO_IP.
Register Address: 6DDH, 1757
MSR_LASTBRANCH_29_TO_IP
Last Branch Record 29 To IP (R/W)
Thread
See description of MSR_LASTBRANCH_0_TO_IP.
Register Address: 6DEH, 1758
MSR_LASTBRANCH_30_TO_IP
Last Branch Record 30 To IP (R/W)
Thread
See description of MSR_LASTBRANCH_0_TO_IP.
Register Address: 6DFH, 1759
MSR_LASTBRANCH_31_TO_IP
Last Branch Record 31 To IP (R/W)
Thread
See description of MSR_LASTBRANCH_0_TO_IP.
Register Address: 770H, 1904
IA32_PM_ENABLE
See Section 15.4.2, “Enabling HWP.”
Package
Register Address: 771H, 1905
IA32_HWP_CAPABILITIES
See Section 15.4.3, “HWP Performance Range and Dynamic Capabilities.”
Thread
Register Address: 772H, 1906
IA32_HWP_REQUEST_PKG
See Section 15.4.4, “Managing HWP.”
Package
Register Address: 773H, 1907
IA32_HWP_INTERRUPT
See Section 15.4.6, “HWP Notifications.”
Thread
Register Address: 774H, 1908
IA32_HWP_REQUEST
See Section 15.4.4, “Managing HWP.”
Thread
7:0
Minimum Performance (R/W)
15:8
Maximum Performance (R/W)
23:16
Desired Performance (R/W)
31:24
Energy/Performance Preference (R/W)
41:32
Activity Window (R/W)
42
Package Control (R/W)
2-348 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors, 1st-5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
63:43
Reserved.
Register Address: 777H, 1911
IA32_HWP_STATUS
See Section 15.4.5, “HWP Feedback.”
Thread
Register Address: D90H, 3472
IA32_BNDCFGS
See Table 2-2.
Thread
Register Address: DA0H, 3488
IA32_XSS
See Table 2-2.
Thread
Register Address: DB0H, 3504
IA32_PKG_HDC_CTL
See Section 15.5.2, “Package level Enabling HDC.”
Package
Register Address: DB1H, 3505
IA32_PM_CTL1
See Section 15.5.3, “Logical-Processor Level HDC Control.”
Thread
Register Address: DB2H, 3506
IA32_THREAD_STALL
See Section 15.5.4.1, “IA32_THREAD_STALL.”
Thread
Register Address: DC0H, 3520
MSR_LBR_INFO_0
Last Branch Record 0 Additional Information (R/W)
Thread
One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag,
TSX-related and elapsed cycle information. See also:
• Last Branch Record Stack TOS at 1C9H.
• Section 18.9.1, “LBR Stack.”
Register Address: DC1H, 3521
MSR_LBR_INFO_1
Last Branch Record 1 Additional Information (R/W)
Thread
See description of MSR_LBR_INFO_0.
Register Address: DC2H, 3522
MSR_LBR_INFO_2
Last Branch Record 2 Additional Information (R/W)
Thread
See description of MSR_LBR_INFO_0.
Register Address: DC3H, 3523
MSR_LBR_INFO_3
Last Branch Record 3 Additional Information (R/W)
Thread
See description of MSR_LBR_INFO_0.
Register Address: DC4H, 3524
MSR_LBR_INFO_4
Last Branch Record 4 Additional Information (R/W)
Thread
See description of MSR_LBR_INFO_0.
Register Address: DC5H, 3525
MSR_LBR_INFO_5
Last Branch Record 5 Additional Information (R/W)
Thread
See description of MSR_LBR_INFO_0.
Register Address: DC6H, 3526
MSR_LBR_INFO_6
Last Branch Record 6 Additional Information (R/W)
Thread
See description of MSR_LBR_INFO_0.
Register Address: DC7H, 3527
MSR_LBR_INFO_7
Vol. 4
2-349
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors, 1st-5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Last Branch Record 7 Additional Information (R/W)
Thread
See description of MSR_LBR_INFO_0.
Register Address: DC8H, 3528
MSR_LBR_INFO_8
Last Branch Record 8 Additional Information (R/W)
Thread
See description of MSR_LBR_INFO_0.
Register Address: DC9H, 3529
MSR_LBR_INFO_9
Last Branch Record 9 Additional Information (R/W)
Thread
See description of MSR_LBR_INFO_0.
Register Address: DCAH, 3530
MSR_LBR_INFO_10
Last Branch Record 10 Additional Information (R/W)
Thread
See description of MSR_LBR_INFO_0.
Register Address: DCBH, 3531
MSR_LBR_INFO_11
Last Branch Record 11 Additional Information (R/W)
Thread
See description of MSR_LBR_INFO_0.
Register Address: DCCH, 3532
MSR_LBR_INFO_12
Last Branch Record 12 Additional Information (R/W)
Thread
See description of MSR_LBR_INFO_0.
Register Address: DCDH, 3533
MSR_LBR_INFO_13
Last Branch Record 13 Additional Information (R/W)
Thread
See description of MSR_LBR_INFO_0.
Register Address: DCEH, 3534
MSR_LBR_INFO_14
Last Branch Record 14 Additional Information (R/W)
Thread
See description of MSR_LBR_INFO_0.
Register Address: DCFH, 3535
MSR_LBR_INFO_15
Last Branch Record 15 Additional Information (R/W)
Thread
See description of MSR_LBR_INFO_0.
Register Address: DD0H, 3536
MSR_LBR_INFO_16
Last Branch Record 16 Additional Information (R/W)
Thread
See description of MSR_LBR_INFO_0.
Register Address: DD1H, 3537
MSR_LBR_INFO_17
Last Branch Record 17 Additional Information (R/W)
Thread
See description of MSR_LBR_INFO_0.
Register Address: DD2H, 3538
MSR_LBR_INFO_18
Last Branch Record 18 Additional Information (R/W)
Thread
See description of MSR_LBR_INFO_0.
Register Address: DD3H, 3539
MSR_LBR_INFO_19
Last Branch Record 19 Additional Information (R/W)
Thread
See description of MSR_LBR_INFO_0.
2-350 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-39. Additional MSRs Supported by the 6th-13th Generation Intel® Core™ Processors, 1st-5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: DD4H, 3540
MSR_LBR_INFO_20
Last Branch Record 20 Additional Information (R/W)
Thread
See description of MSR_LBR_INFO_0.
Register Address: DD5H, 3541
MSR_LBR_INFO_21
Last Branch Record 21 Additional Information (R/W)
Thread
See description of MSR_LBR_INFO_0.
Register Address: DD6H, 3542
MSR_LBR_INFO_22
Last Branch Record 22 Additional Information (R/W)
Thread
See description of MSR_LBR_INFO_0.
Register Address: DD7H, 3543
MSR_LBR_INFO_23
Last Branch Record 23 Additional Information (R/W)
Thread
See description of MSR_LBR_INFO_0.
Register Address: DD8H, 3544
MSR_LBR_INFO_24
Last Branch Record 24 Additional Information (R/W)
Thread
See description of MSR_LBR_INFO_0.
Register Address: DD9H, 3545
MSR_LBR_INFO_25
Last Branch Record 25 Additional Information (R/W)
Thread
See description of MSR_LBR_INFO_0.
Register Address: DDAH, 3546
MSR_LBR_INFO_26
Last Branch Record 26 Additional Information (R/W)
Thread
See description of MSR_LBR_INFO_0.
Register Address: DDBH, 3547
MSR_LBR_INFO_27
Last Branch Record 27 Additional Information (R/W)
Thread
See description of MSR_LBR_INFO_0.
Register Address: DDCH, 3548
MSR_LBR_INFO_28
Last Branch Record 28 Additional Information (R/W)
Thread
See description of MSR_LBR_INFO_0.
Register Address: DDDH, 3549
MSR_LBR_INFO_29
Last Branch Record 29 Additional Information (R/W)
Thread
See description of MSR_LBR_INFO_0.
Register Address: DDEH, 3550
MSR_LBR_INFO_30
Last Branch Record 30 Additional Information (R/W)
Thread
See description of MSR_LBR_INFO_0.
Register Address: DDFH, 3551
MSR_LBR_INFO_31
Last Branch Record 31 Additional Information (R/W)
Thread
See description of MSR_LBR_INFO_0.
Vol. 4
2-351
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-40 lists the MSRs of uncore PMU for Intel processors with a CPUID Signature DisplayFamily_DisplayModel
value of 06_4EH, 06_5EH, 06_8EH, 06_9EH, or 06_66H.
Table 2-40. Uncore PMU MSRs Supported by 6th Generation, 7th Generation, and 8th Generation Intel® Core™
Processors, and 8th generation Intel® Core™ i3 Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 394H, 916
MSR_UNC_PERF_FIXED_CTRL
Uncore Fixed Counter Control (R/W)
Package
19:0
Reserved.
20
Enable overflow propagation.
21
Reserved.
22
Enable counting.
63:23
Reserved.
Register Address: 395H, 917
MSR_UNC_PERF_FIXED_CTR
Uncore Fixed Counter
Package
43:0
Current count.
63:44
Reserved.
Register Address: 396H, 918
MSR_UNC_CBO_CONFIG
Uncore C-Box Configuration Information (R/O)
Package
3:0
Specifies the number of C-Box units with programmable counters
(including processor cores and processor graphics).
63:4
Reserved.
Register Address: 3B0H, 946
MSR_UNC_ARB_PERFCTR0
Uncore Arb Unit, Performance Counter 0
Package
Register Address: 3B1H, 947
MSR_UNC_ARB_PERFCTR1
Uncore Arb Unit, Performance Counter 1
Package
Register Address: 3B2H, 944
MSR_UNC_ARB_PERFEVTSEL0
Uncore Arb Unit, Counter 0 Event Select MSR
Package
Register Address: 3B3H, 945
MSR_UNC_ARB_PERFEVTSEL1
Uncore Arb Unit, Counter 1 Event Select MSR
Package
Register Address: 700H, 1792
MSR_UNC_CBO_0_PERFEVTSEL0
Uncore C-Box 0, Counter 0 Event Select MSR
Package
Register Address: 701H, 1793
MSR_UNC_CBO_0_PERFEVTSEL1
Uncore C-Box 0, Counter 1 Event Select MSR
Package
Register Address: 706H, 1798
MSR_UNC_CBO_0_PERFCTR0
Uncore C-Box 0, Performance Counter 0
Package
Register Address: 707H, 1799
MSR_UNC_CBO_0_PERFCTR1
Uncore C-Box 0, Performance Counter 1
Package
Register Address: 710H, 1808
MSR_UNC_CBO_1_PERFEVTSEL0
Uncore C-Box 1, Counter 0 Event Select MSR
Package
Register Address: 711H, 1809
MSR_UNC_CBO_1_PERFEVTSEL1
2-352 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-40. Uncore PMU MSRs Supported by 6th Generation, 7th Generation, and 8th Generation Intel® Core™
Processors, and 8th generation Intel® Core™ i3 Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Uncore C-Box 1, Counter 1 Event Select MSR
Package
Register Address: 716H, 1814
MSR_UNC_CBO_1_PERFCTR0
Uncore C-Box 1, Performance Counter 0
Package
Register Address: 717H, 1815
MSR_UNC_CBO_1_PERFCTR1
Uncore C-Box 1, Performance Counter 1
Package
Register Address: 720H, 1824
MSR_UNC_CBO_2_PERFEVTSEL0
Uncore C-Box 2, Counter 0 Event Select MSR
Package
Register Address: 721H, 1825
MSR_UNC_CBO_2_PERFEVTSEL1
Uncore C-Box 2, Counter 1 Event Select MSR
Package
Register Address: 726H, 1830
MSR_UNC_CBO_2_PERFCTR0
Uncore C-Box 2, Performance Counter 0
Package
Register Address: 727H, 1831
MSR_UNC_CBO_2_PERFCTR1
Uncore C-Box 2, Performance Counter 1
Package
Register Address: 730H, 1840
MSR_UNC_CBO_3_PERFEVTSEL0
Uncore C-Box 3, Counter 0 Event Select MSR
Package
Register Address: 731H, 1841
MSR_UNC_CBO_3_PERFEVTSEL1
Uncore C-Box 3, Counter 1 Event Select MSR
Package
Register Address: 736H, 1846
MSR_UNC_CBO_3_PERFCTR0
Uncore C-Box 3, Performance Counter 0
Package
Register Address: 737H, 1847
MSR_UNC_CBO_3_PERFCTR1
Uncore C-Box 3, Performance Counter 1
Package
Register Address: E01H, 3585
MSR_UNC_PERF_GLOBAL_CTRL
Uncore PMU Global Control
Package
0
Slice 0 select.
1
Slice 1 select.
2
Slice 2 select.
3
Slice 3 select.
4
Slice 4select.
18:5
Reserved.
29
Enable all uncore counters.
30
Enable wake on PMI.
31
Enable Freezing counter when overflow.
63:32
Reserved.
Register Address: E02H, 3586
MSR_UNC_PERF_GLOBAL_STATUS
Uncore PMU Main Status
Package
0
Fixed counter overflowed.
1
An ARB counter overflowed.
Vol. 4
2-353
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-40. Uncore PMU MSRs Supported by 6th Generation, 7th Generation, and 8th Generation Intel® Core™
Processors, and 8th generation Intel® Core™ i3 Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
2
Reserved.
3
A CBox counter overflowed (on any slice).
63:4
Reserved.
2.17.1 MSRs Introduced in 7th Generation and 8th Generation Intel® Core™ Processors Based
on Kaby Lake Microarchitecture and Coffee Lake Microarchitecture
Table 2-41 lists additional MSRs for 7th generation and 8th generation Intel Core processors with a CPUID Signa-
ture DisplayFamily_DisplayModel value of 06_8EH or 06_9EH. For an MSR listed in Table 2-41 that also appears in
the model-specific tables of prior generations, Table 2-41 supersedes prior generation tables.
Table 2-41. Additional MSRs Supported by the 7th Generation and 8th Generation Intel® Core™ Processors Based
on Kaby Lake Microarchitecture and Coffee Lake Microarchitecture
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 80H, 128
MSR_TRACE_HUB_STH_ACPIBAR_BASE
NPK Address Used by AET Messages (R/W)
Package
0
Lock Bit
If set, this MSR cannot be re-written anymore. Lock bit has to be set in
order for the AET packets to be directed to NPK MMIO.
17:1
Reserved.
63:18
ACPIBAR_BASE_ADDRESS
AET target address in NPK MMIO space.
Register Address: 1F4H, 500
MSR_PRMRR_PHYS_BASE
Processor Reserved Memory Range Register - Physical Base Control Register (R/W)
Core
2:0
MemType
PRMRR BASE MemType.
11:3
Reserved.
45:12
Base
PRMRR Base Address.
63:46
Reserved.
Register Address: 1F5H, 501
MSR_PRMRR_PHYS_MASK
Processor Reserved Memory Range Register - Physical Mask Control Register (R/W)
Core
9:0
Reserved.
10
Lock
Lock bit for the PRMRR.
11
VLD
Enable bit for the PRMRR.
45:12
Mask
PRMRR MASK bits.
2-354 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-41. Additional MSRs Supported by the 7th Generation and 8th Generation Intel® Core™ Processors Based
on Kaby Lake Microarchitecture and Coffee Lake Microarchitecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
63:46
Reserved.
Register Address: 1FBH, 507
MSR_PRMRR_VALID_CONFIG
Valid PRMRR Configurations (R/W)
Core
0
1M supported MEE size.
4:1
Reserved.
5
32M supported MEE size.
6
64M supported MEE size.
7
128M supported MEE size.
31:8
Reserved.
Register Address: 2F4H, 756
MSR_UNCORE_PRMRR_PHYS_BASE1
(R/W)
Package
The PRMRR range is used to protect the processor reserved memory from unauthorized reads and writes. Any IO
access to this range is aborted. This register controls the location of the PRMRR range by indicating its starting
address. It functions in tandem with the PRMRR mask register.
11:0
Reserved.
PAWIDTH-1:12
Range Base
This field corresponds to bits PAWIDTH-1:12 of the base address memory
range which is allocated to PRMRR memory.
63:PAWIDTH
Reserved.
Register Address: 2F5H, 757
MSR_UNCORE_PRMRR_PHYS_MASK1
(R/W)
Package
This register controls the size of the PRMRR range by indicating which address bits must match the PRMRR base
register value.
9:0
Reserved.
10
Lock
Setting this bit locks all writeable settings in this register, including itself.
11
Range_En
Indicates whether the PRMRR range is enabled and valid.
38:12
Range_Mask
This field indicates which address bits must match PRMRR base in order
to qualify as an PRMRR access.
63:39
Reserved.
Register Address: 620H, 1568
MSR_RING_RATIO_LIMIT
Ring Ratio Limit (R/W)
Package
This register provides Min/Max Ratio Limits for the LLC and Ring.
6:0
MAX_Ratio
This field is used to limit the max ratio of the LLC/Ring.
7
Reserved.
Vol. 4
2-355
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-41. Additional MSRs Supported by the 7th Generation and 8th Generation Intel® Core™ Processors Based
on Kaby Lake Microarchitecture and Coffee Lake Microarchitecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
14:8
MIN_Ratio
Writing to this field controls the minimum possible ratio of the LLC/Ring.
63:15
Reserved.
NOTES:
1. This MSR is specific to 7th generation and 8th generation Intel® Core™ processors.
2.17.2 MSRs Specific to 8th Generation Intel® Core™ i3 Processors
Table 2-42 lists additional MSRs for 8th generation Intel Core i3 processors with a CPUID Signature
DisplayFamily_DisplayModel value of 06_66H. For an MSR listed in Table 2-42 that also appears in the model-
specific tables of prior generations, Table 2-42 supersede prior generation tables.
Table 2-42. Additional MSRs Supported by the 8th Generation Intel® Core™ i3 Processors
Based on Cannon Lake Microarchitecture
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 3AH, 58
IA32_FEATURE_CONTROL
Control Features in Intel 64 Processor (R/W)
Thread
See Table 2-2.
0
Lock (R/WL)
1
Enable VMX Inside SMX Operation (R/WL)
2
Enable VMX Outside SMX Operation (R/WL)
14:8
SENTER Local Functions Enables (R/WL)
15
SENTER Global Functions Enable (R/WL)
17
SGX Launch Control Enable (R/WL)
This bit must be set to enable runtime reconfiguration of SGX Launch
Control via IA32_SGXLEPUBKEYHASHn MSR.
Available only if CPUID.(EAX=07H, ECX=0H): ECX[30] = 1.
18
SGX Global Functions Enable (R/WL)
63:21
Reserved.
Register Address: 350H, 848
MSR_BR_DETECT_CTRL
Branch Monitoring Global Control (R/W)
0
EnMonitoring
Global enable for branch monitoring.
1
EnExcept
Enable branch monitoring event signaling on threshold trip.
The branch monitoring event handler is signaled via the existing PMI
signaling mechanism as programmed from the corresponding local APIC
LVT entry.
2-356 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-42. Additional MSRs Supported by the 8th Generation Intel® Core™ i3 Processors
Based on Cannon Lake Microarchitecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
2
EnLBRFrz
Enable LBR freeze on threshold trip. This will cause the LBR frozen bit
58 to be set in IA32_PERF_GLOBAL_STATUS when a triggering
condition occurs and this bit is enabled.
3
DisableInGuest
When set to ‘1’, branch monitoring, event triggering and LBR freeze
actions are disabled when operating at VMX non-root operation.
7:4
Reserved.
17:8
WindowSize
Window size defined by WindowCntSel. Values 0 - 1023 are supported.
Once the Window counter reaches the WindowSize count both the
Window Counter and all Branch Monitoring Counters are cleared.
23:18
Reserved.
25:24
WindowCntSel
Window event count select:
‘00 = Instructions retired.
‘01 = Branch instructions retired
‘10 = Return instructions retired.
‘11 = Indirect branch instructions retired.
26
CntAndMode
When set to ‘1’, the overall branch monitoring event triggering
condition is true only if all enabled counters’ threshold conditions are
true.
When ‘0’, the threshold tripping condition is true if any enabled
counters’ threshold is true.
63:27
Reserved.
Register Address: 351H, 849
MSR_BR_DETECT_STATUS
Branch Monitoring Global Status (R/W)
0
Branch Monitoring Event Signaled
When set to '1', Branch Monitoring event signaling is blocked until this
bit is cleared by software.
1
LBRsValid
This status bit is set to ‘1’ if the LBR state is considered valid for
sampling by branch monitoring software.
7:2
Reserved.
8
CntrHit0
Branch monitoring counter #0 threshold hit. This status bit is sticky
and once set requires clearing by software. Counter operation
continues independent of the state of the bit.
9
CntrHit1
Branch monitoring counter #1 threshold hit. This status bit is sticky
and once set requires clearing by software. Counter operation
continues independent of the state of the bit.
Vol. 4
2-357
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-42. Additional MSRs Supported by the 8th Generation Intel® Core™ i3 Processors
Based on Cannon Lake Microarchitecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
15:10
Reserved.
Reserved for additional branch monitoring counters threshold hit
status.
25:16
CountWindow
The current value of the window counter. The count value is frozen on
a valid branch monitoring triggering condition. This is a 10-bit unsigned
value.
31:26
Reserved.
Reserved for future extension of CountWindow.
39:32
Count0
The current value of counter 0 updated after each occurrence of the
event being counted. The count value is frozen on a valid branch
monitoring triggering condition (in which case CntrHit0 will also be set).
This is an 8-bit signed value (2’s complement).
Heuristic events which only increment will saturate and freeze at
maximum value 0xFF (256).
RET-CALL event counter saturate at maximum value 0x7F (+127) and
minimum value 0x80 (-128).
47:40
Count1
The current value of counter 1 updated after each occurrence of the
event being counted. The count value is frozen on a valid branch
monitoring triggering condition (in which case CntrHit1 will also be set).
This is an 8-bit signed value (2’s complement).
Heuristic events which only increment will saturate and freeze at
maximum value 0xFF (256).
RET-CALL event counter saturate at maximum value 0x7F (+127) and
minimum value 0x80 (-128).
63:48
Reserved.
Register Address: 354H-355H, 852-853
MSR_BR_DETECT_COUNTER_CONFIG_i
Branch Monitoring Detect Counter Configuration (R/W)
0
CntrEn
Enable counter.
7:1
CntrEvSel
Event select (other values #GP)
‘0000000 = RETs.
‘0000001 = RET-CALL bias.
‘0000010 = RET mispredicts.
‘0000011 = Branch (all) mispredicts.
‘0000100 = Indirect branch mispredicts.
‘0000101 = Far branch instructions.
14:8
CntrThreshold
Threshold (an unsigned value of 0 to 127 supported). The value 0 of
counter threshold will result in event signaled after every instruction.
#GP if threshold is < 2.
2-358 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-42. Additional MSRs Supported by the 8th Generation Intel® Core™ i3 Processors
Based on Cannon Lake Microarchitecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
15
MispredEventCnt
Mispredict events counting behavior:
‘0 = Mispredict events are counted in a window.
‘1 = Mispredict events are counted based on a consecutive occurrence.
CntrThreshold is treated as # of consecutive mispredicts. This control
bit only applies to events specified by CntrEvSel that involve a
prediction (0000010, 0000011, 0000100). Setting this bit for other
events is ignored.
63:16
Reserved.
Register Address: 3F8H, 1016
MSR_PKG_C3_RESIDENCY
Package C3 Residency Counter (R/O)
Package
63:0
Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI C-states.
Register Address: 620H, 1568
MSR_RING_RATIO_LIMIT
Ring Ratio Limit (R/W)
Package
This register provides Min/Max Ratio Limits for the LLC and Ring.
6:0
MAX_Ratio
This field is used to limit the max ratio of the LLC/Ring.
7
Reserved.
14:8
MIN_Ratio
Writing to this field controls the minimum possible ratio of the
LLC/Ring.
63:15
Reserved.
Register Address: 660H, 1632
MSR_CORE_C1_RESIDENCY
Core C1 Residency Counter (R/O)
Core
63:0
Value since last reset for the Core C1 residency. Counter rate is the
Max Non-Turbo frequency (same as TSC). This counter counts in case
both of the core's threads are in an idle state and at least one of the
core's thread residency is in a C1 state or in one of its sub states. The
counter is updated only after a core C state exit. Note: Always reads 0
if core C1 is unsupported. A value of zero indicates that this processor
does not support core C1 or never entered core C1 level state.
Register Address: 662H, 1634
MSR_CORE_C3_RESIDENCY
Core C3 Residency Counter (R/O)
Core
63:0
Will always return 0.
Table 2-43 lists the MSRs of uncore PMU for Intel processors with a CPUID Signature DisplayFamily_DisplayModel
value of 06_66H.
Vol. 4
2-359
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-43. Uncore PMU MSRs Supported by Intel® Core™ Processors Based on Cannon Lake Microarchitecture
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 394H, 916
MSR_UNC_PERF_FIXED_CTRL
Uncore Fixed Counter Control (R/W)
Package
19:0
Reserved.
20
Enable overflow propagation.
21
Reserved
22
Enable counting.
63:23
Reserved.
Register Address: 395H, 917
MSR_UNC_PERF_FIXED_CTR
Uncore Fixed Counter
Package
47:0
Current count.
63:48
Reserved.
Register Address: 396H, 918
MSR_UNC_CBO_CONFIG
Uncore C-Box Configuration Information (R/O)
Package
3:0
Report the number of C-Box units with performance counters, including
processor cores and processor graphics.
63:4
Reserved.
Register Address: 3B0H, 946
MSR_UNC_ARB_PERFCTR0
Uncore Arb Unit, Performance Counter 0
Package
Register Address: 3B1H, 947
MSR_UNC_ARB_PERFCTR1
Uncore Arb Unit, Performance Counter 1
Package
Register Address: 3B2H, 944
MSR_UNC_ARB_PERFEVTSEL0
Uncore Arb Unit, Counter 0 Event Select MSR
Package
Register Address: 3B3H, 945
MSR_UNC_ARB_PERFEVTSEL1
Uncore Arb unit, Counter 1 Event Select MSR
Package
Register Address: 700H, 1792
MSR_UNC_CBO_0_PERFEVTSEL0
Uncore C-Box 0, Counter 0 Event Select MSR
Package
Register Address: 701H, 1793
MSR_UNC_CBO_0_PERFEVTSEL1
Uncore C-Box 0, Counter 1 Event Select MSR
Package
Register Address: 702H, 1794
MSR_UNC_CBO_0_PERFCTR0
Uncore C-Box 0, Performance Counter 0
Package
Register Address: 703H, 1795
MSR_UNC_CBO_0_PERFCTR1
Uncore C-Box 0, Performance Counter 1
Package
Register Address: 708H, 1800
MSR_UNC_CBO_1_PERFEVTSEL0
Uncore C-Box 1, Counter 0 Event Select MSR
Package
Register Address: 709H, 1801
MSR_UNC_CBO_1_PERFEVTSEL1
Uncore C-Box 1, Counter 1 Event Select MSR
Package
Register Address: 70AH, 1802
MSR_UNC_CBO_1_PERFCTR0
2-360 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-43. Uncore PMU MSRs Supported by Intel® Core™ Processors Based on Cannon Lake Microarchitecture
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Uncore C-Box 1, Performance Counter 0
Package
Register Address: 70BH, 1803
MSR_UNC_CBO_1_PERFCTR1
Uncore C-Box 1, Performance Counter 1
Package
Register Address: 710H, 1808
MSR_UNC_CBO_2_PERFEVTSEL0
Uncore C-Box 2, Counter 0 Event Select MSR
Package
Register Address: 711H, 1809
MSR_UNC_CBO_2_PERFEVTSEL1
Uncore C-Box 2, Counter 1 Event Select MSR
Package
Register Address: 712H, 1810
MSR_UNC_CBO_2_PERFCTR0
Uncore C-Box 2, Performance Counter 0
Package
Register Address: 713H, 1811
MSR_UNC_CBO_2_PERFCTR1
Uncore C-Box 2, Performance Counter 1
Package
Register Address: 718H, 1816
MSR_UNC_CBO_3_PERFEVTSEL0
Uncore C-Box 3, Counter 0 Event Select MSR
Package
Register Address: 719H, 1817
MSR_UNC_CBO_3_PERFEVTSEL1
Uncore C-Box 3, Counter 1 Event Select MSR
Package
Register Address: 71AH, 1818
MSR_UNC_CBO_3_PERFCTR0
Uncore C-Box 3, Performance Counter 0
Package
Register Address: 71BH, 1819
MSR_UNC_CBO_3_PERFCTR1
Uncore C-Box 3, Performance Counter 1
Package
Register Address: 720H, 1824
MSR_UNC_CBO_4_PERFEVTSEL0
Uncore C-Box 4, Counter 0 Event Select MSR
Package
Register Address: 721H, 1825
MSR_UNC_CBO_4_PERFEVTSEL1
Uncore C-Box 4, Counter 1 Event Select MSR
Package
Register Address: 722H, 1826
MSR_UNC_CBO_4_PERFCTR0
Uncore C-Box 4, Performance Counter 0
Package
Register Address: 723H, 1827
MSR_UNC_CBO_4_PERFCTR1
Uncore C-Box 4, Performance Counter 1
Package
Register Address: 728H, 1832
MSR_UNC_CBO_5_PERFEVTSEL0
Uncore C-Box 5, Counter 0 Event Select MSR
Package
Register Address: 729H, 1833
MSR_UNC_CBO_5_PERFEVTSEL1
Uncore C-Box 5, Counter 1 Event Select MSR
Package
Register Address: 72AH, 1834
MSR_UNC_CBO_5_PERFCTR0
Uncore C-Box 5, Performance Counter 0
Package
Register Address: 72BH, 1835
MSR_UNC_CBO_5_PERFCTR1
Uncore C-Box 5, Performance Counter 1
Package
Register Address: 730H, 1840
MSR_UNC_CBO_6_PERFEVTSEL0
Uncore C-Box 6, Counter 0 Event Select MSR
Package
Vol. 4
2-361
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-43. Uncore PMU MSRs Supported by Intel® Core™ Processors Based on Cannon Lake Microarchitecture
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 731H, 1841
MSR_UNC_CBO_6_PERFEVTSEL1
Uncore C-Box 6, Counter 1 Event Select MSR
Package
Register Address: 732H, 1842
MSR_UNC_CBO_6_PERFCTR0
Uncore C-Box 6, Performance Counter 0
Package
Register Address: 733H, 1843
MSR_UNC_CBO_6_PERFCTR1
Uncore C-Box 6, Performance Counter 1
Package
Register Address: 738H, 1848
MSR_UNC_CBO_7_PERFEVTSEL0
Uncore C-Box 7, Counter 0 Event Select MSR
Package
Register Address: 739H, 1849
MSR_UNC_CBO_7_PERFEVTSEL1
Uncore C-Box 7, Counter 1 Event Select MSR
Package
Register Address: 73AH, 1850
MSR_UNC_CBO_7_PERFCTR0
Uncore C-Box 7, Performance Counter 0
Package
Register Address: 73BH, 1851
MSR_UNC_CBO_7_PERFCTR1
Uncore C-Box 7, Performance Counter 1
Package
Register Address: E01H, 3585
MSR_UNC_PERF_GLOBAL_CTRL
Uncore PMU Global Control
Package
0
Slice 0 select.
1
Slice 1 select.
2
Slice 2 select.
3
Slice 3 select.
4
Slice 4select.
18:5
Reserved.
29
Enable all uncore counters.
30
Enable wake on PMI.
31
Enable Freezing counter when overflow.
63:32
Reserved.
Register Address: E02H, 3586
MSR_UNC_PERF_GLOBAL_STATUS
Uncore PMU Main Status
Package
0
Fixed counter overflowed.
1
An ARB counter overflowed.
2
Reserved.
3
A CBox counter overflowed (on any slice).
63:4
Reserved.
2.17.3 MSRs Introduced in 10th Generation Intel® Core™ Processors
Table 2-44 lists additional MSRs for 10th generation Intel Core processors with a CPUID Signature
DisplayFamily_DisplayModel value of 06_7DH or 06_7EH. For an MSR listed in Table 2-44 that also appears in the
model-specific tables of prior generations, Table 2-44 supersede prior generation tables.
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-44. MSRs Supported by the 10th Generation Intel® Core™ Processors (Ice Lake Microarchitecture)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 33H, 51
MSR_MEMORY_CTRL
Memory Control Register
Core
28:0
Reserved.
29
SPLIT_LOCK_DISABLE
If set to 1, a split lock will cause an #AC(0) exception.
See Section 9.1.2.3, “Features to Disable Bus Locks.”
30
Reserved.
31
Reserved.
Register Address: 48H, 72
IA32_SPEC_CTRL
See Table 2-2.
Core
Register Address: 49H, 73
IA32_PREDICT_CMD
See Table 2-2.
Thread
Register Address: 8CH, 140
IA32_SGXLEPUBKEYHASH0
See Table 2-2.
Thread
Register Address: 8DH, 141
IA32_SGXLEPUBKEYHASH1
See Table 2-2.
Thread
Register Address: 8EH, 142
IA32_SGXLEPUBKEYHASH2
See Table 2-2.
Thread
Register Address: 8FH, 143
IA32_SGXLEPUBKEYHASH3
See Table 2-2.
Thread
Register Address: A0H, 160
MSR_BIOS_MCU_ERRORCODE
BIOS MCU ERRORCODE (R/O)
Package
This MSR indicates if WRMSR 0x79 failed to configure PRM memory and gives a hint to debug BIOS.
15:0
Error Codes (R/O)
Package
30:16
Reserved.
31
MCU Partial Success (R/O)
Thread
When set to 1, WRMSR 0x79 skipped part of the functionality during
BIOS.
Register Address: A5H, 165
MSR_FIT_BIOS_ERROR
FIT BIOS ERROR (R/W)
Thread
Report error codes for debug in case the processor failed to parse the Firmware Table in BIOS.
Can also be used to log BIOS information.
7:0
Error Codes (R/W)
Error codes for debug.
15:8
Entry Type (R/W)
Failed FIT entry type.
16
FIT MCU Entry (R/W)
FIT contains MCU entry.
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-44. MSRs Supported by the 10th Generation Intel® Core™ Processors (Ice Lake Microarchitecture) (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
62:17
Reserved.
63
LOCK (R/W)
When set to 1, writes to this MSR will be skipped.
Register Address: 10BH, 267
IA32_FLUSH_CMD
See Table 2-2.
Thread
Register Address: 151H, 337
MSR_BIOS_DONE
BIOS Done (R/WO)
Thread
0
BIOS Done Indication (R/WO)
Thread
Set by BIOS when it finishes programming the processor and wants to
lock the memory configuration from changes by software that is running
on this thread.
Writes to the bit will be ignored if EAX[0] is 0.
1
Package BIOS Done Indication (R/O)
Package
When set to 1, all threads in the package have bit 0 of this MSR set.
31:2
Reserved.
Register Address: 1F1H, 497
MSR_CRASHLOG_CONTROL
Write Data to a Crash Log Configuration
Thread
0
CDDIS: CrashDump_Disable
If set, indicates that Crash Dump is disabled.
63:1
Reserved.
Register Address: 2A0H, 672
MSR_PRMRR_BASE_0
Processor Reserved Memory Range Register - Physical Base Control Register (R/W)
Core
2:0
MEMTYPE: PRMRR BASE Memory Type.
3
CONFIGURED: PRMRR BASE Configured.
11:4
Reserved.
51:12
BASE: PRMRR Base Address.
63:52
Reserved.
Register Address: 30CH, 780
IA32_FIXED_CTR3
Fixed-Function Performance Counter Register 3 (R/W)
Thread
Bit definitions are the same as found in IA32_FIXED_CTR0, offset 309H. See Table 2-2.
Register Address: 329H, 809
MSR_PERF_METRICS
Performance Metrics (R/W)
Thread
Reports metrics directly. Software can check (and/or expose to its guests) the availability of PERF_METRICS feature
using IA32_PERF_CAPABILITIES.PERF_METRICS_AVAILABLE (bit 15).
7:0
Retiring. Percent of utilized slots by uops that eventually retire (commit).
15:8
Bad Speculation. Percent of wasted slots due to incorrect speculation,
covering utilized by uops that do not retire, or recovery bubbles
(unutilized slots).
23:16
Frontend Bound. Percent of unutilized slots where front-end did not
deliver a uop while back-end is ready.
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-44. MSRs Supported by the 10th Generation Intel® Core™ Processors (Ice Lake Microarchitecture) (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
31:24
Backend Bound. Percent of unutilized slots where a uop was not delivered
to back-end due to lack of back-end resources.
63:25
Reserved.
Register Address: 3F2H, 1010
MSR_PEBS_DATA_CFG
PEBS Data Configuration (R/W)
Thread
Provides software the capability to select data groups of interest and thus reduce the record size in memory and
record generation latency. Hence, a PEBS record's size and layout vary based on the selected groups. The MSR also
allows software to select LBR depth for branch data records.
0
Memory Info.
Setting this bit will capture memory information such as the linear
address, data source and latency of the memory access in the PEBS
record.
1
GPRs.
Setting this bit will capture the contents of the General Purpose registers
in the PEBS record.
2
XMMs.
Setting this bit will capture the contents of the XMM registers in the PEBS
record.
3
LBRs.
Setting this bit will capture LBR TO, FROM, and INFO in the PEBS record.
23:4
Reserved.
31:24
LBR Entries.
Set the field to the desired number of entries - 1. For example, if the
LBR_entries field is 0, a single entry will be included in the record. To
include 32 LBR entries, set the LBR_entries field to 31 (0x1F). To ensure
all PEBS records are 16-byte aligned, software can use LBR_entries that
is multiple of 3.
Register Address: 541H, 1345
MSR_CORE_UARCH_CTL
Core Microarchitecture Control MSR (R/W)
Core
0
L1 Scrubbing Enable
When set to 1, enable L1 scrubbing.
31:1
Reserved.
Register Address: 657H, 1623
MSR_FAST_UNCORE_MSRS_CTL
Fast WRMSR/RDMSR Control MSR (R/W)
Thread
3:0
FAST_ACCESS_ENABLE:
Bit 0: When set to '1', provides a hint for the hardware to enable fast
access mode for the IA32_HWP_REQUEST MSR.
This bit is sticky and is cleaned by the hardware only during reset time.
This bit is valid only if FAST_UNCORE_MSRS_CAPABILITY[0] is set. Setting
this bit will cause CPUID[6].EAX[18] to be set.
31:4
Reserved.
Register Address: 65EH, 1630
MSR_FAST_UNCORE_MSRS_STATUS
Indication of Uncore MSRs, Post Write Activates
Thread
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-44. MSRs Supported by the 10th Generation Intel® Core™ Processors (Ice Lake Microarchitecture) (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
0
Indicates whether the CPU is still in the middle of writing
IA32_HWP_REQUEST MSR, even after the WRMSR instruction has retired.
A value of 1 indicates the last write of IA32_HWP_REQUEST is still
ongoing.
A value of 0 indicates the last write of IA32_HWP_REQUEST is visible
outside the logical processor.
Software can use the status of this bit to avoid overwriting
IA32_HWP_REQUEST.
31:1
Reserved.
Register Address: 65FH, 1631
MSR_FAST_UNCORE_MSRS_CAPABILITY
Fast WRMSR/RDMSR Enumeration MSR (R/O)
Thread
3:0
MSRS_CAPABILITY:
Bit 0: If set to ‘1’, hardware supports the fast access mode for the
IA32_HWP_REQUEST MSR.
31:4
Reserved.
Register Address: 772H, 1906
IA32_HWP_REQUEST_PKG
See Table 2-2.
Package
Register Address: 775H, 1909
IA32_PECI_HWP_REQUEST_INFO
See Table 2-2.
Thread
Register Address: 777H, 1911
IA32_HWP_STATUS
See Table 2-2.
Thread
2.17.4 MSRs Introduced in the 11th Generation Intel® Core™ Processors based on Tiger Lake
Microarchitecture
Table 2-45 lists additional MSRs for 11th generation Intel Core processors with a CPUID Signature
DisplayFamily_DisplayModel value of 06_8CH or 06_8DH. The MSRs listed in Table 2-44 are also supported by
these processors. For an MSR listed in Table 2-45 that also appears in the model-specific tables of prior genera-
tions, Table 2-45 supersedes prior generation tables.
Table 2-45. Additional MSRs Supported by the 11th Generation Intel® Core™ Processors Based on Tiger Lake
Microarchitecture
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: A0H, 160
MSR_BIOS_MCU_ERRORCODE
BIOS MCU ERRORCODE (R/O)
Package
15:0
Error Codes
31:16
Reserved.
Register Address: A7H, 167
MSR_BIOS_DEBUG
BIOS DEBUG (R/O)
Thread
This MSR indicates if WRMSR 79H failed to configure PRM memory and gives a hint to debug BIOS.
30:0
Reserved.
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-45. Additional MSRs Supported by the 11th Generation Intel® Core™ Processors Based on Tiger Lake
Microarchitecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
31
MCU Partial Success
When set to 1, WRMSR 79H skipped part of the functionality during
BIOS.
63:32
Reserved.
Register Address: CFH, 207
IA32_CORE_CAPABILITIES
IA32 Core Capabilities Register (R/O)
Package
If CPUID.(EAX=07H, ECX=0):EDX[30] = 1.
This MSR provides an architectural enumeration function for model-specific behavior.
1:0
Reserved.
2
FUSA_SUPPORTED
3
RSM_IN_CPL0_ONLY
When set to 1, the RSM instruction is only allowed in CPL0 (#GP
triggered in any CPL != 0).
When set to 0, then any CPL may execute the RSM instruction.
4
Reserved.
5
SPLIT_LOCK_DISABLE_SUPPORTED
When read as 1, software can set bit 29 of MSR_MEMORY_CTRL
(MSR address 33H).
31:6
Reserved.
Register Address: 492H, 1170
IA32_VMX_PROCBASED_CTLS3
IA32_VMX_PROCBASED_CTLS3
Core
This MSR enumerates the allowed 1-settings of the third set of processor-based controls. Specifically, VM entry
allows bit X of the tertiary processor-based VM-execution controls to be 1 if and only if bit X of the MSR is set to 1.
If bit X of the MSR is cleared to 0, VM entry fails if control X and the “activate tertiary controls” primary processor-
based VM-execution control are both 1.
0
LOADIWKEY
This control determines whether executions of LOADIWKEY cause VM
exits.
63:1
Reserved.
Register Address: 601H, 1537
MSR_VR_CURRENT_CONFIG
Power Limit 4 (PL4)
Package
Package-level maximum power limit (in Watts). It is a proactive, instantaneous limit.
12:0
PL4 Value
PL4 value in 0.125 A increments. This field is locked by
VR_CURRENT_CONFIG[LOCK]. When the LOCK bit is set to 1b, this
field becomes Read Only.
30:13
Reserved.
31
Lock Indication (LOCK)
This bit will lock the CURRENT_LIMIT settings in this register and will
also lock this setting. This means that once set to 1b, the
CURRENT_LIMIT setting and this bit become Read Only until the next
Warm Reset.
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-45. Additional MSRs Supported by the 11th Generation Intel® Core™ Processors Based on Tiger Lake
Microarchitecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
62:32
Not in use.
63
Reserved.
Register Address: 6A0H, 1696
IA32_U_CET
Configure User Mode CET (R/W)
See Table 2-2.
Register Address: 6A2H, 1698
IA32_S_CET
Configure Supervisor Mode CET (R/W)
See Table 2-2.
Register Address: 6A4H, 1700
IA32_PL0_SSP
Linear address to be loaded into SSP on transition to privilege level 0. (R/W)
See Table 2-2.
Register Address: 6A5H, 1701
IA32_PL1_SSP
Linear address to be loaded into SSP on transition to privilege level 1. (R/W)
See Table 2-2.
Register Address: 6A6H, 1702
IA32_PL2_SSP
Linear address to be loaded into SSP on transition to privilege level 2. (R/W)
See Table 2-2.
Register Address: 6A7H, 1703
IA32_PL3_SSP
Linear address to be loaded into SSP on transition to privilege level 3. (R/W)
See Table 2-2.
Register Address: 6A8H, 1704
IA32_INTERRUPT_SSP_TABLE_ADDR
Linear address of a table of seven shadow stack pointers that are selected in IA-32e mode using the IST index (when
not 0) from the interrupt gate descriptor. (R/W)
See Table 2-2.
Register Address: 981H, 2433
IA32_TME_CAPABILITY
See Table 2-2.
Register Address: 982H, 2434
IA32_TME_ACTIVATE
See Table 2-2.
Register Address: 983H, 2435
IA32_TME_EXCLUDE_MASK
See Table 2-2.
Register Address: 984H, 2436
IA32_TME_EXCLUDE_BASE
See Table 2-2.
Register Address: 990H, 2448
IA32_COPY_STATUS1
See Table 2-2.
Thread
Register Address: 991H, 2449
IA32_IWKEYBACKUP_STATUS1
See Table 2-2.
Platform
Register Address: C82H, 3202
IA32_L2_QOS_CFG
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-45. Additional MSRs Supported by the 11th Generation Intel® Core™ Processors Based on Tiger Lake
Microarchitecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
IA32_CR_L2_QOS_CFG
Core
This MSR provides software an enumeration of the parameters that L2 QoS (Intel RDT) support in any particular
implementation.
0
CDP_ENABLE
When set to 1, it will enable the code and data prioritization for the
L2 CAT/Intel RDT feature.
When set to 0, code and data prioritization is disabled for L2 CAT/Intel
RDT. See Chapter 18, “Debug, Branch Profile, TSC, and Intel® Resource
Director Technology (Intel® RDT) Features‚” for further details on CDP.
31:1
Reserved.
Register Address: D10H-D17H, 3220-3351
IA32_L2_QOS_MASK_[0-7]
IA32_CR_L2_QOS_MASK_[0-7]
Package
Controls MLC (L2) Intel RDT allocation. For more details on CAT/RDT, see Chapter 18, “Debug, Branch Profile, TSC, and
Intel® Resource Director Technology (Intel® RDT) Features.”
19:0
WAYS_MASK
Setting a 1 in this bit X allows threads with CLOS <n> (where N is [0-
7]) to allocate to way X in the MLC. Ones are only allowed to be
written to ways that physically exist in the MLC
(CPUID.4.2:EBX[31:22] will indicate this).
Writing a 1 to a value beyond the highest way or a non-contiguous
set of 1s will cause a #GP on the WRMSR to this MSR.
31:20
Reserved.
Register Address: D91H, 3473
IA32_COPY_LOCAL_TO_PLATFORM1
See Table 2-2.
Thread
Register Address: D92H, 3474
IA32_COPY_PLATFORM_TO_LOCAL1
See Table 2-2.
Thread
NOTES:
1. Further details on Key Locker and usage of this MSR can be found here:
https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html.
2.17.5 MSRs Introduced in the 12th and 13th Generation Intel® Core™ Processors Supporting
Performance Hybrid Architecture
Table 2-46 lists additional MSRs for 12th and 13th generation Intel Core processors with a CPUID Signature
DisplayFamily_DisplayModel value of 06_97H, 06_9AH, 06_BAH, 06_B7H, or 06_BFH. Table 2-47 lists the MSRs
unique to the processor P-core. Table 2-48 lists the MSRs unique to the processor E-core.
The MSRs listed in Table 2-441 and Table 2-45 are also supported by these processors. For an MSR listed in Table
2-46, Table 2-47, or Table 2-48 that also appears in the model-specific tables of prior generations, Table 2-46,
Table 2-47, and Table 2-48 supersede prior generation tables.
1. MSRs at the following addresses are not supported in the 12th and 13th generation Intel Core processor E-core: 30CH, 329H, 541H,
and 657H. The MSR at address 657H is not supported in the 12th and 13th generation Intel Core processor P-core.
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-46. Additional MSRs Supported by the 12th and 13th Generation Intel® Core™ Processors Supporting
Performance Hybrid Architecture
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 33H, 51
MSR_MEMORY_CTRL
Memory Control Register
Core
26:0
Reserved.
27
UC_STORE_THROTTLE
If set to 1, when enabled, the processor will only allow one in-
progress UC store at a time.
28
UC_LOCK_DISABLE
If set to 1, a UC lock will cause a #GP(0) exception.
See Section 9.1.2.3, “Features to Disable Bus Locks.”
29
SPLIT_LOCK_DISABLE
If set to 1, a split lock will cause an #AC(0) exception.
See Section 9.1.2.3, “Features to Disable Bus Locks.”
30
Reserved.
31
Reserved.
Register Address: BCH, 188
IA32_MISC_PACKAGE_CTLS
Power Filtering Control (R/W)
Package
IA32_ARCH_CAPABILITIES[bit 10] enumerates support for this MSR.
See Table 2-2.
Register Address: C7H, 199
IA32_PMC6
General Performance Counter 6 (R/W)
Core
See Table 2-2.
Register Address: C8H, 200
IA32_PMC7
General Performance Counter 7 (R/W)
Core
See Table 2-2.
Register Address: CFH, 207
IA32_CORE_CAPABILITIES
IA32 Core Capabilities Register (R/O)
Package
If CPUID.(EAX=07H, ECX=0):EDX[30] = 1.
This MSR provides an architectural enumeration function for model-specific behavior.
0
STLB_QOS_SUPPORTED
When set to 1, the STLB QoS feature is supported and the STLB
QoS MSRs (1A8FH -1A97H) are accessible. When set to 0, access
to these MSRs will #GP.
1
Reserved.
2
FUSA_SUPPORTED
3
RSM_IN_CPL0_ONLY
When set to 1, the RSM instruction is only allowed in CPL0 (#GP
triggered in any CPL != 0).
When set to 0, then any CPL may execute the RSM instruction.
2-370 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-46. Additional MSRs Supported by the 12th and 13th Generation Intel® Core™ Processors Supporting
Performance Hybrid Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
4
UC_LOCK_DISABLE_SUPPORTED
When read as 1, software can set bit 28 of MSR_MEMORY_CTRL
(MSR address 33H).
5
SPLIT_LOCK_DISABLE_SUPPORTED
When read as 1, software can set bit 29 of MSR_MEMORY_CTRL.
6
SNOOP_FILTER_QOS_SUPPORTED
When set to 1, the Snoop Filter Qos Mask MSRs are supported.
When set to 0, access to these MSRs will #GP.
7
UC_STORE_THROTTLING_SUPPORTED
When set 1, UC Store throttle capability exist through
MSR_MEMORY_CTRL (33H) bit 27.
31:8
Reserved.
Register Address: E1H, 225
IA32_UMWAIT_CONTROL
UMWAIT Control (R/W)
See Table 2-2.
Register Address: 10AH, 266
IA32_ARCH_CAPABILITIES
Enumeration of Architectural Features (R/O)
See Table 2-2.
Register Address: 18CH, 396
IA32_PERFEVTSEL6
See Table 2-20.
Core
Register Address: 18DH, 397
IA32_PERFEVTSEL7
See Table 2-20.
Core
Register Address: 195H, 405
IA32_OVERCLOCKING_STATUS
Overclocking Status (R/O)
Package
IA32_ARCH_CAPABILITIES[bit 23] enumerates support for this MSR. See Table 2-2.
Register Address: 1ADH, 429
MSR_PRIMARY_TURBO_RATIO_LIMIT
Primary Maximum Turbo Ratio Limit (R/W)
Package
Software can configure these limits when MSR_PLATFORM_INFO[28] = 1. Specifies Maximum Ratio Limit for each
group. Maximum ratio for groups with more cores must decrease monotonically.
7:0
MAX_TURBO_GROUP_0:
Maximum turbo ratio limit with 1 core active.
15:8
MAX_TURBO_GROUP_1:
Maximum turbo ratio limit with 2 cores active.
23:16
MAX_TURBO_GROUP_2:
Maximum turbo ratio limit with 3 cores active.
31:24
MAX_TURBO_GROUP_3:
Maximum turbo ratio limit with 4 cores active.
39:32
MAX_TURBO_GROUP_4:
Maximum turbo ratio limit with 5 cores active.
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-46. Additional MSRs Supported by the 12th and 13th Generation Intel® Core™ Processors Supporting
Performance Hybrid Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
47:40
MAX_TURBO_GROUP_5:
Maximum turbo ratio limit with 6 cores active.
55:48
MAX_TURBO_GROUP_6:
Maximum turbo ratio limit with 7 cores active.
63:56
MAX_TURBO_GROUP_7:
Maximum turbo ratio limit with 8 cores active.
Register Address: 493H, 1171
IA32_VMX_EXIT_CTLS2
See Table 2-2.
Register Address: 4C7H, 1223
IA32_A_PMC6
Full Width Writable IA32_PMC6 Alias (R/W)
See Table 2-2.
Register Address: 4C8H, 1224
IA32_A_PMC7
Full Width Writable IA32_PMC7 Alias (R/W)
See Table 2-2.
Register Address: 650H, 1616
MSR_SECONDARY_TURBO_RATIO_LIMIT
Secondary Maximum Turbo Ratio Limit (R/W)
Package
Software can configure these limits when MSR_PLATFORM_INFO[28] = 1.
Specifies Maximum Ratio Limit for each group. Maximum ratio for groups with more cores must decrease
monotonically.
7:0
MAX_TURBO_GROUP_0:
Maximum turbo ratio limit with 1 core active.
15:8
MAX_TURBO_GROUP_1:
Maximum turbo ratio limit with 2 cores active.
23:16
MAX_TURBO_GROUP_2:
Maximum turbo ratio limit with 3 cores active.
31:24
MAX_TURBO_GROUP_3:
Maximum turbo ratio limit with 4 cores active.
39:32
MAX_TURBO_GROUP_4:
Maximum turbo ratio limit with 5 cores active.
47:40
MAX_TURBO_GROUP_5:
Maximum turbo ratio limit with 6 cores active.
55:48
MAX_TURBO_GROUP_6:
Maximum turbo ratio limit with 7 cores active.
63:56
MAX_TURBO_GROUP_7:
Maximum turbo ratio limit with 8 cores active.
Register Address: 664H, 1636
MSR_MC6_RESIDENCY_COUNTER
Module C6 Residency Counter (R/0)
Module
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-46. Additional MSRs Supported by the 12th and 13th Generation Intel® Core™ Processors Supporting
Performance Hybrid Architecture (Contd.)
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
63:0
Time that this module is in module-specific C6 states since last
reset. Counts at 1 Mhz frequency.
Register Address: 6E1H, 1761
IA32_PKRS
Specifies the PK permissions associated with each protection domain for supervisor pages (R/W)
See Table 2-2.
Register Address: 776H, 1910
IA32_HWP_CTL
See Table 2-2.
Register Address: 981H, 2433
IA32_TME_CAPABILITY
Memory Encryption Capability MSR
See Table 2-2.
Register Address: 1200H-121FH, 4608-4639
IA32_LBR_x_INFO
Last Branch Record Entry X Info Register (R/W)
See Table 2-2.
Register Address: 14CEH, 5326
IA32_LBR_CTL
Last Branch Record Enabling and Configuration Register (R/W)
See Table 2-2.
Register Address: 14CFH, 5327
IA32_LBR_DEPTH
Last Branch Record Maximum Stack Depth Register (R/W)
See Table 2-2.
IA32_LBR_x_FROM_IP
Register Address: 1500H-151FH, 5376-5407
Last Branch Record Entry X Source IP Register (R/W)
See Table 2-2.
IA32_LBR_x_TO_IP
Register Address: 1600H-161FH, 5632-5663
Last Branch Record Entry X Destination IP Register (R/W)
See Table 2-2.
Register Address: 17D2H, 6098
IA32_THREAD_FEEDBACK_CHAR
Thread Feedback Characteristics (R/O)
See Table 2-2.
Register Address: 17D4H, 6100
IA32_HW_FEEDBACK_THREAD_CONFIG
Hardware Feedback Thread Configuration (R/W)
See Table 2-2.
Register Address: 17DAH, 6106
IA32_HRESET_ENABLE
History Reset Enable (R/W)
See Table 2-2.
The MSRs listed in Table 2-47 are unique to the 12th and 13th generation Intel Core processor P-core. These MSRs
are not supported on the processor E-core.
Vol. 4
2-373
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-47. MSRs Supported by 12th and 13th Generation Intel® Core™ Processor P-core
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 1A4H, 420
MSR_PREFETCH_CONTROL
Prefetch Disable Bits (R/W)
0
L2_HARDWARE_PREFETCHER_DISABLE
If 1, disables the L2 hardware prefetcher, which fetches additional
lines of code or data into the L2 cache.
1
L2_ADJACENT_CACHE_LINE_PREFETCHER_DISABLE
If 1, disables the adjacent cache line prefetcher, which fetches the
cache line that comprises a cache line pair (128 bytes).
2
DCU_HARDWARE_PREFETCHER_DISABLE
If 1, disables the L1 data cache prefetcher, which fetches the next
cache line into L1 data cache.
3
DCU_IP_PREFETCHER_DISABLE
If 1, disables the L1 data cache IP prefetcher, which uses sequential
load history (based on instruction pointer of previous loads) to
determine whether to prefetch additional lines.
4
Reserved.
5
AMP_PREFETCH_DISABLE
If 1, disables the L2 Adaptive Multipath Probability (AMP) prefetcher.
63:6
Reserved.
Register Address: 3F7H, 1015
MSR_PEBS_FRONTEND
FrontEnd Precise Event Condition Select (R/W)
Thread
See Table 2-39.
Register Address: 540H, 1344
MSR_THREAD_UARCH_CTL
Thread Microarchitectural Control (R/W)
Thread
0
WB_MEM_STRM_LD_DISABLE
Disable streaming behavior for MOVNTDQA loads to WB memory
type. If set, these accesses will be treated like regular cacheable
loads (Data will be cached).
63:1
Reserved.
Register Address: 541H, 1345
MSR_CORE_UARCH_CTL
Core Microarchitecture Control MSR (R/W)
Core
See Table 2-44.
Register Address: D10H-D17H, 3220-3351
IA32_L2_QOS_MASK_[0-7]
IA32_CR_L2_QOS_MASK_[0-7]
Core
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] ≥ 0.
Controls MLC (L2) Intel RDT allocation. For more details on CAT/RDT, see Chapter 18, “Debug, Branch Profile, TSC, and
Intel® Resource Director Technology (Intel® RDT) Features.”
2-374 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-47. MSRs Supported by 12th and 13th Generation Intel® Core™ Processor P-core
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
19:0
WAYS_MASK
Setting a 1 in this bit X allows threads with CLOS <n> (where N is [0-
7]) to allocate to way X in the MLC. Ones are only allowed to be
written to ways that physically exist in the MLC
(CPUID.4.2:EBX[31:22] will indicate this).
Writing a 1 to a value beyond the highest way or a non-contiguous
set of 1s will cause a #GP on the WRMSR to this MSR.
31:20
Reserved.
The MSRs listed in Table 2-48 are unique to the 12th and 13th generation Intel Core processor E-core. These MSRs
are not supported on the processor P-core.
Table 2-48. MSRs Supported by 12th and 13th Generation Intel® Core™ Processor E-core
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: D10H-D1FH, 3220-3359
IA32_L2_QOS_MASK_[0-15]
IA32_CR_L2_QOS_MASK_[0-15]
Module
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] ≥ 0.
Controls MLC (L2) Intel RDT allocation. For more details on CAT/RDT, see Chapter 18, “Debug, Branch Profile, TSC, and
Intel® Resource Director Technology (Intel® RDT) Features.”
19:0
WAYS_MASK
Setting a 1 in this bit X allows threads with CLOS <n> (where N
is [0-7]) to allocate to way X in the MLC. Ones are only allowed to
be written to ways that physically exist in the MLC
(CPUID.4.2:EBX[31:22] will indicate this).
Writing a 1 to a value beyond the highest way or a non-
contiguous set of 1s will cause a #GP on the WRMSR to this MSR.
31:20
Reserved.
Register Address: 1309H-130BH, 4873
MSR_RELOAD_FIXED_CTRx
-4875
Reload value for IA32_FIXED_CTRx (R/W)
47:0
Value loaded into IA32_FIXED_CTRx when a PEBS record is
generated while PEBS_EN_FIXEDx = 1 and PEBS_OUTPUT =
01B in IA32_PEBS_ENABLE, and FIXED_CTRx is overflowed.
63:48
Reserved.
Register Address: 14C1H-14C6H, 5313 -5318
MSR_RELOAD_PMCx
Reload value for IA32_PMCx (R/W)
Core
47:0
Value loaded into IA32_PMCx when a PEBS record is generated
while PEBS_EN_PMCx = 1 and PEBS_OUTPUT = 01B in
IA32_PEBS_ENABLE, and PMCx is overflowed.
63:48
Reserved.
Table 2-49 lists the MSRs of uncore PMU for Intel processors with a CPUID Signature DisplayFamily_DisplayModel
value of 06_97H, 06_9AH, 06_BAH, 06_B7H, or 06_BFH.
Vol. 4
2-375
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-49. Uncore PMU MSRs Supported by 12th and 13th Generation Intel® Core™ Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 396H, 918
MSR_UNC_CBO_CONFIG
Uncore C-Box Configuration Information (R/O)
Package
3:0
Specifies the number of C-Box units with programmable counters
(including processor cores and processor graphics).
63:4
Reserved.
Register Address: 2000H, 8192
MSR_UNC_CBO_0_PERFEVTSEL0
Uncore C-Box 0, Counter 0 Event Select MSR
Package
Register Address: 2001H, 8193
MSR_UNC_CBO_0_PERFEVTSEL1
Uncore C-Box 0, Counter 1 Event Select MSR
Package
Register Address: 2002H, 8194
MSR_UNC_CBO_0_PERFCTR0
Uncore C-Box 0, Performance Counter 0
Package
Register Address: 2003H, 8195
MSR_UNC_CBO_0_PERFCTR1
Uncore C-Box 0, Performance Counter 1
Package
Register Address: 2008H, 8200
MSR_UNC_CBO_1_PERFEVTSEL0
Uncore C-Box 1, Counter 0 Event Select MSR
Package
Register Address: 2009H, 8201
MSR_UNC_CBO_1_PERFEVTSEL1
Uncore C-Box 1, Counter 1 Event Select MSR
Package
Register Address: 200AH, 8202
MSR_UNC_CBO_1_PERFCTR0
Uncore C-Box 1, Performance Counter 0
Package
Register Address: 200BH, 8203
MSR_UNC_CBO_1_PERFCTR1
Uncore C-Box 1, Performance Counter 1
Package
Register Address: 2010H, 8208
MSR_UNC_CBO_2_PERFEVTSEL0
Uncore C-Box 2, Counter 0 Event Select MSR
Package
Register Address: 2011H, 8209
MSR_UNC_CBO_2_PERFEVTSEL1
Uncore C-Box 2, Counter 1 Event Select MSR
Package
Register Address: 2012H, 8210
MSR_UNC_CBO_2_PERFCTR0
Uncore C-Box 2, Performance Counter 0
Package
Register Address: 2013H, 8211
MSR_UNC_CBO_2_PERFCTR1
Uncore C-Box 2, Performance Counter 1
Package
Register Address: 2018H, 8216
MSR_UNC_CBO_3_PERFEVTSEL0
Uncore C-Box 3, Counter 0 Event Select MSR
Package
Register Address: 2019H, 8217
MSR_UNC_CBO_3_PERFEVTSEL1
Uncore C-Box 3, Counter 1 Event Select MSR
Package
Register Address: 201AH, 8218
MSR_UNC_CBO_3_PERFCTR0
Uncore C-Box 3, Performance Counter 0
Package
Register Address: 201BH, 8219
MSR_UNC_CBO_3_PERFCTR1
Uncore C-Box 3, Performance Counter 1
Package
2-376 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-49. Uncore PMU MSRs Supported by 12th and 13th Generation Intel® Core™ Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Register Address: 2020H, 8224
MSR_UNC_CBO_4_PERFEVTSEL0
Uncore C-Box 4, Counter 0 Event Select MSR
Package
Register Address: 2021H, 8225
MSR_UNC_CBO_4_PERFEVTSEL1
Uncore C-Box 4, Counter 1 Event Select MSR
Package
Register Address: 2022H, 8226
MSR_UNC_CBO_4_PERFCTR0
Uncore C-Box 4, Performance Counter 0
Package
Register Address: 2023H, 8227
MSR_UNC_CBO_4_PERFCTR1
Uncore C-Box 4, Performance Counter 1
Package
Register Address: 2028H, 8232
MSR_UNC_CBO_5_PERFEVTSEL0
Uncore C-Box 5, Counter 0 Event Select MSR
Package
Register Address: 2029H, 8233
MSR_UNC_CBO_5_PERFEVTSEL1
Uncore C-Box 5, Counter 1 Event Select MSR
Package
Register Address: 202AH, 8234
MSR_UNC_CBO_5_PERFCTR0
Uncore C-Box 5, Performance Counter 0
Package
Register Address: 202BH, 8235
MSR_UNC_CBO_5_PERFCTR1
Uncore C-Box 5, Performance Counter 1
Package
Register Address: 2030H, 8240
MSR_UNC_CBO_6_PERFEVTSEL0
Uncore C-Box 6, Counter 0 Event Select MSR
Package
Register Address: 2031H, 8241
MSR_UNC_CBO_6_PERFEVTSEL1
Uncore C-Box 6, Counter 1 Event Select MSR
Package
Register Address: 2032H, 8242
MSR_UNC_CBO_6_PERFCTR0
Uncore C-Box 6, Performance Counter 0
Package
Register Address: 2033H, 8243
MSR_UNC_CBO_6_PERFCTR1
Uncore C-Box 6, Performance Counter 1
Package
Register Address: 2038H, 8248
MSR_UNC_CBO_7_PERFEVTSEL0
Uncore C-Box 7, Counter 0 Event Select MSR
Package
Register Address: 2039H, 8249
MSR_UNC_CBO_7_PERFEVTSEL1
Uncore C-Box 7, Counter 1 Event Select MSR
Package
Register Address: 203AH, 8250
MSR_UNC_CBO_7_PERFCTR0
Uncore C-Box 7, Performance Counter 0
Package
Register Address: 203BH, 8251
MSR_UNC_CBO_7_PERFCTR1
Uncore C-Box 7, Performance Counter 1
Package
Register Address: 2040H, 8256
MSR_UNC_CBO_8_PERFEVTSEL0
Uncore C-Box 8, Counter 0 Event Select MSR
Package
Register Address: 2041H, 8257
MSR_UNC_CBO_8_PERFEVTSEL1
Uncore C-Box 8, Counter 1 Event Select MSR
Package
Register Address: 2042H, 8258
MSR_UNC_CBO_8_PERFCTR0
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-49. Uncore PMU MSRs Supported by 12th and 13th Generation Intel® Core™ Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
Uncore C-Box 8, Performance Counter 0
Package
Register Address: 2043H, 8259
MSR_UNC_CBO_8_PERFCTR1
Uncore C-Box 8, Performance Counter 1
Package
Register Address: 2048H, 8264
MSR_UNC_CBO_9_PERFEVTSEL0
Uncore C-Box 9, Counter 0 Event Select MSR
Package
Register Address: 2049H, 8265
MSR_UNC_CBO_9_PERFEVTSEL1
Uncore C-Box 9, Counter 1 Event Select MSR
Package
Register Address: 204AH, 8266
MSR_UNC_CBO_9_PERFCTR0
Uncore C-Box 9, Performance Counter 0
Package
Register Address: 204BH, 8267
MSR_UNC_CBO_9_PERFCTR1
Uncore C-Box 9, Performance Counter 1
Package
Register Address: 2FD0H, 12240
MSR_UNC_ARB_0_PERFEVTSEL0
Uncore Arb Unit 0, Counter 0 Event Select MSR
Package
Register Address: 2FD1H, 12241
MSR_UNC_ARB_0_PERFEVTSEL1
Uncore Arb Unit 0, Counter 1 Event Select MSR
Package
Register Address: 2FD2H, 12242
MSR_UNC_ARB_0_PERFCTR0
Uncore Arb Unit 0, Performance Counter 0
Package
Register Address: 2FD3H, 12243
MSR_UNC_ARB_0_PERFCTR1
Uncore Arb Unit 0, Performance Counter 1
Package
Register Address: 2FD4H, 12244
MSR_UNC_ARB_0_PERF_STATUS
Uncore Arb Unit 0, Performance Status
Package
Register Address: 2FD5H, 12245
MSR_UNC_ARB_0_PERF_CTRL
Uncore Arb Unit 0, Performance Control
Package
Register Address: 2FD8H, 12248
MSR_UNC_ARB_1_PERFEVTSEL0
Uncore Arb Unit 1, Counter 0 Event Select MSR
Package
Register Address: 2FD9H, 12249
MSR_UNC_ARB_1_PERFEVTSEL1
Uncore Arb Unit 1, Counter 1 Event Select MSR
Package
Register Address: 2FDAH, 12250
MSR_UNC_ARB_1_PERFCTR0
Uncore Arb Unit 1, Performance Counter 0
Package
Register Address: 2FDBH, 12251
MSR_UNC_ARB_1_PERFCTR1
Uncore Arb Unit 1, Performance Counter 1
Package
Register Address: 2FDCH, 12252
MSR_UNC_ARB_1_PERF_STATUS
Uncore Arb Unit 1, Performance Status
Package
Register Address: 2FDDH, 12253
MSR_UNC_ARB_1_PERF_CTRL
Uncore Arb Unit 1, Performance Control
Package
Register Address: 2FDEH, 12254
MSR_UNC_PERF_FIXED_CTRL
Uncore Fixed Counter Control (R/W)
Package
2-378 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-49. Uncore PMU MSRs Supported by 12th and 13th Generation Intel® Core™ Processors
Register Address: Hex, Decimal
Register Name
Register Information / Bit Fields
Bit Description
Scope
19:0
Reserved.
20
Enable overflow propagation.
21
Reserved.
22
Enable counting.
63:23
Reserved.
Register Address: 2FDFH, 12255
MSR_UNC_PERF_FIXED_CTR
Uncore Fixed Counter
Package
43:0
Current count.
63:44
Reserved.
Register Address: 2FF0H, 12272
MSR_UNC_PERF_GLOBAL_CTRL
Uncore PMU Global Control
Package
0
Slice 0 select.
1
Slice 1 select.
2
Slice 2 select.
3
Slice 3 select.
4
Slice 4 select.
18:5
Reserved.
29
Enable all uncore counters.
30
Enable wake on PMI.
31
Enable Freezing counter when overflow.
63:32
Reserved.
Register Address: 2FF2H, 12274
MSR_UNC_PERF_GLOBAL_STATUS
Uncore PMU Main Status
Package
0
Fixed counter overflowed.
1
An ARB counter overflowed.
2
Reserved.
3
A CBox counter overflowed (on any slice).
63:4
Reserved.
2.17.6 MSRs Introduced in the Intel® Xeon® Scalable Processor Family
The Intel® Xeon® Scalable Processor Family (CPUID Signature DisplayFamily_DisplayModel value of 06_55H)
supports the MSRs listed in Table 2-50.
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
Register Address: 3AH, 58
IA32_FEATURE_CONTROL
Vol. 4
2-379
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
Control Features in Intel 64 Processor (R/W)
Thread
See Table 2-2.
0
Lock (R/WL)
1
Enable VMX Inside SMX Operation (R/WL)
2
Enable VMX Outside SMX Operation (R/WL)
14:8
SENTER Local Functions Enables (R/WL)
15
SENTER Global Functions Enable (R/WL)
18
SGX Global Functions Enable (R/WL)
20
LMCE_ENABLED (R/WL)
63:21
Reserved.
Register Address: 4EH, 78
IA32_PPIN_CTL (MSR_PPIN_CTL)
Protected Processor Inventory Number Enable Control (R/W)
Package
0
LockOut (R/WO)
See Table 2-2.
1
Enable_PPIN (R/W)
See Table 2-2.
63:2
Reserved.
Register Address: 4FH, 79
IA32_PPIN (MSR_PPIN)
Protected Processor Inventory Number (R/O)
Package
63:0
Protected Processor Inventory Number (R/O)
See Table 2-2.
Register Address: CEH, 206
MSR_PLATFORM_INFO
Platform Information
Package
Contains power management and other model specific features enumeration. See http://biosbits.org.
7:0
Reserved.
15:8
Maximum Non-Turbo Ratio (R/O)
Package
See Table 2-26.
22:16
Reserved.
23
PPIN_CAP (R/O)
Package
See Table 2-26.
27:24
Reserved.
28
Programmable Ratio Limit for Turbo Mode (R/O)
Package
See Table 2-26.
29
Programmable TDP Limit for Turbo Mode (R/O)
Package
See Table 2-26.
30
Programmable TJ OFFSET (R/O)
Package
See Table 2-26.
39:31
Reserved.
2-380 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
47:40
Maximum Efficiency Ratio (R/O)
Package
See Table 2-26.
63:48
Reserved.
Register Address: E2H, 226
MSR_PKG_CST_CONFIG_CONTROL
C-State Configuration Control (R/W)
Core
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-states. See http://biosbits.org.
2:0
Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code name (consuming the
least power) for the package. The default is set as factory-configured
package C-state limit.
The following C-state code name encodings are supported:
000b: C0/C1 (no package C-state support)
001b: C2
010b: C6 (non-retention)
011b: C6 (retention)
111b: No Package C state limits. All C states supported by the processor
are available.
9:3
Reserved.
10
I/O MWAIT Redirection Enable (R/W)
14:11
Reserved.
15
CFG Lock (R/WO)
16
Automatic C-State Conversion Enable (R/W)
If 1, the processor will convert HALT or MWAT(C1) to MWAIT(C6).
24:17
Reserved.
25
C3 State Auto Demotion Enable (R/W)
26
C1 State Auto Demotion Enable (R/W)
27
Enable C3 Undemotion (R/W)
28
Enable C1 Undemotion (R/W)
29
Package C State Demotion Enable (R/W)
30
Package C State Undemotion Enable (R/W)
63:31
Reserved.
Register Address: 179H, 377
IA32_MCG_CAP
Global Machine Check Capability (R/O)
Thread
7:0
Count.
8
MCG_CTL_P
9
MCG_EXT_P
10
MCP_CMCI_P
11
MCG_TES_P
Vol. 4
2-381
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
15:12
Reserved.
23:16
MCG_EXT_CNT
24
MCG_SER_P
25
MCG_EM_P
26
MCG_ELOG_P
63:27
Reserved.
Register Address: 17DH, 381
MSR_SMM_MCA_CAP
Enhanced SMM Capabilities (SMM-RO)
Thread
Reports SMM capability Enhancement. Accessible only while in SMM.
57:0
Reserved.
58
SMM_Code_Access_Chk (SMM-RO)
If set to 1 indicates that the SMM code access restriction is supported and
a host-space interface is available to SMM handler.
59
Long_Flow_Indication (SMM-RO)
If set to 1 indicates that the SMM long flow indicator is supported and a
host-space interface is available to SMM handler.
63:60
Reserved.
Register Address: 19CH, 412
IA32_THERM_STATUS
Thermal Monitor Status (R/W)
Core
See Table 2-2.
0
Thermal Status (R/O)
See Table 2-2.
1
Thermal Status Log (R/WC0)
See Table 2-2.
2
PROTCHOT # or FORCEPR# Status (R/O)
See Table 2-2.
3
PROTCHOT # or FORCEPR# Log (R/WC0)
See Table 2-2.
4
Critical Temperature Status (R/O)
See Table 2-2.
5
Critical Temperature Status Log (R/WC0)
See Table 2-2.
6
Thermal Threshold #1 Status (R/O)
See Table 2-2.
7
Thermal Threshold #1 Log (R/WC0)
See Table 2-2.
8
Thermal Threshold #2 Status (R/O)
See Table 2-2.
2-382 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
9
Thermal Threshold #2 Log (R/WC0)
See Table 2-2.
10
Power Limitation Status (R/O)
See Table 2-2.
11
Power Limitation Log (R/WC0)
See Table 2-2.
12
Current Limit Status (R/O)
See Table 2-2.
13
Current Limit Log (R/WC0)
See Table 2-2.
14
Cross Domain Limit Status (R/O)
See Table 2-2.
15
Cross Domain Limit Log (R/WC0)
See Table 2-2.
22:16
Digital Readout (R/O)
See Table 2-2.
26:23
Reserved.
30:27
Resolution in Degrees Celsius (R/O)
See Table 2-2.
31
Reading Valid (R/O)
See Table 2-2.
63:32
Reserved.
Register Address: 1A2H, 418
MSR_TEMPERATURE_TARGET
Temperature Target
Package
15:0
Reserved.
23:16
Temperature Target (R/O)
See Table 2-26.
27:24
TCC Activation Offset (R/W)
See Table 2-26.
63:28
Reserved.
Register Address: 1ADH, 429
MSR_TURBO_RATIO_LIMIT
This register defines the ratio limits. RATIO[0:7] must be populated in ascending order. RATIO[i+1] must be less than
Package
or equal to RATIO[i]. Entries with RATIO[i] will be ignored. If any of the rules above are broken, the configuration is
silently rejected. If the programmed ratio is:
• Above the fused ratio for that core count, it will be clipped to the fuse limits (assuming !OC).
• Below the min supported ratio, it will be clipped.
7:0
RATIO_0
Defines ratio limits.
15:8
RATIO_1
Defines ratio limits.
Vol. 4
2-383
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
23:16
RATIO_2
Defines ratio limits.
31:24
RATIO_3
Defines ratio limits.
39:32
RATIO_4
Defines ratio limits.
47:40
RATIO_5
Defines ratio limits.
55:48
RATIO_6
Defines ratio limits.
63:56
RATIO_7
Defines ratio limits.
Register Address: 1AEH, 430
MSR_TURBO_RATIO_LIMIT_CORES
This register defines the active core ranges for each frequency point. NUMCORE[0:7] must be populated in ascending
Package
order. NUMCORE[i+1] must be greater than NUMCORE[i]. Entries with NUMCORE[i] == 0 will be ignored. The last valid
entry must have NUMCORE >= the number of cores in the SKU. If any of the rules above are broken, the configuration
is silently rejected.
7:0
NUMCORE_0
Defines the active core ranges for each frequency point.
15:8
NUMCORE_1
Defines the active core ranges for each frequency point.
23:16
NUMCORE_2
Defines the active core ranges for each frequency point.
31:24
NUMCORE_3
Defines the active core ranges for each frequency point.
39:32
NUMCORE_4
Defines the active core ranges for each frequency point.
47:40
NUMCORE_5
Defines the active core ranges for each frequency point.
55:48
NUMCORE_6
Defines the active core ranges for each frequency point.
63:56
NUMCORE_7
Defines the active core ranges for each frequency point.
Register Address: 280H, 640
IA32_MC0_CTL2
See Table 2-2.
Core
Register Address: 281H, 641
IA32_MC1_CTL2
See Table 2-2.
Core
Register Address: 282H, 642
IA32_MC2_CTL2
See Table 2-2.
Core
2-384 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
Register Address: 283H, 643
IA32_MC3_CTL2
See Table 2-2.
Core
Register Address: 284H, 644
IA32_MC4_CTL2
See Table 2-2.
Package
Register Address: 285H, 645
IA32_MC5_CTL2
See Table 2-2.
Package
Register Address: 286H, 646
IA32_MC6_CTL2
See Table 2-2.
Package
Register Address: 287H, 647
IA32_MC7_CTL2
See Table 2-2.
Package
Register Address: 288H, 648
IA32_MC8_CTL2
See Table 2-2.
Package
Register Address: 289H, 649
IA32_MC9_CTL2
See Table 2-2.
Package
Register Address: 28AH, 650
IA32_MC10_CTL2
See Table 2-2.
Package
Register Address: 28BH, 651
IA32_MC11_CTL2
See Table 2-2.
Package
Register Address: 28CH, 652
IA32_MC12_CTL2
See Table 2-2.
Package
Register Address: 28DH, 653
IA32_MC13_CTL2
See Table 2-2.
Package
Register Address: 28EH, 654
IA32_MC14_CTL2
See Table 2-2.
Package
Register Address: 28FH, 655
IA32_MC15_CTL2
See Table 2-2.
Package
Register Address: 290H, 656
IA32_MC16_CTL2
See Table 2-2.
Package
Register Address: 291H, 657
IA32_MC17_CTL2
See Table 2-2.
Package
Register Address: 292H, 658
IA32_MC18_CTL2
See Table 2-2.
Package
Register Address: 293H, 659
IA32_MC19_CTL2
See Table 2-2.
Package
Register Address: 400H, 1024
IA32_MC0_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Core
Bank MC0 reports MC errors from the IFU module.
Vol. 4
2-385
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
Register Address: 401H, 1025
IA32_MC0_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Core
Bank MC0 reports MC errors from the IFU module.
Register Address: 402H, 1026
IA32_MC0_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Core
Bank MC0 reports MC errors from the IFU module.
Register Address: 403H, 1027
IA32_MC0_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Core
Bank MC0 reports MC errors from the IFU module.
Register Address: 404H, 1028
IA32_MC1_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Core
Bank MC1 reports MC errors from the DCU module.
Register Address: 405H, 1029
IA32_MC1_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Core
Bank MC1 reports MC errors from the DCU module.
Register Address: 406H, 1030
IA32_MC1_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Core
Bank MC1 reports MC errors from the DCU module.
Register Address: 407H, 1031
IA32_MC1_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Core
Bank MC1 reports MC errors from the DCU module.
Register Address: 408H, 1032
IA32_MC2_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Core
Bank MC2 reports MC errors from the DTLB module.
Register Address: 409H, 1033
IA32_MC2_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Core
Bank MC2 reports MC errors from the DTLB module.
Register Address: 40AH, 1034
IA32_MC2_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Core
Bank MC2 reports MC errors from the DTLB module.
Register Address: 40BH, 1035
IA32_MC2_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Core
Bank MC2 reports MC errors from the DTLB module.
Register Address: 40CH, 1036
IA32_MC3_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Core
Bank MC3 reports MC errors from the MLC module.
Register Address: 40DH, 1037
IA32_MC3_STATUS
2-386 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Core
Bank MC3 reports MC errors from the MLC module.
Register Address: 40EH, 1038
IA32_MC3_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Core
Bank MC3 reports MC errors from the MLC module.
Register Address: 40FH, 1039
IA32_MC3_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Core
Bank MC3 reports MC errors from the MLC module.
Register Address: 410H, 1040
IA32_MC4_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC4 reports MC errors from the PCU module.
Register Address: 411H, 1041
IA32_MC4_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC4 reports MC errors from the PCU module.
Register Address: 412H, 1042
IA32_MC4_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC4 reports MC errors from the PCU module.
Register Address: 413H, 1043
IA32_MC4_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC4 reports MC errors from the PCU module.
Register Address: 414H, 1044
IA32_MC5_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC5 reports MC errors from a link interconnect module.
Register Address: 415H, 1045
IA32_MC5_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC5 reports MC errors from a link interconnect module.
Register Address: 416H, 1046
IA32_MC5_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC5 reports MC errors from a link interconnect module.
Register Address: 417H, 1047
IA32_MC5_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC5 reports MC errors from a link interconnect module.
Register Address: 418H, 1048
IA32_MC6_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC6 reports MC errors from the integrated I/O module.
Register Address: 419H, 1049
IA32_MC6_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC6 reports MC errors from the integrated I/O module.
Vol. 4
2-387
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
Register Address: 41AH, 1050
IA32_MC6_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC6 reports MC errors from the integrated I/O module.
Register Address: 41BH, 1051
IA32_MC6_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC6 reports MC errors from the integrated I/O module.
Register Address: 41CH, 1052
IA32_MC7_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC7 reports MC errors from the M2M 0.
Register Address: 41DH, 1053
IA32_MC7_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC7 reports MC errors from the M2M 0.
Register Address: 41EH, 1054
IA32_MC7_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC7 reports MC errors from the M2M 0.
Register Address: 41FH, 1055
IA32_MC7_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC7 reports MC errors from the M2M 0.
Register Address: 420H, 1056
IA32_MC8_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC8 reports MC errors from the M2M 1.
Register Address: 421H, 1057
IA32_MC8_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC8 reports MC errors from the M2M 1.
Register Address: 422H, 1058
IA32_MC8_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC8 reports MC errors from the M2M 1.
Register Address: 423H, 1059
IA32_MC8_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC8 reports MC errors from the M2M 1.
Register Address: 424H, 1060
IA32_MC9_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 - MC11 report MC errors from the CHA.
Register Address: 425H, 1061
IA32_MC9_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 - MC11 report MC errors from the CHA.
Register Address: 426H, 1062
IA32_MC9_ADDR
2-388 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 - MC11 report MC errors from the CHA.
Register Address: 427H, 1063
IA32_MC9_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 - MC11 report MC errors from the CHA.
Register Address: 428H, 1064
IA32_MC10_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 - MC11 report MC errors from the CHA.
Register Address: 429H, 1065
IA32_MC10_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 - MC11 report MC errors from the CHA.
Register Address: 42AH, 1066
IA32_MC10_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 - MC11 report MC errors from the CHA.
Register Address: 42BH, 1067
IA32_MC10_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 - MC11 report MC errors from the CHA.
Register Address: 42CH, 1068
IA32_MC11_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 - MC11 report MC errors from the CHA.
Register Address: 42DH, 1069
IA32_MC11_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 - MC11 report MC errors from the CHA.
Register Address: 42EH, 1070
IA32_MC11_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 - MC11 report MC errors from the CHA.
Register Address: 42FH, 1071
IA32_MC11_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC9 - MC11 report MC errors from the CHA.
Register Address: 430H, 1072
IA32_MC12_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC12 report MC errors from each channel of a link interconnect module.
Register Address: 431H, 1073
IA32_MC12_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC12 report MC errors from each channel of a link interconnect module.
Register Address: 432H, 1074
IA32_MC12_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC12 report MC errors from each channel of a link interconnect module.
Vol. 4
2-389
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
Register Address: 433H, 1075
IA32_MC12_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC12 report MC errors from each channel of a link interconnect module.
Register Address: 434H, 1076
IA32_MC13_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Register Address: 435H, 1077
IA32_MC13_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Register Address: 436H, 1078
IA32_MC13_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Register Address: 437H, 1079
IA32_MC13_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Register Address: 438H, 1080
IA32_MC14_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Register Address: 439H, 1081
IA32_MC14_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Register Address: 43AH, 1082
IA32_MC14_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Register Address: 43BH, 1083
IA32_MC14_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Register Address: 43CH, 1084
IA32_MC15_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Register Address: 43DH, 1085
IA32_MC15_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Register Address: 43EH, 1086
IA32_MC15_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Register Address: 43FH, 1087
IA32_MC15_MISC
2-390 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Register Address: 440H, 1088
IA32_MC16_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Register Address: 441H, 1089
IA32_MC16_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Register Address: 442H, 1090
IA32_MC16_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Register Address: 443H, 1091
IA32_MC16_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Register Address: 444H, 1092
IA32_MC17_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Register Address: 445H, 1093
IA32_MC17_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Register Address: 446H, 1094
IA32_MC17_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Register Address: 447H, 1095
IA32_MC17_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Register Address: 448H, 1096
IA32_MC18_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Register Address: 449H, 1097
IA32_MC18_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Register Address: 44AH, 1098
IA32_MC18_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Register Address: 44BH, 1099
IA32_MC18_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Vol. 4
2-391
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal
Register Name (Former Register Name)
Register Information / Bit Fields
Bit Description
Scope
Register Address: 44CH, 1100
IA32_MC19_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC19 reports MC errors from a link interconnect module.
Register Address: 44DH, 1101
IA32_MC19_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC19 reports MC errors from a link interconnect module.
Register Address: 44EH, 1102
IA32_MC19_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC19 reports MC errors from a link interconnect module.
Register Address: 44FH, 1103
IA32_MC19_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Package
Bank MC19 reports MC errors from a link interconnect module.
Register Address: 606H, 1542
MSR_RAPL_POWER_UNIT
Unit Multipliers Used in RAPL Interfaces (R/O)
Package
3:0
Power Units
Package
See Section 15.10.1, “RAPL Interfaces.”
7:4
Reserved.
Package
12:8
Energy Status Units
Package
Energy related information (in Joules) is based on the multiplier, 1/2^ESU;
where ESU is an unsigned integer represented by bits 12:8. Default value
is 0EH (or 61 micro-joules).
15:13
Reserved.
Package
19:16
Time Units
Package
See Section 15.10.1, “RAPL Interfaces.”
63:20
Reserved.
Register Address: 618H, 1560
MSR_DRAM_POWER_LIMIT
DRAM RAPL Power Limit Control (R/W)
Package
See Section 15.10.5, “DRAM RAPL Domain.”
Register Address: 619H, 1561
MSR_DRAM_ENERGY_STATUS
DRAM Energy Status (R/O)
Package
Energy consumed by DRAM devices.
31:0
Energy in 15.3 micro-joules. Requires BIOS configuration to enable DRAM
RAPL mode 0 (Direct VR).
63:32
Reserved.
Register Address: 61BH, 1563
MSR_DRAM_PERF_STATUS
DRAM Performance Throttling Status (R/O)
Package
See Section 15.10.5, “DRAM RAPL Domain.”
Register Address: 61CH, 1564
MSR_DRAM_POWER_INFO
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