PCI/PCI-X Family of Gigabit Ethernet Controllers. Software Developer’s Manual (2009)

Initial

Field

Bit(s)

Description

Value

Device Reset

0b = normal; 1b = reset. Self clearing.

When set, it globally resets the entire Ethernet controller with

the exception of the PCI configuration registers. All registers

(receive, transmit, interrupt, statistics, etc.), and state machines

are set to their power-on reset values. This reset is equivalent to

RST

a PCI reset, with the one exception being that the PCI

configuration registers are not reset.

To ensure that global device reset has fully completed and that

the Ethernet controller responds to subsequent access, wait

approximately 1 s after setting and before attempting to check

to see if the bit has cleared or to access any other device

Receive Flow Control Enable.

When set, indicates that the Ethernet controller responds to the

reception of flow control packets. Reception and responding to

flow control packets requires matching the content of the

RFCE

Ethernet controller’s FCAL/H and FCT registers. If Auto-

Negotiation is enabled, this bit is set to the negotiated flow

control value. See Section 8.6 for more information about Auto-

Negotiation.

Transmit Flow Control Enable.

When set, indicates that the Ethernet controller transmits flow

control packets (XON and XOFF frames) based on the receive

TFCE

FIFO fullness, or when triggered to do so based on external

control pins (XOFF XON pins when FCTRH.XFCE is set). If

Auto-Negotiation is enabled, this bit is set to the negotiated flow

control value. See Auto-Negotiation for more information.

Reserved.

Reserved

Should be written with 0b to ensure future compatibility. Read as

0b.

VLAN Mode Enable

When set to 1b, all packets transmitted from the Ethernet

controller that have VLE bit set in their descriptor is sent with an

802.1Q header added to the packet. The contents of the header

come from the transmit descriptor and from the VLAN type

VME

packets and is loaded to the packet’s descriptor. See Section

9.2 for more details.

Reserved. Should be written with 0b to ensure future

compatibility.

Note: Not applicable to the 82541ER.

PHY Reset

0b = Normal.

1b = Assert hardware reset to the internal PHY.

The technique is to set the bit, wait approximately 3 s, then

PHY_RST

clear the bit. For the 82547GI/82541GI (B1 stepping), this

Note: For the 82546GB, when resetting the PHY through the

MAC, the PHY should be held in reset for a minimum of 10 ms

before releasing the reset signal.

82541xx and 82547GI/EI only.

If the signature bits of the EEPROM’s Initialization Control Word 1 match (01b), these bits are read from the EEPROM.

228

The ADVD3WUC bit (Advertise D3Cold Wakeup Capability Enable control) allows the

AUX_PWR pin to determine whether D3Cold support is advertised. If full 1 Gb/s operation in D3

state is desired but the system’s power requirements in this mode would exceed the D3Cold

Wakeup-Enabled specification limit (375 mA at 3.3 V dc), this bit can be used to prevent the

capability from being advertised to the system.

EEPROM settings allow the default PHY behavior to re-negotiate a lower functional link speed in

D3 and D0u states, when PHY operation is still needed for manageability or wakeup capability.

The EN_PHY_PWR_MGMT bit allows this capability to be disabled, in case full 1Gb/s speed is

desired in these states. The PHY is always powered-down in D3 states when unneeded for either

manageability or wakeup support.

Table 13-4. Little-Endian Data Ordering

BEM = 0 (64-bit mode; Little-Endian)

13.4.2

Device Status Register

STATUS (00008h; R)

This register provides software status indication about the Ethernet controller’s settings and modes

of operation.

Note: TBI Mode is used only by the 82544GC/EI Ethernet controller. Internal SerDes mode is used only

by the 82546GB/EB and 82545GM/EM Ethernet controllers.

229

Table 13-5. Status Register Bit Description

13 12

Reserved

Status

Initial

Field

Bit(s)

Description

Value

Link Full Duplex configuration Indication

When cleared, the Ethernet controller operates in half-duplex;

when set, the Ethernet controller operates in Full duplex.

The FD provides the duplex setting status of the Ethernet

controller as set by either Hardware Auto-Negotiation function,

or by software.

Link Up Indication

0b = no link config; 1b = link config.

For TBI mode/internal SerDes operation: If Auto-Negotiation is

enabled, this bit is set if a valid link is negotiated. If link is forced

through CTRL.SLU, it reflects the status of this control bit.

For internal PHY mode of operation: Reflects the status of the

internal link signal indicating a transition to a Link Up.

See Section 8.6 for more information about Auto-Negotiation.

Function ID.

Provides software a mechanism to determine the Ethernet

controller function number (LAN identifier) for this MAC. Read

Function ID

3:2

as: [0b,0b] LAN A, [0b,1b] LAN B.

Note: These settings are only applicable to the 82546GB/EB.

For all other Ethernet controllers, set these bits to 0b.

Transmission Paused

When set, Indicates the transmit function is in Pause state due

to reception of an XOFF pause frame when symmetrical flow

TXOFF

control is enabled. It is cleared upon expiration of the pause

timer, or receipt of an XON frame. Applicable only while working

in full-duplex flow-control mode of operation.

TBI Mode/internal SerDes Indication

When set, the Ethernet controller is configured to work in TBI

mode/internal SerDes of operation.

When clear, the Ethernet controller is configured to work in

TBIMODE

internal PHY mode.

Note: For the 82544GC/EI, reflects the status of the TBI_MODE

input pin.

For all other Ethernet controllers, set this bit to 0b.

230

Initial

Field

Bit(s)

Description

Value

Link speed setting

Indicates the configured speed of the link.

These bits are either forced by software when forcing the link

speed through the CTRL.SPEED control bits, automatically set

by hardware when Auto-Speed Detection is enabled or reflect

the internal indication inputs from the PHY.

When Auto-Speed Detection is enabled, the Ethernet

SPEED

7:6

controller’s speed is configured only once after the internal link

is asserted.

Speed indication is mapped as follows:

00b = 10 Mb/s

01b = 100 Mb/s

10b = 1000 Mb/s

11b = 1000 Mb/s

These bits are not valid in TBI mode/internal SerDes.

Auto Speed Detection Value

Indicates the speed sensed by the Ethernet controller from the

internal PHY. The ASDV status bits are provided for diagnostics

ASDV

9:8

purposes. The ASD function can be initiated by software writing

a logic 1b to the CTRL_EXT.ASDCHK bit. The resultant speed

detection is reflected in these bits. See Section 13.4.6 for

details.

Reserved

Reads as 0b.

PCI Bus speed indication

When set, indicates that the PCI bus is running at 66 MHz.

PCI66

Reflects the M66EN input pin.

Note: Not applicable to the 82547GI/EI.

PCI Bus Width indication

When set, indicates that the Ethernet controller is sitting on a

BUS64¹

64-bit PCI/PCI-X bus. BUS64 is determined by REQ64#

assertion.

PCIX_MODE¹

PCI-X Mode indication

When set to 1b, the Ethernet controller is operating in PCI-X

Mode; otherwise, the Ethernet controller is operating in

conventional PCI Mode.

PCIXSPD¹

15:14

PCI-X Bus Speed Indication

Attempts to indicate the speed of the bus when operating in a

PCI-X bus. Only valid when STATUS.PCIX_Mode = 1b.

00b = 50-66 MHz

01b = 66-100 MHz

10b = 100-133 MHz

11b = Reserved

Reserved

31:16

Reserved

Reads as 0b.

Not applicable to the 82540EP/EM, 82541xx, or 82547GI/EI.

231

13.4.3

EEPROM/Flash Control & Data Register

EECD (00010h; R/W)

This register provides a simplified interface for software accesses to the EEPROM. Software

controls the EEPROM by successive writes to this register.

Data and address information is clocked into the EEPROM by software toggling the EECD.SK bit

(2) of this register with EECD.CS set to 1b.

Data output from the EEPROM is latched into bit 3 of this register and can be accessed by software

through reads of this register.

See Section 5 for more detailed EEPROM information.

Table 13-6. EECD Register Bit Description

31 - 10

Reserved

SIZE

PRES

GNT

REQ

FWE

82544GC/EI Only

6 5

Reserved

FWE

Initial

Field

Bit

Description

Value

Clock input to the EEPROM

The EESK output signal is mapped to this bit and provides the

serial clock input to the EEPROM. Software clocks the EEPROM

by means of toggling this bit with successive writes to EECD.

Chip select input to the EEPROM

The EECS output signal is mapped to the chip select of the

EEPROM device. Software enables the EEPROM by writing a 1b

to this bit.

Data input to the EEPROM

The EEDI output signal is mapped directly to this bit. Software

provides data input to the EEPROM through writes to this bit.

Data output bit from the EEPROM

The EEDO input signal is mapped directly to this bit in the register

and contains the EEPROM data output. This bit is read-only from

the software perspective - writes to this bit have no effect.

Flash Write Enable Control

These two bits, control whether writes to Flash memory are

allowed.

FWE

5:4

01b

00b = Not allowed

01b = Flash writes disabled

10b = Flash writes enabled

11b = Not allowed

232

Initial

Field

Bit

Description

Value

Request EEPROM Access

The software must write a 1b to this bit to get direct EEPROM

EE_REQ

6¹

access. It has access when EE_GNT is 1b. When the software

completes the access it must write a 0b.

Grant EEPROM Access

EE_GNT

7¹

When this bit is 1b the software can access the EEPROM using the

SK, CS, DI, and DO bits.

EEPROM Present

This bit indicates that an EEPROM is present by monitoring the

EE_PRES

8¹

0b²

EEDO input for a active-low acknowledge by the serial EEPROM

during initial EEPROM scan. 1b = EEPROM present.

EEPROM Size

0b = 1024-bit (64 word) NM93C46 compatible EEPROM

1b = 4096-bit (256 word) NM93C66 compatible EEPROM

EE_SIZE

9¹

This bit indicates the EEPROM size, based on acknowledges seen

during EEPROM scans of different addresses. This bit is read-only.

Note: This is a reserved bit for the 82541xx and 82547GI/EI.

EEPROM Size (82541xx and 82547GI/EI)

For Microwire EEPROMs:

0b = 6-bit addressable (64 words).

EE_SIZE

10¹

1b = 8-bit addressable (256 words).

For SPI EEPROMs:

0b = 8-bit addressable.

1b = 16-bit addressable.

Reserved

12:11

00b

Should be written with 0b to ensure future compatibility. Reads as

0b.

EEPROM Type: Reflects the EE_MODE pin. (82541xx and

82547GI/EI)

EE_TYPE

13¹

0b = Microwire.

1b = SPI.

Reserved

31:14

Should be written with 0b to ensure future compatibility. Reads as

0b.

Not applicable to the 82544GC/EI.

82541xx and 82547GI/EI only.

This register provides software direct access to the EEPROM. Software can control the EEPROM

by successive writes to this register. Data & address information is clocked into the EEPROM by

software toggling the EESK bit (2) of this register with EECS set to 1b. Data output from the

EEPROM is latched into bit 3 of this register via the internal 62.5 MHz clock and can be accessed

by software via reads of this register.

Note: Attempts to write to the FLASH device when writes are disabled (FEW = 01b) should not be

attempted. Behavior after such an operation is undefined, and can result in component and/or

system hangs.

233

13.4.4

EEPROM Read Register¹

EERD (00014h; RW)

Table 13-7. EEPROM Read Register Bit Description

Data

Address

RSV.

DONE

RSV.

START

Initial

Field

Bit(s)

Description

Value

Start Read

Writing a 1b to this bit causes the EEPROM to read a (16-bit) word at

START

the address stored in the EE_ADDR field and then storing the result in

the EE_DATA field. This bit is self-clearing.

Reserved

3:1

Reserved. Reads as 0b.

Read Done

Set to 1b when the EEPROM read completes.

DONE

Set to 0b when the EEPROM read is in progress.

Writes by software are ignored.

Reserved

7:5

Reserved. Reads as 0b.

Read Address

ADDR

15:8

This field is written by software along with Start Read to indicate the

word to read.

DATA

31:16

Read Data. Data returned from the EEPROM read.

Not applicable to the 82544GC/EI.

234

Table 13-8. EEPROM Read Register Bit Description (82541xx and 82547GI/EI)

Data

Address

DONE

START

Initial

Field

Bit(s)

Description

Value

Start Read

Writing a 1b to this bit causes the EEPROM to read a (16-bit) word at

START

the address stored in the EE_ADDR field and then storing the result in

the EE_DATA field. This bit is self-clearing.

Read Done

Set to 1b when the EEPROM read completes.

DONE

Set to 0b when the EEPROM read is in progress.

Writes by software are ignored.

Read Address

ADDR

15:2

This field is written by software along with Start Read to indicate the

word to read.

DATA

31:16

Read Data. Data returned from the EEPROM read.

This register is used by software to cause the Ethernet controller to read individual words in the

EEPROM. To read a word, software writes the address to the Read Address field and simultane-

ously writes a 1b to the Start Read field. The Ethernet controller reads the word from the EEPROM

and places it in the Read Data field, setting the Read Done filed to 1b. Software can poll this

When this register is used to read a word from the EEPROM, that word is not written to any of

Ethernet controller’s internal registers even if it is normally a hardware accessed word.

Note: If software has requested direct pin control of the EEPROM using the EEC register, an access

through the EERD register mechanism can stall until the EEC control has been released. Software

should ensure that EEC.EE_REQ = 0b and that EEC.EE_GNT = 0b as well before attempting to

use EERD to access the EEPROM.

235

13.4.5

Flash Access¹

FLA (0001Ch; R/W)

This register provides software direct access to the Flash memory. Software can control the Flash

device by successive writes to this register. Data and address information is clocked into the Flash

memory by software toggling the FL_SCK bit (0) of this register with FL_CE set to 1b. Data

output from the Flash memory is latched into bit three of this register via the internal 125 MHz

clock and is accessed by software via reads of this register.

Table 13-9. Flash Access - FLA

29 - 6

Reserved

GNT

REQ

SCK

Initial

Field

Bit(s)

Description

Value

Clock Input to the FLASH.

When FL_GNT is 1b, the FL_SCK out signal is mapped to this bit and

FL_SCK

provides the serial clock input to the Flash device. Software clocks the

Flash memory via toggling this bit with successive writes.

Chip FL Input to the FLASH.

When FL_GNT is 1b, the FL_CS output signal is mapped to the chip

FL_CE

select of the device. Software enables the FLASH by writing a 0b to this

bit.

Data Input to the FLASH.

FL_SI

When FL_GNT is 1b, the FL_DI output signal is mapped directly to this

bit. Software provides data input to the FLASH via writes to this bit.

Data Output Bit from the FLASH.

The FL_SO input signal is mapped directly to this bit in the register and

FL_SO

contains the Flash memory serial data output. This bit is read only from

the software perspective - writes to this bit have no effect.

Request FLASH Access.

The software must write a 1b to this bit to get direct Flash memory

FL_REQ

access. It has access when FL_GNT is 1b. When the software

completes the access it must write a 0b.

Grant FLASH Access.

FL_GNT

When this bit is 1b, the software can access the Flash memory using

the FL_SCK, FL_CE, FL_SI, and FL_SO bits.

Reserved.

Reserved

29:6

Reads as 0b.

Flash Busy.

This bit is set to 1b while a write or an erase to the Flash memory is in

FL_BUSY

progress. While this bit is clear (read as 0b) software can access to

write a new byte to the Flash device.

Flash Erase Command.

FL_ER

This command will be sent to the Flash component only if bits 5:4 are

also set. This bit is automatically cleared and read as 0b.

Applicable to the 82541xx and 82547GI/EI only.

236

13.4.6

Extended Device Control Register

CTRL_EXT (00018h, R/W)

This register and the Device Control register (CTRL) controls the major operational modes for the

Ethernet controller. CTRL_EXT provides extended control of the Ethernet controller functionality

over the Device Control register (CTRL).

Note: See Table 13-12 and Table 13-13 for the 82544GC/EI.

Table 13-10. CTRL_EXT Register Bit Description

31 - 24

23 - 16 15

Reserved

Extended Device Control Bits

Initial

Field

Bit(s)

Description

Value

Reserved bits for the 82541xx and 82547GI/EI. Should be written

Reserved

1:0

as 0b to ensure future compatibility.

General Purpose Interrupt Enables

These bits determine whether the upper three software definable

pins SDP[7:6] and SDP[4] are mapped to the ICR.GPI interrupt

GPI_EN

3:0

bits. These mappings are enabled only when the SDP[7:6] and

SDP[4] pins are configured as inputs through

CTRL_EXT.SWDPIOHI. Refer to Table 13-11 for SDP to ICR.GPI

bit mapping.

General Purpose Interrupt Enables for the 82541xx and 82547GI/

EI.

These bits determine whether the upper software definable pins

GPI_EN

3:2

SDP[3:2] are mapped to the ICR.GPI interrupt bits. These

mappings are enabled only when the SDP[3:2] pins are configured

as inputs through CTRL_EXT.SWDPIOHI. Refer to Table 13-11 for

SDP to ICR.GPI bit mapping.

Reserved

Reserved. Formally used as SDP4 pin data value. Reads as 0b.

PHY Interrupt Value. When read, returns the current value of the

PHYINT

PHY internal interrupt status PHYINT.

Note: This is a reserved bit for the 82541xx and 82547GI/EI.

SDP6_DATA

SDP6[2] Data Value. Used to read (write) value of software-

controllable IO pin SDP6[2]. If SDP6[2] is configured as an output

SDP2_DATA

0b¹

(SDP6[2]_IODIR = 1b), this bit controls the value driven on the pin

(82541xx and

(initial value EEPROM-configurable). If SDP6[2] is configured as

82547GI/EI)

an input, reads return the current value of the pin.

SDP7_DATA

SDP7[3] Data Value. Used to read (write) value of software-

controllable IO pin SDP7[3]. If SDP7[3] is configured as an output

SDP3_DATA

0b¹

(SDP7[3]_IODIR = 1b), this bit controls the value driven on the pin

(82541xx and

(initial value EEPROM-configurable). If SDP7[3] is configured as

82547GI/EI)

an input, reads return the current value of the pin.

Reserved

9:8

01b

Should be written as 01b to ensure future compatibility.

237

Initial

Field

Bit(s)

Description

Value

SDP6_IODIR

SDP6[2] Pin Directionality. Controls whether software-controllable

pin SDP6[2] is configured as an input or output (0b = input, 1b =

SDP2_IODIR

0b¹

output). Initial value is EEPROM-configurable. This bit is not

(82541xx and

affected by software or system reset, only by initial power-on or

82547GI/EI)

direct software writes.

SDP7_IODIR

SDP7[2] Pin Directionality. Controls whether software-controllable

pin SDP7[2] is configured as an input or output (0b = input, 1b =

SDP2_IODIR

0b¹

output). Initial value is EEPROM-configurable. This bit is not

(82541xx and

affected by software or system reset, only by initial power-on or

82547GI/EI)

direct software writes.

ASD Check

Initiate an Auto-Speed-Detection (ASD) sequence to sense the

frequency of the PHY receive clock. The results are reflected in

ASDCHK

STATUS.ASDV. This bit is self-clearing.

This functionality is provided for diagnostic purposes, regardless of

whether the Auto Speed Detection feature is enabled. This bit is

applicable only for internal PHY mode of operation.

EEPROM Reset

When set, initiates a reset-like event to the EEPROM function. This

EE_RST

causes the EEPROM to be read as if a RST# assertion had

occurred. All device functions should be disabled prior to setting

this bit. This bit is self-clearing.

Reserved

0b¹

Reserved. Should be set to 0b.

Speed Select Bypass

When set to 1b, all speed detection mechanisms are bypassed,

and the Ethernet controller is immediately set to the speed

indicated by CTRL.SPEED. This can be used to override the

SPD_BYPS

hardware clock switching circuitry and give full control to software.

SPD_BYPS differs from the CTRL.FRCSPD function in that

FRCSPD uses the internal clock switching circuitry rather than an

immediate forcing function of the speed settings, as does

SPD_BYPS.

Reserved

0b¹

Reserved. Should be set to 0b.

Relaxed Ordering Disabled

When set to 1b, the Ethernet controller does not request any

relaxed ordering transactions in PCI-X mode regardless of the

state of bit 1 in the PCI-X command register. When this bit is clear

RO-DIS

and bit 1 of the PCI-X command register is set, the Ethernet

controller requests relaxed ordering transactions.

Note: This is a reserved bit for the 82540EP/EM, 82541xx, and

82547GI/EI. Set to 0b.

Reserved

20:18

Should be written with 0b to ensure future compatibility.

Reads as 0b.

238

Initial

Field

Bit(s)

Description

Value

Voltage Regulator Power Down (82541xx and 82547GI/EI only)

0b = Normal operation.

VREG POWER

1b = Voltage regulators power down.

DOWN

This bit is initialized from the EEPROM.

Note: This is a reserved bit for all remaining Ethernet controllers.

Set to 0b.

Link Mode. This controls which interface is used to talk to the link.

00b = Direct copper (1000Base-T) interface (GMII/MII internal PHY

mode)

01b = Reserved

LINK_MODE

23:22

10b = Direct Fiber interface (using internal SerDes)

11b = external TBI interface

Note: These are reserved bits for the 82540EP/EM, 82541xx, and

82547GI/EI. Set to 00b

Reserved

31:24

Should be written with 0b to ensure future compatibility.

Reads as 0b.

These bits are read from the EEPROM

The Ethernet controller allows for up to two externally controlled interrupts. The upper two

software-definable pins, SDP[7:6] (SDP[3:2] for the 82541xx and 82547GI/EI), can be mapped

for use as GPI interrupt bits. These mappings are enabled by the SDPx_GPIEN bits only when

these signals are also configured as inputs via SDPx_IODIR. When configured to function as

external interrupt pins, a GPI interrupt is generated when the corresponding pin is sampled in an

active-high state.

The bit mappings are shown in Table 13-11 for clarity.

Table 13-11. GPI to SDP Bit Mappings

SDP pin to be used as

Resulting ICR bit

CTRL_EXT field settings

GPI

(GPI)

Directionality

Enable as GPI interrupt

SDP7_IODIR

SDP7_GPIEN

2¹

SDP2_IODIR¹

SDP2_GPIEN¹

SDP6_IODIR

SDP6_GPIEN

3¹

SDP3_IODIR¹

SDP3_GPIEN¹

82541xx and 82547GI/EI only

239

Table 13-12. 82544GC/EI CTRL_EXT Register Bit Description

16 15

Reserved

Extended Device Control Bits

Initial

Field

Bit(s)

Description

Value

General Purpose Interrupt Enables

These bits determine whether the upper three software

definable pins SDP[7:6] and SDP[4] are mapped to the ICR.GPI

GPI_EN

3:0

interrupt bits. These mappings are enabled only when the

SDP[7:6] and SDP[4] pins are configured as inputs through

CTRL_EXT.SWDPIOHI. Refer to Table 13-13 for SDP to

ICR.GPI bit mapping.

Software Defined Pins - high nibble

These three bits allow direct control of SDP[7:6] and SDP[4].

These pins can be either input pins or output pins as

SWDPINSHI

7:6, 4

determined by the SWDPIOHI bits. The initial direction of the

software defined pins is read out of the EEPROM.

Note: SDP[5] and its associated bit is not used. It should be

programmed to 0b for future compatibility.

Software Defined Pins Input or Output

These three bits control whether each of the high nibble

software defined pins SDP[7:6] and SDP[4] is used as an input

or an output.

0b = inputs; 1b = outputs.

SWDPIOHI

11:10, 8

This field is not affected by assertion of software reset

(CTRL.RST).

Configurable through EEPROM.

Note: SDP[5] and its associated bit is not used. It should be

programmed to 0b for future compatibility.

ASD Check

Initiate an Auto-Speed-Detection (ASD) sequence to sense the

frequency of the PHY receive clock. The results are reflected in

STATUS.ASDV. This bit is self-clearing.

ASDCHK

This functionality is provided for diagnostic purposes,

regardless of whether the Auto Speed Detection feature is

enabled. This bit is applicable only for internal PHY mode of

operation.

EEPROM Reset

When set, initiates a “reset-like” event to the EEPROM function.

EE_RST

This causes the EEPROM to be read as if a RST# assertion had

occurred. All Ethernet controller functions should be disabled

prior to setting this bit. This bit is self-clearing.

Invert Power State Bit 0

When set to 1b, inverts the assertion polarity of the

IPS

PWR_STATE bit 0 output. When cleared to 0b, PWR_STATE is

logic high in normal operation.

Configurable through EEPROM.

240

Initial

Field

Bit(s)

Description

Value

Speed Select Bypass

When set to 1b, all speed detection mechanisms are bypassed,

and the Ethernet controller is immediately set to the speed

indicated by CTRL.SPEED. This might be used to override the

SPD_BYPS

hardware clock switching circuitry and give full control to

software. SPD_BYPS differs from the CTRL.FRCSPD function

in that FRCSPD uses the internal clock switching circuitry rather

than an immediate forcing function of the speed settings, as

does SPD_BYPS.

Invert Power State Bit 1

Inverts the polarity of bit 1 of the PWR_STATE signal when set

IPS1

to 1b.

Configurable through the EEPROM.

Relaxed Ordering Disabled

When set to 1b, the Ethernet controller does not request any

relaxed ordering transactions in PCI-X mode regardless of the

RO-DIS

state of bit 1 in the PCI-X command register. When this bit is

clear and bit 1 of the PCI-X command register is set, the

Ethernet controller requests relaxed ordering transactions as

described.

Reserved

31:18

Should be written with 0b to ensure future compatibility.

Reads as 0b.

Table 13-13. 82544GC/EI GPI to SDP Bit Mapping

CTRL_EXT

ICR

B_SDP

(SWDPINHI)

(GPI_EN)

(GPI)

Reserved

241

13.4.7

MDI Control Register

MDIC (00020h; R/W)

Software uses this register to read or write Management Data Interface (MDI) registers in the

internal PHY.

To read a location in the PHY, first perform an MDI write cycle with the following bit settings:

• Ready = 0b

• Interrupt Enable programmed to 1b or 0b

• Opcode = 10b (read)

• PHYADD = PHY address from the MDI register

• REGADD = Register address within the PHY to be read

When the serial data transfer from PHY to MAC is complete, the Ethernet controller issues an

interrupt if the MDI interrupt is enabled. The Ethernet controller also sets the Ready bit. This

indication tells the system that the read data is available from the 16-bit data field in the MDI

Control register. Perform a second read operation to the register at this time to recover the data.

To write a location in the PHY, perform an MDI write cycle with the following bit settings:

• Ready = 0b

• Interrupt Enable programmed to 1b or 0b

• Opcode = 01b (write)

• PHYADD = PHY address from the MDI register

• REGADD = Register address within the PHY to be written

• Data = Specific data for PHY operation

If enabled, the Ethernet controller issues an interrupt when the write completes. The Ethernet

controller also sets the Ready bit, denoting that a subsequent operation can be carried out.

Note:

The internal PHY register bit descriptions follow Table 13-14.

242

Table 13-14. MDI Control Register Bit Description

16 15

RSV

PHY

REG

DATA

Initial

Field

Bit(s)

Description

Value

Data

In a Write command, software places the data bits and the

DATA

15:0

Ethernet controller shifts them out to the PHY. In a Read

command, the Ethernet controller reads these bits serially from

the PHY and software can read them from this location.

REGADD

20:16

PHY Register Address: Reg. 0, 1, 2, ...31

PHY Address

PHYADD

25:21

The Internal PHY’s MDI address for each MAC is 0001b

Opcode

01b = MDI Write

27:26

10b = MDI Read

All other values are reserved.

Ready Bit

Set to 1b by the Ethernet controller at the end of the MDI

transaction (for example, indication of a Read or Write

completion). It should be reset to 0b by software at the same

time the command is written.

Interrupt Enable

When set to 1b by software, it causes an Interrupt to be

asserted to indicate the end of an MDI cycle.

Error

This bit is set to 1b by hardware when it fails to complete an

MDI read. Software should make sure this bit is clear (0b)

before issuing an MDI read or write command.

Reserved

Reads as 0b.

243

13.4.7.1

PHY Registers

This document uses a special nomenclature to define the read/write mode of individual bits in each

For all binary equations appearing in the register map, the symbol “|” is equivalent to a binary OR

operation.

Table 13-15. PHY Register Bit Mode Definitions

Description

Latched High. Event is latched and erased when read.

Latched Low. Event is latched and erased when read. For

example, Link Loss is latched when the PHY Control

Control Register bit 2 is set to 1b.

Read Only.

R/W

Read and Write.

Self-Clear. The bit is set, automatically executed, and then

reset to normal operation.

Clear after Read. For example, 1000BASE-T Status

Value written to the register bit does not take effect until

Update

software PHY reset is executed.

244

13.4.7.1.1

PHY Control Register

PCTRL (00d; R/W)

Table 13-16. PHY Control Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

These bits are reserved and should be

Always

Reserved

5:0

set to 000000b.

RW¹

000000b

Speed Selection is determined by bits 6

(MSB) and 13 (LSB) as follows.

11b = Reserved

10b = 1000 Mbps

01b = 100 Mbps

00b = 10 Mbps

A write to these bits do not take effect

until a software reset is asserted,

Restart Auto-Negotiation is asserted, or

Speed Selection

Power Down transitions from power

R/W

Update

(MSB)

down to normal operation.

82544GC/EI only:

The Speed Selection bits take on the

ANEG[3:2]

values set by external pins ANEG[3:0]

MODE[3:0]

on hardware reset only.

Bit 6: ANEG[3] | ANEG[2] | (MODE[3:0]

is one of xx01b, 1x00b, 001xb, 0111b).

Bit 13: (ANEG[3:1] = 001b) and

(MODE[3:0] is not any of xx01b, 1x00b,

001xb, 0111b).

1b = Enable COL signal test.

Collision Test

R/W

0b = Disable COL signal test.

1b = Full Duplex.

0b = Half Duplex.

82544GC/EI only:

The Duplex bit takes on the value set by

external pins ANEG[3:2, 0] on hardware

reset only.

Duplex Mode

R/W

Update

Bit 8: ANEG[3:2,0] = 001 | ANEG[3].

A write to this bit does not take effect

ANEG[3:2,

until a software reset is asserted,

Restart Auto-Negotiation is asserted, or

Power Down transitions from power

down to normal power.

1b = Restart Auto-Negotiation Process.

0b = Normal operation.

Restart Auto-

Auto-Negotiation automatically restarts

R/W,

Self

Negotiation

after hardware or software reset

Clear

regardless of whether or not the restart

bit is set.

1b = Isolate.

Isolate

R/W

0b = Normal operation.

245

Table 13-16. PHY Control Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

1b = Power down.

0b = Normal operation.

Power down shuts down the Ethernet

controller except for the MAC interface if

the MAC interface power down bit is set

to 1b. If it equals 0b, then the MAC

interface also shuts down. For the

82544GC/EI, power down has no effect

on the 125CLK output if the Disable

125CLK bit is set to 0b.

NOTE: Setting this bit to 1b will prevent

wakeup by detecting circuitry

on the CAT5 cable. To enable

Power Down

R/W

wakeup, this bit must be written

back to 0b.

82544GC/EI only:

If bit 12 is set to 0b and speed is

manually forced to 1000 Mb/s in bits 13

and 6, then Auto-Negotiation is still

enabled and only 1000BASE-T full

duplex is advertised if bit 8 is set to 1b.

1000BASE-T half duplex is advertised if

bit 8 is cleared (0b). Duplex settings in

other registers are ignored. Auto-

Negotiation is required by IEEE for

proper operation in 1000BASE-T.

246

Table 13-16. PHY Control Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

1b = Enable Auto-Negotiation Process.

0b = Disable Auto-Negotiation Process.

A write to this bit does not take effect

until a software reset is asserted,

Restart Auto-Negotiation is asserted, or

Power Down transitions from power

down to normal operation.

When the port is switched from power

down to normal operation, software

reset and restart Auto-Negotiation are

performed even if bits Reset and Restart

Auto-Negotiation are not set by the

R/W

Update

programmer.

If bit 12 is set to 0b and speed is

manually forced to 1000 Mbps in bits 13

and 6, then Auto-Negotiation is still

enabled and only 1000BASE-T full

Auto-Negotiation

duplex is advertised if bit 8 is set to 1b.

Enable

1000BASE-T half duplex is advertised if

bit 8 is cleared (0b). Duplex settings in

other registers are ignored. Auto-

Negotiation is required by IEEE for

proper operation in 1000BASE-T.

82544GC/EI only:

R/W

ANEG[3:2]

Update

Auto-Negotiation enable takes on the

ENA_XC

value set by external pins ANEG[3:0] on

hardware reset only.

Bit 12: ANEG[3:2] = 11b.

If MODE[3:0] equals 001xb or 0111b,

where x equals either 0b or 1b, then the

ANE bit determines whether

1000BASE-X Auto-Negotiation is on or

off. Otherwise ANE determines whether

10/100/1000BASE-T Auto-Negotiation

is on or off.

R/W

Update

Speed Selection

See Speed Selection (MSB), bit 6.

ANEG[3:1]²

(LSB)

MODE[3:0]

1b = Enable loopback.

Loopback

R/W

0b = Disable loopback.

1b = PHY reset.

R/W,

Self

Reset

0b = Normal operation.

Clear

82541xx and 82547GI/EI only.

82544GC/EI only.

247

13.4.7.1.2

PHY Status Register

PSTATUS (01d; R)

Table 13-17. PHY Status Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

Extended Capability

1b = Extended register capabilities.

Always 1b

1b = Jabber condition detected.

RO,L

Jabber Detect

0b = Jabber condition not detected.

1b = Link is up.

0b = Link is down.

This register indicates whether link was

lost after the last read. For the current

RO,

Link Status

link status, either read this register

back-to-back or read the Link Real Time

bit 17 in the PHY Specific Status

Auto-Negotiation

1b = PHY able to perform Auto-

Always 1b

Ability

Negotiation.

1b = Remote fault condition detected.

RO,L

Remote Fault

0b = Remote fault condition not

detected.

1b = Auto-Negotiation process

Auto-Negotiation

complete.

Complete

0b = Auto-Negotiation process not

complete.

Always 1b

MF Preamble

1b = PHY accepts management frames

(0b for the 82541xx

Suppression

with preamble suppressed.

and 82547GI/EI)

Reserved

Reserved. Should be set to 0b

Always 0b

1b = Extended status information in the

Extended Status

Always 1b

Extended PHY Status Register (15d).

100BASE-T2 Half

0b = PHY not able to perform half

Always 0b

Duplex

duplex 100BASE-T2.

100BASE-T2 Full

0b = PHY not able to perform full duplex

Always 0b

Duplex

100BASE-T2.

1b = PHY able to perform half duplex

10BASE-T.

0b = PHY not able to perform half

duplex 10BASE-T.

10 Mb/s Half Duplex

82544GC/EI only:

Bit 14 = Bit 13 = Bit 12 = Bit 11 =

MODE[3:0]

(MODE[3:0] is not any of xx01b, 1x00b,

001xb, 0111b).

248

Table 13-17. PHY Status Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

1b = PHY able to perform full duplex

10BASE-T.

0b = PHY not able to perform full duplex

10BASE-T.

10 Mb/s Full Duplex

82544GC/EI only:

Bit 14 = Bit 13 = Bit 12 = Bit 11 =

MODE[3:0]

(MODE[3:0] is not any of xx01b, 1x00b,

001xb, 0111b).

1b = PHY able to perform half duplex

100BASE-X.

0b = PHY able to perform half duplex

100BASE-X Half

100BASE-X.

Duplex

82544GC/EI only:

Bit 14 = Bit 13 = Bit 12 = Bit 11 =

MODE[3:0]

(MODE[3:0] is not any of xx01b, 1x00b,

001xb, 0111b).

1b = PHY able to perform full duplex

100BASE-X.

0b = PHY not able to perform full duplex

100BASE-X Full

100BASE-X.

Duplex

82544GC/EI only:

Bit 14 = Bit 13 = Bit 12 = Bit 11 =

MODE[3:0]

(MODE[3:0] is not any of xx01b, 1x00b,

001xb, 0111b).

0b = PHY not able to perform 100BASE-

100BASE-T4

Always 0b

T4.

249

13.4.7.1.3

PHY Identifier Register (LSB)

PID (02d; R)

Table 13-18. PHY Identifier Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

0000_0001_0100_0001b

Always 0141h

OUI is 005043h.

Organizationally

Unique Identifier Bit

15:0

The PHY identifier composed of bits 3

18:3¹

Always 02A8h²

through 18 of the OUI (Organizationally

Unique Identifier)²

PHY ID number for the 82541xx and 82547GI/EI only.

82541xx and 82547GI/EI only.

13.4.7.1.4

Extended PHY Identifier Register (MSB)

EPID (03d; R)

Table 13-19. Extended PHY Identifier Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

Contains the current revision number.

Always static

Revision Number

3:0

4 bits containing the manufacturer’s

00h¹

revision number.¹

000010b = 10/100/1000 Copper PHY.

Always 000010b

82544GC/EI only:

Model Number

9:4

000011b = 10/100/1000 Copper PHY.

Always 000011b

6 bits containing the manufacturer’s part

Always 111000b¹

number¹

Organizationally

Unique Identifier Bit

000011b.

Always 000011b

19:24

15:10

(PHY ID Number for

The PHY identifier composed of bits 19

0h¹

the 82541xx and

through 24 of the OUI¹

82547GI/EI)

82541xx and 82547GI/EI only.

250

13.4.7.1.5

Auto-Negotiation Advertisement Register

ANA (04d; R/W)

Table 13-20. Auto-Negotiation Advertisement Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

00001b = 802.3

For the 82541xx and 82547GI/EI:

Other combinations are reserved.

Always 00001b

Selector Field

4:0

Unspecified or reserved combinations

should not be transmitted.

Note: Setting this field to a value other

than 00001b can cause auto

negotiation to fail.

1b = Advertise.

0b = Not advertised.

Values programmed in the Auto-

Negotiation Advertisement Register

have no effect unless Auto-

Negotiation is restarted (PHY Control

10BASE-TX Half

Duplex

This bit can be overridden by the PHY

R/W

Retain

Control Register.

82544GC/EI only:

10Base-T (82541xx

ANEG[3:1]

and 82547GI/EI)

Bit 5: (ANEG[3:0] = 0000b |

MODE[3:0]

ANEG[3:2] = 11b) and (MODE[3:0] is

not any of xx01b, 1x00b, 001xb,

0111b).

82541xx and 82547GI/EI only:

1b = DTE is 10BASE-T capable.

0b = DTE is not 10BASE-T capable.

1b = Advertise.

0b = Not advertised.

Values programmed in the Auto-

Negotiation advertisement register

have no effect unless Auto-

Negotiation is restarted (PHY Control

10BASE-TX Full

This bit can be overridden by the PHY

Duplex

Control Register.

R/W

Retain

82544GC/EI only:

10Base-T Full Duplex

Bit 5: (ANEG[3:0] = 0001b |

(82541xx and

ANEG[3:0]

ANEG[3:2] = 11b) and (MODE[3:0] is

82547GI/EI)

not any of xx01b, 1x00b, 001xb,

MODE[3:0]

0111b).

82541xx and 82547GI/EI only:

1b = DTE is 10BASE-T full duplex

capable.

0b = DTE is not 10BASE-T full duplex

capable.

251

Table 13-20. Auto-Negotiation Advertisement Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

1b = Advertise.

0b = Not advertised.

Values programmed in the Auto-

Negotiation advertisement register

have no effect unless Auto-

Negotiation is restarted (PHY Control

100BASE-TX Half

Duplex

This bit can be overridden by the PHY

R/W

Retain

Control Register.

82544GC/EI only:

100Base-TX

(82541xx and

Bit 5: (ANEG[3:0] = 0010b |

ANEG[3:1]

82547GI/EI)

ANEG[3:2] = 11b) and (MODE[3:0] is

MODE[3:0]

not any of xx01b, 1x00b, 001xb,

0111b).

82541xx and 82547GI/EI only¹:

1b = DTE is 100BASE-TX capable.

0b = DTE is not 100BASE-TX

capable.

1b = Advertise.

0b = Not advertised.

Values programmed in the Auto-

Negotiation advertisement register

have no effect unless Auto-

Negotiation is restarted (PHY Control

This bit can be overridden by the PHY

Control Register.

R/W

Retain

100BASE-TX Full

82544GC/EI only:

Duplex

ANEG[3:0]

Bit 8: (ANEG[3:0] = 0011b |

MODE[3:0]

ANEG[3:2] = 11b) and (MODE[3:0] is

not any of xx01b, 1x00b, 001xb,

0111b).

82541xx and 82547GI/EI only:¹

1b = DTE is 100BASE-TX full duplex

capable.

0b = DTE is not 100BASE-TX full

duplex capable.

100BASE-T4

0b = Not capable of 100BASE-T4.

Always 0b

1b = MAC PAUSE implemented.

0b = MAC PAUSE not implemented.

Values programmed in the Auto-

Negotiation advertisement register

have no effect unless Auto-

1b for the

PAUSE

Negotiation is restarted (PHY Control

R/W

Retain

(82541xx

and

82541xx and 82547GI/EI only:

82547GI/

EI)

Advertise to Partner that Pause

operation (as defined in 802.3x) is

desired.

252

Table 13-20. Auto-Negotiation Advertisement Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

1b = Asymmetric Pause.

0b = No asymmetric Pause.

Values programmed in the Auto-

Asymmetric Pause

Negotiation advertisement register

have no effect unless Auto-

1b for the

Negotiation is restarted (PHY Control

R/W

Retain

ASM_DIR for the

(82541xx

(82541xx and

and

82547GI/EI)

82541xx and 82547GI/EI only:

82547GI/

EI)

Advertise Asymmetric Pause direction

bit. This bit is used in conjunction with

PAUSE.

This bit is reserved and equals 0b.

Values programmed in the Auto-

Negotiation advertisement register

have no effect unless Auto-

Reserved

Negotiation is restarted (PHY Control

R/W

Retain

Reserved bit is R/W to allow for

forward compatibility with future IEEE

standards.

1b = Set Remote Fault bit.

0b = Do not set Remote Fault bit.

Values programmed in the Auto-

Remote Fault

R/W

Retain

Negotiation advertisement register

have no effect unless Auto-

Negotiation is restarted (PHY Control

Reserved

Reserved. Should be set to 0b.

Always 0b

1b = Advertise.

0b = Not advertised.

Values programmed in the Auto-

Negotiation advertisement register

have no effect unless Auto-

Negotiation is restarted (PHY Control

If 1000BASE-T is advertised then the

required next pages are automatically

R/W

Retain

transmitted. The Next Page bit should

equal 0 if no additional next pages are

needed.

82541xx and 82547GI/EI only:

1b = Manual control of Next Page

(Software).

0b = Ethernet controller control of Next

Page (Auto).

For the 82541xx and 82547GI/EI, if EEPROM bit ADV10LU is asserted, then the default is set to 0b. Otherwise, the default

is 1b.

253

82544GC/EI Only:

Table 13-21. Auto-Negotiation Advertisement Register Bit Description

(MODE[3:0] is one of 001xb, 0111b)

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

Values programmed in this register have

no effect unless Auto-Negotiation is

restarted (PHY Control Register) or the

Reserved

4:0

R/W

00000b

Retain

link goes down.

Reserved bit is R/W to allow forward

compatibility with future IEEE standards.

1b = Advertise

0b = Not advertised

Values programmed in this register have

1000BASE-X Full

no effect unless Auto-Negotiation is

R/W

ANEG[3]

Retain

Duplex

restarted (PHY Control Register) or the

link goes down.

Bit 5: ANEG[3] = 1b

1b = Advertise

0b= Not advertised

Values programmed in this register have

1000BASE-X Half

no effect unless Auto-Negotiation is

R/W

ANEG[2]

Retain

Duplex

restarted (PHY Control Register) or the

link goes down.

Bit 6: ANEG[2] = 1b

Values programmed in this register have

no effect unless Auto-Negotiation is

Pause

R/W

Retain

restarted (PHY Control Register) or the

link goes down.

Values programmed in this register have

no effect unless Auto-Negotiation is

Asymmetric Pause

R/W

000b

Retain

restarted (PHY Control Register) or the

link goes down.

Values programmed in this register have

no effect unless Auto-Negotiation is

restarted (PHY Control Register) or the

Reserved

11:9

R/W

Retain

link goes down.

Reserved bit is R/W to allow forward

compatibility with future IEEE standards.

Values programmed in this register have

no effect unless Auto-Negotiation is

restarted (PHY Control Register) or the

RF1

R/W

Retain

link goes down.

Ethernet controller has no ability to

detect remote fault.

Values programmed in this register have

no effect unless Auto-Negotiation is

restarted (PHY Control Register) or the

RF2

R/W

Retain

link goes down.

Ethernet controller has no ability to

detect remote fault.

Reserved

Reserved. Should be set to 0b.

Always 0b

254

Table 13-21. Auto-Negotiation Advertisement Register Bit Description

(MODE[3:0] is one of 001xb, 0111b)

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

0b = Not advertised

Values programmed in this register have

no effect unless Auto-Negotiation is

restarted (PHY Control Register) or the

Always 0b

link goes down.

Next Page is not supported in

1000BASE-X mode.

13.4.7.1.6

Link Partner Ability Register (Base Page)

LPA (05d; R)

Table 13-22. Link Partner Ability Register (Base Page) Bit

Description¹

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

Selector Field

4:0

Received Code Word Bit 4:0.

00000b

Technology Ability

12:5

Received Code Word Bit 12:5.

00h

Field

Remote Fault

Received Code Word Bit 13.

Acknowledge

Received Code Word Bit 14.

Received Code Word Bit 15.

(MODE[3:0] is one of xx00b, 1x01b, 101xb, 1111b) for the 82544GC/EI only.

255

82544GC/EI Only:

Table 13-23. Link Partner Ability Register (Base Page) Bit

Description¹

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

Reserved

4:0

Reserved. Should be set to 00000b.

00000b

1b = 10 Base-TX half duplex is

10BASE-TX Half

available.

Duplex

0b = 10 Base-TX half duplex is not

available.

1b = 10 Base-TX full duplex is available.

10BASE-TX Full

0b = 10 Base-TX full duplex is not

Duplex

available.

1b = 100 Base-TX half duplex is

100BASE-TX Half

available.

Duplex

0b = 100 Base-TX half duplex is not

available.

1b = 100 Base-TX full duplex is

100BASE-TX Full

available.

Duplex

0b = 100 Base-TX full duplex is not

available.

100BASE-T4

0b = Not capable of 100BASE-T4.

Always 0b

1b = Pause operation is available.

Pause

0b = Pause operation is not available.

1b = Asymmetric Pause operation is

available.

Asymmetric Pause

0b = Asymmetric Pause operation is not

available.

Reserved

Reserved. Should be set to 0b.

Remote Fault

Indicates a remote fault.

Reserved

Reserved. Should be set to 0b.

1b = Link partner is Next Pagable.

0b = Link partner is not Next Pagable.

(MODE[3:0] is one of 001xb, 0111b).

256

82541xx and 82547GI/EI Only:

Table 13-24. PHY Link Page Ability Bit Description¹

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

<00001> = IEEE 802.3

Other combinations are reserved.

Unspecified or reserved combinations

Selector Field [4:0]

4:0

shall not be transmitted.

N/A

If field does not match PHY Register 4,

bits 4:0, the AN process does not

complete and no HCD is selected.

1b = Link Partner is 10BASE-T capable.

10BASE-T

0b = Link Partner is not 10BASE-T

N/A

capable.

1b = Link Partner is 10BASE-T full

10BASE-T Full

duplex capable.

N/A

Duplex

0b = Link Partner is not 10BASE-T full

duplex capable.

1b = Link Partner is 100BASE-TX

capable.

100BASE-TX

N/A

0b = Link Partner is not 100BASE-TX

capable.

1b = Link Partner is 100BASE-TX full

100BASE-TX Full

duplex capable.

N/A

Duplex

0b = Link Partner is not 100BASE-TX

full duplex capable.

1b = Link Partner is 100BASE-T4

capable.

100BASE-T4

N/A

0b = Link Partner is not 100BASE-T4

capable.

Link Partner uses Pause Operation as

LP Pause

N/A

defined in 802.3x.

Asymmetric Pause Direction Bit

1b = Link Partner is capable of

LP ASM_DIR

asymmetric pause.

N/A

0b = Link Partner is not capable of

asymmetric pause.

Reserved

Reserved. Should be set to 0b.

1b = Remote fault.

Remote Fault

N/A

0b = No remote fault.

1b = Link Partner has received Link

Code Word from the PHY.

Acknowledge

N/A

0b = Link Partner has not received Link

Code Word from the PHY.

1b = Link Partner has ability to send

multiple pages.

N/A

0b = Link Partner has no ability to send

multiple pages.

PHY register 8d stores the Auto-Negotiation Link Partner Received Next Pages. PHY register 5d is not used to store Next

Pages. It contains the information from the last Base Page correctly received.

257

13.4.7.1.7

Auto-Negotiation Expansion Register

ANE (06d; R)

Table 13-25. Auto-Negotiation Expansion Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

1b = Link Partner is Auto-Negotiation

Link Partner Auto-

able.

Negotiation Able

0b = Link Partner is not Auto-

Negotiation able.

1b = A New Page has been received.

0b = A New Page has not been

received.

82541xx and 82547GI/EI only:

RO/

Page Received

If PHY register 16, bit 1 (Alternate NP

LH¹

Feature) is set, the Page Received bit

also clears when mr_page_rx = false or

transmit_disable = true.

Local Next Page Able

1b = Local Device is Next Pageable.

1b (82541xx and

82547GI/EI)

1b = Link Partner is Next Page able.

0b = Link Partner is not Next Page able.

Link Partner Next

82544GC/EI only:

Page Able

MODE

Bit 2 = 1 if MODE[3:0] is not 001xb or

MODE[3:0]

[3:0]

0111b.

1b = A fault has been detected via the

Parallel Detection

Parallel Detection function.

RO/

Fault

0b = A fault has not been detected via

LH¹

the Parallel Detection function.

82541xx and 82547GI/EI only:

This bit indicates the status of the Auto-

Negotiation variable, base page. If flags

synchronization with the Auto-

Negotiation state diagram enabling

detection of interrupted links. This bit is

RO/

Base Page

only used if PHY register 16, bit 1

LH¹

(Alternate NP Feature) is set.

1b = base_page = true.

0b = base_page = false.

Note: This is a reserved bit for all

remaining Ethernet controllers.

Reserved

15:6

0000000000b

Always 000h

82541xx and 82547GI/EI only.

NOTE: The ANE Register is not valid until the Auto-Negotiation complete bit in the PHY Status Register

indicates completion of the Auto-Negotiation process.

258

13.4.7.1.8

Next Page Transmit Register

NPT (07d; R/W)

Table 13-26. Next Page Transmit Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

Transmit Code Word Bit 10:0.

Message/

10:0

82541xx and 82547GI/EI only:

R/W

001h

Unformatted Field

11-bit message code field.

Transmit Code Word Bit 11.

82541xx and 82547GI/EI only:

1b = Previous value of the transmitted

Toggle

Link Code Word = logical 0.

0b = Previous value of the transmitted

Link Code Word = logical 1.

Transmit Code Word Bit 12.

82541xx and 82547GI/EI only:

Acknowledge 2

R/W

1b = Complies with message.

0b = Cannot comply with message.

Transmit Code Word Bit 13.

82541xx and 82547GI/EI only:

Message Page

R/W

1b = Message page.

0b¹

0b = Unformatted page.

Transmit Code Word Bit 14.

82541xx and 82547GI/EI only:

Reserved

Always read as 0b. Write to 0b for

normal operation.

Transmit Code Word Bit 15.

A write to the NPT Register implicitly

sets a variable in the Auto-Negotiation

state machine.

R/W

82541xx and 82547GI/EI only:

1b = Additional next pages follow.

0b = Last page.

82541xx and 82547GI/EI only.

259

13.4.7.1.9

Link Partner Next Page Register

LPN (08d; R)

Table 13-27. Link Partner Next Page Register Bit Description

Bit(s)

Field

Description

Mode

HW Rst

SW Rst

Received Code Word Bit 10:0.

Message/

10:0

82541xx and 82547GI/EI only:

000h

Unformatted Field

11-bit message code field.

Received Code Word Bit 11.

82541xx and 82547GI/EI only:

1b = Previous value of the transmitted

Toggle

Link Code Word = a logic 0.

0b = Previous value of the transmitted

Link Code Word = a logic 1.

Received Code Word Bit 12.

82541xx and 82547GI/EI only:

1b = Link Partner complies with the

Acknowledge 2

message.

0b = Link Partner cannot comply with

the message.

Received Code Word Bit 13.

82541xx and 82547GI/EI only:

1b = Page sent by the Link Partner is a

Message Page

Message Page.

0b = Page sent by the Link Partner is an

Unformatted Page.

Received Code Word Bit 14.

82541xx and 82547GI/EI only:

1b = Link Partner has received Link

Acknowledge

Code Word from the PHY.

0b = Link Partner has not received Link

Code Word from the PHY.

Received Code Word Bit 15.

82541xx and 82547GI/EI only:

1b = Link Partner has additional next

pages to send.

0b = Link Partner has no additional next

pages to send.

260

13.4.7.1.10

1000BASE-T Control Register

GCON (09d; R/W)

Table 13-28. 1000BASE-T Control Register Bit Description

Bit(s)

Field

Description

Mode

HW Rst

SW Rst

7:0

Reserved

Reserved. Should be set to 00000000b.

R/W

1b = Advertise.

0b = Not advertised.

82544GC/EI only:

1000BASE-T Half

Bit 8 = ANEG[2].

R/W

Retain

Duplex

82541xx and 82547GI/EI only:

ANEG[2]

1b = DTE is 1000BASE-T capable.

0b = DTE is not 1000BASE-T capable.

This bit is used by Smart Negotiation.

1b = Advertise.

0b = Not advertised.

82544GC/EI only:

Bit 9 = ANEG[3].

1000BASE-T Full

82541xx and 82547GI/EI only:

R/W

Retain

Duplex

1b = DTE is 1000BASE-T full duplex

ANEG[3]

capable.

0b = DTE is not 1000BASE-T full duplex

capable. This bit is used by Smart

Negotiation (see Note 3).

1b = Prefer multi-port device

(MASTER).

0b = Prefer single port device (SLAVE)¹.

R/W

Retain

Port Type

82544GC/EI only:

ANEG[0]

Bit 10 =!ANEG[0].

Bit 10 is ignored if bit 12 = 1b.

1b = Manual configure as MASTER³.

0b = Manual configure as SLAVE³.

MASTER/SLAVE

R/W

1b²

Retain

82544GC/EI only:

Configuration Value

ANEG[0]

Bit 11 =!ANEG[0].

Bit 11 is ignored if bit 12 = 0b.

1b = Manual MASTER/SLAVE

configuration.

MASTER/SLAVE

0b = Automatic MASTER/SLAVE

R/W

1b²

Retain

Manual Configuration

configuration.

ANEG[1]

Enable

82544GC/EI only:

Bit 12 =!ANEG[1].

261

Table 13-28. 1000BASE-T Control Register Bit Description

Bit(s)

Field

Description

Mode

HW Rst

SW Rst

000b = Normal Mode.

001b = Test Mode 1 - Transmit

Waveform Test.

010b = Test Mode 2 - Transmit Jitter

Test (MASTER mode).

15:13

Test mode

R/W

000b

011b = Test Mode 3 - Transmit Jitter

Test (SLAVE mode).

100b = Test Mode 4 - Transmit

Distortion Test.

101b, 110b, 111b = Reserved.

For the 82541xx and 82547GI/EI, only when PHY register 9, bit 12 is set to a logical 0.

0b for the 82541xx and 82547GI/EI only

For the 82541xx and 82547GI/EI, only when PHY register 9, bit 12 is set to a logical 1.

NOTES:

1. Values programmed in bits 12:8 of the 1000BASE-T Control Register have no effect unless Auto-Negotiation

is restarted (PHY Control Register, bit 9) or the link goes down. These bits can also be overridden by the PHY

Control Register.

2. The symbol “!” is equivalent to logical “not.”

3. For the 82541xx and 82547GI/EI, the default for bit 9 is affected by configuration bits in the EEPROM. If

EEPROM ANI1000DIS is asserted, then the default is set to 0b. If EEPROM ADV10LU is asserted, then the

default is set to 0b.

13.4.7.1.11

1000BASE-T Status Register

GSTATUS (10d; R)

Table 14-29. 1000BASE-T Status Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

Idle Error Counter.

RO,

0000b

Idle Error Count

7:0

The counter stops at 1111b 1111b and

0000b

does not roll over.

Reserved

9:8

Reserved. Should be set to 00b

00b

1b = Link Partner is capable of

1000BASE-T half duplex.

Link Partner

0b = Link Partner is not capable of

1000BASE-T

1000BASE-T half duplex.

Half Duplex

Values in bits 11:10 are not valid until

Capability

the ANE Register Page Received bit

equals 1b.

1b = Link Partner is capable of

1000BASE-T full duplex.

Link Partner

0b = Link Partner is not capable of

1000BASE-T

1000BASE-T full duplex.

Full Duplex Capability

Values in bits 11:10 are not valid until

the ANE Register Page Received bit

equals 1b.

Remote Receiver

1b = Remote Receiver OK.

Status

0 b = Remote Receiver Not OK.

262

Table 14-29. 1000BASE-T Status Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

1b = Local Receiver OK.

Local Receiver Status

0b = Local Receiver Not OK.

1b = Local PHY configuration resolved

MASTER/SLAVE

to MASTER.

Configuration

0b = Local PHY configuration resolved

Resolution

to SLAVE.

1b = MASTER/SLAVE configuration

RO,

MASTER/SLAVE

fault detected.

LH,

Configuration Fault

0b = No MASTER/SLAVE configuration

fault detected.

13.4.7.1.12

Extended PHY Status Register

EPSTATUS (15d; R)

Table 13-30. Extended PHY Status Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

Reserved. Should be set to

Reserved

11:0

000h

000000000000b.

1b = 1000BASE-T half duplex capable.

0b = not 1000BASE-T half duplex

1000BASE-T Half

capable.

1b¹

Duplex

Note: 1000Mb-Half duplex is NOT

supported.

1b = 1000BASE-T full duplex capable.

1000BASE-T Full

0b = Not 1000BASE-T full duplex

1b¹

Duplex

capable.

1b =1000BASE-X half duplex capable.

0b = Not 1000BASE-X half duplex

1000BASE-X Half

capable.

0b¹

Duplex

Note: 1000Mb-Half Duplex is NOT

supported.

1b =1000BASE-X full duplex capable.

1000BASE-X Full

0b = Not 1000BASE-X full duplex

0b¹

Duplex

capable.

MODE[3:0] 82544GC/EI only.

NOTES:

1. 1000BASE-X Half Duplex only applicable to the 82544GC/EI.

2. Bit 12 = bit 13 = 1b if MODE[3:0] does not = 001xb or 0111b.

3. Bit 14 = bit 15 = 1b if MODE[3:0] = 001xb or 0111b.

263

13.4.7.1.13 PHY Specific Control Register

PSCON (16d; R/W)

Table 13-31. PHY Specific Control Register Bit Description

Description

Field

Bit(s)

Mode

HW Rst

SW Rst

1000BASE-T

10/100BASE-T

1b = Disable jabber function.

0b = Enable jabber function.

Disable Jabber

R/W

Retain

Jabber has effect only in 10BASE-T half

duplex mode.

1b = Polarity Reversal Disabled.

0b = Polarity Reversal Enabled.

Polarity Reversal

R/W

Retain

If polarity is disabled, then the polarity is

forced to be normal in 10BASE-T.

1b = SQE test enabled.

0b = SQE test disabled.

SQE Test

R/W

Retain

Jabber has effect only in 10BASE-T half

duplex mode.

1b = Always power up.

0b = Can power down.

This bit determines whether the MAC

MAC Interface Power

interface powers down when register

R/W

Update

Down

PHY Control Register bit 11 is used to

power down the Ethernet controller or

when the PHY enters the energy detect

state.

1b = 125CLK Low.

0b = 125CLK Toggling.

Disable 125CLK¹

Bit 4 = ENA_XC.

R/W

DIS_

Update

Reserved

This bit is reserved for all Ethernet

125CLK¹

controllers except the 82544GC/EI.

Should be set to 0b.

00b = Manual MDI configuration.

01b = Manual MDI-X configuration.

10b = Reserved.

11b = Enable automatic crossover for all

MDI Crossover Mode

6:5

R/W

11b

Update

modes.

82544GC/EI only:

Bit 6 = DIS_125.

Bit 5 = ENA_XC.

1b = Lower 10BASE-T receive

threshold.

0b = Normal 10BASE-T receive

Enable Extended

threshold.

R/W

Retain

Distance

When a cable longer than 100 m is

used, the 10BASE-T receive threshold

must be lowered in order to detect

incoming signals.

264

Table 13-31. PHY Specific Control Register Bit Description

Description

Field

Bit(s)

Mode

HW Rst

SW Rst

1000BASE-T

10/100BASE-T

Energy Detect.

0xb = Off.

Energy Detect

9:8

10b = Sense only on receive.

R/W

Retain

11b = Sense and periodically transmit

NLP.

1b = Force link good.

0 b = Normal operation.

Force Link Good

If link is forced to be good, the link state

R/W

Retain

machine is bypassed and the link is

always up. In 1000BASE-T mode this

has no effect.

1b = Assert on transmit.

Assert CRS on

0b = Never assert on transmit.

R/W

Retain

Transmit

This bit has no effect in full duplex.

00b = 16 Bits

00b = 8 Bits

01b = 24 Bits

01b = 12 Bits

10b = 32 Bits

10b = 16 Bits

Receive FIFO depth

13:12

R/W

00b

Retain

11b = 40 Bits

11b = 20 Bits

Receive FIFO is enabled in internal

SerDes mode² or serial interface mode.

00b = 16 Bits

00 b= 8 Bits

01b = 24 Bits

01b = 12 Bits

10b = 32 Bits

10b = 16 Bits

Transmit FIFO depth

15:14

R/W

00b

Retain

11b = 40 Bits

11b = 20 Bits

Transmit FIFO is enabled in 1000BASE-

T mode or serial interface mode.

82544GC/EI only.

TBI Mode for the 82544GC/EI.

PHY Port Configuration Register (82541xx and 82547GI/EI Only)

PPCONF (16d; R/W)

Table 13-32. PHY Port Configuration Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

Reserved

Write to 0b for normal operation.

R/W

1b = Enable alternate Auto-Negotiate

next page feature.

0b = Disable alternate Auto-Negotiate

Alternate NP Feature

R/W

next page feature.

If polarity is disabled, then the polarity is

forced to be normal in 10BASE-T.

Reserved

3:2

Write to 0b for normal operation.

R/W

265

Table 13-32. PHY Port Configuration Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

Auto_MDIX Parallel Detect Bypass.

Bypasses the fix to IEEE auto-MDIX

algorithm for the case where the PHY is

in forced-speed mode and the link

partner is auto-negotiating.

Auto MDIX Parallel

1b = Strict 802.3 Auto-MDIX algorithm.

R/W

Detect Bypass

0b = Auto-MDIX algorithm handles

Auto-Negotiation disabled modes. This

is accomplished by lengthening the

auto-MDIX switch timer before

attempting to swap pairs on the first time

out.

Preamble Enable

0b = Set RX_DV high coincident with

PRE_EN

SFD.

R/W

1b = Set RX_DV high and RXD =

preamble (after CRS is asserted).

Reserved

Write to 0b for normal operation.

R/W

1b = Smart Speed selection enabled.

Smart Speed

R/W

0b¹

0b = Smart Speed selection disabled.

1b = Disable TP loopback during half-

TP Loopback

duplex operation.

R/W

(10BASE-T)

0b = Normal operation.

Reserved

Write to 0b for normal operation.

R/W

1b = Disable jabber.

Jabber (10BASE-T)

R/W

0b = Enable jabber.

1b = Bypass4B5B encoder and

Bypass 4B5B

decoder.

R/W

(100BASE-TX)

0b = Normal operation.

1b = Bypass scrambler and

Bypass Scramble

descrambler.

R/W

(100BASE-TX)

0b = Normal operation.

1b = Disable twisted-pair transmitter.

Transmit Disable

R/W

0b = Normal operation.

1b = Force link pass

0b = Normal operation

For 10BASE-T, this bit forces the link

signals to be active. In 100BASE-T

Link Disable

mode, setting this bit should force the

R/W

Link Monitor into it’s LINKGOOD state.

For Gigabit operation, this merely

bypasses Auto-Negotiation-the link

signals still correctly indicate the

appropriate status.

Always read as 0b. Write 0b for normal

Reserved

16:15

R/W

operation.

The default for this bit is determined by EEPROM bit SSPEED.

266

13.4.7.1.14

PHY Specific Status Register

PSSTAT (17d; R)

Table 13-33. PHY Specific Status Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

1b = Jabber.

Jabber (real time)

Retain

0 = No jabber.

1b = Reversed.

Polarity (real time)

0b = Normal.

1b = Receive pause enabled.

0b = Receive pause disabled.

The Receive Pause Enable bit is valid

only after the Speed and Duplex

Receive Pause

Resolved bit (11) is set. This occurs

Enable

when Auto-Negotiation is completed or

Auto-Negotiation is disabled.

This is a reflection of the MAC pause

resolution.

1b = Transmit pause enabled.

0b = Transmit pause disabled.

The Transmit Pause Enable bit is valid

Transmit Pause

only after the Speed and Duplex

Enabled

Resolved bit (11) is set. This occurs

when Auto-Negotiation is completed or

Auto-Negotiation is disabled.

0b = Active

Energy Detect Status

1b = Sleep

1b = Downshift.

Downshift Status

0b = No Downshift.

1b = MDI-X.

0b = MDI.

The MDI Crossover Status bit is valid

MDI Crossover

only after the Speed and Duplex

Status

Resolved bit (11) is set. This occurs

when Auto-Negotiation is completed or

Auto-Negotiation is disabled.

000b = < 50 m.

001b = 50  80 m.

010b = 80  110 m.

011b = 110  140 m.

Cable Length

100b = >140 m.

(100/1000 modes

9:7

000b

only)

Cable length measurement is only a

rough estimate. The actual value

depends on the attenuation of the cable,

output levels of the remote transceiver,

connector impedance, etc.

1b = Link up.

Link (real time)

0b = Link down.

267

Table 13-33. PHY Specific Status Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

1b = Resolved.

0b = Not resolved.

Speed, Duplex, MDI Crossover Status,

Transmit Pause Enable, and Receive

Speed and Duplex

Pause Enable bits are valid only after

Resolved

the Speed and Duplex Resolved bit (11)

is set. This occurs when Auto-

Negotiation is completed or Auto-

Negotiation is disabled.

1b = Page received.

RO,

Page Received

0b = Page not received.

1b = Full duplex.

0b = Half duplex.

The Duplex bit is valid only after the

Duplex

Speed and Duplex Resolved bit (11) is

Retain

set. This occurs when Auto-Negotiation

is completed or Auto-Negotiation is

disabled.

11b = Reserved.

10b = 1000 Mb/s.

01b = 100 Mb/s.

00b = 10 Mb/s.

Speed

15:14

The Speed bit is valid only after the

00b

Retain

Speed and Duplex Resolved bit (11) is

set. This occurs when Auto-Negotiation

is completed or Auto-Negotiation is

disabled.

268

PHY Port Status 1 Register (82541xx and 82547GI/EI Only)

PPSTAT (17d; R)

Table 13-34. PHY Status 1 Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

Status bit indicating the Auto-

Negotiation Link Fail Inhibit Timer has

expired. This indicates that the Auto-

Negotiation process completed page

exchanges but was unable to bring up

the selected MAU’s link.

1b = Auto-Negotiation has aborted Link

establishment following normal page

exchange.

RO/

0b = Auto-Negotiation has either

LFIT Indicator

LH/

completed normally, or is still in

progress.

This bit is cleared when read or when

one of the following occurs:

Link comes up (PHY register 17, bit 10 =

1b).

Auto-Negotiation is disabled (PHY

Auto-Negotiation is restarted (PHY

1b = 10BASE-T polarity is reversed.

Polarity Status

0b = 10BASE-T polarity is normal.

Reserved

8:2

Write to 0b for normal operation.

1b = Full duplex.

Duplex Mode

0b = Half duplex.

Indicates the current status of the link.

Differs from PHY register 1, bit 2 in that

this bit changes anytime the link status

changes. PHY register 1, bit 2 latches

Link

low and stays low until read regardless

of link status.

1b = Link is currently up.

0b = Link is currently down.

Status indicator of the current MDI/MDI-

X state of the twisted pair interface. This

status bit is valid regardless of the MAU

selected.

MDI-X Status

1b = PHY has selected MDI-X (crossed

over).

0b = PHY has selected MDI (NOT

crossed over).

1b = PHY currently receiving a packet.

Receive Status

0b = PHY receiver is IDLE.

When in loopback, this bit reads as 0b.

269

Table 13-34. PHY Status 1 Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

1b = PHY currently transmitting a

packet.

Transmit Status

0b = PHY transmitter is IDLE.

When in loopback, this bit reads as 0b.

00b = Reserved.

01b = PHY operating in 10BASE-T

mode.

Data Rate

15:14

10b = PHY operating in 100BASE-TX

mode.

11b = PHY operating in 1000BASE-T

mode.

13.4.7.1.15 PHY Interrupt Enable Register

PINTE (18d; R/W)

Table 13-35. PHY Interrupt Enable Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

Jabber Interrupt

1b = Interrupt enable.

R/W

Retain

Enable

0b = Interrupt disable.

Polarity Changed

1b = Interrupt enable.

R/W

Retain

Interrupt Enable

0b = Interrupt disable.

Reserved

3:2

Always write 00b.

R/W

Retain

1b = Interrupt enable.

Energy Detect

R/W

Retain

0b = Interrupt disable.

Downshift Interrupt

1b = Interrupt enable.

R/W

Retain

Enable

0b = Interrupt disable.

MDI Crossover

1b = Interrupt enable.

Changed

R/W

Retain

0b = Interrupt disable.

Interrupt Enable

FIFO Over/Underflow

1b = Interrupt enable.

R/W

Retain

Interrupt Enable

0b = Interrupt disable.

False Carrier

1b = Interrupt enable.

R/W

Retain

Interrupt Enable

0 b= Interrupt disable.

Symbol Error

1b = Interrupt enable.

R/W

Retain

Interrupt Enable

0b = Interrupt disable.

Link Status Changed

1b = Interrupt enable.

R/W

Retain

Interrupt Enable

0b = Interrupt disable.

Auto-Negotiation

1b = Interrupt enable.

Completed

R/W

Retain

0b = Interrupt disable.

Interrupt Enable

270

Table 13-35. PHY Interrupt Enable Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

Page Received

1b = Interrupt enable.

R/W

Retain

Interrupt Enable

0b = Interrupt disable.

Duplex Changed

1b = Interrupt enable.

R/W

Retain

Interrupt Enable

0b = Interrupt disable.

Speed Changed

1b = Interrupt enable.

R/W

Retain

Interrupt Enable

0b = Interrupt disable.

Auto-Negotiation

1b = Interrupt enable.

Error

R/W

Retain

0b = Interrupt disable.

Interrupt Enable

PHY Port Control Register (82541xx and 82547GI/EI Only)

PPCONT (18d; R/W)

Table 13-36. PHY Port Control Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

Always read as 0b. Write to 0b for

Reserved

3:0

R/W

normal operation.

TP Loopback

Allow gigabit loopback on twisted pairs.

R/W

82541EI/82547GI (B0 stepping):

Reserved, write to 0b.

82541/GI/ER and 82547GI (B1

Fast Downshift

stepping): Fast 1000 Mb to 100 Mb

R/W

Enable

downshift enable.

0b = Downshift after 16 seconds.

1b = Downshift after 10 seconds.

Always read as 0b. Write to 0b for

Reserved

8:6

R/W

normal operation.

1b = Detect and correct for non-

Non-Compliant

compliant scrambler.

Scrambler

R/W

0b¹

0b = Detect and report non-compliant

Compensation

scrambler.

1b = Extend CRS to cover GMII latency

and RX_DV.

TEN_CRS_Select

R/W

0b = Do not extend CRS (RX_DV can

continue past CRS).

Reserved

Always write as 1b for normal operation.

R/W

Auto-MDI-X algorithm enable.

1b = Enable Auto-MDI-X mode.

0b = Disable Auto-MDI-X mode (manual

mode).

Auto-MDI-X

R/W

Note: When forcing speed to 10Base-T

or 100Base-T, use manual mode. Clear

the bit and set PHY register 18, bit 13

according to the required MDI-X mode.

271

Table 13-36. PHY Port Control Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

Force MDI-X mode. Valid only when

operating in manual mode. (PHY

MDI-X Mode

R/W

1b = MDI-X (cross over).

0b = MDI (no cross over).

Always read as 0b. Write to 0b for

Reserved

R/W

normal operation.

This configuration bit is used to enable

the Ethernet controller to drive its

differential transmit clock out through

the appropriate Analog Test (ATEST+/-)

output pads. This feature is required in

order to demonstrate conformance to

the IEEE Clause 40 jitter specification.

When high, it sends Jitter Test Clock

out.

Jitter Test Clock

R/W

This bit works in conjunction with

internal PHY register 18, bit 15. In order

to have the clock probed out, it is

required to perform the following write

sequence:

PHY register 18, bit15 = 1b

PHY register 31 = 4000h (page select)

PHY register 17 = 0080h

PHY register 31 = 0000h (page select)

The default for this bit is determined by EEPROM configuration bits. If EEPROM bit NCSCRAMB is asserted, then the

default is set to 1b.

13.4.7.1.16 PHY Interrupt Status Register

PINTS (19d; R)

Table 13-37. PHY Interrupt Status Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

1b = Jabber.

RO,

Jabber

0b = No jabber.

1b = Polarity Changed.

RO,

Polarity Changed

0b = Polarity not changed.

Reserved

3:2

Reserved. Should be set to 00b.

Always 00b

1b = Energy Detect state changed

RO,

Energy Detect

0b = No state change detected

1b = Downshift detected.

RO,

Downshift Detected

0b = No down shift.

MDI Crossover

1b = Crossover changed.

RO,

Changed

0b = Crossover not changed.

272

Table 13-37. PHY Interrupt Status Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

1b = Over/Underflow Error.

RO,

FIFO Over/Underflow

0b = No FIFO Error.

1b = False carrier.

RO,

False Carrier

0b = No false carrier.

1b = Symbol error.

RO,

Symbol Error

0b = No symbol error.

1b = Link status changed.

RO,

Link Status Changed

0b = Link status not changed.

Auto-Negotiation

1b = Auto-Negotiation completed.

RO,

Completed

0b = Auto-Negotiation not completed.

1b = Page received.

RO,

Page Received

0b = Page not received.

1b = Duplex changed.

RO,

Duplex Changed

0b = Duplex not changed.

1b = Speed changed.

RO,

Speed Changed

0b = Speed not changed.

1b = Auto-Negotiation Error.

0b = No Auto-Negotiation Error.

An error occurs if MASTER/SLAVE

Auto-Negotiation

RO,

does not resolve, parallel detect fault,

Error

no common HCD, or link does not

validate after negotiation has

completed.

PHY Link Health Register (82541xx and 82547GI/EI Only)

PLINK (19d; R)

Table 13-38. PHY Link Health Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

The channel A DSP had converged to

Valid Channel A

incoming data.

The channel B DSP had converged to

Valid Channel B

incoming data.

The channel C DSP had converged to

Valid Channel C

incoming data.

The channel D DSP had converged to

Valid Channel D

incoming data.

Auto-Negotiation

Auto-Negotiate is actively deciding

Active

HCD.

Reserved

Always read as 0b.

273

Table 13-38. PHY Link Health Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

Auto-Negotiate Fault: This is the logical

Auto-Negotiation

OR of PHY register 1, bit 4, PHY

Fault

15.

Reserved

Always read as 0b.

Mode:

10: 10 Mbps polarity error.

Data Err[0]

100: Symbol error.

1000: Gig idle error.

Mode:

10: Reserved.

RO/

Data Err[1]

100: Scrambler unlocked.

1000: Local receiver not OK.

RO/

Count Overflow

The idle error counter has overflowed.

Gig has detected a remote receiver

Gigabit Rem Rcvr

RO/

status error. This is a latched high

NOK

version of PHY register 10, bit 12.

Gig has resolved to master. This is a

Gigabit Master

duplicate of PHY register 10, bit 14.

Resolution

Programmers must read PHY register

10, bit 14 to clear this bit.

A fault has occurred with the gig master/

slave resolution process. This is a copy

Gigabit Master Fault

of PHY register 10, bit 15.

Programmers must read PHY register

10, bit 15 to clear this bit.

1b indicates that the PHY has detected

gigabit connection errors that are most

likely due to a non-IEEE compliant

scrambler in the link partner.

Gigabit Scrambler

0b = Normal scrambled data.

Error

Definition is: If an_enable is true and in

Gigabit mode, on the rising edge of

internal signal link_fail_inibit

timer_done, the dsp_lock is true but

loc_rcvr_OK is false.

Smart Speed has downgraded the link

RO/

SS Downgrade

speed from the maximum advertised.

274

13.4.7.1.17

Extended PHY Specific Control Register 1¹

EPSCON1 (20d; R/W)

Table 13-39. Extended PHY Specific Control 1 Bit Description¹

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

Reserved

1:0

00b

R/W

00b

Retain

Reserved

R/W

Reserved. Should be set to 0b.

Changes to this bit are disruptive to the

Reserved

6:4

normal operation; any change to this

R/W

110b

Update

reset to take effect.

Reserved. Should be set to 0b.

Changes to this bit are disruptive to the

Reserved

normal operation; any change to this

R/W

Update

reset to take effect.

00b = disable. (10/100 downshift)

01b = 1x.

10b = 2x.

11b = 3x.

Slave downshift

Changes to this bit are disruptive to the

9:8

R/W

01b

Update

counter

normal operation; any change to this

reset to take effect.

Bits 11:10 have no effect unless bits 1:0

are set to their default values.

00b = 1x.

01b = 2x.

10b = 3x.

11b = 4x.

Number of times that the PHY attempts

to achieve gigabit link before

Master downshift

downshifting to the next speed in Master

11:10

R/W

11b

Update

counter

Mode.

Changes to this bit are disruptive to the

normal operation; any change to this

reset to take effect.

Bits 11:10 have no effect unless bits 1:0

are set to their default values.

Reserved

Reserved. Should be set to 0b.

R/W

Reserved

Reserved. Should be set to 0b.

R/W

Reserved

Reserved. Should be set to 0b.

R/W

Reserved

Reserved. Should be set to 0b.

R/W

Extended PHY Specific Control Register - EPSCON for the 82544GC/EI only.

275

GMII FIFO Register (82541xx and 82547GI/EI Only)

PFIFO (20d; R/W)

Table 13-40. GMII FIFO Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

An unsigned integer that stipulates the

number of write clocks to delay the read

controller after internal GMII’s tx_en is

Buffer Size

3:0

first asserted. This “buffer” protects from

R/W

0101b

underflow at the expense of latency.

The maximum value that can be set is

13d or Dh.

When set, the PHY advertises higher

Enable Speed-Up

speed than 10Base-T after reconnect of

Upon Cable

R/W

Note 2

the cable, even if the software

Reconnect

advertised only 10Base-T speed.

When set, the PHY optimizes the power

consumption when the cable is

Power Down On Link

disconnected. The PHY gets back to

R/W

Note 1

Disconnect

normal operation reconnect of the cable,

supporting Auto-Negotiation and parallel

detection.

Always read as 0b. Write to 0b for

Reserved

7:6

R/W

00b

normal operation.

00b, 01b: Enable the output data bus

from GMII FIFO to transmitters, drives

zeros on the output loop-back bus from

GMII FIFO to external application and to

DSP RX-FIFOs in test mode.

10b: Drive zeros on output bus from

FIFO Out Steering

9:8

GMII FIFO to transmitters, enable data

R/W

00b

on the output loop-back bus from GMII

FIFO to external application and to DSP

RX-FIFOs in test mode.

11b: Enable the output data bus from

GMII FIFO to both transmitters and

loop-back bus.

When set, disables the addition of

Disable Error Out

under/overflow errors to the output data

R/W

stream on internal GMII’s tx_error.

Always read as 0b. Write to 0b for

Reserved

13:11

R/W

normal operation.

Status bit set when read clock that is

faster than internal GMII’s gtx_clk

RO/

FIFO Overflow

empties the FIFO mid packet. Increase

the buffer size.

Status bit set when read clock that is

slower than internal GMII’s gtx_clk has

RO/

FIFO Underflow

allowed the FIFO to fill to capacity mid

packet. Decrease buffer size.

NOTES:

1. The default is determined by EEPROM bit SPD_EN.

2. The default is determined by EEPROM bit ADV10LU.

276

13.4.7.1.18

PHY Receive Error Counter

PREC (21d; R)

Table 13-41. PHY Receive Error Counter Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW RST

Receive Error Count

15:0

Error Count.

RO,SC

0000h

NOTE: The counter stops at FFFFh and does not roll over.

PHY Channel Quality Register (82541xx and 82547GI/EI Only)

PCHAN (21d; R)

Table 13-42. PHY Channel Quality Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

The converged mean square error for

MSE D

3:0

Channel D.

The converged mean square error for

MSE C

7:4

Channel C.

The converged mean square error for

MSE B

11:8

Channel B.

The converged mean square error for

Channel A. This field is only meaningful

in gigabit, or in 100BASE-TX if this is

MSE A

15:12

the receive pair.

Use of this field is complex and needs

interpretation based on the chosen

threshold value.

13.4.7.1.19

SPEED_TEN_LED and LINK_ACT_LED Control (82541xx and 82547GI/EI Only)

(23d; R/W)

Table 13-43. SPEED_TEN_LED and LINK_ACT_LED Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

MUX the designated input to

LED Source Select

3:0

R/W

0000b

SPEED_TEN_LED.

Disable the SPEED_TEN_LED Blink

Logic.

LED Blink Disable

R/W

0b = Enable logic.

1b = Disable logic.

277

Table 13-43. SPEED_TEN_LED and LINK_ACT_LED Bit Description

Disable the SPEED_TEN_LED

Extension Logic.

0b = Enable logic.

1b = Disable logic.

LED Stretch Disable

R/W

Note: Only when both the stretch and

blink are disabled the input bypasses

the blink logic and is muxed out with no

sampling (only combinational logic).

Mux the designated input to

LED Source Select

9:6

R/W

0001b

LED_ACT_LED.

Disable the LINK_ACT_LED Blink

Logic.

LED Blink Disable

R/W

0b = Enable logic.

1b = Disable logic.

Disable the LINK_ACT_LED Extension

Logic.

0b = Enable logic.

1b = Disable logic.

LED Stretch Disable

R/W

Note: Only when both the stretch and

blink are disabled the input bypasses

the blink logic and is muxed out with no

sampling (only combinational logic).

When set to 1b, all LED outputs are

Invert Select

R/W

inverted.

Always read as 0b. Write to 0b for

Reserved

14:13

R/W

00b

normal operation

This bit is used to disable special power

saving in 10BASE-T mode and parallel

Disable 10 Power

detection. When set to 1b, power

R/W

Saving

reduction features of 10BASE-10 are

disabled (reserved for customers).

278

13.4.7.1.20

PHY Global Status (82544GC/EI Only)

PGSTAT (23d; R)

Table 13-44. PHY Global Status Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

0b = No Interrupt on Port.

Port 0 Interrupt

1b = Interrupt on Port.

0b = No Interrupt on Port.

Port 1 Interrupt

1b = Interrupt on Port.

0b = No Interrupt on Port.

Port 2 Interrupt

1b = Interrupt on Port.

0b = No Interrupt on Port.

Port 3 Interrupt

1b = Interrupt on Port.

Reserved

15:4

Reserved. Should be set to 0b.

NOTE: Bits 3:0 remain high until the active corresponding interrupt bits are cleared on a read of the PHY

Interrupt Status Register.

13.4.7.1.21 SPEED_100_LED and SPEED_1000_LED Control (82541xx and 82547GI/EI Only)

(24d; R/W)

Table 13-45. SPEED_100_LED and SPEED_1000_LED Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

MUX the designated input to

LED Source Select

3:0

R/W

0011b

SPEED_100_LED.

Disable the SPEED_100_LED Blink

Logic.

LED Blink Disable

R/W

0b = Enable logic.

1b = Disable logic.

Disable the SPEED_100_LED

Extension Logic.

0b = Enable logic.

1b = Disable logic.

LED Stretch Disable

R/W

Note: Only when both the stretch and

blink are disabled the input bypasses

the blink logic and is muxed out with no

sampling (only combinational logic).

Mux the designated input to

LED Source Select

9:6

R/W

0100b

SPEED_1000_LED.

Disable the SPEED_1000_LED Blink

Logic.

LED Blink Disable

R/W

0b = Enable logic.

1b = Disable logic.

279

Table 13-45. SPEED_100_LED and SPEED_1000_LED Bit Description

Disable the SPEED_1000_LED

Extension Logic.

0b = Enable logic.

1b = Disable logic.

LED Stretch Disable

R/W

Note: Only when both the stretch and

blink are disabled the input bypasses

the blink logic and is muxed out with no

sampling (only combinational logic).

Always read as 0b. Write to 0b for

Reserved

15:12

R/W

00b

normal operation

13.4.7.1.22 PHY LED Control Register (82544GC/EI Only)

PLED (24d; R/W)

Table 13-46. PHY LED Control Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

1b = Activity/Link.

LED_TX control

R/W

Retain

0b = Transmit activity.

1b = Receive activity/Link.

LED_RX control

R/W

Retain

0b = Receive activity.

Reserved

Reserved. Should be set to 0b.

R/W

Retain

1xb = Link[2:1], Link.

LED_LINK control

4:3

01b = Link, Speed[1:0].

R/W

00b

Retain

00b = Link[2:0].

Reserved

7:5

Reserved. Should be set to 000b.

R/W

000b

Retain

000b = 42 ms.

001b = 84 ms.

010b = 170 ms.

Blink Rate

10:8

R/W

001b

Retain

011b = 340 ms.

100b = 670 ms.

101b to 111b = Reserved.

0b = Do not force INT# assertion.

Force INT# to Assert

R/W

Retain

1b = Force INT# assertion.

000b = no pulse stretching.

001b = 21 ms to 42 ms.

010b = 42 ms to 84 ms.

01b1 = 84 ms to 170 ms.

Pulse stretch duration

14:12

R/W

100b

Retain

100b = 170 ms to 340 ms.

101b = 340 ms to 670 ms.

110b = 670 ms to 1.3 s.

111b = 1.3s to 2.7 s.

0b = Enable.

Disable LED

R/W

Retain

1b = Disable.

280

13.4.7.1.23

Extended PHY Specific Control Register 2

EPSCON2 (26d; R/W)

Table 13-47. Extended PHY Specific Control Register 2 Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

111b = 1.2, 100b = 0.9, 001b = 0.6

Fiber Output

2:0

110b = 1.1, 011b = 0.8, 000b = 0.5

R/W

100b

Retain

Amplitude

101b = 1.0, 010b = 0.7

Reserved

Reserved. Should be set to 1b.

R/W

Reserved

Reserved. Should be set to 0b.

R/W

Fiber Output

1b= 75 ohm.

R/W

Update

Impedance

0b = 50 ohm.

Fiber Input

1b = 75 ohm.

R/W

Update

Impedance

0b = 50 ohm.

Reserved

15:7

Reserved. Should be set to 0b.

R/W

000h

NOTE: Not applicable to the 82540EP/EM, 82544GC/EI, 82541xx, or 82547GI/EI.

13.4.7.1.24

Extended PHY Specific Status Register (82544GC/EI Only)

EPSSTAT (27d; R)

Table 13-48. Extended PHY Specific Status Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

MODE[3:0]

27.3:0

MODE[3:0].

MODE[3:0]

Retain

Reserved. Should be set to

Reserved

27.15:4

000000000000b.

13.4.7.1.25

MDI Register 30 Page Select¹

R30PS (29d; WO)

Table 13-49. MDI Register 30 Page Select Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

Selects the register accessible via the

15:0

R/W

0000h

Select

“window” at MDI register 30.

Not applicable to the 82544GC/EI, 82541xx, or 82547GI/EI.

281

13.4.7.1.26 MDI Register 30 Access Window¹

R30AW (30d; R/W)

Table 13-50. MDI Register 30 Page Select Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

Provides read/write capability for

15:0

R/W

0000h

13.4.7.1.27 Documented MDI Register 30 Operations¹

Unless otherwise specified, no reset operations are required in order for the following operations to

take effect.

Table 13-51. MDI Register 30 Operations

To Perform

Operation

MDI Read/Write Sequence

Power down SerDes (optimize

• Write MDI register 29 <= 31d

30_31.15:0 <= x2001h

power for copper PHY operation)¹

• Write MDI register 30 <= 2001h

30_5.8 <= 0b

• Write MDI register 29 <= 5d

• Read MDI register 30

• Change bit 8 to 0

• Write result to MDI register 30

Tune VCO on SerDes Rx for

optimal Bit Error Ratio (BER)¹

• Write MDI register 29 <= 4d

30_4.11 <= 1b

• Read MDI register 30

• Change bit 11 to 1

• Write result to MDI register 30

Set PHY output drivers into Class A

• Write MDI register 29 = 11d

mode (Class AB is default after

30_11.15:0 = 8004h

• Write MDI register 30 = 8004h

reset)

Not applicable to 82540EP/EM

NOTE: Any time the PHY is reset it returns to Class AB drive mode.

Not applicable to the 82544GC/EI, 82541xx, or 82547GI/EI.

282

13.4.7.1.28

PHY Page Select Register (82541xx and 82547GI/EI Only)

PPAGE (31d; R/W)

Table 13-52. PHY Page Select Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

This register is used to swap out the

Base Page containing the IEEE

PAGE_SEL

15:0

registers for Intel reserved test and

debug pages residing within the

Extended Address space.

13.4.8

Flow Control Address Low

FCAL (00028h; R/W)

Flow control packets are defined by IEEE 802.3x to be either a unique multicast address or the

station address with the EtherType field indicating PAUSE. The FCAL, FCAH registers provide

the value hardware compares incoming packets against to determine that it should PAUSE its

output, and hardware use when transmit PAUSE packets to its remote node when flow control is

activated.

The FCAL register contains the lower bits of the internal 48-bit Flow Control Ethernet address. All

32 bits are valid. Software can access the High and Low registers as a register pair if it can perform

a 64-bit access to the PCI bus. This register should be programmed with 00_C2_80_01h. The

complete flow control multicast address is: 01_80_C2_00_00_01h; where 01h is the first byte on

the wire, 80h is the second, etc.

Table 13-53. FCAL Register Bit Description

FCAL

Initial

Field

Bit(s)

Description

Value

Flow Control Address Low

FCAL

31:0

Should be programmed with 00_C2_80_01h

13.4.9

Flow Control Address High

FCAH (0002Ch; R/W)

This register contains the upper bits of the 48-bit Flow Control Ethernet address. Only the lower 16

bits of this register have meaning. The complete Flow Control address is {FCAH, FCAL}. This

01_80_C2_00_00_01h; where 01h is the first byte on the wire, 80h is the second, etc.

283

Table 13-54. FCAH Register Bit Description

16 15

Reserved

FCAH

Initial

Field

Bit(s)

Description

Value

Flow Control Address High

FCAH

15:0

Should be programmed with 0100h.

Reserved

31:16

Should be written with 0b to ensure future compatibility.

Reads as 0b.

13.4.10

Flow Control Type

FCT (00030h; R/W)

This register contains the type field that hardware matches to recognize a flow control packet and

that hardware uses when transmitting a PAUSE packet to its remote node. Only the lower 16 bits of

this register have meaning. This register should be programmed with 88_08h. The upper byte is

first on the wire FCT[15:8].

Table 13-55. FCT Register Bit Description

16 15

Reserved

FCT

Initial

Field

Bit(s)

Description

Value

Flow Control Type

FCT

15:0

Should be programmed with 88_08h.

Reserved

31:16

Should be written with 0b to ensure future compatibility.

Reads as 0b.

13.4.11

VLAN Ether Type

VET (00038h; R/W)

This register contains the type field hardware matches against to recognize an 802.1Q (VLAN)

Ethernet packet and uses when add and transmit VLAN Ethernet packets. To be compliant with the

802.3ac standard, this register should be programmed with the value 8100h. For VLAN

transmission the upper byte is first on the wire (VET[15:8]).

284

Table 13-56. VET Register Bit Description

16 15

Reserved

VET

Initial

Field

Bit(s)

Description

Value

VLAN EtherType

VET

15:0

Should be programmed with 8100h.

Reserved

31:16

Reads as 0b.

13.4.12

Flow Control Transmit Timer Value

FCTTV (00170h; R/W)

Provides the Pause slot time value to be included in the transmitted XOFF Pause packets.

The slot time value that is used is a fixed slot of 64-byte time.

Table 13-57. FCTTV Register Bit Description

16 15

Reserved

TTV

Initial

Field

Bit(s)

Description

Value

Transmit Timer Value

Slot time value (Slot time value is 64-byte time) to be inserted into

TTV

15:0

the transmitted Pause frame. If software wishes to send XON

frame, it should set the FCTTV. TTV value to 0b prior to initializing

the Pause frame.

Reserved

31:16

Reads as 0b.

Should be written to 0b for future compatibility.

285

13.4.13

Transmit Configuration Word Register¹

TXCW (00178h; R/W)

This register is applicable to the TBI mode/internal SerDes mode of operation. For internal PHY

operation, program the register to 0000h. For example, clear this register in MMI mode.

This register has two meanings, depending on the state of Auto-Negotiation: one as the “AN

advertise register” defined by IEEE 802.3z, and the other as a register for software control of the

Auto-Negotiation process.

When performing hardware Auto-Negotiation, it fulfills the function defined by sub-clause

37.3.6.1.3 of IEEE 802.3z.

Table 13-58. TXCW Register Bit Description

16 15

Reserved

TxConfigWord

Initial

Field

Bit(s)

Description

Value

Data transmitted during Auto-Negotiation process.

When performing hardware Auto-Negotiation (TXCW.ANE is

set), the value of TxConfigWord is encoded as two 10-

bit symbols and sent as the “config_word” field for the /C/

ordered set. When the Ethernet controller performs software

Auto-Negotiation, TxConfig and TxConfigWord are used to

negotiate with the link partner. Data stored in TxConfigWord is

transmitted during the Auto-Negotiation process. Software

should not read back the contents of this field as content might

change during the software Auto-Negotiation process. In the

absence of loss of synchronization, the value read back is stable

and equal to the value written.

The mapping of the TxConfigWord is as follows:

TxConfigWord

15:0

• TxConfigWord[15] Next page request

• TxConfigWord[14] Reserved (write as 0b; ignore on read)

• TxConfigWord[13:12] Remote fault indication

• TxConfigWord[11:9] Reserved (write as 0b; ignore on read)

• TxConfigWord[8:7] Pause

• TxConfigWord[6] Half-duplex

• TxConfigWord[5] Full-duplex

• TxConfigWord[4:0] Reserved (write as 0b; ignore on read)

Bits 5,7 & 8 of TxConfigWord are loadable from the EEPROM

upon power-up, or chip reset.

Reserved

Reads as 0b.

Reserved

29:16

Should be written to 0b for future compatibility.

Not applicable to the 82541xx, 82547GI/EI, or 82540EP/EM.

286

Initial

Field

Bit(s)

Description

Value

Transmit Config Control bit

0b = Transmit data/idle

1b = Transmit /C/ ordered sets

TxConfig

Setting the TxConfig bit causes transmission of /C/ ordered set in

a software controlled Auto-Negotiation process

(TXCW.ANE=0b).

Auto-Negotiation Enable.

1b = Enable the hardware Auto-Negotiation state machine.

0b = Disable the hardware Auto-Negotiation state machine.

This bit has the same function as bit 0.12 defined in sub-clause

22.2.4.1.4 of the 802.3z standard. Since this bit is a “static”

value, a pulse is generated by hardware in response to writing

this bit with a 1b. This pulse is used to restart the Auto-

ANE

Negotiation state machine.

When ANE is set, a transition from loss of synchronization to

synchronized state restarts the Auto-Negotiation as well.

If ANE is cleared, then the Ethernet controller is performing

software Auto-Negotiation. In that case TxConfig and

TxConfigWord are used to negotiate with the link partner.

The ANE is loadable from the EEPROM upon power up or chip

reset.

Note:

Careful attention to the IEEE 802.3z standard is required in order to meet specified timing

requirements for timing during a software negotiated link.

13.4.14

Receive Configuration Word Register¹

RXCW (00180h; R)

This register has meaning only in TBI/internal SerDes mode of operation. The RXCW register

records the partner abilities and provides indications about its Auto-Negotiation status.

The contents of this register depend on the state of TXCW.ANE. If ANE is set, then this register

records the 16-bit defined in IEEE 802.3z. When performing software Auto-Negotiation, software

should look for RXCW.ANC. When RXCW.ANC is set, the contents of RXCW.RxConfigWord are

valid, when RXCW.ANC is cleared, then the content of this register is undefined.

Note:

While in internal SerDes mode (82546GB/EB and 82545GM/EM only), software might be

required to inspect or monitor the results of RXCW to generate a link up/down indication.

Not applicable to the 82541xx, 82547GI/EI, or 82540EP/EM.

287

Table 13-59. RXCW Register Bit Description

Initial

Field

Bit(s)

Description

Value

Data received during Auto-Negotiation process.

When performing hardware Auto-Negotiation

(TXCW.ANE = 1b), the “AN link partner ability base page

RxConfigWord

15:0

When TXCW.ANE is clear, then this register is used by

software to perform software based Auto-Negotiation. In

that capacity, RxConfigWord records the raw values

returned from the Auto-Negotiation process.

Reserved

25:16

Reads as 0b.

Should be written with 0b for future compatibility.

Carrier Sense Indication

0b = Ethernet controller not receiving idle characters

(Carrier sense is true)

1b = Ethernet controller receiving idle characters (Carrier

sense is false)

Hardware sets RxConfigNoCarrier when it is receiving idle

RxConfigNoCarrier

characters (and when receiving link configuration

information or port status).

Software can use this bit to determine that idles have been

seen prior to exiting the link start-up procedure.

82544GC/EI only:

Valid only in software Auto-Negotiation mode

(TXCW.ANE = 0b).

Invalid Symbol during configuration process

0b = Have not received an invalid symbol during Auto-

Negotiation process.

1b = Have received an invalid symbol during Auto-

Negotiation process (bit is LH).

If the Ethernet controller detects an invalid symbol at any

time, it sets the RxConfigInvalid bit. The bit is latched high

RxConfigInvalid

until read by software. Software is expected to restart the

configuration process when the Ethernet controller receives

an invalid symbol at any time during the Auto-Negotiation

process.

82544GC/EI only:

Valid only in software Auto-Negotiation mode

(TXCW.ANE = 0b).

Change to the RxConfigWord indication

0b = RxConfigWord has changed since last read.

1b = RxConfig is unchanged since last read (LH)

Indicates that the Ethernet controller interface has seen a

RxConfigChange

change to the RxConfigWord. This bit is latched high until

read by software.

82544GC/EI only:

Valid only in software Auto-Negotiation mode

(TXCW.ANE = 0b).

288

Initial

Field

Bit(s)

Description

Value

/C/ order set reception indication

0b = Receive idle/data stream.

1b = Receiving /C/ order sets.

Provides an indication as to whether the interface is

RxConfig

receiving /C/ order set, or normal idle/data stream.

82544GC/EI only:

Valid only in software Auto-Negotiation mode

(TXCW.ANE = 0b).

Lost bit synchronization indication

0b = Lost synchronization.

1b = Bit synchronization (bit is LL).

Used to qualify all other bits in the register (when in

software Auto-Negotiation).

RxSynchronize

Each time the Ethernet controller loses bit synchronization,

this bit becomes ‘0b’ and stays ‘0b’ until read by software.

82544GC/EI only:

Valid only in software Auto-Negotiation mode

(TXCW.ANE = 0b).

Auto Negotiation Complete

0b = The contents of the register are undefined in hardware

Auto-Negotiation mode (TXCW.ANE = 1b)

1b = The contents of the register are valid in hardware Auto-

Negotiation mode.

Reports the status as required in sub-clause 22.2.4.2.11.

ANC

This bit remains cleared from the time Auto-Negotiation is

reset until Auto-Negotiation reaches the “LINK_OK” state.

It remains set until Auto-Negotiation is disabled or restarted.

This bit has meaning only if TXCW.ANE = 1b. If software

Auto-Negotiation is used, it always reads 0b and should be

ignored.

13.4.15

LED Control¹

LEDCTL (00E00h; RW)

31 - 24

23 - 16

15 - 8

7 - 0

LED3 (LINK1000#)

LED2 (LINK100#)

LED1 ACTIVITY#)

LED0 (LINK_UP#)

Not applicable to the 82544GC/EI.

289

Table 13-60. LED Control Bit Description¹

Initial

Field

Bit

Description

Value

LED0/LINK# Mode. This field specifies the control source for the

LED0_MODE

3:0

0010b¹

LED0 output. An initial value of 0010b selects LINK_UP# indication.

Reserved

5:4

00b

Reserved. Read-only as 0b. Write as 0b for future compatibility.

LED0/LINK# Invert. This field specifies the polarity/ inversion of the

LED source prior to output or blink control.

LED0_IVRT

0b¹

0b = do not invert LED source.

1b = invert LED source.

LED0/LINK# Blink. This field specifies whether to apply blink logic to

the (possibly inverted) LED control source prior to the LED output.

LED0_BLINK

0b¹

0b = do not blink asserted LED output.

1b = blink asserted LED output.

LED1/ACTIVITY# Mode. This field specifies the control source for the

LED1_MODE

11:8

0011b

LED1 output. An initial value of 0011b selects ACTIVITY# indication.

Reserved

13:12

00b

Reserved. Read-only as 0b. Write as 0b for future compatibility.

LED1_IVRT

LED1/ACTIVITY# Invert.

LED1_BLINK

LED1/ACTIVITY# Blink.

LED2/LINK100# Mode. This field specifies the control source for the

LED2_MODE

19:16

0110b¹

LED2 output. An initial value of 0011b selects LINK100# indication.

Reserved

21:20

00b

Reserved. Read-only as 0b. Write as 0b for future compatibility.

LED2_IVRT

0b¹

LED2/LINK100# Invert.

LED2_BLINK

0b¹

LED2/LINK100# Blink.

LED3/LINK1000# Mode. This field specifies the control source for the

LED3_MODE

27:24

0111b

LED3 output. An initial value of 0111b selects LINK1000# indication.

Reserved

29:28

00b

Reserved. Read-only as 0b. Write as 0b for future compatibility.

LED3_IVRT

LED3/LINK1000# Invert.

LED3_BLINK

LED3/LINK1000# Blink.

These bits are read from the EEPROM.

13.4.15.1

MODE Encodings for LED Outputs¹

The Table 13-61 lists the MODE encodings used to select the desired LED signal source for each

LED output. Refer to Section 10.1.1 to ensure proper understanding of expression polarity and

resulting LED output polarity.

Note:

All 16 modes listed are functional.

Not applicable to the 82544GC/EI.

290

Table 13-61. Mode Encodings for LED Outputs¹

Mode

Pneumonic

State / Event Indicated

Asserted when either 10 or 1000 Mbps link is

0000b

LINK_10/1000

established and maintained.

Asserted when either 100 or 1000 Mbps link is

0001b

LINK_100/1000

established and maintained.

Asserted when any speed link is established and

0010b

LINK_UP

maintained.

Asserted when link is established and packets are

0011b

ACTIVITY

being transmitted or receive activity that passes

filtering.

Asserted when link is established and when there is

0100b

LINK/ACTIVITY

no transmit or receive activity that passes filtering.

Asserted when a 10 Mbps link is established and

0101b

LINK_10

maintained.

Asserted when a 100 Mbps link is established and

0110b

LINK_100

maintained.

Asserted when a 1000 Mbps link is established and

0111b

LINK_1000

maintained.

Asserted when Ethernet controller is in PCI-X mode

1000b

PCIX_MODE

(deasserted in PCI mode).

Asserted when the link is configured for full duplex

1001b

FULL_DUPLEX

operation (deasserted in half-duplex).

1010b

COLLISION

Asserted when a collision is observed.

Asserted when the Ethernet controller is operating

in a PCI 66 MHz or a PCI-X 133 MHz configuration

1011b

BUS_SPEED

(high-speed PCI operation), deasserted for 33 MHz

PCI and 66 MHz PCI-X (as determined by pins

sampled at PCI reset).

BUS_SIZE

Asserted when the Ethernet controller is operating

1100b

Reserved for the

as a 64-bit PCI or PCI-X device, deasserted for 32-

82547GI/EI only)

bit configuration.

Asserted when the Ethernet controller’s transmitter

1101b

PAUSED

is flow controlled.

Always high. Assuming no optional inversion

1110b

VCC/LED_ON

selected, causes output pin high / LED ON for

typical LED circuit.

Not applicable to the 82544GC/EI.

291

Mode

Pneumonic

State / Event Indicated

Always low. Assuming no optional inversion

1111b

GND/LED_OFF

selected, causes output pin low / LED OFF for

typical LED circuit.

13.4.16

Packet Buffer Allocation

PBA (01000H; R/W)

This register sets the on-chip receive and transmit storage allocation ratio. The receive allocation

value is read/write for the lower seven bits. The receive allocation value must be a multiple of eight

(multiple of two for the 82547GI/EI B1 stepping). The transmit allocation is read-only and is

calculated based on PBA.RXA.

Table 13-62. PBA Register Bit Description

16 15

TXA

RXA

Field

Bit(s)

Initial Value

Description

Receive Packet Buffer Allocation in KB

Sets the size of the receive packet buffer.

0030h¹

The value of this field must be a multiple of eight.

6:0

The upper nine bits are read only as 0b. Default is

0016h (82547EI A0-B0

48 KB.

RXA

15:0 (82541xx

steppings)

and 82547GI/EI)

001Eh (82547GI B1

For the 82541xx and 82547GI/EI, the upper unused

stepping)

bits are read only as 0b. The default is 48 KB for the

82541xx, 24 KB for the 82547EI, and 20 KB for the

82547GI.

Receive Packet Buffer Allocation - Upper Bits

Provides the upper nine bits of the receive packet

RXA_R²

15:7

buffer allocation.

Read only bits - Read as 0b.

Transmit Packet Buffer Allocation

0010h

Provides the size of the transmit packet buffer. The

31:16

value is in units of KB. These bits are read only.

0012h (82547EI A0-B0

TXA is calculated based on RXA value: TXA = 64 -

TXA

15:00 (82541xx

steppings)

RXA.

and 82547GI/EI)

000Ah (82547GI B1

stepping)

For the 82547GI/EI, TXA is calculated based on

RXA value: TXA = 40 - RXA.

Not applicable to the 82547GI/EI.

Not applicable to the 82541xx or 82547GI/EI.

292

13.4.17

Interrupt Cause Read Register

ICR (000C0H; R)

This register contains all interrupt conditions for the Ethernet controller. Each time an interrupt

causing event occurs, the corresponding interrupt bit is set in this register. A PCI interrupt is

generated each time one of the bits in this register is set, and the corresponding interrupt is enabled

through the Interrupt Mask Set/Read IMS Register (see Section 13.4.20).

All register bits are cleared upon read. As a result, reading this register implicitly acknowledges

any pending interrupt events. Writing a 1b to any bit in the register also clears that bit. Writing a 0b

to any bit has no effect on that bit.

Table 13-63. ICR Register Bit Description

31 - 17

16 14

Reserved

ICR Bits

Initial

Field

Bit(s)

Description

Value

Transmit Descriptor Written Back

Set when hardware processes a transmit descriptor with the RS

TXDW

bit set (and possibly IDE set). If using delayed interrupts (IDE set),

the interrupt occurs after the timer expires.

Transmit Queue Empty

TXQE

Set when the last descriptor block for a transmit queue has been

used.

Link Status Change

This bit is set each time the link status changes (either from up to

LSC

down, or from down to up). This bit is affected by the internal link

indication when configured for internal PHY mode.

Receive Sequence Error

In TBI mode/internal SerDes¹, incoming packets with a bad

delimiter sequence set this bit. In other 802.3 implementations,

this would be classified as a framing error. A valid sequence

RXSEQ

consists of:

idle  SOF  data  pad (opt) EOF  fill (opt)  idle.

This is a reserved bit for the 82541xx, 82547GI/EI, and 82540EP/

EM. Set to 0b.

Receive Descriptor Minimum Threshold Reached

RXDMT0

Indicates that the minimum number of receive descriptors are

available and software should load more receive descriptors.

Reserved

Reads as 0b.

Receiver Overrun

Set on receive data FIFO overrun. Could be caused either

RXO

because there are no available receive buffers or because PCI

receive bandwidth is inadequate.

293

Initial

Field

Bit(s)

Description

Value

Receiver Timer Interrupt

Set when the receiver timer expires.

RXT0

The receiver timer is used for receiver descriptor packing. Timer

expiration flushes any accumulated descriptors and sets an

interrupt event when enabled.

Reserved

Reads as 0b.

MDI/O Access Complete

MDAC

This bit is set when the MDI/O access is completed.

Receiving /C/ ordered sets

Mapped to RXCW.RxConfig.

Sets when the hardware receives configuration symbols (/C/

codes). Software should enable this interrupt when forcing link.

When the link is forced, the link partner can begin to Auto-

RXCFG

Negotiate based, due to a reset or enabling of Auto-Negotiation.

The reception of /C/ codes causes an interrupt to software and the

proper hardware configuration might be set.

See Section 13.4.14 for details. Only valid in internal SerDes

mode (TBI mode for the 82544GC/EI).

This is a reserved bit for the 82541xx and 82547GI/EI. Set to 0b.

Reserved. Set this bit to 0b.

Reserved

Not applicable to the 82544GC/EI.

PHY Interrupt (not applicable to the 82544GC/EI)

Set when the PHY generates an interrupt.

PHYINT

If bit 1 (PHYINT_EN) of the CTRL_EXT register (00018h) is set,

then this bit gets set.

This is a reserved bit for the 82541xx and 82547GI/EI. Set to 0b.

GPI_SDP6

General Purpose Interrupt on SDP6[2]. If GPI interrupt detection is

enabled on this pin (via CTRL_EXT), this interrupt cause is set

GPI_SDP2

when the SDP6[2] is sampled high.

(82541xx and

Not applicable to the 82544GC/EI.

82547GI/EI)

GPI_SDP7

General Purpose Interrupt on SDP7[3]. If GPI interrupt detection is

enabled on this pin (via CTRL_EXT), this interrupt cause is set

GPI_SDP3

when the SDP7[3] is sampled high.

(82541xx and

Not applicable to the 82544GC/EI.

82547GI/EI)

General Purpose Interrupts (82544GC/EI only)

14:13,

GPI

These bits are mapped to the upper three SDP pins when they are

configured as inputs. Refer to Section 13.4.6.

Transmit Descriptor Low Threshold hit.

TXD_LOW²

Indicates that the descriptor ring has reached the threshold

specified in the Transmit Descriptor Control register.

Small Receive Packet Detected.

Indicates that a packet of size  RSRPD.SIZE register has been

SRPD²

detected and transferred to host memory. The interrupt is only

asserted if RSRPD.SIZE register has a non-zero value.

294

Initial

Field

Bit(s)

Description

Value

Reserved

31:17

Reads as 0b.

The 82540EP/EM, 82541xx, or 82547GI/EI do not support SerDes functionality.

Not applicable to the 82544GC/EI.

Note: The 82547GI/EI signals interrupts over the CSA port, not a dedicated interrupt pin.

13.4.18

Interrupt Throttling Register¹

ITR (000C4h; R/W)

31 - 16

15 - 0

Reserved

INTERVAL

Initial

Field

Bit(s)

Description

Value

Minimum inter-interrupt interval. The interval is specified in 256 ns

INTERVAL

15:0

increments. Setting this bit to 0b disables interrupt throttling logic.

Reserved

31:16

Reserved. Should be written with 0b to ensure future compatibility.

Software can use this register to pace (or even out) the delivery of interrupts to the host CPU. This

controller, regardless of network traffic conditions. To independently validate configuration

settings, software can use the following algorithm to convert the inter-interrupt interval value to the

common interrupts/sec performance metric:

-9

-1

interrupts/second

25610

 interval

For example, if the interval is programmed to 500d, the Ethernet controller guarantees the CPU is

not interrupted by the Ethernet controller for 128 sec from the last interrupt. The maximum

observable interrupt rate from the Ethernet controller must never exceed 7813 interrupts/sec.

Inversely, inter-interrupt interval value can be calculated as:

-9

-1

inter-interrupt interval

25610

 interrupts/sec

The optimal performance setting for this register is very system and configuration specific. A

initial suggested range is 651-5580 (28Bh - 15CCh).

Not applicable to the 82544GC/EI.

295

13.4.19

Interrupt Cause Set Register

ICS (000C8h; W)

Software uses this register to set an interrupt condition. Any bit written with a 1b sets the

corresponding interrupt. This results in the corresponding bit being set in the Interrupt Cause Read

and the corresponding interrupt is enabled through the Interrupt Mask Set/Read Register (see

Section 13.4.20).

Bits written with 0b are unchanged.

Table 13-64. ICS Register Bit Description

17 16

Reserved

ICS Bits

Initial

Field

Bit(s)

Description

Value

TXDW

Sets Transmit Descriptor Written Back Interrupt.

TXQE

Sets Transmit Queue Empty Interrupt.

LSC

Sets Link Status Change Interrupt.

Sets Receive Sequence Error Interrupt.

RXSEQ

This is a reserved bit for the 82541xx and 82547GI/EI. Set to

0b.

Sets Receive Descriptor Minimum Threshold Reached

RXDMT0

Interrupt.

Reserved

Should be written with 0b to ensure future compatibility.

RXO

Sets on Receiver FIFO Overrun Interrupt.

RXT0

Sets Receiver Timer Interrupt.

Reserved

Should be written with 0b to ensure future compatibility.

MDAC

Sets MDI/O Access Complete Interrupt.

Sets Receiving /C/ ordered sets Interrupt.

RXCFG

This is a reserved bit for the 82541xx and 82547GI/EI. Set to

0b.

Reserved

Should be written with 0b to ensure future compatibility.

Not applicable to the 82544GC/EI.

Sets PHY interrupt. Not applicable to the 82544GC/EI.

PHYINT

This is a reserved bit for the 82541xx and 82547GI/EI. Set to

0b.

296

Initial

Field

Bit(s)

Description

Value

GPI

14:11

Sets General Purpose Interrupts (82544GC/EI only).

GPI

14:13

Sets General Purpose Interrupts.

Transmit Descriptor Low Threshold Hit. Not applicable to the

TXD_LOW

82544GC/EI.

Small Receive Packet Detected and Transferred. Not applicable

SRPD

to the 82544GC/EI.

Reserved

31:17

Should be written with 0b to ensure future compatibility.

13.4.20

Interrupt Mask Set/Read Register

IMS (000D0h; R/W)

An interrupt is enabled if its corresponding mask bit is set to 1b, and disabled if its corresponding

mask bit is set to 0b. A PCI interrupt is generated each time one of the bits in this register is set and

the corresponding interrupt condition occurs. The occurrence of an interrupt condition is reflected

by having a bit set in the Interrupt Cause Read Register (see Section 13.4.17).

A particular interrupt can be enabled by writing a 1b to the corresponding mask bit in this register.

Any bits written with a 0b are unchanged. As a result, if software desires to disable a particular

interrupt condition that had been previously enabled, it must write to the Interrupt Mask Clear

Reading this register returns bits that have an interrupt mask set.

Note:

For the 82547GI/EI, programmers need to first write (clear) the IMS and IMC registers due to a

Hub Link bus being occupied. This results in an interrupt de-assertion message that can’t to be sent

out. When a future interrupt assertion message is generated, two messages are re-ordered and sent

out. This signals APIC that the 82547GI/EI is in a de-asserted state when it is actually in an

asserted state, which causes a system dead lock. To avoid a system dead lock, first clear the IMS

and IMC registers by writing FFFFh and then re-assert IRQ enable.

Table 13-65. IMS Register Bit Description

17 16

Reserved

IMS Bits

Initial

Field

Bit(s)

Description

Value

TXDW

Sets mask for Transmit Descriptor Written Back.

TXQE

Sets mask for Transmit Queue Empty.

LSC

Sets mask for Link Status Change.

297

Initial

Field

Bit(s)

Description

Value

Sets mask for Receive Sequence Error.

RXSEQ

This is a reserved bit for the 82541xx and 82547GI/EI. Set to 0b.

RXDMT0

Sets mask for Receive Descriptor Minimum Threshold hit.

Reserved

Should be written with 0b to ensure future compatibility.

RXO

Sets mask for on Receiver FIFO Overrun.

RXT0

Sets mask for Receiver Timer Interrupt.

Reserved

Should be written with 0b to ensure future compatibility.

MDAC

Sets mask for MDI/O Access Complete Interrupt.

Sets mask for Receiving /C/ ordered sets.

RXCFG

This is a reserved bit for the 82541xx and 82547GI/EI. Set to 0b.

Reserved

Should be written with 0b to ensure future compatibility (not

applicable to the 82544GC/EI).

Sets mask for PHY Interrupt (not applicable to the 82544GC/EI).

PHYINT

This is a reserved bit for the 82541xx and 82547GI/EI. Set to 0b.

GPI

14:11

Sets mask for General Purpose Interrupts (82544GC/EI only).

GPI

14:13

Sets mask for General Purpose Interrupts.

Sets the mask for Transmit Descriptor Low Threshold hit (not

TXD_LOW

applicable to the 82544GC/EI).

Sets mask for Small Receive Packet Detection (not applicable to

SRPD

the 82544GC/EI).

Reserved

31:17

Should be written with 0b to ensure future compatibility.

13.4.21

Interrupt Mask Clear Register

IMC (000D8h; W)

Software uses this register to disable an interrupt. Interrupts are presented to the bus interface only

when the mask bit is set to 1b and the cause bit set to 1b. The status of the mask bit is reflected in

the Interrupt Mask Set/Read Register (see Section 13.4.20), and the status of the cause bit is

reflected in the Interrupt Cause Read Register (see Section 13.4.17).

Software blocks interrupts by clearing the corresponding mask bit. This is accomplished by writing

a 1b to the corresponding bit in this register. Bits written with 0b are unchanged (their mask status

does not change).

298

Software should write a 1b to the reserved bits to ensure future compatibility. Since this register

masks interrupts when 1b is written to the corresponding (defined) bits, then writing 1b to the

reserved bits ensures that the software is never called to handle an interrupt that the software is not

aware exists.

Note: For the 82547GI/EI, programmers need to first write (clear) the IMS and IMC registers due to a

Hub Link bus being occupied. This results in an interrupt de-assertion message that can’t to be sent

out. When a future interrupt assertion message is generated, two messages are re-ordered and sent

out. This signals APIC that the 82547GI/EI is in a de-asserted state when it is actually in an

asserted state, which causes a system dead lock. To avoid a system dead lock, first clear the IMS

and IMC registers by writing FFFFh and then re-assert IRQ enable.

Table 13-66. IMC Register Bit Description

Reserved

IMC Bits

Initial

Field

Bit(s)

Description

Value

TXDW

Clears mask for Transmit Descriptor Written Back.

TXQE

Clears mask for Transmit Queue Empty.

LSC

Clears mask for Link Status Change.

Clears mask for Receive Sequence Error.

RXSEQ

This is a reserved bit for the 82541xx and 82547GI/EI. Set to 0b.

RXDMT0

Sets mask for Receive Descriptor Minimum Threshold hit.

Reserved: Should be written with 1b to ensure future

Reserved

compatibility.

RXO

Clears mask for on Receiver FIFO Overrun.

RXT0

Clears mask for Receiver Timer Interrupt.

Reserved: Should be written with 1b to ensure future

Reserved

compatibility.

MDAC

Clears mask for MDI/O Access Complete Interrupt.

Clears mask for Receiving /C/ ordered sets.

RXCFG

This is a reserved bit for the 82541xx and 82547GI/EI. Set to 0b.

Reserved: Should be written with 1b to ensure future

Reserved

compatibility (not applicable to the 82544GC/EI).

Clears PHY Interrupts (not applicable to the 82544GC/EI).

PHYINT

This is a reserved bit for the 82541xx and 82547GI/EI. Set to 0b.

GPI

14:11

Clears General Purpose Interrupts (82544GC/EI only).

GPI

14:13

Clears General Purpose Interrupts.

299

Initial

Field

Bit(s)

Description

Value

Clears the mask for Transmit Descriptor Low Threshold hit (not

TXD_LOW

applicable to the 82544GC/EI).

Clears mask for Small Receive Packet Detect Interrupt (not

SRPD

applicable to the 82544GC/EI).

Reserved

31:17

Should be written with 1b to ensure future compatibility.

13.4.22

Receive Control Register

RCTL (00100h; R/W)

This register controls all Ethernet controller receiver functions.

Table 13-67. RCTL Register Bit Description

Reserved

Receive Control Bits

Initial

Field

Bit(s)

Description

Value

Reserved

Write to 0b for future compatibility.

Receiver Enable

The receiver is enabled when this bit is 1b. Writing this bit to 0b

stops reception after receipt of any in-progress packets. Data

remains in the receive FIFO until the device is re-enabled.

Disabling or re-enabling the receiver does not reinitialize the packet

filter logic that demarcates packet start and end locations in the

FIFO; Therefore the receiver must be reset before re-enabling it.

Store Bad Packets

0b = do not store.

1b = store bad packets.

When set, the Ethernet controller stores bad packets (CRC error,

SBP

symbol error, sequence error, length error, alignment error, short

packets or where carrier extension or RX_ERR errors) that pass the

filter function in host memory. When the Ethernet controller is in

promiscuous mode, and SBP is set, it might possibly store all

packets.

Unicast Promiscuous Enabled

0b = Disabled.

1b = Enabled.

UPE

When set, passes without filtering out all received unicast packets.

Otherwise, the Ethernet controller accepts or rejects unicast

packets based on the received packet destination address match

with 1 of the 16 stored addresses.

300

Initial

Field

Bit(s)

Description

Value

Multicast Promiscuous Enabled

0b = Disabled.

1b = Enabled.

MPE

When set, passes without filtering out all received multicast packets.

Otherwise, the Ethernet controller accepts or rejects a multicast

packet based on its 4096-bit vector multicast filtering table.

Long Packet Reception Enable

0b = Disabled.

1b = Enabled.

LPE controls whether long packet reception is permitted. When LPE

LPE

is cleared, the Ethernet controller discards packets longer than

1522 bytes. When LPE is set, the Ethernet controller discards

packets that are longer than 16384 bytes.

For the 82541xx and 82547GI/EI, packets larger than 2 KB require

full duplex operation.

Loopback mode.

Controls the loopback mode of the Ethernet controller.

00b = No loopback.

01b = Undefined.

10b = Undefined.

11b = PHY or external SerDes loopback.

LBM

7:6

All loopback modes are only allowed when the Ethernet controller is

configured for full-duplex operation. Receive data from transmit

data looped back internally to the SerDes or internal PHY. In TBI

mode (82544GC/EI), the EWRAP signal is asserted.

Note: The 82540EP/EM, 82541xx, and 82547GI/EI do not support

SerDes functionality.

Receive Descriptor Minimum Threshold Size

The corresponding interrupt ICR.RXDMT0 is set each time the

fractional number of free descriptors becomes equal to RDMTS.

The following table lists which fractional values correspond to

RDMTS values. The size of the total receiver circular descriptor

RDMTS

9:8

buffer is set by RDLEN. See Section 13.4.27 for details regarding

RDLEN.

00b = Free Buffer threshold is set to 1/2 of RDLEN.

01b = Free Buffer threshold is set to 1/4 of RDLEN.

10b = Free Buffer threshold is set to 1/8 of RDLEN.

11b = Reserved.

Reserved

11:10

Should be written with 0b to ensure future compatibility.

Reads as 0b.

Multicast Offset

The Ethernet controller is capable of filtering multicast packets

based on 4096-bit vector multicast filtering table. The MO

determines which bits of the incoming multicast address are used in

13:12

looking up the 4096-bit vector.

00b = bits [47:36] of received destination multicast address.

01b = bits [46:35] of received destination multicast address.

10b = bits [45:34] of received destination multicast address.

11b = bits [43:32] of received destination multicast address.

Reserved

Should be written with 0 to ensure future compatibility

Reads as 0

301

Initial

Field

Bit(s)

Description

Value

Broadcast Accept Mode.

0 = ignore broadcast; 1 = accept broadcast packets.

When set, passes and does not filter out all received broadcast

BAM

packets. Otherwise, the Ethernet controller accepts, or rejects a

broadcast packet only if it matches through perfect or imperfect

filters.

Receive Buffer Size

Controls the size of the receive buffers, allowing the software to

trade off between system performance and storage space. Small

buffers maximize memory efficiency at the cost of multiple

descriptors for bigger packets.

RCTL.BSEX = 0b:

00b = 2048 Bytes.

BSIZE

17:16

01b = 1024 Bytes.

10b = 512 Bytes.

1b1 = 256 Bytes.

RCTL.BSEX = 1b:

00b = Reserved; software should not program this value.

01b = 16384 Bytes.

10b = 8192 Bytes.

11b = 4096 Bytes.

VLAN Filter Enable¹

0b = Disabled (filter table does not decide packet acceptance).

1b = Enabled (filter table decides packet acceptance for 802.1Q

packets).

VFE

Three bits control the VLAN filter table. RCTL.VFE determines

whether the VLAN filter table participates in the packet acceptance

criteria. RCTL.CFIEN and RCTL.CFI are used to decide whether

the CFI bit found in the 802.1Q packet’s tag should be used as part

of the acceptance criteria.

Canonical Form Indicator Enable

0b = Disabled (CFI bit found in received 802.1Q packet’s tag is not

CFIEN

compared to decide packet acceptance).

1b = Enabled (CFI bit found in received 802.1Q packet’s tag must

match RCTL.CFI to accept 802.1Q type packet.

Canonical Form Indicator bit value

CFI

If RCTL.CFIEN is set, then 802.1Q packets with CFI equal to this

field is accepted; otherwise, the 802.1Q packet is discarded.

Reserved

Should be written with 0b to ensure future compatibility.

Reads as 0b.

Discard Pause Frames

0 = incoming pause frames subject to filter comparison.

1 = incoming pause frames are filtered out even if they match filter

registers.

DPF

DPF controls the DMA function of flow control PAUSE packets

addressed to the station address (RAH/L[0]). If a packet is a valid

flow control packet and is addressed to the station’s address, it is

not transferred to host memory if RCTL.DPF = 1b. However, it is

transferred when DPF is set to 0b.

302

Initial

Field

Bit(s)

Description

Value

Pass MAC Control Frames

0b = Do not (specially) pass MAC control frames.

1b = Pass any MAC control frame (type field value of 8808h) that

does not contain the pause opcode of 0001h.

PMCF controls the DMA function of MAC control frames (other than

PMCF

flow control). A MAC control frame in this context must be

addressed to either the MAC control frame multicast address or the

station address, match the type field and NOT match the PAUSE

opcode of 0001h. If PMCF = 1b then frames meeting this criteria are

transferred to host memory. Otherwise, they are filtered out.

Reserved

Should be written with 0b to ensure future compatibility.

Reads as 0b.

Buffer Size Extension

BSEX

When set to one, the original BSIZE values are multiplied by 16.

Refer to the RCTL.BSIZE bit description.

Strip Ethernet CRC from incoming packet

0b = Do not strip CRC field.

1b = Strip CRC field.

SECRC

Controls whether the hardware strips the Ethernet CRC from the

received packet. This stripping occurs prior to any checksum

calculations. The stripped CRC is not transferred to host memory

and is not included in the length reported in the descriptor.

Reserved

31:27

Should be written with 0b to ensure future compatibility.

Reads as 0b.

Not applicable to the 82541ER.

303

13.4.23

Flow Control Receive Threshold Low

FCRTL (02160h; R/W)

This register contains the receive threshold used to determine when to send an XON packet. It

counts in units of bytes. Each time the receive FIFO crosses the receive high threshold

FCRTH.RTH (filling up), and then crosses the receive low threshold FCRTL.RTL, with

FCRTL.XONE enabled, hardware transmits an XON frame.

Flow control reception/transmission are negotiated capabilities by the Auto-Negotiation process.

When the Ethernet controller is manually configured, flow control operation is determined by the

CTRL.RFCE and CTRL.TFCE bits.

Table 13-68. FCRTL Register Bit Description

16 15

3 2

XONE¹

Reserved

RTL

82544GC/EI, 82541xx, and 82547GI/EI only.

Initial

Field

Bit(s)

Description

Value

Reserved

2:0

Should be written with 0b to ensure future compatibility.

Reads as 0b.

Receive Threshold Low.

FIFO low water mark for flow control transmission. Each time the

receive FIFO crosses the receive high threshold FCRTH.RTH and

RTL

15:3

later crosses the receive low threshold FCRTL.RTL with

FCRTL.XONE enabled, hardware transmits an XON frame (a

PAUSE frame with a timer value of 0b).

RTL is provided in units of 8 bytes.

Reserved

31:16

Should be written with 0b for future compatibility.

Reads as 0b.

XON Enable (82544GC/EI, 82541xx, and 82547GI/EI only)

0b = Disabled.

1b = Enabled.

XONE

When set, enables the Ethernet controller to transmit XON packets

based on receive FIFO crosses FCRTL.RTL threshold value, or

based on external pins XOFF and XON.

304

13.4.24

Flow Control Receive Threshold High

FCRTH (02168h; R/W)

This register contains the receive threshold used to determine when to send an XOFF packet. It

counts in units of bytes. Each time the receive FIFO reaches the fullness indicated by FCRTH,

hardware transmits a PAUSE frame if the transmission of flow control frames is enabled

(CTRL.TFCE).

Flow control reception/transmission are negotiated capabilities by the Auto-Negotiation process.

When the Ethernet controller is manually configured, flow control operation is determined by the

CTRL.RFCE & CTRL.TFCE bits.

Table 13-69. FCRTH Register Bit Description

16 15

3 2

XFCE¹

Reserved

RTH

82544GC/EI only.

Initial

Field

Bit(s)

Description

Value

Reserved

2:0

Should be written with 0 for future compatibility

Reads as 0

Receive Threshold High.

FIFO high water mark for flow control transmission.

RTH

15:3

Each time the receive FIFO reaches the fullness indicated by RTH,

the Ethernet controller transmits a Pause packet if enabled to do so.

Reserved

31:16

Should be written with 0b for future compatibility.

Reads as 0b.

External Flow Control Enabled (82544GC/EI only)

0b = Disabled.

1b = Enabled.

Allows the Ethernet controller to send XOFF and XON frames based

on external pins XOFF and XON. The transmission of pause frames

must be also enabled through the CTRL.TFCE control bit. When the

XFCE

XOFF signal is asserted high, the Ethernet controller transmits a

single XOFF frame. The assertion of XON (after deassertion of

XOFF) initiates an XON frame transmission, if enabled by

FCRTL.XONE. The assertion/deassertion of XON is required

between assertions of XOFF in order to send another XOFF frame.

This behavior also provides a built-in hysteresis mechanism.

305

13.4.25

Receive Descriptor Base Address Low

RDBAL (02800h;R/W)

This register contains the lower bits of the 64-bit descriptor base address. The four low-order

aligned block of data.

Table 13-70. RDBAL Register Bit Description

RDBAL

Initial

Field

Bit(s)

Description

Value

3:0

Ignored on writes. Returns 0b on reads.

RDBAL

31:4

Receive Descriptor Base Address Low.

13.4.26

Receive Descriptor Base Address High

RDBAH (02804h; R/W)

This register contains the upper 32 bits of the 64-bit Descriptor Base Address.

Table 13-71. RDBAH Register Bit Description

RDBAH

Initial

Field

Bit(s)

Description

Value

RDBAH

31:0

Receive Descriptor Base Address [63:32]

306

13.4.27

Receive Descriptor Length

RDLEN (02808h; R/W)

This register determines the number of bytes allocated to the circular receive descriptor buffer. This

value must be 128-byte aligned (the maximum cache line size). Since each descriptor is 16 bytes in

length, the total number of receive descriptors is always a multiple of eight.

Table 13-72. RDLEN Register Bit Description

20 19

7 6

Reserved

LEN

Initial

Field

Bit(s)

Description

Value

Zero value

Zero

6:0

Ignore on write. Reads back as 0b.

Receive Descriptor length

LEN

19:7

Provides the number of receive descriptors (in a multiple of eight).

Reserved

31:20

Should be written with 0b to ensure future compatibility.

Reads as 0b.

13.4.28

Receive Descriptor Head

RDH (02810h; R/W)

This register contains the head pointer for the receive descriptor buffer. The register points to a 16-

byte datum. Hardware controls the pointer. The only time that software should write to this register

is after a reset (RCTL.RST or CTRL.RST) and before enabling the receiver function (RCTL.EN).

If software were to write to this register while the receive function was enabled, the on-chip

descriptor buffers can be invalidated and other indeterminate operations might result. Reading the

descriptor head to determine which buffers are finished is not reliable.

Table 13-73. RDH Register Bit Description

16 15

Reserved

RDH

Initial

Field

Bit(s)

Description

Value

RDH

15:0

Receive Descriptor Head.

Reserved. Should be written with 0b for future compatibility.

Reserved

31:16

Reads as 0b.

307

PCI/PCI-X Family of Gigabit Ethernet Controllers. Software Developer’s Manual (2009) - page 4