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Intel 64 and IA-32 Architectures. Software Developer’s Manual (2026) - page 67

INTEL® SGX INSTRUCTION REFERENCES

EADD-Add a Page to an Uninitialized Enclave

Opcode/

Op/En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EAX = 01H

IR

V/V

SGX1

This leaf function adds a page to an uninitialized enclave.

ENCLS[EADD]

Instruction Operand Encoding

Op/En

EAX

RBX

RCX

IR

EADD (In)

Address of a PAGEINFO (In)

Address of the destination EPC page (In)

Description

This leaf function copies a source page from non-enclave memory into the EPC, associates the EPC page with an

SECS page residing in the EPC, and stores the linear address and security attributes in EPCM. As part of the asso-

ciation, the enclave offset and the security attributes are measured and extended into the SECS.MRENCLAVE. This

instruction can only be executed when current privilege level is 0.

RBX contains the effective address of a PAGEINFO structure while RCX contains the effective address of an EPC

page. The table below provides additional information on the memory parameter of EADD leaf function.

EADD Memory Parameter Semantics

PAGEINFO

PAGEINFO.SECS

PAGEINFO.SRCPGE

PAGEINFO.SECINFO

EPCPAGE

Read access permitted

Read/Write access permit-

Read access permitted

Read access permitted

Write access permitted

by Non Enclave

ted by Enclave

by Non Enclave

by Non Enclave

by Enclave

The instruction faults if any of the following:

EADD Faulting Conditions

The operands are not properly aligned.

Unsupported security attributes are set.

Refers to an invalid SECS.

Reference is made to an SECS that is locked by another thread.

The EPC page is locked by another thread.

RCX does not contain an effective address of an EPC page.

The EPC page is already valid.

If security attributes specifies a TCS and the source page specifies unsupported

TCS values or fields.

The SECS has been initialized.

The specified enclave offset is outside of the enclave address space.

Concurrency Restrictions

Table 41-7. Base Concurrency Restrictions of EADD

Base Concurrency Restrictions

Leaf

Parameter

Access

On Conflict

EADD

Target [DS:RCX]

Exclusive

#GP

SECS [DS:RBX]PAGEINFO.SECS

Shared

#GP

EADD-Add a Page to an Uninitialized Enclave

Vol. 3D

41-13

INTEL® SGX INSTRUCTION REFERENCES

Table 41-8. Additional Concurrency Restrictions of EADD

Additional Concurrency Restrictions

vs. EACCEPT, EACCEPTCOPY,

Leaf

Parameter

vs. EADD, EEXTEND, EINIT

vs. ETRACK

EMODPE, EMODPR, EMODT

Access

On Conflict

Access

On Conflict

Access

On Conflict

EADD

Target [DS:RCX]

Concurrent

Concurrent

Concurrent

SECS [DS:RBX]PAGE-

Concurrent

Exclusive

#GP

Concurrent

INFO.SECS

Operation

Temp Variables in EADD Operational Flow

Name

Type

Size (bits)

Description

TMP_SRCPGE

Effective Address

32/64

Effective address of the source page.

TMP_SECS

Effective Address

32/64

Effective address of the SECS destination page.

TMP_SECINFO

Effective Address

32/64

Effective address of an SECINFO structure which contains security

attributes of the page to be added.

SCRATCH_SECINFO

SECINFO

512

Scratch storage for holding the contents of DS:TMP_SECINFO.

TMP_LINADDR

Unsigned Integer

64

Holds the linear address to be stored in the EPCM and used to

calculate TMP_ENCLAVEOFFSET.

TMP_ENCLAVEOFFSET

Enclave Offset

64

The page displacement from the enclave base address.

TMPUPDATEFIELD

SHA256 Buffer

512

Buffer used to hold data being added to TMP_SECS.MRENCLAVE.

IF (DS:RBX is not 32Byte Aligned)

THEN #GP(0); FI;

IF (DS:RCX is not 4KByte Aligned)

THEN #GP(0); FI;

IF (DS:RCX does not resolve within an EPC)

THEN #PF(DS:RCX); FI;

TMP_SRCPGE := DS:RBX.SRCPGE;

TMP_SECS := DS:RBX.SECS;

TMP_SECINFO := DS:RBX.SECINFO;

TMP_LINADDR := DS:RBX.LINADDR;

IF (DS:TMP_SRCPGE is not 4KByte aligned or DS:TMP_SECS is not 4KByte aligned or

DS:TMP_SECINFO is not 64Byte aligned or TMP_LINADDR is not 4KByte aligned)

THEN #GP(0); FI;

IF (DS:TMP_SECS does not resolve within an EPC)

THEN #PF(DS:TMP_SECS); FI;

SCRATCH_SECINFO := DS:TMP_SECINFO;

(* Check for misconfigured SECINFO flags*)

IF (SCRATCH_SECINFO reserved fields are not zero or

41-14

Vol. 3D

EADD-Add a Page to an Uninitialized Enclave

INTEL® SGX INSTRUCTION REFERENCES

EAUG-Add a Page to an Initialized Enclave

Opcode/

Op/En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EAX = 0DH

IR

V/V

SGX2

This leaf function adds a page to an initialized enclave.

ENCLS[EAUG]

Instruction Operand Encoding

Op/En

EAX

RBX

RCX

IR

EAUG (In)

Address of a PAGEINFO (In)

Address of the destination EPC page (In)

Description

This leaf function zeroes a page of EPC memory, associates the EPC page with an SECS page residing in the EPC,

and stores the linear address and security attributes in the EPCM. As part of the association, the security attributes

are configured to prevent access to the EPC page until a corresponding invocation of the EACCEPT leaf or EACCEPT-

COPY leaf confirms the addition of the new page into the enclave. This instruction can only be executed when

current privilege level is 0.

RBX contains the effective address of a PAGEINFO structure while RCX contains the effective address of an EPC

page. The table below provides additional information on the memory parameter of the EAUG leaf function.

EAUG Memory Parameter Semantics

PAGEINFO

PAGEINFO.SECS

PAGEINFO.SRCPGE

PAGEINFO.SECINFO

EPCPAGE

Read access permit-

Read/Write access permit-

Read access permitted by

Write access permitted by

Must be zero

ted by Non Enclave

ted by Enclave

Non Enclave

Enclave

The instruction faults if any of the following:

EAUG Faulting Conditions

The operands are not properly aligned.

Unsupported security attributes are set.

Refers to an invalid SECS.

Reference is made to an SECS that is locked by another thread.

The EPC page is locked by another thread.

RCX does not contain an effective address of an EPC page.

The EPC page is already valid.

The specified enclave offset is outside of the enclave address space.

The SECS has been initialized.

Concurrency Restrictions

Table 41-9. Base Concurrency Restrictions of EAUG

Base Concurrency Restrictions

Leaf

Parameter

Access

On Conflict

EAUG

Target [DS:RCX]

Exclusive

#GP

SECS [DS:RBX]PAGEINFO.SECS

Shared

#GP

41-18

Vol. 3D

EAUG-Add a Page to an Initialized Enclave

INTEL® SGX INSTRUCTION REFERENCES

Table 41-10. Additional Concurrency Restrictions of EAUG

Additional Concurrency Restrictions

vs. EACCEPT, EACCEPTCOPY,

Leaf

Parameter

vs. EADD, EEXTEND, EINIT

vs. ETRACK

EMODPE, EMODPR, EMODT

Access

On Conflict

Access

On Conflict

Access

On Conflict

EAUG

Target [DS:RCX]

Concurrent

Concurrent

Concurrent

SECS [DS:RBX]PAGE-

Concurrent

Concurrent

Concurrent

INFO.SECS

Operation

Temp Variables in EAUG Operational Flow

Name

Type

Size (bits)

Description

TMP_SECS

Effective Address

32/64

Effective address of the SECS destination page.

TMP_SECINFO

Effective Address

32/64

Effective address of an SECINFO structure which contains security

attributes of the page to be added.

SCRATCH_SECINFO

SECINFO

512

Scratch storage for holding the contents of DS:TMP_SECINFO.

TMP_LINADDR

Unsigned Integer

64

Holds the linear address to be stored in the EPCM and used to

calculate TMP_ENCLAVEOFFSET.

IF (DS:RBX is not 32Byte Aligned)

THEN #GP(0); FI;

IF (DS:RCX is not 4KByte Aligned)

THEN #GP(0); FI;

IF (DS:RCX does not resolve within an EPC)

THEN #PF(DS:RCX); FI;

TMP_SECS := DS:RBX.SECS;

TMP_SECINFO := DS:RBX.SECINFO;

IF (DS:RBX.SECINFO is not 0)

THEN

IF (DS:TMP_SECINFO is not 64B aligned)

THEN #GP(0); FI;

FI;

TMP_LINADDR := DS:RBX.LINADDR;

IF ( DS:TMP_SECS is not 4KByte aligned or TMP_LINADDR is not 4KByte aligned )

THEN #GP(0); FI;

IF DS:RBX.SRCPAGE is not 0

THEN #GP(0); FI;

IF (DS:TMP_SECS does not resolve within an EPC)

THEN #PF(DS:TMP_SECS); FI;

(* Check the EPC page for concurrency *)

EAUG-Add a Page to an Initialized Enclave

Vol. 3D

41-19

INTEL® SGX INSTRUCTION REFERENCES

EBLOCK-Mark a page in EPC as Blocked

Opcode/

Op/En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EAX = 09H

IR

V/V

SGX1

This leaf function marks a page in the EPC as blocked.

ENCLS[EBLOCK]

Instruction Operand Encoding

Op/En

EAX

RCX

IR

EBLOCK (In)

Return error code (Out)

Effective address of the EPC page (In)

Description

This leaf function causes an EPC page to be marked as BLOCKED. This instruction can only be executed when

current privilege level is 0.

The content of RCX is an effective address of an EPC page. The DS segment is used to create linear address.

Segment override is not supported.

An error code is returned in RAX.

The table below provides additional information on the memory parameter of EBLOCK leaf function.

EBLOCK Memory Parameter Semantics

EPCPAGE

Read/Write access permitted by Enclave

The error codes are:

Table 41-11. EBLOCK Return Value in RAX

Error Code (see Table 41-3)

Description

No Error

EBLOCK successful.

SGX_BLKSTATE

Page already blocked. This value is used to indicate to a VMM that the page was already in

BLOCKED state as a result of EBLOCK and thus will need to be restored to this state when it is

eventually reloaded (using ELDB).

SGX_ENTRYEPOCH_LOCKED

SECS locked for Entry Epoch update. This value indicates that an ETRACK is currently

executing on the SECS. The EBLOCK should be reattempted.

SGX_NOTBLOCKABLE

Page type is not one which can be blocked.

SGX_PG_INVLD

Page is not valid and cannot be blocked.

SGX_EPC_PAGE_CONFLICT

Page is being written by EADD, EAUG, ECREATE, ELDU/B, EMODT, or EWB.

Concurrency Restrictions

Table 41-12. Base Concurrency Restrictions of EBLOCK

Base Concurrency Restrictions

Leaf

Parameter

Access

On Conflict

EBLOCK

Target [DS:RCX]

Shared

SGX_EPC_PAGE_CONFLICT

41-22

Vol. 3D

EBLOCK-Mark a page in EPC as Blocked

INTEL® SGX INSTRUCTION REFERENCES

Table 41-13. Additional Concurrency Restrictions of EBLOCK

Additional Concurrency Restrictions

vs. EACCEPT, EACCEPTCOPY,

Leaf

Parameter

vs. EADD, EEXTEND, EINIT

vs. ETRACK

EMODPE, EMODPR, EMODT

Access

On Conflict

Access

On Conflict

Access

On Conflict

EBLOCK

Target [DS:RCX]

Concurrent

Concurrent

Concurrent

Operation

Temp Variables in EBLOCK Operational Flow

Name

Type

Size (Bits)

Description

TMP_BLKSTATE

Integer

64

Page is already blocked.

IF (DS:RCX is not 4KByte Aligned)

THEN #GP(0); FI;

IF (DS:RCX does not resolve within an EPC)

THEN #PF(DS:RCX); FI;

RFLAGS.ZF,CF,PF,AF,OF,SF := 0;

RAX := 0;

(* Check the EPC page for concurrency*)

IF (EPC page in use)

THEN

RFLAGS.ZF := 1;

RAX := SGX_EPC_PAGE_CONFLICT;

GOTO DONE;

FI;

IF (EPCM(DS:RCX). VALID = 0)

THEN

RFLAGS.ZF := 1;

RAX := SGX_PG_INVLD;

GOTO DONE;

FI;

IF ( (EPCM(DS:RCX).PT ≠ PT_REG) and (EPCM(DS:RCX).PT ≠ PT_TCS) and (EPCM(DS:RCX).PT ≠ PT_TRIM)

and EPCM(DS:RCX).PT ≠ PT_SS_FIRST) and (EPCM(DS:RCX).PT ≠ PT_SS_REST))

THEN

RFLAGS.CF := 1;

IF (EPCM(DS:RCX).PT = PT_SECS)

THEN RAX := SGX_PG_IS_SECS;

ELSE RAX := SGX_NOTBLOCKABLE;

FI;

GOTO DONE;

FI;

(* Check if the page is already blocked and report blocked state *)

TMP_BLKSTATE := EPCM(DS:RCX).BLOCKED;

EBLOCK-Mark a page in EPC as Blocked

Vol. 3D

41-23

INTEL® SGX INSTRUCTION REFERENCES

ECREATE-Create an SECS page in the Enclave Page Cache

Opcode/

Op/En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EAX = 00H

IR

V/V

SGX1

This leaf function begins an enclave build by creating an SECS

ENCLS[ECREATE]

page in EPC.

Instruction Operand Encoding

Op/En

EAX

RBX

RCX

IR

ECREATE (In)

Address of a PAGEINFO (In)

Address of the destination SECS page (In)

Description

ENCLS[ECREATE] is the first instruction executed in the enclave build process. ECREATE copies an SECS structure

outside the EPC into an SECS page inside the EPC. The internal structure of SECS is not accessible to software.

ECREATE will set up fields in the protected SECS and mark the page as valid inside the EPC. ECREATE initializes or

checks unused fields.

Software sets the following fields in the source structure: SECS:BASEADDR, SECS:SIZE in bytes, ATTRIBUTES,

CONFIGID, and CONFIGSVN. SECS:BASEADDR must be naturally aligned on an SECS.SIZE boundary. SECS.SIZE

must be at least 2 pages (8192).

The source operand RBX contains an effective address of a PAGEINFO structure. PAGEINFO contains an effective

address of a source SECS and an effective address of an SECINFO. The SECS field in PAGEINFO is not used.

The RCX register is the effective address of the destination SECS. It is an address of an empty slot in the EPC. The

SECS structure must be page aligned. SECINFO flags must specify the page as an SECS page.

ECREATE Memory Parameter Semantics

PAGEINFO

PAGEINFO.SRCPGE

PAGEINFO.SECINFO

EPCPAGE

Read access permitted by

Read access permitted by

Read access permitted by Non

Write access permitted by

Non Enclave

Non Enclave

Enclave

Enclave

ECREATE will fault if the SECS target page is in use; already valid; outside the EPC. It will also fault if addresses are

not aligned; unused PAGEINFO fields are not zero.

If the amount of space needed to store the SSA frame is greater than the amount specified in SECS.SSAFRAME-

SIZE, a #GP(0) results. The amount of space needed for an SSA frame is computed based on DS:TMP_-

SECS.ATTRIBUTES.XFRM size. Details of computing the size can be found Section 42.7.

Concurrency Restrictions

Table 41-14. Base Concurrency Restrictions of ECREATE

Base Concurrency Restrictions

Leaf

Parameter

Access

On Conflict

ECREATE

SECS [DS:RCX]

Exclusive

#GP

ECREATE-Create an SECS page in the Enclave Page Cache

Vol. 3D

41-25

INTEL® SGX INSTRUCTION REFERENCES

Table 41-15. Additional Concurrency Restrictions of ECREATE

Additional Concurrency Restrictions

vs. EACCEPT, EACCEPTCOPY,

Leaf

Parameter

vs. EADD, EEXTEND, EINIT

vs. ETRACK

EMODPE, EMODPR, EMODT

Access

On Conflict

Access

On Conflict

Access

On Conflict

ECREATE

SECS [DS:RCX]

Concurrent

Concurrent

Concurrent

Operation

Temp Variables in ECREATE Operational Flow

Name

Type

Size (Bits)

Description

TMP_SRCPGE

Effective Address

32/64

Effective address of the SECS source page.

TMP_SECS

Effective Address

32/64

Effective address of the SECS destination page.

TMP_SECINFO

Effective Address

32/64

Effective address of an SECINFO structure which contains security

attributes of the SECS page to be added.

TMP_XSIZE

SSA Size

64

The size calculation of SSA frame.

TMP_MISC_SIZE

MISC Field Size

64

Size of the selected MISC field components.

TMPUPDATEFIELD

SHA256 Buffer

512

Buffer used to hold data being added to TMP_SECS.MRENCLAVE.

IF (DS:RBX is not 32Byte Aligned)

THEN #GP(0); FI;

IF (DS:RCX is not 4KByte Aligned)

THEN #GP(0); FI;

IF (DS:RCX does not resolve within an EPC)

THEN #PF(DS:RCX); FI;

TMP_SRCPGE := DS:RBX.SRCPGE;

TMP_SECINFO := DS:RBX.SECINFO;

IF (DS:TMP_SRCPGE is not 4KByte aligned or DS:TMP_SECINFO is not 64Byte aligned)

THEN #GP(0); FI;

IF (DS:RBX.LINADDR ! = 0 or DS:RBX.SECS ≠ 0)

THEN #GP(0); FI;

(* Check for misconfigured SECINFO flags*)

IF (DS:TMP_SECINFO reserved fields are not zero or DS:TMP_SECINFO.FLAGS.PT ≠ PT_SECS)

THEN #GP(0); FI;

TMP_SECS := RCX;

IF (EPC entry in use)

THEN #GP(0); FI;

IF (EPCM(DS:RCX).VALID = 1)

THEN #PF(DS:RCX); FI;

41-26

Vol. 3D

ECREATE-Create an SECS page in the Enclave Page Cache

INTEL® SGX INSTRUCTION REFERENCES

EDBGRD-Read From a Debug Enclave

Opcode/

Op/En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EAX = 04H

IR

V/V

SGX1

This leaf function reads a dword/quadword from a debug enclave.

ENCLS[EDBGRD]

Instruction Operand Encoding

Op/En

EAX

RBX

RCX

Return error

IR

EDBGRD (In)

Data read from a debug enclave (Out)

Address of source memory in the EPC (In)

code (Out)

Description

This leaf function copies a quadword/doubleword from an EPC page belonging to a debug enclave into the RBX

register. Eight bytes are read in 64-bit mode, four bytes are read in non-64-bit modes. The size of data read cannot

be overridden.

The effective address of the source location inside the EPC is provided in the register RCX.

EDBGRD Memory Parameter Semantics

EPCQW

Read access permitted by Enclave

The error codes are:

Table 41-16. EDBGRD Return Value in RAX

Error Code (see Table 41-3)

Description

No Error

EDBGRD successful.

SGX_PAGE_NOT_DEBUGGABLE

The EPC page cannot be accessed because it is in the PENDING or MODIFIED state.

The instruction faults if any of the following:

EDBGRD Faulting Conditions

RCX points into a page that is an SECS.

RCX does not resolve to a naturally aligned linear address.

RCX points to a page that does not belong to an

RCX points to a location inside a TCS that is beyond the architectural size of the

enclave that is in debug mode.

TCS (SGX_TCS_LIMIT).

An operand causing any segment violation.

May page fault.

CPL > 0.

This instruction ignores the EPCM RWX attributes on the enclave page. Consequently, violation of EPCM RWX attri-

butes via EDBGRD does not result in a #GP.

41-30

Vol. 3D

EDBGRD-Read From a Debug Enclave

INTEL® SGX INSTRUCTION REFERENCES

Concurrency Restrictions

Table 41-17. Base Concurrency Restrictions of EDBGRD

Base Concurrency Restrictions

Leaf

Parameter

Access

On Conflict

EDBGRD

Target [DS:RCX]

Shared

#GP

Table 41-18. Additional Concurrency Restrictions of EDBGRD

Additional Concurrency Restrictions

vs. EACCEPT, EACCEPTCOPY,

Leaf

Parameter

vs. EADD, EEXTEND, EINIT

vs. ETRACK

EMODPE, EMODPR, EMODT

Access

On Conflict

Access

On Conflict

Access

On Conflict

EDBGRD

Target [DS:RCX]

Concurrent

Concurrent

Concurrent

Operation

Temp Variables in EDBGRD Operational Flow

Name

Type

Size (Bits)

Description

TMP_MODE64

Binary

1

((IA32_EFER.LMA = 1) && (CS.L = 1))

TMP_SECS

64

Physical address of SECS of the enclave to which source operand belongs.

TMP_MODE64 := ((IA32_EFER.LMA = 1) && (CS.L = 1));

IF ( (TMP_MODE64 = 1) and (DS:RCX is not 8Byte Aligned) )

THEN #GP(0); FI;

IF ( (TMP_MODE64 = 0) and (DS:RCX is not 4Byte Aligned) )

THEN #GP(0); FI;

IF (DS:RCX does not resolve within an EPC)

THEN #PF(DS:RCX); FI;

(* make sure no other Intel SGX instruction is accessing the same EPCM entry *)

IF (Another instruction modifying the same EPCM entry is executing)

THEN #GP(0); FI;

IF (EPCM(DS:RCX).VALID = 0)

THEN #PF(DS:RCX); FI;

(* make sure that DS:RCX (SOURCE) is pointing to a PT_REG or PT_TCS or PT_VA or PT_SS_FIRST or PT_SS_REST *)

IF ( (EPCM(DS:RCX).PT ≠ PT_REG) and (EPCM(DS:RCX).PT ≠ PT_TCS) and (EPCM(DS:RCX).PT ≠ PT_VA)

and (EPCM(DS:RCX).PT ≠ PT_SS_FIRST) and (EPCM(DS:RCX).PT ≠ PT_SS_REST))

THEN #PF(DS:RCX); FI;

(* make sure that DS:RCX points to an accessible EPC page *)

IF (EPCM(DS:RCX).PENDING is not 0 or (EPCM(DS:RCX).MODIFIED is not 0) )

THEN

RFLAGS.ZF := 1;

EDBGRD-Read From a Debug Enclave

Vol. 3D

41-31

INTEL® SGX INSTRUCTION REFERENCES

EDBGWR-Write to a Debug Enclave

Opcode/

Op/En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EAX = 05H

IR

V/V

SGX1

This leaf function writes a dword/quadword to a debug enclave.

ENCLS[EDBGWR]

Instruction Operand Encoding

Op/En

EAX

RBX

RCX

Return error

IR

EDBGWR (In)

Data to be written to a debug enclave (In)

Address of Target memory in the EPC (In)

code (Out)

Description

This leaf function copies the content in EBX/RBX to an EPC page belonging to a debug enclave. Eight bytes are

written in 64-bit mode, four bytes are written in non-64-bit modes. The size of data cannot be overridden.

The effective address of the target location inside the EPC is provided in the register RCX.

EDBGWR Memory Parameter Semantics

EPCQW

Write access permitted by Enclave

The instruction faults if any of the following:

EDBGWR Faulting Conditions

RCX points into a page that is an SECS.

RCX does not resolve to a naturally aligned linear address.

RCX points to a page that does not belong to an

RCX points to a location inside a TCS that is not the FLAGS word.

enclave that is in debug mode.

An operand causing any segment violation.

May page fault.

CPL > 0.

The error codes are:

Table 41-19. EDBGWR Return Value in RAX

Error Code (see Table 41-3)

Description

No Error

EDBGWR successful.

SGX_PAGE_NOT_DEBUGGABLE

The EPC page cannot be accessed because it is in the PENDING or MODIFIED state.

This instruction ignores the EPCM RWX attributes on the enclave page. Consequently, violation of EPCM RWX attri-

butes via EDBGRD does not result in a #GP.

41-34

Vol. 3D

EDBGWR-Write to a Debug Enclave

INTEL® SGX INSTRUCTION REFERENCES

Concurrency Restrictions

Table 41-20. Base Concurrency Restrictions of EDBGWR

Base Concurrency Restrictions

Leaf

Parameter

Access

On Conflict

EDBGWR

Target [DS:RCX]

Shared

#GP

Table 41-21. Additional Concurrency Restrictions of EDBGWR

Additional Concurrency Restrictions

vs. EACCEPT, EACCEPTCOPY,

Leaf

Parameter

vs. EADD, EEXTEND, EINIT

vs. ETRACK

EMODPE, EMODPR, EMODT

Access

On Conflict

Access

On Conflict

Access

On Conflict

EDBGWR

Target [DS:RCX]

Concurrent

Concurrent

Concurrent

Operation

Temp Variables in EDBGWR Operational Flow

Name

Type

Size (Bits)

Description

TMP_MODE64

Binary

1

((IA32_EFER.LMA = 1) && (CS.L = 1)).

TMP_SECS

64

Physical address of SECS of the enclave to which source operand belongs.

TMP_MODE64 := ((IA32_EFER.LMA = 1) && (CS.L = 1));

IF ( (TMP_MODE64 = 1) and (DS:RCX is not 8Byte Aligned) )

THEN #GP(0); FI;

IF ( (TMP_MODE64 = 0) and (DS:RCX is not 4Byte Aligned) )

THEN #GP(0); FI;

IF (DS:RCX does not resolve within an EPC)

THEN #PF(DS:RCX); FI;

(* make sure no other Intel SGX instruction is accessing the same EPCM entry *)

IF (Another instruction modifying the same EPCM entry is executing)

THEN #GP(0); FI;

IF (EPCM(DS:RCX).VALID = 0)

THEN #PF(DS:RCX); FI;

(* make sure that DS:RCX (DST) is pointing to a PT_REG or PT_TCS or PT_SS_FIRST or PT_SS_REST *)

IF ( (EPCM(DS:RCX).PT ≠ PT_REG) and (EPCM(DS:RCX).PT ≠ PT_TCS)

and (EPCM(DS:RCX).PT ≠ PT_SS_FIRST) and (EPCM(DS:RCX).PT ≠ PT_SS_REST))

THEN #PF(DS:RCX); FI;

(* make sure that DS:RCX points to an accessible EPC page *)

IF ( (EPCM(DS:RCX).PENDING is not 0) or (EPCM(DS:RCS).MODIFIED is not 0) )

THEN

RFLAGS.ZF := 1;

EDBGWR-Write to a Debug Enclave

Vol. 3D

41-35

INTEL® SGX INSTRUCTION REFERENCES

EEXTEND-Extend Uninitialized Enclave Measurement by 256 Bytes

Opcode/

Op/En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EAX = 06H

IR

V/V

SGX1

This leaf function measures 256 bytes of an uninitialized enclave

ENCLS[EEXTEND]

page.

Instruction Operand Encoding

Op/En

EAX

EBX

RCX

Effective address of the SECS of the

IR

EEXTEND (In)

Effective address of a 256-byte chunk in the EPC (In)

data chunk (In)

Description

This leaf function updates the MRENCLAVE measurement register of an SECS with the measurement of an EXTEND

string compromising of “EEXTEND” || ENCLAVEOFFSET || PADDING || 256 bytes of the enclave page. This instruc-

tion can only be executed when current privilege level is 0 and the enclave is uninitialized.

RBX contains the effective address of the SECS of the region to be measured. The address must be the same as the

one used to add the page into the enclave.

RCX contains the effective address of the 256 byte region of an EPC page to be measured. The DS segment is used

to create linear addresses. Segment override is not supported.

EEXTEND Memory Parameter Semantics

EPC[RCX]

Read access by Enclave

The instruction faults if any of the following:

EEXTEND Faulting Conditions

RBX points to an address not 4KBytes aligned.

RBX does not resolve to an SECS.

RBX does not point to an SECS page.

RBX does not point to the SECS page of the data chunk.

RCX points to an address not 256B aligned.

RCX points to an unused page or a SECS.

RCX does not resolve in an EPC page.

If SECS is locked.

If the SECS is already initialized.

May page fault.

CPL > 0.

Concurrency Restrictions

Table 41-22. Base Concurrency Restrictions of EEXTEND

Base Concurrency Restrictions

Leaf

Parameter

Access

On Conflict

EEXTEND

Target [DS:RCX]

Shared

#GP

SECS [DS:RBX]

Concurrent

41-38

Vol. 3D

EEXTEND-Extend Uninitialized Enclave Measurement by 256 Bytes

INTEL® SGX INSTRUCTION REFERENCES

Table 41-23. Additional Concurrency Restrictions of EEXTEND

Additional Concurrency Restrictions

vs. EACCEPT, EACCEPTCOPY,

Leaf

Parameter

vs. EADD, EEXTEND, EINIT

vs. ETRACK

EMODPE, EMODPR, EMODT

Access

On Conflict

Access

On Conflict

Access

On Conflict

EEXTEND

Target [DS:RCX]

Concurrent

Concurrent

Concurrent

SECS [DS:RBX]

Concurrent

Exclusive

#GP

Concurrent

Operation

Temp Variables in EEXTEND Operational Flow

Name

Type

Size (Bits)

Description

TMP_SECS

64

Physical address of SECS of the enclave to which source operand belongs.

TMP_ENCLAVEOFFS

Enclave Offset

64

The page displacement from the enclave base address.

ET

TMPUPDATEFIELD

SHA256 Buffer

512

Buffer used to hold data being added to TMP_SECS.MRENCLAVE.

TMP_MODE64 := ((IA32_EFER.LMA = 1) && (CS.L = 1));

IF (DS:RBX is not 4096 Byte Aligned)

THEN #GP(0); FI;

IF (DS:RBX does not resolve to an EPC page)

THEN #PF(DS:RBX); FI;

IF (DS:RCX is not 256Byte Aligned)

THEN #GP(0); FI;

IF (DS:RCX does not resolve within an EPC)

THEN #PF(DS:RCX); FI;

(* make sure no other Intel SGX instruction is accessing EPCM *)

IF (Other instructions accessing EPCM)

THEN #GP(0); FI;

IF (EPCM(DS:RCX). VALID = 0)

THEN #PF(DS:RCX); FI;

(* make sure that DS:RCX (DST) is pointing to a PT_REG or PT_TCS or PT_SS_FIRST or PT_SS_REST *)

IF ( (EPCM(DS:RCX).PT ≠ PT_REG) and (EPCM(DS:RCX).PT ≠ PT_TCS)

and (EPCM(DS:RCX).PT ≠ PT_SS_FIRST) and (EPCM(DS:RCX).PT ≠ PT_SS_REST))

THEN #PF(DS:RCX); FI;

TMP_SECS := Get_SECS_ADDRESS();

IF (DS:RBX does not resolve to TMP_SECS)

THEN #GP(0); FI;

(* make sure no other instruction is accessing MRENCLAVE or ATTRIBUTES.INIT *)

IF ( (Other instruction accessing MRENCLAVE) or (Other instructions checking or updating the initialized state of the SECS))

EEXTEND-Extend Uninitialized Enclave Measurement by 256 Bytes

Vol. 3D

41-39

INTEL® SGX INSTRUCTION REFERENCES

EINIT-Initialize an Enclave for Execution

Opcode/

Op/En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EAX = 02H

IR

V/V

SGX1

This leaf function initializes the enclave and makes it ready to

ENCLS[EINIT]

execute enclave code.

Instruction Operand Encoding

Op/En

EAX

RBX

RCX

RDX

IR

EINIT (In)

Error code (Out)

Address of SIGSTRUCT (In)

Address of SECS (In)

Address of EINITTOKEN (In)

Description

This leaf function is the final instruction executed in the enclave build process. After EINIT, the MRENCLAVE

measurement is complete, and the enclave is ready to start user code execution using the EENTER instruction.

EINIT takes the effective address of a SIGSTRUCT and EINITTOKEN. The SIGSTRUCT describes the enclave

including MRENCLAVE, ATTRIBUTES, ISVSVN, a 3072 bit RSA key, and a signature using the included key.

SIGSTRUCT must be populated with two values, q1 and q2. These are calculated using the formulas shown below:

q1 = floor(Signature² / Modulus);

q2 = floor((Signature³ - q1 * Signature * Modulus) / Modulus);

The EINITTOKEN contains the MRENCLAVE, MRSIGNER, and ATTRIBUTES. These values must match the corre-

sponding values in the SECS. If the EINITTOKEN was created with a debug launch key, the enclave must be in

debug mode as well.

Signature

Ve

rify

PubKey

Hashed

ATTRIBUTES

ATTRIBUTEMASK

Check

MRENCLAVE

SIGSTRUCT

MRSIGNER

If VALID=1,

Check

MRSIGNER

D

S:RBX

ATTRIBUTES

If VALID=1,

MRENCLAVE

DS:RDX

Check

EINIT

EINITTOKEN

Copy

ATTRIBUTES

SECS

DS:RCX

MRENCLAVE

Check

ENCLAVE

EPC

Figure 41-1. Relationships Between SECS, SIGSTRUCT, and EINITTOKEN

EINIT-Initialize an Enclave for Execution

Vol. 3D

41-41

INTEL® SGX INSTRUCTION REFERENCES

EINIT Memory Parameter Semantics

SIGSTRUCT

SECS

EINITTOKEN

Access by non-Enclave

Read/Write access by Enclave

Access by non-Enclave

EINIT performs the following steps, which can be seen in Figure 41-1:

1. Validates that SIGSTRUCT is signed using the enclosed public key.

2. Checks that the completed computation of SECS.MRENCLAVE equals SIGSTRUCT.HASHENCLAVE.

3. Checks that no controlled ATTRIBUTES bits are set in SIGSTRUCT.ATTRIBUTES unless the SHA256 digest of

SIGSTRUCT.MODULUS equals IA32_SGX_LEPUBKEYHASH.

4. Checks that the result of bitwise and-ing SIGSTRUCT.ATTRIBUTEMASK with SIGSTRUCT.ATTRIBUTES equals

the result of bitwise and-ing SIGSTRUCT.ATTRIBUTEMASK with SECS.ATTRIBUTES.

5. If EINITTOKEN.VALID is 0, checks that the SHA256 digest of SIGSTRUCT.MODULUS equals IA32_SGX_LEPUB-

KEYHASH.

6. If EINITTOKEN.VALID is 1, checks the validity of EINITTOKEN.

7. If EINITTOKEN.VALID is 1, checks that EINITTOKEN.MRENCLAVE equals SECS.MRENCLAVE.

8. If EINITTOKEN.VALID is 1 and EINITTOKEN.ATTRIBUTES.DEBUG is 1, SECS.ATTRIBUTES.DEBUG must be 1.

9. Commits SECS.MRENCLAVE, and sets SECS.MRSIGNER, SECS.ISVSVN, and SECS.ISVPRODID based on

SIGSTRUCT.

10. Update the SECS as Initialized.

Periodically, EINIT polls for certain asynchronous events. If such an event is detected, it completes with failure code

(ZF=1 and RAX = SGX_UNMASKED_EVENT), and RIP is incremented to point to the next instruction. These events

includes external interrupts, non-maskable interrupts, system-management interrupts, machine checks, INIT

signals, and the VMX-preemption timer. EINIT does not fail if the pending event is inhibited (e.g., external inter-

rupts could be inhibited due to blocking by MOV SS blocking or by STI).

The following bits in RFLAGS are cleared: CF, PF, AF, OF, and SF. When the instruction completes with an error,

RFLAGS.ZF is set to 1, and the corresponding error bit is set in RAX. If no error occurs, RFLAGS.ZF is cleared and

RAX is set to 0.

The error codes are:

Table 41-24. EINIT Return Value in RAX

Error Code (see Table 41-3)

Description

No Error

EINIT successful.

SGX_INVALID_SIG_STRUCT

If SIGSTRUCT contained an invalid value.

SGX_INVALID_ATTRIBUTE

If SIGSTRUCT contains an unauthorized attributes mask.

SGX_INVALID_MEASUREMENT

If SIGSTRUCT contains an incorrect measurement.

If EINITTOKEN contains an incorrect measurement.

SGX_INVALID_SIGNATURE

If signature does not validate with enclosed public key.

SGX_INVALID_LICENSE

If license is invalid.

SGX_INVALID_CPUSVN

If license SVN is unsupported.

SGX_UNMASKED_EVENT

If an unmasked event is received before the instruction completes its operation.

41-42

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EINIT-Initialize an Enclave for Execution

INTEL® SGX INSTRUCTION REFERENCES

Concurrency Restrictions

Table 41-25. Base Concurrency Restrictions of EINIT

Base Concurrency Restrictions

Leaf

Parameter

Access

On Conflict

EINIT

SECS [DS:RCX]

Shared

#GP

Table 41-26. Additional Concurrency Restrictions of ENIT

Additional Concurrency Restrictions

vs. EACCEPT, EACCEPTCOPY,

Leaf

Parameter

vs. EADD, EEXTEND, EINIT

vs. ETRACK

EMODPE, EMODPR, EMODT

Access

On Conflict

Access

On Conflict

Access

On Conflict

EINIT

SECS [DS:RCX]

Concurrent

Exclusive

#GP

Concurrent

Operation

Temp Variables in EINIT Operational Flow

Name

Type

Size

Description

TMP_SIG

SIGSTRUCT

1808Bytes

Temp space for SIGSTRUCT.

TMP_TOKEN

EINITTOKEN

304Bytes

Temp space for EINITTOKEN.

TMP_MRENCLAVE

32Bytes

Temp space for calculating MRENCLAVE.

TMP_MRSIGNER

32Bytes

Temp space for calculating MRSIGNER.

CONTROLLED_ATTRIBU

ATTRIBUTES

16Bytes

Constant mask of all ATTRIBUTE bits that can only be set for authorized

TES

enclaves.

TMP_KEYDEPENDENCIE

Buffer

224Bytes

Temp space for key derivation.

S

TMP_EINITTOKENKEY

16Bytes

Temp space for the derived EINITTOKEN Key.

TMP_SIG_PADDING

PKCS Padding

352Bytes

The value of the top 352 bytes from the computation of Signature³

Buffer

modulo MRSIGNER.

(* make sure SIGSTRUCT and SECS are aligned *)

IF ( (DS:RBX is not 4KByte Aligned) or (DS:RCX is not 4KByte Aligned) )

THEN #GP(0); FI;

(* make sure the EINITTOKEN is aligned *)

IF (DS:RDX is not 512Byte Aligned)

THEN #GP(0); FI;

(* make sure the SECS is inside the EPC *)

IF (DS:RCX does not resolve within an EPC)

THEN #PF(DS:RCX); FI;

TMP_SIG[14463:0] := DS:RBX[14463:0]; // 1808 bytes

TMP_TOKEN[2423:0] := DS:RDX[2423:0]; // 304 bytes

EINIT-Initialize an Enclave for Execution

Vol. 3D

41-43

INTEL® SGX INSTRUCTION REFERENCES

ELDB/ELDU-Load an EPC Page and Mark its State

Opcode/

Op/En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EAX = 07H

IR

V/V

SGX1

This leaf function loads, verifies an EPC page and marks the page

ENCLS[ELDB]

as blocked.

EAX = 08H

IR

V/V

SGX1

This leaf function loads, verifies an EPC page and marks the page

ENCLS[ELDU]

as unblocked.

Instruction Operand Encoding

Op/En

EAX

RBX

RCX

RDX

ELDB/ELDU

Return error

Address of the PAGEINFO

Address of the EPC page

Address of the version-

IR

(In)

code (Out)

(In)

(In)

array slot (In)

Description

This leaf function copies a page from regular main memory to the EPC. As part of the copying process, the page is

cryptographically authenticated and decrypted. This instruction can only be executed when current privilege level

is 0.

The ELDB leaf function sets the BLOCK bit in the EPCM entry for the destination page in the EPC after copying. The

ELDU leaf function clears the BLOCK bit in the EPCM entry for the destination page in the EPC after copying.

RBX contains the effective address of a PAGEINFO structure; RCX contains the effective address of the destination

EPC page; RDX holds the effective address of the version array slot that holds the version of the page.

The table below provides additional information on the memory parameter of ELDB/ELDU leaf functions.

ELDB/ELDU Memory Parameter Semantics

PAGEINFO

PAGEINFO.SRCPGE

PAGEINFO.PCMD

PAGEINFO.SECS

EPCPAGE

Version-Array Slot

Non-enclave

Non-enclave read

Non-enclave read

Enclave read/write

Read/Write access

Read/Write access per-

read access

access

access

access

permitted by Enclave

mitted by Enclave

The error codes are:

Table 41-27. ELDB/ELDU Return Value in RAX

Error Code (see Table 41-3)

Description

No Error

ELDB/ELDU successful.

SGX_MAC_COMPARE_FAIL

If the MAC check fails.

Concurrency Restrictions

Table 41-28. Base Concurrency Restrictions of ELDB/ELDU

Base Concurrency Restrictions

Leaf

Parameter

Access

On Conflict

ELDB/ELDU

Target [DS:RCX]

Exclusive

#GP

VA [DS:RDX]

Shared

#GP

SECS [DS:RBX]PAGEINFO.SECS

Shared

#GP

ELDB/ELDU-Load an EPC Page and Mark its State

Vol. 3D

41-49

INTEL® SGX INSTRUCTION REFERENCES

Table 41-29. Additional Concurrency Restrictions of ELDB/ELDU

Additional Concurrency Restrictions

vs. EACCEPT,

vs. EADD, EEXTEND,

Leaf

Parameter

EACCEPTCOPY, EMODPE,

vs. ETRACK

EINIT

EMODPR, EMODT

Access

On Conflict

Access

On Conflict

Access

On Conflict

ELDB/ELDU

Target [DS:RCX]

Concurrent

Concurrent

Concurrent

VA [DS:RDX]

Concurrent

Concurrent

Concurrent

SECS [DS:RBX]PAGEINFO.SECS

Concurrent

Concurrent

Concurrent

Operation

Temp Variables in ELDB/ELDU Operational Flow

Name

Type

Size (Bits)

Description

TMP_SRCPGE

Memory page

4KBytes

TMP_SECS

Memory page

4KBytes

TMP_PCMD

PCMD

128 Bytes

TMP_HEADER

MACHEADER

128 Bytes

TMP_VER

UINT64

64

TMP_MAC

UINT128

128

TMP_PK

UINT128

128

Page encryption/MAC key.

SCRATCH_PCMD

PCMD

128 Bytes

(* Check PAGEINFO and EPCPAGE alignment *)

IF ( (DS:RBX is not 32Byte Aligned) or (DS:RCX is not 4KByte Aligned) )

THEN #GP(0); FI;

IF (DS:RCX does not resolve within an EPC)

THEN #PF(DS:RCX); FI;

(* Check VASLOT alignment *)

IF (DS:RDX is not 8Byte aligned)

THEN #GP(0); FI;

IF (DS:RDX does not resolve within an EPC)

THEN #PF(DS:RDX); FI;

TMP_SRCPGE := DS:RBX.SRCPGE;

TMP_SECS := DS:RBX.SECS;

TMP_PCMD := DS:RBX.PCMD;

(* Check alignment of PAGEINFO (RBX) linked parameters. Note: PCMD pointer is overlaid on top of PAGEINFO.SECINFO field *)

IF ( (DS:TMP_PCMD is not 128Byte aligned) or (DS:TMP_SRCPGE is not 4KByte aligned) )

THEN #GP(0); FI;

(* Check concurrency of EPC by other Intel SGX instructions *)

IF (other instructions accessing EPC)

41-50

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ELDB/ELDU-Load an EPC Page and Mark its State

INTEL® SGX INSTRUCTION REFERENCES

EMODPR-Restrict the Permissions of an EPC Page

Opcode/

Op/En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EAX = 0EH

IR

V/V

SGX2

This leaf function restricts the access rights associated with a

ENCLS[EMODPR]

EPC page in an initialized enclave.

Instruction Operand Encoding

Op/En

EAX

RBX

RCX

IR

EMODPR (In)

Return Error Code (Out)

Address of a SECINFO (In)

Address of the destination EPC page (In)

Description

This leaf function restricts the access rights associated with an EPC page in an initialized enclave. THE RWX bits of

the SECINFO parameter are treated as a permissions mask; supplying a value that does not restrict the page

permissions will have no effect. This instruction can only be executed when current privilege level is 0.

RBX contains the effective address of a SECINFO structure while RCX contains the effective address of an EPC page.

The table below provides additional information on the memory parameter of the EMODPR leaf function.

EMODPR Memory Parameter Semantics

SECINFO

EPCPAGE

Read access permitted by Non Enclave

Read/Write access permitted by Enclave

The instruction faults if any of the following:

EMODPR Faulting Conditions

The operands are not properly aligned.

If unsupported security attributes are set.

The Enclave is not initialized.

SECS is locked by another thread.

The EPC page is locked by another thread.

RCX does not contain an effective address of an EPC page in the running enclave.

The EPC page is not valid.

The error codes are:

Table 41-30. EMODPR Return Value in RAX

Error Code (see Table 41-3)

Description

No Error

EMODPR successful.

SGX_PAGE_NOT_MODIFIABLE

The EPC page cannot be modified because it is in the PENDING or MODIFIED state.

SGX_EPC_PAGE_CONFLICT

Page is being written by EADD, EAUG, ECREATE, ELDU/B, EMODT, or EWB.

Concurrency Restrictions

Table 41-31. Base Concurrency Restrictions of EMODPR

Base Concurrency Restrictions

Leaf

Parameter

Access

On Conflict

EMODPR

Target [DS:RCX]

Shared

#GP

41-54

Vol. 3D

EMODPR-Restrict the Permissions of an EPC Page

INTEL® SGX INSTRUCTION REFERENCES

Table 41-32. Additional Concurrency Restrictions of EMODPR

Additional Concurrency Restrictions

vs. EACCEPT, EACCEPTCOPY,

Leaf

Parameter

vs. EADD, EEXTEND, EINIT

vs. ETRACK

EMODPE, EMODPR, EMODT

Access

On Conflict

Access

On Conflict

Access

On Conflict

EMODPR

Target [DS:RCX]

Exclusive

SGX_EP-

Concurrent

Concurrent

C_PAGE_CON-

FLICT

Operation

Temp Variables in EMODPR Operational Flow

Name

Type

Size (bits)

Description

TMP_SECS

Effective Address

32/64

Physical address of SECS to which EPC operand belongs.

SCRATCH_SECINFO

SECINFO

512

Scratch storage for holding the contents of DS:RBX.

IF (DS:RBX is not 64Byte Aligned)

THEN #GP(0); FI;

IF (DS:RCX is not 4KByte Aligned)

THEN #GP(0); FI;

IF (DS:RCX does not resolve within an EPC)

THEN #PF(DS:RCX); FI;

SCRATCH_SECINFO := DS:RBX;

(* Check for misconfigured SECINFO flags*)

IF ( (SCRATCH_SECINFO reserved fields are not zero ) or

(SCRATCH_SECINFO.FLAGS.R is 0 and SCRATCH_SECINFO.FLAGS.W is not 0) )

THEN #GP(0); FI;

(* Check concurrency with SGX1 or SGX2 instructions on the EPC page *)

IF (SGX1 or other SGX2 instructions accessing EPC page)

THEN #GP(0); FI;

IF (EPCM(DS:RCX).VALID is 0 )

THEN #PF(DS:RCX); FI;

(* Check the EPC page for concurrency *)

IF (EPC page in use by another SGX2 instruction)

THEN

RFLAGS.ZF := 1;

RAX := SGX_EPC_PAGE_CONFLICT;

GOTO DONE;

FI;

IF (EPCM(DS:RCX).PENDING is not 0 or (EPCM(DS:RCX).MODIFIED is not 0) )

THEN

RFLAGS.ZF := 1;

EMODPR-Restrict the Permissions of an EPC Page

Vol. 3D

41-55

INTEL® SGX INSTRUCTION REFERENCES

EMODT-Change the Type of an EPC Page

Opcode/

Op/En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EAX = 0FH

IR

V/V

SGX2

This leaf function changes the type of an existing EPC page.

ENCLS[EMODT]

Instruction Operand Encoding

Op/En

EAX

RBX

RCX

IR

EMODT (In)

Return Error Code (Out)

Address of a SECINFO (In)

Address of the destination EPC page (In)

Description

This leaf function modifies the type of an EPC page. The security attributes are configured to prevent access to the

EPC page at its new type until a corresponding invocation of the EACCEPT leaf confirms the modification. This

instruction can only be executed when current privilege level is 0.

RBX contains the effective address of a SECINFO structure while RCX contains the effective address of an EPC

page. The table below provides additional information on the memory parameter of the EMODT leaf function.

EMODT Memory Parameter Semantics

SECINFO

EPCPAGE

Read access permitted by Non Enclave

Read/Write access permitted by Enclave

The instruction faults if any of the following:

EMODT Faulting Conditions

The operands are not properly aligned.

If unsupported security attributes are set.

The Enclave is not initialized.

SECS is locked by another thread.

The EPC page is locked by another thread.

RCX does not contain an effective address of an EPC page in the running enclave.

The EPC page is not valid.

The error codes are:

Table 41-33. EMODT Return Value in RAX

Error Code (see Table 41-3)

Description

No Error

EMODT successful.

SGX_PAGE_NOT_MODIFIABLE

The EPC page cannot be modified because it is in the PENDING or MODIFIED state.

SGX_EPC_PAGE_CONFLICT

Page is being written by EADD, EAUG, ECREATE, ELDU/B, EMODPR, or EWB.

Concurrency Restrictions

Table 41-34. Base Concurrency Restrictions of EMODT

Base Concurrency Restrictions

Leaf

Parameter

Access

On Conflict

EMODT

Target [DS:RCX]

Exclusive

SGX_EPC_PAGE_CONFLICT

EMODT-Change the Type of an EPC Page

Vol. 3D

41-57

INTEL® SGX INSTRUCTION REFERENCES

Table 41-35. Additional Concurrency Restrictions of EMODT

Additional Concurrency Restrictions

vs. EACCEPT, EACCEPTCOPY,

Leaf

Parameter

vs. EADD, EEXTEND, EINIT

vs. ETRACK

EMODPE, EMODPR, EMODT

Access

On Conflict

Access

On Conflict

Access

On Conflict

EMODT

Target [DS:RCX]

Exclusive

SGX_EP-

Concurrent

Concurrent

C_PAGE_CON-

FLICT

Operation

Temp Variables in EMODT Operational Flow

Name

Type

Size (bits)

Description

TMP_SECS

Effective Address

32/64

Physical address of SECS to which EPC operand belongs.

SCRATCH_SECINFO

SECINFO

512

Scratch storage for holding the contents of DS:RBX.

IF (DS:RBX is not 64Byte Aligned)

THEN #GP(0); FI;

IF (DS:RCX is not 4KByte Aligned)

THEN #GP(0); FI;

IF (DS:RCX does not resolve within an EPC)

THEN #PF(DS:RCX); FI;

SCRATCH_SECINFO := DS:RBX;

(* Check for misconfigured SECINFO flags*)

IF ( (SCRATCH_SECINFO reserved fields are not zero ) or

!(SCRATCH_SECINFO.FLAGS.PT is PT_TCS or SCRATCH_SECINFO.FLAGS.PT is PT_TRIM) )

THEN #GP(0); FI;

(* Check concurrency with SGX1 instructions on the EPC page *)

IF (other SGX1 instructions accessing EPC page)

THEN

RFLAGS.ZF := 1;

RAX := SGX_EPC_PAGE_CONFLICT;

GOTO DONE;

FI;

IF (EPCM(DS:RCX).VALID is 0)

THEN #PF(DS:RCX); FI;

(* Check the EPC page for concurrency *)

IF (EPC page in use by another SGX2 instruction)

THEN

RFLAGS.ZF := 1;

RAX := SGX_EPC_PAGE_CONFLICT;

GOTO DONE;

FI;

41-58

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EMODT-Change the Type of an EPC Page

INTEL® SGX INSTRUCTION REFERENCES

EPA-Add Version Array

Opcode/

Op/En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EAX = 0AH

IR

V/V

SGX1

This leaf function adds a Version Array to the EPC.

ENCLS[EPA]

Instruction Operand Encoding

Op/En

EAX

RBX

RCX

IR

EPA (In)

PT_VA (In, Constant)

Effective address of the EPC page (In)

Description

This leaf function creates an empty version array in the EPC page whose logical address is given by DS:RCX, and

sets up EPCM attributes for that page. At the time of execution of this instruction, the register RBX must be set to

PT_VA.

The table below provides additional information on the memory parameter of EPA leaf function.

EPA Memory Parameter Semantics

EPCPAGE

Write access permitted by Enclave

Concurrency Restrictions

Table 41-36. Base Concurrency Restrictions of EPA

Base Concurrency Restrictions

Leaf

Parameter

Access

On Conflict

EPA

VA [DS:RCX]

Exclusive

#GP

Table 41-37. Additional Concurrency Restrictions of EPA

Additional Concurrency Restrictions

vs. EACCEPT, EACCEPTCOPY,

Leaf

Parameter

vs. EADD, EEXTEND, EINIT

vs. ETRACK

EMODPE, EMODPR, EMODT

Access

On Conflict

Access

On Conflict

Access

On Conflict

EPA

VA [DS:RCX]

Concurrent

L

Concurrent

Concurrent

Operation

IF (RBX ≠ PT_VA or DS:RCX is not 4KByte Aligned)

THEN #GP(0); FI;

IF (DS:RCX does not resolve within an EPC)

THEN #PF(DS:RCX); FI;

(* Check concurrency with other Intel SGX instructions *)

IF (Other Intel SGX instructions accessing the page)

THEN

#GP(0); FI;

41-60

Vol. 3D

EPA-Add Version Array

INTEL® SGX INSTRUCTION REFERENCES

EREMOVE-Remove a page from the EPC

Opcode/

Op/En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EAX = 03H

IR

V/V

SGX1

This leaf function removes a page from the EPC.

ENCLS[EREMOVE]

Instruction Operand Encoding

Op/En

EAX

RCX

IR

EREMOVE (In)

Return error code (Out)

Effective address of the EPC page (In)

Description

This leaf function causes an EPC page to be un-associated with its SECS and be marked as unused. This instruction

leaf can only be executed when the current privilege level is 0.

The content of RCX is an effective address of an EPC page. The DS segment is used to create linear address.

Segment override is not supported.

The instruction fails if the operand is not properly aligned or does not refer to an EPC page or the page is in use by

another thread, or other threads are running in the enclave to which the page belongs. In addition the instruction

fails if the operand refers to an SECS with associations.

EREMOVE Memory Parameter Semantics

EPCPAGE

Write access permitted by Enclave

The instruction faults if any of the following:

EREMOVE Faulting Conditions

The memory operand is not properly aligned.

The memory operand does not resolve in an EPC page.

Refers to an invalid SECS.

Refers to an EPC page that is locked by another thread.

Another Intel SGX instruction is accessing the EPC page.

RCX does not contain an effective address of an EPC page.

the EPC page refers to an SECS with associations.

The error codes are:

Table 41-38. EREMOVE Return Value in RAX

Error Code (see Table 41-3)

Description

No Error

EREMOVE successful.

SGX_CHILD_PRESENT

If the SECS still have enclave pages loaded into EPC.

SGX_ENCLAVE_ACT

If there are still logical processors executing inside the enclave.

41-62

Vol. 3D

EREMOVE-Remove a page from the EPC

INTEL® SGX INSTRUCTION REFERENCES

Concurrency Restrictions

Table 41-39. Base Concurrency Restrictions of EREMOVE

Base Concurrency Restrictions

Leaf

Parameter

Access

On Conflict

EREMOVE

Target [DS:RCX]

Exclusive

#GP

Table 41-40. Additional Concurrency Restrictions of EREMOVE

Additional Concurrency Restrictions

vs. EACCEPT, EACCEPTCOPY,

Leaf

Parameter

vs. EADD, EEXTEND, EINIT

vs. ETRACK

EMODPE, EMODPR, EMODT

Access

On Conflict

Access

On Conflict

Access

On Conflict

EREMOVE

Target [DS:RCX]

Concurrent

Concurrent

Concurrent

Operation

Temp Variables in EREMOVE Operational Flow

Name

Type

Size (Bits)

Description

TMP_SECS

Effective Address

32/64

Effective address of the SECS destination page.

IF (DS:RCX is not 4KByte Aligned)

THEN #GP(0); FI;

IF (DS:RCX does not resolve to an EPC page)

THEN #PF(DS:RCX); FI;

TMP_SECS := Get_SECS_ADDRESS();

(* Check the EPC page for concurrency *)

IF (EPC page being referenced by another Intel SGX instruction)

THEN

#GP(0); FI;

(* if DS:RCX is already unused, nothing to do*)

IF ( (EPCM(DS:RCX).VALID = 0) or (EPCM(DS:RCX).PT = PT_TRIM AND EPCM(DS:RCX).MODIFIED = 0))

THEN GOTO DONE;

FI;

IF ( (EPCM(DS:RCX).PT = PT_VA) OR

((EPCM(DS:RCX).PT = PT_TRIM) AND (EPCM(DS:RCX).MODIFIED = 0)) )

THEN

EPCM(DS:RCX).VALID := 0;

GOTO DONE;

FI;

IF (EPCM(DS:RCX).PT = PT_SECS)

THEN

IF (DS:RCX has an EPC page associated with it)

THEN

EREMOVE-Remove a page from the EPC

Vol. 3D

41-63

INTEL® SGX INSTRUCTION REFERENCES

ETRACK-Activates EBLOCK Checks

Opcode/

Op/En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EAX = 0CH

IR

V/V

SGX1

This leaf function activates EBLOCK checks.

ENCLS[ETRACK]

Instruction Operand Encoding

Op/En

EAX

RCX

IR

ETRACK (In)

Return error code (Out)

Pointer to the SECS of the EPC page (In)

Description

This leaf function provides the mechanism for hardware to track that software has completed the required TLB

address clears successfully. The instruction can only be executed when the current privilege level is 0.

The content of RCX is an effective address of an EPC page.

The table below provides additional information on the memory parameter of ETRACK leaf function.

ETRACK Memory Parameter Semantics

EPCPAGE

Read/Write access permitted by Enclave

The error codes are:

Table 41-41. ETRACK Return Value in RAX

Error Code (see Table 41-3)

Description

No Error

ETRACK successful.

SGX_PREV_TRK_INCMPL

All processors did not complete the previous shoot-down sequence.

Concurrency Restrictions

Table 41-42. Base Concurrency Restrictions of ETRACK

Base Concurrency Restrictions

Leaf

Parameter

Access

On Conflict

ETRACK

SECS [DS:RCX]

Shared

#GP

Table 41-43. Additional Concurrency Restrictions of ETRACK

Additional Concurrency Restrictions

vs. EACCEPT, EACCEPTCOPY,

Leaf

Parameter

vs. EADD, EEXTEND, EINIT

vs. ETRACK

EMODPE, EMODPR, EMODT

Access

On Conflict

Access

On Conflict

Access

On Conflict

ETRACK

SECS [DS:RCX]

Concurrent

Concurrent

Exclusive

SGX_EP-

C_PAGE_CON-

FLICT

ETRACK-Activates EBLOCK Checks

Vol. 3D

41-65

INTEL® SGX INSTRUCTION REFERENCES

EUPDATESVN-Update CR_CPUSVN

Opcode/

Op/En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EAX = 18H

None

V/V

Bit 10

This leaf function updates the CR_CPUSVN if microcode has been

ENCLS[EUPDATESVN]

updated and EPC is ready.

Description

If EPC is ready for SVN update, this leaf function updates CR_CPUSVN to the currently loaded microcode update

SVN and generates new cryptographic assets. The EPC is ready when no page in the EPC is valid. EREMOVE should

be used to mark all pages as unused.

It is the responsibility of system software to ensure that no other thread is executing or attempts to execute any

ENCLS leaf while executing EUPDATESVN. Concurrency violations between EUPDATESVN and some ENCLS leaves

may cause the ENCLS leaf to generate #GP(0) in ways unexpected to legacy software. System software should also

prevent unnecessary software from having access to EUPDATESVN. For example, enable ENCLS exiting should be

used to prevent VMs that are not part of the management system software from using EUPDATESVN.

The EUPDATESVN leaf function fails if an ENCLS instruction is in progress on any thread, the EPC is not ready for

an update, or there is insufficient entropy in the random number generator. The ZF flag will be set to indicate an

error and a code returned in RAX. If EUPDATESVN was successful but CR_CPUSVN was already up to date, the CF

flag will be set and RAX will indicate that no update occurred.

If insufficient entropy causes a failure, software should repeat the instruction.

The error codes are:

Table 41-44. EUPDATESVN Return Value in RAX

Error Code (see Table 41-3)

Value

Description

No Error

0

EUPDATESVN successful.

SGX_EPC_PAGE_CONFLICT

7

An instruction concurrency rule was violated.

SGX_INSUFFICIENT_ENTROPY

29

RNG contains insufficient entropy.

SGX_EPC_NOT_READY

30

EPC is not ready for SVN update.

SGX_NO_UPDATE

31

EUPDATESVN was successful, but CR_CPUSVN was not updated because

the current SVN is older than CR_CPUSVN.

Concurrency Restrictions

Table 41-45. Base Concurrency Restrictions of EUPDATESVN

Base Concurrency Restrictions

Leaf

Access

On Conflict

EUPDATESVN

Exclusive

SGX_EPC_PAGE_CONFLICT

Table 41-46. Additional Concurrency Restrictions of EUPDATESVN

Additional Concurrency Restrictions

Leaf

vs. EADD, EAUG, ECREATE, ELDB, EPA, EREMOVE, EWB

Access

On Conflict

EUPDATESVN

Exclusive

SGX_EPC_PAGE_CONFLICT

EUPDATESVN-Update CR_CPUSVN

Vol. 3D

41-67

INTEL® SGX INSTRUCTION REFERENCES

Operation

Temp Variables in EUPDATESVN Operational Flow

Name

Type

Size (Bytes)

Description

TMP_CPUSVN

CPUSVN

16

Temporary copy of CR_CPUSVN prior to update.

TMP_KEY

Key

16

Temporary copy of new paging key.

RFLAGS.ZF,CF,PF,AF,OF,SF := 0;

RAX := 0;

IF (Other logical processor is executing an SGX instruction that accesses EPC) THEN

RFLAGS.ZF := 1

RAX := SGX_EPC_PAGE_CONFLICT;

GOTO ERROR_EXIT;

FI

(* Verify EPC is ready *)

IF (the EPC contains any valid pages) THEN

RFLAGS.ZF := 1;

RAX := SGX_EPC_NOT_READY;

GOTO ERROR_EXIT;

FI

(* Refresh paging key *)

TMP_KEY = (* Generate a 128-bit cryptographically random number *)

IF (insufficient entropy available) THEN

RFLAGS.ZF := 1;

RAX := SGX_INSUFFICIENT_ENTROPY;

GOTO ERROR_EXIT;

FI

(* Commit *)

TMP_CPUSVN := CR_CPUSVN;

(* Update CR_CPUSVN to reflect current microcode update SVN *)

(* Determine if info status is needed *)

IF (TMP_CPUSVN = CR_CPUSVN) THEN

RFLAGS.CF := 1;

RAX := SGX_NO_UPDATE;

ELSE

CR_BASE_PK := TMP_KEY[127:0];

FI

ERROR_EXIT:

Flags Affected

ZF is set if an error occurs; otherwise, cleared.

CF is set when the instruction is completed successfully and no SVN update was needed.

PF, AF, OF, and SF are cleared.

41-68

Vol. 3D

EUPDATESVN-Update CR_CPUSVN

INTEL® SGX INSTRUCTION REFERENCES

EWB-Invalidate an EPC Page and Write out to Main Memory

Opcode/

Op/En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EAX = 0BH

IR

V/V

SGX1

This leaf function invalidates an EPC page and writes it out to

ENCLS[EWB]

main memory.

Instruction Operand Encoding

Op/En

EAX

RBX

RCX

RDX

IR

EWB (In)

Error code (Out)

Address of an PAGEINFO (In)

Address of the EPC page (In)

Address of a VA slot (In)

Description

This leaf function copies a page from the EPC to regular main memory. As part of the copying process, the page is

cryptographically protected. This instruction can only be executed when current privilege level is 0.

The table below provides additional information on the memory parameter of EPA leaf function.

EWB Memory Parameter Semantics

PAGEINFO

PAGEINFO.SRCPGE

PAGEINFO.PCMD

EPCPAGE

VASLOT

Non-EPC R/W access

Non-EPC R/W access

Non-EPC R/W access

EPC R/W access

EPC R/W access

The error codes are:

Table 41-47. EWB Return Value in RAX

Error Code (see Table 41-3)

Description

No Error

EWB successful.

SGX_PAGE_NOT_BLOCKED

If page is not marked as blocked.

SGX_NOT_TRACKED

If EWB is racing with ETRACK instruction.

SGX_VA_SLOT_OCCUPIED

Version array slot contained valid entry.

SGX_CHILD_PRESENT

Child page present while attempting to page out enclave.

Concurrency Restrictions

Table 41-48. Base Concurrency Restrictions of EWB

Base Concurrency Restrictions

Leaf

Parameter

Access

On Conflict

EWB

Source [DS:RCX]

Exclusive

#GP

VA [DS:RDX]

Shared

#GP

Table 41-49. Additional Concurrency Restrictions of EWB

Additional Concurrency Restrictions

vs. EACCEPT, EACCEPTCOPY,

Leaf

Parameter

vs. EADD, EEXTEND, EINIT

vs. ETRACK

EMODPE, EMODPR, EMODT

Access

On Conflict

Access

On Conflict

Access

On Conflict

EWB

Source [DS:RCX]

Concurrent

Concurrent

Concurrent

VA [DS:RDX]

Concurrent

Concurrent

Exclusive

EWB-Invalidate an EPC Page and Write out to Main Memory

Vol. 3D

41-69

INTEL® SGX INSTRUCTION REFERENCES

Operation

Temp Variables in EWB Operational Flow

Name

Type

Size (Bytes)

Description

TMP_SRCPGE

Memory page

4096

TMP_PCMD

PCMD

128

TMP_SECS

SECS

4096

TMP_BPEPOCH

UINT64

8

TMP_BPREFCOUNT

UINT64

8

TMP_HEADER

MAC Header

128

TMP_PCMD_ENCLAVEID

UINT64

8

TMP_VER

UINT64

8

TMP_PK

UINT128

16

IF ( (DS:RBX is not 32Byte Aligned) or (DS:RCX is not 4KByte Aligned) )

THEN #GP(0); FI;

IF (DS:RCX does not resolve within an EPC)

THEN #PF(DS:RCX); FI;

IF (DS:RDX is not 8Byte Aligned)

THEN #GP(0); FI;

IF (DS:RDX does not resolve within an EPC)

THEN #PF(DS:RDX); FI;

(* EPCPAGE and VASLOT should not resolve to the same EPC page*)

IF (DS:RCX and DS:RDX resolve to the same EPC page)

THEN #GP(0); FI;

TMP_SRCPGE := DS:RBX.SRCPGE;

(* Note PAGEINFO.PCMD is overlaid on top of PAGEINFO.SECINFO *)

TMP_PCMD := DS:RBX.PCMD;

If (DS:RBX.LINADDR ≠ 0) OR (DS:RBX.SECS ≠ 0)

THEN #GP(0); FI;

IF ( (DS:TMP_PCMD is not 128Byte Aligned) or (DS:TMP_SRCPGE is not 4KByte Aligned) )

THEN #GP(0); FI;

(* Check for concurrent Intel SGX instruction access to the page *)

IF (Other Intel SGX instruction is accessing page)

THEN

#GP(0); FI;

(*Check if the VA Page is being removed or changed*)

IF (VA Page is being modified)

THEN #GP(0); FI;

41-70

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EWB-Invalidate an EPC Page and Write out to Main Memory

INTEL® SGX INSTRUCTION REFERENCES

EACCEPT-Accept Changes to an EPC Page

Opcode/

Op/En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EAX = 05H

IR

V/V

SGX2

This leaf function accepts changes made by system software to

ENCLU[EACCEPT]

an EPC page in the running enclave.

Instruction Operand Encoding

Op/En

EAX

RBX

RCX

IR

EACCEPT (In)

Return Error Code (Out)

Address of a SECINFO (In)

Address of the destination EPC page (In)

Description

This leaf function accepts changes to a page in the running enclave by verifying that the security attributes speci-

fied in the SECINFO match the security attributes of the page in the EPCM. This instruction leaf can only be

executed when inside the enclave.

RBX contains the effective address of a SECINFO structure while RCX contains the effective address of an EPC page.

The table below provides additional information on the memory parameter of the EACCEPT leaf function.

EACCEPT Memory Parameter Semantics

SECINFO

EPCPAGE (Destination)

Read access permitted by Non Enclave

Read access permitted by Enclave

The instruction faults if any of the following:

EACCEPT Faulting Conditions

The operands are not properly aligned.

RBX does not contain an effective address in an EPC page in the running enclave.

The EPC page is locked by another thread.

RCX does not contain an effective address of an EPC page in the running enclave.

The EPC page is not valid.

Page type is PT_REG and MODIFIED bit is 0.

SECINFO contains an invalid request.

Page type is PT_TCS or PT_TRIM and PENDING bit is 0 and MODIFIED bit is 1.

If security attributes of the SECINFO page make

the page inaccessible.

The error codes are:

Table 41-50. EACCEPT Return Value in RAX

Error Code (see Table 41-3)

Description

No Error

EACCEPT successful.

SGX_PAGE_ATTRIBUTES_MISMATCH

The attributes of the target EPC page do not match the expected values.

SGX_NOT_TRACKED

The OS did not complete an ETRACK on the target page.

41-74

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EACCEPT-Accept Changes to an EPC Page

INTEL® SGX INSTRUCTION REFERENCES

Concurrency Restrictions

Table 41-51. Base Concurrency Restrictions of EACCEPT

Base Concurrency Restrictions

Leaf

Parameter

Access

On Conflict

EACCEPT

Target [DS:RCX]

Shared

#GP

SECINFO [DS:RBX]

Concurrent

Table 41-52. Additional Concurrency Restrictions of EACCEPT

Additional Concurrency Restrictions

vs. EACCEPT, EACCEPTCOPY,

Leaf

Parameter

vs. EADD, EEXTEND, EINIT

vs. ETRACK

EMODPE, EMODPR, EMODT

Access

On Conflict

Access

On Conflict

Access

On Conflict

EACCEPT

Target [DS:RCX]

Exclusive

#GP

Concurrent

Concurrent

SECINFO [DS:RBX]

Concurrent

Concurrent

Concurrent

Operation

Temp Variables in EACCEPT Operational Flow

Name

Type

Size (bits)

Description

TMP_SECS

Effective Address

32/64

Physical address of SECS to which EPC operands belongs.

SCRATCH_SECINFO

SECINFO

512

Scratch storage for holding the contents of DS:RBX.

IF (DS:RBX is not 64Byte Aligned)

THEN #GP(0); FI;

IF (DS:RBX is not within CR_ELRANGE)

THEN #GP(0); FI;

IF (DS:RBX does not resolve within an EPC)

THEN #PF(DS:RBX); FI;

IF ( (EPCM(DS:RBX &~FFFH).VALID = 0) or (EPCM(DS:RBX &~FFFH).R = 0) or (EPCM(DS:RBX &~FFFH).PENDING ≠ 0) or

(EPCM(DS:RBX &~FFFH).MODIFIED ≠ 0) or (EPCM(DS:RBX &~FFFH).BLOCKED ≠ 0) or

(EPCM(DS:RBX &~FFFH).PT ≠ PT_REG) or (EPCM(DS:RBX &~FFFH).ENCLAVESECS ≠ CR_ACTIVE_SECS) or

(EPCM(DS:RBX &~FFFH).ENCLAVEADDRESS ≠ (DS:RBX & FFFH)) )

THEN #PF(DS:RBX); FI;

(* Copy 64 bytes of contents *)

SCRATCH_SECINFO := DS:RBX;

(* Check for misconfigured SECINFO flags*)

IF (SCRATCH_SECINFO reserved fields are not zero )

THEN #GP(0); FI;

IF (DS:RCX is not 4KByte Aligned)

THEN #GP(0); FI;

EACCEPT-Accept Changes to an EPC Page

Vol. 3D

41-75

INTEL® SGX INSTRUCTION REFERENCES

EACCEPTCOPY-Initialize a Pending Page

Opcode/

Op/En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EAX = 07H

IR

V/V

SGX2

This leaf function initializes a dynamically allocated EPC page

ENCLU[EACCEPTCOPY]

from another page in the EPC.

Instruction Operand Encoding

Op/En

EAX

RBX

RCX

RDX

Return Error Code

Address of the destina-

Address of the

IR

EACCEPTCOPY (In)

Address of a SECINFO (In)

(Out)

tion EPC page (In)

source EPC page (In)

Description

This leaf function copies the contents of an existing EPC page into an uninitialized EPC page (created by EAUG).

After initialization, the instruction may also modify the access rights associated with the destination EPC page. This

instruction leaf can only be executed when inside the enclave.

RBX contains the effective address of a SECINFO structure while RCX and RDX each contain the effective address

of an EPC page. The table below provides additional information on the memory parameter of the EACCEPTCOPY

leaf function.

EACCEPTCOPY Memory Parameter Semantics

SECINFO

EPCPAGE (Destination)

EPCPAGE (Source)

Read access permitted by Non Enclave

Read/Write access permitted by Enclave

Read access permitted by Enclave

The instruction faults if any of the following:

EACCEPTCOPY Faulting Conditions

The operands are not properly aligned.

If security attributes of the SECINFO page make the page inaccessible.

The EPC page is locked by another thread.

If security attributes of the source EPC page make the page inaccessible.

The EPC page is not valid.

RBX does not contain an effective address in an EPC page in the running enclave.

SECINFO contains an invalid request.

RCX/RDX does not contain an effective address of an EPC page in the running

enclave.

The error codes are:

Table 41-53. EACCEPTCOPY Return Value in RAX

Error Code (see Table 41-3)

Description

No Error

EACCEPTCOPY successful.

SGX_PAGE_ATTRIBUTES_MISMATCH

The attributes of the target EPC page do not match the expected values.

EACCEPTCOPY-Initialize a Pending Page

Vol. 3D

41-79

INTEL® SGX INSTRUCTION REFERENCES

Concurrency Restrictions

Table 41-54. Base Concurrency Restrictions of EACCEPTCOPY

Base Concurrency Restrictions

Leaf

Parameter

Access

On Conflict

EACCEPTCOPY

Target [DS:RCX]

Concurrent

Source [DS:RDX]

Concurrent

SECINFO [DS:RBX]

Concurrent

Table 41-55. Additional Concurrency Restrictions of EACCEPTCOPY

Additional Concurrency Restrictions

vs. EACCEPT, EACCEPTCOPY,

Leaf

Parameter

vs. EADD, EEXTEND, EINIT

vs. ETRACK

EMODPE, EMODPR, EMODT

Access

On Conflict

Access

On Conflict

Access

On Conflict

EACCEPTCOPY

Target [DS:RCX]

Exclusive

#GP

Concurrent

Concurrent

Source [DS:RDX]

Concurrent

Concurrent

Concurrent

SECINFO [DS:RBX]

Concurrent

Concurrent

Concurrent

Operation

Temp Variables in EACCEPTCOPY Operational Flow

Name

Type

Size (bits)

Description

SCRATCH_SECINFO

SECINFO

512

Scratch storage for holding the contents of DS:RBX.

IF (DS:RBX is not 64Byte Aligned)

THEN #GP(0); FI;

IF ( (DS:RCX is not 4KByte Aligned) or (DS:RDX is not 4KByte Aligned) )

THEN #GP(0); FI;

IF ((DS:RBX is not within CR_ELRANGE) or (DS:RCX is not within CR_ELRANGE) or (DS:RDX is not within CR_ELRANGE))

THEN #GP(0); FI;

IF (DS:RBX does not resolve within an EPC)

THEN #PF(DS:RBX); FI;

IF (DS:RCX does not resolve within an EPC)

THEN #PF(DS:RCX); FI;

IF (DS:RDX does not resolve within an EPC)

THEN #PF(DS:RDX); FI;

IF ( (EPCM(DS:RBX &~FFFH).VALID = 0) or (EPCM(DS:RBX &~FFFH).R = 0) or (EPCM(DS:RBX &~FFFH).PENDING ≠ 0) or

(EPCM(DS:RBX &~FFFH).MODIFIED ≠ 0) or (EPCM(DS:RBX &~FFFH).BLOCKED ≠ 0) or (EPCM(DS:RBX &~FFFH).PT ≠ PT_REG) or

(EPCM(DS:RBX &~FFFH).ENCLAVESECS ≠ CR_ACTIVE_SECS) or

(EPCM(DS:RBX &~FFFH).ENCLAVEADDRESS ≠ DS:RBX) )

THEN #PF(DS:RBX); FI;

41-80

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EACCEPTCOPY-Initialize a Pending Page