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Intel 64 and IA-32 Architectures. Software Developer’s Manual (2026) - page 41

VRNDSCALESD-Round Scalar Float64 Value to Include a Given Number of Fraction Bits

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature Flag

Support

EVEX.LLIG.66.0F3A.W1 0B /r ib

A

V/V

AVX512F

Rounds scalar double precision floating-point value in

VRNDSCALESD xmm1 {k1}{z}, xmm2,

OR AVX10.1

xmm3/m64 to a number of fraction bits specified by

xmm3/m64{sae}, imm8

the imm8 field. Stores the result in xmm1 register.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

imm8

Description

Rounds a double precision floating-point value in the low quadword (see Figure 5-29) element of the second source

operand (the third operand) by the rounding mode specified in the immediate operand and places the result in the

corresponding element of the destination operand (the first operand) according to the writemask. The quadword

element at bits 127:64 of the destination is copied from the first source operand (the second operand).

The destination and first source operands are XMM registers, the 2nd source operand can be an XMM register or

memory location. Bits MAXVL-1:128 of the destination register are cleared.

The rounding process rounds the input to an integral value, plus number bits of fraction that are specified by

imm8[7:4] (to be included in the result) and returns the result as a double precision floating-point value.

It should be noticed that no overflow is induced while executing this instruction (although the source is scaled by

the imm8[7:4] value).

The immediate operand also specifies control fields for the rounding operation, three bit fields are defined and

shown in the “Immediate Control Description” figure below. Bit 3 of the immediate byte controls the processor

behavior for a precision exception, bit 2 selects the source of rounding mode control. Bits 1:0 specify a non-sticky

rounding-mode value (immediate control table below lists the encoded values for rounding-mode field).

The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an

SNaN then it will be converted to a QNaN. If DAZ is set to ‘1 then denormals will be converted to zero before

rounding.

The sign of the result of this instruction is preserved, including the sign of zero.

The formula of the operation for VRNDSCALESD is

ROUND(x) = 2^-M*Round_to_INT(x*2^M, round_ctrl),

round_ctrl = imm[3:0];

M=imm[7:4];

The operation of x*2^M is computed as if the exponent range is unlimited (i.e., no overflow ever occurs).

VRNDSCALESD is a more general form of the VEX-encoded VROUNDSD instruction. In VROUNDSD, the formula of

the operation is

ROUND(x) = Round_to_INT(x, round_ctrl),

round_ctrl = imm[3:0];

EVEX encoded version: The source operand is a XMM register or a 64-bit memory location. The destination operand

is a XMM register.

Handling of special case of input values are listed in Table 5-29.

Operation

RoundToIntegerDP(SRC[63:0], imm8[7:0]) {

VRNDSCALESD-Round Scalar Float64 Value to Include a Given Number of Fraction Bits

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VRNDSCALESH-Round Scalar FP16 Value to Include a Given Number of Fraction Bits

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.LLIG.NP.0F3A.W0 0A /r /ib

A

V/V

AVX512_FP16

Round the low FP16 value in xmm3/m16 to a

VRNDSCALESH xmm1{k1}{z}, xmm2,

OR AVX10.1

number of fraction bits specified by the imm8

xmm3/m16 {sae}, imm8

field. Store the result in xmm1 subject to

writemask k1. Bits 127:16 from xmm2 are

copied to xmm1[127:16].

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

A

Scalar

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

imm8 (r)

Description

This instruction rounds the low FP16 value in the second source operand by the rounding mode specified in the

immediate operand (see Table 5-30) and places the result in the destination operand.

Bits 127:16 of the destination operand are copied from the corresponding bits of the first source operand. Bits

MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the destination is updated according

to the writemask.

The rounding process rounds the input to an integral value, plus number bits of fraction that are specified by

imm8[7:4] (to be included in the result), and returns the result as a FP16 value.

Note that no overflow is induced while executing this instruction (although the source is scaled by the imm8[7:4]

value).

The immediate operand also specifies control fields for the rounding operation. Three bit fields are defined and

shown in Table 5-30, “Imm8 Controls for VRNDSCALEPH/VRNDSCALESH.” Bit 3 of the immediate byte controls the

processor behavior for a precision exception, bit 2 selects the source of rounding mode control, and bits 1:0 specify

a non-sticky rounding-mode value.

The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an

SNaN then it will be converted to a QNaN.

The sign of the result of this instruction is preserved, including the sign of zero. Special cases are described in Table

5-31.

If this instruction encoding’s SPE bit (bit 3) in the immediate operand is 1, VRNDSCALESH can set MXCSR.UE

without MXCSR.PE.

The formula of the operation on each data element for VRNDSCALESH is:

ROUND(x) = 2^-M *Round_to_INT(x * 2^M, round_ctrl),

round_ctrl = imm[3:0];

M=imm[7:4];

The operation of x * 2^M is computed as if the exponent range is unlimited (i.e., no overflow ever occurs).

VRNDSCALESH-Round Scalar FP16 Value to Include a Given Number of Fraction Bits

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VRNDSCALESS-Round Scalar Float32 Value to Include a Given Number of Fraction Bits

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature Flag

Support

EVEX.LLIG.66.0F3A.W0 0A /r ib

A

V/V

AVX512F

Rounds scalar single-precision floating-point value in

VRNDSCALESS xmm1 {k1}{z}, xmm2,

OR AVX10.1

xmm3/m32 to a number of fraction bits specified by

xmm3/m32{sae}, imm8

the imm8 field. Stores the result in xmm1 register

under writemask.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Rounds the single precision floating-point value in the low doubleword element of the second source operand (the

third operand) by the rounding mode specified in the immediate operand (see Figure 5-29) and places the result in

the corresponding element of the destination operand (the first operand) according to the writemask. The double-

word elements at bits 127:32 of the destination are copied from the first source operand (the second operand).

The destination and first source operands are XMM registers, the 2nd source operand can be an XMM register or

memory location. Bits MAXVL-1:128 of the destination register are cleared.

The rounding process rounds the input to an integral value, plus number bits of fraction that are specified by

imm8[7:4] (to be included in the result) and returns the result as a single precision floating-point value.

It should be noticed that no overflow is induced while executing this instruction (although the source is scaled by

the imm8[7:4] value).

The immediate operand also specifies control fields for the rounding operation, three bit fields are defined and

shown in the “Immediate Control Description” figure below. Bit 3 of the immediate byte controls the processor

behavior for a precision exception, bit 2 selects the source of rounding mode control. Bits 1:0 specify a non-sticky

rounding-mode value (immediate control tables below lists the encoded values for rounding-mode field).

The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an

SNaN then it will be converted to a QNaN. If DAZ is set to ‘1 then denormals will be converted to zero before

rounding.

The sign of the result of this instruction is preserved, including the sign of zero.

The formula of the operation for VRNDSCALESS is

ROUND(x) = 2^-M*Round_to_INT(x*2^M, round_ctrl),

round_ctrl = imm[3:0];

M=imm[7:4];

The operation of x*2^M is computed as if the exponent range is unlimited (i.e., no overflow ever occurs).

VRNDSCALESS is a more general form of the VEX-encoded VROUNDSS instruction. In VROUNDSS, the formula of

the operation on each element is

ROUND(x) = Round_to_INT(x, round_ctrl),

round_ctrl = imm[3:0];

EVEX encoded version: The source operand is a XMM register or a 32-bit memory location. The destination operand

is a XMM register.

Handling of special case of input values are listed in Table 5-29.

VRNDSCALESS-Round Scalar Float32 Value to Include a Given Number of Fraction Bits

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VRSQRT14PD-Compute Approximate Reciprocals of Square Roots of Packed Float64 Values

Opcode/

Op /

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.128.66.0F38.W1 4E /r

A

V/V

(AVX512VL AND

Computes the approximate reciprocal square roots of

VRSQRT14PD xmm1 {k1}{z},

AVX512F) OR

the packed double precision floating-point values in

xmm2/m128/m64bcst

AVX10.1

xmm2/m128/m64bcst and stores the results in

xmm1. Under writemask.

EVEX.256.66.0F38.W1 4E /r

A

V/V

(AVX512VL AND

Computes the approximate reciprocal square roots of

VRSQRT14PD ymm1 {k1}{z},

AVX512F) OR

the packed double precision floating-point values in

ymm2/m256/m64bcst

AVX10.1

ymm2/m256/m64bcst and stores the results in

ymm1. Under writemask.

EVEX.512.66.0F38.W1 4E /r

A

V/V

AVX512F

Computes the approximate reciprocal square roots of

VRSQRT14PD zmm1 {k1}{z},

OR AVX10.1

the packed double precision floating-point values in

zmm2/m512/m64bcst

zmm2/m512/m64bcst and stores the results in

zmm1 under writemask.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

Description

This instruction performs a SIMD computation of the approximate reciprocals of the square roots of the eight

packed double precision floating-point values in the source operand (the second operand) and stores the packed

double precision floating-point results in the destination operand (the first operand) according to the writemask.

The maximum relative error for this approximation is less than 2^-14.

EVEX.512 encoded version: The source operand can be a ZMM register, a 512-bit memory location, or a 512-bit

vector broadcasted from a 64-bit memory location. The destination operand is a ZMM register, conditionally

updated using writemask k1.

EVEX.256 encoded version: The source operand is a YMM register, a 256-bit memory location, or a 256-bit vector

broadcasted from a 64-bit memory location. The destination operand is a YMM register, conditionally updated using

writemask k1.

EVEX.128 encoded version: The source operand is a XMM register, a 128-bit memory location, or a 128-bit vector

broadcasted from a 64-bit memory location. The destination operand is a XMM register, conditionally updated using

writemask k1.

The VRSQRT14PD instruction is not affected by the rounding control bits in the MXCSR register. When a source

value is a 0.0, an ∞ with the sign of the source value is returned. When the source operand is an +∞ then +ZERO

value is returned. A denormal source value is treated as zero only if DAZ bit is set in MXCSR. Otherwise it is treated

correctly and performs the approximation with the specified masked response. When a source value is a negative

value (other than 0.0) a floating-point QNaN_indefinite is returned. When a source value is an SNaN or QNaN, the

SNaN is converted to a QNaN or the source QNaN is returned.

MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.

Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

A numerically exact implementation of VRSQRT14xx can be found at https://software.intel.com/en-us/arti-

cles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

VRSQRT14PD-Compute Approximate Reciprocals of Square Roots of Packed Float64 Values

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Operation

VRSQRT14PD (EVEX encoded versions)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) AND (SRC *is memory*)

THEN DEST[i+63:i] := APPROXIMATE(1.0/ SQRT(SRC[63:0]));

ELSE DEST[i+63:i] := APPROXIMATE(1.0/ SQRT(SRC[i+63:i]));

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] := 0

FI;

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

Table 5-32. VRSQRT14PD Special Cases

Input value

Result value

Comments

Any denormal

Normal

Cannot generate overflow

X = 2^-2n

2ⁿ

X < 0

QNaN_Indefinite

Including -INF

X = -0

-INF

X = +0

+INF

X = +INF

+0

Intel C/C++ Compiler Intrinsic Equivalent

VRSQRT14PD __m512d _mm512_rsqrt14_pd( __m512d a);

VRSQRT14PD __m512d _mm512_mask_rsqrt14_pd(__m512d s, __mmask8 k, __m512d a);

VRSQRT14PD __m512d _mm512_maskz_rsqrt14_pd( __mmask8 k, __m512d a);

VRSQRT14PD __m256d _mm256_rsqrt14_pd( __m256d a);

VRSQRT14PD __m256d _mm512_mask_rsqrt14_pd(__m256d s, __mmask8 k, __m256d a);

VRSQRT14PD __m256d _mm512_maskz_rsqrt14_pd( __mmask8 k, __m256d a);

VRSQRT14PD __m128d _mm_rsqrt14_pd( __m128d a);

VRSQRT14PD __m128d _mm_mask_rsqrt14_pd(__m128d s, __mmask8 k, __m128d a);

VRSQRT14PD __m128d _mm_maskz_rsqrt14_pd( __mmask8 k, __m128d a);

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-51, “Type E4 Class Exception Conditions.”

VRSQRT14PD-Compute Approximate Reciprocals of Square Roots of Packed Float64 Values

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VRSQRT14PS-Compute Approximate Reciprocals of Square Roots of Packed Float32 Values

Opcode/

Op /

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.128.66.0F38.W0 4E /r

A

V/V

(AVX512VL AND

Computes the approximate reciprocal square roots of

VRSQRT14PS xmm1 {k1}{z},

AVX512F) OR

the packed single-precision floating-point values in

xmm2/m128/m32bcst

AVX10.1

xmm2/m128/m32bcst and stores the results in xmm1.

Under writemask.

EVEX.256.66.0F38.W0 4E /r

A

V/V

(AVX512VL AND

Computes the approximate reciprocal square roots of

VRSQRT14PS ymm1 {k1}{z},

AVX512F) OR

the packed single-precision floating-point values in

ymm2/m256/m32bcst

AVX10.1

ymm2/m256/m32bcst and stores the results in ymm1.

Under writemask.

EVEX.512.66.0F38.W0 4E /r

A

V/V

AVX512F

Computes the approximate reciprocal square roots of

VRSQRT14PS zmm1 {k1}{z},

OR AVX10.1

the packed single-precision floating-point values in

zmm2/m512/m32bcst

zmm2/m512/m32bcst and stores the results in zmm1.

Under writemask.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

Description

This instruction performs a SIMD computation of the approximate reciprocals of the square roots of 16 packed

single precision floating-point values in the source operand (the second operand) and stores the packed single

precision floating-point results in the destination operand (the first operand) according to the writemask. The

maximum relative error for this approximation is less than 2^-14.

EVEX.512 encoded version: The source operand can be a ZMM register, a 512-bit memory location or a 512-bit

vector broadcasted from a 32-bit memory location. The destination operand is a ZMM register, conditionally

updated using writemask k1.

EVEX.256 encoded version: The source operand is a YMM register, a 256-bit memory location, or a 256-bit vector

broadcasted from a 32-bit memory location. The destination operand is a YMM register, conditionally updated using

writemask k1.

EVEX.128 encoded version: The source operand is a XMM register, a 128-bit memory location, or a 128-bit vector

broadcasted from a 32-bit memory location. The destination operand is a XMM register, conditionally updated using

writemask k1.

The VRSQRT14PS instruction is not affected by the rounding control bits in the MXCSR register. When a source

value is a 0.0, an ∞ with the sign of the source value is returned. When the source operand is an +∞ then +ZERO

value is returned. A denormal source value is treated as zero only if DAZ bit is set in MXCSR. Otherwise it is treated

correctly and performs the approximation with the specified masked response. When a source value is a negative

value (other than 0.0) a floating-point QNaN_indefinite is returned. When a source value is an SNaN or QNaN, the

SNaN is converted to a QNaN or the source QNaN is returned.

MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.

Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

A numerically exact implementation of VRSQRT14xx can be found at https://software.intel.com/en-us/arti-

cles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

VRSQRT14PS-Compute Approximate Reciprocals of Square Roots of Packed Float32 Values

Vol. 2C

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Operation

VRSQRT14PS (EVEX encoded versions)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) AND (SRC *is memory*)

THEN DEST[i+31:i] := APPROXIMATE(1.0/ SQRT(SRC[31:0]));

ELSE DEST[i+31:i] := APPROXIMATE(1.0/ SQRT(SRC[i+31:i]));

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

Table 5-33. VRSQRT14PS Special Cases

Input value

Result value

Comments

Any denormal

Normal

Cannot generate overflow

X = 2^-2n

2ⁿ

X < 0

QNaN_Indefinite

Including -INF

X = -0

-INF

X = +0

+INF

X = +INF

+0

Intel C/C++ Compiler Intrinsic Equivalent

VRSQRT14PS __m512 _mm512_rsqrt14_ps( __m512 a);

VRSQRT14PS __m512 _mm512_mask_rsqrt14_ps(__m512 s, __mmask16 k, __m512 a);

VRSQRT14PS __m512 _mm512_maskz_rsqrt14_ps( __mmask16 k, __m512 a);

VRSQRT14PS __m256 _mm256_rsqrt14_ps( __m256 a);

VRSQRT14PS __m256 _mm256_mask_rsqrt14_ps(__m256 s, __mmask8 k, __m256 a);

VRSQRT14PS __m256 _mm256_maskz_rsqrt14_ps( __mmask8 k, __m256 a);

VRSQRT14PS __m128 _mm_rsqrt14_ps( __m128 a);

VRSQRT14PS __m128 _mm_mask_rsqrt14_ps(__m128 s, __mmask8 k, __m128 a);

VRSQRT14PS __m128 _mm_maskz_rsqrt14_ps( __mmask8 k, __m128 a);

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-21, “Type 4 Class Exception Conditions.”

VRSQRT14PS-Compute Approximate Reciprocals of Square Roots of Packed Float32 Values

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VRSQRT14SD-Compute Approximate Reciprocal of Square Root of Scalar Float64 Value

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature Flag

Support

EVEX.LLIG.66.0F38.W1 4F /r

A

V/V

AVX512F

Computes the approximate reciprocal square root of the

VRSQRT14SD xmm1 {k1}{z},

OR AVX10.1

scalar double precision floating-point value in

xmm2, xmm3/m64

xmm3/m64 and stores the result in the low quadword

element of xmm1 using writemask k1. Bits[127:64] of

xmm2 is copied to xmm1[127:64].

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Computes the approximate reciprocal of the square roots of the scalar double precision floating-point value in the

low quadword element of the source operand (the second operand) and stores the result in the low quadword

element of the destination operand (the first operand) according to the writemask. The maximum relative error for

this approximation is less than 2^-14. The source operand can be an XMM register or a 32-bit memory location. The

destination operand is an XMM register.

Bits (127:64) of the XMM register destination are copied from corresponding bits in the first source operand. Bits

(MAXVL-1:128) of the destination register are zeroed.

The VRSQRT14SD instruction is not affected by the rounding control bits in the MXCSR register. When a source

value is a 0.0, an ∞ with the sign of the source value is returned. When the source operand is an +∞ then +ZERO

value is returned. A denormal source value is treated as zero only if DAZ bit is set in MXCSR. Otherwise it is treated

correctly and performs the approximation with the specified masked response. When a source value is a negative

value (other than 0.0) a floating-point QNaN_indefinite is returned. When a source value is an SNaN or QNaN, the

SNaN is converted to a QNaN or the source QNaN is returned.

MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.

A numerically exact implementation of VRSQRT14xx can be found at https://software.intel.com/en-us/arti-

cles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation

VRSQRT14SD (EVEX version)

IF k1[0] or *no writemask*

THEN

DEST[63:0] := APPROXIMATE(1.0/ SQRT(SRC2[63:0]))

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[63:0] remains unchanged*

ELSE

; zeroing-masking

THEN DEST[63:0] := 0

FI;

FI;

DEST[127:64] := SRC1[127:64]

DEST[MAXVL-1:128] := 0

VRSQRT14SD-Compute Approximate Reciprocal of Square Root of Scalar Float64 Value

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Table 5-34. VRSQRT14SD Special Cases

Input value

Result value

Comments

Any denormal

Normal

Cannot generate overflow

X = 2^-2n

2ⁿ

X < 0

QNaN_Indefinite

Including -INF

X = -0

-INF

X = +0

+INF

X = +INF

+0

Intel C/C++ Compiler Intrinsic Equivalent

VRSQRT14SD __m128d _mm_rsqrt14_sd( __m128d a, __m128d b);

VRSQRT14SD __m128d _mm_mask_rsqrt14_sd(__m128d s, __mmask8 k, __m128d a, __m128d b);

VRSQRT14SD __m128d _mm_maskz_rsqrt14_sd( __mmask8d m, __m128d a, __m128d b);

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-53, “Type E5 Class Exception Conditions.”

VRSQRT14SD-Compute Approximate Reciprocal of Square Root of Scalar Float64 Value

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VRSQRT14SS-Compute Approximate Reciprocal of Square Root of Scalar Float32 Value

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature Flag

Support

EVEX.LLIG.66.0F38.W0 4F /r

A

V/V

AVX512F

Computes the approximate reciprocal square root of the

VRSQRT14SS xmm1 {k1}{z},

OR AVX10.1

scalar single-precision floating-point value in xmm3/m32

xmm2, xmm3/m32

and stores the result in the low doubleword element of

xmm1 using writemask k1. Bits[127:32] of xmm2 is

copied to xmm1[127:32].

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Tuple1 Scalar

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Computes of the approximate reciprocal of the square root of the scalar single precision floating-point value in the

low doubleword element of the source operand (the second operand) and stores the result in the low doubleword

element of the destination operand (the first operand) according to the writemask. The maximum relative error for

this approximation is less than 2^-14. The source operand can be an XMM register or a 32-bit memory location. The

destination operand is an XMM register.

Bits (127:32) of the XMM register destination are copied from corresponding bits in the first source operand. Bits

(MAXVL-1:128) of the destination register are zeroed.

The VRSQRT14SS instruction is not affected by the rounding control bits in the MXCSR register. When a source

value is a 0.0, an ∞ with the sign of the source value is returned. When the source operand is an ∞, zero with the

sign of the source value is returned. A denormal source value is treated as zero only if DAZ bit is set in MXCSR.

Otherwise it is treated correctly and performs the approximation with the specified masked response. When a

source value is a negative value (other than 0.0) a floating-point indefinite is returned. When a source value is an

SNaN or QNaN, the SNaN is converted to a QNaN or the source QNaN is returned.

MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.

A numerically exact implementation of VRSQRT14xx can be found at https://software.intel.com/en-us/arti-

cles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation

VRSQRT14SS (EVEX version)

IF k1[0] or *no writemask*

THEN

DEST[31:0] := APPROXIMATE(1.0/ SQRT(SRC2[31:0]))

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[31:0] remains unchanged*

ELSE

; zeroing-masking

THEN DEST[31:0] := 0

FI;

FI;

DEST[127:32] := SRC1[127:32]

DEST[MAXVL-1:128] := 0

VRSQRT14SS-Compute Approximate Reciprocal of Square Root of Scalar Float32 Value

Vol. 2C

5-720

Table 5-35. VRSQRT14SS Special Cases

Input value

Result value

Comments

Any denormal

Normal

Cannot generate overflow

X = 2^-2n

2ⁿ

X < 0

QNaN_Indefinite

Including -INF

X = -0

-INF

X = +0

+INF

X = +INF

+0

Intel C/C++ Compiler Intrinsic Equivalent

VRSQRT14SS __m128 _mm_rsqrt14_ss( __m128 a, __m128 b);

VRSQRT14SS __m128 _mm_mask_rsqrt14_ss(__m128 s, __mmask8 k, __m128 a, __m128 b);

VRSQRT14SS __m128 _mm_maskz_rsqrt14_ss( __mmask8 k, __m128 a, __m128 b);

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-53, “Type E5 Class Exception Conditions.”

VRSQRT14SS-Compute Approximate Reciprocal of Square Root of Scalar Float32 Value

Vol. 2C

5-721

VRSQRTPH-Compute Reciprocals of Square Roots of Packed FP16 Values

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.128.66.MAP6.W0 4E /r

A

V/V

(AVX512_FP16

Compute the approximate reciprocals of the

VRSQRTPH xmm1{k1}{z},

AND AVX512VL)

square roots of packed FP16 values in

xmm2/m128/m16bcst

OR AVX10.1

xmm2/m128/m16bcst and store the result in

xmm1 subject to writemask k1.

EVEX.256.66.MAP6.W0 4E /r

A

V/V

(AVX512_FP16

Compute the approximate reciprocals of the

VRSQRTPH ymm1{k1}{z},

AND AVX512VL)

square roots of packed FP16 values in

ymm2/m256/m16bcst

OR AVX10.1

ymm2/m256/m16bcst and store the result in

ymm1 subject to writemask k1.

EVEX.512.66.MAP6.W0 4E /r

A

V/V

AVX512_FP16

Compute the approximate reciprocals of the

VRSQRTPH zmm1{k1}{z},

OR AVX10.1

square roots of packed FP16 values in

zmm2/m512/m16bcst

zmm2/m512/m16bcst and store the result in

zmm1 subject to writemask k1.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

Description

This instruction performs a SIMD computation of the approximate reciprocals square-root of 8/16/32 packed FP16

floating-point values in the source operand (the second operand) and stores the packed FP16 floating-point results

in the destination operand.

The maximum relative error for this approximation is less than 2^-11 + 2^-14. For special cases, see Table 5-36.

The destination elements are updated according to the writemask.

Table 5-36. VRSQRTPH/VRSQRTSH Special Cases

Input value

Reset Value

Comments

Any denormal

Normal

Cannot generate overflow

X = 2^-2n

2n

X < 0

QNaN_Indefinite

Including -∞

X = -0

-∞

X = +0

+∞

X = +∞

+0

VRSQRTPH-Compute Reciprocals of Square Roots of Packed FP16 Values

Vol. 2C

5-722

VRSQRTSH-Compute Approximate Reciprocal of Square Root of Scalar FP16 Value

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.LLIG.66.MAP6.W0 4F /r

A

V/V

AVX512_FP16

Compute the approximate reciprocal square root

VRSQRTSH xmm1{k1}{z}, xmm2,

OR AVX10.1

of the FP16 value in xmm3/m16 and store the

xmm3/m16

result in the low word element of xmm1 subject

to writemask k1. Bits 127:16 of xmm2 are

copied to xmm1[127:16].

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

A

Scalar

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

This instruction performs the computation of the approximate reciprocal square-root of the low FP16 value in the

second source operand (the third operand) and stores the result in the low word element of the destination operand

(the first operand) according to the writemask k1.

The maximum relative error for this approximation is less than 2^-11 + 2^-14.

Bits 127:16 of the destination operand are copied from the corresponding bits of the first source operand. Bits

MAXVL-1:128 of the destination operand are zeroed.

For special cases, see Table 5-36.

Operation

VRSQRTSH dest{k1}, src1, src2

VL = 128, 256 or 512

KL := VL/16

IF k1[0] or *no writemask*:

DEST.fp16[0] := APPROXIMATE(1.0 / SQRT(src2.fp16[0]))

ELSE IF *zeroing*:

DEST.fp16[0] := 0

//else DEST.fp16[0] remains unchanged

DEST[127:16] := src1[127:16]

DEST[MAXVL-1:128] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VRSQRTSH __m128h _mm_mask_rsqrt_sh (__m128h src, __mmask8 k, __m128h a, __m128h b);

VRSQRTSH __m128h _mm_maskz_rsqrt_sh (__mmask8 k, __m128h a, __m128h b);

VRSQRTSH __m128h _mm_rsqrt_sh (__m128h a, __m128h b);

SIMD Floating-Point Exceptions

None.

Other Exceptions

EVEX-encoded instruction, see Table 2-60, “Type E10 Class Exception Conditions.”

VRSQRTSH-Compute Approximate Reciprocal of Square Root of Scalar FP16 Value

Vol. 2C

5-724

VSCALEFPD-Scale Packed Float64 Values With Float64 Values

Opcode/

Op /

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.128.66.0F38.W1 2C /r

A

V/V

(AVX512VL

Scale the packed double precision floating-point

VSCALEFPD xmm1 {k1}{z}, xmm2,

AND AVX512F)

values in xmm2 using values from

xmm3/m128/m64bcst

OR AVX10.1

xmm3/m128/m64bcst. Under writemask k1.

EVEX.256.66.0F38.W1 2C /r

A

V/V

(AVX512VL

Scale the packed double precision floating-point

VSCALEFPD ymm1 {k1}{z}, ymm2,

AND AVX512F)

values in ymm2 using values from

ymm3/m256/m64bcst

OR AVX10.1

ymm3/m256/m64bcst. Under writemask k1.

EVEX.512.66.0F38.W1 2C /r

A

V/V

AVX512F

Scale the packed double precision floating-point

VSCALEFPD zmm1 {k1}{z}, zmm2,

OR AVX10.1

values in zmm2 using values from

zmm3/m512/m64bcst{er}

zmm3/m512/m64bcst. Under writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs a floating-point scale of the packed double precision floating-point values in the first source operand by

multiplying them by 2 to the power of the double precision floating-point values in second source operand.

The equation of this operation is given by:

zmm1 := zmm2*2^floor(zmm3).

Floor(zmm3) means maximum integer value ≤ zmm3.

If the result cannot be represented in double precision, then the proper overflow response (for positive scaling

operand), or the proper underflow response (for negative scaling operand) is issued. The overflow and underflow

responses are dependent on the rounding mode (for IEEE-compliant rounding), as well as on other settings in

MXCSR (exception mask bits, FTZ bit), and on the SAE bit.

The first source operand is a ZMM/YMM/XMM register. The second source operand is a ZMM/YMM/XMM register, a

512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The

destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.

Handling of special-case input values are listed in Table 5-37 and Table 5-38.

VSCALEFPD-Scale Packed Float64 Values With Float64 Values

Vol. 2C

5-725

Table 5-37. VSCALEFPD/SD/PS/SS Special Cases

Src2

Set IE

±NaN

+Inf

-Inf

0/Denorm/Norm

Src1

±QNaN

QNaN(Src1)

+INF

+0

QNaN(Src1)

IF either source is SNAN

±SNaN

QNaN(Src1)

QNaN(Src1)

QNaN(Src1)

QNaN(Src1)

YES

±Inf

QNaN(Src2)

Src1

QNaN_Indefinite

Src1

IF Src2 is SNAN or -INF

±0

QNaN(Src2)

QNaN_Indefinite

Src1

Src1

IF Src2 is SNAN or +INF

Denorm/Norm

QNaN(Src2)

±INF (Src1 sign)

±0 (Src1 sign)

Compute Result

IF Src2 is SNAN

Table 5-38. Additional VSCALEFPD/SD Special Cases

Special Case

Returned value

Faults

|result| < 2^-1074

±0 or ±Min-Denormal (Src1 sign)

Underflow

|result| ≥ 2¹⁰²⁴

±INF (Src1 sign) or ±Max-normal (Src1 sign)

Overflow

Operation

SCALE(SRC1, SRC2)

{

TMP_SRC2 := SRC2

TMP_SRC1 := SRC1

IF (SRC2 is denormal AND MXCSR.DAZ) THEN TMP_SRC2=0

IF (SRC1 is denormal AND MXCSR.DAZ) THEN TMP_SRC1=0

/* SRC2 is a 64 bits floating-point value */

DEST[63:0] := TMP_SRC1[63:0] * POW(2, Floor(TMP_SRC2[63:0]))

}

VSCALEFPD (EVEX encoded versions)

(KL, VL) = (2, 128), (4, 256), (8, 512)

IF (VL = 512) AND (EVEX.b = 1) AND (SRC2 *is register*)

THEN

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);

ELSE

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);

FI;

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) AND (SRC2 *is memory*)

THEN DEST[i+63:i] := SCALE(SRC1[i+63:i], SRC2[63:0]);

ELSE DEST[i+63:i] := SCALE(SRC1[i+63:i], SRC2[i+63:i]);

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] := 0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VSCALEFPD-Scale Packed Float64 Values With Float64 Values

Vol. 2C

5-726

VSCALEFPH-Scale Packed FP16 Values with FP16 Values

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.128.66.MAP6.W0 2C /r

A

V/V

(AVX512_FP16

Scale the packed FP16 values in xmm2 using

VSCALEFPH xmm1{k1}{z}, xmm2,

AND AVX512VL)

values from xmm3/m128/m16bcst, and store

xmm3/m128/m16bcst

OR AVX10.1

the result in xmm1 subject to writemask k1.

EVEX.256.66.MAP6.W0 2C /r

A

V/V

(AVX512_FP16

Scale the packed FP16 values in ymm2 using

VSCALEFPH ymm1{k1}{z}, ymm2,

AND AVX512VL)

values from ymm3/m256/m16bcst, and store the

ymm3/m256/m16bcst

OR AVX10.1

result in ymm1 subject to writemask k1.

EVEX.512.66.MAP6.W0 2C /r

A

V/V

AVX512_FP16

Scale the packed FP16 values in zmm2 using

VSCALEFPH zmm1{k1}{z}, zmm2,

OR AVX10.1

values from zmm3/m512/m16bcst, and store the

zmm3/m512/m16bcst {er}

result in zmm1 subject to writemask k1.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

This instruction performs a floating-point scale of the packed FP16 values in the first source operand by multiplying

it by 2 to the power of the FP16 values in second source operand. The destination elements are updated according

to the writemask.

The equation of this operation is given by:

zmm1 := zmm2 * 2^floor(zmm3).

Floor(zmm3) means maximum integer value ≤ zmm3.

If the result cannot be represented in FP16, then the proper overflow response (for positive scaling operand), or

the proper underflow response (for negative scaling operand), is issued. The overflow and underflow responses are

dependent on the rounding mode (for IEEE-compliant rounding), as well as on other settings in MXCSR (exception

mask bits), and on the SAE bit.

Handling of special-case input values are listed in Table 5-39 and Table 5-40.

Table 5-39. VSCALEFPH/VSCALEFSH Special Cases

Src2

Src1

Set IE

±NaN

+INF

-INF

0/Denorm/Norm

±QNaN

QNaN(Src1)

+INF

+0

QNaN(Src1)

IF either source is SNaN

±SNaN

QNaN(Src1)

QNaN(Src1)

QNaN(Src1)

QNaN(Src1)

YES

±INF

QNaN(Src2)

Src1

QNaN_Indefinite

Src1

IF Src2 is SNaN or -INF

±0

QNaN(Src2)

QNaN_Indefinite

Src1

Src1

IF Src2 is SNaN or +INF

Denorm/Norm

QNaN(Src2)

±INF (Src1 sign)

±0 (Src1 sign)

Compute Result

IF Src2 is SNaN

Table 5-40. Additional VSCALEFPH/VSCALEFSH Special Cases

Special Case

Returned Value

Faults

|result| < 2^-24

±0 or ±Min-Denormal (Src1 sign)

Underflow

|result| ≥ 2¹⁶

±INF (Src1 sign) or ±Max-Denormal (Src1 sign)

Overflow

VSCALEFPH-Scale Packed FP16 Values with FP16 Values

Vol. 2C

5-728

VSCALEFPS-Scale Packed Float32 Values With Float32 Values

Opcode/

Op /

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.128.66.0F38.W0 2C /r

A

V/V

(AVX512VL

Scale the packed single-precision floating-point

VSCALEFPS xmm1 {k1}{z}, xmm2,

AND AVX512F)

values in xmm2 using values from

xmm3/m128/m32bcst

OR AVX10.1

xmm3/m128/m32bcst. Under writemask k1.

EVEX.256.66.0F38.W0 2C /r

A

V/V

(AVX512VL

Scale the packed single-precision values in ymm2

VSCALEFPS ymm1 {k1}{z}, ymm2,

AND AVX512F)

using floating-point values from

ymm3/m256/m32bcst

OR AVX10.1

ymm3/m256/m32bcst. Under writemask k1.

EVEX.512.66.0F38.W0 2C /r

A

V/V

AVX512F

Scale the packed single-precision floating-point

VSCALEFPS zmm1 {k1}{z}, zmm2,

OR AVX10.1

values in zmm2 using floating-point values from

zmm3/m512/m32bcst{er}

zmm3/m512/m32bcst. Under writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs a floating-point scale of the packed single precision floating-point values in the first source operand by

multiplying them by 2 to the power of the float32 values in second source operand.

The equation of this operation is given by:

zmm1 := zmm2*2^floor(zmm3).

Floor(zmm3) means maximum integer value ≤ zmm3.

If the result cannot be represented in single precision, then the proper overflow response (for positive scaling

operand), or the proper underflow response (for negative scaling operand) is issued. The overflow and underflow

responses are dependent on the rounding mode (for IEEE-compliant rounding), as well as on other settings in

MXCSR (exception mask bits, FTZ bit), and on the SAE bit.

EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM

register, a 512-bit memory location or a 512-bit vector broadcasted from a 32-bit memory location. The destina-

tion operand is a ZMM register conditionally updated with writemask k1.

EVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM

register, a 256-bit memory location, or a 256-bit vector broadcasted from a 32-bit memory location. The destina-

tion operand is a YMM register, conditionally updated using writemask k1.

EVEX.128 encoded version: The first source operand is an XMM register. The second source operand is a XMM

register, a 128-bit memory location, or a 128-bit vector broadcasted from a 32-bit memory location. The destina-

tion operand is a XMM register, conditionally updated using writemask k1.

Handling of special-case input values are listed in Table 5-37 and Table 5-41.

Table 5-41. Additional VSCALEFPS/SS Special Cases

Special Case

Returned value

Faults

|result| < 2^-149

±0 or ±Min-Denormal (Src1 sign)

Underflow

|result| ≥ 2¹²⁸

±INF (Src1 sign) or ±Max-normal (Src1 sign)

Overflow

VSCALEFPS-Scale Packed Float32 Values With Float32 Values

Vol. 2C

5-731

VSCALEFSD-Scale Scalar Float64 Values With Float64 Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature Flag

Support

EVEX.LLIG.66.0F38.W1 2D /r

A

V/V

AVX512F

Scale the scalar double precision floating-point values

VSCALEFSD xmm1 {k1}{z}, xmm2,

OR AVX10.1

in xmm2 using the value from xmm3/m64. Under

xmm3/m64{er}

writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs a floating-point scale of the scalar double precision floating-point value in the first source operand by

multiplying it by 2 to the power of the double precision floating-point value in second source operand.

The equation of this operation is given by:

xmm1 := xmm2*2^floor(xmm3).

Floor(xmm3) means maximum integer value ≤ xmm3.

If the result cannot be represented in double precision, then the proper overflow response (for positive scaling

operand), or the proper underflow response (for negative scaling operand) is issued. The overflow and underflow

responses are dependent on the rounding mode (for IEEE-compliant rounding), as well as on other settings in

MXCSR (exception mask bits, FTZ bit), and on the SAE bit.

EVEX encoded version: The first source operand is an XMM register. The second source operand is an XMM register

or a memory location. The destination operand is an XMM register conditionally updated with writemask k1.

Handling of special-case input values are listed in Table 5-37 and Table 5-38.

Operation

SCALE(SRC1, SRC2)

{

; Check for denormal operands

TMP_SRC2 := SRC2

TMP_SRC1 := SRC1

IF (SRC2 is denormal AND MXCSR.DAZ) THEN TMP_SRC2=0

IF (SRC1 is denormal AND MXCSR.DAZ) THEN TMP_SRC1=0

/* SRC2 is a 64 bits floating-point value */

DEST[63:0] := TMP_SRC1[63:0] * POW(2, Floor(TMP_SRC2[63:0]))

}

VSCALEFSD-Scale Scalar Float64 Values With Float64 Values

Vol. 2C

5-734

VSCALEFSH-Scale Scalar FP16 Values with FP16 Values

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.LLIG.66.MAP6.W0 2D /r

A

V/V

AVX512_FP16

Scale the FP16 values in xmm2 using the value

VSCALEFSH xmm1{k1}{z}, xmm2,

OR AVX10.1

from xmm3/m16 and store the result in xmm1

xmm3/m16 {er}

subject to writemask k1. Bits 127:16 from xmm2

are copied to xmm1[127:16].

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

A

Scalar

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

This instruction performs a floating-point scale of the low FP16 element in the first source operand by multiplying it

by 2 to the power of the low FP16 element in second source operand, storing the result in the low element of the

destination operand.

Bits 127:16 of the destination operand are copied from the corresponding bits of the first source operand. Bits

MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the destination is updated according

to the writemask.

The equation of this operation is given by:

xmm1 := xmm2 * 2^floor(xmm3).

Floor(xmm3) means maximum integer value ≤ xmm3.

If the result cannot be represented in FP16, then the proper overflow response (for positive scaling operand), or

the proper underflow response (for negative scaling operand), is issued. The overflow and underflow responses are

dependent on the rounding mode (for IEEE-compliant rounding), as well as on other settings in MXCSR (exception

mask bits, FTZ bit), and on the SAE bit.

Handling of special-case input values are listed in Table 5-39 and Table 5-40.

Operation

VSCALEFSH dest{k1}, src1, src2

IF (EVEX.b = 1) and no memory operand:

SET_RM(EVEX.RC)

ELSE

SET_RM(MXCSR.RC)

IF k1[0] or *no writemask*:

dest.fp16[0] := scale_fp16(src1.fp16[0], src2.fp16[0]) // see VSCALEFPH

ELSE IF *zeroing*:

dest.fp16[0] := 0

//else DEST.fp16[0] remains unchanged

DEST[127:16] := src1[127:16]

DEST[MAXVL-1:128] := 0

VSCALEFSH-Scale Scalar FP16 Values with FP16 Values

Vol. 2C

5-736

VSCALEFSS-Scale Scalar Float32 Value With Float32 Value

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature Flag

Support

EVEX.LLIG.66.0F38.W0 2D /r

A

V/V

AVX512F

Scale the scalar single-precision floating-point value in

VSCALEFSS xmm1 {k1}{z}, xmm2,

OR AVX10.1

xmm2 using floating-point value from xmm3/m32. Under

xmm3/m32{er}

writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs a floating-point scale of the scalar single precision floating-point value in the first source operand by

multiplying it by 2 to the power of the float32 value in second source operand.

The equation of this operation is given by:

xmm1 := xmm2*2^floor(xmm3).

Floor(xmm3) means maximum integer value ≤ xmm3.

If the result cannot be represented in single precision, then the proper overflow response (for positive scaling

operand), or the proper underflow response (for negative scaling operand) is issued. The overflow and underflow

responses are dependent on the rounding mode (for IEEE-compliant rounding), as well as on other settings in

MXCSR (exception mask bits, FTZ bit), and on the SAE bit.

EVEX encoded version: The first source operand is an XMM register. The second source operand is an XMM register

or a memory location. The destination operand is an XMM register conditionally updated with writemask k1.

Handling of special-case input values are listed in Table 5-37 and Table 5-41.

Operation

SCALE(SRC1, SRC2)

{

; Check for denormal operands

TMP_SRC2 := SRC2

TMP_SRC1 := SRC1

IF (SRC2 is denormal AND MXCSR.DAZ) THEN TMP_SRC2=0

IF (SRC1 is denormal AND MXCSR.DAZ) THEN TMP_SRC1=0

/* SRC2 is a 32 bits floating-point value */

DEST[31:0] := TMP_SRC1[31:0] * POW(2, Floor(TMP_SRC2[31:0]))

}

VSCALEFSS-Scale Scalar Float32 Value With Float32 Value

Vol. 2C

5-738

VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD-Scatter Packed Single Precision,

Packed Double Precision Floating-Point Values with Signed Dword and Qword Indices

Opcode/

Op/E

64/32

CPUID Feature

Description

Instruction

n

bit Mode

Flag

Support

EVEX.128.66.0F38.W0 A2 /vsib

A

V/V

(AVX512VL AND

Using signed dword indices, scatter single-

VSCATTERDPS vm32x {k1}, xmm1

AVX512F) OR

precision floating-point values to memory using

AVX10.1

writemask k1.

EVEX.256.66.0F38.W0 A2 /vsib

A

V/V

(AVX512VL AND

Using signed dword indices, scatter single-

VSCATTERDPS vm32y {k1}, ymm1

AVX512F) OR

precision floating-point values to memory using

AVX10.1

writemask k1.

EVEX.512.66.0F38.W0 A2 /vsib

A

V/V

AVX512F

Using signed dword indices, scatter single-

VSCATTERDPS vm32z {k1}, zmm1

OR AVX10.1

precision floating-point values to memory using

writemask k1.

EVEX.128.66.0F38.W1 A2 /vsib

A

V/V

(AVX512VL AND

Using signed dword indices, scatter double

VSCATTERDPD vm32x {k1}, xmm1

AVX512F) OR

precision floating-point values to memory using

AVX10.1

writemask k1.

EVEX.256.66.0F38.W1 A2 /vsib

A

V/V

(AVX512VL AND

Using signed dword indices, scatter double

VSCATTERDPD vm32y {k1}, ymm1

AVX512F) OR

precision floating-point values to memory using

AVX10.1

writemask k1.

EVEX.512.66.0F38.W1 A2 /vsib

A

V/V

AVX512F

Using signed dword indices, scatter double

VSCATTERDPD vm32z {k1}, zmm1

OR AVX10.1

precision floating-point values to memory using

writemask k1.

EVEX.128.66.0F38.W0 A3 /vsib

A

V/V

(AVX512VL AND

Using signed qword indices, scatter single-

VSCATTERQPS vm64x {k1}, xmm1

AVX512F) OR

precision floating-point values to memory using

AVX10.1

writemask k1.

EVEX.256.66.0F38.W0 A3 /vsib

A

V/V

(AVX512VL AND

Using signed qword indices, scatter single-

VSCATTERQPS vm64y {k1}, xmm1

AVX512F) OR

precision floating-point values to memory using

AVX10.1

writemask k1.

EVEX.512.66.0F38.W0 A3 /vsib

A

V/V

AVX512F

Using signed qword indices, scatter single-

VSCATTERQPS vm64z {k1}, ymm1

OR AVX10.1

precision floating-point values to memory using

writemask k1.

EVEX.128.66.0F38.W1 A3 /vsib

A

V/V

(AVX512VL AND

Using signed qword indices, scatter double

VSCATTERQPD vm64x {k1}, xmm1

AVX512F) OR

precision floating-point values to memory using

AVX10.1

writemask k1.

EVEX.256.66.0F38.W1 A3 /vsib

A

V/V

(AVX512VL AND

Using signed qword indices, scatter double

VSCATTERQPD vm64y {k1}, ymm1

AVX512F) OR

precision floating-point values to memory using

AVX10.1

writemask k1.

EVEX.512.66.0F38.W1 A3 /vsib

A

V/V

AVX512F

Using signed qword indices, scatter double

VSCATTERQPD vm64z {k1}, zmm1

OR AVX10.1

precision floating-point values to memory using

writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

BaseReg (R): VSIB:base,

A

Tuple1 Scalar

ModRM:reg (r)

N/A

N/A

VectorReg(R): VSIB:index

VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD-Scatter Packed Single Precision, Packed Double Precision Floating-

Vol. 2C

5-740

VSHA512MSG1-Perform an Intermediate Calculation for the Next Four SHA512 Message

Qwords

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

VEX.256.F2.0F38.W0 CC 11:rrr:bbb

A

V/V

AVX

Performs an intermediate calculation for the

next four SHA512 message qwords using

VSHA512MSG1 ymm1, xmm2

SHA512

previous message qwords from ymm1 and

xmm2, storing the result in ymm1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

N/A

Description

The VSHA512MSG1 instruction is one of the two SHA512 message scheduling instructions. The instruction

performs an intermediate calculation for the next four SHA512 message qwords.

See https://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.180-4.pdf for more information on the SHA512 standard.

Operation

define ROR64(qword, n):

count := n % 64

dest := (qword >> count) | (qword << (64-count))

return dest

define SHR64(qword, n):

return qword >> n

define s0(qword):

return ROR64(qword,1) ^ ROR64(qword, 8) ^ SHR64(qword, 7)

VSHA512MSG1 SRCDEST, SRC1

W[4] := SRC1.qword[0]

W[3] := SRCDEST.qword[3]

W[2] := SRCDEST.qword[2]

W[1] := SRCDEST.qword[1]

W[0] := SRCDEST.qword[0]

SRCDEST.qword[3] := W[3] + s0(W[4])

SRCDEST.qword[2] := W[2] + s0(W[3])

SRCDEST.qword[1] := W[1] + s0(W[2])

SRCDEST.qword[0] := W[0] + s0(W[1])

Flags Affected

None.

Intel C/C++ Compiler Intrinsic Equivalent

VSHA512MSG1 __m256i _mm256_sha512msg1_epi64 (__m256i __A, __m128i __B);

SIMD Floating-Point Exceptions

None.

VSHA512MSG1-Perform an Intermediate Calculation for the Next Four SHA512 Message Qwords

Vol. 2C

5-744

VSHA512MSG2-Perform a Final Calculation for the Next Four SHA512 Message Qwords

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

VEX.256.F2.0F38.W0 CD 11:rrr:bbb

A

V/V

AVX

Performs the final calculation for the next four

SHA512 message qwords using previous

VSHA512MSG2 ymm1, ymm2

SHA512

message qwords from ymm1 and ymm2,

storing the result in ymm1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

N/A

Description

The VSHA512MSG2 instruction is one of the two SHA512 message scheduling instructions. The instruction

performs the final calculation for the next four SHA512 message qwords.

See https://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.180-4.pdf for more information on the SHA512 standard.

Operation

define ROR64(qword, n):

count := n % 64

dest := (qword >> count) | (qword << (64-count))

return dest

define SHR64(qword, n):

return qword >> n

define s1(qword):

return ROR64(qword,19) ^ ROR64(qword, 61) ^ SHR64(qword, 6)

VSHA512MSG2 SRCDEST, SRC1

W[14] := SRC1.qword[2]

W[15] := SRC1.qword[3]

W[16] := SRCDEST.qword[0] + s1(W[14])

W[17] := SRCDEST.qword[1] + s1(W[15])

W[18] := SRCDEST.qword[2] + s1(W[16])

W[19] := SRCDEST.qword[3] + s1(W[17])

SRCDEST.qword[3] := W[19]

SRCDEST.qword[2] := W[18]

SRCDEST.qword[1] := W[17]

SRCDEST.qword[0] := W[16]

Flags Affected

None.

Intel C/C++ Compiler Intrinsic Equivalent

VSHA512MSG2 __m256i _mm256_sha512msg2_epi64 (__m256i __A, __m256i __B);

SIMD Floating-Point Exceptions

None.

VSHA512MSG2-Perform a Final Calculation for the Next Four SHA512 Message Qwords

Vol. 2C

5-746

VSHA512RNDS2-Perform Two Rounds of SHA512 Operation

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

VEX.256.F2.0F38.W0 CB 11:rrr:bbb

A

V/V

AVX

Perform 2 rounds of SHA512 operation using

an initial SHA512 state (C,D,G,H) from ymm1,

VSHA512RNDS2 ymm1, ymm2,

SHA512

an initial SHA512 state (A,B,E,F) from ymm2,

xmm3

and a pre-computed sum of the next 2 round

message qwords and the corresponding round

constants from xmm3, storing the updated

SHA512 state (A,B,E,F) result in ymm1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (r, w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

The VSHA512RNDS2 instruction performs two rounds of SHA512 operation using initial SHA512 state (C,D,G,H)

from the first operand, an initial SHA512 state (A,B,E,F) from the second operand, and a pre-computed sum of the

next two round message qwords and the corresponding round constants from the third operand (only the two

lower qwords of the third operand). The updated SHA512 state (A,B,E,F) is written to the first operand, and the

second operand can be used as the updated state (C,D,G,H) in later rounds.

See https://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.180-4.pdf for more information on the SHA512 standard.

Operation

define ROR64(qword, n):

count := n % 64

dest := (qword >> count) | (qword << (64-count))

return dest

define SHR64(qword, n):

return qword >> n

define cap_sigma0(qword):

return ROR64(qword,28) ^ ROR64(qword, 34) ^ ROR64(qword, 39)

define cap_sigma1(qword):

return ROR64(qword,14) ^ ROR64(qword, 18) ^ ROR64(qword, 41)

define MAJ(a,b,c):

return (a & b) ^ (a & c) ^ (b & c)

define CH(e,f,g):

return (e & f) ^ (g & ~e)

VSHA512RNDS2-Perform Two Rounds of SHA512 Operation

Vol. 2C

5-748

VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2-Shuffle Packed Values at 128-Bit

Granularity

Opcode/

Op /

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.256.66.0F3A.W0 23 /r ib

A

V/V

(AVX512VL AND

Shuffle 128-bit packed single-precision floating-

VSHUFF32X4 ymm1{k1}{z}, ymm2,

AVX512F) OR

point values selected by imm8 from ymm2 and

ymm3/m256/m32bcst, imm8

AVX10.1

ymm3/m256/m32bcst and place results in ymm1

subject to writemask k1.

EVEX.512.66.0F3A.W0 23 /r ib

A

V/V

AVX512F

Shuffle 128-bit packed single-precision floating-

VSHUFF32x4 zmm1{k1}{z}, zmm2,

OR AVX10.1

point values selected by imm8 from zmm2 and

zmm3/m512/m32bcst, imm8

zmm3/m512/m32bcst and place results in zmm1

subject to writemask k1.

EVEX.256.66.0F3A.W1 23 /r ib

A

V/V

(AVX512VL AND

Shuffle 128-bit packed double precision floating-

VSHUFF64X2 ymm1{k1}{z}, ymm2,

AVX512F) OR

point values selected by imm8 from ymm2 and

ymm3/m256/m64bcst, imm8

AVX10.1

ymm3/m256/m64bcst and place results in ymm1

subject to writemask k1.

EVEX.512.66.0F3A.W1 23 /r ib

A

V/V

AVX512F

Shuffle 128-bit packed double precision floating-

VSHUFF64x2 zmm1{k1}{z}, zmm2,

OR AVX10.1

point values selected by imm8 from zmm2 and

zmm3/m512/m64bcst, imm8

zmm3/m512/m64bcst and place results in zmm1

subject to writemask k1.

EVEX.256.66.0F3A.W0 43 /r ib

A

V/V

(AVX512VL AND

Shuffle 128-bit packed double-word values

VSHUFI32X4 ymm1{k1}{z}, ymm2,

AVX512F) OR

selected by imm8 from ymm2 and

ymm3/m256/m32bcst, imm8

AVX10.1

ymm3/m256/m32bcst and place results in ymm1

subject to writemask k1.

EVEX.512.66.0F3A.W0 43 /r ib

A

V/V

AVX512F

Shuffle 128-bit packed double-word values

VSHUFI32x4 zmm1{k1}{z}, zmm2,

OR AVX10.1

selected by imm8 from zmm2 and

zmm3/m512/m32bcst, imm8

zmm3/m512/m32bcst and place results in zmm1

subject to writemask k1.

EVEX.256.66.0F3A.W1 43 /r ib

A

V/V

(AVX512VL AND

Shuffle 128-bit packed quad-word values selected

VSHUFI64X2 ymm1{k1}{z}, ymm2,

AVX512F) OR

by imm8 from ymm2 and ymm3/m256/m64bcst

ymm3/m256/m64bcst, imm8

AVX10.1

and place results in ymm1 subject to writemask k1.

EVEX.512.66.0F3A.W1 43 /r ib

A

V/V

AVX512F

Shuffle 128-bit packed quad-word values selected

VSHUFI64x2 zmm1{k1}{z}, zmm2,

OR AVX10.1

by imm8 from zmm2 and zmm3/m512/m64bcst

zmm3/m512/m64bcst, imm8

and place results in zmm1 subject to writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

256-bit Version: Moves one of the two 128-bit packed single precision floating-point values from the first source

operand (second operand) into the low 128-bit of the destination operand (first operand); moves one of the two

packed 128-bit floating-point values from the second source operand (third operand) into the high 128-bit of the

destination operand. The selector operand (third operand) determines which values are moved to the destination

operand.

512-bit Version: Moves two of the four 128-bit packed single precision floating-point values from the first source

operand (second operand) into the low 256-bit of each double qword of the destination operand (first operand);

moves two of the four packed 128-bit floating-point values from the second source operand (third operand) into

the high 256-bit of the destination operand. The selector operand (third operand) determines which values are

moved to the destination operand.

VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2-Shuffle Packed Values at 128-Bit Granularity

Vol. 2C

5-750

VSM3MSG1-Perform Initial Calculation for the Next Four SM3 Message Words

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

VEX.128.NP.0F38.W0 DA /r

A

V/V

AVX

Performs an initial calculation for the next four

SM3 message words using previous message

VSM3MSG1 xmm1, xmm2,

SM3

words from xmm2 and xmm3/m128, storing

xmm3/m128

the result in xmm1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (r, w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

The VSM3MSG1 instruction is one of the two SM3 message scheduling instructions. The instruction performs an

initial calculation for the next four SM3 message words.

Operation

define ROL32(dword, n):

count := n % 32

dest := (dword << count) | (dword >> (32-count))

return dest

define P1(x):

return x ^ ROL32(x, 15) ^ ROL32(x, 23)

VSM3MSG1 SRCDEST, SRC1, SRC2

W[0] := SRC2.dword[0]

W[1] := SRC2.dword[1]

W[2] := SRC2.dword[2]

W[3] := SRC2.dword[3]

W[7] := SRCDEST.dword[0]

W[8] := SRCDEST.dword[1]

W[9] := SRCDEST.dword[2]

W[10] := SRCDEST.dword[3]

W[13] := SRC1.dword[0]

W[14] := SRC1.dword[1]

W[15] := SRC1.dword[2]

TMP0 := W[7] ^ W[0] ^ ROL32(W[13], 15)

TMP1 := W[8] ^ W[1] ^ ROL32(W[14], 15)

TMP2 := W[9] ^ W[2] ^ ROL32(W[15], 15)

TMP3 := W[10] ^ W[3]

SRCDEST.dword[0] := P1(TMP0)

SRCDEST.dword[1] := P1(TMP1)

SRCDEST.dword[2] := P1(TMP2)

SRCDEST.dword[3] := P1(TMP3)

VSM3MSG1-Perform Initial Calculation for the Next Four SM3 Message Words

Vol. 2C

5-755

VSM3MSG2-Perform Final Calculation for the Next Four SM3 Message Words

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

VEX.128.66.0F38.W0 DA /r

A

V/V

AVX

Performs the final calculation for the next four

SM3 message words using previous message

VSM3MSG2 xmm1, xmm2,

SM3

words from xmm2 and xmm3/m128, storing

xmm3/m128

the result in xmm1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (r, w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

The VSM3MSG2 instruction is one of the two SM3 message scheduling instructions. The instruction performs the

final calculation for the next four SM3 message words.

Operation

//see the VSM3MSG1 instruction for definition of ROL32()

VSM3MSG2 SRCDEST, SRC1, SRC2

WTMP[0] := SRCDEST.dword[0]

WTMP[1] := SRCDEST.dword[1]

WTMP[2] := SRCDEST.dword[2]

WTMP[3] := SRCDEST.dword[3]

// Dword array W[] has indices are based on the SM3 specification.

W[3] := SRC1.dword[0]

W[4] := SRC1.dword[1]

W[5] := SRC1.dword[2]

W[6] := SRC1.dword[3]

W[10] := SRC2.dword[0]

W[11] := SRC2.dword[1]

W[12] := SRC2.dword[2]

W[13] := SRC2.dword[3]

W[16] := ROL32(W[3], 7) ^ W[10] ^ WTMP[0]

W[17] := ROL32(W[4], 7) ^ W[11] ^ WTMP[1]

W[18] := ROL32(W[5], 7) ^ W[12] ^ WTMP[2]

W[19] := ROL32(W[6], 7) ^ W[13] ^ WTMP[3]

W[19] := W[19] ^ ROL32(W[16], 6) ^ ROL32(W[16], 15) ^ ROL32(W[16], 30)

SRCDEST.dword[0] := W[16]

SRCDEST.dword[1] := W[17]

SRCDEST.dword[2] := W[18]

SRCDEST.dword[3] := W[19]

Flags Affected

None.

VSM3MSG2-Perform Final Calculation for the Next Four SM3 Message Words

Vol. 2C

5-757

VSM3RNDS2-Perform Two Rounds of SM3 Operation

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

VEX.128.66.0F3A.W0 DE /r /ib

A

V/V

AVX

Performs two rounds of SM3 operation using

the initial SM3 states from xmm1 and xmm2,

VSM3RNDS2 xmm1, xmm2,

SM3

and pre-computed words from xmm3/m128,

xmm3/m128, imm8

storing the result in xmm1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (r, w)

VEX.vvvv (r)

ModRM:r/m (r)

imm8

Description

The VSM3RNDS2 instruction performs two rounds of SM3 operation using initial SM3 state (C, D, G, H) from the

first operand, an initial SM3 states (A, B, E, F) from the second operand and a pre-computed words from the third

operand. The first operand with initial SM3 state of (C, D, G, H) assumes input of non-rotated left variables from

previous state. The updated SM3 state (A, B, E, F) is written to the first operand.

The imm8 should contain the even round number for the first of the two rounds computed by this instruction. The

computation masks the imm8 value by AND’ing it with 0x3E so that only even round numbers from 0 through 62

are used for this operation.

Operation

//see the VSM3MSG1 instruction for definition of ROL32()

define P0(dword):

return dword ^ ROL32(dword, 9) ^ ROL32(dword, 17)

define FF(x,y,z, round):

if round < 16:

return (x ^ y ^ z)

else:

return (x & y) | (x & z) | (y & z)

define GG(x,y,z, round):

if round < 16:

return (x ^ y ^ z)

else:

return (x & y) | (~x & z)

VSM3RNDS2 SRCDEST, SRC1, SRC2, IMM8

A[0] := SRC1.dword[3]

B[0] := SRC1.dword[2]

C[0] := SRCDEST.dword[3]

D[0] := SRCDEST.dword[2]

E[0] := SRC1.dword[1]

F[0] := SRC1.dword[0]

G[0] := SRCDEST.dword[1]

H[0] := SRCDEST.dword[0]

W[0] := SRC2.dword[0]

W[1] := SRC2.dword[1]

W[4] := SRC2.dword[2]

VSM3RNDS2-Perform Two Rounds of SM3 Operation

Vol. 2C

5-759

VSM4KEY4-Perform Four Rounds of SM4 Key Expansion

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

VEX.128.F3.0F38.W0 DA /r

A

V/V

AVX

Performs four rounds of SM4 key expansion.

VSM4KEY4 xmm1, xmm2,

SM4

xmm3/m128

VEX.256.F3.0F38.W0 DA /r

A

V/V

AVX

Performs four rounds of SM4 key expansion.

VSM4KEY4 ymm1, ymm2,

SM4

ymm3/m256

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

The VSM4KEY4 instruction performs four rounds of SM4 key expansion. The instruction operates on independent

128-bit lanes.

Additional details can be found at: https://tools.ietf.org/html/draft-ribose-cfrg-sm4-10.

Both SM4 instructions use a common sbox table:

BYTE sbox[256] = {

0xD6, 0x90, 0xE9, 0xFE, 0xCC, 0xE1, 0x3D, 0xB7, 0x16, 0xB6, 0x14, 0xC2, 0x28, 0xFB, 0x2C, 0x05,

0x2B, 0x67, 0x9A, 0x76, 0x2A, 0xBE, 0x04, 0xC3, 0xAA, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,

0x9C, 0x42, 0x50, 0xF4, 0x91, 0xEF, 0x98, 0x7A, 0x33, 0x54, 0x0B, 0x43, 0xED, 0xCF, 0xAC, 0x62,

0xE4, 0xB3, 0x1C, 0xA9, 0xC9, 0x08, 0xE8, 0x95, 0x80, 0xDF, 0x94, 0xFA, 0x75, 0x8F, 0x3F, 0xA6,

0x47, 0x07, 0xA7, 0xFC, 0xF3, 0x73, 0x17, 0xBA, 0x83, 0x59, 0x3C, 0x19, 0xE6, 0x85, 0x4F, 0xA8,

0x68, 0x6B, 0x81, 0xB2, 0x71, 0x64, 0xDA, 0x8B, 0xF8, 0xEB, 0x0F, 0x4B, 0x70, 0x56, 0x9D, 0x35,

0x1E, 0x24, 0x0E, 0x5E, 0x63, 0x58, 0xD1, 0xA2, 0x25, 0x22, 0x7C, 0x3B, 0x01, 0x21, 0x78, 0x87,

0xD4, 0x00, 0x46, 0x57, 0x9F, 0xD3, 0x27, 0x52, 0x4C, 0x36, 0x02, 0xE7, 0xA0, 0xC4, 0xC8, 0x9E,

0xEA, 0xBF, 0x8A, 0xD2, 0x40, 0xC7, 0x38, 0xB5, 0xA3, 0xF7, 0xF2, 0xCE, 0xF9, 0x61, 0x15, 0xA1,

0xE0, 0xAE, 0x5D, 0xA4, 0x9B, 0x34, 0x1A, 0x55, 0xAD, 0x93, 0x32, 0x30, 0xF5, 0x8C, 0xB1, 0xE3,

0x1D, 0xF6, 0xE2, 0x2E, 0x82, 0x66, 0xCA, 0x60, 0xC0, 0x29, 0x23, 0xAB, 0x0D, 0x53, 0x4E, 0x6F,

0xD5, 0xDB, 0x37, 0x45, 0xDE, 0xFD, 0x8E, 0x2F, 0x03, 0xFF, 0x6A, 0x72, 0x6D, 0x6C, 0x5B, 0x51,

0x8D, 0x1B, 0xAF, 0x92, 0xBB, 0xDD, 0xBC, 0x7F, 0x11, 0xD9, 0x5C, 0x41, 0x1F, 0x10, 0x5A, 0xD8,

0x0A, 0xC1, 0x31, 0x88, 0xA5, 0xCD, 0x7B, 0xBD, 0x2D, 0x74, 0xD0, 0x12, 0xB8, 0xE5, 0xB4, 0xB0,

0x89, 0x69, 0x97, 0x4A, 0x0C, 0x96, 0x77, 0x7E, 0x65, 0xB9, 0xF1, 0x09, 0xC5, 0x6E, 0xC6, 0x84,

0x18, 0xF0, 0x7D, 0xEC, 0x3A, 0xDC, 0x4D, 0x20, 0x79, 0xEE, 0x5F, 0x3E, 0xD7, 0xCB, 0x39, 0x48

}

Operation

define ROL32(dword, n):

count := n % 32

dest := (dword << count) | (dword >> (32-count))

return dest

define SBOX_BYTE(dword, i):

// sbox[] array defined in introduction

return sbox[dword.byte[i]]

define lower_t(dword):

tmp.byte[0] := SBOX_BYTE(dword, 0)

VSM4KEY4-Perform Four Rounds of SM4 Key Expansion

Vol. 2C

5-761

VSM4RNDS4-Performs Four Rounds of SM4 Encryption

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

VEX.128.F2.0F38.W0 DA /r

A

V/V

AVX

Performs four rounds of SM4 encryption.

VSM4RNDS4 xmm1, xmm2,

SM4

xmm3/m128

VEX.256.F2.0F38.W0 DA /r

A

V/V

AVX

Performs four rounds of SM4 encryption.

VSM4RNDS4 ymm1, ymm2,

SM4

ymm3/m256

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

The SM4RNDS4 instruction performs four rounds of SM4 encryption. The instruction operates on independent 128-

bit lanes.

Additional details can be found at: https://tools.ietf.org/html/draft-ribose-cfrg-sm4-10.

See “VSM4KEY4-Perform Four Rounds of SM4 Key Expansion” for the sbox table.

Operation

// see the VSM4KEY4 instruction for the definition of ROL32, lower_t

define L_RND(dword):

tmp := dword

tmp := tmp ^ ROL32(dword, 2)

tmp := tmp ^ ROL32(dword, 10)

tmp := tmp ^ ROL32(dword, 18)

tmp := tmp ^ ROL32(dword, 24)

return tmp

define T_RND(dword):

return L_RND(lower_t(dword))

define F_RND(X0, X1, X2, X3, round_key):

return X0 ^ T_RND(X1 ^ X2 ^ X3 ^ round_key)

VSM4RNDS4-Performs Four Rounds of SM4 Encryption

Vol. 2C

5-763

VSQRTPH-Compute Square Root of Packed FP16 Values

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.128.NP.MAP5.W0 51 /r

A

V/V

(AVX512_FP16

Compute square roots of the packed FP16 values

VSQRTPH xmm1{k1}{z},

AND AVX512VL)

in xmm2/m128/m16bcst, and store the result in

xmm2/m128/m16bcst

OR AVX10.1

xmm1 subject to writemask k1.

EVEX.256.NP.MAP5.W0 51 /r

A

V/V

(AVX512_FP16

Compute square roots of the packed FP16 values

VSQRTPH ymm1{k1}{z},

AND AVX512VL)

in ymm2/m256/m16bcst, and store the result in

ymm2/m256/m16bcst

OR AVX10.1

ymm1 subject to writemask k1.

EVEX.512.NP.MAP5.W0 51 /r

A

V/V

AVX512_FP16

Compute square roots of the packed FP16 values

VSQRTPH zmm1{k1}{z},

OR AVX10.1

in zmm2/m512/m16bcst, and store the result in

zmm2/m512/m16bcst {er}

zmm1 subject to writemask k1.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

Description

This instruction performs a packed FP16 square-root computation on the values from source operand and stores

the packed FP16 result in the destination operand. The destination elements are updated according to the write-

mask.

Operation

VSQRTPH dest{k1}, src

VL = 128, 256 or 512

KL := VL/16

FOR i := 0 to KL-1:

IF k1[i] or *no writemask*:

IF SRC is memory and (EVEX.b = 1):

tsrc := src.fp16[0]

ELSE:

tsrc := src.fp16[i]

DEST.fp16[i] := SQRT(tsrc)

ELSE IF *zeroing*:

DEST.fp16[i] := 0

//else DEST.fp16[i] remains unchanged

DEST[MAXVL-1:VL] := 0

VSQRTPH-Compute Square Root of Packed FP16 Values

Vol. 2C

5-765

VSQRTSH-Compute Square Root of Scalar FP16 Value

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.LLIG.F3.MAP5.W0 51 /r

A

V/V

AVX512_FP16

Compute square root of the low FP16 value in

VSQRTSH xmm1{k1}{z}, xmm2,

OR AVX10.1

xmm3/m16 and store the result in xmm1 subject

xmm3/m16 {er}

to writemask k1. Bits 127:16 from xmm2 are

copied to xmm1[127:16].

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

A

Scalar

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

This instruction performs a scalar FP16 square-root computation on the source operand and stores the FP16 result

in the destination operand. Bits 127:16 of the destination operand are copied from the corresponding bits of the

first source operand. Bits MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the desti-

nation is updated according to the writemask.

Operation

VSQRTSH dest{k1}, src1, src2

IF k1[0] or *no writemask*:

DEST.fp16[0] := SQRT(src2.fp16[0])

ELSE IF *zeroing*:

DEST.fp16[0] := 0

//else DEST.fp16[0] remains unchanged

DEST[127:16] := src1[127:16]

DEST[MAXVL-1:128] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VSQRTSH __m128h _mm_mask_sqrt_round_sh (__m128h src, __mmask8 k, __m128h a, __m128h b, const int rounding);

VSQRTSH __m128h _mm_maskz_sqrt_round_sh (__mmask8 k, __m128h a, __m128h b, const int rounding);

VSQRTSH __m128h _mm_sqrt_round_sh (__m128h a, __m128h b, const int rounding);

VSQRTSH __m128h _mm_mask_sqrt_sh (__m128h src, __mmask8 k, __m128h a, __m128h b);

VSQRTSH __m128h _mm_maskz_sqrt_sh (__mmask8 k, __m128h a, __m128h b);

VSQRTSH __m128h _mm_sqrt_sh (__m128h a, __m128h b);

SIMD Floating-Point Exceptions

Invalid, Precision, Denormal

Other Exceptions

EVEX-encoded instructions, see Table 2-49, “Type E3 Class Exception Conditions.”

VSQRTSH-Compute Square Root of Scalar FP16 Value

Vol. 2C

5-767

VSUBPH-Subtract Packed FP16 Values

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.128.NP.MAP5.W0 5C /r

A

V/V

(AVX512_FP16

Subtract packed FP16 values from

VSUBPH xmm1{k1}{z}, xmm2,

AND AVX512VL)

xmm3/m128/m16bcst to xmm2, and store the

xmm3/m128/m16bcst

OR AVX10.1

result in xmm1 subject to writemask k1.

EVEX.256.NP.MAP5.W0 5C /r

A

V/V

(AVX512_FP16

Subtract packed FP16 values from

VSUBPH ymm1{k1}{z}, ymm2,

AND AVX512VL)

ymm3/m256/m16bcst to ymm2, and store the

ymm3/m256/m16bcst

OR AVX10.1¹

result in ymm1 subject to writemask k1.

EVEX.512.NP.MAP5.W0 5C /r

A

V/V

AVX512_FP16

Subtract packed FP16 values from

VSUBPH zmm1{k1}{z}, zmm2,

OR AVX10.1¹

zmm3/m512/m16bcst to zmm2, and store the

zmm3/m512/m16bcst {er}

result in zmm1 subject to writemask k1.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

This instruction subtracts packed FP16 values from second source operand from the corresponding elements in the

first source operand, storing the packed FP16 result in the destination operand. The destination elements are

updated according to the writemask.

Operation

VSUBPH (EVEX encoded versions) when src2 operand is a register

VL = 128, 256 or 512

KL := VL/16

IF (VL = 512) AND (EVEX.b = 1):

SET_RM(EVEX.RC)

ELSE

SET_RM(MXCSR.RC)

FOR j := 0 TO KL-1:

IF k1[j] OR *no writemask*:

DEST.fp16[j] := SRC1.fp16[j] - SRC2.fp16[j]

ELSE IF *zeroing*:

DEST.fp16[j] := 0

// else dest.fp16[j] remains unchanged

DEST[MAXVL-1:VL] := 0

VSUBPH-Subtract Packed FP16 Values

Vol. 2C

5-768

VSUBSH-Subtract Scalar FP16 Value

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.LLIG.F3.MAP5.W0 5C /r

A

V/V

AVX512_FP16

Subtract the low FP16 value in xmm3/m16 from

VSUBSH xmm1{k1}{z}, xmm2,

OR AVX10.1

xmm2 and store the result in xmm1 subject to

xmm3/m16 {er}

writemask k1. Bits 127:16 from xmm2 are

copied to xmm1[127:16].

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

A

Scalar

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

This instruction subtracts the low FP16 value from the second source operand from the corresponding value in the

first source operand, storing the FP16 result in the destination operand. Bits 127:16 of the destination operand are

copied from the corresponding bits of the first source operand. Bits MAXVL-1:128 of the destination operand are

zeroed. The low FP16 element of the destination is updated according to the writemask.

Operation

VSUBSH (EVEX encoded versions)

IF EVEX.b = 1 and SRC2 is a register:

SET_RM(EVEX.RC)

ELSE

SET_RM(MXCSR.RC)

IF k1[0] OR *no writemask*:

DEST.fp16[0] := SRC1.fp16[0] - SRC2.fp16[0]

ELSE IF *zeroing*:

DEST.fp16[0] := 0

// else dest.fp16[0] remains unchanged

DEST[127:16] := SRC1[127:16]

DEST[MAXVL-1:128] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VSUBSH __m128h _mm_mask_sub_round_sh (__m128h src, __mmask8 k, __m128h a, __m128h b, int rounding);

VSUBSH __m128h _mm_maskz_sub_round_sh (__mmask8 k, __m128h a, __m128h b, int rounding);

VSUBSH __m128h _mm_sub_round_sh (__m128h a, __m128h b, int rounding);

VSUBSH __m128h _mm_mask_sub_sh (__m128h src, __mmask8 k, __m128h a, __m128h b);

VSUBSH __m128h _mm_maskz_sub_sh (__mmask8 k, __m128h a, __m128h b);

VSUBSH __m128h _mm_sub_sh (__m128h a, __m128h b);

SIMD Floating-Point Exceptions

Invalid, Underflow, Overflow, Precision, Denormal.

Other Exceptions

EVEX-encoded instructions, see Table 2-49, “Type E3 Class Exception Conditions.”

VSUBSH-Subtract Scalar FP16 Value

Vol. 2C

5-770

VTESTPD/VTESTPS-Packed Bit Test

Opcode/

Op

64/32

CPUID

Description

Instruction

/

bit Mode

Feature

En

Support

Flag

VEX.128.66.0F38.W0 0E /r

RM

V/V

AVX

Set ZF and CF depending on sign bit AND and

VTESTPS xmm1, xmm2/m128

ANDN of packed single precision floating-point

sources.

VEX.256.66.0F38.W0 0E /r

RM

V/V

AVX

Set ZF and CF depending on sign bit AND and

VTESTPS ymm1, ymm2/m256

ANDN of packed single precision floating-point

sources.

VEX.128.66.0F38.W0 0F /r

RM

V/V

AVX

Set ZF and CF depending on sign bit AND and

VTESTPD xmm1, xmm2/m128

ANDN of packed double precision floating-point

sources.

VEX.256.66.0F38.W0 0F /r

RM

V/V

AVX

Set ZF and CF depending on sign bit AND and

VTESTPD ymm1, ymm2/m256

ANDN of packed double precision floating-point

sources.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RM

ModRM:reg (r)

ModRM:r/m (r)

N/A

N/A

Description

VTESTPS performs a bitwise comparison of all the sign bits of the packed single precision elements in the first

source operation and corresponding sign bits in the second source operand. If the AND of the source sign bits with

the dest sign bits produces all zeros, the ZF is set else the ZF is clear. If the AND of the source sign bits with the

inverted dest sign bits produces all zeros the CF is set else the CF is clear. An attempt to execute VTESTPS with

VEX.W=1 will cause #UD.

VTESTPD performs a bitwise comparison of all the sign bits of the double precision elements in the first source

operation and corresponding sign bits in the second source operand. If the AND of the source sign bits with the dest

sign bits produces all zeros, the ZF is set else the ZF is clear. If the AND the source sign bits with the inverted dest

sign bits produces all zeros the CF is set else the CF is clear. An attempt to execute VTESTPS with VEX.W=1 will

cause #UD.

The first source register is specified by the ModR/M reg field.

128-bit version: The first source register is an XMM register. The second source register can be an XMM register or

a 128-bit memory location. The destination register is not modified.

VEX.256 encoded version: The first source register is a YMM register. The second source register can be a YMM

register or a 256-bit memory location. The destination register is not modified.

Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

VTESTPD/VTESTPS-Packed Bit Test

Vol. 2C

5-771

VUCOMISH-Unordered Compare Scalar FP16 Values and Set EFLAGS

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.LLIG.NP.MAP5.W0 2E /r

A

V/V

AVX512_FP16

Compare low FP16 values in xmm1 and

VUCOMISH xmm1, xmm2/m16 {sae}

OR AVX10.1

xmm2/m16 and set the EFLAGS flags accordingly.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

A

Scalar

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

Description

This instruction compares the FP16 values in the low word of operand 1 (first operand) and operand 2 (second

operand), and sets the ZF, PF, and CF flags in the EFLAGS register according to the result (unordered, greater than,

less than, or equal). The OF, SF and AF flags in the EFLAGS register are set to 0. The unordered result is returned

if either source operand is a NaN (QNaN or SNaN).

Operand 1 is an XMM register; operand 2 can be an XMM register or a 16-bit memory location.

The VUCOMISH instruction differs from the VCOMISH instruction in that it signals a SIMD floating-point invalid oper-

ation exception (#I) only if a source operand is an SNaN. The COMISS instruction signals an invalid numeric excep-

tion when a source operand is either a QNaN or SNaN.

The EFLAGS register is not updated if an unmasked SIMD floating-point exception is generated. EVEX.vvvv are

reserved and must be 1111b, otherwise instructions will #UD.

Operation

VUCOMISH

RESULT := UnorderedCompare(SRC1.fp16[0],SRC2.fp16[0])

if RESULT is UNORDERED:

ZF, PF, CF := 1, 1, 1

else if RESULT is GREATER_THAN:

ZF, PF, CF := 0, 0, 0

else if RESULT is LESS_THAN:

ZF, PF, CF := 0, 0, 1

else: // RESULT is EQUALS

ZF, PF, CF := 1, 0, 0

OF, AF, SF := 0, 0, 0

Intel C/C++ Compiler Intrinsic Equivalent

VUCOMISH int _mm_ucomieq_sh (__m128h a, __m128h b);

VUCOMISH int _mm_ucomige_sh (__m128h a, __m128h b);

VUCOMISH int _mm_ucomigt_sh (__m128h a, __m128h b);

VUCOMISH int _mm_ucomile_sh (__m128h a, __m128h b);

VUCOMISH int _mm_ucomilt_sh (__m128h a, __m128h b);

VUCOMISH int _mm_ucomineq_sh (__m128h a, __m128h b);

SIMD Floating-Point Exceptions

Invalid, Denormal.

Other Exceptions

EVEX-encoded instructions, see Table 2-50, “Type E3NF Class Exception Conditions.”

VUCOMISH-Unordered Compare Scalar FP16 Values and Set EFLAGS

Vol. 2C

5-774

VZEROALL-Zero XMM, YMM, and ZMM Registers

Opcode/

Op

64/32

CPUID

Description

Instruction

/

bit Mode

Feature

En

Support

Flag

VEX.256.0F.WIG 77

ZO

V/V

AVX

Zero some of the XMM, YMM, and ZMM

registers.

VZEROALL

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ZO

N/A

N/A

N/A

N/A

Description

In 64-bit mode, the instruction zeroes XMM0-XMM15, YMM0-YMM15, and ZMM0-ZMM15. Outside 64-bit mode, it

zeroes only XMM0-XMM7, YMM0-YMM7, and ZMM0-ZMM7. VZEROALL does not modify ZMM16-ZMM31.

Note: VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD. In Compatibility and legacy 32-bit

mode only the lower 8 registers are modified.

Operation

simd_reg_file[][] is a two dimensional array representing the SIMD register file containing all the overlapping xmm, ymm, and zmm

registers present in that implementation. The major dimension is the register number: 0 for xmm0, ymm0, and zmm0; 1 for xmm1,

ymm1, and zmm1; etc. The minor dimension size is the width of the implemented SIMD state measured in bits. On a machine

supporting Intel AVX-512, the width is 512.

VZEROALL (VEX.256 encoded version)

IF (64-bit mode)

limit :=15

ELSE

limit := 7

FOR i in 0 .. limit:

simd_reg_file[i][MAXVL-1:0] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VZEROALL:

_mm256_zeroall()

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-25, “Type 8 Class Exception Conditions.”

VZEROALL-Zero XMM, YMM, and ZMM Registers

Vol. 2C

5-775

VZEROUPPER-Zero Upper Bits of YMM and ZMM Registers

Opcode/

Op

64/32

CPUID

Description

Instruction

/

bit Mode

Feature

En

Support

Flag

VEX.128.0F.WIG 77

ZO

V/V

AVX

Zero bits in positions 128 and higher of

some YMM and ZMM registers.

VZEROUPPER

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ZO

N/A

N/A

N/A

N/A

Description

In 64-bit mode, the instruction zeroes the bits in positions 128 and higher in YMM0-YMM15 and ZMM0-ZMM15.

Outside 64-bit mode, it zeroes those bits only in YMM0-YMM7 and ZMM0-ZMM7. VZEROUPPER does not modify the

lower 128 bits of these registers and it does not modify ZMM16-ZMM31.

This instruction is recommended when transitioning between AVX and legacy SSE code; it will eliminate perfor-

mance penalties caused by false dependencies.

Note: VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD. In Compatibility and legacy 32-bit

mode only the lower 8 registers are modified.

Operation

simd_reg_file[][] is a two dimensional array representing the SIMD register file containing all the overlapping xmm, ymm, and zmm

registers present in that implementation. The major dimension is the register number: 0 for xmm0, ymm0, and zmm0; 1 for xmm1,

ymm1, and zmm1; etc. The minor dimension size is the width of the implemented SIMD state measured in bits.

VZEROUPPER

IF (64-bit mode)

limit :=15

ELSE

limit := 7

FOR i in 0 .. limit:

simd_reg_file[i][MAXVL-1:128] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VZEROUPPER:

_mm256_zeroupper()

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-25, “Type 8 Class Exception Conditions.”

VZEROUPPER-Zero Upper Bits of YMM and ZMM Registers

Vol. 2C

5-776

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