Intel 64 and IA-32 Architectures. Software Developer’s Manual (2026) - page 39
SIMD Floating-Point Exceptions
None.
Other Exceptions
VEX-encoded instructions, see Table 2-21, “Type 4 Class Exception Conditions.”
EVEX-encoded instructions, see Table 2-51, “Type E4 Class Exception Conditions.”
VPMADD52LUQ-Packed Multiply of Unsigned 52-Bit Integers and Add the Low 52-Bit Products to Qword Accumulators
Vol. 2C
5-570
VPMASKMOV-Conditional SIMD Integer Packed Loads and Stores
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
-bit
Feature
Mode
Flag
VEX.128.66.0F38.W0 8C /r
RVM
V/V
AVX2
Conditionally load dword values from m128 using mask
VPMASKMOVD xmm1, xmm2, m128
in xmm2 and store in xmm1.
VEX.256.66.0F38.W0 8C /r
RVM
V/V
AVX2
Conditionally load dword values from m256 using mask
VPMASKMOVD ymm1, ymm2, m256
in ymm2 and store in ymm1.
VEX.128.66.0F38.W1 8C /r
RVM
V/V
AVX2
Conditionally load qword values from m128 using mask
VPMASKMOVQ xmm1, xmm2, m128
in xmm2 and store in xmm1.
VEX.256.66.0F38.W1 8C /r
RVM
V/V
AVX2
Conditionally load qword values from m256 using mask
VPMASKMOVQ ymm1, ymm2, m256
in ymm2 and store in ymm1.
VEX.128.66.0F38.W0 8E /r
MVR
V/V
AVX2
Conditionally store dword values from xmm2 using
VPMASKMOVD m128, xmm1, xmm2
mask in xmm1.
VEX.256.66.0F38.W0 8E /r
MVR
V/V
AVX2
Conditionally store dword values from ymm2 using
VPMASKMOVD m256, ymm1, ymm2
mask in ymm1.
VEX.128.66.0F38.W1 8E /r
MVR
V/V
AVX2
Conditionally store qword values from xmm2 using
VPMASKMOVQ m128, xmm1, xmm2
mask in xmm1.
VEX.256.66.0F38.W1 8E /r
MVR
V/V
AVX2
Conditionally store qword values from ymm2 using
VPMASKMOVQ m256, ymm1, ymm2
mask in ymm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
MVR
ModRM:r/m (w)
VEX.vvvv (r)
ModRM:reg (r)
N/A
Description
Conditionally moves packed data elements from the second source operand into the corresponding data element
of the destination operand, depending on the mask bits associated with each data element. The mask bits are
specified in the first source operand.
The mask bit for each data element is the most significant bit of that element in the first source operand. If a mask
is 1, the corresponding data element is copied from the second source operand to the destination operand. If the
mask is 0, the corresponding data element is set to zero in the load form of these instructions, and unmodified in
the store form.
The second source operand is a memory address for the load form of these instructions. The destination operand
is a memory address for the store form of these instructions. The other operands are either XMM registers (for
VEX.128 version) or YMM registers (for VEX.256 version).
Faults occur only due to mask-bit required memory accesses that caused the faults. Faults will not occur due to
referencing any memory location if the corresponding mask bit for that memory location is 0. For example, no
faults will be detected if the mask bits are all zero.
Unlike previous MASKMOV instructions (MASKMOVQ and MASKMOVDQU), a nontemporal hint is not applied to
these instructions.
Instruction behavior on alignment check reporting with mask bits of less than all 1s are the same as with mask bits
of all 1s.
VPMASKMOV-Conditional SIMD Integer Packed Loads and Stores
Vol. 2C
5-571
VMASKMOV should not be used to access memory mapped I/O as the ordering of the individual loads or stores it
does is implementation specific.
In cases where mask bits indicate data should not be loaded or stored paging A and D bits will be set in an imple-
mentation dependent way. However, A and D bits are always set for pages where data is actually loaded/stored.
Note: for load forms, the first source (the mask) is encoded in VEX.vvvv; the second source is encoded in rm_field,
and the destination register is encoded in reg_field.
Note: for store forms, the first source (the mask) is encoded in VEX.vvvv; the second source register is encoded in
reg_field, and the destination memory location is encoded in rm_field.
Operation
VPMASKMOVD - 256-bit load
DEST[31:0] := IF (SRC1[31]) Load_32(mem) ELSE 0
DEST[63:32] := IF (SRC1[63]) Load_32(mem + 4) ELSE 0
DEST[95:64] := IF (SRC1[95]) Load_32(mem + 8) ELSE 0
DEST[127:96] := IF (SRC1[127]) Load_32(mem + 12) ELSE 0
DEST[159:128] := IF (SRC1[159]) Load_32(mem + 16) ELSE 0
DEST[191:160] := IF (SRC1[191]) Load_32(mem + 20) ELSE 0
DEST[223:192] := IF (SRC1[223]) Load_32(mem + 24) ELSE 0
DEST[255:224] := IF (SRC1[255]) Load_32(mem + 28) ELSE 0
VPMASKMOVD -128-bit load
DEST[31:0] := IF (SRC1[31]) Load_32(mem) ELSE 0
DEST[63:32] := IF (SRC1[63]) Load_32(mem + 4) ELSE 0
DEST[95:64] := IF (SRC1[95]) Load_32(mem + 8) ELSE 0
DEST[127:97] := IF (SRC1[127]) Load_32(mem + 12) ELSE 0
DEST[MAXVL-1:128] := 0
VPMASKMOVQ - 256-bit load
DEST[63:0] := IF (SRC1[63]) Load_64(mem) ELSE 0
DEST[127:64] := IF (SRC1[127]) Load_64(mem + 8) ELSE 0
DEST[195:128] := IF (SRC1[191]) Load_64(mem + 16) ELSE 0
DEST[255:196] := IF (SRC1[255]) Load_64(mem + 24) ELSE 0
VPMASKMOVQ - 128-bit load
DEST[63:0] := IF (SRC1[63]) Load_64(mem) ELSE 0
DEST[127:64] := IF (SRC1[127]) Load_64(mem + 8) ELSE 0
DEST[MAXVL-1:128] := 0
VPMASKMOVD - 256-bit store
IF (SRC1[31]) DEST[31:0] := SRC2[31:0]
IF (SRC1[63]) DEST[63:32] := SRC2[63:32]
IF (SRC1[95]) DEST[95:64] := SRC2[95:64]
IF (SRC1[127]) DEST[127:96] := SRC2[127:96]
IF (SRC1[159]) DEST[159:128] :=SRC2[159:128]
IF (SRC1[191]) DEST[191:160] := SRC2[191:160]
IF (SRC1[223]) DEST[223:192] := SRC2[223:192]
IF (SRC1[255]) DEST[255:224] := SRC2[255:224]
VPMASKMOV-Conditional SIMD Integer Packed Loads and Stores
Vol. 2C
5-572
VPMASKMOVD - 128-bit store
IF (SRC1[31]) DEST[31:0] := SRC2[31:0]
IF (SRC1[63]) DEST[63:32] := SRC2[63:32]
IF (SRC1[95]) DEST[95:64] := SRC2[95:64]
IF (SRC1[127]) DEST[127:96] := SRC2[127:96]
VPMASKMOVQ - 256-bit store
IF (SRC1[63]) DEST[63:0] := SRC2[63:0]
IF (SRC1[127]) DEST[127:64] :=SRC2[127:64]
IF (SRC1[191]) DEST[191:128] := SRC2[191:128]
IF (SRC1[255]) DEST[255:192] := SRC2[255:192]
VPMASKMOVQ - 128-bit store
IF (SRC1[63]) DEST[63:0] := SRC2[63:0]
IF (SRC1[127]) DEST[127:64] :=SRC2[127:64]
Intel C/C++ Compiler Intrinsic Equivalent
VPMASKMOVD: __m256i _mm256_maskload_epi32(int const *a, __m256i mask)
VPMASKMOVD: void _mm256_maskstore_epi32(int *a, __m256i mask, __m256i b)
VPMASKMOVQ: __m256i _mm256_maskload_epi64(__int64 const *a, __m256i mask);
VPMASKMOVQ: void _mm256_maskstore_epi64(__int64 *a, __m256i mask, __m256d b);
VPMASKMOVD: __m128i _mm_maskload_epi32(int const *a, __m128i mask)
VPMASKMOVD: void _mm_maskstore_epi32(int *a, __m128i mask, __m128 b)
VPMASKMOVQ: __m128i _mm_maskload_epi64(__int cont *a, __m128i mask);
VPMASKMOVQ: void _mm_maskstore_epi64(__int64 *a, __m128i mask, __m128i b);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-23, “Type 6 Class Exception Conditions” (No AC# reported for any mask bit combinations).
VPMASKMOV-Conditional SIMD Integer Packed Loads and Stores
Vol. 2C
5-573
VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M-Convert a Vector Register to a Mask
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.F3.0F38.W0 29 /r
RM
V/V
(AVX512VL AND
Sets each bit in k1 to 1 or 0 based on the value of the
VPMOVB2M k1, xmm1
AVX512BW) OR
most significant bit of the corresponding byte in XMM1.
AVX10.1
EVEX.256.F3.0F38.W0 29 /r
RM
V/V
(AVX512VL AND
Sets each bit in k1 to 1 or 0 based on the value of the
VPMOVB2M k1, ymm1
AVX512BW) OR
most significant bit of the corresponding byte in YMM1.
AVX10.1
EVEX.512.F3.0F38.W0 29 /r
RM
V/V
AVX512BW
Sets each bit in k1 to 1 or 0 based on the value of the
VPMOVB2M k1, zmm1
OR AVX10.1
most significant bit of the corresponding byte in ZMM1.
EVEX.128.F3.0F38.W1 29 /r
RM
V/V
(AVX512VL AND
Sets each bit in k1 to 1 or 0 based on the value of the
VPMOVW2M k1, xmm1
AVX512BW) OR
most significant bit of the corresponding word in XMM1.
AVX10.1
EVEX.256.F3.0F38.W1 29 /r
RM
V/V
(AVX512VL AND
Sets each bit in k1 to 1 or 0 based on the value of the
VPMOVW2M k1, ymm1
AVX512BW) OR
most significant bit of the corresponding word in YMM1.
AVX10.1
EVEX.512.F3.0F38.W1 29 /r
RM
V/V
AVX512BW
Sets each bit in k1 to 1 or 0 based on the value of the
VPMOVW2M k1, zmm1
OR AVX10.1
most significant bit of the corresponding word in ZMM1.
EVEX.128.F3.0F38.W0 39 /r
RM
V/V
(AVX512VL AND
Sets each bit in k1 to 1 or 0 based on the value of the
VPMOVD2M k1, xmm1
AVX512DQ) OR
most significant bit of the corresponding doubleword in
AVX10.1
XMM1.
EVEX.256.F3.0F38.W0 39 /r
RM
V/V
(AVX512VL AND
Sets each bit in k1 to 1 or 0 based on the value of the
VPMOVD2M k1, ymm1
AVX512DQ) OR
most significant bit of the corresponding doubleword in
AVX10.1
YMM1.
EVEX.512.F3.0F38.W0 39 /r
RM
V/V
AVX512DQ
Sets each bit in k1 to 1 or 0 based on the value of the
VPMOVD2M k1, zmm1
OR AVX10.1
most significant bit of the corresponding doubleword in
ZMM1.
EVEX.128.F3.0F38.W1 39 /r
RM
V/V
(AVX512VL AND
Sets each bit in k1 to 1 or 0 based on the value of the
VPMOVQ2M k1, xmm1
AVX512DQ) OR
most significant bit of the corresponding quadword in
AVX10.1
XMM1.
EVEX.256.F3.0F38.W1 39 /r
RM
V/V
(AVX512VL AND
Sets each bit in k1 to 1 or 0 based on the value of the
VPMOVQ2M k1, ymm1
AVX512DQ) OR
most significant bit of the corresponding quadword in
AVX10.1
YMM1.
EVEX.512.F3.0F38.W1 39 /r
RM
V/V
AVX512DQ
Sets each bit in k1 to 1 or 0 based on the value of the
VPMOVQ2M k1, zmm1
OR AVX10.1
most significant bit of the corresponding quadword in
ZMM1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts a vector register to a mask register. Each element in the destination register is set to 1 or 0 depending on
the value of most significant bit of the corresponding element in the source register.
The source operand is a ZMM/YMM/XMM register. The destination operand is a mask register.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M-Convert a Vector Register to a Mask
Vol. 2C
5-574
Operation
VPMOVB2M (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j := 0 TO KL-1
i := j * 8
IF SRC[i+7]
THEN DEST[j] := 1
ELSE
DEST[j] := 0
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0
VPMOVW2M (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1
i := j * 16
IF SRC[i+15]
THEN DEST[j] := 1
ELSE
DEST[j] := 0
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0
VPMOVD2M (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF SRC[i+31]
THEN DEST[j] := 1
ELSE
DEST[j] := 0
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0
VPMOVQ2M (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF SRC[i+63]
THEN DEST[j] := 1
ELSE
DEST[j] := 0
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0
VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M-Convert a Vector Register to a Mask
Vol. 2C
5-575
Intel C/C++ Compiler Intrinsic Equivalents
VPMPOVB2M __mmask64 _mm512_movepi8_mask( __m512i );
VPMPOVD2M __mmask16 _mm512_movepi32_mask( __m512i );
VPMPOVQ2M __mmask8 _mm512_movepi64_mask( __m512i );
VPMPOVW2M __mmask32 _mm512_movepi16_mask( __m512i );
VPMPOVB2M __mmask32 _mm256_movepi8_mask( __m256i );
VPMPOVD2M __mmask8 _mm256_movepi32_mask( __m256i );
VPMPOVQ2M __mmask8 _mm256_movepi64_mask( __m256i );
VPMPOVW2M __mmask16 _mm256_movepi16_mask( __m256i );
VPMPOVB2M __mmask16 _mm_movepi8_mask( __m128i );
VPMPOVD2M __mmask8 _mm_movepi32_mask( __m128i );
VPMPOVQ2M __mmask8 _mm_movepi64_mask( __m128i );
VPMPOVW2M __mmask8 _mm_movepi16_mask( __m128i );
SIMD Floating-Point Exceptions
None.
Other Exceptions
EVEX-encoded instruction, see Table 2-57, “Type E7NM Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M-Convert a Vector Register to a Mask
Vol. 2C
5-576
VPMOVDB/VPMOVSDB/VPMOVUSDB-Down Convert DWord to Byte
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.F3.0F38.W0 31 /r
A
V/V
(AVX512VL
Converts 4 packed double-word integers from
VPMOVDB xmm1/m32 {k1}{z}, xmm2
AND AVX512F)
xmm2 into 4 packed byte integers in
OR AVX10.1
xmm1/m32 with truncation under writemask
k1.
EVEX.128.F3.0F38.W0 21 /r
A
V/V
(AVX512VL
Converts 4 packed signed double-word integers
VPMOVSDB xmm1/m32 {k1}{z}, xmm2
AND AVX512F)
from xmm2 into 4 packed signed byte integers
OR AVX10.1
in xmm1/m32 using signed saturation under
writemask k1.
EVEX.128.F3.0F38.W0 11 /r
A
V/V
(AVX512VL
Converts 4 packed unsigned double-word
VPMOVUSDB xmm1/m32 {k1}{z}, xmm2
AND AVX512F)
integers from xmm2 into 4 packed unsigned
OR AVX10.1
byte integers in xmm1/m32 using unsigned
saturation under writemask k1.
EVEX.256.F3.0F38.W0 31 /r
A
V/V
(AVX512VL
Converts 8 packed double-word integers from
VPMOVDB xmm1/m64 {k1}{z}, ymm2
AND AVX512F)
ymm2 into 8 packed byte integers in
OR AVX10.1
xmm1/m64 with truncation under writemask
k1.
EVEX.256.F3.0F38.W0 21 /r
A
V/V
(AVX512VL
Converts 8 packed signed double-word integers
VPMOVSDB xmm1/m64 {k1}{z}, ymm2
AND AVX512F)
from ymm2 into 8 packed signed byte integers
OR AVX10.1
in xmm1/m64 using signed saturation under
writemask k1.
EVEX.256.F3.0F38.W0 11 /r
A
V/V
(AVX512VL
Converts 8 packed unsigned double-word
VPMOVUSDB xmm1/m64 {k1}{z}, ymm2
AND AVX512F)
integers from ymm2 into 8 packed unsigned
OR AVX10.1
byte integers in xmm1/m64 using unsigned
saturation under writemask k1.
EVEX.512.F3.0F38.W0 31 /r
A
V/V
AVX512F
Converts 16 packed double-word integers from
VPMOVDB xmm1/m128 {k1}{z}, zmm2
OR AVX10.1
zmm2 into 16 packed byte integers in
xmm1/m128 with truncation under writemask
k1.
EVEX.512.F3.0F38.W0 21 /r
A
V/V
AVX512F
Converts 16 packed signed double-word
VPMOVSDB xmm1/m128 {k1}{z}, zmm2
OR AVX10.1
integers from zmm2 into 16 packed signed byte
integers in xmm1/m128 using signed saturation
under writemask k1.
EVEX.512.F3.0F38.W0 11 /r
A
V/V
AVX512F
Converts 16 packed unsigned double-word
VPMOVUSDB xmm1/m128 {k1}{z},
OR AVX10.1
integers from zmm2 into 16 packed unsigned
zmm2
byte integers in xmm1/m128 using unsigned
saturation under writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Quarter Mem
ModRM:r/m (w)
ModRM:reg (r)
N/A
N/A
VPMOVDB/VPMOVSDB/VPMOVUSDB-Down Convert DWord to Byte
Vol. 2C
5-577
Description
VPMOVDB down converts 32-bit integer elements in the source operand (the second operand) into packed bytes
using truncation. VPMOVSDB converts signed 32-bit integers into packed signed bytes using signed saturation.
VPMOVUSDB convert unsigned double-word values into unsigned byte values using unsigned saturation.
The source operand is a ZMM/YMM/XMM register. The destination operand is a XMM register or a 128/64/32-bit
memory location.
Down-converted byte elements are written to the destination operand (the first operand) from the least-significant
byte. Byte elements of the destination operand are updated according to the writemask. Bits (MAXVL-1:128/64/32)
of the register destination are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VPMOVDB instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 8
m := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := TruncateDoubleWordToByte (SRC[m+31:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/4] := 0;
VPMOVDB instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 8
m := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := TruncateDoubleWordToByte (SRC[m+31:m])
ELSE *DEST[i+7:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVSDB instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 8
m := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := SaturateSignedDoubleWordToByte (SRC[m+31:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] := 0
FI
VPMOVDB/VPMOVSDB/VPMOVUSDB-Down Convert DWord to Byte
Vol. 2C
5-578
FI;
ENDFOR
DEST[MAXVL-1:VL/4] := 0;
VPMOVSDB instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 8
m := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := SaturateSignedDoubleWordToByte (SRC[m+31:m])
ELSE *DEST[i+7:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVUSDB instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 8
m := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := SaturateUnsignedDoubleWordToByte (SRC[m+31:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/4] := 0;
VPMOVUSDB instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 8
m := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := SaturateUnsignedDoubleWordToByte (SRC[m+31:m])
ELSE *DEST[i+7:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVDB/VPMOVSDB/VPMOVUSDB-Down Convert DWord to Byte
Vol. 2C
5-579
Intel C/C++ Compiler Intrinsic Equivalents
VPMOVDB __m128i _mm512_cvtepi32_epi8( __m512i a);
VPMOVDB __m128i _mm512_mask_cvtepi32_epi8(__m128i s, __mmask16 k, __m512i a);
VPMOVDB __m128i _mm512_maskz_cvtepi32_epi8( __mmask16 k, __m512i a);
VPMOVDB void _mm512_mask_cvtepi32_storeu_epi8(void * d, __mmask16 k, __m512i a);
VPMOVSDB __m128i _mm512_cvtsepi32_epi8( __m512i a);
VPMOVSDB __m128i _mm512_mask_cvtsepi32_epi8(__m128i s, __mmask16 k, __m512i a);
VPMOVSDB __m128i _mm512_maskz_cvtsepi32_epi8( __mmask16 k, __m512i a);
VPMOVSDB void _mm512_mask_cvtsepi32_storeu_epi8(void * d, __mmask16 k, __m512i a);
VPMOVUSDB __m128i _mm512_cvtusepi32_epi8( __m512i a);
VPMOVUSDB __m128i _mm512_mask_cvtusepi32_epi8(__m128i s, __mmask16 k, __m512i a);
VPMOVUSDB __m128i _mm512_maskz_cvtusepi32_epi8( __mmask16 k, __m512i a);
VPMOVUSDB void _mm512_mask_cvtusepi32_storeu_epi8(void * d, __mmask16 k, __m512i a);
VPMOVUSDB __m128i _mm256_cvtusepi32_epi8(__m256i a);
VPMOVUSDB __m128i _mm256_mask_cvtusepi32_epi8(__m128i a, __mmask8 k, __m256i b);
VPMOVUSDB __m128i _mm256_maskz_cvtusepi32_epi8( __mmask8 k, __m256i b);
VPMOVUSDB void _mm256_mask_cvtusepi32_storeu_epi8(void * , __mmask8 k, __m256i b);
VPMOVUSDB __m128i _mm_cvtusepi32_epi8(__m128i a);
VPMOVUSDB __m128i _mm_mask_cvtusepi32_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVUSDB __m128i _mm_maskz_cvtusepi32_epi8( __mmask8 k, __m128i b);
VPMOVUSDB void _mm_mask_cvtusepi32_storeu_epi8(void * , __mmask8 k, __m128i b);
VPMOVSDB __m128i _mm256_cvtsepi32_epi8(__m256i a);
VPMOVSDB __m128i _mm256_mask_cvtsepi32_epi8(__m128i a, __mmask8 k, __m256i b);
VPMOVSDB __m128i _mm256_maskz_cvtsepi32_epi8( __mmask8 k, __m256i b);
VPMOVSDB void _mm256_mask_cvtsepi32_storeu_epi8(void * , __mmask8 k, __m256i b);
VPMOVSDB __m128i _mm_cvtsepi32_epi8(__m128i a);
VPMOVSDB __m128i _mm_mask_cvtsepi32_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVSDB __m128i _mm_maskz_cvtsepi32_epi8( __mmask8 k, __m128i b);
VPMOVSDB void _mm_mask_cvtsepi32_storeu_epi8(void * , __mmask8 k, __m128i b);
VPMOVDB __m128i _mm256_cvtepi32_epi8(__m256i a);
VPMOVDB __m128i _mm256_mask_cvtepi32_epi8(__m128i a, __mmask8 k, __m256i b);
VPMOVDB __m128i _mm256_maskz_cvtepi32_epi8( __mmask8 k, __m256i b);
VPMOVDB void _mm256_mask_cvtepi32_storeu_epi8(void * , __mmask8 k, __m256i b);
VPMOVDB __m128i _mm_cvtepi32_epi8(__m128i a);
VPMOVDB __m128i _mm_mask_cvtepi32_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVDB __m128i _mm_maskz_cvtepi32_epi8( __mmask8 k, __m128i b);
VPMOVDB void _mm_mask_cvtepi32_storeu_epi8(void * , __mmask8 k, __m128i b);
SIMD Floating-Point Exceptions
None.
Other Exceptions
EVEX-encoded instruction, see Table 2-55, “Type E6 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VPMOVDB/VPMOVSDB/VPMOVUSDB-Down Convert DWord to Byte
Vol. 2C
5-580
VPMOVDW/VPMOVSDW/VPMOVUSDW-Down Convert DWord to Word
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.F3.0F38.W0 33 /r
A
V/V
(AVX512VL AND
Converts 4 packed double-word integers
VPMOVDW xmm1/m64 {k1}{z}, xmm2
AVX512F) OR
from xmm2 into 4 packed word integers in
AVX10.1
xmm1/m64 with truncation under
writemask k1.
EVEX.128.F3.0F38.W0 23 /r
A
V/V
(AVX512VL AND
Converts 4 packed signed double-word
VPMOVSDW xmm1/m64 {k1}{z}, xmm2
AVX512F) OR
integers from xmm2 into 4 packed signed
AVX10.1
word integers in ymm1/m64 using signed
saturation under writemask k1.
EVEX.128.F3.0F38.W0 13 /r
A
V/V
(AVX512VL AND
Converts 4 packed unsigned double-word
VPMOVUSDW xmm1/m64 {k1}{z}, xmm2
AVX512F) OR
integers from xmm2 into 4 packed unsigned
AVX10.1
word integers in xmm1/m64 using unsigned
saturation under writemask k1.
EVEX.256.F3.0F38.W0 33 /r
A
V/V
(AVX512VL AND
Converts 8 packed double-word integers
VPMOVDW xmm1/m128 {k1}{z}, ymm2
AVX512F) OR
from ymm2 into 8 packed word integers in
AVX10.1
xmm1/m128 with truncation under
writemask k1.
EVEX.256.F3.0F38.W0 23 /r
A
V/V
(AVX512VL AND
Converts 8 packed signed double-word
VPMOVSDW xmm1/m128 {k1}{z}, ymm2
AVX512F) OR
integers from ymm2 into 8 packed signed
AVX10.1
word integers in xmm1/m128 using signed
saturation under writemask k1.
EVEX.256.F3.0F38.W0 13 /r
A
V/V
(AVX512VL AND
Converts 8 packed unsigned double-word
VPMOVUSDW xmm1/m128 {k1}{z},
AVX512F) OR
integers from ymm2 into 8 packed unsigned
ymm2
AVX10.1
word integers in xmm1/m128 using
unsigned saturation under writemask k1.
EVEX.512.F3.0F38.W0 33 /r
A
V/V
AVX512F
Converts 16 packed double-word integers
VPMOVDW ymm1/m256 {k1}{z}, zmm2
OR AVX10.1
from zmm2 into 16 packed word integers in
ymm1/m256 with truncation under
writemask k1.
EVEX.512.F3.0F38.W0 23 /r
A
V/V
AVX512F
Converts 16 packed signed double-word
VPMOVSDW ymm1/m256 {k1}{z}, zmm2
OR AVX10.1
integers from zmm2 into 16 packed signed
word integers in ymm1/m256 using signed
saturation under writemask k1.
EVEX.512.F3.0F38.W0 13 /r
A
V/V
AVX512F
Converts 16 packed unsigned double-word
VPMOVUSDW ymm1/m256 {k1}{z},
OR AVX10.1
integers from zmm2 into 16 packed unsigned
zmm2
word integers in ymm1/m256 using
unsigned saturation under writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Half Mem
ModRM:r/m (w)
ModRM:reg (r)
N/A
N/A
VPMOVDW/VPMOVSDW/VPMOVUSDW-Down Convert DWord to Word
Vol. 2C
5-581
Description
VPMOVDW down converts 32-bit integer elements in the source operand (the second operand) into packed words
using truncation. VPMOVSDW converts signed 32-bit integers into packed signed words using signed saturation.
VPMOVUSDW convert unsigned double-word values into unsigned word values using unsigned saturation.
The source operand is a ZMM/YMM/XMM register. The destination operand is a YMM/XMM/XMM register or a
256/128/64-bit memory location.
Down-converted word elements are written to the destination operand (the first operand) from the least-significant
word. Word elements of the destination operand are updated according to the writemask. Bits (MAXVL-
1:256/128/64) of the register destination are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VPMOVDW instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 16
m := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := TruncateDoubleWordToWord (SRC[m+31:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0;
VPMOVDW instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 16
m := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := TruncateDoubleWordToWord (SRC[m+31:m])
ELSE
*DEST[i+15:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVSDW instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 16
m := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := SaturateSignedDoubleWordToWord (SRC[m+31:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] := 0
VPMOVDW/VPMOVSDW/VPMOVUSDW-Down Convert DWord to Word
Vol. 2C
5-582
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0;
VPMOVSDW instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 16
m := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := SaturateSignedDoubleWordToWord (SRC[m+31:m])
ELSE
*DEST[i+15:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVUSDW instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 16
m := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := SaturateUnsignedDoubleWordToWord (SRC[m+31:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0;
VPMOVUSDW instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 16
m := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := SaturateUnsignedDoubleWordToWord (SRC[m+31:m])
ELSE
*DEST[i+15:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVDW/VPMOVSDW/VPMOVUSDW-Down Convert DWord to Word
Vol. 2C
5-583
Intel C/C++ Compiler Intrinsic Equivalents
VPMOVDW __m256i _mm512_cvtepi32_epi16( __m512i a);
VPMOVDW __m256i _mm512_mask_cvtepi32_epi16(__m256i s, __mmask16 k, __m512i a);
VPMOVDW __m256i _mm512_maskz_cvtepi32_epi16( __mmask16 k, __m512i a);
VPMOVDW void _mm512_mask_cvtepi32_storeu_epi16(void * d, __mmask16 k, __m512i a);
VPMOVSDW __m256i _mm512_cvtsepi32_epi16( __m512i a);
VPMOVSDW __m256i _mm512_mask_cvtsepi32_epi16(__m256i s, __mmask16 k, __m512i a);
VPMOVSDW __m256i _mm512_maskz_cvtsepi32_epi16( __mmask16 k, __m512i a);
VPMOVSDW void _mm512_mask_cvtsepi32_storeu_epi16(void * d, __mmask16 k, __m512i a);
VPMOVUSDW __m256i _mm512_cvtusepi32_epi16 __m512i a);
VPMOVUSDW __m256i _mm512_mask_cvtusepi32_epi16(__m256i s, __mmask16 k, __m512i a);
VPMOVUSDW __m256i _mm512_maskz_cvtusepi32_epi16( __mmask16 k, __m512i a);
VPMOVUSDW void _mm512_mask_cvtusepi32_storeu_epi16(void * d, __mmask16 k, __m512i a);
VPMOVUSDW __m128i _mm256_cvtusepi32_epi16(__m256i a);
VPMOVUSDW __m128i _mm256_mask_cvtusepi32_epi16(__m128i a, __mmask8 k, __m256i b);
VPMOVUSDW __m128i _mm256_maskz_cvtusepi32_epi16( __mmask8 k, __m256i b);
VPMOVUSDW void _mm256_mask_cvtusepi32_storeu_epi16(void * , __mmask8 k, __m256i b);
VPMOVUSDW __m128i _mm_cvtusepi32_epi16(__m128i a);
VPMOVUSDW __m128i _mm_mask_cvtusepi32_epi16(__m128i a, __mmask8 k, __m128i b);
VPMOVUSDW __m128i _mm_maskz_cvtusepi32_epi16( __mmask8 k, __m128i b);
VPMOVUSDW void _mm_mask_cvtusepi32_storeu_epi16(void * , __mmask8 k, __m128i b);
VPMOVSDW __m128i _mm256_cvtsepi32_epi16(__m256i a);
VPMOVSDW __m128i _mm256_mask_cvtsepi32_epi16(__m128i a, __mmask8 k, __m256i b);
VPMOVSDW __m128i _mm256_maskz_cvtsepi32_epi16( __mmask8 k, __m256i b);
VPMOVSDW void _mm256_mask_cvtsepi32_storeu_epi16(void * , __mmask8 k, __m256i b);
VPMOVSDW __m128i _mm_cvtsepi32_epi16(__m128i a);
VPMOVSDW __m128i _mm_mask_cvtsepi32_epi16(__m128i a, __mmask8 k, __m128i b);
VPMOVSDW __m128i _mm_maskz_cvtsepi32_epi16( __mmask8 k, __m128i b);
VPMOVSDW void _mm_mask_cvtsepi32_storeu_epi16(void * , __mmask8 k, __m128i b);
VPMOVDW __m128i _mm256_cvtepi32_epi16(__m256i a);
VPMOVDW __m128i _mm256_mask_cvtepi32_epi16(__m128i a, __mmask8 k, __m256i b);
VPMOVDW __m128i _mm256_maskz_cvtepi32_epi16( __mmask8 k, __m256i b);
VPMOVDW void _mm256_mask_cvtepi32_storeu_epi16(void * , __mmask8 k, __m256i b);
VPMOVDW __m128i _mm_cvtepi32_epi16(__m128i a);
VPMOVDW __m128i _mm_mask_cvtepi32_epi16(__m128i a, __mmask8 k, __m128i b);
VPMOVDW __m128i _mm_maskz_cvtepi32_epi16( __mmask8 k, __m128i b);
VPMOVDW void _mm_mask_cvtepi32_storeu_epi16(void * , __mmask8 k, __m128i b);
SIMD Floating-Point Exceptions
None.
Other Exceptions
EVEX-encoded instruction, see Table 2-55, “Type E6 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VPMOVDW/VPMOVSDW/VPMOVUSDW-Down Convert DWord to Word
Vol. 2C
5-584
VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q-Convert a Mask Register to a Vector
Register
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.F3.0F38.W0 28 /r
RM
V/V
(AVX512VL AND
Sets each byte in XMM1 to all 1’s or all 0’s based on the
VPMOVM2B xmm1, k1
AVX512BW) OR
value of the corresponding bit in k1.
AVX10.1
EVEX.256.F3.0F38.W0 28 /r
RM
V/V
(AVX512VL AND
Sets each byte in YMM1 to all 1’s or all 0’s based on the
VPMOVM2B ymm1, k1
AVX512BW) OR
value of the corresponding bit in k1.
AVX10.1
EVEX.512.F3.0F38.W0 28 /r
RM
V/V
AVX512BW
Sets each byte in ZMM1 to all 1’s or all 0’s based on the
VPMOVM2B zmm1, k1
OR AVX10.1
value of the corresponding bit in k1.
EVEX.128.F3.0F38.W1 28 /r
RM
V/V
(AVX512VL AND
Sets each word in XMM1 to all 1’s or all 0’s based on
VPMOVM2W xmm1, k1
AVX512BW) OR
the value of the corresponding bit in k1.
AVX10.1
EVEX.256.F3.0F38.W1 28 /r
RM
V/V
(AVX512VL AND
Sets each word in YMM1 to all 1’s or all 0’s based on
VPMOVM2W ymm1, k1
AVX512BW) OR
the value of the corresponding bit in k1.
AVX10.1
EVEX.512.F3.0F38.W1 28 /r
RM
V/V
AVX512BW
Sets each word in ZMM1 to all 1’s or all 0’s based on
VPMOVM2W zmm1, k1
OR AVX10.1
the value of the corresponding bit in k1.
EVEX.128.F3.0F38.W0 38 /r
RM
V/V
(AVX512VL AND
Sets each doubleword in XMM1 to all 1’s or all 0’s
VPMOVM2D xmm1, k1
AVX512DQ) OR
based on the value of the corresponding bit in k1.
AVX10.1
EVEX.256.F3.0F38.W0 38 /r
RM
V/V
(AVX512VL AND
Sets each doubleword in YMM1 to all 1’s or all 0’s based
VPMOVM2D ymm1, k1
AVX512DQ) OR
on the value of the corresponding bit in k1.
AVX10.1
EVEX.512.F3.0F38.W0 38 /r
RM
V/V
AVX512DQ
Sets each doubleword in ZMM1 to all 1’s or all 0’s based
VPMOVM2D zmm1, k1
OR AVX10.1
on the value of the corresponding bit in k1.
EVEX.128.F3.0F38.W1 38 /r
RM
V/V
(AVX512VL AND
Sets each quadword in XMM1 to all 1’s or all 0’s based
VPMOVM2Q xmm1, k1
AVX512DQ) OR
on the value of the corresponding bit in k1.
AVX10.1
EVEX.256.F3.0F38.W1 38 /r
RM
V/V
(AVX512VL AND
Sets each quadword in YMM1 to all 1’s or all 0’s based
VPMOVM2Q ymm1, k1
AVX512DQ) OR
on the value of the corresponding bit in k1.
AVX10.1
EVEX.512.F3.0F38.W1 38 /r
RM
V/V
AVX512DQ
Sets each quadword in ZMM1 to all 1’s or all 0’s based
VPMOVM2Q zmm1, k1
OR AVX10.1
on the value of the corresponding bit in k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts a mask register to a vector register. Each element in the destination register is set to all 1’s or all 0’s
depending on the value of the corresponding bit in the source mask register.
The source operand is a mask register. The destination operand is a ZMM/YMM/XMM register.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q-Convert a Mask Register to a Vector Register
Vol. 2C
5-585
Operation
VPMOVM2B (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j := 0 TO KL-1
i := j * 8
IF SRC[j]
THEN DEST[i+7:i] := -1
ELSE
DEST[i+7:i] := 0
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPMOVM2W (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1
i := j * 16
IF SRC[j]
THEN DEST[i+15:i] := -1
ELSE
DEST[i+15:i] := 0
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPMOVM2D (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF SRC[j]
THEN DEST[i+31:i] := -1
ELSE
DEST[i+31:i] := 0
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPMOVM2Q (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF SRC[j]
THEN DEST[i+63:i] := -1
ELSE
DEST[i+63:i] := 0
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q-Convert a Mask Register to a Vector Register
Vol. 2C
5-586
Intel C/C++ Compiler Intrinsic Equivalents
VPMOVM2B __m512i _mm512_movm_epi8(__mmask64 );
VPMOVM2D __m512i _mm512_movm_epi32(__mmask8 );
VPMOVM2Q __m512i _mm512_movm_epi64(__mmask16 );
VPMOVM2W __m512i _mm512_movm_epi16(__mmask32 );
VPMOVM2B __m256i _mm256_movm_epi8(__mmask32 );
VPMOVM2D __m256i _mm256_movm_epi32(__mmask8 );
VPMOVM2Q __m256i _mm256_movm_epi64(__mmask8 );
VPMOVM2W __m256i _mm256_movm_epi16(__mmask16 );
VPMOVM2B __m128i _mm_movm_epi8(__mmask16 );
VPMOVM2D __m128i _mm_movm_epi32(__mmask8 );
VPMOVM2Q __m128i _mm_movm_epi64(__mmask8 );
VPMOVM2W __m128i _mm_movm_epi16(__mmask8 );
SIMD Floating-Point Exceptions
None.
Other Exceptions
EVEX-encoded instruction, see Table 2-57, “Type E7NM Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q-Convert a Mask Register to a Vector Register
Vol. 2C
5-587
VPMOVQB/VPMOVSQB/VPMOVUSQB-Down Convert QWord to Byte
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.F3.0F38.W0 32 /r
A
V/V
(AVX512VL AND
Converts 2 packed quad-word integers from
VPMOVQB xmm1/m16 {k1}{z}, xmm2
AVX512F) OR
xmm2 into 2 packed byte integers in
AVX10.1
xmm1/m16 with truncation under writemask
k1.
EVEX.128.F3.0F38.W0 22 /r
A
V/V
(AVX512VL AND
Converts 2 packed signed quad-word integers
VPMOVSQB xmm1/m16 {k1}{z}, xmm2
AVX512F) OR
from xmm2 into 2 packed signed byte integers
AVX10.1
in xmm1/m16 using signed saturation under
writemask k1.
EVEX.128.F3.0F38.W0 12 /r
A
V/V
(AVX512VL AND
Converts 2 packed unsigned quad-word
VPMOVUSQB xmm1/m16 {k1}{z},
AVX512F) OR
integers from xmm2 into 2 packed unsigned
xmm2
AVX10.1
byte integers in xmm1/m16 using unsigned
saturation under writemask k1.
EVEX.256.F3.0F38.W0 32 /r
A
V/V
(AVX512VL AND
Converts 4 packed quad-word integers from
VPMOVQB xmm1/m32 {k1}{z}, ymm2
AVX512F) OR
ymm2 into 4 packed byte integers in
AVX10.1
xmm1/m32 with truncation under writemask
k1.
EVEX.256.F3.0F38.W0 22 /r
A
V/V
(AVX512VL AND
Converts 4 packed signed quad-word integers
VPMOVSQB xmm1/m32 {k1}{z}, ymm2
AVX512F) OR
from ymm2 into 4 packed signed byte integers
AVX10.1
in xmm1/m32 using signed saturation under
writemask k1.
EVEX.256.F3.0F38.W0 12 /r
A
V/V
(AVX512VL AND
Converts 4 packed unsigned quad-word
VPMOVUSQB xmm1/m32 {k1}{z},
AVX512F) OR
integers from ymm2 into 4 packed unsigned
ymm2
AVX10.1
byte integers in xmm1/m32 using unsigned
saturation under writemask k1.
EVEX.512.F3.0F38.W0 32 /r
A
V/V
AVX512F
Converts 8 packed quad-word integers from
VPMOVQB xmm1/m64 {k1}{z}, zmm2
OR AVX10.1
zmm2 into 8 packed byte integers in
xmm1/m64 with truncation under writemask
k1.
EVEX.512.F3.0F38.W0 22 /r
A
V/V
AVX512F
Converts 8 packed signed quad-word integers
VPMOVSQB xmm1/m64 {k1}{z}, zmm2
OR AVX10.1
from zmm2 into 8 packed signed byte integers
in xmm1/m64 using signed saturation under
writemask k1.
EVEX.512.F3.0F38.W0 12 /r
A
V/V
AVX512F
Converts 8 packed unsigned quad-word
VPMOVUSQB xmm1/m64 {k1}{z},
OR AVX10.1
integers from zmm2 into 8 packed unsigned
zmm2
byte integers in xmm1/m64 using unsigned
saturation under writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Eighth Mem
ModRM:r/m (w)
ModRM:reg (r)
N/A
N/A
VPMOVQB/VPMOVSQB/VPMOVUSQB-Down Convert QWord to Byte
Vol. 2C
5-588
Description
VPMOVQB down converts 64-bit integer elements in the source operand (the second operand) into packed byte
elements using truncation. VPMOVSQB converts signed 64-bit integers into packed signed bytes using signed satu-
ration. VPMOVUSQB convert unsigned quad-word values into unsigned byte values using unsigned saturation. The
source operand is a vector register. The destination operand is an XMM register or a memory location.
Down-converted byte elements are written to the destination operand (the first operand) from the least-significant
byte. Byte elements of the destination operand are updated according to the writemask. Bits (MAXVL-1:64) of the
destination are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VPMOVQB instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 8
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := TruncateQuadWordToByte (SRC[m+63:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/8] := 0;
VPMOVQB instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 8
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := TruncateQuadWordToByte (SRC[m+63:m])
ELSE
*DEST[i+7:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVSQB instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 8
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := SaturateSignedQuadWordToByte (SRC[m+63:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] := 0
FI
VPMOVQB/VPMOVSQB/VPMOVUSQB-Down Convert QWord to Byte
Vol. 2C
5-589
FI;
ENDFOR
DEST[MAXVL-1:VL/8] := 0;
VPMOVSQB instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 8
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := SaturateSignedQuadWordToByte (SRC[m+63:m])
ELSE
*DEST[i+7:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVUSQB instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 8
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := SaturateUnsignedQuadWordToByte (SRC[m+63:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/8] := 0;
VPMOVUSQB instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 8
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := SaturateUnsignedQuadWordToByte (SRC[m+63:m])
ELSE
*DEST[i+7:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVQB/VPMOVSQB/VPMOVUSQB-Down Convert QWord to Byte
Vol. 2C
5-590
Intel C/C++ Compiler Intrinsic Equivalents
VPMOVQB __m128i _mm512_cvtepi64_epi8( __m512i a);
VPMOVQB __m128i _mm512_mask_cvtepi64_epi8(__m128i s, __mmask8 k, __m512i a);
VPMOVQB __m128i _mm512_maskz_cvtepi64_epi8( __mmask8 k, __m512i a);
VPMOVQB void _mm512_mask_cvtepi64_storeu_epi8(void * d, __mmask8 k, __m512i a);
VPMOVSQB __m128i _mm512_cvtsepi64_epi8( __m512i a);
VPMOVSQB __m128i _mm512_mask_cvtsepi64_epi8(__m128i s, __mmask8 k, __m512i a);
VPMOVSQB __m128i _mm512_maskz_cvtsepi64_epi8( __mmask8 k, __m512i a);
VPMOVSQB void _mm512_mask_cvtsepi64_storeu_epi8(void * d, __mmask8 k, __m512i a);
VPMOVUSQB __m128i _mm512_cvtusepi64_epi8( __m512i a);
VPMOVUSQB __m128i _mm512_mask_cvtusepi64_epi8(__m128i s, __mmask8 k, __m512i a);
VPMOVUSQB __m128i _mm512_maskz_cvtusepi64_epi8( __mmask8 k, __m512i a);
VPMOVUSQB void _mm512_mask_cvtusepi64_storeu_epi8(void * d, __mmask8 k, __m512i a);
VPMOVUSQB __m128i _mm256_cvtusepi64_epi8(__m256i a);
VPMOVUSQB __m128i _mm256_mask_cvtusepi64_epi8(__m128i a, __mmask8 k, __m256i b);
VPMOVUSQB __m128i _mm256_maskz_cvtusepi64_epi8( __mmask8 k, __m256i b);
VPMOVUSQB void _mm256_mask_cvtusepi64_storeu_epi8(void * , __mmask8 k, __m256i b);
VPMOVUSQB __m128i _mm_cvtusepi64_epi8(__m128i a);
VPMOVUSQB __m128i _mm_mask_cvtusepi64_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVUSQB __m128i _mm_maskz_cvtusepi64_epi8( __mmask8 k, __m128i b);
VPMOVUSQB void _mm_mask_cvtusepi64_storeu_epi8(void * , __mmask8 k, __m128i b);
VPMOVSQB __m128i _mm256_cvtsepi64_epi8(__m256i a);
VPMOVSQB __m128i _mm256_mask_cvtsepi64_epi8(__m128i a, __mmask8 k, __m256i b);
VPMOVSQB __m128i _mm256_maskz_cvtsepi64_epi8( __mmask8 k, __m256i b);
VPMOVSQB void _mm256_mask_cvtsepi64_storeu_epi8(void * , __mmask8 k, __m256i b);
VPMOVSQB __m128i _mm_cvtsepi64_epi8(__m128i a);
VPMOVSQB __m128i _mm_mask_cvtsepi64_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVSQB __m128i _mm_maskz_cvtsepi64_epi8( __mmask8 k, __m128i b);
VPMOVSQB void _mm_mask_cvtsepi64_storeu_epi8(void * , __mmask8 k, __m128i b);
VPMOVQB __m128i _mm256_cvtepi64_epi8(__m256i a);
VPMOVQB __m128i _mm256_mask_cvtepi64_epi8(__m128i a, __mmask8 k, __m256i b);
VPMOVQB __m128i _mm256_maskz_cvtepi64_epi8( __mmask8 k, __m256i b);
VPMOVQB void _mm256_mask_cvtepi64_storeu_epi8(void * , __mmask8 k, __m256i b);
VPMOVQB __m128i _mm_cvtepi64_epi8(__m128i a);
VPMOVQB __m128i _mm_mask_cvtepi64_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVQB __m128i _mm_maskz_cvtepi64_epi8( __mmask8 k, __m128i b);
VPMOVQB void _mm_mask_cvtepi64_storeu_epi8(void * , __mmask8 k, __m128i b);
SIMD Floating-Point Exceptions
None.
Other Exceptions
EVEX-encoded instruction, see Table 2-55, “Type E6 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VPMOVQB/VPMOVSQB/VPMOVUSQB-Down Convert QWord to Byte
Vol. 2C
5-591
VPMOVQD/VPMOVSQD/VPMOVUSQD-Down Convert QWord to DWord
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.F3.0F38.W0 35 /r
A
V/V
(AVX512VL AND
Converts 2 packed quad-word integers from
VPMOVQD xmm1/m128 {k1}{z}, xmm2
AVX512F) OR
xmm2 into 2 packed double-word integers in
AVX10.1
xmm1/m128 with truncation subject to
writemask k1.
EVEX.128.F3.0F38.W0 25 /r
A
V/V
(AVX512VL AND
Converts 2 packed signed quad-word integers
VPMOVSQD xmm1/m64 {k1}{z}, xmm2
AVX512F) OR
from xmm2 into 2 packed signed double-word
AVX10.1
integers in xmm1/m64 using signed saturation
subject to writemask k1.
EVEX.128.F3.0F38.W0 15 /r
A
V/V
(AVX512VL AND
Converts 2 packed unsigned quad-word integers
VPMOVUSQD xmm1/m64 {k1}{z},
AVX512F) OR
from xmm2 into 2 packed unsigned double-word
xmm2
AVX10.1
integers in xmm1/m64 using unsigned
saturation subject to writemask k1.
EVEX.256.F3.0F38.W0 35 /r
A
V/V
(AVX512VL AND
Converts 4 packed quad-word integers from
VPMOVQD xmm1/m128 {k1}{z}, ymm2
AVX512F) OR
ymm2 into 4 packed double-word integers in
AVX10.1
xmm1/m128 with truncation subject to
writemask k1.
EVEX.256.F3.0F38.W0 25 /r
A
V/V
(AVX512VL AND
Converts 4 packed signed quad-word integers
VPMOVSQD xmm1/m128 {k1}{z}, ymm2
AVX512F) OR
from ymm2 into 4 packed signed double-word
AVX10.1
integers in xmm1/m128 using signed saturation
subject to writemask k1.
EVEX.256.F3.0F38.W0 15 /r
A
V/V
(AVX512VL AND
Converts 4 packed unsigned quad-word integers
VPMOVUSQD xmm1/m128 {k1}{z},
AVX512F) OR
from ymm2 into 4 packed unsigned double-word
ymm2
AVX10.1
integers in xmm1/m128 using unsigned
saturation subject to writemask k1.
EVEX.512.F3.0F38.W0 35 /r
A
V/V
AVX512F
Converts 8 packed quad-word integers from
VPMOVQD ymm1/m256 {k1}{z}, zmm2
OR AVX10.1
zmm2 into 8 packed double-word integers in
ymm1/m256 with truncation subject to
writemask k1.
EVEX.512.F3.0F38.W0 25 /r
A
V/V
AVX512F
Converts 8 packed signed quad-word integers
VPMOVSQD ymm1/m256 {k1}{z}, zmm2
OR AVX10.1
from zmm2 into 8 packed signed double-word
integers in ymm1/m256 using signed saturation
subject to writemask k1.
EVEX.512.F3.0F38.W0 15 /r
A
V/V
AVX512F
Converts 8 packed unsigned quad-word integers
VPMOVUSQD ymm1/m256 {k1}{z},
OR AVX10.1
from zmm2 into 8 packed unsigned double-word
zmm2
integers in ymm1/m256 using unsigned
saturation subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Half Mem
ModRM:r/m (w)
ModRM:reg (r)
N/A
N/A
VPMOVQD/VPMOVSQD/VPMOVUSQD-Down Convert QWord to DWord
Vol. 2C
5-592
Description
VPMOVQW down converts 64-bit integer elements in the source operand (the second operand) into packed double-
words using truncation. VPMOVSQW converts signed 64-bit integers into packed signed doublewords using signed
saturation. VPMOVUSQW convert unsigned quad-word values into unsigned double-word values using unsigned
saturation.
The source operand is a ZMM/YMM/XMM register. The destination operand is a YMM/XMM/XMM register or a
256/128/64-bit memory location.
Down-converted doubleword elements are written to the destination operand (the first operand) from the least-
significant doubleword. Doubleword elements of the destination operand are updated according to the writemask.
Bits (MAXVL-1:256/128/64) of the register destination are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VPMOVQD instruction (EVEX encoded version) reg-reg form
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 32
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := TruncateQuadWordToDWord (SRC[m+63:m])
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0;
VPMOVQD instruction (EVEX encoded version) memory form
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 32
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := TruncateQuadWordToDWord (SRC[m+63:m])
ELSE *DEST[i+31:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVSQD instruction (EVEX encoded version) reg-reg form
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 32
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := SaturateSignedQuadWordToDWord (SRC[m+63:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
VPMOVQD/VPMOVSQD/VPMOVUSQD-Down Convert QWord to DWord
Vol. 2C
5-593
DEST[MAXVL-1:VL/2] := 0;
VPMOVSQD instruction (EVEX encoded version) memory form
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 32
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := SaturateSignedQuadWordToDWord (SRC[m+63:m])
ELSE *DEST[i+31:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVUSQD instruction (EVEX encoded version) reg-reg form
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 32
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := SaturateUnsignedQuadWordToDWord (SRC[m+63:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0;
VPMOVUSQD instruction (EVEX encoded version) memory form
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 32
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := SaturateUnsignedQuadWordToDWord (SRC[m+63:m])
ELSE *DEST[i+31:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVQD/VPMOVSQD/VPMOVUSQD-Down Convert QWord to DWord
Vol. 2C
5-594
Intel C/C++ Compiler Intrinsic Equivalents
VPMOVQD __m256i _mm512_cvtepi64_epi32( __m512i a);
VPMOVQD __m256i _mm512_mask_cvtepi64_epi32(__m256i s, __mmask8 k, __m512i a);
VPMOVQD __m256i _mm512_maskz_cvtepi64_epi32( __mmask8 k, __m512i a);
VPMOVQD void _mm512_mask_cvtepi64_storeu_epi32(void * d, __mmask8 k, __m512i a);
VPMOVSQD __m256i _mm512_cvtsepi64_epi32( __m512i a);
VPMOVSQD __m256i _mm512_mask_cvtsepi64_epi32(__m256i s, __mmask8 k, __m512i a);
VPMOVSQD __m256i _mm512_maskz_cvtsepi64_epi32( __mmask8 k, __m512i a);
VPMOVSQD void _mm512_mask_cvtsepi64_storeu_epi32(void * d, __mmask8 k, __m512i a);
VPMOVUSQD __m256i _mm512_cvtusepi64_epi32( __m512i a);
VPMOVUSQD __m256i _mm512_mask_cvtusepi64_epi32(__m256i s, __mmask8 k, __m512i a);
VPMOVUSQD __m256i _mm512_maskz_cvtusepi64_epi32( __mmask8 k, __m512i a);
VPMOVUSQD void _mm512_mask_cvtusepi64_storeu_epi32(void * d, __mmask8 k, __m512i a);
VPMOVUSQD __m128i _mm256_cvtusepi64_epi32(__m256i a);
VPMOVUSQD __m128i _mm256_mask_cvtusepi64_epi32(__m128i a, __mmask8 k, __m256i b);
VPMOVUSQD __m128i _mm256_maskz_cvtusepi64_epi32( __mmask8 k, __m256i b);
VPMOVUSQD void _mm256_mask_cvtusepi64_storeu_epi32(void * , __mmask8 k, __m256i b);
VPMOVUSQD __m128i _mm_cvtusepi64_epi32(__m128i a);
VPMOVUSQD __m128i _mm_mask_cvtusepi64_epi32(__m128i a, __mmask8 k, __m128i b);
VPMOVUSQD __m128i _mm_maskz_cvtusepi64_epi32( __mmask8 k, __m128i b);
VPMOVUSQD void _mm_mask_cvtusepi64_storeu_epi32(void * , __mmask8 k, __m128i b);
VPMOVSQD __m128i _mm256_cvtsepi64_epi32(__m256i a);
VPMOVSQD __m128i _mm256_mask_cvtsepi64_epi32(__m128i a, __mmask8 k, __m256i b);
VPMOVSQD __m128i _mm256_maskz_cvtsepi64_epi32( __mmask8 k, __m256i b);
VPMOVSQD void _mm256_mask_cvtsepi64_storeu_epi32(void * , __mmask8 k, __m256i b);
VPMOVSQD __m128i _mm_cvtsepi64_epi32(__m128i a);
VPMOVSQD __m128i _mm_mask_cvtsepi64_epi32(__m128i a, __mmask8 k, __m128i b);
VPMOVSQD __m128i _mm_maskz_cvtsepi64_epi32( __mmask8 k, __m128i b);
VPMOVSQD void _mm_mask_cvtsepi64_storeu_epi32(void * , __mmask8 k, __m128i b);
VPMOVQD __m128i _mm256_cvtepi64_epi32(__m256i a);
VPMOVQD __m128i _mm256_mask_cvtepi64_epi32(__m128i a, __mmask8 k, __m256i b);
VPMOVQD __m128i _mm256_maskz_cvtepi64_epi32( __mmask8 k, __m256i b);
VPMOVQD void _mm256_mask_cvtepi64_storeu_epi32(void * , __mmask8 k, __m256i b);
VPMOVQD __m128i _mm_cvtepi64_epi32(__m128i a);
VPMOVQD __m128i _mm_mask_cvtepi64_epi32(__m128i a, __mmask8 k, __m128i b);
VPMOVQD __m128i _mm_maskz_cvtepi64_epi32( __mmask8 k, __m128i b);
VPMOVQD void _mm_mask_cvtepi64_storeu_epi32(void * , __mmask8 k, __m128i b);
SIMD Floating-Point Exceptions
None.
Other Exceptions
EVEX-encoded instruction, see Table 2-55, “Type E6 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VPMOVQD/VPMOVSQD/VPMOVUSQD-Down Convert QWord to DWord
Vol. 2C
5-595
VPMOVQW/VPMOVSQW/VPMOVUSQW-Down Convert QWord to Word
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.F3.0F38.W0 34 /r
A
V/V
(AVX512VL AND
Converts 2 packed quad-word integers from
VPMOVQW xmm1/m32 {k1}{z}, xmm2
AVX512F) OR
xmm2 into 2 packed word integers in
AVX10.1
xmm1/m32 with truncation under writemask
k1.
EVEX.128.F3.0F38.W0 24 /r
A
V/V
(AVX512VL AND
Converts 8 packed signed quad-word integers
VPMOVSQW xmm1/m32 {k1}{z}, xmm2
AVX512F) OR
from zmm2 into 8 packed signed word
AVX10.1
integers in xmm1/m32 using signed
saturation under writemask k1.
EVEX.128.F3.0F38.W0 14 /r
A
V/V
(AVX512VL AND
Converts 2 packed unsigned quad-word
VPMOVUSQW xmm1/m32 {k1}{z}, xmm2
AVX512F) OR
integers from xmm2 into 2 packed unsigned
AVX10.1
word integers in xmm1/m32 using unsigned
saturation under writemask k1.
EVEX.256.F3.0F38.W0 34 /r
A
V/V
(AVX512VL AND
Converts 4 packed quad-word integers from
VPMOVQW xmm1/m64 {k1}{z}, ymm2
AVX512F) OR
ymm2 into 4 packed word integers in
AVX10.1
xmm1/m64 with truncation under writemask
k1.
EVEX.256.F3.0F38.W0 24 /r
A
V/V
(AVX512VL AND
Converts 4 packed signed quad-word integers
VPMOVSQW xmm1/m64 {k1}{z}, ymm2
AVX512F) OR
from ymm2 into 4 packed signed word
AVX10.1
integers in xmm1/m64 using signed
saturation under writemask k1.
EVEX.256.F3.0F38.W0 14 /r
A
V/V
(AVX512VL AND
Converts 4 packed unsigned quad-word
VPMOVUSQW xmm1/m64 {k1}{z}, ymm2
AVX512F) OR
integers from ymm2 into 4 packed unsigned
AVX10.1
word integers in xmm1/m64 using unsigned
saturation under writemask k1.
EVEX.512.F3.0F38.W0 34 /r
A
V/V
AVX512F
Converts 8 packed quad-word integers from
VPMOVQW xmm1/m128 {k1}{z}, zmm2
OR AVX10.1
zmm2 into 8 packed word integers in
xmm1/m128 with truncation under
writemask k1.
EVEX.512.F3.0F38.W0 24 /r
A
V/V
AVX512F
Converts 8 packed signed quad-word integers
VPMOVSQW xmm1/m128 {k1}{z}, zmm2
OR AVX10.1
from zmm2 into 8 packed signed word
integers in xmm1/m128 using signed
saturation under writemask k1.
EVEX.512.F3.0F38.W0 14 /r
A
V/V
AVX512F
Converts 8 packed unsigned quad-word
VPMOVUSQW xmm1/m128 {k1}{z},
OR AVX10.1
integers from zmm2 into 8 packed unsigned
zmm2
word integers in xmm1/m128 using unsigned
saturation under writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Quarter Mem
ModRM:r/m (w)
ModRM:reg (r)
N/A
N/A
VPMOVQW/VPMOVSQW/VPMOVUSQW-Down Convert QWord to Word
Vol. 2C
5-596
Description
VPMOVQW down converts 64-bit integer elements in the source operand (the second operand) into packed words
using truncation. VPMOVSQW converts signed 64-bit integers into packed signed words using signed saturation.
VPMOVUSQW convert unsigned quad-word values into unsigned word values using unsigned saturation.
The source operand is a ZMM/YMM/XMM register. The destination operand is a XMM register or a 128/64/32-bit
memory location.
Down-converted word elements are written to the destination operand (the first operand) from the least-significant
word. Word elements of the destination operand are updated according to the writemask. Bits (MAXVL-
1:128/64/32) of the register destination are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VPMOVQW instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 16
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := TruncateQuadWordToWord (SRC[m+63:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/4] := 0;
VPMOVQW instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 16
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := TruncateQuadWordToWord (SRC[m+63:m])
ELSE
*DEST[i+15:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVSQW instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 16
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := SaturateSignedQuadWordToWord (SRC[m+63:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] := 0
VPMOVQW/VPMOVSQW/VPMOVUSQW-Down Convert QWord to Word
Vol. 2C
5-597
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/4] := 0;
VPMOVSQW instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 16
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := SaturateSignedQuadWordToWord (SRC[m+63:m])
ELSE
*DEST[i+15:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVUSQW instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 16
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := SaturateUnsignedQuadWordToWord (SRC[m+63:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/4] := 0;
VPMOVUSQW instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 16
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := SaturateUnsignedQuadWordToWord (SRC[m+63:m])
ELSE
*DEST[i+15:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVQW/VPMOVSQW/VPMOVUSQW-Down Convert QWord to Word
Vol. 2C
5-598
Intel C/C++ Compiler Intrinsic Equivalents
VPMOVQW __m128i _mm512_cvtepi64_epi16( __m512i a);
VPMOVQW __m128i _mm512_mask_cvtepi64_epi16(__m128i s, __mmask8 k, __m512i a);
VPMOVQW __m128i _mm512_maskz_cvtepi64_epi16( __mmask8 k, __m512i a);
VPMOVQW void _mm512_mask_cvtepi64_storeu_epi16(void * d, __mmask8 k, __m512i a);
VPMOVSQW __m128i _mm512_cvtsepi64_epi16( __m512i a);
VPMOVSQW __m128i _mm512_mask_cvtsepi64_epi16(__m128i s, __mmask8 k, __m512i a);
VPMOVSQW __m128i _mm512_maskz_cvtsepi64_epi16( __mmask8 k, __m512i a);
VPMOVSQW void _mm512_mask_cvtsepi64_storeu_epi16(void * d, __mmask8 k, __m512i a);
VPMOVUSQW __m128i _mm512_cvtusepi64_epi16( __m512i a);
VPMOVUSQW __m128i _mm512_mask_cvtusepi64_epi16(__m128i s, __mmask8 k, __m512i a);
VPMOVUSQW __m128i _mm512_maskz_cvtusepi64_epi16( __mmask8 k, __m512i a);
VPMOVUSQW void _mm512_mask_cvtusepi64_storeu_epi16(void * d, __mmask8 k, __m512i a);
VPMOVUSQD __m128i _mm256_cvtusepi64_epi32(__m256i a);
VPMOVUSQD __m128i _mm256_mask_cvtusepi64_epi32(__m128i a, __mmask8 k, __m256i b);
VPMOVUSQD __m128i _mm256_maskz_cvtusepi64_epi32( __mmask8 k, __m256i b);
VPMOVUSQD void _mm256_mask_cvtusepi64_storeu_epi32(void * , __mmask8 k, __m256i b);
VPMOVUSQD __m128i _mm_cvtusepi64_epi32(__m128i a);
VPMOVUSQD __m128i _mm_mask_cvtusepi64_epi32(__m128i a, __mmask8 k, __m128i b);
VPMOVUSQD __m128i _mm_maskz_cvtusepi64_epi32( __mmask8 k, __m128i b);
VPMOVUSQD void _mm_mask_cvtusepi64_storeu_epi32(void * , __mmask8 k, __m128i b);
VPMOVSQD __m128i _mm256_cvtsepi64_epi32(__m256i a);
VPMOVSQD __m128i _mm256_mask_cvtsepi64_epi32(__m128i a, __mmask8 k, __m256i b);
VPMOVSQD __m128i _mm256_maskz_cvtsepi64_epi32( __mmask8 k, __m256i b);
VPMOVSQD void _mm256_mask_cvtsepi64_storeu_epi32(void * , __mmask8 k, __m256i b);
VPMOVSQD __m128i _mm_cvtsepi64_epi32(__m128i a);
VPMOVSQD __m128i _mm_mask_cvtsepi64_epi32(__m128i a, __mmask8 k, __m128i b);
VPMOVSQD __m128i _mm_maskz_cvtsepi64_epi32( __mmask8 k, __m128i b);
VPMOVSQD void _mm_mask_cvtsepi64_storeu_epi32(void * , __mmask8 k, __m128i b);
VPMOVQD __m128i _mm256_cvtepi64_epi32(__m256i a);
VPMOVQD __m128i _mm256_mask_cvtepi64_epi32(__m128i a, __mmask8 k, __m256i b);
VPMOVQD __m128i _mm256_maskz_cvtepi64_epi32( __mmask8 k, __m256i b);
VPMOVQD void _mm256_mask_cvtepi64_storeu_epi32(void * , __mmask8 k, __m256i b);
VPMOVQD __m128i _mm_cvtepi64_epi32(__m128i a);
VPMOVQD __m128i _mm_mask_cvtepi64_epi32(__m128i a, __mmask8 k, __m128i b);
VPMOVQD __m128i _mm_maskz_cvtepi64_epi32( __mmask8 k, __m128i b);
VPMOVQD void _mm_mask_cvtepi64_storeu_epi32(void * , __mmask8 k, __m128i b);
SIMD Floating-Point Exceptions
None.
Other Exceptions
EVEX-encoded instruction, see Table 2-55, “Type E6 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VPMOVQW/VPMOVSQW/VPMOVUSQW-Down Convert QWord to Word
Vol. 2C
5-599
VPMOVWB/VPMOVSWB/VPMOVUSWB-Down Convert Word to Byte
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.F3.0F38.W0 30 /r
A
V/V
(AVX512VL AND
Converts 8 packed word integers from xmm2
VPMOVWB xmm1/m64 {k1}{z}, xmm2
AVX512BW) OR
into 8 packed bytes in xmm1/m64 with
AVX10.1
truncation under writemask k1.
EVEX.128.F3.0F38.W0 20 /r
A
V/V
(AVX512VL AND
Converts 8 packed signed word integers from
VPMOVSWB xmm1/m64 {k1}{z},
AVX512BW) OR
xmm2 into 8 packed signed bytes in xmm1/m64
xmm2
AVX10.1
using signed saturation under writemask k1.
EVEX.128.F3.0F38.W0 10 /r
A
V/V
(AVX512VL AND
Converts 8 packed unsigned word integers from
VPMOVUSWB xmm1/m64 {k1}{z},
AVX512BW) OR
xmm2 into 8 packed unsigned bytes in
xmm2
AVX10.1
8mm1/m64 using unsigned saturation under
writemask k1.
EVEX.256.F3.0F38.W0 30 /r
A
V/V
(AVX512VL AND
Converts 16 packed word integers from ymm2
VPMOVWB xmm1/m128 {k1}{z},
AVX512BW) OR
into 16 packed bytes in xmm1/m128 with
ymm2
AVX10.1
truncation under writemask k1.
EVEX.256.F3.0F38.W0 20 /r
A
V/V
(AVX512VL AND
Converts 16 packed signed word integers from
VPMOVSWB xmm1/m128 {k1}{z},
AVX512BW) OR
ymm2 into 16 packed signed bytes in
ymm2
AVX10.1
xmm1/m128 using signed saturation under
writemask k1.
EVEX.256.F3.0F38.W0 10 /r
A
V/V
(AVX512VL AND
Converts 16 packed unsigned word integers
VPMOVUSWB xmm1/m128 {k1}{z},
AVX512BW) OR
from ymm2 into 16 packed unsigned bytes in
ymm2
AVX10.1
xmm1/m128 using unsigned saturation under
writemask k1.
EVEX.512.F3.0F38.W0 30 /r
A
V/V
AVX512BW
Converts 32 packed word integers from zmm2
VPMOVWB ymm1/m256 {k1}{z},
OR AVX10.1
into 32 packed bytes in ymm1/m256 with
zmm2
truncation under writemask k1.
EVEX.512.F3.0F38.W0 20 /r
A
V/V
AVX512BW
Converts 32 packed signed word integers from
VPMOVSWB ymm1/m256 {k1}{z},
OR AVX10.1
zmm2 into 32 packed signed bytes in
zmm2
ymm1/m256 using signed saturation under
writemask k1.
EVEX.512.F3.0F38.W0 10 /r
A
V/V
AVX512BW
Converts 32 packed unsigned word integers
VPMOVUSWB ymm1/m256 {k1}{z},
OR AVX10.1
from zmm2 into 32 packed unsigned bytes in
zmm2
ymm1/m256 using unsigned saturation under
writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Half Mem
ModRM:r/m (w)
ModRM:reg (r)
N/A
N/A
Description
VPMOVWB down converts 16-bit integers into packed bytes using truncation. VPMOVSWB converts signed 16-bit
integers into packed signed bytes using signed saturation. VPMOVUSWB convert unsigned word values into
unsigned byte values using unsigned saturation.
The source operand is a ZMM/YMM/XMM register. The destination operand is a YMM/XMM/XMM register or a
256/128/64-bit memory location.
Down-converted byte elements are written to the destination operand (the first operand) from the least-significant
byte. Byte elements of the destination operand are updated according to the writemask. Bits (MAXVL-
1:256/128/64) of the register destination are zeroed.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
VPMOVWB/VPMOVSWB/VPMOVUSWB-Down Convert Word to Byte
Vol. 2C
5-600
Operation
VPMOVWB instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO Kl-1
i := j * 8
m := j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := TruncateWordToByte (SRC[m+15:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] = 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0;
VPMOVWB instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO Kl-1
i := j * 8
m := j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := TruncateWordToByte (SRC[m+15:m])
ELSE
*DEST[i+7:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVSWB instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO Kl-1
i := j * 8
m := j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := SaturateSignedWordToByte (SRC[m+15:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] = 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0;
VPMOVWB/VPMOVSWB/VPMOVUSWB-Down Convert Word to Byte
Vol. 2C
5-601
VPMOVSWB instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO Kl-1
i := j * 8
m := j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := SaturateSignedWordToByte (SRC[m+15:m])
ELSE
*DEST[i+7:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVUSWB instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO Kl-1
i := j * 8
m := j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := SaturateUnsignedWordToByte (SRC[m+15:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] = 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0;
VPMOVUSWB instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO Kl-1
i := j * 8
m := j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := SaturateUnsignedWordToByte (SRC[m+15:m])
ELSE
*DEST[i+7:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVWB/VPMOVSWB/VPMOVUSWB-Down Convert Word to Byte
Vol. 2C
5-602
Intel C/C++ Compiler Intrinsic Equivalents
VPMOVUSWB __m256i _mm512_cvtusepi16_epi8(__m512i a);
VPMOVUSWB __m256i _mm512_mask_cvtusepi16_epi8(__m256i a, __mmask32 k, __m512i b);
VPMOVUSWB __m256i _mm512_maskz_cvtusepi16_epi8( __mmask32 k, __m512i b);
VPMOVUSWB void _mm512_mask_cvtusepi16_storeu_epi8(void * , __mmask32 k, __m512i b);
VPMOVSWB __m256i _mm512_cvtsepi16_epi8(__m512i a);
VPMOVSWB __m256i _mm512_mask_cvtsepi16_epi8(__m256i a, __mmask32 k, __m512i b);
VPMOVSWB __m256i _mm512_maskz_cvtsepi16_epi8( __mmask32 k, __m512i b);
VPMOVSWB void _mm512_mask_cvtsepi16_storeu_epi8(void * , __mmask32 k, __m512i b);
VPMOVWB __m256i _mm512_cvtepi16_epi8(__m512i a);
VPMOVWB __m256i _mm512_mask_cvtepi16_epi8(__m256i a, __mmask32 k, __m512i b);
VPMOVWB __m256i _mm512_maskz_cvtepi16_epi8( __mmask32 k, __m512i b);
VPMOVWB void _mm512_mask_cvtepi16_storeu_epi8(void * , __mmask32 k, __m512i b);
VPMOVUSWB __m128i _mm256_cvtusepi16_epi8(__m256i a);
VPMOVUSWB __m128i _mm256_mask_cvtusepi16_epi8(__m128i a, __mmask16 k, __m256i b);
VPMOVUSWB __m128i _mm256_maskz_cvtusepi16_epi8( __mmask16 k, __m256i b);
VPMOVUSWB void _mm256_mask_cvtusepi16_storeu_epi8(void * , __mmask16 k, __m256i b);
VPMOVUSWB __m128i _mm_cvtusepi16_epi8(__m128i a);
VPMOVUSWB __m128i _mm_mask_cvtusepi16_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVUSWB __m128i _mm_maskz_cvtusepi16_epi8( __mmask8 k, __m128i b);
VPMOVUSWB void _mm_mask_cvtusepi16_storeu_epi8(void * , __mmask8 k, __m128i b);
VPMOVSWB __m128i _mm256_cvtsepi16_epi8(__m256i a);
VPMOVSWB __m128i _mm256_mask_cvtsepi16_epi8(__m128i a, __mmask16 k, __m256i b);
VPMOVSWB __m128i _mm256_maskz_cvtsepi16_epi8( __mmask16 k, __m256i b);
VPMOVSWB void _mm256_mask_cvtsepi16_storeu_epi8(void * , __mmask16 k, __m256i b);
VPMOVSWB __m128i _mm_cvtsepi16_epi8(__m128i a);
VPMOVSWB __m128i _mm_mask_cvtsepi16_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVSWB __m128i _mm_maskz_cvtsepi16_epi8( __mmask8 k, __m128i b);
VPMOVSWB void _mm_mask_cvtsepi16_storeu_epi8(void * , __mmask8 k, __m128i b);
VPMOVWB __m128i _mm256_cvtepi16_epi8(__m256i a);
VPMOVWB __m128i _mm256_mask_cvtepi16_epi8(__m128i a, __mmask16 k, __m256i b);
VPMOVWB __m128i _mm256_maskz_cvtepi16_epi8( __mmask16 k, __m256i b);
VPMOVWB void _mm256_mask_cvtepi16_storeu_epi8(void * , __mmask16 k, __m256i b);
VPMOVWB __m128i _mm_cvtepi16_epi8(__m128i a);
VPMOVWB __m128i _mm_mask_cvtepi16_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVWB __m128i _mm_maskz_cvtepi16_epi8( __mmask8 k, __m128i b);
VPMOVWB void _mm_mask_cvtepi16_storeu_epi8(void * , __mmask8 k, __m128i b);
SIMD Floating-Point Exceptions
None.
Other Exceptions
EVEX-encoded instruction, see Table 2-55, “Type E6 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VPMOVWB/VPMOVSWB/VPMOVUSWB-Down Convert Word to Byte
Vol. 2C
5-603
VPMULTISHIFTQB-Select Packed Unaligned Bytes From Quadword Sources
Opcode /
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.66.0F38.W1 83 /r
A
V/V
(AVX512VL AND
Select unaligned bytes from qwords in
VPMULTISHIFTQB xmm1 {k1}{z},
AVX512_VBMI)
xmm3/m128/m64bcst using control bytes in
xmm2,xmm3/m128/m64bcst
OR AVX10.1
xmm2, write byte results to xmm1 under k1.
EVEX.256.66.0F38.W1 83 /r
A
V/V
(AVX512VL
Select unaligned bytes from qwords in
VPMULTISHIFTQB ymm1 {k1}{z},
AVX512_VBMI)
ymm3/m256/m64bcst using control bytes in
ymm2,ymm3/m256/m64bcst
OR AVX10.1
ymm2, write byte results to ymm1 under k1.
EVEX.512.66.0F38.W1 83 /r
A
V/V
AVX512_VBMI
Select unaligned bytes from qwords in
VPMULTISHIFTQB zmm1 {k1}{z},
OR AVX10.1
zmm3/m512/m64bcst using control bytes in
zmm2,zmm3/m512/m64bcst
zmm2, write byte results to zmm1 under k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
This instruction selects eight unaligned bytes from each input qword element of the second source operand (the
third operand) and writes eight assembled bytes for each qword element in the destination operand (the first
operand). Each byte result is selected using a byte-granular shift control within the corresponding qword element
of the first source operand (the second operand). Each byte result in the destination operand is updated under the
writemask k1.
Only the low 6 bits of each control byte are used to select an 8-bit slot to extract the output byte from the qword
data in the second source operand. The starting bit of the 8-bit slot can be unaligned relative to any byte boundary
and is extracted from the input qword source at the location specified in the low 6-bit of the control byte. If the 8-
bit slot would exceed the qword boundary, the out-of-bound portion of the 8-bit slot is wrapped back to start from
bit 0 of the input qword element.
The first source operand is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM reg-
ister, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-bit memory loca-
tion. The destination operand is a ZMM/YMM/XMM register.
VPMULTISHIFTQB-Select Packed Unaligned Bytes From Quadword Sources
Vol. 2C
5-604
Operation
VPMULTISHIFTQB DEST, SRC1, SRC2 (EVEX encoded version)
(KL, VL) = (2, 128),(4, 256), (8, 512)
FOR i := 0 TO KL-1
IF EVEX.b=1 AND src2 is memory THEN
tcur := src2.qword[0]; //broadcasting
ELSE
tcur := src2.qword[i];
FI;
FOR j := 0 to 7
ctrl := src1.qword[i].byte[j] & 63;
FOR k := 0 to 7
res.bit[k] := tcur.bit[ (ctrl+k) mod 64 ];
ENDFOR
IF k1[i*8+j] or no writemask THEN
DEST.qword[i].byte[j] := res;
ELSE IF zeroing-masking THEN
DEST.qword[i].byte[j] := 0;
ENDFOR
ENDFOR
DEST.qword[MAX_VL-1:VL] := 0;
Intel C/C++ Compiler Intrinsic Equivalent
VPMULTISHIFTQB __m512i _mm512_multishift_epi64_epi8( __m512i a, __m512i b);
VPMULTISHIFTQB __m512i _mm512_mask_multishift_epi64_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);
VPMULTISHIFTQB __m512i _mm512_maskz_multishift_epi64_epi8( __mmask64 k, __m512i a, __m512i b);
VPMULTISHIFTQB __m256i _mm256_multishift_epi64_epi8( __m256i a, __m256i b);
VPMULTISHIFTQB __m256i _mm256_mask_multishift_epi64_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);
VPMULTISHIFTQB __m256i _mm256_maskz_multishift_epi64_epi8( __mmask32 k, __m256i a, __m256i b);
VPMULTISHIFTQB __m128i _mm_multishift_epi64_epi8( __m128i a, __m128i b);
VPMULTISHIFTQB __m128i _mm_mask_multishift_epi64_epi8(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMULTISHIFTQB __m128i _mm_maskz_multishift_epi64_epi8( __mmask8 k, __m128i a, __m128i b);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-52, “Type E4NF Class Exception Conditions.”
VPMULTISHIFTQB-Select Packed Unaligned Bytes From Quadword Sources
Vol. 2C
5-605
VPOPCNT-Return the Count of Number of Bits Set to 1 in BYTE/WORD/DWORD/QWORD
Opcode/
Op/
64/32
CPUID Feature Flag
Description
Instruction
En
bit Mode
Support
EVEX.128.66.0F38.W0 54 /r
A
V/V
(AVX512_BITALG
Counts the number of bits set to one in
VPOPCNTB xmm1{k1}{z},
AND AVX512VL) OR
xmm2/m128 and puts the result in xmm1 with
xmm2/m128
AVX10.1
writemask k1.
EVEX.256.66.0F38.W0 54 /r
A
V/V
(AVX512_BITALG
Counts the number of bits set to one in
VPOPCNTB ymm1{k1}{z},
AND AVX512VL) OR
ymm2/m256 and puts the result in ymm1 with
ymm2/m256
AVX10.1
writemask k1.
EVEX.512.66.0F38.W0 54 /r
A
V/V
AVX512_BITALG
Counts the number of bits set to one in
VPOPCNTB zmm1{k1}{z},
OR AVX10.1
zmm2/m512 and puts the result in zmm1 with
zmm2/m512
writemask k1.
EVEX.128.66.0F38.W1 54 /r
A
V/V
(AVX512_BITALG
Counts the number of bits set to one in
VPOPCNTW xmm1{k1}{z},
AND AVX512VL) OR
xmm2/m128 and puts the result in xmm1 with
xmm2/m128
AVX10.1
writemask k1.
EVEX.256.66.0F38.W1 54 /r
A
V/V
(AVX512_BITALG
Counts the number of bits set to one in
VPOPCNTW ymm1{k1}{z},
AND AVX512VL) OR
ymm2/m256 and puts the result in ymm1 with
ymm2/m256
AVX10.1
writemask k1.
EVEX.512.66.0F38.W1 54 /r
A
V/V
AVX512_BITALG
Counts the number of bits set to one in
VPOPCNTW zmm1{k1}{z},
OR AVX10.1
zmm2/m512 and puts the result in zmm1 with
zmm2/m512
writemask k1.
EVEX.128.66.0F38.W0 55 /r
B
V/V
(AVX512_VPOPCNTDQ
Counts the number of bits set to one in
VPOPCNTD xmm1{k1}{z},
AND AVX512VL) OR
xmm2/m128/m32bcst and puts the result in
xmm2/m128/m32bcst
AVX10.1
xmm1 with writemask k1.
EVEX.256.66.0F38.W0 55 /r
B
V/V
(AVX512_VPOPCNTDQ
Counts the number of bits set to one in
VPOPCNTD ymm1{k1}{z},
AND AVX512VL) OR
ymm2/m256/m32bcst and puts the result in
ymm2/m256/m32bcst
AVX10.1
ymm1 with writemask k1.
EVEX.512.66.0F38.W0 55 /r
B
V/V
AVX512_VPOPCNTDQ
Counts the number of bits set to one in
VPOPCNTD zmm1{k1}{z},
OR AVX10.1
zmm2/m512/m32bcst and puts the result in
zmm2/m512/m32bcst
zmm1 with writemask k1.
EVEX.128.66.0F38.W1 55 /r
B
V/V
(AVX512_VPOPCNTDQ
Counts the number of bits set to one in
VPOPCNTQ xmm1{k1}{z},
AND AVX512VL) OR
xmm2/m128/m32bcst and puts the result in
xmm2/m128/m64bcst
AVX10.1
xmm1 with writemask k1.
EVEX.256.66.0F38.W1 55 /r
B
V/V
(AVX512_VPOPCNTDQ
Counts the number of bits set to one in
VPOPCNTQ ymm1{k1}{z},
AND AVX512VL) OR
ymm2/m256/m32bcst and puts the result in
ymm2/m256/m64bcst
AVX10.1
ymm1 with writemask k1.
EVEX.512.66.0F38.W1 55 /r
B
V/V
AVX512_VPOPCNTDQ
Counts the number of bits set to one in
VPOPCNTQ zmm1{k1}{z},
OR AVX10.1
zmm2/m512/m64bcst and puts the result in
zmm2/m512/m64bcst
zmm1 with writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full Mem
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
B
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction counts the number of bits set to one in each byte, word, dword or qword element of its source (e.g.,
zmm2 or memory) and places the results in the destination register (zmm1). This instruction supports memory
fault suppression.
VPOPCNT-Return the Count of Number of Bits Set to 1 in BYTE/WORD/DWORD/QWORD
Vol. 2C
5-606
Operation
VPOPCNTB
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j := 0 TO KL-1:
IF MaskBit(j) OR *no writemask*:
DEST.byte[j] := POPCNT(SRC.byte[j])
ELSE IF *merging-masking*:
*DEST.byte[j] remains unchanged*
ELSE:
DEST.byte[j] := 0
DEST[MAX_VL-1:VL] := 0
VPOPCNTW
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1:
IF MaskBit(j) OR *no writemask*:
DEST.word[j] := POPCNT(SRC.word[j])
ELSE IF *merging-masking*:
*DEST.word[j] remains unchanged*
ELSE:
DEST.word[j] := 0
DEST[MAX_VL-1:VL] := 0
VPOPCNTD
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1:
IF MaskBit(j) OR *no writemask*:
IF SRC is broadcast memop:
t := SRC.dword[0]
ELSE:
t := SRC.dword[j]
DEST.dword[j] := POPCNT(t)
ELSE IF *merging-masking*:
*DEST..dword[j] remains unchanged*
ELSE:
DEST..dword[j] := 0
DEST[MAX_VL-1:VL] := 0
VPOPCNT-Return the Count of Number of Bits Set to 1 in BYTE/WORD/DWORD/QWORD
Vol. 2C
5-607
VPOPCNTQ
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1:
IF MaskBit(j) OR *no writemask*:
IF SRC is broadcast memop:
t := SRC.qword[0]
ELSE:
t := SRC.qword[j]
DEST.qword[j] := POPCNT(t)
ELSE IF *merging-masking*:
*DEST..qword[j] remains unchanged*
ELSE:
DEST..qword[j] := 0
DEST[MAX_VL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPOPCNTW __m128i _mm_popcnt_epi16(__m128i);
VPOPCNTW __m128i _mm_mask_popcnt_epi16(__m128i, __mmask8, __m128i);
VPOPCNTW __m128i _mm_maskz_popcnt_epi16(__mmask8, __m128i);
VPOPCNTW __m256i _mm256_popcnt_epi16(__m256i);
VPOPCNTW __m256i _mm256_mask_popcnt_epi16(__m256i, __mmask16, __m256i);
VPOPCNTW __m256i _mm256_maskz_popcnt_epi16(__mmask16, __m256i);
VPOPCNTW __m512i _mm512_popcnt_epi16(__m512i);
VPOPCNTW __m512i _mm512_mask_popcnt_epi16(__m512i, __mmask32, __m512i);
VPOPCNTW __m512i _mm512_maskz_popcnt_epi16(__mmask32, __m512i);
VPOPCNTQ __m128i _mm_popcnt_epi64(__m128i);
VPOPCNTQ __m128i _mm_mask_popcnt_epi64(__m128i, __mmask8, __m128i);
VPOPCNTQ __m128i _mm_maskz_popcnt_epi64(__mmask8, __m128i);
VPOPCNTQ __m256i _mm256_popcnt_epi64(__m256i);
VPOPCNTQ __m256i _mm256_mask_popcnt_epi64(__m256i, __mmask8, __m256i);
VPOPCNTQ __m256i _mm256_maskz_popcnt_epi64(__mmask8, __m256i);
VPOPCNTQ __m512i _mm512_popcnt_epi64(__m512i);
VPOPCNTQ __m512i _mm512_mask_popcnt_epi64(__m512i, __mmask8, __m512i);
VPOPCNTQ __m512i _mm512_maskz_popcnt_epi64(__mmask8, __m512i);
VPOPCNTD __m128i _mm_popcnt_epi32(__m128i);
VPOPCNTD __m128i _mm_mask_popcnt_epi32(__m128i, __mmask8, __m128i);
VPOPCNTD __m128i _mm_maskz_popcnt_epi32(__mmask8, __m128i);
VPOPCNTD __m256i _mm256_popcnt_epi32(__m256i);
VPOPCNTD __m256i _mm256_mask_popcnt_epi32(__m256i, __mmask8, __m256i);
VPOPCNTD __m256i _mm256_maskz_popcnt_epi32(__mmask8, __m256i);
VPOPCNTD __m512i _mm512_popcnt_epi32(__m512i);
VPOPCNTD __m512i _mm512_mask_popcnt_epi32(__m512i, __mmask16, __m512i);
VPOPCNTD __m512i _mm512_maskz_popcnt_epi32(__mmask16, __m512i);
VPOPCNTB __m128i _mm_popcnt_epi8(__m128i);
VPOPCNTB __m128i _mm_mask_popcnt_epi8(__m128i, __mmask16, __m128i);
VPOPCNTB __m128i _mm_maskz_popcnt_epi8(__mmask16, __m128i);
VPOPCNTB __m256i _mm256_popcnt_epi8(__m256i);
VPOPCNTB __m256i _mm256_mask_popcnt_epi8(__m256i, __mmask32, __m256i);
VPOPCNTB __m256i _mm256_maskz_popcnt_epi8(__mmask32, __m256i);
VPOPCNTB __m512i _mm512_popcnt_epi8(__m512i);
VPOPCNTB __m512i _mm512_mask_popcnt_epi8(__m512i, __mmask64, __m512i);
VPOPCNTB __m512i _mm512_maskz_popcnt_epi8(__mmask64, __m512i);
VPOPCNT-Return the Count of Number of Bits Set to 1 in BYTE/WORD/DWORD/QWORD
Vol. 2C
5-608
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-51, “Type E4 Class Exception Conditions.”
VPOPCNT-Return the Count of Number of Bits Set to 1 in BYTE/WORD/DWORD/QWORD
Vol. 2C
5-609
VPROLD/VPROLVD/VPROLQ/VPROLVQ-Bit Rotate Left
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.66.0F38.W0 15 /r
B
V/V
(AVX512VL AND
Rotate doublewords in xmm2 left by count in the
VPROLVD xmm1 {k1}{z}, xmm2,
AVX512F) OR
corresponding element of xmm3/m128/m32bcst.
xmm3/m128/m32bcst
AVX10.1
Result written to xmm1 under writemask k1.
EVEX.128.66.0F.W0 72 /1 ib
A
V/V
(AVX512VL AND
Rotate doublewords in xmm2/m128/m32bcst
VPROLD xmm1 {k1}{z},
AVX512F) OR
left by imm8. Result written to xmm1 using
xmm2/m128/m32bcst, imm8
AVX10.1
writemask k1.
EVEX.128.66.0F38.W1 15 /r
B
V/V
(AVX512VL AND
Rotate quadwords in xmm2 left by count in the
VPROLVQ xmm1 {k1}{z}, xmm2,
AVX512F) OR
corresponding element of xmm3/m128/m64bcst.
xmm3/m128/m64bcst
AVX10.1
Result written to xmm1 under writemask k1.
EVEX.128.66.0F.W1 72 /1 ib
A
V/V
(AVX512VL AND
Rotate quadwords in xmm2/m128/m64bcst left
VPROLQ xmm1 {k1}{z},
AVX512F) OR
by imm8. Result written to xmm1 using
xmm2/m128/m64bcst, imm8
AVX10.1
writemask k1.
EVEX.256.66.0F38.W0 15 /r
B
V/V
(AVX512VL AND
Rotate doublewords in ymm2 left by count in the
VPROLVD ymm1 {k1}{z}, ymm2,
AVX512F) OR
corresponding element of ymm3/m256/m32bcst.
ymm3/m256/m32bcst
AVX10.1
Result written to ymm1 under writemask k1.
EVEX.256.66.0F.W0 72 /1 ib
A
V/V
(AVX512VL AND
Rotate doublewords in ymm2/m256/m32bcst
VPROLD ymm1 {k1}{z},
AVX512F) OR
left by imm8. Result written to ymm1 using
ymm2/m256/m32bcst, imm8
AVX10.1
writemask k1.
EVEX.256.66.0F38.W1 15 /r
B
V/V
(AVX512VL AND
Rotate quadwords in ymm2 left by count in the
VPROLVQ ymm1 {k1}{z}, ymm2,
AVX512F) OR
corresponding element of ymm3/m256/m64bcst.
ymm3/m256/m64bcst
AVX10.1
Result written to ymm1 under writemask k1.
EVEX.256.66.0F.W1 72 /1 ib
A
V/V
(AVX512VL AND
Rotate quadwords in ymm2/m256/m64bcst left
VPROLQ ymm1 {k1}{z},
AVX512F) OR
by imm8. Result written to ymm1 using
ymm2/m256/m64bcst, imm8
AVX10.1
writemask k1.
EVEX.512.66.0F38.W0 15 /r
B
V/V
AVX512F
Rotate left of doublewords in zmm2 by count in
VPROLVD zmm1 {k1}{z}, zmm2,
OR AVX10.11
the corresponding element of
zmm3/m512/m32bcst
zmm3/m512/m32bcst. Result written to zmm1
using writemask k1.
EVEX.512.66.0F.W0 72 /1 ib
A
V/V
AVX512F
Rotate left of doublewords in
VPROLD zmm1 {k1}{z},
OR AVX10.1
zmm3/m512/m32bcst by imm8. Result written
zmm2/m512/m32bcst, imm8
to zmm1 using writemask k1.
EVEX.512.66.0F38.W1 15 /r
B
V/V
AVX512F
Rotate quadwords in zmm2 left by count in the
VPROLVQ zmm1 {k1}{z}, zmm2,
OR AVX10.1
corresponding element of zmm3/m512/m64bcst.
zmm3/m512/m64bcst
Result written to zmm1under writemask k1.
EVEX.512.66.0F.W1 72 /1 ib
A
V/V
AVX512F
Rotate quadwords in zmm2/m512/m64bcst left
VPROLQ zmm1 {k1}{z},
OR AVX10.1
by imm8. Result written to zmm1 using
zmm2/m512/m64bcst, imm8
writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
VEX.vvvv (w)
ModRM:r/m (R)
imm8
N/A
B
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
VPROLD/VPROLVD/VPROLQ/VPROLVQ-Bit Rotate Left
Vol. 2C
5-610
Description
Rotates the bits in the individual data elements (doublewords, or quadword) in the first source operand to the left
by the number of bits specified in the count operand. If the value specified by the count operand is greater than 31
(for doublewords), or 63 (for a quadword), then the count operand modulo the data size (32 or 64) is used.
EVEX.128 encoded version: The destination operand is a XMM register. The source operand is a XMM register or a
memory location (for immediate form). The count operand can come either from an XMM register or a memory
location or an 8-bit immediate. Bits (MAXVL-1:128) of the corresponding ZMM register are zeroed.
EVEX.256 encoded version: The destination operand is a YMM register. The source operand is a YMM register or a
memory location (for immediate form). The count operand can come either from an XMM register or a memory
location or an 8-bit immediate. Bits (MAXVL-1:256) of the corresponding ZMM register are zeroed.
EVEX.512 encoded version: The destination operand is a ZMM register updated according to the writemask. For the
count operand in immediate form, the source operand can be a ZMM register, a 512-bit memory location or a 512-
bit vector broadcasted from a 32/64-bit memory location, the count operand is an 8-bit immediate. For the count
operand in variable form, the first source operand (the second operand) is a ZMM register and the counter operand
(the third operand) is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32/64-bit
memory location.
Operation
LEFT_ROTATE_DWORDS(SRC, COUNT_SRC)
COUNT := COUNT_SRC modulo 32;
DEST[31:0] := (SRC << COUNT) | (SRC >> (32 - COUNT));
LEFT_ROTATE_QWORDS(SRC, COUNT_SRC)
COUNT := COUNT_SRC modulo 64;
DEST[63:0] := (SRC << COUNT) | (SRC >> (64 - COUNT));
VPROLD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC1 *is memory*)
THEN DEST[i+31:i] := LEFT_ROTATE_DWORDS(SRC1[31:0], imm8)
ELSE DEST[i+31:i] := LEFT_ROTATE_DWORDS(SRC1[i+31:i], imm8)
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPROLD/VPROLVD/VPROLQ/VPROLVQ-Bit Rotate Left
Vol. 2C
5-611
VPROLVD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+31:i] := LEFT_ROTATE_DWORDS(SRC1[i+31:i], SRC2[31:0])
ELSE DEST[i+31:i] := LEFT_ROTATE_DWORDS(SRC1[i+31:i], SRC2[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPROLQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC1 *is memory*)
THEN DEST[i+63:i] := LEFT_ROTATE_QWORDS(SRC1[63:0], imm8)
ELSE DEST[i+63:i] := LEFT_ROTATE_QWORDS(SRC1[i+63:i], imm8)
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPROLVQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+63:i] := LEFT_ROTATE_QWORDS(SRC1[i+63:i], SRC2[63:0])
ELSE DEST[i+63:i] := LEFT_ROTATE_QWORDS(SRC1[i+63:i], SRC2[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
VPROLD/VPROLVD/VPROLQ/VPROLVQ-Bit Rotate Left
Vol. 2C
5-612
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPROLD __m512i _mm512_rol_epi32(__m512i a, int imm);
VPROLD __m512i _mm512_mask_rol_epi32(__m512i a, __mmask16 k, __m512i b, int imm);
VPROLD __m512i _mm512_maskz_rol_epi32( __mmask16 k, __m512i a, int imm);
VPROLD __m256i _mm256_rol_epi32(__m256i a, int imm);
VPROLD __m256i _mm256_mask_rol_epi32(__m256i a, __mmask8 k, __m256i b, int imm);
VPROLD __m256i _mm256_maskz_rol_epi32( __mmask8 k, __m256i a, int imm);
VPROLD __m128i _mm_rol_epi32(__m128i a, int imm);
VPROLD __m128i _mm_mask_rol_epi32(__m128i a, __mmask8 k, __m128i b, int imm);
VPROLD __m128i _mm_maskz_rol_epi32( __mmask8 k, __m128i a, int imm);
VPROLQ __m512i _mm512_rol_epi64(__m512i a, int imm);
VPROLQ __m512i _mm512_mask_rol_epi64(__m512i a, __mmask8 k, __m512i b, int imm);
VPROLQ __m512i _mm512_maskz_rol_epi64(__mmask8 k, __m512i a, int imm);
VPROLQ __m256i _mm256_rol_epi64(__m256i a, int imm);
VPROLQ __m256i _mm256_mask_rol_epi64(__m256i a, __mmask8 k, __m256i b, int imm);
VPROLQ __m256i _mm256_maskz_rol_epi64( __mmask8 k, __m256i a, int imm);
VPROLQ __m128i _mm_rol_epi64(__m128i a, int imm);
VPROLQ __m128i _mm_mask_rol_epi64(__m128i a, __mmask8 k, __m128i b, int imm);
VPROLQ __m128i _mm_maskz_rol_epi64( __mmask8 k, __m128i a, int imm);
VPROLVD __m512i _mm512_rolv_epi32(__m512i a, __m512i cnt);
VPROLVD __m512i _mm512_mask_rolv_epi32(__m512i a, __mmask16 k, __m512i b, __m512i cnt);
VPROLVD __m512i _mm512_maskz_rolv_epi32(__mmask16 k, __m512i a, __m512i cnt);
VPROLVD __m256i _mm256_rolv_epi32(__m256i a, __m256i cnt);
VPROLVD __m256i _mm256_mask_rolv_epi32(__m256i a, __mmask8 k, __m256i b, __m256i cnt);
VPROLVD __m256i _mm256_maskz_rolv_epi32(__mmask8 k, __m256i a, __m256i cnt);
VPROLVD __m128i _mm_rolv_epi32(__m128i a, __m128i cnt);
VPROLVD __m128i _mm_mask_rolv_epi32(__m128i a, __mmask8 k, __m128i b, __m128i cnt);
VPROLVD __m128i _mm_maskz_rolv_epi32(__mmask8 k, __m128i a, __m128i cnt);
VPROLVQ __m512i _mm512_rolv_epi64(__m512i a, __m512i cnt);
VPROLVQ __m512i _mm512_mask_rolv_epi64(__m512i a, __mmask8 k, __m512i b, __m512i cnt);
VPROLVQ __m512i _mm512_maskz_rolv_epi64( __mmask8 k, __m512i a, __m512i cnt);
VPROLVQ __m256i _mm256_rolv_epi64(__m256i a, __m256i cnt);
VPROLVQ __m256i _mm256_mask_rolv_epi64(__m256i a, __mmask8 k, __m256i b, __m256i cnt);
VPROLVQ __m256i _mm256_maskz_rolv_epi64(__mmask8 k, __m256i a, __m256i cnt);
VPROLVQ __m128i _mm_rolv_epi64(__m128i a, __m128i cnt);
VPROLVQ __m128i _mm_mask_rolv_epi64(__m128i a, __mmask8 k, __m128i b, __m128i cnt);
VPROLVQ __m128i _mm_maskz_rolv_epi64(__mmask8 k, __m128i a, __m128i cnt);
SIMD Floating-Point Exceptions
None.
Other Exceptions
EVEX-encoded instruction, see Table 2-51, “Type E4 Class Exception Conditions.”
VPROLD/VPROLVD/VPROLQ/VPROLVQ-Bit Rotate Left
Vol. 2C
5-613
VPRORD/VPRORVD/VPRORQ/VPRORVQ-Bit Rotate Right
Opcode/
Op
64/32
CPUID Feature
Description
Instruction
/ En
bit Mode
Flag
Support
EVEX.128.66.0F38.W0 14 /r
B
V/V
(AVX512VL AND
Rotate doublewords in xmm2 right by count in the
VPRORVD xmm1 {k1}{z}, xmm2,
AVX512F) OR
corresponding element of xmm3/m128/m32bcst,
xmm3/m128/m32bcst
AVX10.1
store result using writemask k1.
EVEX.128.66.0F.W0 72 /0 ib
A
V/V
(AVX512VL AND
Rotate doublewords in xmm2/m128/m32bcst right
VPRORD xmm1 {k1}{z},
AVX512F) OR
by imm8, store result using writemask k1.
xmm2/m128/m32bcst, imm8
AVX10.1
EVEX.128.66.0F38.W1 14 /r
B
V/V
(AVX512VL AND
Rotate quadwords in xmm2 right by count in the
VPRORVQ xmm1 {k1}{z}, xmm2,
AVX512F) OR
corresponding element of xmm3/m128/m64bcst,
xmm3/m128/m64bcst
AVX10.1
store result using writemask k1.
EVEX.128.66.0F.W1 72 /0 ib
A
V/V
(AVX512VL AND
Rotate quadwords in xmm2/m128/m64bcst right
VPRORQ xmm1 {k1}{z},
AVX512F) OR
by imm8, store result using writemask k1.
xmm2/m128/m64bcst, imm8
AVX10.1
EVEX.256.66.0F38.W0 14 /r
B
V/V
(AVX512VL AND
Rotate doublewords in ymm2 right by count in the
VPRORVD ymm1 {k1}{z}, ymm2,
AVX512F) OR
corresponding element of ymm3/m256/m32bcst,
ymm3/m256/m32bcst
AVX10.1
store using result writemask k1.
EVEX.256.66.0F.W0 72 /0 ib
A
V/V
(AVX512VL AND
Rotate doublewords in ymm2/m256/m32bcst right
VPRORD ymm1 {k1}{z},
AVX512F) OR
by imm8, store result using writemask k1.
ymm2/m256/m32bcst, imm8
AVX10.1
EVEX.256.66.0F38.W1 14 /r
B
V/V
(AVX512VL AND
Rotate quadwords in ymm2 right by count in the
VPRORVQ ymm1 {k1}{z}, ymm2,
AVX512F) OR
corresponding element of ymm3/m256/m64bcst,
ymm3/m256/m64bcst
AVX10.1
store result using writemask k1.
EVEX.256.66.0F.W1 72 /0 ib
A
V/V
(AVX512VL AND
Rotate quadwords in ymm2/m256/m64bcst right
VPRORQ ymm1 {k1}{z},
AVX512F) OR
by imm8, store result using writemask k1.
ymm2/m256/m64bcst, imm8
AVX10.1
EVEX.512.66.0F38.W0 14 /r
B
V/V
AVX512F
Rotate doublewords in zmm2 right by count in the
VPRORVD zmm1 {k1}{z}, zmm2,
OR AVX10.11
corresponding element of zmm3/m512/m32bcst,
zmm3/m512/m32bcst
store result using writemask k1.
EVEX.512.66.0F.W0 72 /0 ib
A
V/V
AVX512F
Rotate doublewords in zmm2/m512/m32bcst right
VPRORD zmm1 {k1}{z},
OR AVX10.1
by imm8, store result using writemask k1.
zmm2/m512/m32bcst, imm8
EVEX.512.66.0F38.W1 14 /r
B
V/V
AVX512F
Rotate quadwords in zmm2 right by count in the
VPRORVQ zmm1 {k1}{z}, zmm2,
OR AVX10.1
corresponding element of zmm3/m512/m64bcst,
zmm3/m512/m64bcst
store result using writemask k1.
EVEX.512.66.0F.W1 72 /0 ib
A
V/V
AVX512F
Rotate quadwords in zmm2/m512/m64bcst right
VPRORQ zmm1 {k1}{z},
OR AVX10.1
by imm8, store result using writemask k1.
zmm2/m512/m64bcst, imm8
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
VEX.vvvv (w)
ModRM:r/m (R)
imm8
N/A
B
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
VPRORD/VPRORVD/VPRORQ/VPRORVQ-Bit Rotate Right
Vol. 2C
5-614
Description
Rotates the bits in the individual data elements (doublewords, or quadword) in the first source operand to the right
by the number of bits specified in the count operand. If the value specified by the count operand is greater than 31
(for doublewords), or 63 (for a quadword), then the count operand modulo the data size (32 or 64) is used.
EVEX.128 encoded version: The destination operand is a XMM register. The source operand is a XMM register or a
memory location (for immediate form). The count operand can come either from an XMM register or a memory
location or an 8-bit immediate. Bits (MAXVL-1:128) of the corresponding ZMM register are zeroed.
EVEX.256 encoded version: The destination operand is a YMM register. The source operand is a YMM register or a
memory location (for immediate form). The count operand can come either from an XMM register or a memory
location or an 8-bit immediate. Bits (MAXVL-1:256) of the corresponding ZMM register are zeroed.
EVEX.512 encoded version: The destination operand is a ZMM register updated according to the writemask. For the
count operand in immediate form, the source operand can be a ZMM register, a 512-bit memory location or a 512-
bit vector broadcasted from a 32/64-bit memory location, the count operand is an 8-bit immediate. For the count
operand in variable form, the first source operand (the second operand) is a ZMM register and the counter operand
(the third operand) is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32/64-bit
memory location.
Operation
RIGHT_ROTATE_DWORDS(SRC, COUNT_SRC)
COUNT := COUNT_SRC modulo 32;
DEST[31:0] := (SRC >> COUNT) | (SRC << (32 - COUNT));
RIGHT_ROTATE_QWORDS(SRC, COUNT_SRC)
COUNT := COUNT_SRC modulo 64;
DEST[63:0] := (SRC >> COUNT) | (SRC << (64 - COUNT));
VPRORD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC1 *is memory*)
THEN DEST[i+31:i] := RIGHT_ROTATE_DWORDS( SRC1[31:0], imm8)
ELSE DEST[i+31:i] := RIGHT_ROTATE_DWORDS(SRC1[i+31:i], imm8)
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPRORVD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+31:i] := RIGHT_ROTATE_DWORDS(SRC1[i+31:i], SRC2[31:0])
ELSE DEST[i+31:i] := RIGHT_ROTATE_DWORDS(SRC1[i+31:i], SRC2[i+31:i])
FI;
VPRORD/VPRORVD/VPRORQ/VPRORVQ-Bit Rotate Right
Vol. 2C
5-615
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPRORQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC1 *is memory*)
THEN DEST[i+63:i] := RIGHT_ROTATE_QWORDS(SRC1[63:0], imm8)
ELSE DEST[i+63:i] := RIGHT_ROTATE_QWORDS(SRC1[i+63:i], imm8])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPRORVQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+63:i] := RIGHT_ROTATE_QWORDS(SRC1[i+63:i], SRC2[63:0])
ELSE DEST[i+63:i] := RIGHT_ROTATE_QWORDS(SRC1[i+63:i], SRC2[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPRORD/VPRORVD/VPRORQ/VPRORVQ-Bit Rotate Right
Vol. 2C
5-616
Intel C/C++ Compiler Intrinsic Equivalent
VPRORD __m512i _mm512_ror_epi32(__m512i a, int imm);
VPRORD __m512i _mm512_mask_ror_epi32(__m512i a, __mmask16 k, __m512i b, int imm);
VPRORD __m512i _mm512_maskz_ror_epi32( __mmask16 k, __m512i a, int imm);
VPRORD __m256i _mm256_ror_epi32(__m256i a, int imm);
VPRORD __m256i _mm256_mask_ror_epi32(__m256i a, __mmask8 k, __m256i b, int imm);
VPRORD __m256i _mm256_maskz_ror_epi32( __mmask8 k, __m256i a, int imm);
VPRORD __m128i _mm_ror_epi32(__m128i a, int imm);
VPRORD __m128i _mm_mask_ror_epi32(__m128i a, __mmask8 k, __m128i b, int imm);
VPRORD __m128i _mm_maskz_ror_epi32( __mmask8 k, __m128i a, int imm);
VPRORQ __m512i _mm512_ror_epi64(__m512i a, int imm);
VPRORQ __m512i _mm512_mask_ror_epi64(__m512i a, __mmask8 k, __m512i b, int imm);
VPRORQ __m512i _mm512_maskz_ror_epi64(__mmask8 k, __m512i a, int imm);
VPRORQ __m256i _mm256_ror_epi64(__m256i a, int imm);
VPRORQ __m256i _mm256_mask_ror_epi64(__m256i a, __mmask8 k, __m256i b, int imm);
VPRORQ __m256i _mm256_maskz_ror_epi64( __mmask8 k, __m256i a, int imm);
VPRORQ __m128i _mm_ror_epi64(__m128i a, int imm);
VPRORQ __m128i _mm_mask_ror_epi64(__m128i a, __mmask8 k, __m128i b, int imm);
VPRORQ __m128i _mm_maskz_ror_epi64( __mmask8 k, __m128i a, int imm);
VPRORVD __m512i _mm512_rorv_epi32(__m512i a, __m512i cnt);
VPRORVD __m512i _mm512_mask_rorv_epi32(__m512i a, __mmask16 k, __m512i b, __m512i cnt);
VPRORVD __m512i _mm512_maskz_rorv_epi32(__mmask16 k, __m512i a, __m512i cnt);
VPRORVD __m256i _mm256_rorv_epi32(__m256i a, __m256i cnt);
VPRORVD __m256i _mm256_mask_rorv_epi32(__m256i a, __mmask8 k, __m256i b, __m256i cnt);
VPRORVD __m256i _mm256_maskz_rorv_epi32(__mmask8 k, __m256i a, __m256i cnt);
VPRORVD __m128i _mm_rorv_epi32(__m128i a, __m128i cnt);
VPRORVD __m128i _mm_mask_rorv_epi32(__m128i a, __mmask8 k, __m128i b, __m128i cnt);
VPRORVD __m128i _mm_maskz_rorv_epi32(__mmask8 k, __m128i a, __m128i cnt);
VPRORVQ __m512i _mm512_rorv_epi64(__m512i a, __m512i cnt);
VPRORVQ __m512i _mm512_mask_rorv_epi64(__m512i a, __mmask8 k, __m512i b, __m512i cnt);
VPRORVQ __m512i _mm512_maskz_rorv_epi64( __mmask8 k, __m512i a, __m512i cnt);
VPRORVQ __m256i _mm256_rorv_epi64(__m256i a, __m256i cnt);
VPRORVQ __m256i _mm256_mask_rorv_epi64(__m256i a, __mmask8 k, __m256i b, __m256i cnt);
VPRORVQ __m256i _mm256_maskz_rorv_epi64(__mmask8 k, __m256i a, __m256i cnt);
VPRORVQ __m128i _mm_rorv_epi64(__m128i a, __m128i cnt);
VPRORVQ __m128i _mm_mask_rorv_epi64(__m128i a, __mmask8 k, __m128i b, __m128i cnt);
VPRORVQ __m128i _mm_maskz_rorv_epi64(__mmask8 k, __m128i a, __m128i cnt);
SIMD Floating-Point Exceptions
None.
Other Exceptions
EVEX-encoded instruction, see Table 2-51, “Type E4 Class Exception Conditions.”
VPRORD/VPRORVD/VPRORQ/VPRORVQ-Bit Rotate Right
Vol. 2C
5-617
VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ-Scatter Packed Dword, Packed
Qword with Signed Dword, Signed Qword Indices
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.66.0F38.W0 A0 /vsib
A
V/V
(AVX512VL AND
Using signed dword indices, scatter dword values
VPSCATTERDD vm32x {k1}, xmm1
AVX512F) OR
to memory using writemask k1.
AVX10.1
EVEX.256.66.0F38.W0 A0 /vsib
A
V/V
(AVX512VL AND
Using signed dword indices, scatter dword values
VPSCATTERDD vm32y {k1}, ymm1
AVX512F) OR
to memory using writemask k1.
AVX10.1
EVEX.512.66.0F38.W0 A0 /vsib
A
V/V
AVX512F
Using signed dword indices, scatter dword values
VPSCATTERDD vm32z {k1}, zmm1
OR AVX10.1
to memory using writemask k1.
EVEX.128.66.0F38.W1 A0 /vsib
A
V/V
(AVX512VL AND
Using signed dword indices, scatter qword values
VPSCATTERDQ vm32x {k1}, xmm1
AVX512F) OR
to memory using writemask k1.
AVX10.1
EVEX.256.66.0F38.W1 A0 /vsib
A
V/V
(AVX512VL AND
Using signed dword indices, scatter qword values
VPSCATTERDQ vm32x {k1}, ymm1
AVX512F) OR
to memory using writemask k1.
AVX10.1
EVEX.512.66.0F38.W1 A0 /vsib
A
V/V
AVX512F
Using signed dword indices, scatter qword values
VPSCATTERDQ vm32y {k1}, zmm1
OR AVX10.1
to memory using writemask k1.
EVEX.128.66.0F38.W0 A1 /vsib
A
V/V
(AVX512VL AND
Using signed qword indices, scatter dword values
VPSCATTERQD vm64x {k1}, xmm1
AVX512F) OR
to memory using writemask k1.
AVX10.1
EVEX.256.66.0F38.W0 A1 /vsib
A
V/V
(AVX512VL AND
Using signed qword indices, scatter dword values
VPSCATTERQD vm64y {k1}, xmm1
AVX512F) OR
to memory using writemask k1.
AVX10.1
EVEX.512.66.0F38.W0 A1 /vsib
A
V/V
AVX512F
Using signed qword indices, scatter dword values
VPSCATTERQD vm64z {k1}, ymm1
OR AVX10.1
to memory using writemask k1.
EVEX.128.66.0F38.W1 A1 /vsib
A
V/V
(AVX512VL AND
Using signed qword indices, scatter qword values
VPSCATTERQQ vm64x {k1}, xmm1
AVX512F) OR
to memory using writemask k1.
AVX10.1
EVEX.256.66.0F38.W1 A1 /vsib
A
V/V
(AVX512VL AND
Using signed qword indices, scatter qword values
VPSCATTERQQ vm64y {k1}, ymm1
AVX512F) OR
to memory using writemask k1.
AVX10.1
EVEX.512.66.0F38.W1 A1 /vsib
A
V/V
AVX512F
Using signed qword indices, scatter qword values
VPSCATTERQQ vm64z {k1}, zmm1
OR AVX10.1
to memory using writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
BaseReg (R): VSIB:base,
A
Tuple1 Scalar
ModRM:reg (r)
N/A
N/A
VectorReg(R): VSIB:index
Description
Stores up to 16 elements (8 elements for qword indices) in doubleword vector or 8 elements in quadword vector to
the memory locations pointed by base address BASE_ADDR and index vector VINDEX, with scale SCALE. The
elements are specified via the VSIB (i.e., the index register is a vector register, holding packed indices). Elements
will only be stored if their corresponding mask bit is one. The entire mask register will be set to zero by this instruc-
tion unless it triggers an exception.
VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ-Scatter Packed Dword, Packed Qword with Signed Dword, Signed
Vol. 2C
5-618
This instruction can be suspended by an exception if at least one element is already scattered (i.e., if the exception
is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination
register and the mask register are partially updated. If any traps or interrupts are pending from already scattered
elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction
breakpoint is not re-triggered when the instruction is continued.
Note that:
• Only writes to overlapping vector indices are guaranteed to be ordered with respect to each other (from LSB to
MSB of the source registers). Note that this also include partially overlapping vector indices. Writes that are not
overlapped may happen in any order. Memory ordering with other instructions follows the Intel-64 memory
ordering model. Note that this does not account for non-overlapping indices that map into the same physical
address locations.
• If two or more destination indices completely overlap, the “earlier” write(s) may be skipped.
• Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
elements closer to the LSB of the destination ZMM will be completed (and non-faulting). Individual elements
closer to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered
in the conventional order.
• Elements may be scattered in any order, but faults must be delivered in a right-to left order; thus, elements to
the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
instruction is repeatable - given the same input values and architectural state, the same set of elements to the
left of the faulting one will be gathered.
• This instruction does not perform AC checks, and so will never deliver an AC fault.
• Not valid with 16-bit effective addresses. Will deliver a #UD fault.
• If this instruction overwrites itself and then takes a fault, only a subset of elements may be completed before
the fault is delivered (as described above). If the fault handler completes and attempts to re-execute this
instruction, the new instruction will be executed, and the scatter will not complete.
Note that the presence of VSIB byte is enforced in this instruction. Hence, the instruction will #UD fault if
ModRM.rm is different than 100b.
This instruction has special disp8*N and alignment rules. N is considered to be the size of a single vector element.
The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-bit
mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address bits are
ignored.
The instruction will #UD fault if the k0 mask register is specified.
The instruction will #UD fault if EVEX.Z = 1.
Operation
BASE_ADDR stands for the memory operand base address (a GPR); may not exist
VINDEX stands for the memory operand vector of indices (a ZMM register)
SCALE stands for the memory operand scalar (1, 2, 4 or 8)
DISP is the optional 1 or 4 byte displacement
VPSCATTERDD (EVEX encoded versions)
(KL, VL)= (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN MEM[BASE_ADDR +SignExtend(VINDEX[i+31:i]) * SCALE + DISP] := SRC[i+31:i]
k1[j] := 0
FI;
ENDFOR
k1[MAX_KL-1:KL] := 0
VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ-Scatter Packed Dword, Packed Qword with Signed Dword, Signed
Vol. 2C
5-619
VPSCATTERDQ (EVEX encoded versions)
(KL, VL)= (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
k := j * 32
IF k1[j] OR *no writemask*
THEN MEM[BASE_ADDR +SignExtend(VINDEX[k+31:k]) * SCALE + DISP] := SRC[i+63:i]
k1[j] := 0
FI;
ENDFOR
k1[MAX_KL-1:KL] := 0
VPSCATTERQD (EVEX encoded versions)
(KL, VL)= (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 32
k := j * 64
IF k1[j] OR *no writemask*
THEN MEM[BASE_ADDR + (VINDEX[k+63:k]) * SCALE + DISP] := SRC[i+31:i]
k1[j] := 0
FI;
ENDFOR
k1[MAX_KL-1:KL] := 0
VPSCATTERQQ (EVEX encoded versions)
(KL, VL)= (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN MEM[BASE_ADDR + (VINDEX[j+63:j]) * SCALE + DISP] := SRC[i+63:i]
FI;
ENDFOR
k1[MAX_KL-1:KL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPSCATTERDD void _mm512_i32scatter_epi32(void * base, __m512i vdx, __m512i a, int scale);
VPSCATTERDD void _mm256_i32scatter_epi32(void * base, __m256i vdx, __m256i a, int scale);
VPSCATTERDD void _mm_i32scatter_epi32(void * base, __m128i vdx, __m128i a, int scale);
VPSCATTERDD void _mm512_mask_i32scatter_epi32(void * base, __mmask16 k, __m512i vdx, __m512i a, int scale);
VPSCATTERDD void _mm256_mask_i32scatter_epi32(void * base, __mmask8 k, __m256i vdx, __m256i a, int scale);
VPSCATTERDD void _mm_mask_i32scatter_epi32(void * base, __mmask8 k, __m128i vdx, __m128i a, int scale);
VPSCATTERDQ void _mm512_i32scatter_epi64(void * base, __m256i vdx, __m512i a, int scale);
VPSCATTERDQ void _mm256_i32scatter_epi64(void * base, __m128i vdx, __m256i a, int scale);
VPSCATTERDQ void _mm_i32scatter_epi64(void * base, __m128i vdx, __m128i a, int scale);
VPSCATTERDQ void _mm512_mask_i32scatter_epi64(void * base, __mmask8 k, __m256i vdx, __m512i a, int scale);
VPSCATTERDQ void _mm256_mask_i32scatter_epi64(void * base, __mmask8 k, __m128i vdx, __m256i a, int scale);
VPSCATTERDQ void _mm_mask_i32scatter_epi64(void * base, __mmask8 k, __m128i vdx, __m128i a, int scale);
VPSCATTERQD void _mm512_i64scatter_epi32(void * base, __m512i vdx, __m256i a, int scale);
VPSCATTERQD void _mm256_i64scatter_epi32(void * base, __m256i vdx, __m128i a, int scale);
VPSCATTERQD void _mm_i64scatter_epi32(void * base, __m128i vdx, __m128i a, int scale);
VPSCATTERQD void _mm512_mask_i64scatter_epi32(void * base, __mmask8 k, __m512i vdx, __m256i a, int scale);
VPSCATTERQD void _mm256_mask_i64scatter_epi32(void * base, __mmask8 k, __m256i vdx, __m128i a, int scale);
VPSCATTERQD void _mm_mask_i64scatter_epi32(void * base, __mmask8 k, __m128i vdx, __m128i a, int scale);
VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ-Scatter Packed Dword, Packed Qword with Signed Dword, Signed
Vol. 2C
5-620
VPSCATTERQQ void _mm512_i64scatter_epi64(void * base, __m512i vdx, __m512i a, int scale);
VPSCATTERQQ void _mm256_i64scatter_epi64(void * base, __m256i vdx, __m256i a, int scale);
VPSCATTERQQ void _mm_i64scatter_epi64(void * base, __m128i vdx, __m128i a, int scale);
VPSCATTERQQ void _mm512_mask_i64scatter_epi64(void * base, __mmask8 k, __m512i vdx, __m512i a, int scale);
VPSCATTERQQ void _mm256_mask_i64scatter_epi64(void * base, __mmask8 k, __m256i vdx, __m256i a, int scale);
VPSCATTERQQ void _mm_mask_i64scatter_epi64(void * base, __mmask8 k, __m128i vdx, __m128i a, int scale);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-63, “Type E12 Class Exception Conditions.”
VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ-Scatter Packed Dword, Packed Qword with Signed Dword, Signed
Vol. 2C
5-621
VPSHLD-Concatenate and Shift Packed Data Left Logical
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.66.0F3A.W1 70 /r /ib
A
V/V
(AVX512_VBMI2
Concatenate destination and source operands,
VPSHLDW xmm1{k1}{z}, xmm2,
AND AVX512VL)
extract result shifted to the left by constant
xmm3/m128, imm8
OR AVX10.1
value in imm8 into xmm1.
EVEX.256.66.0F3A.W1 70 /r /ib
A
V/V
(AVX512_VBMI2
Concatenate destination and source operands,
VPSHLDW ymm1{k1}{z}, ymm2,
AND AVX512VL)
extract result shifted to the left by constant
ymm3/m256, imm8
OR AVX10.1
value in imm8 into ymm1.
EVEX.512.66.0F3A.W1 70 /r /ib
A
V/V
AVX512_VBMI2
Concatenate destination and source operands,
VPSHLDW zmm1{k1}{z}, zmm2,
OR AVX10.1
extract result shifted to the left by constant
zmm3/m512, imm8
value in imm8 into zmm1.
EVEX.128.66.0F3A.W0 71 /r /ib
B
V/V
(AVX512_VBMI2
Concatenate destination and source operands,
VPSHLDD xmm1{k1}{z}, xmm2,
AND AVX512VL)
extract result shifted to the left by constant
xmm3/m128/m32bcst, imm8
OR AVX10.1
value in imm8 into xmm1.
EVEX.256.66.0F3A.W0 71 /r /ib
B
V/V
(AVX512_VBMI2
Concatenate destination and source operands,
VPSHLDD ymm1{k1}{z}, ymm2,
AND AVX512VL)
extract result shifted to the left by constant
ymm3/m256/m32bcst, imm8
OR AVX10.1
value in imm8 into ymm1.
EVEX.512.66.0F3A.W0 71 /r /ib
B
V/V
AVX512_VBMI2
Concatenate destination and source operands,
VPSHLDD zmm1{k1}{z}, zmm2,
OR AVX10.1
extract result shifted to the left by constant
zmm3/m512/m32bcst, imm8
value in imm8 into zmm1.
EVEX.128.66.0F3A.W1 71 /r /ib
B
V/V
(AVX512_VBMI2
Concatenate destination and source operands,
VPSHLDQ xmm1{k1}{z}, xmm2,
AND AVX512VL)
extract result shifted to the left by constant
xmm3/m128/m64bcst, imm8
OR AVX10.1
value in imm8 into xmm1.
EVEX.256.66.0F3A.W1 71 /r /ib
B
V/V
(AVX512_VBMI2
Concatenate destination and source operands,
VPSHLDQ ymm1{k1}{z}, ymm2,
AND AVX512VL)
extract result shifted to the left by constant
ymm3/m256/m64bcst, imm8
OR AVX10.1
value in imm8 into ymm1.
EVEX.512.66.0F3A.W1 71 /r /ib
B
V/V
AVX512_VBMI2
Concatenate destination and source operands,
VPSHLDQ zmm1{k1}{z}, zmm2,
OR AVX10.1
extract result shifted to the left by constant
zmm3/m512/m64bcst, imm8
value in imm8 into zmm1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full Mem
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
imm8 (r)
B
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
imm8 (r)
Description
Concatenate packed data, extract result shifted to the left by constant value.
This instruction supports memory fault suppression.
VPSHLD-Concatenate and Shift Packed Data Left Logical
Vol. 2C
5-622
Operation
VPSHLDW DEST, SRC2, SRC3, imm8
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1:
IF MaskBit(j) OR *no writemask*:
tmp := concat(SRC2.word[j], SRC3.word[j]) << (imm8 & 15)
DEST.word[j] := tmp.word[1]
ELSE IF *zeroing*:
DEST.word[j] := 0
*ELSE DEST.word[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0
VPSHLDD DEST, SRC2, SRC3, imm8
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1:
IF SRC3 is broadcast memop:
tsrc3 := SRC3.dword[0]
ELSE:
tsrc3 := SRC3.dword[j]
IF MaskBit(j) OR *no writemask*:
tmp := concat(SRC2.dword[j], tsrc3) << (imm8 & 31)
DEST.dword[j] := tmp.dword[1]
ELSE IF *zeroing*:
DEST.dword[j] := 0
*ELSE DEST.dword[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0
VPSHLDQ DEST, SRC2, SRC3, imm8
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1:
IF SRC3 is broadcast memop:
tsrc3 := SRC3.qword[0]
ELSE:
tsrc3 := SRC3.qword[j]
IF MaskBit(j) OR *no writemask*:
tmp := concat(SRC2.qword[j], tsrc3) << (imm8 & 63)
DEST.qword[j] := tmp.qword[1]
ELSE IF *zeroing*:
DEST.qword[j] := 0
*ELSE DEST.qword[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0
VPSHLD-Concatenate and Shift Packed Data Left Logical
Vol. 2C
5-623
Intel C/C++ Compiler Intrinsic Equivalent
VPSHLDD __m128i _mm_shldi_epi32(__m128i, __m128i, int);
VPSHLDD __m128i _mm_mask_shldi_epi32(__m128i, __mmask8, __m128i, __m128i, int);
VPSHLDD __m128i _mm_maskz_shldi_epi32(__mmask8, __m128i, __m128i, int);
VPSHLDD __m256i _mm256_shldi_epi32(__m256i, __m256i, int);
VPSHLDD __m256i _mm256_mask_shldi_epi32(__m256i, __mmask8, __m256i, __m256i, int);
VPSHLDD __m256i _mm256_maskz_shldi_epi32(__mmask8, __m256i, __m256i, int);
VPSHLDD __m512i _mm512_shldi_epi32(__m512i, __m512i, int);
VPSHLDD __m512i _mm512_mask_shldi_epi32(__m512i, __mmask16, __m512i, __m512i, int);
VPSHLDD __m512i _mm512_maskz_shldi_epi32(__mmask16, __m512i, __m512i, int);
VPSHLDQ __m128i _mm_shldi_epi64(__m128i, __m128i, int);
VPSHLDQ __m128i _mm_mask_shldi_epi64(__m128i, __mmask8, __m128i, __m128i, int);
VPSHLDQ __m128i _mm_maskz_shldi_epi64(__mmask8, __m128i, __m128i, int);
VPSHLDQ __m256i _mm256_shldi_epi64(__m256i, __m256i, int);
VPSHLDQ __m256i _mm256_mask_shldi_epi64(__m256i, __mmask8, __m256i, __m256i, int);
VPSHLDQ __m256i _mm256_maskz_shldi_epi64(__mmask8, __m256i, __m256i, int);
VPSHLDQ __m512i _mm512_shldi_epi64(__m512i, __m512i, int);
VPSHLDQ __m512i _mm512_mask_shldi_epi64(__m512i, __mmask8, __m512i, __m512i, int);
VPSHLDQ __m512i _mm512_maskz_shldi_epi64(__mmask8, __m512i, __m512i, int);
VPSHLDW __m128i _mm_shldi_epi16(__m128i, __m128i, int);
VPSHLDW __m128i _mm_mask_shldi_epi16(__m128i, __mmask8, __m128i, __m128i, int);
VPSHLDW __m128i _mm_maskz_shldi_epi16(__mmask8, __m128i, __m128i, int);
VPSHLDW __m256i _mm256_shldi_epi16(__m256i, __m256i, int);
VPSHLDW __m256i _mm256_mask_shldi_epi16(__m256i, __mmask16, __m256i, __m256i, int);
VPSHLDW __m256i _mm256_maskz_shldi_epi16(__mmask16, __m256i, __m256i, int);
VPSHLDW __m512i _mm512_shldi_epi16(__m512i, __m512i, int);
VPSHLDW __m512i _mm512_mask_shldi_epi16(__m512i, __mmask32, __m512i, __m512i, int);
VPSHLDW __m512i _mm512_maskz_shldi_epi16(__mmask32, __m512i, __m512i, int);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-51, “Type E4 Class Exception Conditions.”
VPSHLD-Concatenate and Shift Packed Data Left Logical
Vol. 2C
5-624
VPSHLDV-Concatenate and Variable Shift Packed Data Left Logical
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.66.0F38.W1 70 /r
A
V/V
(AVX512_VBMI2
Concatenate xmm1 and xmm2, extract result
VPSHLDVW xmm1{k1}{z}, xmm2,
AND AVX512VL)
shifted to the left by value in xmm3/m128 into
xmm3/m128
OR AVX10.1
xmm1.
EVEX.256.66.0F38.W1 70 /r
A
V/V
(AVX512_VBMI2
Concatenate ymm1 and ymm2, extract result
VPSHLDVW ymm1{k1}{z}, ymm2,
AND AVX512VL)
shifted to the left by value in xmm3/m256 into
ymm3/m256
OR AVX10.1
ymm1.
EVEX.512.66.0F38.W1 70 /r
A
V/V
AVX512_VBMI2
Concatenate zmm1 and zmm2, extract result
VPSHLDVW zmm1{k1}{z}, zmm2,
OR AVX10.1
shifted to the left by value in zmm3/m512 into
zmm3/m512
zmm1.
EVEX.128.66.0F38.W0 71 /r
B
V/V
(AVX512_VBMI2
Concatenate xmm1 and xmm2, extract result
VPSHLDVD xmm1{k1}{z}, xmm2,
AND AVX512VL)
shifted to the left by value in xmm3/m128 into
xmm3/m128/m32bcst
OR AVX10.1
xmm1.
EVEX.256.66.0F38.W0 71 /r
B
V/V
(AVX512_VBMI2
Concatenate ymm1 and ymm2, extract result
VPSHLDVD ymm1{k1}{z}, ymm2,
AND AVX512VL)
shifted to the left by value in xmm3/m256 into
ymm3/m256/m32bcst
OR AVX10.1
ymm1.
EVEX.512.66.0F38.W0 71 /r
B
V/V
AVX512_VBMI2
Concatenate zmm1 and zmm2, extract result
VPSHLDVD zmm1{k1}{z}, zmm2,
OR AVX10.1
shifted to the left by value in zmm3/m512 into
zmm3/m512/m32bcst
zmm1.
EVEX.128.66.0F38.W1 71 /r
B
V/V
(AVX512_VBMI2
Concatenate xmm1 and xmm2, extract result
VPSHLDVQ xmm1{k1}{z}, xmm2,
AND AVX512VL)
shifted to the left by value in xmm3/m128 into
xmm3/m128/m64bcst
OR AVX10.1
xmm1.
EVEX.256.66.0F38.W1 71 /r
B
V/V
(AVX512_VBMI2
Concatenate ymm1 and ymm2, extract result
VPSHLDVQ ymm1{k1}{z}, ymm2,
AND AVX512VL)
shifted to the left by value in xmm3/m256 into
ymm3/m256/m64bcst
OR AVX10.1
ymm1.
EVEX.512.66.0F38.W1 71 /r
B
V/V
AVX512_VBMI2
Concatenate zmm1 and zmm2, extract result
VPSHLDVQ zmm1{k1}{z}, zmm2,
OR AVX10.1
shifted to the left by value in zmm3/m512 into
zmm3/m512/m64bcst
zmm1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full Mem
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
B
Full
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Concatenate packed data, extract result shifted to the left by variable value.
This instruction supports memory fault suppression.
VPSHLDV-Concatenate and Variable Shift Packed Data Left Logical
Vol. 2C
5-625
Operation
FUNCTION concat(a,b):
IF words:
d.word[1] := a
d.word[0] := b
return d
ELSE IF dwords:
q.dword[1] := a
q.dword[0] := b
return q
ELSE IF qwords:
o.qword[1] := a
o.qword[0] := b
return o
VPSHLDVW DEST, SRC2, SRC3
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1:
IF MaskBit(j) OR *no writemask*:
tmp := concat(DEST.word[j], SRC2.word[j]) << (SRC3.word[j] & 15)
DEST.word[j] := tmp.word[1]
ELSE IF *zeroing*:
DEST.word[j] := 0
*ELSE DEST.word[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0
VPSHLDVD DEST, SRC2, SRC3
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1:
IF SRC3 is broadcast memop:
tsrc3 := SRC3.dword[0]
ELSE:
tsrc3 := SRC3.dword[j]
IF MaskBit(j) OR *no writemask*:
tmp := concat(DEST.dword[j], SRC2.dword[j]) << (tsrc3 & 31)
DEST.dword[j] := tmp.dword[1]
ELSE IF *zeroing*:
DEST.dword[j] := 0
*ELSE DEST.dword[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0
VPSHLDV-Concatenate and Variable Shift Packed Data Left Logical
Vol. 2C
5-626
VPSHLDVQ DEST, SRC2, SRC3
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1:
IF SRC3 is broadcast memop:
tsrc3 := SRC3.qword[0]
ELSE:
tsrc3 := SRC3.qword[j]
IF MaskBit(j) OR *no writemask*:
tmp := concat(DEST.qword[j], SRC2.qword[j]) << (tsrc3 & 63)
DEST.qword[j] := tmp.qword[1]
ELSE IF *zeroing*:
DEST.qword[j] := 0
*ELSE DEST.qword[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPSHLDVW __m128i _mm_shldv_epi16(__m128i, __m128i, __m128i);
VPSHLDVW __m128i _mm_mask_shldv_epi16(__m128i, __mmask8, __m128i, __m128i);
VPSHLDVW __m128i _mm_maskz_shldv_epi16(__mmask8, __m128i, __m128i, __m128i);
VPSHLDVW __m256i _mm256_shldv_epi16(__m256i, __m256i, __m256i);
VPSHLDVW __m256i _mm256_mask_shldv_epi16(__m256i, __mmask16, __m256i, __m256i);
VPSHLDVW __m256i _mm256_maskz_shldv_epi16(__mmask16, __m256i, __m256i, __m256i);
VPSHLDVQ __m512i _mm512_shldv_epi64(__m512i, __m512i, __m512i);
VPSHLDVQ __m512i _mm512_mask_shldv_epi64(__m512i, __mmask8, __m512i, __m512i);
VPSHLDVQ __m512i _mm512_maskz_shldv_epi64(__mmask8, __m512i, __m512i, __m512i);
VPSHLDVW __m128i _mm_shldv_epi16(__m128i, __m128i, __m128i);
VPSHLDVW __m128i _mm_mask_shldv_epi16(__m128i, __mmask8, __m128i, __m128i);
VPSHLDVW __m128i _mm_maskz_shldv_epi16(__mmask8, __m128i, __m128i, __m128i);
VPSHLDVW __m256i _mm256_shldv_epi16(__m256i, __m256i, __m256i);
VPSHLDVW __m256i _mm256_mask_shldv_epi16(__m256i, __mmask16, __m256i, __m256i);
VPSHLDVW __m256i _mm256_maskz_shldv_epi16(__mmask16, __m256i, __m256i, __m256i);
VPSHLDVW __m512i _mm512_shldv_epi16(__m512i, __m512i, __m512i);
VPSHLDVW __m512i _mm512_mask_shldv_epi16(__m512i, __mmask32, __m512i, __m512i);
VPSHLDVW __m512i _mm512_maskz_shldv_epi16(__mmask32, __m512i, __m512i, __m512i);
VPSHLDVD __m128i _mm_shldv_epi32(__m128i, __m128i, __m128i);
VPSHLDVD __m128i _mm_mask_shldv_epi32(__m128i, __mmask8, __m128i, __m128i);
VPSHLDVD __m128i _mm_maskz_shldv_epi32(__mmask8, __m128i, __m128i, __m128i);
VPSHLDVD __m256i _mm256_shldv_epi32(__m256i, __m256i, __m256i);
VPSHLDVD __m256i _mm256_mask_shldv_epi32(__m256i, __mmask8, __m256i, __m256i);
VPSHLDVD __m256i _mm256_maskz_shldv_epi32(__mmask8, __m256i, __m256i, __m256i);
VPSHLDVD __m512i _mm512_shldv_epi32(__m512i, __m512i, __m512i);
VPSHLDVD __m512i _mm512_mask_shldv_epi32(__m512i, __mmask16, __m512i, __m512i);
VPSHLDVD __m512i _mm512_maskz_shldv_epi32(__mmask16, __m512i, __m512i, __m512i);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-51, “Type E4 Class Exception Conditions.”
VPSHLDV-Concatenate and Variable Shift Packed Data Left Logical
Vol. 2C
5-627
VPSHRD-Concatenate and Shift Packed Data Right Logical
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.66.0F3A.W1 72 /r /ib
A
V/V
(AVX512_VBMI2
Concatenate destination and source operands,
VPSHRDW xmm1{k1}{z}, xmm2,
AND AVX512VL)
extract result shifted to the right by constant
xmm3/m128, imm8
OR AVX10.1
value in imm8 into xmm1.
EVEX.256.66.0F3A.W1 72 /r /ib
A
V/V
(AVX512_VBMI2
Concatenate destination and source operands,
VPSHRDW ymm1{k1}{z}, ymm2,
AND AVX512VL)
extract result shifted to the right by constant
ymm3/m256, imm8
OR AVX10.1
value in imm8 into ymm1.
EVEX.512.66.0F3A.W1 72 /r /ib
A
V/V
AVX512_VBMI2
Concatenate destination and source operands,
VPSHRDW zmm1{k1}{z}, zmm2,
OR AVX10.1
extract result shifted to the right by constant
zmm3/m512, imm8
value in imm8 into zmm1.
EVEX.128.66.0F3A.W0 73 /r /ib
B
V/V
(AVX512_VBMI2
Concatenate destination and source operands,
VPSHRDD xmm1{k1}{z}, xmm2,
AND AVX512VL)
extract result shifted to the right by constant
xmm3/m128/m32bcst, imm8
OR AVX10.1
value in imm8 into xmm1.
EVEX.256.66.0F3A.W0 73 /r /ib
B
V/V
(AVX512_VBMI2
Concatenate destination and source operands,
VPSHRDD ymm1{k1}{z}, ymm2,
AND AVX512VL)
extract result shifted to the right by constant
ymm3/m256/m32bcst, imm8
OR AVX10.1
value in imm8 into ymm1.
EVEX.512.66.0F3A.W0 73 /r /ib
B
V/V
AVX512_VBMI2
Concatenate destination and source operands,
VPSHRDD zmm1{k1}{z}, zmm2,
OR AVX10.1
extract result shifted to the right by constant
zmm3/m512/m32bcst, imm8
value in imm8 into zmm1.
EVEX.128.66.0F3A.W1 73 /r /ib
B
V/V
(AVX512_VBMI2
Concatenate destination and source operands,
VPSHRDQ xmm1{k1}{z}, xmm2,
AND AVX512VL)
extract result shifted to the right by constant
xmm3/m128/m64bcst, imm8
OR AVX10.1
value in imm8 into xmm1.
EVEX.256.66.0F3A.W1 73 /r /ib
B
V/V
(AVX512_VBMI2
Concatenate destination and source operands,
VPSHRDQ ymm1{k1}{z}, ymm2,
AND AVX512VL)
extract result shifted to the right by constant
ymm3/m256/m64bcst, imm8
OR AVX10.1
value in imm8 into ymm1.
EVEX.512.66.0F3A.W1 73 /r /ib
B
V/V
AVX512_VBMI2
Concatenate destination and source operands,
VPSHRDQ zmm1{k1}{z}, zmm2,
OR AVX10.1
extract result shifted to the right by constant
zmm3/m512/m64bcst, imm8
value in imm8 into zmm1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full Mem
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
imm8 (r)
B
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
imm8 (r)
Description
Concatenate packed data, extract result shifted to the right by constant value.
This instruction supports memory fault suppression.
VPSHRD-Concatenate and Shift Packed Data Right Logical
Vol. 2C
5-628
Operation
VPSHRDW DEST, SRC2, SRC3, imm8
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1:
IF MaskBit(j) OR *no writemask*:
DEST.word[j] := concat(SRC3.word[j], SRC2.word[j]) >> (imm8 & 15)
ELSE IF *zeroing*:
DEST.word[j] := 0
*ELSE DEST.word[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0
VPSHRDD DEST, SRC2, SRC3, imm8
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1:
IF SRC3 is broadcast memop:
tsrc3 := SRC3.dword[0]
ELSE:
tsrc3 := SRC3.dword[j]
IF MaskBit(j) OR *no writemask*:
DEST.dword[j] := concat(tsrc3, SRC2.dword[j]) >> (imm8 & 31)
ELSE IF *zeroing*:
DEST.dword[j] := 0
*ELSE DEST.dword[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0
VPSHRDQ DEST, SRC2, SRC3, imm8
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1:
IF SRC3 is broadcast memop:
tsrc3 := SRC3.qword[0]
ELSE:
tsrc3 := SRC3.qword[j]
IF MaskBit(j) OR *no writemask*:
DEST.qword[j] := concat(tsrc3, SRC2.qword[j]) >> (imm8 & 63)
ELSE IF *zeroing*:
DEST.qword[j] := 0
*ELSE DEST.qword[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0
VPSHRD-Concatenate and Shift Packed Data Right Logical
Vol. 2C
5-629
Intel C/C++ Compiler Intrinsic Equivalent
VPSHRDQ __m128i _mm_shrdi_epi64(__m128i, __m128i, int);
VPSHRDQ __m128i _mm_mask_shrdi_epi64(__m128i, __mmask8, __m128i, __m128i, int);
VPSHRDQ __m128i _mm_maskz_shrdi_epi64(__mmask8, __m128i, __m128i, int);
VPSHRDQ __m256i _mm256_shrdi_epi64(__m256i, __m256i, int);
VPSHRDQ __m256i _mm256_mask_shrdi_epi64(__m256i, __mmask8, __m256i, __m256i, int);
VPSHRDQ __m256i _mm256_maskz_shrdi_epi64(__mmask8, __m256i, __m256i, int);
VPSHRDQ __m512i _mm512_shrdi_epi64(__m512i, __m512i, int);
VPSHRDQ __m512i _mm512_mask_shrdi_epi64(__m512i, __mmask8, __m512i, __m512i, int);
VPSHRDQ __m512i _mm512_maskz_shrdi_epi64(__mmask8, __m512i, __m512i, int);
VPSHRDD __m128i _mm_shrdi_epi32(__m128i, __m128i, int);
VPSHRDD __m128i _mm_mask_shrdi_epi32(__m128i, __mmask8, __m128i, __m128i, int);
VPSHRDD __m128i _mm_maskz_shrdi_epi32(__mmask8, __m128i, __m128i, int);
VPSHRDD __m256i _mm256_shrdi_epi32(__m256i, __m256i, int);
VPSHRDD __m256i _mm256_mask_shrdi_epi32(__m256i, __mmask8, __m256i, __m256i, int);
VPSHRDD __m256i _mm256_maskz_shrdi_epi32(__mmask8, __m256i, __m256i, int);
VPSHRDD __m512i _mm512_shrdi_epi32(__m512i, __m512i, int);
VPSHRDD __m512i _mm512_mask_shrdi_epi32(__m512i, __mmask16, __m512i, __m512i, int);
VPSHRDD __m512i _mm512_maskz_shrdi_epi32(__mmask16, __m512i, __m512i, int);
VPSHRDW __m128i _mm_shrdi_epi16(__m128i, __m128i, int);
VPSHRDW __m128i _mm_mask_shrdi_epi16(__m128i, __mmask8, __m128i, __m128i, int);
VPSHRDW __m128i _mm_maskz_shrdi_epi16(__mmask8, __m128i, __m128i, int);
VPSHRDW __m256i _mm256_shrdi_epi16(__m256i, __m256i, int);
VPSHRDW __m256i _mm256_mask_shrdi_epi16(__m256i, __mmask16, __m256i, __m256i, int);
VPSHRDW __m256i _mm256_maskz_shrdi_epi16(__mmask16, __m256i, __m256i, int);
VPSHRDW __m512i _mm512_shrdi_epi16(__m512i, __m512i, int);
VPSHRDW __m512i _mm512_mask_shrdi_epi16(__m512i, __mmask32, __m512i, __m512i, int);
VPSHRDW __m512i _mm512_maskz_shrdi_epi16(__mmask32, __m512i, __m512i, int);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-51, “Type E4 Class Exception Conditions.”
VPSHRD-Concatenate and Shift Packed Data Right Logical
Vol. 2C
5-630
VPSHRDV-Concatenate and Variable Shift Packed Data Right Logical
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.66.0F38.W1 72 /r
A
V/V
(AVX512_VBMI2
Concatenate xmm1 and xmm2, extract result
VPSHRDVW xmm1{k1}{z}, xmm2,
AND AVX512VL)
shifted to the right by value in xmm3/m128
xmm3/m128
OR AVX10.1
into xmm1.
EVEX.256.66.0F38.W1 72 /r
A
V/V
(AVX512_VBMI2
Concatenate ymm1 and ymm2, extract result
VPSHRDVW ymm1{k1}{z}, ymm2,
AND AVX512VL)
shifted to the right by value in xmm3/m256
ymm3/m256
OR AVX10.1
into ymm1.
EVEX.512.66.0F38.W1 72 /r
A
V/V
AVX512_VBMI2
Concatenate zmm1 and zmm2, extract result
VPSHRDVW zmm1{k1}{z}, zmm2,
OR AVX10.1
shifted to the right by value in zmm3/m512
zmm3/m512
into zmm1.
EVEX.128.66.0F38.W0 73 /r
B
V/V
(AVX512_VBMI2
Concatenate xmm1 and xmm2, extract result
VPSHRDVD xmm1{k1}{z}, xmm2,
AND AVX512VL)
shifted to the right by value in xmm3/m128
xmm3/m128/m32bcst
OR AVX10.1
into xmm1.
EVEX.256.66.0F38.W0 73 /r
B
V/V
(AVX512_VBMI2
Concatenate ymm1 and ymm2, extract result
VPSHRDVD ymm1{k1}{z}, ymm2,
AND AVX512VL)
shifted to the right by value in xmm3/m256
ymm3/m256/m32bcst
OR AVX10.1
into ymm1.
EVEX.512.66.0F38.W0 73 /r
B
V/V
AVX512_VBMI2
Concatenate zmm1 and zmm2, extract result
VPSHRDVD zmm1{k1}{z}, zmm2,
OR AVX10.1
shifted to the right by value in zmm3/m512
zmm3/m512/m32bcst
into zmm1.
EVEX.128.66.0F38.W1 73 /r
B
V/V
(AVX512_VBMI2
Concatenate xmm1 and xmm2, extract result
VPSHRDVQ xmm1{k1}{z}, xmm2,
AND AVX512VL)
shifted to the right by value in xmm3/m128
xmm3/m128/m64bcst
OR AVX10.1
into xmm1.
EVEX.256.66.0F38.W1 73 /r
B
V/V
(AVX512_VBMI2
Concatenate ymm1 and ymm2, extract result
VPSHRDVQ ymm1{k1}{z}, ymm2,
AND AVX512VL)
shifted to the right by value in xmm3/m256
ymm3/m256/m64bcst
OR AVX10.1
into ymm1.
EVEX.512.66.0F38.W1 73 /r
B
V/V
AVX512_VBMI2
Concatenate zmm1 and zmm2, extract result
VPSHRDVQ zmm1{k1}{z}, zmm2,
OR AVX10.1
shifted to the right by value in zmm3/m512
zmm3/m512/m64bcst
into zmm1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full Mem
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
B
Full
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Concatenate packed data, extract result shifted to the right by variable value.
This instruction supports memory fault suppression.
VPSHRDV-Concatenate and Variable Shift Packed Data Right Logical
Vol. 2C
5-631
Operation
VPSHRDVW DEST, SRC2, SRC3
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1:
IF MaskBit(j) OR *no writemask*:
DEST.word[j] := concat(SRC2.word[j], DEST.word[j]) >> (SRC3.word[j] & 15)
ELSE IF *zeroing*:
DEST.word[j] := 0
*ELSE DEST.word[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0
VPSHRDVD DEST, SRC2, SRC3
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1:
IF SRC3 is broadcast memop:
tsrc3 := SRC3.dword[0]
ELSE:
tsrc3 := SRC3.dword[j]
IF MaskBit(j) OR *no writemask*:
DEST.dword[j] := concat(SRC2.dword[j], DEST.dword[j]) >> (tsrc3 & 31)
ELSE IF *zeroing*:
DEST.dword[j] := 0
*ELSE DEST.dword[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0
VPSHRDVQ DEST, SRC2, SRC3
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1:
IF SRC3 is broadcast memop:
tsrc3 := SRC3.qword[0]
ELSE:
tsrc3 := SRC3.qword[j]
IF MaskBit(j) OR *no writemask*:
DEST.qword[j] := concat(SRC2.qword[j], DEST.qword[j]) >> (tsrc3 & 63)
ELSE IF *zeroing*:
DEST.qword[j] := 0
*ELSE DEST.qword[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0
VPSHRDV-Concatenate and Variable Shift Packed Data Right Logical
Vol. 2C
5-632
Intel C/C++ Compiler Intrinsic Equivalent
VPSHRDVQ __m128i _mm_shrdv_epi64(__m128i, __m128i, __m128i);
VPSHRDVQ __m128i _mm_mask_shrdv_epi64(__m128i, __mmask8, __m128i, __m128i);
VPSHRDVQ __m128i _mm_maskz_shrdv_epi64(__mmask8, __m128i, __m128i, __m128i);
VPSHRDVQ __m256i _mm256_shrdv_epi64(__m256i, __m256i, __m256i);
VPSHRDVQ __m256i _mm256_mask_shrdv_epi64(__m256i, __mmask8, __m256i, __m256i);
VPSHRDVQ __m256i _mm256_maskz_shrdv_epi64(__mmask8, __m256i, __m256i, __m256i);
VPSHRDVQ __m512i _mm512_shrdv_epi64(__m512i, __m512i, __m512i);
VPSHRDVQ __m512i _mm512_mask_shrdv_epi64(__m512i, __mmask8, __m512i, __m512i);
VPSHRDVQ __m512i _mm512_maskz_shrdv_epi64(__mmask8, __m512i, __m512i, __m512i);
VPSHRDVD __m128i _mm_shrdv_epi32(__m128i, __m128i, __m128i);
VPSHRDVD __m128i _mm_mask_shrdv_epi32(__m128i, __mmask8, __m128i, __m128i);
VPSHRDVD __m128i _mm_maskz_shrdv_epi32(__mmask8, __m128i, __m128i, __m128i);
VPSHRDVD __m256i _mm256_shrdv_epi32(__m256i, __m256i, __m256i);
VPSHRDVD __m256i _mm256_mask_shrdv_epi32(__m256i, __mmask8, __m256i, __m256i);
VPSHRDVD __m256i _mm256_maskz_shrdv_epi32(__mmask8, __m256i, __m256i, __m256i);
VPSHRDVD __m512i _mm512_shrdv_epi32(__m512i, __m512i, __m512i);
VPSHRDVD __m512i _mm512_mask_shrdv_epi32(__m512i, __mmask16, __m512i, __m512i);
VPSHRDVD __m512i _mm512_maskz_shrdv_epi32(__mmask16, __m512i, __m512i, __m512i);
VPSHRDVW __m128i _mm_shrdv_epi16(__m128i, __m128i, __m128i);
VPSHRDVW __m128i _mm_mask_shrdv_epi16(__m128i, __mmask8, __m128i, __m128i);
VPSHRDVW __m128i _mm_maskz_shrdv_epi16(__mmask8, __m128i, __m128i, __m128i);
VPSHRDVW __m256i _mm256_shrdv_epi16(__m256i, __m256i, __m256i);
VPSHRDVW __m256i _mm256_mask_shrdv_epi16(__m256i, __mmask16, __m256i, __m256i);
VPSHRDVW __m256i _mm256_maskz_shrdv_epi16(__mmask16, __m256i, __m256i, __m256i);
VPSHRDVW __m512i _mm512_shrdv_epi16(__m512i, __m512i, __m512i);
VPSHRDVW __m512i _mm512_mask_shrdv_epi16(__m512i, __mmask32, __m512i, __m512i);
VPSHRDVW __m512i _mm512_maskz_shrdv_epi16(__mmask32, __m512i, __m512i, __m512i);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-51, “Type E4 Class Exception Conditions.”
VPSHRDV-Concatenate and Variable Shift Packed Data Right Logical
Vol. 2C
5-633
VPSHUFBITQMB-Shuffle Bits From Quadword Elements Using Byte Indexes Into Mask
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.66.0F38.W0 8F /r
A
V/V
(AVX512_BITALG
Extract values in xmm2 using control bits of
VPSHUFBITQMB k1{k2}, xmm2,
AND AVX512VL)
xmm3/m128 with writemask k2 and load the
xmm3/m128
OR AVX10.1
result into mask register k1.
EVEX.256.66.0F38.W0 8F /r
A
V/V
(AVX512_BITALG
Extract values in ymm2 using control bits of
VPSHUFBITQMB k1{k2}, ymm2,
AND AVX512VL)
ymm3/m256 with writemask k2 and load the
ymm3/m256
OR AVX10.1
result into mask register k1.
EVEX.512.66.0F38.W0 8F /r
A
V/V
AVX512_BITALG
Extract values in zmm2 using control bits of
VPSHUFBITQMB k1{k2}, zmm2,
OR AVX10.1
zmm3/m512 with writemask k2 and load the
zmm3/m512
result into mask register k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full Mem
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
The VPSHUFBITQMB instruction performs a bit gather select using second source as control and first source as
data. The value of each output bit is identified using 6 control bits from the second source operand to select a data
bit to be gathered from one of 64 contiguous bits of data in the first source operand. Each byte of the second source
operand provides a 6-bit index that gives access to 64 bits (26=64) within each respective quadword 64-bit lane
(i.e., index values in SRC2.qword[x] allow selecting bit values in SRC1.qword[x]).
Control data for each output bit is stored in 8 bit elements of SRC2, but only the 6 least significant bits of each
element are used.
This instruction uses write masking according to the writemask k2 (zeroing only). This instruction supports
memory fault suppression.
The first source operand is a ZMM/YMM/XMM register. The second source operand is a ZMM/YMM/XMM register or
a memory location. The destination operand is mask register k1.
Operation
VPSHUFBITQMB DEST, SRC1, SRC2
(KL, VL) = (16,128), (32,256), (64, 512)
FOR i := 0 TO KL/8-1:
//Qword
FOR j := 0 to 7:
// Byte
IF k2[i*8+j] or *no writemask*:
m := SRC2.qword[i].byte[j] & 0x3F
k1[i*8+j] := SRC1.qword[i].bit[m]
ELSE:
k1[i*8+j] := 0
k1[MAX_KL-1:KL] := 0
VPSHUFBITQMB-Shuffle Bits From Quadword Elements Using Byte Indexes Into Mask
Vol. 2C
5-634
Intel C/C++ Compiler Intrinsic Equivalent
VPSHUFBITQMB __mmask16 _mm_bitshuffle_epi64_mask(__m128i, __m128i);
VPSHUFBITQMB __mmask16 _mm_mask_bitshuffle_epi64_mask(__mmask16, __m128i, __m128i);
VPSHUFBITQMB __mmask32 _mm256_bitshuffle_epi64_mask(__m256i, __m256i);
VPSHUFBITQMB __mmask32 _mm256_mask_bitshuffle_epi64_mask(__mmask32, __m256i, __m256i);
VPSHUFBITQMB __mmask64 _mm512_bitshuffle_epi64_mask(__m512i, __m512i);
VPSHUFBITQMB __mmask64 _mm512_mask_bitshuffle_epi64_mask(__mmask64, __m512i, __m512i);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-51, "Type E4 Class Exception Conditions."
VPSHUFBITQMB-Shuffle Bits From Quadword Elements Using Byte Indexes Into Mask
Vol. 2C
5-635
VPSLLVW/VPSLLVD/VPSLLVQ-Variable Bit Shift Left Logical
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
VEX.128.66.0F38.W0 47 /r
A
V/V
AVX2
Shift doublewords in xmm2 left by amount
VPSLLVD xmm1, xmm2, xmm3/m128
specified in the corresponding element of
xmm3/m128 while shifting in 0s.
VEX.128.66.0F38.W1 47 /r
A
V/V
AVX2
Shift quadwords in xmm2 left by amount specified
VPSLLVQ xmm1, xmm2, xmm3/m128
in the corresponding element of xmm3/m128
while shifting in 0s.
VEX.256.66.0F38.W0 47 /r
A
V/V
AVX2
Shift doublewords in ymm2 left by amount
VPSLLVD ymm1, ymm2, ymm3/m256
specified in the corresponding element of
ymm3/m256 while shifting in 0s.
VEX.256.66.0F38.W1 47 /r
A
V/V
AVX2
Shift quadwords in ymm2 left by amount specified
VPSLLVQ ymm1, ymm2, ymm3/m256
in the corresponding element of ymm3/m256
while shifting in 0s.
EVEX.128.66.0F38.W1 12 /r
B
V/V
(AVX512VL AND
Shift words in xmm2 left by amount specified in
VPSLLVW xmm1 {k1}{z}, xmm2,
AVX512BW) OR
the corresponding element of xmm3/m128 while
xmm3/m128
AVX10.1
shifting in 0s using writemask k1.
EVEX.256.66.0F38.W1 12 /r
B
V/V
(AVX512VL AND
Shift words in ymm2 left by amount specified in
VPSLLVW ymm1 {k1}{z}, ymm2,
AVX512BW) OR
the corresponding element of ymm3/m256 while
ymm3/m256
AVX10.1
shifting in 0s using writemask k1.
EVEX.512.66.0F38.W1 12 /r
B
V/V
AVX512BW
Shift words in zmm2 left by amount specified in
VPSLLVW zmm1 {k1}{z}, zmm2,
OR AVX10.1
the corresponding element of zmm3/m512 while
zmm3/m512
shifting in 0s using writemask k1.
EVEX.128.66.0F38.W0 47 /r
C
V/V
(AVX512VL AND
Shift doublewords in xmm2 left by amount
VPSLLVD xmm1 {k1}{z}, xmm2,
AVX512F) OR
specified in the corresponding element of
xmm3/m128/m32bcst
AVX10.1
xmm3/m128/m32bcst while shifting in 0s using
writemask k1.
EVEX.256.66.0F38.W0 47 /r
C
V/V
(AVX512VL AND
Shift doublewords in ymm2 left by amount
VPSLLVD ymm1 {k1}{z}, ymm2,
AVX512F) OR
specified in the corresponding element of
ymm3/m256/m32bcst
AVX10.1
ymm3/m256/m32bcst while shifting in 0s using
writemask k1.
EVEX.512.66.0F38.W0 47 /r
C
V/V
AVX512F
Shift doublewords in zmm2 left by amount
VPSLLVD zmm1 {k1}{z}, zmm2,
OR AVX10.1
specified in the corresponding element of
zmm3/m512/m32bcst
zmm3/m512/m32bcst while shifting in 0s using
writemask k1.
EVEX.128.66.0F38.W1 47 /r
C
V/V
(AVX512VL AND
Shift quadwords in xmm2 left by amount specified
VPSLLVQ xmm1 {k1}{z}, xmm2,
AVX512F) OR
in the corresponding element of
xmm3/m128/m64bcst
AVX10.1
xmm3/m128/m64bcst while shifting in 0s using
writemask k1.
EVEX.256.66.0F38.W1 47 /r
C
V/V
(AVX512VL AND
Shift quadwords in ymm2 left by amount specified
VPSLLVQ ymm1 {k1}{z}, ymm2,
AVX512F) OR
in the corresponding element of
ymm3/m256/m64bcst
AVX10.1
ymm3/m256/m64bcst while shifting in 0s using
writemask k1.
EVEX.512.66.0F38.W1 47 /r
C
V/V
AVX512F
Shift quadwords in zmm2 left by amount specified
VPSLLVQ zmm1 {k1}{z}, zmm2,
OR AVX10.1
in the corresponding element of
zmm3/m512/m64bcst
zmm3/m512/m64bcst while shifting in 0s using
writemask k1.
VPSLLVW/VPSLLVD/VPSLLVQ-Variable Bit Shift Left Logical
Vol. 2C
5-636
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
B
Full Mem
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
C
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Shifts the bits in the individual data elements (words, doublewords or quadword) in the first source operand to the
left by the count value of respective data elements in the second source operand. As the bits in the data elements
are shifted left, the empty low-order bits are cleared (set to 0).
The count values are specified individually in each data element of the second source operand. If the unsigned
integer value specified in the respective data element of the second source operand is greater than 15 (for word),
31 (for doublewords), or 63 (for a quadword), then the destination data element are written with 0.
VEX.128 encoded version: The destination and first source operands are XMM registers. The count operand can be
either an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding destination register
are zeroed.
VEX.256 encoded version: The destination and first source operands are YMM registers. The count operand can be
either an YMM register or a 256-bit memory. Bits (MAXVL-1:256) of the corresponding ZMM register are zeroed.
EVEX encoded VPSLLVD/Q: The destination and first source operands are ZMM/YMM/XMM registers. The count
operand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512-bit vector broad-
casted from a 32/64-bit memory location. The destination is conditionally updated with writemask k1.
EVEX encoded VPSLLVW: The destination and first source operands are ZMM/YMM/XMM registers. The count
operand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination is condition-
ally updated with writemask k1.
Operation
VPSLLVW (EVEX encoded version)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1
i := j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := ZeroExtend(SRC1[i+15:i] << SRC2[i+15:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+15:i] := 0
FI
FI;
ENDFOR;
DEST[MAXVL-1:VL] := 0;
VPSLLVW/VPSLLVD/VPSLLVQ-Variable Bit Shift Left Logical
Vol. 2C
5-637
VPSLLVD (VEX.128 version)
COUNT_0 := SRC2[31 : 0]
(* Repeat Each COUNT_i for the 2nd through 4th dwords of SRC2*)
COUNT_3 := SRC2[127 : 96];
IF COUNT_0 < 32 THEN
DEST[31:0] := ZeroExtend(SRC1[31:0] << COUNT_0);
ELSE
DEST[31:0] := 0;
(* Repeat shift operation for 2nd through 4th dwords *)
IF COUNT_3 < 32 THEN
DEST[127:96] := ZeroExtend(SRC1[127:96] << COUNT_3);
ELSE
DEST[127:96] := 0;
DEST[MAXVL-1:128] := 0;
VPSLLVD (VEX.256 version)
COUNT_0 := SRC2[31 : 0];
(* Repeat Each COUNT_i for the 2nd through 7th dwords of SRC2*)
COUNT_7 := SRC2[255 : 224];
IF COUNT_0 < 32 THEN
DEST[31:0] := ZeroExtend(SRC1[31:0] << COUNT_0);
ELSE
DEST[31:0] := 0;
(* Repeat shift operation for 2nd through 7th dwords *)
IF COUNT_7 < 32 THEN
DEST[255:224] := ZeroExtend(SRC1[255:224] << COUNT_7);
ELSE
DEST[255:224] := 0;
DEST[MAXVL-1:256] := 0;
VPSLLVD (EVEX encoded version)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+31:i] := ZeroExtend(SRC1[i+31:i] << SRC2[31:0])
ELSE DEST[i+31:i] := ZeroExtend(SRC1[i+31:i] << SRC2[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR;
DEST[MAXVL-1:VL] := 0;
VPSLLVW/VPSLLVD/VPSLLVQ-Variable Bit Shift Left Logical
Vol. 2C
5-638
VPSLLVQ (VEX.128 version)
COUNT_0 := SRC2[63 : 0];
COUNT_1 := SRC2[127 : 64];
IF COUNT_0 < 64THEN
DEST[63:0] := ZeroExtend(SRC1[63:0] << COUNT_0);
ELSE
DEST[63:0] := 0;
IF COUNT_1 < 64 THEN
DEST[127:64] := ZeroExtend(SRC1[127:64] << COUNT_1);
ELSE
DEST[127:96] := 0;
DEST[MAXVL-1:128] := 0;
VPSLLVQ (VEX.256 version)
COUNT_0 := SRC2[63 : 0];
(* Repeat Each COUNT_i for the 2nd through 4th dwords of SRC2*)
COUNT_3 := SRC2[255 : 192];
IF COUNT_0 < 64THEN
DEST[63:0] := ZeroExtend(SRC1[63:0] << COUNT_0);
ELSE
DEST[63:0] := 0;
(* Repeat shift operation for 2nd through 4th dwords *)
IF COUNT_3 < 64 THEN
DEST[255:192] := ZeroExtend(SRC1[255:192] << COUNT_3);
ELSE
DEST[255:192] := 0;
DEST[MAXVL-1:256] := 0;
VPSLLVQ (EVEX encoded version)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+63:i] := ZeroExtend(SRC1[i+63:i] << SRC2[63:0])
ELSE DEST[i+63:i] := ZeroExtend(SRC1[i+63:i] << SRC2[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR;
DEST[MAXVL-1:VL] := 0;
VPSLLVW/VPSLLVD/VPSLLVQ-Variable Bit Shift Left Logical
Vol. 2C
5-639