Intel 64 and IA-32 Architectures. Software Developer’s Manual (2026) - page 36
VGATHERDPD __m512d _mm512_mask_i32gather_pd(__m512d s, __mmask8 k, __m256i vdx, void * base, int scale);
VGATHERDPD __m256d _mm256_mmask_i32gather_pd(__m256d s, __mmask8 k, __m128i vdx, void * base, int scale);
VGATHERDPD __m128d _mm_mmask_i32gather_pd(__m128d s, __mmask8 k, __m128i vdx, void * base, int scale);
VGATHERDPS __m512 _mm512_i32gather_ps( __m512i vdx, void * base, int scale);
VGATHERDPS __m512 _mm512_mask_i32gather_ps(__m512 s, __mmask16 k, __m512i vdx, void * base, int scale);
VGATHERDPS __m256 _mm256_mmask_i32gather_ps(__m256 s, __mmask8 k, __m256i vdx, void * base, int scale);
GATHERDPS __m128 _mm_mmask_i32gather_ps(__m128 s, __mmask8 k, __m128i vdx, void * base, int scale);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-63, “Type E12 Class Exception Conditions.”
VGATHERDPS/VGATHERDPD-Gather Packed Single, Packed Double with Signed Dword Indices
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VGATHERDPS/VGATHERQPS-Gather Packed Single Precision Floating-Point Values Using
Signed Dword/Qword Indices
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
Bit Mode
Feature
Support
Flag
VEX.128.66.0F38.W0 92 /r
A
V/V
AVX2
Using dword indices specified in vm32x, gather single
VGATHERDPS xmm1, vm32x, xmm2
precision floating-point values from memory conditioned
on mask specified by xmm2. Conditionally gathered ele-
ments are merged into xmm1.
VEX.128.66.0F38.W0 93 /r
A
V/V
AVX2
Using qword indices specified in vm64x, gather single
VGATHERQPS xmm1, vm64x, xmm2
precision floating-point values from memory conditioned
on mask specified by xmm2. Conditionally gathered ele-
ments are merged into xmm1.
VEX.256.66.0F38.W0 92 /r
A
V/V
AVX2
Using dword indices specified in vm32y, gather single
VGATHERDPS ymm1, vm32y, ymm2
precision floating-point values from memory conditioned
on mask specified by ymm2. Conditionally gathered ele-
ments are merged into ymm1.
VEX.256.66.0F38.W0 93 /r
A
V/V
AVX2
Using qword indices specified in vm64y, gather single
VGATHERQPS xmm1, vm64y, xmm2
precision floating-point values from memory conditioned
on mask specified by xmm2. Conditionally gathered ele-
ments are merged into xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
A
ModRM:reg (r,w)
BaseReg (R): VSIB:base,
VEX.vvvv (r, w)
N/A
VectorReg(R): VSIB:index
Description
The instruction conditionally loads up to 4 or 8 single precision floating-point values from memory addresses spec-
ified by the memory operand (the second operand) and using dword indices. The memory operand uses the VSIB
form of the SIB byte to specify a general purpose register operand as the common base, a vector register for an
array of indices relative to the base and a constant scale factor.
The mask operand (the third operand) specifies the conditional load operation from each memory address and the
corresponding update of each data element of the destination operand (the first operand). Conditionality is speci-
fied by the most significant bit of each data element of the mask register. If an element’s mask bit is not set, the
corresponding element of the destination register is left unchanged. The width of data element in the destination
register and mask register are identical. The entire mask register will be set to zero by this instruction unless the
instruction causes an exception.
Using qword indices, the instruction conditionally loads up to 2 or 4 single precision floating-point values from the
VSIB addressing memory operand, and updates the lower half of the destination register. The upper 128 or 256 bits
of the destination register are zero’ed with qword indices.
This instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception
is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination
register and the mask operand are partially updated; those elements that have been gathered are placed into the
destination register and have their mask bits set to zero. If any traps or interrupts are pending from already gath-
ered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction
breakpoint is not re-triggered when the instruction is continued.
If the data size and index size are different, part of the destination register and part of the mask register do not
correspond to any elements being gathered. This instruction sets those parts to zero. It may do this to one or both
of those registers even if the instruction triggers an exception, and even if the instruction triggers the exception
before gathering any elements.
VGATHERDPS/VGATHERQPS-Gather Packed Single Precision Floating-Point Values Using Signed Dword/Qword Indices
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VEX.128 version: For dword indices, the instruction will gather four single precision floating-point values. For
qword indices, the instruction will gather two values and zero the upper 64 bits of the destination.
VEX.256 version: For dword indices, the instruction will gather eight single precision floating-point values. For
qword indices, the instruction will gather four values and zero the upper 128 bits of the destination.
Note that:
• If any pair of the index, mask, or destination registers are the same, this instruction results a UD fault.
• The values may be read from memory in any order. Memory ordering with other instructions follows the Intel-
64 memory-ordering model.
• Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
elements closer to the LSB of the destination will be completed (and non-faulting). Individual elements closer
to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered in the
conventional order.
• Elements may be gathered in any order, but faults must be delivered in a right-to-left order; thus, elements to
the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
instruction is repeatable - given the same input values and architectural state, the same set of elements to the
left of the faulting one will be gathered.
• This instruction does not perform AC checks, and so will never deliver an AC fault.
• This instruction will cause a #UD if the address size attribute is 16-bit.
• This instruction will cause a #UD if the memory operand is encoded without the SIB byte.
• This instruction should not be used to access memory mapped I/O as the ordering of the individual loads it does
is implementation specific, and some implementations may use loads larger than the data element size or load
elements an indeterminate number of times.
• The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-
bit mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address
bits are ignored.
Operation
DEST := SRC1;
BASE_ADDR: base register encoded in VSIB addressing;
VINDEX: the vector index register encoded by VSIB addressing;
SCALE: scale factor encoded by SIB:[7:6];
DISP: optional 1, 4 byte displacement;
MASK := SRC3;
VGATHERDPS (VEX.128 version)
MASK[MAXVL-1:128] := 0;
FOR j := 0 to 3
i := j * 32;
IF MASK[31+i] THEN
MASK[i +31:i] := FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +31:i] := 0;
FI;
ENDFOR
FOR j := 0 to 3
i := j * 32;
DATA_ADDR := BASE_ADDR + (SignExtend(VINDEX[i+31:i])*SCALE + DISP;
IF MASK[31+i] THEN
DEST[i +31:i] := FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +31:i] := 0;
ENDFOR
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DEST[MAXVL-1:128] := 0;
VGATHERQPS (VEX.128 version)
MASK[MAXVL-1:64] := 0;
FOR j := 0 to 3
i := j * 32;
IF MASK[31+i] THEN
MASK[i +31:i] := FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +31:i] := 0;
FI;
ENDFOR
FOR j := 0 to 1
k := j * 64;
i := j * 32;
DATA_ADDR := BASE_ADDR + (SignExtend(VINDEX1[k+63:k])*SCALE + DISP;
IF MASK[31+i] THEN
DEST[i +31:i] := FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +31:i] := 0;
ENDFOR
DEST[MAXVL-1:64] := 0;
VGATHERDPS (VEX.256 version)
MASK[MAXVL-1:256] := 0;
FOR j := 0 to 7
i := j * 32;
IF MASK[31+i] THEN
MASK[i +31:i] := FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +31:i] := 0;
FI;
ENDFOR
FOR j := 0 to 7
i := j * 32;
DATA_ADDR := BASE_ADDR + (SignExtend(VINDEX1[i+31:i])*SCALE + DISP;
IF MASK[31+i] THEN
DEST[i +31:i] := FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +31:i] := 0;
ENDFOR
DEST[MAXVL-1:256] := 0;
VGATHERQPS (VEX.256 version)
MASK[MAXVL-1:128] := 0;
FOR j := 0 to 7
i := j * 32;
IF MASK[31+i] THEN
MASK[i +31:i] := FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +31:i] := 0;
FI;
ENDFOR
FOR j := 0 to 3
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k := j * 64;
i := j * 32;
DATA_ADDR := BASE_ADDR + (SignExtend(VINDEX1[k+63:k])*SCALE + DISP;
IF MASK[31+i] THEN
DEST[i +31:i] := FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +31:i] := 0;
ENDFOR
DEST[MAXVL-1:128] := 0;
Intel C/C++ Compiler Intrinsic Equivalent
VGATHERDPS:
__m128 _mm_i32gather_ps (float const * base, __m128i index, const int scale);
VGATHERDPS:
__m128 _mm_mask_i32gather_ps (__m128 src, float const * base, __m128i index, __m128 mask, const int scale);
VGATHERDPS:
__m256 _mm256_i32gather_ps (float const * base, __m256i index, const int scale);
VGATHERDPS:
__m256 _mm256_mask_i32gather_ps (__m256 src, float const * base, __m256i index, __m256 mask, const int
scale);
VGATHERQPS:
__m128 _mm_i64gather_ps (float const * base, __m128i index, const int scale);
VGATHERQPS:
__m128 _mm_mask_i64gather_ps (__m128 src, float const * base, __m128i index, __m128 mask, const int scale);
VGATHERQPS:
__m128 _mm256_i64gather_ps (float const * base, __m256i index, const int scale);
VGATHERQPS:
__m128 _mm256_mask_i64gather_ps (__m128 src, float const * base, __m256i index, __m128 mask, const int
scale);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-27, “Type 12 Class Exception Conditions.”
VGATHERDPS/VGATHERQPS-Gather Packed Single Precision Floating-Point Values Using Signed Dword/Qword Indices
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VGATHERQPS/VGATHERQPD-Gather Packed Single, Packed Double with Signed Qword Indices
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.66.0F38.W0 93 /vsib
A
V/V
(AVX512VL AND
Using signed qword indices, gather single-precision
VGATHERQPS xmm1 {k1}, vm64x
AVX512F) OR
floating-point values from memory using k1 as
AVX10.1
completion mask.
EVEX.256.66.0F38.W0 93 /vsib
A
V/V
(AVX512VL AND
Using signed qword indices, gather single-precision
VGATHERQPS xmm1 {k1}, vm64y
AVX512F) OR
floating-point values from memory using k1 as
AVX10.1
completion mask.
EVEX.512.66.0F38.W0 93 /vsib
A
V/V
AVX512F
Using signed qword indices, gather single-precision
VGATHERQPS ymm1 {k1}, vm64z
OR AVX10.1
floating-point values from memory using k1 as
completion mask.
EVEX.128.66.0F38.W1 93 /vsib
A
V/V
(AVX512VL AND
Using signed qword indices, gather float64 vector into
VGATHERQPD xmm1 {k1}, vm64x
AVX512F) OR
float64 vector xmm1 using k1 as completion mask.
AVX10.1
EVEX.256.66.0F38.W1 93 /vsib
A
V/V
(AVX512VL AND
Using signed qword indices, gather float64 vector into
VGATHERQPD ymm1 {k1}, vm64y
AVX512F) OR
float64 vector ymm1 using k1 as completion mask.
AVX10.1
EVEX.512.66.0F38.W1 93 /vsib
A
V/V
AVX512F
Using signed qword indices, gather float64 vector into
VGATHERQPD zmm1 {k1}, vm64z
OR AVX10.1
float64 vector zmm1 using k1 as completion mask.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
BaseReg (R): VSIB:base,
A
Tuple1 Scalar
ModRM:reg (w)
N/A
N/A
VectorReg(R): VSIB:index
Description
A set of 8 single precision/double precision faulting-point memory locations pointed by base address BASE_ADDR
and index vector V_INDEX with scale SCALE are gathered. The result is written into vector a register. The elements
are specified via the VSIB (i.e., the index register is a vector register, holding packed indices). Elements will only
be loaded if their corresponding mask bit is one. If an element’s mask bit is not set, the corresponding element of
the destination register is left unchanged. The entire mask register will be set to zero by this instruction unless it
triggers an exception.
This instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception
is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination
register and the mask register (k1) are partially updated; those elements that have been gathered are placed into
the destination register and have their mask bits set to zero. If any traps or interrupts are pending from already
gathered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruc-
tion breakpoint is not re-triggered when the instruction is continued.
If the data element size is less than the index element size, the higher part of the destination register and the mask
register do not correspond to any elements being gathered. This instruction sets those higher parts to zero. It may
update these unused elements to one or both of those registers even if the instruction triggers an exception, and
even if the instruction triggers the exception before gathering any elements.
Note that:
• The values may be read from memory in any order. Memory ordering with other instructions follows the Intel-
64 memory-ordering model.
• Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
elements closer to the LSB of the destination zmm will be completed (and non-faulting). Individual elements
closer to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered
in the conventional order.
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• Elements may be gathered in any order, but faults must be delivered in a right-to left order; thus, elements to
the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
instruction is repeatable - given the same input values and architectural state, the same set of elements to the
left of the faulting one will be gathered.
• This instruction does not perform AC checks, and so will never deliver an AC fault.
• Not valid with 16-bit effective addresses. Will deliver a #UD fault.
Note that the presence of VSIB byte is enforced in this instruction. Hence, the instruction will #UD fault if
ModRM.rm is different than 100b.
This instruction has special disp8*N and alignment rules. N is considered to be the size of a single vector element.
The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-bit
mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address bits are
ignored.
The instruction will #UD fault if the destination vector zmm1 is the same as index vector VINDEX. The instruction
will #UD fault if the k0 mask register is specified.
Operation
BASE_ADDR stands for the memory operand base address (a GPR); may not exist
VINDEX stands for the memory operand vector of indices (a ZMM register)
SCALE stands for the memory operand scalar (1, 2, 4 or 8)
DISP is the optional 1 or 4 byte displacement
VGATHERQPS (EVEX encoded version)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 32
k := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] :=
MEM[BASE_ADDR + (VINDEX[k+63:k]) * SCALE + DISP]
k1[j] := 0
ELSE *DEST[i+31:i] := remains unchanged*
FI;
ENDFOR
k1[MAX_KL-1:KL] := 0
DEST[MAXVL-1:VL/2] := 0
VGATHERQPD (EVEX encoded version)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] := MEM[BASE_ADDR + (VINDEX[i+63:i]) * SCALE + DISP]
k1[j] := 0
ELSE *DEST[i+63:i] := remains unchanged*
FI;
ENDFOR
k1[MAX_KL-1:KL] := 0
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VGATHERQPD __m512d _mm512_i64gather_pd( __m512i vdx, void * base, int scale);
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VGATHERQPD __m512d _mm512_mask_i64gather_pd(__m512d s, __mmask8 k, __m512i vdx, void * base, int scale);
VGATHERQPD __m256d _mm256_mask_i64gather_pd(__m256d s, __mmask8 k, __m256i vdx, void * base, int scale);
VGATHERQPD __m128d _mm_mask_i64gather_pd(__m128d s, __mmask8 k, __m128i vdx, void * base, int scale);
VGATHERQPS __m256 _mm512_i64gather_ps( __m512i vdx, void * base, int scale);
VGATHERQPS __m256 _mm512_mask_i64gather_ps(__m256 s, __mmask16 k, __m512i vdx, void * base, int scale);
VGATHERQPS __m128 _mm256_mask_i64gather_ps(__m128 s, __mmask8 k, __m256i vdx, void * base, int scale);
VGATHERQPS __m128 _mm_mask_i64gather_ps(__m128 s, __mmask8 k, __m128i vdx, void * base, int scale);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-63, “Type E12 Class Exception Conditions.”
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VGETEXPPD-Convert Exponents of Packed Double Precision Floating-Point Values to Double
Precision Floating-Point Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.66.0F38.W1 42 /r
A
V/V
(AVX512VL
Convert the exponent of packed double precision floating-
VGETEXPPD xmm1 {k1}{z},
AND AVX512F)
point values in the source operand to double precision
xmm2/m128/m64bcst
OR AVX10.1
floating-point results representing unbiased integer
exponents and stores the results in the destination register.
EVEX.256.66.0F38.W1 42 /r
A
V/V
(AVX512VL
Convert the exponent of packed double precision floating-
VGETEXPPD ymm1 {k1}{z},
AND AVX512F)
point values in the source operand to double precision
ymm2/m256/m64bcst
OR AVX10.1
floating-point results representing unbiased integer
exponents and stores the results in the destination register.
EVEX.512.66.0F38.W1 42 /r
A
V/V
AVX512F
Convert the exponent of packed double precision floating-
VGETEXPPD zmm1 {k1}{z},
OR AVX10.1
point values in the source operand to double precision
zmm2/m512/m64bcst{sae}
floating-point results representing unbiased integer
exponents and stores the results in the destination under
writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Extracts the biased exponents from the normalized double precision floating-point representation of each qword
data element of the source operand (the second operand) as unbiased signed integer value, or convert the
denormal representation of input data to unbiased negative integer values. Each integer value of the unbiased
exponent is converted to double precision floating-point value and written to the corresponding qword elements of
the destination operand (the first operand) as double precision floating-point numbers.
The destination operand is a ZMM/YMM/XMM register and updated under the writemask. The source operand can
be a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from
a 64-bit memory location.
EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Each GETEXP operation converts the exponent value into a floating-point number (permitting input value in
denormal representation). Special cases of input values are listed in Table 5-13.
The formula is:
GETEXP(x) = floor(log2(|x|))
Notation floor(x) stands for the greatest integer not exceeding real number x.
Table 5-13. VGETEXPPD/SD Special Cases
Input Operand
Result
Comments
src1 = NaN
QNaN(src1)
If (SRC = SNaN) then #IE
0 < |src1| < INF
floor(log2(|src1|))
If (SRC = denormal) then #DE
| src1| = +INF
+INF
| src1| = 0
-INF
Operation
NormalizeExpTinyDPFP(SRC[63:0])
{
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// Jbit is the hidden integral bit of a floating-point number. In case of denormal number it has the value of ZERO.
Src.Jbit := 0;
Dst.exp := 1;
Dst.fraction := SRC[51:0];
WHILE(Src.Jbit = 0)
{
Src.Jbit := Dst.fraction[51];
// Get the fraction MSB
Dst.fraction := Dst.fraction << 1 ;
// One bit shift left
Dst.exp-- ;
// Decrement the exponent
}
Dst.fraction := 0;
// zero out fraction bits
Dst.sign := 1;
// Return negative sign
TMP[63:0] := MXCSR.DAZ? 0 : (Dst.sign << 63) OR (Dst.exp << 52) OR (Dst.fraction) ;
Return (TMP[63:0]);
}
ConvertExpDPFP(SRC[63:0])
{
Src.sign := 0;
// Zero out sign bit
Src.exp := SRC[62:52];
Src.fraction := SRC[51:0];
// Check for NaN
IF (SRC = NaN)
{
IF ( SRC = SNAN ) SET IE;
Return QNAN(SRC);
}
// Check for +INF
IF (Src = +INF) RETURN (Src);
// check if zero operand
IF ((Src.exp = 0) AND ((Src.fraction = 0) OR (MXCSR.DAZ = 1))) Return (-INF);
}
ELSE
// check if denormal operand (notice that MXCSR.DAZ = 0)
{
IF ((Src.exp = 0) AND (Src.fraction != 0))
{
TMP[63:0] := NormalizeExpTinyDPFP(SRC[63:0]) ;
// Get Normalized Exponent
Set #DE
}
ELSE
// exponent value is correct
{
TMP[63:0] := (Src.sign << 63) OR (Src.exp << 52) OR (Src.fraction) ;
}
TMP := SAR(TMP, 52) ;
// Shift Arithmetic Right
TMP := TMP - 1023;
// Subtract Bias
Return CvtI2D(TMP);
// Convert INT to double precision floating-point number
}
}
VGETEXPPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
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IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC *is memory*)
THEN
DEST[i+63:i] :=
ConvertExpDPFP(SRC[63:0])
ELSE
DEST[i+63:i] :=
ConvertExpDPFP(SRC[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VGETEXPPD __m512d _mm512_getexp_pd(__m512d a);
VGETEXPPD __m512d _mm512_mask_getexp_pd(__m512d s, __mmask8 k, __m512d a);
VGETEXPPD __m512d _mm512_maskz_getexp_pd( __mmask8 k, __m512d a);
VGETEXPPD __m512d _mm512_getexp_round_pd(__m512d a, int sae);
VGETEXPPD __m512d _mm512_mask_getexp_round_pd(__m512d s, __mmask8 k, __m512d a, int sae);
VGETEXPPD __m512d _mm512_maskz_getexp_round_pd( __mmask8 k, __m512d a, int sae);
VGETEXPPD __m256d _mm256_getexp_pd(__m256d a);
VGETEXPPD __m256d _mm256_mask_getexp_pd(__m256d s, __mmask8 k, __m256d a);
VGETEXPPD __m256d _mm256_maskz_getexp_pd( __mmask8 k, __m256d a);
VGETEXPPD __m128d _mm_getexp_pd(__m128d a);
VGETEXPPD __m128d _mm_mask_getexp_pd(__m128d s, __mmask8 k, __m128d a);
VGETEXPPD __m128d _mm_maskz_getexp_pd( __mmask8 k, __m128d a);
SIMD Floating-Point Exceptions
Invalid, Denormal.
VGETEXPPD-Convert Exponents of Packed Double Precision Floating-Point Values to Double Precision Floating-Point Values
Vol. 2C
5-374
Other Exceptions
See Table 2-48, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VGETEXPPD-Convert Exponents of Packed Double Precision Floating-Point Values to Double Precision Floating-Point Values
Vol. 2C
5-375
VGETEXPPH-Convert Exponents of Packed FP16 Values to FP16 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.66.MAP6.W0 42 /r
A
V/V
(AVX512_FP16
Convert the exponent of FP16 values in the source
VGETEXPPH xmm1{k1}{z},
AND AVX512VL)
operand to FP16 results representing unbiased
xmm2/m128/m16bcst
OR AVX10.1
integer exponents and stores the results in the
destination register subject to writemask k1.
EVEX.256.66.MAP6.W0 42 /r
A
V/V
(AVX512_FP16
Convert the exponent of FP16 values in the source
VGETEXPPH ymm1{k1}{z},
AND AVX512VL)
operand to FP16 results representing unbiased
ymm2/m256/m16bcst
OR AVX10.1
integer exponents and stores the results in the
destination register subject to writemask k1.
EVEX.512.66.MAP6.W0 42 /r
A
V/V
AVX512_FP16
Convert the exponent of FP16 values in the source
VGETEXPPH zmm1{k1}{z},
OR AVX10.1
operand to FP16 results representing unbiased
zmm2/m512/m16bcst {sae}
integer exponents and stores the results in the
destination register subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction extracts the biased exponents from the normalized FP16 representation of each word element of
the source operand (the second operand) as unbiased signed integer value, or convert the denormal representa-
tion of input data to unbiased negative integer values. Each integer value of the unbiased exponent is converted to
an FP16 value and written to the corresponding word elements of the destination operand (the first operand) as
FP16 numbers.
The destination elements are updated according to the writemask.
Each GETEXP operation converts the exponent value into a floating-point number (permitting input value in
denormal representation). Special cases of input values are listed in Table 5-8.
The formula is:
GETEXP(x) = floor(log2(|x|))
Notation floor(x) stands for maximal integer not exceeding real number x.
Software usage of VGETEXPxx and VGETMANTxx instructions generally involve a combination of GETEXP operation
and GETMANT operation (see VGETMANTPH). Thus, the VGETEXPPH instruction does not require software to
handle SIMD floating-point exceptions.
Table 5-14. VGETEXPPH/VGETEXPSH Special Cases
Input Operand
Result
Comments
src1 = NaN
QNaN(src1)
If (SRC = SNaN), then #IE.
0 < |src1| < INF
floor(log2(|src1|))
If (SRC = denormal), then #DE.
| src1| = +INF
+INF
| src1| = 0
-INF
VGETEXPPH-Convert Exponents of Packed FP16 Values to FP16 Values
Vol. 2C
5-376
Operation
def normalize_exponent_tiny_fp16(src):
jbit := 0
// src & dst are FP16 numbers with sign(1b), exp(5b) and fraction (10b) fields
dst.exp := 1
// write bits 14:10
dst.fraction := src.fraction // copy bits 9:0
while jbit == 0:
jbit := dst.fraction[9]
// msb of the fraction
dst.fraction := dst.fraction << 1
dst.exp := dst.exp - 1
dst.fraction := 0
return dst
def getexp_fp16(src):
src.sign := 0
// make positive
exponent_all_ones := (src[14:10] == 0x1F)
exponent_all_zeros := (src[14:10] == 0)
mantissa_all_zeros := (src[9:0] == 0)
zero := exponent_all_zeros and mantissa_all_zeros
signaling_bit := src[9]
nan := exponent_all_ones and not(mantissa_all_zeros)
snan := nan and not(signaling_bit)
qnan := nan and signaling_bit
positive_infinity := not(negative) and exponent_all_ones and mantissa_all_zeros
denormal := exponent_all_zeros and not(mantissa_all_zeros)
if nan:
if snan:
MXCSR.IE := 1
return qnan(src)
// convert snan to a qnan
if positive_infinity:
return src
if zero:
return -INF
if denormal:
tmp := normalize_exponent_tiny_fp16(src)
MXCSR.DE := 1
else:
tmp := src
tmp := SAR(tmp, 10)
// shift arithmetic right
tmp := tmp - 15
// subtract bias
return convert_integer_to_fp16(tmp)
VGETEXPPH-Convert Exponents of Packed FP16 Values to FP16 Values
Vol. 2C
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VGETEXPPH dest{k1}, src
VL = 128, 256 or 512
KL := VL/16
FOR i := 0 to KL-1:
IF k1[i] or *no writemask*:
IF SRC is memory and (EVEX.b = 1):
tsrc := src.fp16[0]
ELSE:
tsrc := src.fp16[i]
DEST.fp16[i] := getexp_fp16(tsrc)
ELSE IF *zeroing*:
DEST.fp16[i] := 0
//else DEST.fp16[i] remains unchanged
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VGETEXPPH __m128h _mm_getexp_ph (__m128h a);
VGETEXPPH __m128h _mm_mask_getexp_ph (__m128h src, __mmask8 k, __m128h a);
VGETEXPPH __m128h _mm_maskz_getexp_ph (__mmask8 k, __m128h a);
VGETEXPPH __m256h _mm256_getexp_ph (__m256h a);
VGETEXPPH __m256h _mm256_mask_getexp_ph (__m256h src, __mmask16 k, __m256h a);
VGETEXPPH __m256h _mm256_maskz_getexp_ph (__mmask16 k, __m256h a);
VGETEXPPH __m512h _mm512_getexp_ph (__m512h a);
VGETEXPPH __m512h _mm512_mask_getexp_ph (__m512h src, __mmask32 k, __m512h a);
VGETEXPPH __m512h _mm512_maskz_getexp_ph (__mmask32 k, __m512h a);
VGETEXPPH __m512h _mm512_getexp_round_ph (__m512h a, const int sae);
VGETEXPPH __m512h _mm512_mask_getexp_round_ph (__m512h src, __mmask32 k, __m512h a, const int sae);
VGETEXPPH __m512h _mm512_maskz_getexp_round_ph (__mmask32 k, __m512h a, const int sae);
SIMD Floating-Point Exceptions
Invalid, Denormal.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
VGETEXPPH-Convert Exponents of Packed FP16 Values to FP16 Values
Vol. 2C
5-378
VGETEXPPS-Convert Exponents of Packed Single Precision Floating-Point Values to Single
Precision Floating-Point Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.66.0F38.W0 42 /r
A
V/V
(AVX512VL
Convert the exponent of packed single-precision floating-
VGETEXPPS xmm1 {k1}{z},
AND AVX512F)
point values in the source operand to single-precision
xmm2/m128/m32bcst
OR AVX10.1
floating-point results representing unbiased integer
exponents and stores the results in the destination
register.
EVEX.256.66.0F38.W0 42 /r
A
V/V
(AVX512VL
Convert the exponent of packed single-precision floating-
VGETEXPPS ymm1 {k1}{z},
AND AVX512F)
point values in the source operand to single-precision
ymm2/m256/m32bcst
OR AVX10.1
floating-point results representing unbiased integer
exponents and stores the results in the destination
register.
EVEX.512.66.0F38.W0 42 /r
A
V/V
AVX512F
Convert the exponent of packed single-precision floating-
VGETEXPPS zmm1 {k1}{z},
OR AVX10.1
point values in the source operand to single-precision
zmm2/m512/m32bcst{sae}
floating-point results representing unbiased integer
exponents and stores the results in the destination
register.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Extracts the biased exponents from the normalized single precision floating-point representation of each dword
element of the source operand (the second operand) as unbiased signed integer value, or convert the denormal
representation of input data to unbiased negative integer values. Each integer value of the unbiased exponent is
converted to single precision floating-point value and written to the corresponding dword elements of the destina-
tion operand (the first operand) as single precision floating-point numbers.
The destination operand is a ZMM/YMM/XMM register and updated under the writemask. The source operand can
be a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from
a 32-bit memory location.
EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Each GETEXP operation converts the exponent value into a floating-point number (permitting input value in
denormal representation). Special cases of input values are listed in Table 5-15.
The formula is:
GETEXP(x) = floor(log2(|x|))
Notation floor(x) stands for maximal integer not exceeding real number x.
Software usage of VGETEXPxx and VGETMANTxx instructions generally involve a combination of GETEXP operation
and GETMANT operation (see VGETMANTPD). Thus VGETEXPxx instruction do not require software to handle SIMD
floating-point exceptions.
VGETEXPPS-Convert Exponents of Packed Single Precision Floating-Point Values to Single Precision Floating-Point Values
Vol. 2C
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Table 5-15. VGETEXPPS/SS Special Cases
Input Operand
Result
Comments
src1 = NaN
QNaN(src1)
If (SRC = SNaN) then #IE
0 < |src1| < INF
floor(log2(|src1|))
If (SRC = denormal) then #DE
| src1| = +INF
+INF
| src1| = 0
-INF
Figure 5-14 illustrates the VGETEXPPS functionality on input values with normalized representation.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
s
exp
Fraction
Src = 2^1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SAR Src, 23 = 080h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
-Bias
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
Tmp - Bias = 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Cvt_PI2PS(01h) = 2^0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-14. VGETEXPPS Functionality On Normal Input values
Operation
NormalizeExpTinySPFP(SRC[31:0])
{
// Jbit is the hidden integral bit of a floating-point number. In case of denormal number it has the value of ZERO.
Src.Jbit := 0;
Dst.exp := 1;
Dst.fraction := SRC[22:0];
WHILE(Src.Jbit = 0)
{
Src.Jbit := Dst.fraction[22];
// Get the fraction MSB
Dst.fraction := Dst.fraction << 1 ;
// One bit shift left
Dst.exp-- ;
// Decrement the exponent
}
Dst.fraction := 0;
// zero out fraction bits
Dst.sign := 1;
// Return negative sign
TMP[31:0] := MXCSR.DAZ? 0 : (Dst.sign << 31) OR (Dst.exp << 23) OR (Dst.fraction) ;
Return (TMP[31:0]);
}
ConvertExpSPFP(SRC[31:0])
{
Src.sign := 0;
// Zero out sign bit
Src.exp := SRC[30:23];
Src.fraction := SRC[22:0];
// Check for NaN
IF (SRC = NaN)
{
IF ( SRC = SNAN ) SET IE;
VGETEXPPS-Convert Exponents of Packed Single Precision Floating-Point Values to Single Precision Floating-Point Values
Vol. 2C
5-380
Return QNAN(SRC);
}
// Check for +INF
IF (Src = +INF) RETURN (Src);
// check if zero operand
IF ((Src.exp = 0) AND ((Src.fraction = 0) OR (MXCSR.DAZ = 1))) Return (-INF);
}
ELSE
// check if denormal operand (notice that MXCSR.DAZ = 0)
{
IF ((Src.exp = 0) AND (Src.fraction != 0))
{
TMP[31:0] := NormalizeExpTinySPFP(SRC[31:0]) ;
// Get Normalized Exponent
Set #DE
}
ELSE
// exponent value is correct
{
TMP[31:0] := (Src.sign << 31) OR (Src.exp << 23) OR (Src.fraction) ;
}
TMP := SAR(TMP, 23) ;
// Shift Arithmetic Right
TMP := TMP - 127;
// Subtract Bias
Return CvtI2S(TMP);
// Convert INT to single precision floating-point number
}
}
VGETEXPPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC *is memory*)
THEN
DEST[i+31:i] :=
ConvertExpSPFP(SRC[31:0])
ELSE
DEST[i+31:i] :=
ConvertExpSPFP(SRC[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VGETEXPPS-Convert Exponents of Packed Single Precision Floating-Point Values to Single Precision Floating-Point Values
Vol. 2C
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Intel C/C++ Compiler Intrinsic Equivalent
VGETEXPPS __m512 _mm512_getexp_ps( __m512 a);
VGETEXPPS __m512 _mm512_mask_getexp_ps(__m512 s, __mmask16 k, __m512 a);
VGETEXPPS __m512 _mm512_maskz_getexp_ps( __mmask16 k, __m512 a);
VGETEXPPS __m512 _mm512_getexp_round_ps( __m512 a, int sae);
VGETEXPPS __m512 _mm512_mask_getexp_round_ps(__m512 s, __mmask16 k, __m512 a, int sae);
VGETEXPPS __m512 _mm512_maskz_getexp_round_ps( __mmask16 k, __m512 a, int sae);
VGETEXPPS __m256 _mm256_getexp_ps(__m256 a);
VGETEXPPS __m256 _mm256_mask_getexp_ps(__m256 s, __mmask8 k, __m256 a);
VGETEXPPS __m256 _mm256_maskz_getexp_ps( __mmask8 k, __m256 a);
VGETEXPPS __m128 _mm_getexp_ps(__m128 a);
VGETEXPPS __m128 _mm_mask_getexp_ps(__m128 s, __mmask8 k, __m128 a);
VGETEXPPS __m128 _mm_maskz_getexp_ps( __mmask8 k, __m128 a);
SIMD Floating-Point Exceptions
Invalid, Denormal.
Other Exceptions
See Table 2-48, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VGETEXPPS-Convert Exponents of Packed Single Precision Floating-Point Values to Single Precision Floating-Point Values
Vol. 2C
5-382
VGETEXPSD-Convert Exponents of Scalar Double Precision Floating-Point Value to Double
Precision Floating-Point Value
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
Bit Mode
Feature Flag
Support
EVEX.LLIG.66.0F38.W1 43 /r
A
V/V
AVX512F
Convert the biased exponent (bits 62:52) of the low
VGETEXPSD xmm1 {k1}{z},
OR AVX10.1
double precision floating-point value in xmm3/m64 to a
xmm2, xmm3/m64{sae}
double precision floating-point value representing
unbiased integer exponent. Stores the result to the low
64-bit of xmm1 under the writemask k1 and merge with
the other elements of xmm2.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Scalar
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Extracts the biased exponent from the normalized double precision floating-point representation of the low qword
data element of the source operand (the third operand) as unbiased signed integer value, or convert the denormal
representation of input data to unbiased negative integer values. The integer value of the unbiased exponent is
converted to double precision floating-point value and written to the destination operand (the first operand) as
double precision floating-point numbers. Bits (127:64) of the XMM register destination are copied from corre-
sponding bits in the first source operand.
The destination must be a XMM register, the source operand can be a XMM register or a float64 memory location.
If writemasking is used, the low quadword element of the destination operand is conditionally updated depending
on the value of writemask register k1. If writemasking is not used, the low quadword element of the destination
operand is unconditionally updated.
Each GETEXP operation converts the exponent value into a floating-point number (permitting input value in
denormal representation). Special cases of input values are listed in Table 5-13.
The formula is:
GETEXP(x) = floor(log2(|x|))
Notation floor(x) stands for maximal integer not exceeding real number x.
Operation
// NormalizeExpTinyDPFP(SRC[63:0]) is defined in the Operation section of VGETEXPPD
// ConvertExpDPFP(SRC[63:0]) is defined in the Operation section of VGETEXPPD
VGETEXPSD-Convert Exponents of Scalar Double Precision Floating-Point Value to Double Precision Floating-Point Value
Vol. 2C
5-383
VGETEXPSD (EVEX encoded version)
IF k1[0] OR *no writemask*
THEN DEST[63:0] :=
ConvertExpDPFP(SRC2[63:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
DEST[63:0] := 0
FI
FI;
DEST[127:64] := SRC1[127:64]
DEST[MAXVL-1:128] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VGETEXPSD __m128d _mm_getexp_sd( __m128d a, __m128d b);
VGETEXPSD __m128d _mm_mask_getexp_sd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VGETEXPSD __m128d _mm_maskz_getexp_sd( __mmask8 k, __m128d a, __m128d b);
VGETEXPSD __m128d _mm_getexp_round_sd( __m128d a, __m128d b, int sae);
VGETEXPSD __m128d _mm_mask_getexp_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int sae);
VGETEXPSD __m128d _mm_maskz_getexp_round_sd( __mmask8 k, __m128d a, __m128d b, int sae);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
See Table 2-49, “Type E3 Class Exception Conditions.”
VGETEXPSD-Convert Exponents of Scalar Double Precision Floating-Point Value to Double Precision Floating-Point Value
Vol. 2C
5-384
VGETEXPSH-Convert Exponents of Scalar FP16 Values to FP16 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.LLIG.66.MAP6.W0 43 /r
A
V/V
AVX512_FP16
Convert the exponent of FP16 values in the low
VGETEXPSH xmm1{k1}{z}, xmm2,
OR AVX10.1
word of the source operand to FP16 results
xmm3/m16 {sae}
representing unbiased integer exponents, and stores
the results in the low word of the destination
register subject to writemask k1. Bits 127:16 of
xmm2 are copied to xmm1[127:16].
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
This instruction extracts the biased exponents from the normalized FP16 representation of the low word element of
the source operand (the second operand) as unbiased signed integer value, or convert the denormal representa-
tion of input data to an unbiased negative integer value. The integer value of the unbiased exponent is converted
to an FP16 value and written to the low word element of the destination operand (the first operand) as an FP16
number.
Bits 127:16 of the destination operand are copied from the corresponding bits of the first source operand. Bits
MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the destination is updated according
to the writemask.
Each GETEXP operation converts the exponent value into a floating-point number (permitting input value in
denormal representation). Special cases of input values are listed in Table 5-14.
The formula is:
GETEXP(x) = floor(log2(|x|))
Notation floor(x) stands for maximal integer not exceeding real number x.
Software usage of VGETEXPxx and VGETMANTxx instructions generally involve a combination of GETEXP operation
and GETMANT operation (see VGETMANTSH). Thus, the VGETEXPSH instruction does not require software to
handle SIMD floating-point exceptions.
Operation
VGETEXPSH dest{k1}, src1, src2
IF k1[0] or *no writemask*:
DEST.fp16[0] := getexp_fp16(src2.fp16[0]) // see VGETEXPPH
ELSE IF *zeroing*:
DEST.fp16[0] := 0
//else DEST.fp16[0] remains unchanged
DEST[127:16] := src1[127:16]
DEST[MAXVL-1:128] := 0
VGETEXPSH-Convert Exponents of Scalar FP16 Values to FP16 Values
Vol. 2C
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Intel C/C++ Compiler Intrinsic Equivalent
VGETEXPSH __m128h _mm_getexp_round_sh (__m128h a, __m128h b, const int sae);
VGETEXPSH __m128h _mm_mask_getexp_round_sh (__m128h src, __mmask8 k, __m128h a, __m128h b, const int sae);
VGETEXPSH __m128h _mm_maskz_getexp_round_sh (__mmask8 k, __m128h a, __m128h b, const int sae);
VGETEXPSH __m128h _mm_getexp_sh (__m128h a, __m128h b);
VGETEXPSH __m128h _mm_mask_getexp_sh (__m128h src, __mmask8 k, __m128h a, __m128h b);
VGETEXPSH __m128h _mm_maskz_getexp_sh (__mmask8 k, __m128h a, __m128h b);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
EVEX-encoded instructions, see Table 2-49, “Type E3 Class Exception Conditions.”
VGETEXPSH-Convert Exponents of Scalar FP16 Values to FP16 Values
Vol. 2C
5-386
VGETEXPSS-Convert Exponents of Scalar Single Precision Floating-Point Value to Single
Precision Floating-Point Value
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
Bit Mode
Feature Flag
Support
EVEX.LLIG.66.0F38.W0 43 /r
A
V/V
AVX512F
Convert the biased exponent (bits 30:23) of the low
VGETEXPSS xmm1 {k1}{z}, xmm2,
OR AVX10.1
single-precision floating-point value in xmm3/m32 to a
xmm3/m32{sae}
single-precision floating-point value representing
unbiased integer exponent. Stores the result to xmm1
under the writemask k1 and merge with the other
elements of xmm2.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Scalar
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Extracts the biased exponent from the normalized single precision floating-point representation of the low double-
word data element of the source operand (the third operand) as unbiased signed integer value, or convert the
denormal representation of input data to unbiased negative integer values. The integer value of the unbiased expo-
nent is converted to single precision floating-point value and written to the destination operand (the first operand)
as single precision floating-point numbers. Bits (127:32) of the XMM register destination are copied from corre-
sponding bits in the first source operand.
The destination must be a XMM register, the source operand can be a XMM register or a float32 memory location.
If writemasking is used, the low doubleword element of the destination operand is conditionally updated depending
on the value of writemask register k1. If writemasking is not used, the low doubleword element of the destination
operand is unconditionally updated.
Each GETEXP operation converts the exponent value into a floating-point number (permitting input value in
denormal representation). Special cases of input values are listed in Table 5-15.
The formula is:
GETEXP(x) = floor(log2(|x|))
Notation floor(x) stands for maximal integer not exceeding real number x.
Software usage of VGETEXPxx and VGETMANTxx instructions generally involve a combination of GETEXP operation
and GETMANT operation (see VGETMANTPD). Thus VGETEXPxx instruction do not require software to handle SIMD
floating-point exceptions.
Operation
// NormalizeExpTinySPFP(SRC[31:0]) is defined in the Operation section of VGETEXPPS
// ConvertExpSPFP(SRC[31:0]) is defined in the Operation section of VGETEXPPS
VGETEXPSS-Convert Exponents of Scalar Single Precision Floating-Point Value to Single Precision Floating-Point Value
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VGETEXPSS (EVEX encoded version)
IF k1[0] OR *no writemask*
THEN DEST[31:0] :=
ConvertExpDPFP(SRC2[31:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
DEST[31:0]:= 0
FI
FI;
ENDFOR
DEST[127:32] := SRC1[127:32]
DEST[MAXVL-1:128] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VGETEXPSS __m128 _mm_getexp_ss( __m128 a, __m128 b);
VGETEXPSS __m128 _mm_mask_getexp_ss(__m128 s, __mmask8 k, __m128 a, __m128 b);
VGETEXPSS __m128 _mm_maskz_getexp_ss( __mmask8 k, __m128 a, __m128 b);
VGETEXPSS __m128 _mm_getexp_round_ss( __m128 a, __m128 b, int sae);
VGETEXPSS __m128 _mm_mask_getexp_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int sae);
VGETEXPSS __m128 _mm_maskz_getexp_round_ss( __mmask8 k, __m128 a, __m128 b, int sae);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
See Table 2-49, “Type E3 Class Exception Conditions.”
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VGETMANTPD-Extract Float64 Vector of Normalized Mantissas From Float64 Vector
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.66.0F3A.W1 26 /r ib
A
V/V
(AVX512VL
Get Normalized Mantissa from float64 vector
VGETMANTPD xmm1 {k1}{z},
AND AVX512F)
xmm2/m128/m64bcst and store the result in xmm1,
xmm2/m128/m64bcst, imm8
OR AVX10.1
using imm8 for sign control and mantissa interval
normalization, under writemask.
EVEX.256.66.0F3A.W1 26 /r ib
A
V/V
(AVX512VL
Get Normalized Mantissa from float64 vector
VGETMANTPD ymm1 {k1}{z},
AND AVX512F)
ymm2/m256/m64bcst and store the result in ymm1,
ymm2/m256/m64bcst, imm8
OR AVX10.1
using imm8 for sign control and mantissa interval
normalization, under writemask.
EVEX.512.66.0F3A.W1 26 /r ib
A
V/V
AVX512F
Get Normalized Mantissa from float64 vector
VGETMANTPD zmm1 {k1}{z},
OR AVX10.1
zmm2/m512/m64bcst and store the result in zmm1,
zmm2/m512/m64bcst{sae},
using imm8 for sign control and mantissa interval
imm8
normalization, under writemask.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
imm8
N/A
Description
Convert double precision floating values in the source operand (the second operand) to double precision floating-
point values with the mantissa normalization and sign control specified by the imm8 byte, see Figure 5-15. The
converted results are written to the destination operand (the first operand) using writemask k1. The normalized
mantissa is specified by interv (imm8[1:0]) and the sign control (sc) is specified by bits 3:2 of the immediate byte.
The destination operand is a ZMM/YMM/XMM register updated under the writemask. The source operand can be a
ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 64-
bit memory location.
7
6
5
4
3
2
1
0
imm8
Must Be Zero
Sign Control (SC)
Normaiization Interval
Imm8[1:0] = 00b : Interval is [ 1, 2)
Imm8[3:2] = 00b : sign(SRC)
Imm8[1:0] = 01b : Interval is [1/2, 2)
Imm8[3:2] = 01b : 0
Imm8[1:0] = 10b : Interval is [ 1/2, 1)
Imm8[3] = 1b : qNan_Indefinite if sign(SRC) != 0, regardless of imm8[2].
Imm8[1:0] = 11b : Interval is [3/4, 3/2)
Figure 5-15. Imm8 Controls for VGETMANTPD/SD/PS/SS
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For each input double precision floating-point value x, The conversion operation is:
GetMant(x) = ±2k|x.significand|
where:
1 <= |x.significand| < 2
Unbiased exponent k can be either 0 or -1, depending on the interval range defined by interv, the range of the
significand and whether the exponent of the source is even or odd. The sign of the final result is determined by sc
and the source sign. The encoded value of imm8[1:0] and sign control are shown in Figure 5-15.
Each converted double precision floating-point result is encoded according to the sign control, the unbiased expo-
nent k (adding bias) and a mantissa normalized to the range specified by interv.
The GetMant() function follows Table 5-16 when dealing with floating-point special numbers.
This instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1
are computed and stored into the destination. Elements in zmm1 with the corresponding bit clear in k1 retain their
previous values.
Note: EVEX.vvvv is reserved and must be 1111b; otherwise instructions will #UD.
Table 5-16. GetMant() Special Float Values Behavior
Input
Result
Exceptions / Comments
NaN
QNaN(SRC)
Ignore interv
If (SRC = SNaN) then #IE
+∞
1.0
Ignore interv
+0
1.0
Ignore interv
-0
IF (SC[0]) THEN +1.0
Ignore interv
ELSE -1.0
-∞
IF (SC[1]) THEN {QNaN_Indefinite}
Ignore interv
ELSE {
If (SC[1]) then #IE
IF (SC[0]) THEN +1.0
ELSE -1.0
negative
SC[1] ? QNaN_Indefinite : Getmant(SRC)1
If (SC[1]) then #IE
NOTES:
1. In case SC[1]==0, the sign of Getmant(SRC) is declared according to SC[0].
Operation
def getmant_fp64(src, sign_control, normalization_interval):
bias := 1023
dst.sign := sign_control[0] ? 0 : src.sign
signed_one := sign_control[0] ? +1.0 : -1.0
dst.exp := src.exp
dst.fraction := src.fraction
zero := (dst.exp = 0) and ((dst.fraction = 0) or (MXCSR.DAZ=1))
denormal := (dst.exp = 0) and (dst.fraction != 0) and (MXCSR.DAZ=0)
infinity := (dst.exp = 0x7FF) and (dst.fraction = 0)
nan := (dst.exp = 0x7FF) and (dst.fraction != 0)
src_signaling := src.fraction[51]
snan := nan and (src_signaling = 0)
positive := (src.sign = 0)
negative := (src.sign = 1)
if nan:
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if snan:
MXCSR.IE := 1
return qnan(src)
if positive and (zero or infinity):
return 1.0
if negative:
if zero:
return signed_one
if infinity:
if sign_control[1]:
MXCSR.IE := 1
return QNaN_Indefinite
return signed_one
if sign_control[1]:
MXCSR.IE := 1
return QNaN_Indefinite
if denormal:
jbit := 0
dst.exp := bias
while jbit = 0:
jbit := dst.fraction[51]
dst.fraction := dst.fraction << 1
dst.exp : = dst.exp - 1
MXCSR.DE := 1
unbiased_exp := dst.exp - bias
odd_exp := unbiased_exp[0]
signaling_bit := dst.fraction[51]
if normalization_interval = 0b00:
dst.exp := bias
else if normalization_interval = 0b01:
dst.exp := odd_exp ? bias-1 : bias
else if normalization_interval = 0b10:
dst.exp := bias-1
else if normalization_interval = 0b11:
dst.exp := signaling_bit ? bias-1 : bias
return dst
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VGETMANTPD (EVEX Encoded Versions)
VGETMANTPD dest{k1}, src, imm8
VL = 128, 256, or 512
KL := VL / 64
sign_control := imm8[3:2]
normalization_interval := imm8[1:0]
FOR i := 0 to KL-1:
IF k1[i] or *no writemask*:
IF SRC is memory and (EVEX.b = 1):
tsrc := src.double[0]
ELSE:
tsrc := src.double[i]
DEST.double[i] := getmant_fp64(tsrc, sign_control, normalization_interval)
ELSE IF *zeroing*:
DEST.double[i] := 0
//else DEST.double[i] remains unchanged
DEST[MAX_VL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VGETMANTPD __m512d _mm512_getmant_pd( __m512d a, enum intv, enum sgn);
VGETMANTPD __m512d _mm512_mask_getmant_pd(__m512d s, __mmask8 k, __m512d a, enum intv, enum sgn);
VGETMANTPD __m512d _mm512_maskz_getmant_pd( __mmask8 k, __m512d a, enum intv, enum sgn);
VGETMANTPD __m512d _mm512_getmant_round_pd( __m512d a, enum intv, enum sgn, int r);
VGETMANTPD __m512d _mm512_mask_getmant_round_pd(__m512d s, __mmask8 k, __m512d a, enum intv, enum sgn, int r);
VGETMANTPD __m512d _mm512_maskz_getmant_round_pd( __mmask8 k, __m512d a, enum intv, enum sgn, int r);
VGETMANTPD __m256d _mm256_getmant_pd( __m256d a, enum intv, enum sgn);
VGETMANTPD __m256d _mm256_mask_getmant_pd(__m256d s, __mmask8 k, __m256d a, enum intv, enum sgn);
VGETMANTPD __m256d _mm256_maskz_getmant_pd( __mmask8 k, __m256d a, enum intv, enum sgn);
VGETMANTPD __m128d _mm_getmant_pd( __m128d a, enum intv, enum sgn);
VGETMANTPD __m128d _mm_mask_getmant_pd(__m128d s, __mmask8 k, __m128d a, enum intv, enum sgn);
VGETMANTPD __m128d _mm_maskz_getmant_pd( __mmask8 k, __m128d a, enum intv, enum sgn);
SIMD Floating-Point Exceptions
Denormal, Invalid.
Other Exceptions
See Table 2-48, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
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VGETMANTPH-Extract FP16 Vector of Normalized Mantissas from FP16 Vector
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.NP.0F3A.W0 26 /r /ib
A
V/V
(AVX512_FP16
Get normalized mantissa from FP16 vector
VGETMANTPH xmm1{k1}{z},
AND AVX512VL)
xmm2/m128/m16bcst and store the result in
xmm2/m128/m16bcst, imm8
OR AVX10.1
xmm1, using imm8 for sign control and mantissa
interval normalization, subject to writemask k1.
EVEX.256.NP.0F3A.W0 26 /r /ib
A
V/V
(AVX512_FP16
Get normalized mantissa from FP16 vector
VGETMANTPH ymm1{k1}{z},
AND AVX512VL)
ymm2/m256/m16bcst and store the result in
ymm2/m256/m16bcst, imm8
OR AVX10.1
ymm1, using imm8 for sign control and mantissa
interval normalization, subject to writemask k1.
EVEX.512.NP.0F3A.W0 26 /r /ib
A
V/V
AVX512_FP16
Get normalized mantissa from FP16 vector
VGETMANTPH zmm1{k1}{z},
OR AVX10.1
zmm2/m512/m16bcst and store the result in
zmm2/m512/m16bcst {sae}, imm8
zmm1, using imm8 for sign control and mantissa
interval normalization, subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
imm8 (r)
N/A
Description
This instruction converts the FP16 values in the source operand (the second operand) to FP16 values with the
mantissa normalization and sign control specified by the imm8 byte, see Table 5-17. The converted results are
written to the destination operand (the first operand) using writemask k1. The normalized mantissa is specified by
interv (imm8[1:0]) and the sign control (SC) is specified by bits 3:2 of the immediate byte.
The destination elements are updated according to the writemask.
Table 5-17. imm8 Controls for VGETMANTPH/VGETMANTSH
imm8 Bits
Definition
imm8[7:4]
Must be zero.
imm8[3:2]
Sign Control (SC)
0b00: Sign(SRC)
0b01: 0
0b1x: QNaN_Indefinite if sign(SRC)!=0
imm8[1:0]
Interv
0b00: Interval is [1, 2)
0b01: Interval is [1/2, 2)
0b10: Interval is [1/2, 1)
0b11: Interval is [3/4, 3/2)
For each input FP16 value x, The conversion operation is:
GetMant(x) = ±2k|x.significand|
where:
1 ≤ |x.significand| < 2
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Unbiased exponent k depends on the interval range defined by interv and whether the exponent of the source is
even or odd. The sign of the final result is determined by the sign control and the source sign and the leading frac-
tion bit.
The encoded value of imm8[1:0] and sign control are shown in Table 5-17.
Each converted FP16 result is encoded according to the sign control, the unbiased exponent k (adding bias) and a
mantissa normalized to the range specified by interv.
The GetMant() function follows Table 5-18 when dealing with floating-point special numbers.
Table 5-18. GetMant() Special Float Values Behavior
Input
Result
Exceptions / Comments
NaN
QNaN(SRC)
Ignore interv.
If (SRC = SNaN), then #IE.
+∞
1.0
Ignore interv.
+0
1.0
Ignore interv.
-0
IF (SC[0]) THEN +1.0
Ignore interv.
ELSE -1.0
-∞
IF (SC[1]) THEN {QNaN_Indefinite}
Ignore interv.
ELSE {
If (SC[1]), then #IE.
IF (SC[0]) THEN +1.0
ELSE -1.0
negative
SC[1] ? QNaN_Indefinite : Getmant(SRC)1
If (SC[1]), then #IE.
NOTES:
1. In case SC[1]==0, the sign of Getmant(SRC) is declared according to SC[0].
Operation
def getmant_fp16(src, sign_control, normalization_interval):
bias := 15
dst.sign := sign_control[0] ? 0 : src.sign
signed_one := sign_control[0] ? +1.0 : -1.0
dst.exp := src.exp
dst.fraction := src.fraction
zero := (dst.exp = 0) and (dst.fraction = 0)
denormal := (dst.exp = 0) and (dst.fraction != 0)
infinity := (dst.exp = 0x1F) and (dst.fraction = 0)
nan := (dst.exp = 0x1F) and (dst.fraction != 0)
src_signaling := src.fraction[9]
snan := nan and (src_signaling = 0)
positive := (src.sign = 0)
negative := (src.sign = 1)
if nan:
if snan:
MXCSR.IE := 1
return qnan(src)
if positive and (zero or infinity):
return 1.0
if negative:
if zero:
return signed_one
if infinity:
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if sign_control[1]:
MXCSR.IE := 1
return QNaN_Indefinite
return signed_one
if sign_control[1]:
MXCSR.IE := 1
return QNaN_Indefinite
if denormal:
jbit := 0
dst.exp := bias
// set exponent to bias value
while jbit = 0:
jbit := dst.fraction[9]
dst.fraction := dst.fraction << 1
dst.exp : = dst.exp - 1
MXCSR.DE := 1
unbaiased_exp := dst.exp - bias
odd_exp := unbaiased_exp[0]
signaling_bit := dst.fraction[9]
if normalization_interval = 0b00:
dst.exp := bias
else if normalization_interval = 0b01:
dst.exp := odd_exp ? bias-1 : bias
else if normalization_interval = 0b10:
dst.exp := bias-1
else if normalization_interval = 0b11:
dst.exp := signaling_bit ? bias-1 : bias
return dst
VGETMANTPH dest{k1}, src, imm8
VL = 128, 256 or 512
KL := VL/16
sign_control := imm8[3:2]
normalization_interval := imm8[1:0]
FOR i := 0 to KL-1:
IF k1[i] or *no writemask*:
IF SRC is memory and (EVEX.b = 1):
tsrc := src.fp16[0]
ELSE:
tsrc := src.fp16[i]
DEST.fp16[i] := getmant_fp16(tsrc, sign_control, normalization_interval)
ELSE IF *zeroing*:
DEST.fp16[i] := 0
//else DEST.fp16[i] remains unchanged
DEST[MAXVL-1:VL] := 0
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Intel C/C++ Compiler Intrinsic Equivalent
VGETMANTPH __m128h _mm_getmant_ph (__m128h a, _MM_MANTISSA_NORM_ENUM norm, _MM_MANTISSA_SIGN_ENUM sign);
VGETMANTPH __m128h _mm_mask_getmant_ph (__m128h src, __mmask8 k, __m128h a, _MM_MANTISSA_NORM_ENUM norm,
_MM_MANTISSA_SIGN_ENUM sign);
VGETMANTPH __m128h _mm_maskz_getmant_ph (__mmask8 k, __m128h a, _MM_MANTISSA_NORM_ENUM norm,
_MM_MANTISSA_SIGN_ENUM sign);
VGETMANTPH __m256h _mm256_getmant_ph (__m256h a, _MM_MANTISSA_NORM_ENUM norm, _MM_MANTISSA_SIGN_ENUM sign);
VGETMANTPH __m256h _mm256_mask_getmant_ph (__m256h src, __mmask16 k, __m256h a, _MM_MANTISSA_NORM_ENUM norm,
_MM_MANTISSA_SIGN_ENUM sign);
VGETMANTPH __m256h _mm256_maskz_getmant_ph (__mmask16 k, __m256h a, _MM_MANTISSA_NORM_ENUM norm,
_MM_MANTISSA_SIGN_ENUM sign);
VGETMANTPH __m512h _mm512_getmant_ph (__m512h a, _MM_MANTISSA_NORM_ENUM norm, _MM_MANTISSA_SIGN_ENUM sign);
VGETMANTPH __m512h _mm512_mask_getmant_ph (__m512h src, __mmask32 k, __m512h a, _MM_MANTISSA_NORM_ENUM norm,
_MM_MANTISSA_SIGN_ENUM sign);
VGETMANTPH __m512h _mm512_maskz_getmant_ph (__mmask32 k, __m512h a, _MM_MANTISSA_NORM_ENUM norm,
_MM_MANTISSA_SIGN_ENUM sign);
VGETMANTPH __m512h _mm512_getmant_round_ph (__m512h a, _MM_MANTISSA_NORM_ENUM norm,
_MM_MANTISSA_SIGN_ENUM sign, const int sae);
VGETMANTPH __m512h _mm512_mask_getmant_round_ph (__m512h src, __mmask32 k, __m512h a, _MM_MANTISSA_NORM_ENUM
norm, _MM_MANTISSA_SIGN_ENUM sign, const int sae);
VGETMANTPH __m512h _mm512_maskz_getmant_round_ph (__mmask32 k, __m512h a, _MM_MANTISSA_NORM_ENUM norm,
_MM_MANTISSA_SIGN_ENUM sign, const int sae);
SIMD Floating-Point Exceptions
Invalid, Denormal.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
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VGETMANTPS-Extract Float32 Vector of Normalized Mantissas From Float32 Vector
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.128.66.0F3A.W0 26 /r ib
A
V/V
(AVX512VL
Get normalized mantissa from float32 vector
VGETMANTPS xmm1 {k1}{z},
AND AVX512F)
xmm2/m128/m32bcst and store the result in xmm1, using
xmm2/m128/m32bcst, imm8
OR AVX10.1
imm8 for sign control and mantissa interval normalization,
under writemask.
EVEX.256.66.0F3A.W0 26 /r ib
A
V/V
(AVX512VL
Get normalized mantissa from float32 vector
VGETMANTPS ymm1 {k1}{z},
AND AVX512F)
ymm2/m256/m32bcst and store the result in ymm1, using
ymm2/m256/m32bcst, imm8
OR AVX10.1
imm8 for sign control and mantissa interval normalization,
under writemask.
EVEX.512.66.0F3A.W0 26 /r ib
A
V/V
AVX512F
Get normalized mantissa from float32 vector
VGETMANTPS zmm1 {k1}{z},
OR AVX10.1
zmm2/m512/m32bcst and store the result in zmm1, using
zmm2/m512/m32bcst{sae},
imm8 for sign control and mantissa interval normalization,
imm8
under writemask.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
imm8
N/A
Description
Convert single precision floating values in the source operand (the second operand) to single precision floating-
point values with the mantissa normalization and sign control specified by the imm8 byte, see Figure 5-15. The
converted results are written to the destination operand (the first operand) using writemask k1. The normalized
mantissa is specified by interv (imm8[1:0]) and the sign control (sc) is specified by bits 3:2 of the immediate byte.
The destination operand is a ZMM/YMM/XMM register updated under the writemask. The source operand can be a
ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 32-
bit memory location.
For each input single precision floating-point value x, The conversion operation is:
GetMant(x) = ±2k|x.significand|
where:
1 <= |x.significand| < 2
Unbiased exponent k can be either 0 or -1, depending on the interval range defined by interv, the range of the
significand and whether the exponent of the source is even or odd. The sign of the final result is determined by sc
and the source sign. The encoded value of imm8[1:0] and sign control are shown in Figure 5-15.
Each converted single precision floating-point result is encoded according to the sign control, the unbiased expo-
nent k (adding bias) and a mantissa normalized to the range specified by interv.
The GetMant() function follows Table 5-16 when dealing with floating-point special numbers.
This instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1
are computed and stored into the destination. Elements in zmm1 with the corresponding bit clear in k1 retain their
previous values.
Note: EVEX.vvvv is reserved and must be 1111b, VEX.L must be 0; otherwise instructions will #UD.
VGETMANTPS-Extract Float32 Vector of Normalized Mantissas From Float32 Vector
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Operation
def getmant_fp32(src, sign_control, normalization_interval):
bias := 127
dst.sign := sign_control[0] ? 0 : src.sign
signed_one := sign_control[0] ? +1.0 : -1.0
dst.exp := src.exp
dst.fraction := src.fraction
zero := (dst.exp = 0) and ((dst.fraction = 0) or (MXCSR.DAZ=1))
denormal := (dst.exp = 0) and (dst.fraction != 0) and (MXCSR.DAZ=0)
infinity := (dst.exp = 0xFF) and (dst.fraction = 0)
nan := (dst.exp = 0xFF) and (dst.fraction != 0)
src_signaling := src.fraction[22]
snan := nan and (src_signaling = 0)
positive := (src.sign = 0)
negative := (src.sign = 1)
if nan:
if snan:
MXCSR.IE := 1
return qnan(src)
if positive and (zero or infinity):
return 1.0
if negative:
if zero:
return signed_one
if infinity:
if sign_control[1]:
MXCSR.IE := 1
return QNaN_Indefinite
return signed_one
if sign_control[1]:
MXCSR.IE := 1
return QNaN_Indefinite
if denormal:
jbit := 0
dst.exp := bias
while jbit = 0:
jbit := dst.fraction[22]
dst.fraction := dst.fraction << 1
dst.exp : = dst.exp - 1
MXCSR.DE := 1
unbiased_exp := dst.exp - bias
odd_exp := unbiased_exp[0]
signaling_bit := dst.fraction[22]
if normalization_interval = 0b00:
dst.exp := bias
else if normalization_interval = 0b01:
dst.exp := odd_exp ? bias-1 : bias
else if normalization_interval = 0b10:
dst.exp := bias-1
else if normalization_interval = 0b11:
dst.exp := signaling_bit ? bias-1 : bias
VGETMANTPS-Extract Float32 Vector of Normalized Mantissas From Float32 Vector
Vol. 2C
5-398
return dst
VGETMANTPS (EVEX encoded versions)
VGETMANTPS dest{k1}, src, imm8
VL = 128, 256, or 512
KL := VL / 32
sign_control := imm8[3:2]
normalization_interval := imm8[1:0]
FOR i := 0 to KL-1:
IF k1[i] or *no writemask*:
IF SRC is memory and (EVEX.b = 1):
tsrc := src.float[0]
ELSE:
tsrc := src.float[i]
DEST.float[i] := getmant_fp32(tsrc, sign_control, normalization_interval)
ELSE IF *zeroing*:
DEST.float[i] := 0
//else DEST.float[i] remains unchanged
DEST[MAX_VL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VGETMANTPS __m512 _mm512_getmant_ps( __m512 a, enum intv, enum sgn);
VGETMANTPS __m512 _mm512_mask_getmant_ps(__m512 s, __mmask16 k, __m512 a, enum intv, enum sgn;
VGETMANTPS __m512 _mm512_maskz_getmant_ps(__mmask16 k, __m512 a, enum intv, enum sgn);
VGETMANTPS __m512 _mm512_getmant_round_ps( __m512 a, enum intv, enum sgn, int r);
VGETMANTPS __m512 _mm512_mask_getmant_round_ps(__m512 s, __mmask16 k, __m512 a, enum intv, enum sgn, int r);
VGETMANTPS __m512 _mm512_maskz_getmant_round_ps(__mmask16 k, __m512 a, enum intv, enum sgn, int r);
VGETMANTPS __m256 _mm256_getmant_ps( __m256 a, enum intv, enum sgn);
VGETMANTPS __m256 _mm256_mask_getmant_ps(__m256 s, __mmask8 k, __m256 a, enum intv, enum sgn);
VGETMANTPS __m256 _mm256_maskz_getmant_ps( __mmask8 k, __m256 a, enum intv, enum sgn);
VGETMANTPS __m128 _mm_getmant_ps( __m128 a, enum intv, enum sgn);
VGETMANTPS __m128 _mm_mask_getmant_ps(__m128 s, __mmask8 k, __m128 a, enum intv, enum sgn);
VGETMANTPS __m128 _mm_maskz_getmant_ps( __mmask8 k, __m128 a, enum intv, enum sgn);
SIMD Floating-Point Exceptions
Denormal, Invalid.
Other Exceptions
See Table 2-48, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VGETMANTPS-Extract Float32 Vector of Normalized Mantissas From Float32 Vector
Vol. 2C
5-399
VGETMANTSD-Extract Float64 of Normalized Mantissa From Float64 Scalar
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
Bit Mode
Feature Flag
Support
EVEX.LLIG.66.0F3A.W1 27 /r ib
A
V/V
AVX512F
Extract the normalized mantissa of the low float64
VGETMANTSD xmm1 {k1}{z}, xmm2,
OR AVX10.1
element in xmm3/m64 using imm8 for sign control
xmm3/m64{sae}, imm8
and mantissa interval normalization. Store the
mantissa to xmm1 under the writemask k1 and
merge with the other elements of xmm2.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Scalar
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Convert the double precision floating values in the low quadword element of the second source operand (the third
operand) to double precision floating-point value with the mantissa normalization and sign control specified by the
imm8 byte, see Figure 5-15. The converted result is written to the low quadword element of the destination
operand (the first operand) using writemask k1. Bits (127:64) of the XMM register destination are copied from
corresponding bits in the first source operand. The normalized mantissa is specified by interv (imm8[1:0]) and the
sign control (sc) is specified by bits 3:2 of the immediate byte.
The conversion operation is:
GetMant(x) = ±2k|x.significand|
where:
1 <= |x.significand| < 2
Unbiased exponent k can be either 0 or -1, depending on the interval range defined by interv, the range of the
significand and whether the exponent of the source is even or odd. The sign of the final result is determined by sc
and the source sign. The encoded value of imm8[1:0] and sign control are shown in Figure 5-15.
The converted double precision floating-point result is encoded according to the sign control, the unbiased expo-
nent k (adding bias) and a mantissa normalized to the range specified by interv.
The GetMant() function follows Table 5-16 when dealing with floating-point special numbers.
If writemasking is used, the low quadword element of the destination operand is conditionally updated depending
on the value of writemask register k1. If writemasking is not used, the low quadword element of the destination
operand is unconditionally updated.
VGETMANTSD-Extract Float64 of Normalized Mantissa From Float64 Scalar
Vol. 2C
5-400
Operation
// getmant_fp64(src, sign_control, normalization_interval) is defined in the operation section of VGETMANTPD
VGETMANTSD (EVEX encoded version)
SignCtrl[1:0] := IMM8[3:2];
Interv[1:0] := IMM8[1:0];
IF k1[0] OR *no writemask*
THEN DEST[63:0] :=
getmant_fp64(src, sign_control, normalization_interval)
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
DEST[63:0] := 0
FI
FI;
DEST[127:64] := SRC1[127:64]
DEST[MAXVL-1:128] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VGETMANTSD __m128d _mm_getmant_sd( __m128d a, __m128 b, enum intv, enum sgn);
VGETMANTSD __m128d _mm_mask_getmant_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, enum intv, enum sgn);
VGETMANTSD __m128d _mm_maskz_getmant_sd( __mmask8 k, __m128 a, __m128d b, enum intv, enum sgn);
VGETMANTSD __m128d _mm_getmant_round_sd( __m128d a, __m128 b, enum intv, enum sgn, int r);
VGETMANTSD __m128d _mm_mask_getmant_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, enum intv, enum sgn, int r);
VGETMANTSD __m128d _mm_maskz_getmant_round_sd( __mmask8 k, __m128d a, __m128d b, enum intv, enum sgn, int r);
SIMD Floating-Point Exceptions
Denormal, Invalid
Other Exceptions
See Table 2-49, “Type E3 Class Exception Conditions.”
VGETMANTSD-Extract Float64 of Normalized Mantissa From Float64 Scalar
Vol. 2C
5-401
VGETMANTSH-Extract FP16 of Normalized Mantissa from FP16 Scalar
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
EVEX.LLIG.NP.0F3A.W0 27 /r /ib
A
V/V
AVX512_FP16
Extract the normalized mantissa of the low FP16
VGETMANTSH xmm1{k1}{z}, xmm2,
OR AVX10.1
element in xmm3/m16 using imm8 for sign
xmm3/m16 {sae}, imm8
control and mantissa interval normalization. Store
the mantissa to xmm1 subject to writemask k1
and merge with the other elements of xmm2. Bits
127:16 of xmm2 are copied to xmm1[127:16].
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
imm8 (r)
Description
This instruction converts the FP16 value in the low element of the second source operand to FP16 values with the
mantissa normalization and sign control specified by the imm8 byte, see Table 5-17. The converted result is written
to the low element of the destination operand using writemask k1. The normalized mantissa is specified by interv
(imm8[1:0]) and the sign control (SC) is specified by bits 3:2 of the immediate byte.
Bits 127:16 of the destination operand are copied from the corresponding bits of the first source operand. Bits
MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the destination is updated according
to the writemask.
For each input FP16 value x, The conversion operation is:
GetMant(x) = ±2k|x.significand|
where:
1 ≤ |x.significand| < 2
Unbiased exponent k depends on the interval range defined by interv and whether the exponent of the source is
even or odd. The sign of the final result is determined by the sign control and the source sign and the leading frac-
tion bit.
The encoded value of imm8[1:0] and sign control are shown in Table 5-17.
Each converted FP16 result is encoded according to the sign control, the unbiased exponent k (adding bias) and a
mantissa normalized to the range specified by interv.
The GetMant() function follows Table 5-18 when dealing with floating-point special numbers.
VGETMANTSH-Extract FP16 of Normalized Mantissa from FP16 Scalar
Vol. 2C
5-402
Operation
VGETMANTSH dest{k1}, src1, src2, imm8
sign_control := imm8[3:2]
normalization_interval := imm8[1:0]
IF k1[0] or *no writemask*:
dest.fp16[0] := getmant_fp16(src2.fp16[0],
// see VGETMANTPH
sign_control,
normalization_interval)
ELSE IF *zeroing*:
dest.fp16[0] := 0
//else dest.fp16[0] remains unchanged
DEST[127:16] := src1[127:16]
DEST[MAXVL-1:128] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VGETMANTSH __m128h _mm_getmant_round_sh (__m128h a, __m128h b, _MM_MANTISSA_NORM_ENUM norm,
_MM_MANTISSA_SIGN_ENUM sign, const int sae);
VGETMANTSH __m128h _mm_mask_getmant_round_sh (__m128h src, __mmask8 k, __m128h a, __m128h b,
_MM_MANTISSA_NORM_ENUM norm, _MM_MANTISSA_SIGN_ENUM sign, const int sae);
VGETMANTSH __m128h _mm_maskz_getmant_round_sh (__mmask8 k, __m128h a, __m128h b, _MM_MANTISSA_NORM_ENUM norm,
_MM_MANTISSA_SIGN_ENUM sign, const int sae);
VGETMANTSH __m128h _mm_getmant_sh (__m128h a, __m128h b, _MM_MANTISSA_NORM_ENUM norm,
_MM_MANTISSA_SIGN_ENUM sign);
VGETMANTSH __m128h _mm_mask_getmant_sh (__m128h src, __mmask8 k, __m128h a, __m128h b, _MM_MANTISSA_NORM_ENUM
norm, _MM_MANTISSA_SIGN_ENUM sign);
VGETMANTSH __m128h _mm_maskz_getmant_sh (__mmask8 k, __m128h a, __m128h b, _MM_MANTISSA_NORM_ENUM norm,
_MM_MANTISSA_SIGN_ENUM sign);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
EVEX-encoded instructions, see Table 2-49, “Type E3 Class Exception Conditions.”
VGETMANTSH-Extract FP16 of Normalized Mantissa from FP16 Scalar
Vol. 2C
5-403
VGETMANTSS-Extract Float32 Vector of Normalized Mantissa From Float32 Scalar
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
Bit Mode
Feature Flag
Support
EVEX.LLIG.66.0F3A.W0 27 /r ib
A
V/V
AVX512F
Extract the normalized mantissa from the low float32
VGETMANTSS xmm1 {k1}{z}, xmm2,
OR AVX10.1
element of xmm3/m32 using imm8 for sign control
xmm3/m32{sae}, imm8
and mantissa interval normalization, store the
mantissa to xmm1 under the writemask k1 and merge
with the other elements of xmm2.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Scalar
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Convert the single precision floating values in the low doubleword element of the second source operand (the third
operand) to single precision floating-point value with the mantissa normalization and sign control specified by the
imm8 byte, see Figure 5-15. The converted result is written to the low doubleword element of the destination
operand (the first operand) using writemask k1. Bits (127:32) of the XMM register destination are copied from
corresponding bits in the first source operand. The normalized mantissa is specified by interv (imm8[1:0]) and the
sign control (sc) is specified by bits 3:2 of the immediate byte.
The conversion operation is:
GetMant(x) = ±2k|x.significand|
where:
1 <= |x.significand| < 2
Unbiased exponent k can be either 0 or -1, depending on the interval range defined by interv, the range of the
significand and whether the exponent of the source is even or odd. The sign of the final result is determined by sc
and the source sign. The encoded value of imm8[1:0] and sign control are shown in Figure 5-15.
The converted single precision floating-point result is encoded according to the sign control, the unbiased exponent
k (adding bias) and a mantissa normalized to the range specified by interv.
The GetMant() function follows Table 5-16 when dealing with floating-point special numbers.
If writemasking is used, the low doubleword element of the destination operand is conditionally updated depending
on the value of writemask register k1. If writemasking is not used, the low doubleword element of the destination
operand is unconditionally updated.
VGETMANTSS-Extract Float32 Vector of Normalized Mantissa From Float32 Scalar
Vol. 2C
5-404
Operation
// getmant_fp32(src, sign_control, normalization_interval) is defined in the operation section of VGETMANTPS
VGETMANTSS (EVEX encoded version)
SignCtrl[1:0] := IMM8[3:2];
Interv[1:0] := IMM8[1:0];
IF k1[0] OR *no writemask*
THEN DEST[31:0] :=
getmant_fp32(src, sign_control, normalization_interval)
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
DEST[31:0] := 0
FI
FI;
DEST[127:32] := SRC1[127:32]
DEST[MAXVL-1:128] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VGETMANTSS __m128 _mm_getmant_ss( __m128 a, __m128 b, enum intv, enum sgn);
VGETMANTSS __m128 _mm_mask_getmant_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn);
VGETMANTSS __m128 _mm_maskz_getmant_ss( __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn);
VGETMANTSS __m128 _mm_getmant_round_ss( __m128 a, __m128 b, enum intv, enum sgn, int r);
VGETMANTSS __m128 _mm_mask_getmant_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn, int r);
VGETMANTSS __m128 _mm_maskz_getmant_round_ss( __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn, int r);
SIMD Floating-Point Exceptions
Denormal, Invalid
Other Exceptions
See Table 2-49, “Type E3 Class Exception Conditions.”
VGETMANTSS-Extract Float32 Vector of Normalized Mantissa From Float32 Scalar
Vol. 2C
5-405
VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4-Insert Packed
Floating-Point Values
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
VEX.256.66.0F3A.W0 18 /r ib
A
V/V
AVX
Insert 128 bits of packed floating-point values
VINSERTF128 ymm1, ymm2,
from xmm3/m128 and the remaining values
xmm3/m128, imm8
from ymm2 into ymm1.
EVEX.256.66.0F3A.W0 18 /r ib
C
V/V
(AVX512VL AND
Insert 128 bits of packed single-precision
VINSERTF32X4 ymm1 {k1}{z}, ymm2,
AVX512F) OR
floating-point values from xmm3/m128 and the
xmm3/m128, imm8
AVX10.1
remaining values from ymm2 into ymm1 under
writemask k1.
EVEX.512.66.0F3A.W0 18 /r ib
C
V/V
AVX512F
Insert 128 bits of packed single-precision
VINSERTF32X4 zmm1 {k1}{z}, zmm2,
OR AVX10.1
floating-point values from xmm3/m128 and the
xmm3/m128, imm8
remaining values from zmm2 into zmm1 under
writemask k1.
EVEX.256.66.0F3A.W1 18 /r ib
B
V/V
(AVX512VL AND
Insert 128 bits of packed double precision
VINSERTF64X2 ymm1 {k1}{z}, ymm2,
AVX512DQ) OR
floating-point values from xmm3/m128 and the
xmm3/m128, imm8
AVX10.1
remaining values from ymm2 into ymm1 under
writemask k1.
EVEX.512.66.0F3A.W1 18 /r ib
B
V/V
AVX512DQ
Insert 128 bits of packed double precision
VINSERTF64X2 zmm1 {k1}{z}, zmm2,
OR AVX10.1
floating-point values from xmm3/m128 and the
xmm3/m128, imm8
remaining values from zmm2 into zmm1 under
writemask k1.
EVEX.512.66.0F3A.W0 1A /r ib
D
V/V
AVX512DQ
Insert 256 bits of packed single-precision
VINSERTF32X8 zmm1 {k1}{z}, zmm2,
OR AVX10.1
floating-point values from ymm3/m256 and the
ymm3/m256, imm8
remaining values from zmm2 into zmm1 under
writemask k1.
EVEX.512.66.0F3A.W1 1A /r ib
C
V/V
AVX512F
Insert 256 bits of packed double precision
VINSERTF64X4 zmm1 {k1}{z}, zmm2,
OR AVX10.1
floating-point values from ymm3/m256 and the
ymm3/m256, imm8
remaining values from zmm2 into zmm1 under
writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
imm8
B
Tuple2
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
imm8
C
Tuple4
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
imm8
D
Tuple8
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
imm8
Description
VINSERTF128/VINSERTF32x4 and VINSERTF64x2 insert 128-bits of packed floating-point values from the second
source operand (the third operand) into the destination operand (the first operand) at an 128-bit granularity offset
multiplied by imm8[0] (256-bit) or imm8[1:0]. The remaining portions of the destination operand are copied from
the corresponding fields of the first source operand (the second operand). The second source operand can be either
an XMM register or a 128-bit memory location. The destination and first source operands are vector registers.
VINSERTF32x4: The destination operand is a ZMM/YMM register and updated at 32-bit granularity according to the
writemask. The high 6/7 bits of the immediate are ignored.
VINSERTF64x2: The destination operand is a ZMM/YMM register and updated at 64-bit granularity according to the
writemask. The high 6/7 bits of the immediate are ignored.
VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4-Insert Packed Floating-Point Values
Vol. 2C
5-406
VINSERTF32x8 and VINSERTF64x4 inserts 256-bits of packed floating-point values from the second source operand
(the third operand) into the destination operand (the first operand) at a 256-bit granular offset multiplied by
imm8[0]. The remaining portions of the destination are copied from the corresponding fields of the first source
operand (the second operand). The second source operand can be either an YMM register or a 256-bit memory
location. The high 7 bits of the immediate are ignored. The destination operand is a ZMM register and updated at
32/64-bit granularity according to the writemask.
Operation
VINSERTF32x4 (EVEX encoded versions)
(KL, VL) = (8, 256), (16, 512)
TEMP_DEST[VL-1:0] := SRC1[VL-1:0]
IF VL = 256
CASE (imm8[0]) OF
0: TMP_DEST[127:0] := SRC2[127:0]
1: TMP_DEST[255:128] := SRC2[127:0]
ESAC.
FI;
IF VL = 512
CASE (imm8[1:0]) OF
00: TMP_DEST[127:0] := SRC2[127:0]
01: TMP_DEST[255:128] := SRC2[127:0]
10: TMP_DEST[383:256] := SRC2[127:0]
11: TMP_DEST[511:384] := SRC2[127:0]
ESAC.
FI;
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4-Insert Packed Floating-Point Values
Vol. 2C
5-407
VINSERTF64x2 (EVEX encoded versions)
(KL, VL) = (4, 256), (8, 512)
TEMP_DEST[VL-1:0] := SRC1[VL-1:0]
IF VL = 256
CASE (imm8[0]) OF
0: TMP_DEST[127:0] := SRC2[127:0]
1: TMP_DEST[255:128] := SRC2[127:0]
ESAC.
FI;
IF VL = 512
CASE (imm8[1:0]) OF
00: TMP_DEST[127:0] := SRC2[127:0]
01: TMP_DEST[255:128] := SRC2[127:0]
10: TMP_DEST[383:256] := SRC2[127:0]
11: TMP_DEST[511:384] := SRC2[127:0]
ESAC.
FI;
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] := TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VINSERTF32x8 (EVEX.U1.512 encoded version)
TEMP_DEST[VL-1:0] := SRC1[VL-1:0]
CASE (imm8[0]) OF
0: TMP_DEST[255:0] := SRC2[255:0]
1: TMP_DEST[511:256] := SRC2[255:0]
ESAC.
FOR j := 0 TO 15
i := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4-Insert Packed Floating-Point Values
Vol. 2C
5-408
VINSERTF64x4 (EVEX.512 encoded version)
VL = 512
TEMP_DEST[VL-1:0] := SRC1[VL-1:0]
CASE (imm8[0]) OF
0: TMP_DEST[255:0] := SRC2[255:0]
1: TMP_DEST[511:256] := SRC2[255:0]
ESAC.
FOR j := 0 TO 7
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] := TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VINSERTF128 (VEX encoded version)
TEMP[255:0] := SRC1[255:0]
CASE (imm8[0]) OF
0: TEMP[127:0] := SRC2[127:0]
1: TEMP[255:128] := SRC2[127:0]
ESAC
DEST := TEMP
Intel C/C++ Compiler Intrinsic Equivalent
VINSERTF32x4 __m512 _mm512_insertf32x4( __m512 a, __m128 b, int imm);
VINSERTF32x4 __m512 _mm512_mask_insertf32x4(__m512 s, __mmask16 k, __m512 a, __m128 b, int imm);
VINSERTF32x4 __m512 _mm512_maskz_insertf32x4( __mmask16 k, __m512 a, __m128 b, int imm);
VINSERTF32x4 __m256 _mm256_insertf32x4( __m256 a, __m128 b, int imm);
VINSERTF32x4 __m256 _mm256_mask_insertf32x4(__m256 s, __mmask8 k, __m256 a, __m128 b, int imm);
VINSERTF32x4 __m256 _mm256_maskz_insertf32x4( __mmask8 k, __m256 a, __m128 b, int imm);
VINSERTF32x8 __m512 _mm512_insertf32x8( __m512 a, __m256 b, int imm);
VINSERTF32x8 __m512 _mm512_mask_insertf32x8(__m512 s, __mmask16 k, __m512 a, __m256 b, int imm);
VINSERTF32x8 __m512 _mm512_maskz_insertf32x8( __mmask16 k, __m512 a, __m256 b, int imm);
VINSERTF64x2 __m512d _mm512_insertf64x2( __m512d a, __m128d b, int imm);
VINSERTF64x2 __m512d _mm512_mask_insertf64x2(__m512d s, __mmask8 k, __m512d a, __m128d b, int imm);
VINSERTF64x2 __m512d _mm512_maskz_insertf64x2( __mmask8 k, __m512d a, __m128d b, int imm);
VINSERTF64x2 __m256d _mm256_insertf64x2( __m256d a, __m128d b, int imm);
VINSERTF64x2 __m256d _mm256_mask_insertf64x2(__m256d s, __mmask8 k, __m256d a, __m128d b, int imm);
VINSERTF64x2 __m256d _mm256_maskz_insertf64x2( __mmask8 k, __m256d a, __m128d b, int imm);
VINSERTF64x4 __m512d _mm512_insertf64x4( __m512d a, __m256d b, int imm);
VINSERTF64x4 __m512d _mm512_mask_insertf64x4(__m512d s, __mmask8 k, __m512d a, __m256d b, int imm);
VINSERTF64x4 __m512d _mm512_maskz_insertf64x4( __mmask8 k, __m512d a, __m256d b, int imm);
VINSERTF128 __m256 _mm256_insertf128_ps (__m256 a, __m128 b, int offset);
VINSERTF128 __m256d _mm256_insertf128_pd (__m256d a, __m128d b, int offset);
VINSERTF128 __m256i _mm256_insertf128_si256 (__m256i a, __m128i b, int offset);
VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4-Insert Packed Floating-Point Values
Vol. 2C
5-409
SIMD Floating-Point Exceptions
None
Other Exceptions
VEX-encoded instruction, see Table 2-23, “Type 6 Class Exception Conditions.”
Additionally:
#UD
If VEX.L = 0.
EVEX-encoded instruction, see Table 2-56, “Type E6NF Class Exception Conditions.”
VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4-Insert Packed Floating-Point Values
Vol. 2C
5-410
VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4-Insert Packed
Integer Values
Opcode/
Op /
64/32
CPUID Feature
Description
Instruction
En
Bit Mode
Flag
Support
VEX.256.66.0F3A.W0 38 /r ib
A
V/V
AVX2
Insert 128 bits of integer data from xmm3/m128
VINSERTI128 ymm1, ymm2,
and the remaining values from ymm2 into ymm1.
xmm3/m128, imm8
EVEX.256.66.0F3A.W0 38 /r ib
C
V/V
(AVX512VL AND
Insert 128 bits of packed doubleword integer
VINSERTI32X4 ymm1 {k1}{z}, ymm2,
AVX512F) OR
values from xmm3/m128 and the remaining
xmm3/m128, imm8
AVX10.1
values from ymm2 into ymm1 under writemask
k1.
EVEX.512.66.0F3A.W0 38 /r ib
C
V/V
AVX512F
Insert 128 bits of packed doubleword integer
VINSERTI32X4 zmm1 {k1}{z}, zmm2,
OR AVX10.1
values from xmm3/m128 and the remaining
xmm3/m128, imm8
values from zmm2 into zmm1 under writemask
k1.
EVEX.256.66.0F3A.W1 38 /r ib
B
V/V
(AVX512VL AND
Insert 128 bits of packed quadword integer
VINSERTI64X2 ymm1 {k1}{z}, ymm2,
AVX512DQ) OR
values from xmm3/m128 and the remaining
xmm3/m128, imm8
AVX10.1
values from ymm2 into ymm1 under writemask
k1.
EVEX.512.66.0F3A.W1 38 /r ib
B
V/V
AVX512DQ OR
Insert 128 bits of packed quadword integer
VINSERTI64X2 zmm1 {k1}{z}, zmm2,
AVX10.1
values from xmm3/m128 and the remaining
xmm3/m128, imm8
values from zmm2 into zmm1 under writemask
k1.
EVEX.512.66.0F3A.W0 3A /r ib
D
V/V
AVX512DQ OR
Insert 256 bits of packed doubleword integer
VINSERTI32X8 zmm1 {k1}{z}, zmm2,
AVX10.1
values from ymm3/m256 and the remaining
ymm3/m256, imm8
values from zmm2 into zmm1 under writemask
k1.
EVEX.512.66.0F3A.W1 3A /r ib
C
V/V
AVX512F
Insert 256 bits of packed quadword integer
VINSERTI64X4 zmm1 {k1}{z}, zmm2,
OR AVX10.1
values from ymm3/m256 and the remaining
ymm3/m256, imm8
values from zmm2 into zmm1 under writemask
k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
imm8
B
Tuple2
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
imm8
C
Tuple4
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
imm8
D
Tuple8
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
imm8
Description
VINSERTI32x4 and VINSERTI64x2 inserts 128-bits of packed integer values from the second source operand (the
third operand) into the destination operand (the first operand) at an 128-bit granular offset multiplied by imm8[0]
(256-bit) or imm8[1:0]. The remaining portions of the destination are copied from the corresponding fields of the
first source operand (the second operand). The second source operand can be either an XMM register or a 128-bit
memory location. The high 6/7bits of the immediate are ignored. The destination operand is a ZMM/YMM register
and updated at 32 and 64-bit granularity according to the writemask.
VINSERTI32x8 and VINSERTI64x4 inserts 256-bits of packed integer values from the second source operand (the
third operand) into the destination operand (the first operand) at a 256-bit granular offset multiplied by imm8[0].
The remaining portions of the destination are copied from the corresponding fields of the first source operand (the
second operand). The second source operand can be either an YMM register or a 256-bit memory location. The
VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4-Insert Packed Integer Values
Vol. 2C
5-411
upper bits of the immediate are ignored. The destination operand is a ZMM register and updated at 32 and 64-bit
granularity according to the writemask.
VINSERTI128 inserts 128-bits of packed integer data from the second source operand (the third operand) into the
destination operand (the first operand) at a 128-bit granular offset multiplied by imm8[0]. The remaining portions
of the destination are copied from the corresponding fields of the first source operand (the second operand). The
second source operand can be either an XMM register or a 128-bit memory location. The high 7 bits of the imme-
diate are ignored. VEX.L must be 1, otherwise attempt to execute this instruction with VEX.L=0 will cause #UD.
Operation
VINSERTI32x4 (EVEX encoded versions)
(KL, VL) = (8, 256), (16, 512)
TEMP_DEST[VL-1:0] := SRC1[VL-1:0]
IF VL = 256
CASE (imm8[0]) OF
0: TMP_DEST[127:0] := SRC2[127:0]
1: TMP_DEST[255:128] := SRC2[127:0]
ESAC.
FI;
IF VL = 512
CASE (imm8[1:0]) OF
00: TMP_DEST[127:0] := SRC2[127:0]
01: TMP_DEST[255:128] := SRC2[127:0]
10: TMP_DEST[383:256] := SRC2[127:0]
11: TMP_DEST[511:384] := SRC2[127:0]
ESAC.
FI;
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4-Insert Packed Integer Values
Vol. 2C
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VINSERTI64x2 (EVEX encoded versions)
(KL, VL) = (4, 256), (8, 512)
TEMP_DEST[VL-1:0] := SRC1[VL-1:0]
IF VL = 256
CASE (imm8[0]) OF
0: TMP_DEST[127:0] := SRC2[127:0]
1: TMP_DEST[255:128] := SRC2[127:0]
ESAC.
FI;
IF VL = 512
CASE (imm8[1:0]) OF
00: TMP_DEST[127:0] := SRC2[127:0]
01: TMP_DEST[255:128] := SRC2[127:0]
10: TMP_DEST[383:256] := SRC2[127:0]
11: TMP_DEST[511:384] := SRC2[127:0]
ESAC.
FI;
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] := TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VINSERTI32x8 (EVEX.U1.512 encoded version)
TEMP_DEST[VL-1:0] := SRC1[VL-1:0]
CASE (imm8[0]) OF
0: TMP_DEST[255:0] := SRC2[255:0]
1: TMP_DEST[511:256] := SRC2[255:0]
ESAC.
FOR j := 0 TO 15
i := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4-Insert Packed Integer Values
Vol. 2C
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VINSERTI64x4 (EVEX.512 encoded version)
VL = 512
TEMP_DEST[VL-1:0] := SRC1[VL-1:0]
CASE (imm8[0]) OF
0: TMP_DEST[255:0] := SRC2[255:0]
1: TMP_DEST[511:256] := SRC2[255:0]
ESAC.
FOR j := 0 TO 7
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] := TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VINSERTI128
TEMP[255:0] := SRC1[255:0]
CASE (imm8[0]) OF
0: TEMP[127:0] := SRC2[127:0]
1: TEMP[255:128] := SRC2[127:0]
ESAC
DEST := TEMP
Intel C/C++ Compiler Intrinsic Equivalent
VINSERTI32x4 _mm512i _inserti32x4( __m512i a, __m128i b, int imm);
VINSERTI32x4 _mm512i _mask_inserti32x4(__m512i s, __mmask16 k, __m512i a, __m128i b, int imm);
VINSERTI32x4 _mm512i _maskz_inserti32x4( __mmask16 k, __m512i a, __m128i b, int imm);
VINSERTI32x4 __m256i _mm256_inserti32x4( __m256i a, __m128i b, int imm);
VINSERTI32x4 __m256i _mm256_mask_inserti32x4(__m256i s, __mmask8 k, __m256i a, __m128i b, int imm);
VINSERTI32x4 __m256i _mm256_maskz_inserti32x4( __mmask8 k, __m256i a, __m128i b, int imm);
VINSERTI32x8 __m512i _mm512_inserti32x8( __m512i a, __m256i b, int imm);
VINSERTI32x8 __m512i _mm512_mask_inserti32x8(__m512i s, __mmask16 k, __m512i a, __m256i b, int imm);
VINSERTI32x8 __m512i _mm512_maskz_inserti32x8( __mmask16 k, __m512i a, __m256i b, int imm);
VINSERTI64x2 __m512i _mm512_inserti64x2( __m512i a, __m128i b, int imm);
VINSERTI64x2 __m512i _mm512_mask_inserti64x2(__m512i s, __mmask8 k, __m512i a, __m128i b, int imm);
VINSERTI64x2 __m512i _mm512_maskz_inserti64x2( __mmask8 k, __m512i a, __m128i b, int imm);
VINSERTI64x2 __m256i _mm256_inserti64x2( __m256i a, __m128i b, int imm);
VINSERTI64x2 __m256i _mm256_mask_inserti64x2(__m256i s, __mmask8 k, __m256i a, __m128i b, int imm);
VINSERTI64x2 __m256i _mm256_maskz_inserti64x2( __mmask8 k, __m256i a, __m128i b, int imm);
VINSERTI64x4 _mm512_inserti64x4( __m512i a, __m256i b, int imm);
VINSERTI64x4 _mm512_mask_inserti64x4(__m512i s, __mmask8 k, __m512i a, __m256i b, int imm);
VINSERTI64x4 _mm512_maskz_inserti64x4( __mmask m, __m512i a, __m256i b, int imm);
VINSERTI128 __m256i _mm256_insertf128_si256 (__m256i a, __m128i b, int offset);
SIMD Floating-Point Exceptions
None.
VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4-Insert Packed Integer Values
Vol. 2C
5-414
Other Exceptions
VEX-encoded instruction, see Table 2-23, “Type 6 Class Exception Conditions.”
Additionally:
#UD
If VEX.L = 0.
EVEX-encoded instruction, see Table 2-56, “Type E6NF Class Exception Conditions.”
VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4-Insert Packed Integer Values
Vol. 2C
5-415
VMASKMOV-Conditional SIMD Packed Loads and Stores
Opcode/
Op/
64/32-
CPUID
Description
Instruction
En
bit Mode
Feature
Flag
VEX.128.66.0F38.W0 2C /r
RV
V/V
AVX
Conditionally load packed single precision values from
M
m128 using mask in xmm2 and store in xmm1.
VMASKMOVPS xmm1, xmm2, m128
VEX.256.66.0F38.W0 2C /r
RV
V/V
AVX
Conditionally load packed single precision values from
M
m256 using mask in ymm2 and store in ymm1.
VMASKMOVPS ymm1, ymm2, m256
VEX.128.66.0F38.W0 2D /r
RV
V/V
AVX
Conditionally load packed double precision values from
M
m128 using mask in xmm2 and store in xmm1.
VMASKMOVPD xmm1, xmm2, m128
VEX.256.66.0F38.W0 2D /r
RV
V/V
AVX
Conditionally load packed double precision values from
M
m256 using mask in ymm2 and store in ymm1.
VMASKMOVPD ymm1, ymm2, m256
VEX.128.66.0F38.W0 2E /r
MV
V/V
AVX
Conditionally store packed single precision values from
R
xmm2 using mask in xmm1.
VMASKMOVPS m128, xmm1, xmm2
VEX.256.66.0F38.W0 2E /r
MV
V/V
AVX
Conditionally store packed single precision values from
R
ymm2 using mask in ymm1.
VMASKMOVPS m256, ymm1, ymm2
VEX.128.66.0F38.W0 2F /r
MV
V/V
AVX
Conditionally store packed double precision values from
R
xmm2 using mask in xmm1.
VMASKMOVPD m128, xmm1, xmm2
VEX.256.66.0F38.W0 2F /r
MV
V/V
AVX
Conditionally store packed double precision values from
R
ymm2 using mask in ymm1.
VMASKMOVPD m256, ymm1, ymm2
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
MVR
ModRM:r/m (w)
VEX.vvvv (r)
ModRM:reg (r)
N/A
Description
Conditionally moves packed data elements from the second source operand into the corresponding data element
of the destination operand, depending on the mask bits associated with each data element. The mask bits are
specified in the first source operand.
The mask bit for each data element is the most significant bit of that element in the first source operand. If a mask
is 1, the corresponding data element is copied from the second source operand to the destination operand. If the
mask is 0, the corresponding data element is set to zero in the load form of these instructions, and unmodified in
the store form.
The second source operand is a memory address for the load form of these instruction. The destination operand is
a memory address for the store form of these instructions. The other operands are both XMM registers (for
VEX.128 version) or YMM registers (for VEX.256 version).
Faults occur only due to mask-bit required memory accesses that caused the faults. Faults will not occur due to
referencing any memory location if the corresponding mask bit for that memory location is 0. For example, no
faults will be detected if the mask bits are all zero.
Unlike previous MASKMOV instructions (MASKMOVQ and MASKMOVDQU), a nontemporal hint is not applied to
these instructions.
Instruction behavior on alignment check reporting with mask bits of less than all 1s are the same as with mask bits
of all 1s.
VMASKMOV should not be used to access memory mapped I/O and un-cached memory as the access and the
ordering of the individual loads or stores it does is implementation specific.
VMASKMOV-Conditional SIMD Packed Loads and Stores
Vol. 2C
5-416
In cases where mask bits indicate data should not be loaded or stored paging A and D bits will be set in an imple-
mentation dependent way. However, A and D bits are always set for pages where data is actually loaded/stored.
Note: for load forms, the first source (the mask) is encoded in VEX.vvvv; the second source is encoded in rm_field,
and the destination register is encoded in reg_field.
Note: for store forms, the first source (the mask) is encoded in VEX.vvvv; the second source register is encoded in
reg_field, and the destination memory location is encoded in rm_field.
Operation
VMASKMOVPS -128-bit load
DEST[31:0] := IF (SRC1[31]) Load_32(mem) ELSE 0
DEST[63:32] := IF (SRC1[63]) Load_32(mem + 4) ELSE 0
DEST[95:64] := IF (SRC1[95]) Load_32(mem + 8) ELSE 0
DEST[127:97] := IF (SRC1[127]) Load_32(mem + 12) ELSE 0
DEST[MAXVL-1:128] := 0
VMASKMOVPS - 256-bit load
DEST[31:0] := IF (SRC1[31]) Load_32(mem) ELSE 0
DEST[63:32] := IF (SRC1[63]) Load_32(mem + 4) ELSE 0
DEST[95:64] := IF (SRC1[95]) Load_32(mem + 8) ELSE 0
DEST[127:96] := IF (SRC1[127]) Load_32(mem + 12) ELSE 0
DEST[159:128] := IF (SRC1[159]) Load_32(mem + 16) ELSE 0
DEST[191:160] := IF (SRC1[191]) Load_32(mem + 20) ELSE 0
DEST[223:192] := IF (SRC1[223]) Load_32(mem + 24) ELSE 0
DEST[255:224] := IF (SRC1[255]) Load_32(mem + 28) ELSE 0
VMASKMOVPD - 128-bit load
DEST[63:0] := IF (SRC1[63]) Load_64(mem) ELSE 0
DEST[127:64] := IF (SRC1[127]) Load_64(mem + 16) ELSE 0
DEST[MAXVL-1:128] := 0
VMASKMOVPD - 256-bit load
DEST[63:0] := IF (SRC1[63]) Load_64(mem) ELSE 0
DEST[127:64] := IF (SRC1[127]) Load_64(mem + 8) ELSE 0
DEST[195:128] := IF (SRC1[191]) Load_64(mem + 16) ELSE 0
DEST[255:196] := IF (SRC1[255]) Load_64(mem + 24) ELSE 0
VMASKMOVPS - 128-bit store
IF (SRC1[31]) DEST[31:0] := SRC2[31:0]
IF (SRC1[63]) DEST[63:32] := SRC2[63:32]
IF (SRC1[95]) DEST[95:64] := SRC2[95:64]
IF (SRC1[127]) DEST[127:96] := SRC2[127:96]
VMASKMOVPS - 256-bit store
IF (SRC1[31]) DEST[31:0] := SRC2[31:0]
IF (SRC1[63]) DEST[63:32] := SRC2[63:32]
IF (SRC1[95]) DEST[95:64] := SRC2[95:64]
IF (SRC1[127]) DEST[127:96] := SRC2[127:96]
IF (SRC1[159]) DEST[159:128] :=SRC2[159:128]
IF (SRC1[191]) DEST[191:160] := SRC2[191:160]
IF (SRC1[223]) DEST[223:192] := SRC2[223:192]
IF (SRC1[255]) DEST[255:224] := SRC2[255:224]
VMASKMOV-Conditional SIMD Packed Loads and Stores
Vol. 2C
5-417
VMASKMOVPD - 128-bit store
IF (SRC1[63]) DEST[63:0] := SRC2[63:0]
IF (SRC1[127]) DEST[127:64] := SRC2[127:64]
VMASKMOVPD - 256-bit store
IF (SRC1[63]) DEST[63:0] := SRC2[63:0]
IF (SRC1[127]) DEST[127:64] := SRC2[127:64]
IF (SRC1[191]) DEST[191:128] := SRC2[191:128]
IF (SRC1[255]) DEST[255:192] := SRC2[255:192]
Intel C/C++ Compiler Intrinsic Equivalent
__m256 _mm256_maskload_ps(float const *a, __m256i mask)
void _mm256_maskstore_ps(float *a, __m256i mask, __m256 b)
__m256d _mm256_maskload_pd(double *a, __m256i mask);
void _mm256_maskstore_pd(double *a, __m256i mask, __m256d b);
__m128 _mm_maskload_ps(float const *a, __m128i mask)
void _mm_maskstore_ps(float *a, __m128i mask, __m128 b)
__m128d _mm_maskload_pd(double const *a, __m128i mask);
void _mm_maskstore_pd(double *a, __m128i mask, __m128d b);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-23, “Type 6 Class Exception Conditions” (No AC# reported for any mask bit combinations).
Additionally:
#UD
If VEX.W = 1.
VMASKMOV-Conditional SIMD Packed Loads and Stores
Vol. 2C
5-418
VMAXPH-Return Maximum of Packed FP16 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.NP.MAP5.W0 5F /r
A
V/V
(AVX512_FP16
Return the maximum packed FP16 values
VMAXPH xmm1{k1}{z}, xmm2,
AND AVX512VL)
between xmm2 and xmm3/m128/m16bcst and
xmm3/m128/m16bcst
OR AVX10.1
store the result in xmm1 subject to writemask k1.
EVEX.256.NP.MAP5.W0 5F /r
A
V/V
(AVX512_FP16
Return the maximum packed FP16 values
VMAXPH ymm1{k1}{z}, ymm2,
AND AVX512VL)
between ymm2 and ymm3/m256/m16bcst and
ymm3/m256/m16bcst
OR AVX10.1
store the result in ymm1 subject to writemask k1.
EVEX.512.NP.MAP5.W0 5F /r
A
V/V
AVX512_FP16
Return the maximum packed FP16 values
VMAXPH zmm1{k1}{z}, zmm2,
OR AVX10.1
between zmm2 and zmm3/m512/m16bcst and
zmm3/m512/m16bcst {sae}
store the result in zmm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
This instruction performs a SIMD compare of the packed FP16 values in the first source operand and the second
source operand and returns the maximum value for each pair of values to the destination operand.
If the values being compared are both 0.0s (of either sign), the value in the second operand (source operand) is
returned. If a value in the second operand is an SNaN, then SNaN is forwarded unchanged to the destination (that
is, a QNaN version of the SNaN is not returned).
If only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN
or a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source
operand (from either the first or second operand) be returned, the action of VMAXPH can be emulated using a
sequence of instructions, such as, a comparison followed by AND, ANDN and OR.
EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcast from a 16-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
Operation
def MAX(SRC1, SRC2):
IF (SRC1 = 0.0) and (SRC2 = 0.0):
DEST := SRC2
ELSE IF (SRC1 = NaN):
DEST := SRC2
ELSE IF (SRC2 = NaN):
DEST := SRC2
ELSE IF (SRC1 > SRC2):
DEST := SRC1
ELSE:
DEST := SRC2
VMAXPH-Return Maximum of Packed FP16 Values
Vol. 2C
5-419
VMAXPH dest, src1, src2
VL = 128, 256 or 512
KL := VL/16
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF EVEX.b = 1:
tsrc2 := SRC2.fp16[0]
ELSE:
tsrc2 := SRC2.fp16[j]
DEST.fp16[j] := MAX(SRC1.fp16[j], tsrc2)
ELSE IF *zeroing*:
DEST.fp16[j] := 0
// else dest.fp16[j] remains unchanged
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VMAXPH __m128h _mm_mask_max_ph (__m128h src, __mmask8 k, __m128h a, __m128h b);
VMAXPH __m128h _mm_maskz_max_ph (__mmask8 k, __m128h a, __m128h b);
VMAXPH __m128h _mm_max_ph (__m128h a, __m128h b);
VMAXPH __m256h _mm256_mask_max_ph (__m256h src, __mmask16 k, __m256h a, __m256h b);
VMAXPH __m256h _mm256_maskz_max_ph (__mmask16 k, __m256h a, __m256h b);
VMAXPH __m256h _mm256_max_ph (__m256h a, __m256h b);
VMAXPH __m512h _mm512_mask_max_ph (__m512h src, __mmask32 k, __m512h a, __m512h b);
VMAXPH __m512h _mm512_maskz_max_ph (__mmask32 k, __m512h a, __m512h b);
VMAXPH __m512h _mm512_max_ph (__m512h a, __m512h b);
VMAXPH __m512h _mm512_mask_max_round_ph (__m512h src, __mmask32 k, __m512h a, __m512h b, int sae);
VMAXPH __m512h _mm512_maskz_max_round_ph (__mmask32 k, __m512h a, __m512h b, int sae);
VMAXPH __m512h _mm512_max_round_ph (__m512h a, __m512h b, int sae);
SIMD Floating-Point Exceptions
Invalid, Denormal.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
VMAXPH-Return Maximum of Packed FP16 Values
Vol. 2C
5-420
VMAXSH-Return Maximum of Scalar FP16 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.LLIG.F3.MAP5.W0 5F /r
A
V/V
AVX512_FP16
Return the maximum low FP16 value between
VMAXSH xmm1{k1}{z}, xmm2,
OR AVX10.1
xmm3/m16 and xmm2 and store the result in
xmm3/m16 {sae}
xmm1 subject to writemask k1. Bits 127:16 of
xmm2 are copied to xmm1[127:16].
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
This instruction performs a compare of the low packed FP16 values in the first source operand and the second
source operand and returns the maximum value for the pair of values to the destination operand.
If the values being compared are both 0.0s (of either sign), the value in the second operand (source operand) is
returned. If a value in the second operand is an SNaN, then SNaN is forwarded unchanged to the destination (that
is, a QNaN version of the SNaN is not returned).
If only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN
or a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source
operand (from either the first or second operand) be returned, the action of VMAXSH can be emulated using a
sequence of instructions, such as, a comparison followed by AND, ANDN, and OR.
Bits 127:16 of the destination operand are copied from the corresponding bits of the first source operand. Bits
MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the destination is updated according
to the writemask.
Operation
def MAX(SRC1, SRC2):
IF (SRC1 = 0.0) and (SRC2 = 0.0):
DEST := SRC2
ELSE IF (SRC1 = NaN):
DEST := SRC2
ELSE IF (SRC2 = NaN):
DEST := SRC2
ELSE IF (SRC1 > SRC2):
DEST := SRC1
ELSE:
DEST := SRC2
VMAXSH-Return Maximum of Scalar FP16 Values
Vol. 2C
5-421
VMAXSH dest, src1, src2
IF k1[0] OR *no writemask*:
DEST.fp16[0] := MAX(SRC1.fp16[0], SRC2.fp16[0])
ELSE IF *zeroing*:
DEST.fp16[0] := 0
// else dest.fp16[j] remains unchanged
DEST[127:16] := SRC1[127:16]
DEST[MAXVL-1:128] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VMAXSH __m128h _mm_mask_max_round_sh (__m128h src, __mmask8 k, __m128h a, __m128h b, int sae);
VMAXSH __m128h _mm_maskz_max_round_sh (__mmask8 k, __m128h a, __m128h b, int sae);
VMAXSH __m128h _mm_max_round_sh (__m128h a, __m128h b, int sae);
VMAXSH __m128h _mm_mask_max_sh (__m128h src, __mmask8 k, __m128h a, __m128h b);
VMAXSH __m128h _mm_maskz_max_sh (__mmask8 k, __m128h a, __m128h b);
VMAXSH __m128h _mm_max_sh (__m128h a, __m128h b);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
EVEX-encoded instructions, see Table 2-49, “Type E3 Class Exception Conditions.”
VMAXSH-Return Maximum of Scalar FP16 Values
Vol. 2C
5-422
VMINPH-Return Minimum of Packed FP16 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.NP.MAP5.W0 5D /r
A
V/V
(AVX512_FP16
Return the minimum packed FP16 values between
VMINPH xmm1{k1}{z}, xmm2,
AND AVX512VL)
xmm2 and xmm3/m128/m16bcst and store the
xmm3/m128/m16bcst
OR AVX10.1
result in xmm1 subject to writemask k1.
EVEX.256.NP.MAP5.W0 5D /r
A
V/V
(AVX512_FP16
Return the minimum packed FP16 values between
VMINPH ymm1{k1}{z}, ymm2,
AND AVX512VL)
ymm2 and ymm3/m256/m16bcst and store the
ymm3/m256/m16bcst
OR AVX10.1
result in ymm1 subject to writemask k1.
EVEX.512.NP.MAP5.W0 5D /r
A
V/V
AVX512_FP16
Return the minimum packed FP16 values between
VMINPH zmm1{k1}{z}, zmm2,
OR AVX10.1
zmm2 and zmm3/m512/m16bcst and store the
zmm3/m512/m16bcst {sae}
result in zmm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
This instruction performs a SIMD compare of the packed FP16 values in the first source operand and the second
source operand and returns the minimum value for each pair of values to the destination operand.
If the values being compared are both 0.0s (of either sign), the value in the second operand (source operand) is
returned. If a value in the second operand is an SNaN, then SNaN is forwarded unchanged to the destination (that
is, a QNaN version of the SNaN is not returned).
If only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN
or a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source
operand (from either the first or second operand) be returned, the action of VMINPH can be emulated using a
sequence of instructions, such as, a comparison followed by AND, ANDN and OR.
EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcast from a 16-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
Operation
def MIN(SRC1, SRC2):
IF (SRC1 = 0.0) and (SRC2 = 0.0):
DEST := SRC2
ELSE IF (SRC1 = NaN):
DEST := SRC2
ELSE IF (SRC2 = NaN):
DEST := SRC2
ELSE IF (SRC1 < SRC2):
DEST := SRC1
ELSE:
DEST := SRC2
VMINPH-Return Minimum of Packed FP16 Values
Vol. 2C
5-423
VMINPH dest, src1, src2
VL = 128, 256 or 512
KL := VL/16
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF EVEX.b = 1:
tsrc2 := SRC2.fp16[0]
ELSE:
tsrc2 := SRC2.fp16[j]
DEST.fp16[j] := MIN(SRC1.fp16[j], tsrc2)
ELSE IF *zeroing*:
DEST.fp16[j] := 0
// else dest.fp16[j] remains unchanged
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VMINPH __m128h _mm_mask_min_ph (__m128h src, __mmask8 k, __m128h a, __m128h b);
VMINPH __m128h _mm_maskz_min_ph (__mmask8 k, __m128h a, __m128h b);
VMINPH __m128h _mm_min_ph (__m128h a, __m128h b);
VMINPH __m256h _mm256_mask_min_ph (__m256h src, __mmask16 k, __m256h a, __m256h b);
VMINPH __m256h _mm256_maskz_min_ph (__mmask16 k, __m256h a, __m256h b);
VMINPH __m256h _mm256_min_ph (__m256h a, __m256h b);
VMINPH __m512h _mm512_mask_min_ph (__m512h src, __mmask32 k, __m512h a, __m512h b);
VMINPH __m512h _mm512_maskz_min_ph (__mmask32 k, __m512h a, __m512h b);
VMINPH __m512h _mm512_min_ph (__m512h a, __m512h b);
VMINPH __m512h _mm512_mask_min_round_ph (__m512h src, __mmask32 k, __m512h a, __m512h b, int sae);
VMINPH __m512h _mm512_maskz_min_round_ph (__mmask32 k, __m512h a, __m512h b, int sae);
VMINPH __m512h _mm512_min_round_ph (__m512h a, __m512h b, int sae);
SIMD Floating-Point Exceptions
Invalid, Denormal.
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
VMINPH-Return Minimum of Packed FP16 Values
Vol. 2C
5-424
VMINSH-Return Minimum Scalar FP16 Value
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.LLIG.F3.MAP5.W0 5D /r
A
V/V
AVX512_FP16
Return the minimum low FP16 value between
VMINSH xmm1{k1}{z}, xmm2,
OR AVX10.1
xmm3/m16 and xmm2. Stores the result in
xmm3/m16 {sae}
xmm1 subject to writemask k1. Bits 127:16 of
xmm2 are copied to xmm1[127:16].
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
This instruction performs a compare of the low packed FP16 values in the first source operand and the second
source operand and returns the minimum value for the pair of values to the destination operand.
If the values being compared are both 0.0s (of either sign), the value in the second operand (source operand) is
returned. If a value in the second operand is an SNaN, then SNaN is forwarded unchanged to the destination (that
is, a QNaN version of the SNaN is not returned).
If only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN
or a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source
operand (from either the first or second operand) be returned, the action of VMINSH can be emulated using a
sequence of instructions, such as, a comparison followed by AND, ANDN, and OR.
EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcast from a 16-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
Bits 127:16 of the destination operand are copied from the corresponding bits of the first source operand. Bits
MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the destination is updated according
to the writemask.
Operation
def MIN(SRC1, SRC2):
IF (SRC1 = 0.0) and (SRC2 = 0.0):
DEST := SRC2
ELSE IF (SRC1 = NaN):
DEST := SRC2
ELSE IF (SRC2 = NaN):
DEST := SRC2
ELSE IF (SRC1 < SRC2):
DEST := SRC1
ELSE:
DEST := SRC2
VMINSH-Return Minimum Scalar FP16 Value
Vol. 2C
5-425
VMINSH dest, src1, src2
IF k1[0] OR *no writemask*:
DEST.fp16[0] := MIN(SRC1.fp16[0], SRC2.fp16[0])
ELSE IF *zeroing*:
DEST.fp16[0] := 0
// else dest.fp16[j] remains unchanged
DEST[127:16] := SRC1[127:16]
DEST[MAXVL-1:128] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VMINSH __m128h _mm_mask_min_round_sh (__m128h src, __mmask8 k, __m128h a, __m128h b, int sae);
VMINSH __m128h _mm_maskz_min_round_sh (__mmask8 k, __m128h a, __m128h b, int sae);
VMINSH __m128h _mm_min_round_sh (__m128h a, __m128h b, int sae);
VMINSH __m128h _mm_mask_min_sh (__m128h src, __mmask8 k, __m128h a, __m128h b);
VMINSH __m128h _mm_maskz_min_sh (__mmask8 k, __m128h a, __m128h b);
VMINSH __m128h _mm_min_sh (__m128h a, __m128h b);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
EVEX-encoded instructions, see Table 2-49, “Type E3 Class Exception Conditions.”
VMINSH-Return Minimum Scalar FP16 Value
Vol. 2C
5-426
VMOVSH-Move Scalar FP16 Value
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.LLIG.F3.MAP5.W0 10 /r
A
V/V
AVX512_FP16
Move FP16 value from m16 to xmm1 subject to
VMOVSH xmm1{k1}{z}, m16
OR AVX10.1
writemask k1.
EVEX.LLIG.F3.MAP5.W0 11 /r
B
V/V
AVX512_FP16
Move low FP16 value from xmm1 to m16 subject
VMOVSH m16{k1}, xmm1
OR AVX10.1
to writemask k1.
EVEX.LLIG.F3.MAP5.W0 10 /r
C
V/V
AVX512_FP16
Move low FP16 values from xmm3 to xmm1
VMOVSH xmm1{k1}{z}, xmm2, xmm3
OR AVX10.1
subject to writemask k1. Bits 127:16 of xmm2
are copied to xmm1[127:16].
EVEX.LLIG.F3.MAP5.W0 11 /r
D
V/V
AVX512_FP16
Move low FP16 values from xmm3 to xmm1
VMOVSH xmm1{k1}{z}, xmm2, xmm3
OR AVX10.1
subject to writemask k1. Bits 127:16 of xmm2
are copied to xmm1[127:16].
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
B
Scalar
ModRM:r/m (w)
ModRM:reg (r)
N/A
N/A
C
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
D
N/A
ModRM:r/m (w)
VEX.vvvv (r)
ModRM:reg (r)
N/A
Description
This instruction moves a FP16 value to a register or memory location.
The two register-only forms are aliases and differ only in where their operands are encoded; this is a side effect of
the encodings selected.
Operation
VMOVSH dest, src (two operand load)
IF k1[0] or no writemask:
DEST.fp16[0] := SRC.fp16[0]
ELSE IF *zeroing*:
DEST.fp16[0] := 0
// ELSE DEST.fp16[0] remains unchanged
DEST[MAXVL:16] := 0
VMOVSH dest, src (two operand store)
IF k1[0] or no writemask:
DEST.fp16[0] := SRC.fp16[0]
// ELSE DEST.fp16[0] remains unchanged
VMOVSH-Move Scalar FP16 Value
Vol. 2C
5-427
VMOVSH dest, src1, src2 (three operand copy)
IF k1[0] or no writemask:
DEST.fp16[0] := SRC2.fp16[0]
ELSE IF *zeroing*:
DEST.fp16[0] := 0
// ELSE DEST.fp16[0] remains unchanged
DEST[127:16] := SRC1[127:16]
DEST[MAXVL:128] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VMOVSH __m128h _mm_load_sh (void const* mem_addr);
VMOVSH __m128h _mm_mask_load_sh (__m128h src, __mmask8 k, void const* mem_addr);
VMOVSH __m128h _mm_maskz_load_sh (__mmask8 k, void const* mem_addr);
VMOVSH __m128h _mm_mask_move_sh (__m128h src, __mmask8 k, __m128h a, __m128h b);
VMOVSH __m128h _mm_maskz_move_sh (__mmask8 k, __m128h a, __m128h b);
VMOVSH __m128h _mm_move_sh (__m128h a, __m128h b);
VMOVSH void _mm_mask_store_sh (void * mem_addr, __mmask8 k, __m128h a);
VMOVSH void _mm_store_sh (void * mem_addr, __m128h a);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Table 2-53, “Type E5 Class Exception Conditions.”
VMOVSH-Move Scalar FP16 Value
Vol. 2C
5-428
VMOVW-Move Word
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.66.MAP5.WIG 6E /r
A
V/V
AVX512_FP16
Copy word from reg/m16 to xmm1.
VMOVW xmm1, reg/m16
OR AVX10.1
EVEX.128.66.MAP5.WIG 7E /r
B
V/V
AVX512_FP16
Copy word from xmm1 to reg/m16.
VMOVW reg/m16, xmm1
OR AVX10.1
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
B
Scalar
ModRM:r/m (w)
ModRM:reg (r)
N/A
N/A
Description
This instruction either (a) copies one word element from an XMM register to a general-purpose register or memory
location or (b) copies one word element from a general-purpose register or memory location to an XMM register.
When writing a general-purpose register, the lower 16-bits of the register will contain the word value. The upper bits
of the general-purpose register are written with zeros.
Operation
VMOVW dest, src (two operand load)
DEST.word[0] := SRC.word[0]
DEST[MAXVL:16] := 0
VMOVW dest, src (two operand store)
DEST.word[0] := SRC.word[0]
// upper bits of GPR DEST are zeroed
Intel C/C++ Compiler Intrinsic Equivalent
VMOVW short _mm_cvtsi128_si16 (__m128i a);
VMOVW __m128i _mm_cvtsi16_si128 (short a);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instructions, see Table 2-59, “Type E9NF Class Exception Conditions.”
VMOVW-Move Word
Vol. 2C
5-429
VMULPH-Multiply Packed FP16 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.NP.MAP5.W0 59 /r
A
V/V
(AVX512_FP16
Multiply packed FP16 values from
VMULPH xmm1{k1}{z}, xmm2,
AND AVX512VL)
xmm3/m128/m16bcst to xmm2 and store the
xmm3/m128/m16bcst
OR AVX10.1
result in xmm1 subject to writemask k1.
EVEX.256.NP.MAP5.W0 59 /r
A
V/V
(AVX512_FP16
Multiply packed FP16 values from
VMULPH ymm1{k1}{z}, ymm2,
AND AVX512VL)
ymm3/m256/m16bcst to ymm2 and store the
ymm3/m256/m16bcst
OR AVX10.1
result in ymm1 subject to writemask k1.
EVEX.512.NP.MAP5.W0 59 /r
A
V/V
AVX512_FP16
Multiply packed FP16 values in
VMULPH zmm1{k1}{z}, zmm2,
OR AVX10.1
zmm3/m512/m16bcst with zmm2 and store the
zmm3/m512/m16bcst {er}
result in zmm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
This instruction multiplies packed FP16 values from source operands and stores the packed FP16 result in the desti-
nation operand. The destination elements are updated according to the writemask.
Operation
VMULPH (EVEX encoded versions) when src2 operand is a register
VL = 128, 256 or 512
KL := VL/16
IF (VL = 512) AND (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE
SET_RM(MXCSR.RC)
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
DEST.fp16[j] := SRC1.fp16[j] * SRC2.fp16[j]
ELSE IF *zeroing*:
DEST.fp16[j] := 0
// else dest.fp16[j] remains unchanged
DEST[MAXVL-1:VL] := 0
VMULPH-Multiply Packed FP16 Values
Vol. 2C
5-430
VMULPH (EVEX encoded versions) when src2 operand is a memory source
VL = 128, 256 or 512
KL := VL/16
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF EVEX.b = 1:
DEST.fp16[j] := SRC1.fp16[j] * SRC2.fp16[0]
ELSE:
DEST.fp16[j] := SRC1.fp16[j] * SRC2.fp16[j]
ELSE IF *zeroing*:
DEST.fp16[j] := 0
// else dest.fp16[j] remains unchanged
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VMULPH __m128h _mm_mask_mul_ph (__m128h src, __mmask8 k, __m128h a, __m128h b);
VMULPH __m128h _mm_maskz_mul_ph (__mmask8 k, __m128h a, __m128h b);
VMULPH __m128h _mm_mul_ph (__m128h a, __m128h b);
VMULPH __m256h _mm256_mask_mul_ph (__m256h src, __mmask16 k, __m256h a, __m256h b);
VMULPH __m256h _mm256_maskz_mul_ph (__mmask16 k, __m256h a, __m256h b);
VMULPH __m256h _mm256_mul_ph (__m256h a, __m256h b);
VMULPH __m512h _mm512_mask_mul_ph (__m512h src, __mmask32 k, __m512h a, __m512h b);
VMULPH __m512h _mm512_maskz_mul_ph (__mmask32 k, __m512h a, __m512h b);
VMULPH __m512h _mm512_mul_ph (__m512h a, __m512h b);
VMULPH __m512h _mm512_mask_mul_round_ph (__m512h src, __mmask32 k, __m512h a, __m512h b, int rounding);
VMULPH __m512h _mm512_maskz_mul_round_ph (__mmask32 k, __m512h a, __m512h b, int rounding);
VMULPH __m512h _mm512_mul_round_ph (__m512h a, __m512h b, int rounding);
SIMD Floating-Point Exceptions
Invalid, Underflow, Overflow, Precision, Denormal
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E2 Class Exception Conditions.”
VMULPH-Multiply Packed FP16 Values
Vol. 2C
5-431