Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023)

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-51. MSRs Supported by the 3rd Generation Intel® Xeon® Scalable Processor Family with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_6AH or 06_6CH

Address

Scope

Bit Description

Hex

Dec

61BH

1563

MSR_DRAM_PERF_STATUS

Package

DRAM Performance Throttling Status (R/O)

See Section 15.10.5, “DRAM RAPL Domain.”

61CH

1564

MSR_DRAM_POWER_INFO

Package

DRAM Power Parameters (R/W)

14:0

Spec DRAM Power (DRAM_TDP):

The Spec power allowed for DRAM. The TDP setting is

typical (not guaranteed).

The units for this value are defined in

MSR_DRAM_POWER_INFO_UNIT[PWR_UNIT].

Reserved

30:16

Minimal DRAM Power (DRAM_MIN_PWR):

The minimal power setting allowed for DRAM. Lower

values will be clamped to this value. The minimum

setting is typical (not guaranteed).

The units for this value are defined in

MSR_DRAM_POWER_INFO_UNIT[PWR_UNIT].

Reserved

46:32

Maximal Package Power (DRAM_MAX_PWR):

The maximal power setting allowed for DRAM. Higher

values will be clamped to this value. The maximum

setting is typical (not guaranteed).

The units for this value are defined in

MSR_DRAM_POWER_INFO_UNIT[PWR_UNIT].

Reserved

54:48

Maximal Time Window (DRAM_MAX_WIN):

The maximal time window allowed for the DRAM.

Higher values will be clamped to this value.

x = PKG_MAX_WIN[54:53]

y = PKG_MAX_WIN[52:48]

The timing interval window is a floating-point number

given by 1.x *power(2,y).

The unit of measurement is defined in

MSR_DRAM_POWER_INFO_UNIT[TIME_UNIT].

62:55

Reserved

LOCK:

Lock bit to lock the register.

981H

2433

IA32_TME_CAPABILITY

See Table 2-2.

982H

2434

IA32_TME_ACTIVATE

See Table 2-2.

983H

2435

IA32_TME_EXCLUDE_MASK

See Table 2-2.

984H

2436

IA32_TME_EXCLUDE_BASE

See Table 2-2.

Vol. 4

2-345

MODEL-SPECIFIC REGISTERS (MSRS)

2.17.8 MSRs Specific to the 4th Generation Intel® Xeon® Scalable Processor Family Based on

Sapphire Rapids Microarchitecture

The 4th generation Intel^® Xeon^® Scalable Processor Family based on Sapphire Rapids microarchitecture (CPUID

Signature DisplayFamily_DisplayModel value of 06_8FH) supports the MSRs listed in Section 2.17, “MSRs In the

6th Generation, 7th Generation, 8th Generation, 9th Generation, 10th Generation, 11th Generation, 12th Genera-

tion, and 13th Generation Intel® Core™ Processors, Intel® Xeon® Scalable Processor Family, 2nd, 3rd, and 4th

Generation Intel® Xeon® Scalable Processor Family, 8th Generation Intel® Core™ i3 Processors, and Intel®

Xeon® E processors,” including Table 2-52. For an MSR listed in Table 2-52 that also appears in the model-specific

tables of prior generations, Table 2-52 supersedes prior generation tables.

Table 2-52. Additional MSRs Supported by the 4th Generation Intel® Xeon® Scalable Processor Family

with a CPUID Signature DisplayFamily_DisplayModel Value of 06_8FH

Address

Scope

Bit Description

Hex

Dec

33H

MSR_MEMORY_CTRL

Core

Memory Control Register (R/W)

27:0

Reserved.

UC_LOCK_DISABLE

If set to 1, a UC lock will cause a #GP(0) exception.

See Section 9.1.2.3, “Features to Disable Bus Locks.”

SPLIT_LOCK_DISABLE

If set to 1, a split lock will cause an #AC(0) exception.

See Section 9.1.2.3, “Features to Disable Bus Locks.”

31:30

Reserved.

A7H

167

MSR_BIOS_DEBUG

Thread

BIOS DEBUG (R/O)

See Table 2-45.

BCH

188

IA32_MISC_PACKAGE_CTLS

Package

Power Filtering Control (R/W)

IA32_ARCH_CAPABILITIES[bit 10] enumerates

support for this MSR.

See Table 2-2.

CFH

207

IA32_CORE_CAPABILITIES

Core

IA32 Core Capabilities Register (R/W)

If CPUID.(EAX=07H, ECX=0):EDX[30] = 1.

This MSR provides an architectural enumeration

function for model-specific behavior.

Reserved: returns zero.

INTEGRITY_CAPABILITIES

When set to 1, the processor supports

MSR_INTEGRITY_CAPABILITIES.

RSM_IN_CPL0_ONLY

Indicates that RSM will only be allowed in CPL0 and

will #GP for all non-CPL0 privilege levels.

UC_LOCK_DISABLE_SUPPORTED

When read as 1, software can set bit 28 of

MSR_MEMORY_CTRL (MSR address 33H).

2-346 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-52. Additional MSRs Supported by the 4th Generation Intel® Xeon® Scalable Processor Family

with a CPUID Signature DisplayFamily_DisplayModel Value of 06_8FH

Address

Scope

Bit Description

Hex

Dec

SPLIT_LOCK_DISABLE_SUPPORTED

When read as 1, software can set bit 29 of

MSR_MEMORY_CTRL.

Reserved: returns zero.

UC_STORE_THROTTLING_SUPPORTED

Indicates that the snoop filter quality of service MSRs

are supported on this core. This is based on the

existence of a non-inclusive cache and the L2/MLC

QoS feature supported.

63:8

Reserved: returns zero.

E1H

225

IA32_UMWAIT_CONTROL

UMWAIT Control (R/W)

See Table 2-2.

EDH

237

MSR_RAR_CONTROL

Thread

RAR Control (R/W)

63:32

Reserved.

ENABLE

RAR events are recognized. When RAR is not enabled,

RARs are dropped.

IGNORE_IF

Allow RAR servicing at the RLP regardless of the

value of RFLAGS.IF.

29:0

Reserved.

EEH

238

MSR_RAR_ACTION_VECTOR_BASE

Thread

Pointer to RAR Action Vector (R/W)

63:MAXPHYADDR

Reserved.

MAXPHYADDR-1:6

VECTOR_PHYSICAL_ADDRESS

Pointer to the physical address of the 64B aligned

RAR action vector.

5:0

Reserved.

EFH

239

MSR_RAR_PAYLOAD_TABLE_BASE

Thread

Pointer to Base of RAR Payload Table (R/W)

63:MAXPHYADDR

Reserved.

MAXPHYADDR-1:12

TABLE_PHYSICAL_ADDRESS

Pointer to the base physical address of the 4K aligned

RAR payload table.

11:0

Reserved.

F0H

240

MSR_RAR_INFO

Thread

Read Only RAR Information (RO)

63:38

Always zero.

37:32

Table Max Index

Maximum supported payload table index.

31:0

Supported payload type bitmap. A value of 1 in bit

position [i] indicates that payload type [i] is supported.

Vol. 4

2-347

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-52. Additional MSRs Supported by the 4th Generation Intel® Xeon® Scalable Processor Family

with a CPUID Signature DisplayFamily_DisplayModel Value of 06_8FH

Address

Scope

Bit Description

Hex

Dec

105H

261

MSR_CORE_BIST

Core

Core BIST (R/W)

Controls Array BIST activation and status checking as

part of FUSA.

31:0

BIST_ARRAY

Bitmap indicating which arrays to run BIST on (WRITE).

Bitmap indicating which arrays were not processed,

i.e., completion mask (READ).

39:32

BANK

Array bank of the [least significant set bit] array

indicated in EAX to start BIST(WRITE).

Array bank interrupted or failed (READ).

47:40

DWORD

Array dword of the [least significant set bit] array

indicated in EAX to start BIST (WRITE).

Array dword interrupted or failed (READ).

62:48

Reserved

CTRL_RESULT

Indicates whether WRMSR should signal Machine-

Check upon BIST-error (WRITE).

BIST result PASS(0)/FAIL(1) of the (least significant

set bit) array indicated in EAX (READ).

10AH

266

IA32_ARCH_CAPABILITIES

Enumeration of Architectural Features (R/O)

See Table 2-2.

1A4H

420

MSR_PREFETCH_CONTROL

Prefetch Disable Bits (R/W)

L2_HARDWARE_PREFETCHER_DISABLE

If 1, disables the L2 hardware prefetcher, which

fetches additional lines of code or data into the L2

cache.

L2_ADJACENT_CACHE_LINE_PREFETCHER_DISABLE

If 1, disables the adjacent cache line prefetcher, which

fetches the cache line that comprises a cache line pair

(128 bytes).

DCU_HARDWARE_PREFETCHER_DISABLE

If 1, disables the L1 data cache prefetcher, which

fetches the next cache line into L1 data cache.

DCU_IP_PREFETCHER_DISABLE

If 1, disables the L1 data cache IP prefetcher, which

uses sequential load history (based on instruction

pointer of previous loads) to determine whether to

prefetch additional lines.

Reserved.

2-348 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-52. Additional MSRs Supported by the 4th Generation Intel® Xeon® Scalable Processor Family

with a CPUID Signature DisplayFamily_DisplayModel Value of 06_8FH

Address

Scope

Bit Description

Hex

Dec

AMP_PREFETCH_DISABLE

If 1, disables the L2 Adaptive Multipath Probability

(AMP) prefetcher.

63:6

Reserved.

1ADH

429

MSR_PRIMARY_TURBO_RATIO_LIMIT

Package

Primary Maximum Turbo Ratio Limit (R/W)

See Table 2-46.

1AEH

430

MSR_TURBO_RATIO_LIMIT_CORES

Package

See Table 2-50.

1C4H

452

IA32_XFD

Extended Feature Detect (R/W)

See Table 2-2.

1C5H

453

IA32_XFD_ERR

XFD Error Code (R/W)

See Table 2-2.

2C2H

706

MSR_COPY_SCAN_HASHES

Die

COPY_SCAN_HASHES (W)

63:0

SCAN_HASH_ADDR

Contains the linear address of the SCAN Test HASH

Binary loaded into memory.

2C3H

707

MSR_SCAN_HASHES_STATUS

SCAN_HASHES_STATUS (R/O)

15:0

Die

CHUNK_SIZE

Chunk size of the test in KB.

23:16

Die

NUM_CHUNKS

Total number of chunks.

31:24

Reserved: all zeros.

39:32

Thread

ERROR_CODE

The error-code refers to the LP that runs

WRMSR(2C2H).

0x0: No error reported.

0x1: Attempt to copy scan-hashes when copy already

in progress.

0x2: Secure Memory not set up correctly.

0x3: Scan-image header Image_info.ProgramID

doesn't match RDMSR(2D9H)[31:24], or scan-image

header Processor-Signature doesn't match F/M/S, or

scan-image header Processor-Flags doesn't match

PlatformID.

0x4: Reserved

0x5: Integrity check failed.

0x6: Re-install of scan test image attempted when

current scan test image is in use by other LPs.

50:40

Reserved: set to all zeros.

Vol. 4

2-349

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-52. Additional MSRs Supported by the 4th Generation Intel® Xeon® Scalable Processor Family

with a CPUID Signature DisplayFamily_DisplayModel Value of 06_8FH

Address

Scope

Bit Description

Hex

Dec

62:51

Die

MAX_CORE_LIMIT

Maximum Number of cores that can run Intel® In-field

Scan simultaneously minus 1.

0 means 1 core at a time.

Die

Valid

Valid bit is set when COPY_SCAN_HASHES has

completed successfully.

2C4H

708

MSR_AUTHENTICATE_AND_COPY_CHUNK

Die

AUTHENTICATE_AND_COPY_CHUNK (W)

7:0

CHUNK_INDEX

Chunk Index, should be less than the total number of

chunks defined by NUM_CHUNKS

(MSR_SCAN_HASHES_STATUS[23:16]).

63:8

CHUNK_ADDR

Bits 63:8 of 256B aligned Linear address of scan

chunk in memory.

2C5H

709

MSR_CHUNKS_AUTHENTICATION_STATUS

CHUNKS_AUTHENTICATION_STATUS (R/O)

7:0

Die

VALID_CHUNKS

Total number of Valid (authenticated) chunks.

15:8

Die

TOTAL_CHUNKS

Total number of chunks.

31:16

Reserved: all zeros.

39:32

Thread

ERROR_CODE

The error code refers to the LP that runs

WRMSR(2C4H).

0x0: No error reported.

0x1: Attempt to authenticate a CHUNK which is

already marked as authentic or is currently being

installed by another core.

0x2: CHUNK authentication error. HASH of chunk did

not match expected value.

63:40

Reserved: set to all zeros.

2C6H

710

MSR_ACTIVATE_SCAN

Thread

ACTIVATE_SCAN (W)

7:0

CHUNK_START_INDEX

Indicates chunk index to start from.

15:8

CHUNK_STOP_INDEX

Indicates what chunk index to stop at (inclusive).

31:16

Reserved: all zeros.

62:32

THREAD_WAIT_DELAY

TSC based delay to allow threads to rendezvous.

2-350 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-52. Additional MSRs Supported by the 4th Generation Intel® Xeon® Scalable Processor Family

with a CPUID Signature DisplayFamily_DisplayModel Value of 06_8FH

Address

Scope

Bit Description

Hex

Dec

SIGNAL_MCE

If 1, then on scan-error log MC in MC4_STATUS and

signal MCE if machine check signaling enabled in

MC4_CTL[0].

If 0, then no logging/no signaling.

2C7H

711

MSR_SCAN_STATUS

SCAN_STATUS (R/O)

7:0

Core

CHUNK_NUM

SCAN Chunk that was reached.

15:8

Core

CHUNK_STOP_INDEX

Indicates what chunk index to stop at (inclusive). Maps

to same field in WRMSR(ACTIVATE_SCAN).

31:16

Reserved: return all zeros.

39:32

Thread

ERROR_CODE

0x0: No error.

0x1: SCAN operation did not start. Other thread did

not join in time.

0x2: SCAN operation did not start. Interrupt occurred

prior to threads rendezvous.

0x3: SCAN operation did not start. Power

Management conditions are inadequate to run Intel In-

field Scan.

0x4: SCAN operation did not start. Non-valid chunks in

the range CHUNK_STOP_INDEX :

CHUNK_START_INDEX.

0x5: SCAN operation did not start. Mismatch in

arguments between threads T0/T1.

0x6: SCAN operation did not start. Core not capable of

performing SCAN currently.

0x8: SCAN operation did not start. Exceeded number

of Logical Processors (LP) allowed to run Intel In-field

Scan concurrently. MAX_CORE_LIMIT exceeded.

0x9: Interrupt occurred. Scan operation aborted

prematurely, not all chunks requested have been

executed.

61:40

Reserved: return all zeros.

Core

SCAN_CONTROL_ERROR

Scan-System-Controller malfunction.

Core

SCAN_SIGNATURE_ERROR

Core failed SCAN-SIGNATURE checking for this chunk.

2C8H

712

MSR_SCAN_MODULE_ID

Module

SCAN_MODULE_ID (R/O)

31:0

RevID of the currently installed scan test image. Maps

to Revision field in external header (offset 4).

63:32

Reserved: return all zeros.

Vol. 4

2-351

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-52. Additional MSRs Supported by the 4th Generation Intel® Xeon® Scalable Processor Family

with a CPUID Signature DisplayFamily_DisplayModel Value of 06_8FH

Address

Scope

Bit Description

Hex

Dec

2C9H

713

MSR_LAST_SAF_WP

Core

LAST_SAF_WP (R/O)

31:0

LAST_WP

Provides information about the core when the last

WRMSR(ACTIVATE_SCAN) was executed. Available

only if enumerated in

MSR_INTEGRITY_CAPABILITIES[10:9].

63:32

Reserved: return all zeros.

2D9H

729

MSR_INTEGRITY_CAPABILITIES

Module

INTEGRITY_CAPABILITIES (R/O)

STARTUP_SCAN_BIST

When set, supports Intel In-field Scan.

3:1

Reserved: return all zeros.

PERIODIC_SCAN_BIST

When set, supports Intel In-field Scan.

23:5

Reserved: return all zeros.

31:24

ID of the scan programs supported for this part.

WRMSR(2C2H) verifies this value against the

corresponding value in the scan-image header, i.e.,

Image_info.

410H

1040

IA32_MC4_CTL

Package

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through

Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

411H

1041

IA32_MC4_STATUS

Package

Bank MC4 reports MC errors from the PCU module.

412H

1042

IA32_MC4_ADDR

Package

If SIGNAL_MCE is set, a Scan Status is logged in

413H

1043

IA32_MC4_MISC

Package

MC4_STATUS and MC4_MISC.

492H

1170

IA32_VMX_PROCBASED_CTLS3

Capability Reporting Register of Tertiary Processor-

Based VM-Execution Controls (R/O)

See Table 2-2.

493H

1171

IA32_VMX_EXIT_CTLS2

Capability Reporting Register of Secondary VM-Exit

Controls (R/O)

See Table 2-2.

540H

1344

MSR_THREAD_UARCH_CTL

Thread

Thread Microarchitectural Control (R/W)

See Table 2-47.

64DH

1613

MSR_PLATFORM_ENERGY_STATUS

Package

Platform Energy Status (R/O)

31:0

TOTAL_ENERGY_CONSUMED

Total energy consumption in J (32.0), in 10nsec units.

63:32

TIME_STAMP

Time stamp (U32.0).

65CH

1628

MSR_PLATFORM_POWER_LIMIT

Package

Platform Power Limit Control (R/W-L)

2-352 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-52. Additional MSRs Supported by the 4th Generation Intel® Xeon® Scalable Processor Family

with a CPUID Signature DisplayFamily_DisplayModel Value of 06_8FH

Address

Scope

Bit Description

Hex

Dec

16:0

POWER_LIMIT_1

The average power limit value that the platform must

not exceed over a time window as specified by the

Power_Limit_1_TIME field.

The default value is the Thermal Design Power (TDP)

and varies with product skus. The unit is specified in

MSR_RAPL_POWER_UNIT.

POWER_LIMIT_1_EN

When set, the processor can apply control policies

such that the platform average power does not

exceed the Power_Limit_1 value over an exponential

weighted moving average of the time window.

CRITICAL_POWER_CLAMP_1

When set, the processor can go below the OS-

requested P States to maintain the power below the

specified Power_Limit_1 value.

25:19

POWER_LIMIT_1_TIME

This indicates the time window over which the

Power_Limit_1 value should be maintained.

This field is made up of two numbers from the

following equation:

Time Window = (float) ((1+(X/4))*(2^Y)), where:

X = POWER_LIMIT_1_TIME[23:22]

Y = POWER_LIMIT_1_TIME[21:17]

The maximum allowed value in this field is defined in

MSR_PKG_POWER_INFO[PKG_MAX_WIN].

The default value is 0DH, and the unit is specified in

MSR_RAPL_POWER_UNIT[Time Unit].

31:26

Reserved

48:32

POWER_LIMIT_2

This is the Duration Power limit value that the

platform must not exceed.

The unit is specified in MSR_RAPL_POWER_UNIT.

Enable Platform Power Limit #2

When set, enables the processor to apply control

policy such that the platform power does not exceed

Platform Power limit #2 over the Short Duration time

window.

Platform Clamping Limitation #2

When set, allows the processor to go below the OS

requested P states in order to maintain the power

below specified Platform Power Limit #2 value.

Vol. 4

2-353

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-52. Additional MSRs Supported by the 4th Generation Intel® Xeon® Scalable Processor Family

with a CPUID Signature DisplayFamily_DisplayModel Value of 06_8FH

Address

Scope

Bit Description

Hex

Dec

57:51

POWER_LIMIT_2_TIME

This indicates the time window over which the

Power_Limit_2 value should be maintained.

This field has the same format as the

POWER_LIMIT_1_TIME field.

62:58

Reserved

LOCK

Setting this bit will lock all other bits of this MSR until

system RESET.

665H

1637

MSR_PLATFORM_POWER_INFO

Package

Platform Power Information (R/W)

16:0

MAX_PPL1

Maximum PP L1 value.

The unit is specified in MSR_RAPL_POWER_UNIT.

31:17

MIN_PPL1

Minimum PP L1 value.

The unit is specified in MSR_RAPL_POWER_UNIT.

48:32

MAX_PPL2

Maximum PP L2 value.

The unit is specified in MSR_RAPL_POWER_UNIT.

55:49

MAX_TW

Maximum time window.

The unit is specified in MSR_RAPL_POWER_UNIT.

62:56

Reserved

LOCK

Setting this bit will lock all other bits of this MSR until

system RESET.

666H

1638

MSR_PLATFORM_RAPL_SOCKET_PERF_

Package

Platform RAPL Socket Performance Status (R/O)

STATUS

31:0

Count of limited performance due to platform RAPL

limit.

6A0H

1696

IA32_U_CET

Configure User Mode CET (R/W)

See Table 2-2.

6A2H

1698

IA32_S_CET

Configure Supervisor Mode CET (R/W)

See Table 2-2.

6A4H

1700

IA32_PL0_SSP

Linear address to be loaded into SSP on transition to

privilege level 0. (R/W)

See Table 2-2.

6A5H

1701

IA32_PL1_SSP

Linear address to be loaded into SSP on transition to

privilege level 1. (R/W)

See Table 2-2.

2-354 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-52. Additional MSRs Supported by the 4th Generation Intel® Xeon® Scalable Processor Family

with a CPUID Signature DisplayFamily_DisplayModel Value of 06_8FH

Address

Scope

Bit Description

Hex

Dec

6A6H

1702

IA32_PL2_SSP

Linear address to be loaded into SSP on transition to

privilege level 2. (R/W)

See Table 2-2.

6A7H

1703

IA32_PL3_SSP

Linear address to be loaded into SSP on transition to

privilege level 3. (R/W)

See Table 2-2.

6A8H

1704

IA32_INTERRUPT_SSP_TABLE_ADDR

Linear address of a table of seven shadow stack

pointers that are selected in IA-32e mode using the

IST index (when not 0) from the interrupt gate

descriptor. (R/W)

See Table 2-2.

6E1H

1761

IA32_PKRS

Specifies the PK permissions associated with each

protection domain for supervisor pages (R/W)

See Table 2-2.

776H

1910

IA32_HWP_CTL

See Table 2-2.

981H

2433

IA32_TME_CAPABILITY

Memory Encryption Capability MSR

See Table 2-2.

985H

2437

IA32_UINTR_RR

User Interrupt Request Register (R/W)

See Table 2-2.

986H

2438

IA32_UINTR_HANDLER

User Interrupt Handler Address (R/W)

See Table 2-2.

987H

2439

IA32_UINTR_STACKADJUST

User Interrupt Stack Adjustment (R/W)

See Table 2-2.

988H

2440

IA32_UINTR_MISC

User-Interrupt Target-Table Size and Notification

Vector (R/W)

See Table 2-2.

989H

2441

IA32_UINTR_PD

User Interrupt PID Address (R/W)

See Table 2-2.

98AH

2442

IA32_UINTR_TT

User-Interrupt Target Table (R/W)

See Table 2-2.

C70H

3184

MSR_B1_PMON_EVNT_SEL0

Package

Uncore B-box 1 perfmon event select MSR.

C71H

3185

MSR_B1_PMON_CTR0

Package

Uncore B-box 1 perfmon counter MSR.

C72H

3186

MSR_B1_PMON_EVNT_SEL1

Package

Uncore B-box 1 perfmon event select MSR.

C73H

3187

MSR_B1_PMON_CTR1

Package

Uncore B-box 1 perfmon counter MSR.

C74H

3188

MSR_B1_PMON_EVNT_SEL2

Package

Uncore B-box 1 perfmon event select MSR.

C75H

3189

MSR_B1_PMON_CTR2

Package

Uncore B-box 1 perfmon counter MSR.

Vol. 4

2-355

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-52. Additional MSRs Supported by the 4th Generation Intel® Xeon® Scalable Processor Family

with a CPUID Signature DisplayFamily_DisplayModel Value of 06_8FH

Address

Scope

Bit Description

Hex

Dec

C76H

3190

MSR_B1_PMON_EVNT_SEL3

Package

Uncore B-box 1vperfmon event select MSR.

C77H

3191

MSR_B1_PMON_CTR3

Package

Uncore B-box 1 perfmon counter MSR.

C82H

3122

MSR_W_PMON_BOX_OVF_CTRL

Package

Uncore W-box perfmon local box overflow control

MSR.

C8FH

3215

IA32_PQR_ASSOC

See Table 2-2.

C90H

3216

IA32_L3_QOS_MASK_0 through

Package

See Table 2-50.

IA32_L3_QOS_MASK_14

C9EH

3230

D10H

3344

IA32_L2_QOS_MASK_[0-7]

Core

IA32_CR_L2_QOS_MASK_[0-7]

If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] ≥ 0.

D17H

3351

See Table 2-2.

D93H

3475

IA32_PASID

See Table 2-2.

1200H

4608

IA32_LBR_x_INFO

Last Branch Record Entry X Info Register (R/W)

See Table 2-2.

121FH

4639

1406H

5126

IA32_MCU_CONTROL

See Table 2-2.

14CEH

5326

IA32_LBR_CTL

Last Branch Record Enabling and Configuration

See Table 2-2.

14CFH

5327

IA32_LBR_DEPTH

Last Branch Record Maximum Stack Depth Register

(R/W)

See Table 2-2.

1500H

5376

IA32_LBR_x_FROM_IP

Last Branch Record Entry X Source IP Register (R/W)

See Table 2-2.

151FH

5407

1600H

5632

IA32_LBR_x_TO_IP

Last Branch Record Entry X Destination IP Register

(R/W)

See Table 2-2.

161FH

5663

2.18

MSRS IN THE INTEL® XEON PHI™ PROCESSOR 3200/5200/7200 SERIES

AND THE INTEL® XEON PHI™ PROCESSOR 7215/7285/7295 SERIES

The Intel^® Xeon Phi™ processor 3200, 5200, 7200 series, with a CPUID Signature DisplayFamily_DisplayModel

value of 06_57H, supports the MSR interfaces listed in Table 2-53. These processors are based on the Knights

Landing microarchitecture. The Intel^® Xeon Phi™ processor 7215, 7285, 7295 series, with a CPUID Signature

DisplayFamily_DisplayModel value of 06_85H, supports the MSR interfaces listed in Table 2-53 and Table 2-54.

These processors are based on the Knights Mill microarchitecture. Some MSRs are shared between a pair of

processor cores, and the scope is marked as module.

2-356 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-53. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_57H or 06_85H

Address

Scope

Bit Description

(Former MSR Name)

Hex

Dec

IA32_P5_MC_ADDR

Module

See Section 2.23, “MSRs in Pentium Processors.”

IA32_P5_MC_TYPE

Module

See Section 2.23, “MSRs in Pentium Processors.”

IA32_MONITOR_FILTER_SIZE

Thread

See Section 9.10.5, “Monitor/Mwait Address Range

Determination.” See Table 2-2.

10H

IA32_TIME_STAMP_COUNTER

Thread

See Section 18.17, “Time-Stamp Counter,” and

Table 2-2.

17H

IA32_PLATFORM_ID

Package

Platform ID (R)

See Table 2-2.

1BH

IA32_APIC_BASE

Thread

See Section 11.4.4, “Local APIC Status and Location,”

and Table 2-2.

34H

MSR_SMI_COUNT

Thread

SMI Counter (R/O)

31:0

SMI Count (R/O)

63:32

Reserved

3AH

IA32_FEATURE_CONTROL

Thread

Control Features in Intel 64Processor (R/W)

See Table 2-2.

Lock (R/WL)

Reserved

Enable VMX outside SMX operation (R/WL)

3BH

IA32_TSC_ADJUST

THREAD

Per-Logical-Processor TSC ADJUST (R/W)

See Table 2-2.

4EH

IA32_PPIN_CTL

Package

Protected Processor Inventory Number Enable Control

(R/W)

(MSR_PPIN_CTL)

LockOut (R/WO)

See Table 2-2.

Enable_PPIN (R/W)

See Table 2-2.

63:2

Reserved

4FH

IA32_PPIN

Package

Protected Processor Inventory Number (R/O)

(MSR_PPIN)

63:0

Protected Processor Inventory Number (R/O)

See Table 2-2.

79H

121

IA32_BIOS_UPDT_TRIG

Core

BIOS Update Trigger Register (W)

See Table 2-2.

8BH

139

IA32_BIOS_SIGN_ID

THREAD

BIOS Update Signature ID (R/W)

See Table 2-2.

C1H

193

IA32_PMC0

THREAD

Performance Counter Register

See Table 2-2.

Vol. 4

2-357

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-53. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)

Address

Scope

Bit Description

(Former MSR Name)

Hex

Dec

C2H

194

IA32_PMC1

THREAD

Performance Counter Register

See Table 2-2.

CEH

206

MSR_PLATFORM_INFO

Package

Platform Information

Contains power management and other model specific

features enumeration. See http://biosbits.org.

7:0

Reserved

15:8

Package

Maximum Non-Turbo Ratio (R/O)

This is the ratio of the frequency that invariant TSC runs

at. Frequency = ratio * 100 MHz.

27:16

Reserved

Package

Programmable Ratio Limit for Turbo Mode (R/O)

When set to 1, indicates that Programmable Ratio Limit

for Turbo mode is enabled. When set to 0, indicates

Programmable Ratio Limit for Turbo mode is disabled.

Package

Programmable TDP Limit for Turbo Mode (R/O)

When set to 1, indicates that TDP Limit for Turbo mode

is programmable. When set to 0, indicates TDP Limit for

Turbo mode is not programmable.

39:30

Reserved

47:40

Package

Maximum Efficiency Ratio (R/O)

This is the minimum ratio (maximum efficiency) that the

processor can operate, in units of 100MHz.

63:48

Reserved

E2H

226

MSR_PKG_CST_CONFIG_CONTROL

Package

C-State Configuration Control (R/W)

2-358 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-53. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)

Address

Scope

Bit Description

(Former MSR Name)

Hex

Dec

2:0

Package C-State Limit (R/W)

Specifies the lowest C-state for the package. This

feature does not limit the processor core C-state. The

power-on default value from bit[2:0] of this register

reports the deepest package C-state the processor is

capable to support when manufactured. It is

recommended that BIOS always read the power-on

default value reported from this bit field to determine

the supported deepest C-state on the processor and

leave it as default without changing it.

000b - C0/C1 (No package C-state support)

001b - C2

010b - C6 (non retention)*

011b - C6 (Retention)*

100b - Reserved

101b - Reserved

110b - Reserved

111b - No package C-state limit. All C-States supported

by the processor are available.

Note: C6 retention mode provides more power saving

than C6 non-retention mode. Limiting the package to C6

non retention mode does prevent the

MSR_PKG_C6_RESIDENCY counter (MSR 3F9h) from

being incremented.

9:3

Reserved

I/O MWAIT Redirection Enable (R/W)

When set, will map IO_read instructions sent to IO

registers at MSR_PMG_IO_CAPTURE_BASE[15:0] to

MWAIT instructions.

14:11

Reserved

CFG Lock (R/O)

When set, locks bits [15:0] of this register for further

writes until the next reset occurs.

Reserved

C1 State Auto Demotion Enable (R/W)

When set, the processor will conditionally demote

C3/C6/C7 requests to C1 based on uncore auto-demote

information.

Reserved

C1 State Auto Undemotion Enable (R/W)

When set, enables Undemotion from Demoted C1.

PKG C-State Auto Demotion Enable (R/W)

When set, enables Package C state demotion.

63:30

Reserved

Vol. 4

2-359

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-53. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)

Address

Scope

Bit Description

(Former MSR Name)

Hex

Dec

E4H

228

MSR_PMG_IO_CAPTURE_BASE

Tile

Power Management IO Capture Base (R/W)

15:0

LVL_2 Base Address (R/W)

Microcode will compare IO-read zone to this base

address to determine if an MWAIT(C2/3/4) needs to be

issued instead of the IO-read. Should be programmed to

the chipset Plevel_2 IO address.

22:16

C-State Range (R/W)

The IO-port block size in which IO-redirection will be

executed (0-127). Should be programmed based on the

number of LVLx registers existing in the chipset.

63:23

Reserved

E7H

231

IA32_MPERF

Thread

Maximum Performance Frequency Clock Count (R/W)

See Table 2-2.

E8H

232

IA32_APERF

Thread

Actual Performance Frequency Clock Count (R/W)

See Table 2-2.

FEH

254

IA32_MTRRCAP

Core

Memory Type Range Register (R)

See Table 2-2.

13CH

316

MSR_FEATURE_CONFIG

Core

AES Configuration (RW-L)

Privileged post-BIOS agent must provide a #GP handler

to handle unsuccessful read of this MSR.

1:0

AES Configuration (RW-L)

Upon a successful read of this MSR, the configuration of

AES instruction set availability is as follows:

11b: AES instructions are not available until next RESET.

Otherwise, AES instructions are available.

Note, the AES instruction set is not available if read is

unsuccessful. If the configuration is not 01b, AES

instructions can be mis-configured if a privileged agent

unintentionally writes 11b.

63:2

Reserved

140H

320

MISC_FEATURE_ENABLES

Thread

MISC_FEATURE_ENABLES

Reserved

User Mode MONITOR and MWAIT (R/W)

If set to 1, the MONITOR and MWAIT instructions do not

cause invalid-opcode exceptions when executed with

CPL > 0 or in virtual-8086 mode. If MWAIT is executed

when CPL > 0 or in virtual-8086 mode, and if EAX

indicates a C-state other than C0 or C1, the instruction

operates as if EAX indicated the C-state C1.

63:2

Reserved

174H

372

IA32_SYSENTER_CS

Thread

See Table 2-2.

175H

373

IA32_SYSENTER_ESP

Thread

See Table 2-2.

2-360 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-53. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)

Address

Scope

Bit Description

(Former MSR Name)

Hex

Dec

176H

374

IA32_SYSENTER_EIP

Thread

See Table 2-2.

179H

377

IA32_MCG_CAP

Thread

See Table 2-2.

17AH

378

IA32_MCG_STATUS

Thread

See Table 2-2.

17DH

381

MSR_SMM_MCA_CAP

Thread

Enhanced SMM Capabilities (SMM-RO)

Reports SMM capability Enhancement. Accessible only

while in SMM.

31:0

Bank Support (SMM-RO)

One bit per MCA bank. If the bit is set, that bank

supports Enhanced MCA (Default all 0; does not support

EMCA).

55:32

Reserved

Targeted SMI (SMM-RO)

Set if targeted SMI is supported.

SMM_CPU_SVRSTR (SMM-RO)

Set if SMM SRAM save/restore feature is supported.

SMM_CODE_ACCESS_CHK (SMM-RO)

Set if SMM code access check feature is supported.

Long_Flow_Indication (SMM-RO)

If set to 1, indicates that the SMM long flow indicator is

supported and a host-space interface available to SMM

handler.

63:60

Reserved

186H

390

IA32_PERFEVTSEL0

Thread

Performance Monitoring Event Select Register (R/W)

See Table 2-2.

7:0

Event Select

15:8

UMask

USR

Edge

INT

AnyThread

INV

31:24

CMASK

63:32

Reserved

187H

391

IA32_PERFEVTSEL1

Thread

See Table 2-2.

198H

408

IA32_PERF_STATUS

Package

See Table 2-2.

Vol. 4

2-361

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-53. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)

Address

Scope

Bit Description

(Former MSR Name)

Hex

Dec

199H

409

IA32_PERF_CTL

Thread

See Table 2-2.

19AH

410

IA32_CLOCK_MODULATION

Thread

Clock Modulation (R/W)

See Table 2-2.

19BH

411

IA32_THERM_INTERRUPT

Module

Thermal Interrupt Control (R/W)

See Table 2-2.

19CH

412

IA32_THERM_STATUS

Module

Thermal Monitor Status (R/W)

See Table 2-2.

Thermal Status (R/O)

Thermal Status Log (R/WC0)

PROTCHOT # or FORCEPR# Status (R/O)

PROTCHOT # or FORCEPR# Log (R/WC0)

Critical Temperature Status (R/O)

Critical Temperature Status Log (R/WC0)

Thermal Threshold #1 Status (R/O)

Thermal Threshold #1 Log (R/WC0)

Thermal Threshold #2 Status (R/O)

Thermal Threshold #2 Log (R/WC0)

Power Limitation Status (R/O)

Power Limitation Log (RWC0)