Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023)

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-28. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families (Contd.)

Address

Scope

Bit Description

Hex

Dec

E51H

3665

MSR_C10_PMON_EVNTSEL1

Package

Uncore C-Box 10 Perfmon Event Select for C-Box

10 Counter 1

E52H

3666

MSR_C10_PMON_EVNTSEL2

Package

Uncore C-Box 10 Perfmon Event Select for C-Box

10 Counter 2

E53H

3667

MSR_C10_PMON_EVNTSEL3

Package

Uncore C-Box 10 Perfmon Event Select for C-Box

10 Counter 3

E54H

3668

MSR_C10_PMON_BOX_FILTER

Package

Uncore C-Box 10 Perfmon Box Wide Filter

E56H

3670

MSR_C10_PMON_CTR0

Package

Uncore C-Box 10 Perfmon Counter 0

E57H

3671

MSR_C10_PMON_CTR1

Package

Uncore C-Box 10 Perfmon Counter 1

E58H

3672

MSR_C10_PMON_CTR2

Package

Uncore C-Box 10 Perfmon Counter 2

E59H

3673

MSR_C10_PMON_CTR3

Package

Uncore C-Box 10 Perfmon Counter 3

E5AH

3674

MSR_C10_PMON_BOX_FILTER1

Package

Uncore C-Box 10 Perfmon Box Wide Filter1

E64H

3684

MSR_C11_PMON_BOX_CTL

Package

Uncore C-Box 11 Perfmon Local Box Wide Control

E70H

3696

MSR_C11_PMON_EVNTSEL0

Package

Uncore C-Box 11 Perfmon Event Select for C-Box

11 Counter 0

E71H

3697

MSR_C11_PMON_EVNTSEL1

Package

Uncore C-Box 11 Perfmon Event Select for C-Box

11 Counter 1

E72H

3698

MSR_C11_PMON_EVNTSEL2

Package

Uncore C-Box 11 Perfmon Event Select for C-Box

11 Counter 2

E73H

3699

MSR_C11_PMON_EVNTSEL3

Package

Uncore C-Box 11 Perfmon Event Select for C-Box

11 Counter 3

E74H

3700

MSR_C11_PMON_BOX_FILTER

Package

Uncore C-Box 11 Perfmon Box Wide Filter

E76H

3702

MSR_C11_PMON_CTR0

Package

Uncore C-Box 11 Perfmon Counter 0

E77H

3703

MSR_C11_PMON_CTR1

Package

Uncore C-Box 11 Perfmon Counter 1

E78H

3704

MSR_C11_PMON_CTR2

Package

Uncore C-Box 11 Perfmon Counter 2

E79H

3705

MSR_C11_PMON_CTR3

Package

Uncore C-Box 11 Perfmon Counter 3

E7AH

3706

MSR_C11_PMON_BOX_FILTER1

Package

Uncore C-Box 11 Perfmon Box Wide Filter1

E84H

3716

MSR_C12_PMON_BOX_CTL

Package

Uncore C-Box 12 Perfmon Local Box Wide Control

E90H

3728

MSR_C12_PMON_EVNTSEL0

Package

Uncore C-Box 12 Perfmon Event Select for C-Box

12 Counter 0

E91H

3729

MSR_C12_PMON_EVNTSEL1

Package

Uncore C-Box 12 Perfmon Event Select for C-Box

12 Counter 1

E92H

3730

MSR_C12_PMON_EVNTSEL2

Package

Uncore C-Box 12 Perfmon Event Select for C-Box

12 Counter 2

E93H

3731

MSR_C12_PMON_EVNTSEL3

Package

Uncore C-Box 12 Perfmon Event Select for C-Box

12 Counter 3

E94H

3732

MSR_C12_PMON_BOX_FILTER

Package

Uncore C-Box 12 Perfmon Box Wide Filter

E96H

3734

MSR_C12_PMON_CTR0

Package

Uncore C-Box 12 Perfmon Counter 0

E97H

3735

MSR_C12_PMON_CTR1

Package

Uncore C-Box 12 Perfmon Counter 1

E98H

3736

MSR_C12_PMON_CTR2

Package

Uncore C-Box 12 Perfmon Counter 2

Vol. 4

2-225

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-28. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families (Contd.)

Address

Scope

Bit Description

Hex

Dec

E99H

3737

MSR_C12_PMON_CTR3

Package

Uncore C-Box 12 Perfmon Counter 3

E9AH

3738

MSR_C12_PMON_BOX_FILTER1

Package

Uncore C-Box 12 Perfmon Box Wide Filter1

EA4H

3748

MSR_C13_PMON_BOX_CTL

Package

Uncore C-Box 13 Perfmon Local Box Wide Control

EB0H

3760

MSR_C13_PMON_EVNTSEL0

Package

Uncore C-Box 13 Perfmon Event Select for C-Box

13 Counter 0

EB1H

3761

MSR_C13_PMON_EVNTSEL1

Package

Uncore C-Box 13 Perfmon Event Select for C-Box

13 Counter 1

EB2H

3762

MSR_C13_PMON_EVNTSEL2

Package

Uncore C-Box 13 Perfmon Event Select for C-Box

13 Counter 2

EB3H

3763

MSR_C13_PMON_EVNTSEL3

Package

Uncore C-Box 13 Perfmon Event Select for C-Box

13 Counter 3

EB4H

3764

MSR_C13_PMON_BOX_FILTER

Package

Uncore C-Box 13 Perfmon Box Wide Filter

EB6H

3766

MSR_C13_PMON_CTR0

Package

Uncore C-Box 13 Perfmon Counter 0

EB7H

3767

MSR_C13_PMON_CTR1

Package

Uncore C-Box 13 Perfmon Counter 1

EB8H

3768

MSR_C13_PMON_CTR2

Package

Uncore C-Box 13 Perfmon Counter 2

EB9H

3769

MSR_C13_PMON_CTR3

Package

Uncore C-Box 13 Perfmon Counter 3

EBAH

3770

MSR_C13_PMON_BOX_FILTER1

Package

Uncore C-Box 13 Perfmon Box Wide Filter1

EC4H

3780

MSR_C14_PMON_BOX_CTL

Package

Uncore C-Box 14 Perfmon Local Box Wide Control

ED0H

3792

MSR_C14_PMON_EVNTSEL0

Package

Uncore C-Box 14 Perfmon Event Select for C-Box

14 Counter 0

ED1H

3793

MSR_C14_PMON_EVNTSEL1

Package

Uncore C-Box 14 Perfmon Event Select for C-Box

14 Counter 1

ED2H

3794

MSR_C14_PMON_EVNTSEL2

Package

Uncore C-Box 14 Perfmon Event Select for C-Box

14 Counter 2

ED3H

3795

MSR_C14_PMON_EVNTSEL3

Package

Uncore C-Box 14 Perfmon Event Select for C-Box

14 Counter 3

ED4H

3796

MSR_C14_PMON_BOX_FILTER

Package

Uncore C-Box 14 Perfmon Box Wide Filter

ED6H

3798

MSR_C14_PMON_CTR0

Package

Uncore C-Box 14 Perfmon Counter 0

ED7H

3799

MSR_C14_PMON_CTR1

Package

Uncore C-Box 14 Perfmon Counter 1

ED8H

3800

MSR_C14_PMON_CTR2

Package

Uncore C-Box 14 Perfmon Counter 2

ED9H

3801

MSR_C14_PMON_CTR3

Package

Uncore C-Box 14 Perfmon Counter 3

EDAH

3802

MSR_C14_PMON_BOX_FILTER1

Package

Uncore C-Box 14 Perfmon Box Wide Filter1

2.13

MSRS IN THE 4TH GENERATION INTEL® CORE™ PROCESSORS BASED ON

HASWELL MICROARCHITECTURE

The 4th generation Intel^® Core™ processor family and the Intel^® Xeon^® processor E3-1200v3 product family

(based on Haswell microarchitecture), with a CPUID Signature DisplayFamily_DisplayModel value of 06_3CH,

06_45H, or 06_46H, support the MSR interfaces listed in Table 2-20, Table 2-21, Table 2-22, and Table 2-29. For an

MSR listed in Table 2-20 that also appears in Table 2-29, Table 2-29 supersedes Table 2-20.

2-226 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

The MSRs listed in Table 2-29 also apply to processors based on Haswell-E microarchitecture (see Section 2.14).

Table 2-29. Additional MSRs Supported by Processors Based on the Haswell and Haswell-E Microarchitectures

Address

Scope

Bit Description

Hex

Dec

3BH

IA32_TSC_ADJUST

Thread

Per-Logical-Processor TSC ADJUST (R/W)

See Table 2-2.

CEH

206

MSR_PLATFORM_INFO

Package

Platform Information

Contains power management and other model

specific features enumeration. See

http://biosbits.org.

7:0

Reserved

15:8

Package

Maximum Non-Turbo Ratio (R/O)

This is the ratio of the frequency that invariant TSC

runs at. Frequency = ratio * 100 MHz.

27:16

Reserved

Package

Programmable Ratio Limit for Turbo Mode (R/O)

When set to 1, indicates that Programmable Ratio

Limit for Turbo mode is enabled. When set to 0,

indicates Programmable Ratio Limit for Turbo mode

is disabled.

Package

Programmable TDP Limit for Turbo Mode (R/O)

When set to 1, indicates that TDP Limit for Turbo

mode is programmable. When set to 0, indicates TDP

Limit for Turbo mode is not programmable.

31:30

Reserved

Package

Low Power Mode Support (LPM) (R/O)

When set to 1, indicates that LPM is supported.

When set to 0, indicates LPM is not supported.

34:33

Package

Number of ConfigTDP Levels (R/O)

00: Only Base TDP level available.

01: One additional TDP level available.

02: Two additional TDP level available.

03: Reserved

39:35

Reserved

47:40

Package

Maximum Efficiency Ratio (R/O)

This is the minimum ratio (maximum efficiency) that

the processor can operate, in units of 100MHz.

55:48

Package

Minimum Operating Ratio (R/O)

Contains the minimum supported operating ratio in

units of 100 MHz.

63:56

Reserved

186H

390

IA32_PERFEVTSEL0

Thread

Performance Event Select for Counter 0 (R/W)

Supports all fields described inTable 2-2 and the

fields below.

Vol. 4

2-227

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-29. Additional MSRs Supported by Processors Based on the Haswell and Haswell-E Microarchitectures

Address

Scope

Bit Description

Hex

Dec

IN_TX: See Section 20.3.6.5.1.

When IN_TX (bit 32) is set, AnyThread (bit 21)

should be cleared to prevent incorrect results.

187H

391

IA32_PERFEVTSEL1

Thread

Performance Event Select for Counter 1 (R/W)

Supports all fields described inTable 2-2 and the

fields below.

IN_TX: See Section 20.3.6.5.1.

When IN_TX (bit 32) is set, AnyThread (bit 21)

should be cleared to prevent incorrect results.

188H

392

IA32_PERFEVTSEL2

Thread

Performance Event Select for Counter 2 (R/W)

Supports all fields described inTable 2-2 and the

fields below.

IN_TX: See Section 20.3.6.5.1.

When IN_TX (bit 32) is set, AnyThread (bit 21)

should be cleared to prevent incorrect results.

IN_TXCP: See Section 20.3.6.5.1.

When IN_TXCP=1 & IN_TX=1 and in sampling, a

spurious PMI may occur and transactions may

continuously abort near overflow conditions.

Software should favor using IN_TXCP for counting

over sampling. If sampling, software should use large

“sample-after” value after clearing the counter

configured to use IN_TXCP and also always reset the

counter even when no overflow condition was

reported.

189H

393

IA32_PERFEVTSEL3

Thread

Performance Event Select for Counter 3 (R/W)

Supports all fields described inTable 2-2 and the

fields below.

IN_TX: See Section 20.3.6.5.1

When IN_TX (bit 32) is set, AnyThread (bit 21)

should be cleared to prevent incorrect results.

1C8H

456

MSR_LBR_SELECT

Thread

Last Branch Record Filtering Select Register (R/W)

CPL_EQ_0

CPL_NEQ_0

JCC

NEAR_REL_CALL

NEAR_IND_CALL

NEAR_RET

NEAR_IND_JMP

NEAR_REL_JMP

FAR_BRANCH

EN_CALL_STACK

2-228 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-29. Additional MSRs Supported by Processors Based on the Haswell and Haswell-E Microarchitectures

Address

Scope

Bit Description

Hex

Dec

63:9

Reserved

1D9H

473

IA32_DEBUGCTL

Thread

Debug Control (R/W)

See Table 2-2.

LBR: Last Branch Record

BTF

5:2

Reserved

TR: Branch Trace

BTS: Log Branch Trace Message to BTS Buffer

BTINT

BTS_OFF_OS

BTS_OFF_USER

FREEZE_LBR_ON_PMI

FREEZE_PERFMON_ON_PMI

ENABLE_UNCORE_PMI

FREEZE_WHILE_SMM

RTM_DEBUG

63:15

Reserved

491H

1169

IA32_VMX_VMFUNC

Thread

Capability Reporting Register of VM-Function

Controls (R/O)

See Table 2-2.

60BH

1548

MSR_PKGC_IRTL1

Package

Package C6/C7 Interrupt Response Limit 1 (R/W)

This MSR defines the interrupt response time limit

used by the processor to manage a transition to a

package C6 or C7 state. The latency programmed in

this register is for the shorter-latency sub C-states

used by an MWAIT hint to a C6 or C7 state.

Note: C-state values are processor specific C-state

code names, unrelated to MWAIT extension C-state

parameters or ACPI C-States.

9:0

Interrupt Response Time Limit (R/W)

Specifies the limit that should be used to decide if

the package should be put into a package C6 or C7

state.

12:10

Time Unit (R/W)

Specifies the encoding value of time unit of the

interrupt response time limit. See Table 2-20 for

supported time unit encodings.

14:13

Reserved

Valid (R/W)

Indicates whether the values in bits 12:0 are valid

and can be used by the processor for package C-sate

management.

Vol. 4

2-229

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-29. Additional MSRs Supported by Processors Based on the Haswell and Haswell-E Microarchitectures

Address

Scope

Bit Description

Hex

Dec

63:16

Reserved

60CH

1548

MSR_PKGC_IRTL2

Package

Package C6/C7 Interrupt Response Limit 2 (R/W)

This MSR defines the interrupt response time limit

used by the processor to manage a transition to a

package C6 or C7 state. The latency programmed in

this register is for the longer-latency sub C-states

used by an MWAIT hint to a C6 or C7 state.

Note: C-state values are processor specific C-state

code names, unrelated to MWAIT extension C-state

parameters or ACPI C-States.

9:0

Interrupt response time limit (R/W)

Specifies the limit that should be used to decide if

the package should be put into a package C6 or C7

state.

12:10

Time Unit (R/W)

Specifies the encoding value of time unit of the

interrupt response time limit. See Table 2-20 for

supported time unit encodings.

14:13

Reserved

Valid (R/W)

Indicates whether the values in bits 12:0 are valid

and can be used by the processor for package C-sate

management.

63:16

Reserved

613H

1555

MSR_PKG_PERF_STATUS

Package

PKG Perf Status (R/O)

See Section 15.10.3, “Package RAPL Domain.”

619H

1561

MSR_DRAM_ENERGY_STATUS

Package

DRAM Energy Status (R/O)

See Section 15.10.5, “DRAM RAPL Domain.”

61BH

1563

MSR_DRAM_PERF_STATUS

Package

DRAM Performance Throttling Status (R/O)

See Section 15.10.5, “DRAM RAPL Domain.”

648H

1608

MSR_CONFIG_TDP_NOMINAL

Package

Base TDP Ratio (R/O)

7:0

Config_TDP_Base

Base TDP level ratio to be used for this specific

processor (in units of 100 MHz).

63:8

Reserved

649H

1609

MSR_CONFIG_TDP_LEVEL1

Package

ConfigTDP Level 1 Ratio and Power Level (R/O)

14:0

PKG_TDP_LVL1

Power setting for ConfigTDP Level 1.

Reserved

23:16

Config_TDP_LVL1_Ratio

ConfigTDP level 1 ratio to be used for this specific

processor.

31:24

Reserved

2-230 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-29. Additional MSRs Supported by Processors Based on the Haswell and Haswell-E Microarchitectures

Address

Scope

Bit Description

Hex

Dec

46:32

PKG_MAX_PWR_LVL1

Max Power setting allowed for ConfigTDP Level 1.

62:47

PKG_MIN_PWR_LVL1

MIN Power setting allowed for ConfigTDP Level 1.

Reserved

64AH

1610

MSR_CONFIG_TDP_LEVEL2

Package

ConfigTDP Level 2 Ratio and Power Level (R/O)

14:0

PKG_TDP_LVL2

Power setting for ConfigTDP Level 2.

Reserved

23:16

Config_TDP_LVL2_Ratio

ConfigTDP level 2 ratio to be used for this specific

processor.

31:24

Reserved

46:32

PKG_MAX_PWR_LVL2

Max Power setting allowed for ConfigTDP Level 2.

62:47

PKG_MIN_PWR_LVL2

MIN Power setting allowed for ConfigTDP Level 2.

Reserved

64BH

1611

MSR_CONFIG_TDP_CONTROL

Package

ConfigTDP Control (R/W)

1:0

TDP_LEVEL (RW/L)

System BIOS can program this field.

30:2

Reserved

Config_TDP_Lock (RW/L)

When this bit is set, the content of this register is

locked until a reset.

63:32

Reserved

64CH

1612

MSR_TURBO_ACTIVATION_RATIO

Package

ConfigTDP Control (R/W)

7:0

MAX_NON_TURBO_RATIO (RW/L)

System BIOS can program this field.

30:8

Reserved

TURBO_ACTIVATION_RATIO_Lock (RW/L)

When this bit is set, the content of this register is

locked until a reset.

63:32

Reserved

C80H

3200

IA32_DEBUG_INTERFACE

Package

Silicon Debug Feature Control (R/W)

See Table 2-2.

Vol. 4

2-231

MODEL-SPECIFIC REGISTERS (MSRS)

2.13.1 MSRs in the 4th Generation Intel® Core™ Processor Family Based on Haswell

Microarchitecture

Table 2-30 lists model-specific registers (MSRs) that are specific to the 4th generation Intel^® Core™ processor

family and the Intel^® Xeon^® processor E3-1200 v3 product family (based on Haswell microarchitecture). These

processors have a CPUID Signature DisplayFamily_DisplayModel value of 06_3CH, 06_45H, or 06_46H; see Table

2-1.

Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture)

Address

Scope

Bit Description

Hex

Dec

E2H

226

MSR_PKG_CST_CONFIG_CONTROL

Core

C-State Configuration Control (R/W)

Note: C-state values are processor specific C-state

code names, unrelated to MWAIT extension C-state

parameters or ACPI C-states.

See http://biosbits.org.

3:0

Package C-State Limit (R/W)

Specifies the lowest processor-specific C-state code

name (consuming the least power) for the package.

The default is set as factory-configured package C-

state limit.

The following C-state code name encodings are

supported:

0000b: C0/C1 (no package C-state support)

0001b: C2

0010b: C3

0011b: C6

0100b: C7

0101b: C7s

Package C states C7 are not available to processors

with a CPUID Signature DisplayFamily_DisplayModel

value of 06_3CH.

9:4

Reserved

I/O MWAIT Redirection Enable (R/W)

14:11

Reserved

CFG Lock (R/WO)

24:16

Reserved

C3 State Auto Demotion Enable (R/W)

C1 State Auto Demotion Enable (R/W)

Enable C3 Undemotion (R/W)

Enable C1 Undemotion (R/W)

63:29

Reserved

17DH

381

MSR_SMM_MCA_CAP

THREAD

Enhanced SMM Capabilities (SMM-RO)

Reports SMM capability Enhancement. Accessible

only while in SMM.

57:0

Reserved

2-232 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)

Address

Scope

Bit Description

Hex

Dec

SMM_Code_Access_Chk (SMM-RO)

If set to 1, indicates that the SMM code access

restriction is supported and the

MSR_SMM_FEATURE_CONTROL is supported.

Long_Flow_Indication (SMM-RO)

If set to 1, indicates that the SMM long flow indicator

is supported and the MSR_SMM_DELAYED is

supported.

63:60

Reserved

1ADH

429

MSR_TURBO_RATIO_LIMIT

Package

Maximum Ratio Limit of Turbo Mode

R/O if MSR_PLATFORM_INFO.[28] = 0.

R/W if MSR_PLATFORM_INFO.[28] = 1.

7:0

Package

Maximum Ratio Limit for 1C

Maximum turbo ratio limit of 1 core active.

15:8

Package

Maximum Ratio Limit for 2C

Maximum turbo ratio limit of 2 core active.

23:16

Package

Maximum Ratio Limit for 3C

Maximum turbo ratio limit of 3 core active.

31:24

Package

Maximum Ratio Limit for 4C

Maximum turbo ratio limit of 4 core active.

63:32

Reserved

391H

913

MSR_UNC_PERF_GLOBAL_CTRL

Package

Uncore PMU Global Control

Core 0 select.

Core 1 select.

Core 2 select.

Core 3 select.

18:4

Reserved

Enable all uncore counters.

Enable wake on PMI.

Enable Freezing counter when overflow.

63:32

Reserved

392H

914

MSR_UNC_PERF_GLOBAL_STATUS

Package

Uncore PMU Main Status

Fixed counter overflowed.

An ARB counter overflowed.

Reserved

A CBox counter overflowed (on any slice).

63:4

Reserved

394H

916

MSR_UNC_PERF_FIXED_CTRL

Package

Uncore Fixed Counter Control (R/W)

19:0

Reserved

Vol. 4

2-233

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)

Address

Scope

Bit Description

Hex

Dec

Enable overflow propagation.

Reserved

Enable counting.

63:23

Reserved

395H

917

MSR_UNC_PERF_FIXED_CTR

Package

Uncore Fixed Counter

47:0

Current count.

63:48

Reserved

396H

918

MSR_UNC_CBO_CONFIG

Package

Uncore C-Box Configuration Information (R/O)

3:0

Encoded number of C-Box, derive value by “-1“.

63:4

Reserved

3B0H

946

MSR_UNC_ARB_PERFCTR0

Package

Uncore Arb Unit, Performance Counter 0

3B1H

947

MSR_UNC_ARB_PERFCTR1

Package

Uncore Arb Unit, Performance Counter 1

3B2H

944

MSR_UNC_ARB_PERFEVTSEL0

Package

Uncore Arb Unit, Counter 0 Event Select MSR

3B3H

945

MSR_UNC_ARB_PERFEVTSEL1

Package

Uncore Arb Unit, Counter 1 Event Select MSR

391H

913

MSR_UNC_PERF_GLOBAL_CTRL

Package

Uncore PMU Global Control

Core 0 select.

Core 1 select.

Core 2 select.

Core 3 select.

18:4

Reserved

Enable all uncore counters.

Enable wake on PMI.

Enable Freezing counter when overflow.

63:32

Reserved

395H

917

MSR_UNC_PERF_FIXED_CTR

Package

Uncore Fixed Counter

47:0

Current count.

63:48

Reserved

3B3H

945

MSR_UNC_ARB_PERFEVTSEL1

Package

Uncore Arb Unit, Counter 1 Event Select MSR

4E0H

1248

MSR_SMM_FEATURE_CONTROL

Package

Enhanced SMM Feature Control (SMM-RW)

Reports SMM capability Enhancement. Accessible

only while in SMM.

Lock (SMM-RWO)

When set to ‘1’ locks this register from further

changes.

Reserved

2-234 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)

Address

Scope

Bit Description

Hex

Dec

SMM_Code_Chk_En (SMM-RW)

This control bit is available only if

MSR_SMM_MCA_CAP[58] == 1. When set to ‘0’

(default) none of the logical processors are

prevented from executing SMM code outside the

ranges defined by the SMRR.

When set to ‘1’ any logical processor in the package

that attempts to execute SMM code not within the

ranges defined by the SMRR will assert an

unrecoverable MCE.

63:3

Reserved

4E2H

1250

MSR_SMM_DELAYED

Package

SMM Delayed (SMM-RO)

Reports the interruptible state of all logical

processors in the package. Available only while in

SMM and

MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] ==

N-1:0

LOG_PROC_STATE (SMM-RO)

Each bit represents a logical processor of its state in

a long flow of internal operation which delays

servicing an interrupt. The corresponding bit will be

set at the start of long events such as: Microcode

Update Load, C6, WBINVD, Ratio Change, Throttle.

The bit is automatically cleared at the end of each

long event. The reset value of this field is 0.

Only bit positions below N = CPUID.(EAX=0BH,

ECX=PKG_LVL):EBX[15:0] can be updated.

63:N

Reserved

4E3H

1251

MSR_SMM_BLOCKED

Package

SMM Blocked (SMM-RO)

Reports the blocked state of all logical processors in

the package. Available only while in SMM.

N-1:0

LOG_PROC_STATE (SMM-RO)

Each bit represents a logical processor of its blocked

state to service an SMI. The corresponding bit will be

set if the logical processor is in one of the following

states: Wait For SIPI or SENTER Sleep.

The reset value of this field is 0FFFH.

Only bit positions below N = CPUID.(EAX=0BH,

ECX=PKG_LVL):EBX[15:0] can be updated.

63:N

Reserved

606H

1542

MSR_RAPL_POWER_UNIT

Package

Unit Multipliers Used in RAPL Interfaces (R/O)

3:0

Package

Power Units

See Section 15.10.1, “RAPL Interfaces.”

7:4

Package

Reserved

Vol. 4

2-235

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)

Address

Scope

Bit Description

Hex

Dec

12:8

Package

Energy Status Units

Energy related information (in Joules) is based on the

multiplier, 1/2^ESU; where ESU is an unsigned

integer represented by bits 12:8. Default value is

0EH (or 61 micro-joules).

15:13

Package

Reserved

19:16

Package

Time Units

See Section 15.10.1, “RAPL Interfaces.”

63:20

Reserved

639H

1593

MSR_PP0_ENERGY_STATUS

Package

PP0 Energy Status (R/O)

See Section 15.10.4, “PP0/PP1 RAPL Domains.”

640H

1600

MSR_PP1_POWER_LIMIT

Package

PP1 RAPL Power Limit Control (R/W)

See Section 15.10.4, “PP0/PP1 RAPL Domains.”

641H

1601

MSR_PP1_ENERGY_STATUS

Package

PP1 Energy Status (R/O)

See Section 15.10.4, “PP0/PP1 RAPL Domains.”

642H

1602

MSR_PP1_POLICY

Package

PP1 Balance Policy (R/W)

See Section 15.10.4, “PP0/PP1 RAPL Domains.”

690H

1680

MSR_CORE_PERF_LIMIT_REASONS

Package

Indicator of Frequency Clipping in Processor Cores

(R/W)

(Frequency refers to processor core frequency.)

PROCHOT Status (R0)

When set, processor core frequency is reduced below

the operating system request due to assertion of

external PROCHOT.

Thermal Status (R0)

When set, frequency is reduced below the operating

system request due to a thermal event.

3:2

Reserved

Graphics Driver Status (R0)

When set, frequency is reduced below the operating

system request due to Processor Graphics driver

override.

Autonomous Utilization-Based Frequency Control

Status (R0)

When set, frequency is reduced below the operating

system request because the processor has detected

that utilization is low.

VR Therm Alert Status (R0)

When set, frequency is reduced below the operating

system request due to a thermal alert from the

Voltage Regulator.

Reserved

2-236 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)

Address

Scope

Bit Description

Hex

Dec

Electrical Design Point Status (R0)

When set, frequency is reduced below the operating

system request due to electrical design point

constraints (e.g., maximum electrical current

consumption).

Core Power Limiting Status (R0)

When set, frequency is reduced below the operating

system request due to domain-level power limiting.

Package-Level Power Limiting PL1 Status (R0)

When set, frequency is reduced below the operating

system request due to package-level power limiting

PL1.

Package-Level PL2 Power Limiting Status (R0)

When set, frequency is reduced below the operating

system request due to package-level power limiting

PL2.

Max Turbo Limit Status (R0)

When set, frequency is reduced below the operating

system request due to multi-core turbo limits.

Turbo Transition Attenuation Status (R0)

When set, frequency is reduced below the operating

system request due to Turbo transition attenuation.

This prevents performance degradation due to

frequent operating ratio changes.

15:14

Reserved

PROCHOT Log

When set, indicates that the PROCHOT Status bit has

asserted since the log bit was last cleared.

This log bit will remain set until cleared by software

writing 0.

Thermal Log

When set, indicates that the Thermal Status bit has

asserted since the log bit was last cleared.

This log bit will remain set until cleared by software

writing 0.

19:18

Reserved

Graphics Driver Log

When set, indicates that the Graphics Driver Status

bit has asserted since the log bit was last cleared.

This log bit will remain set until cleared by software

writing 0.

Vol. 4

2-237

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)

Address

Scope

Bit Description

Hex

Dec

Autonomous Utilization-Based Frequency Control Log

When set, indicates that the Autonomous Utilization-

Based Frequency Control Status bit has asserted

since the log bit was last cleared.

This log bit will remain set until cleared by software

writing 0.

VR Therm Alert Log

When set, indicates that the VR Therm Alert Status

bit has asserted since the log bit was last cleared.

This log bit will remain set until cleared by software

writing 0.

Reserved

Electrical Design Point Log

When set, indicates that the EDP Status bit has

asserted since the log bit was last cleared.

This log bit will remain set until cleared by software

writing 0.

Core Power Limiting Log

When set, indicates that the Core Power Limiting

Status bit has asserted since the log bit was last

cleared.

This log bit will remain set until cleared by software

writing 0.

Package-Level PL1 Power Limiting Log

When set, indicates that the Package Level PL1

Power Limiting Status bit has asserted since the log

bit was last cleared.

This log bit will remain set until cleared by software

writing 0.

Package-Level PL2 Power Limiting Log

When set, indicates that the Package Level PL2

Power Limiting Status bit has asserted since the log

bit was last cleared.

This log bit will remain set until cleared by software

writing 0.

Max Turbo Limit Log

When set, indicates that the Max Turbo Limit Status

bit has asserted since the log bit was last cleared.

This log bit will remain set until cleared by software

writing 0.

2-238 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)

Address

Scope

Bit Description

Hex

Dec

Turbo Transition Attenuation Log

When set, indicates that the Turbo Transition

Attenuation Status bit has asserted since the log bit

was last cleared.

This log bit will remain set until cleared by software

writing 0.

63:30

Reserved

6B0H

1712

MSR_GRAPHICS_PERF_LIMIT_REASONS

Package

Indicator of Frequency Clipping in the Processor

Graphics (R/W)

(Frequency refers to processor graphics frequency.)

PROCHOT Status (R0)

When set, frequency is reduced below the operating

system request due to assertion of external

PROCHOT.

Thermal Status (R0)

When set, frequency is reduced below the operating

system request due to a thermal event.

3:2

Reserved

Graphics Driver Status (R0)

When set, frequency is reduced below the operating

system request due to Processor Graphics driver

override.

Autonomous Utilization-Based Frequency Control

Status (R0)

When set, frequency is reduced below the operating

system request because the processor has detected

that utilization is low.

VR Therm Alert Status (R0)

When set, frequency is reduced below the operating

system request due to a thermal alert from the

Voltage Regulator.

Reserved

Electrical Design Point Status (R0)

When set, frequency is reduced below the operating

system request due to electrical design point

constraints (e.g., maximum electrical current

consumption).

Graphics Power Limiting Status (R0)

When set, frequency is reduced below the operating

system request due to domain-level power limiting.

Package-Level Power Limiting PL1 Status (R0)

When set, frequency is reduced below the operating

system request due to package-level power limiting

PL1.

Vol. 4

2-239

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)

Address

Scope

Bit Description

Hex

Dec

Package-Level PL2 Power Limiting Status (R0)

When set, frequency is reduced below the operating

system request due to package-level power limiting

PL2.

15:12

Reserved

PROCHOT Log

When set, indicates that the PROCHOT Status bit has

asserted since the log bit was last cleared.

This log bit will remain set until cleared by software

writing 0.

Thermal Log

When set, indicates that the Thermal Status bit has

asserted since the log bit was last cleared.

This log bit will remain set until cleared by software

writing 0.

19:18

Reserved

Graphics Driver Log

When set, indicates that the Graphics Driver Status

bit has asserted since the log bit was last cleared.

This log bit will remain set until cleared by software

writing 0.

Autonomous Utilization-Based Frequency Control Log

When set, indicates that the Autonomous Utilization-

Based Frequency Control Status bit has asserted

since the log bit was last cleared.

This log bit will remain set until cleared by software

writing 0.

VR Therm Alert Log

When set, indicates that the VR Therm Alert Status

bit has asserted since the log bit was last cleared.

This log bit will remain set until cleared by software

writing 0.

Reserved

Electrical Design Point Log

When set, indicates that the EDP Status bit has

asserted since the log bit was last cleared.

This log bit will remain set until cleared by software

writing 0.

Core Power Limiting Log

When set, indicates that the Core Power Limiting

Status bit has asserted since the log bit was last

cleared.

This log bit will remain set until cleared by software

writing 0.

2-240 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)

Address

Scope

Bit Description

Hex

Dec

Package-Level PL1 Power Limiting Log

When set, indicates that the Package Level PL1

Power Limiting Status bit has asserted since the log

bit was last cleared.

This log bit will remain set until cleared by software

writing 0.

Package-Level PL2 Power Limiting Log

When set, indicates that the Package Level PL2

Power Limiting Status bit has asserted since the log

bit was last cleared.

This log bit will remain set until cleared by software

writing 0.

Max Turbo Limit Log

When set, indicates that the Max Turbo Limit Status

bit has asserted since the log bit was last cleared.

This log bit will remain set until cleared by software

writing 0.

Turbo Transition Attenuation Log

When set, indicates that the Turbo Transition

Attenuation Status bit has asserted since the log bit

was last cleared.

This log bit will remain set until cleared by software

writing 0.

63:30

Reserved

6B1H

1713

MSR_RING_PERF_LIMIT_REASONS

Package

Indicator of Frequency Clipping in the Ring

Interconnect (R/W)

(Frequency refers to ring interconnect in the uncore.)

PROCHOT Status (R0)

When set, frequency is reduced below the operating

system request due to assertion of external

PROCHOT.

Thermal Status (R0)

When set, frequency is reduced below the operating

system request due to a thermal event.

5:2

Reserved

VR Therm Alert Status (R0)

When set, frequency is reduced below the operating

system request due to a thermal alert from the

Voltage Regulator.

Reserved

Electrical Design Point Status (R0)

When set, frequency is reduced below the operating

system request due to electrical design point

constraints (e.g., maximum electrical current

consumption).

Vol. 4

2-241

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)

Address

Scope

Bit Description

Hex

Dec

Reserved

Package-Level Power Limiting PL1 Status (R0)

When set, frequency is reduced below the operating

system request due to package-level power limiting

PL1.

Package-Level PL2 Power Limiting Status (R0)

When set, frequency is reduced below the operating

system request due to package-level power limiting

PL2.

15:12

Reserved

PROCHOT Log

When set, indicates that the PROCHOT Status bit has

asserted since the log bit was last cleared.

This log bit will remain set until cleared by software

writing 0.

Thermal Log

When set, indicates that the Thermal Status bit has

asserted since the log bit was last cleared.

This log bit will remain set until cleared by software

writing 0.

19:18

Reserved.

Graphics Driver Log

When set, indicates that the Graphics Driver Status

bit has asserted since the log bit was last cleared.

This log bit will remain set until cleared by software

writing 0.

Autonomous Utilization-Based Frequency Control Log

When set, indicates that the Autonomous Utilization-

Based Frequency Control Status bit has asserted

since the log bit was last cleared.

This log bit will remain set until cleared by software

writing 0.

VR Therm Alert Log

When set, indicates that the VR Therm Alert Status

bit has asserted since the log bit was last cleared.

This log bit will remain set until cleared by software

writing 0.

Reserved

Electrical Design Point Log

When set, indicates that the EDP Status bit has

asserted since the log bit was last cleared.

This log bit will remain set until cleared by software

writing 0.

2-242 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)

Address

Scope

Bit Description

Hex

Dec

Core Power Limiting Log

When set, indicates that the Core Power Limiting

Status bit has asserted since the log bit was last

cleared.

This log bit will remain set until cleared by software

writing 0.

Package-Level PL1 Power Limiting Log

When set, indicates that the Package Level PL1

Power Limiting Status bit has asserted since the log

bit was last cleared.

This log bit will remain set until cleared by software

writing 0.

Package-Level PL2 Power Limiting Log

When set, indicates that the Package Level PL2

Power Limiting Status bit has asserted since the log

bit was last cleared.

This log bit will remain set until cleared by software

writing 0.

Max Turbo Limit Log

When set, indicates that the Max Turbo Limit Status

bit has asserted since the log bit was last cleared.

This log bit will remain set until cleared by software

writing 0.

Turbo Transition Attenuation Log

When set, indicates that the Turbo Transition

Attenuation Status bit has asserted since the log bit

was last cleared.

This log bit will remain set until cleared by software

writing 0.

63:30

Reserved

700H

1792

MSR_UNC_CBO_0_PERFEVTSEL0

Package

Uncore C-Box 0, Counter 0 Event Select MSR

701H

1793

MSR_UNC_CBO_0_PERFEVTSEL1

Package

Uncore C-Box 0, Counter 1 Event Select MSR

706H

1798

MSR_UNC_CBO_0_PERFCTR0

Package

Uncore C-Box 0, Performance Counter 0

707H

1799

MSR_UNC_CBO_0_PERFCTR1

Package

Uncore C-Box 0, Performance Counter 1

710H

1808

MSR_UNC_CBO_1_PERFEVTSEL0

Package

Uncore C-Box 1, Counter 0 Event Select MSR

711H

1809

MSR_UNC_CBO_1_PERFEVTSEL1

Package

Uncore C-Box 1, Counter 1 Event Select MSR

716H

1814

MSR_UNC_CBO_1_PERFCTR0

Package

Uncore C-Box 1, Performance Counter 0

717H

1815

MSR_UNC_CBO_1_PERFCTR1

Package

Uncore C-Box 1, Performance Counter 1

720H

1824

MSR_UNC_CBO_2_PERFEVTSEL0

Package

Uncore C-Box 2, Counter 0 Event Select MSR

721H

1824

MSR_UNC_CBO_2_PERFEVTSEL1

Package

Uncore C-Box 2, Counter 1 Event Select MSR

726H

1830

MSR_UNC_CBO_2_PERFCTR0

Package

Uncore C-Box 2, Performance Counter 0

727H

1831

MSR_UNC_CBO_2_PERFCTR1

Package

Uncore C-Box 2, Performance Counter 1

Vol. 4

2-243

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)

Address

Scope

Bit Description

Hex

Dec

730H

1840

MSR_UNC_CBO_3_PERFEVTSEL0

Package

Uncore C-Box 3, Counter 0 Event Select MSR

731H

1841

MSR_UNC_CBO_3_PERFEVTSEL1

Package

Uncore C-Box 3, Counter 1 Event Select MSR

736H

1846

MSR_UNC_CBO_3_PERFCTR0

Package

Uncore C-Box 3, Performance Counter 0

737H

1847

MSR_UNC_CBO_3_PERFCTR1

Package

Uncore C-Box 3, Performance Counter 1

See Table 2-20, Table 2-21, Table 2-22, Table 2-25, and Table 2-29 for other MSR definitions applicable to processors with a CPUID

Signature DisplayFamily_DisplayModel value of 063CH or 06_46H.

2.13.2 Additional Residency MSRs Supported in 4th Generation Intel® Core™ Processors

The 4th generation Intel^® Core™ processor family (based on Haswell microarchitecture) with a CPUID Signature

DisplayFamily_DisplayModel value of 06_45H supports the MSR interfaces listed in Table 2-20, Table 2-21, Table

2-29, Table 2-30, and Table 2-31.

Table 2-31. Additional Residency MSRs Supported by 4th Generation Intel® Core™ Processors with a

CPUID Signature DisplayFamily_DisplayModel Value of 06_45H

Address

Scope

Bit Description

Hex

Dec

E2H

226

MSR_PKG_CST_CONFIG_CONTROL

Core

C-State Configuration Control (R/W)

Note: C-state values are processor specific C-state code

names, unrelated to MWAIT extension C-state

parameters or ACPI C-states.

See http://biosbits.org.

3:0

Package C-State Limit (R/W)

Specifies the lowest processor-specific C-state code

name (consuming the least power) for the package. The

default is set as factory-configured package C-state

limit.

The following C-state code name encodings are

supported:

0000b: C0/C1 (no package C-state support)

0001b: C2

0010b: C3

0011b: C6

0100b: C7

0101b: C7s

0110b: C8

0111b: C9

1000b: C10

9:4

Reserved

I/O MWAIT Redirection Enable (R/W)

14:11

Reserved

CFG Lock (R/WO)

2-244 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-31. Additional Residency MSRs Supported by 4th Generation Intel® Core™ Processors with a

CPUID Signature DisplayFamily_DisplayModel Value of 06_45H

Address

Scope

Bit Description

Hex

Dec

24:16

Reserved

C3 State Auto Demotion Enable (R/W)

C1 State Auto Demotion Enable (R/W)

Enable C3 Undemotion (R/W)

Enable C1 Undemotion (R/W)

63:29

Reserved

630H

1584

MSR_PKG_C8_RESIDENCY

Package

Note: C-state values are processor specific C-state code

names, unrelated to MWAIT extension C-state

parameters or ACPI C-States.

59:0

Package C8 Residency Counter (R/O)

Value since last reset that this package is in processor-

specific C8 states. Count at the same frequency as the

TSC.

63:60

Reserved

631H

1585

MSR_PKG_C9_RESIDENCY

Package

Note: C-state values are processor specific C-state code

names, unrelated to MWAIT extension C-state

parameters or ACPI C-States.

59:0

Package C9 Residency Counter (R/O)

Value since last reset that this package is in processor-

specific C9 states. Count at the same frequency as the

TSC.

63:60

Reserved

632H

1586

MSR_PKG_C10_RESIDENCY

Package

Note: C-state values are processor specific C-state code

names, unrelated to MWAIT extension C-state

parameters or ACPI C-States.

59:0

Package C10 Residency Counter (R/O)

Value since last reset that this package is in processor-

specific C10 states. Count at the same frequency as the

TSC.

63:60

Reserved

See Table 2-20, Table 2-21, Table 2-22, Table 2-29, and Table 2-30 for other MSR definitions applicable to processors with a CPUID

Signature DisplayFamily_DisplayModel value of 06_45H.

2.14

MSRS IN THE INTEL® XEON® PROCESSOR E5 V3 AND E7 V3 PRODUCT

FAMILY

The Intel^® Xeon^® processor E5 v3 family and the Intel^® Xeon^® processor E7 v3 family are based on Haswell-E

microarchitecture (CPUID Signature DisplayFamily_DisplayModel value of 06_3F). These processors support the

MSR interfaces listed in Table 2-20, Table 2-29, and Table 2-32.

Vol. 4

2-245

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family

Address

Scope

Bit Description

Hex

Dec

35H

MSR_CORE_THREAD_COUNT

Package

Configured State of Enabled Processor Core Count and

Logical Processor Count (R/O)

• After a Power-On RESET, enumerates factory

configuration of the number of processor cores and

logical processors in the physical package.

• Following the sequence of (i) BIOS modified a

Configuration Mask which selects a subset of

processor cores to be active post RESET and (ii) a

RESET event after the modification, enumerates the

current configuration of enabled processor core

count and logical processor count in the physical

package.

15:0

THREAD_COUNT (R/O)

The number of logical processors that are currently

enabled (by either factory configuration or BIOS

configuration) in the physical package.

31:16

Core_COUNT (R/O)

The number of processor cores that are currently

enabled (by either factory configuration or BIOS

configuration) in the physical package.

63:32

Reserved

53H

MSR_THREAD_ID_INFO

Thread

A Hardware Assigned ID for the Logical Processor (R/O)

7:0

Logical_Processor_ID (R/O)

An implementation-specific numerical value physically

assigned to each logical processor. This ID is not related

to Initial APIC ID or x2APIC ID, it is unique within a

physical package.

63:8

Reserved

E2H

226

MSR_PKG_CST_CONFIG_CONTROL

Core

C-State Configuration Control (R/W)

Note: C-state values are processor specific C-state code

names, unrelated to MWAIT extension C-state

parameters or ACPI C-states.

See http://biosbits.org.

2:0

Package C-State Limit (R/W)

Specifies the lowest processor-specific C-state code

name (consuming the least power) for the package. The

default is set as factory-configured package C-state

limit.

The following C-state code name encodings are

supported:

000b: C0/C1 (no package C-state support)

001b: C2

010b: C6 (non-retention)

011b: C6 (retention)

111b: No Package C state limits. All C states supported

by the processor are available.

2-246 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family

Address

Scope

Bit Description

Hex

Dec

9:3

Reserved

I/O MWAIT Redirection Enable (R/W)

14:11

Reserved

CFG Lock (R/WO)

24:16

Reserved

C3 State Auto Demotion Enable (R/W)

C1 State Auto Demotion Enable (R/W)

Enable C3 Undemotion (R/W)

Enable C1 Undemotion (R/W)

Package C State Demotion Enable (R/W)

Package C State UnDemotion Enable (R/W)

63:31

Reserved

179H

377

IA32_MCG_CAP

Thread

Global Machine Check Capability (R/O)

7:0

Count

MCG_CTL_P

MCG_EXT_P

MCP_CMCI_P

MCG_TES_P

15:12

Reserved

23:16

MCG_EXT_CNT

MCG_SER_P

MCG_EM_P

MCG_ELOG_P

63:27

Reserved

17DH

381

MSR_SMM_MCA_CAP

Thread

Enhanced SMM Capabilities (SMM-RO)

Reports SMM capability Enhancement. Accessible only

while in SMM.

57:0

Reserved

SMM_Code_Access_Chk (SMM-RO)

If set to 1, indicates that the SMM code access

restriction is supported and a host-space interface

available to SMM handler.

Long_Flow_Indication (SMM-RO)

If set to 1, indicates that the SMM long flow indicator is

supported and a host-space interface available to SMM

handler.

63:60

Reserved

17FH

383

MSR_ERROR_CONTROL

Package

MC Bank Error Configuration (R/W)

Reserved

Vol. 4

2-247

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family

Address

Scope

Bit Description

Hex

Dec

MemError Log Enable (R/W)

When set, enables IMC status bank to log additional info

in bits 36:32.

63:2

Reserved

1ADH

429

MSR_TURBO_RATIO_LIMIT

Package

Maximum Ratio Limit of Turbo Mode

R/O if MSR_PLATFORM_INFO.[28] = 0.

R/W if MSR_PLATFORM_INFO.[28] = 1.

7:0

Package

Maximum Ratio Limit for 1C

Maximum turbo ratio limit of 1 core active.

15:8

Package

Maximum Ratio Limit for 2C

Maximum turbo ratio limit of 2 core active.