Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 129
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-7. MSRs Common to the Silvermont and Airmont Microarchitectures
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
22:9
Reserved
23
L2 Not Present (R/O)
0 = L2 Present.
1 = L2 Not Present.
63:24
Reserved
1A0H
416
IA32_MISC_ENABLE
Enable Misc. Processor Features (R/W)
Allows a variety of processor functions to be enabled
and disabled.
0
Core
Fast-Strings Enable
See Table 2-2.
2:1
Reserved
3
Module
Automatic Thermal Control Circuit Enable (R/W)
See Table 2-2. Default value is 0.
6:4
Reserved
7
Core
Performance Monitoring Available (R)
See Table 2-2.
10:8
Reserved
11
Core
Branch Trace Storage Unavailable (R/O)
See Table 2-2.
12
Core
Processor Event Based Sampling Unavailable (R/O)
See Table 2-2.
15:13
Reserved
16
Module
Enhanced Intel SpeedStep Technology Enable (R/W)
See Table 2-2.
18
Core
ENABLE MONITOR FSM (R/W)
See Table 2-2.
21:19
Reserved
22
Core
Limit CPUID Maxval (R/W)
See Table 2-2.
23
Module
xTPR Message Disable (R/W)
See Table 2-2.
33:24
Reserved
34
Core
XD Bit Disable (R/W)
See Table 2-3.
37:35
Reserved
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-7. MSRs Common to the Silvermont and Airmont Microarchitectures
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
38
Module
Turbo Mode Disable (R/W)
When set to 1 on processors that support Intel Turbo
Boost Technology, the turbo mode feature is disabled
and the IDA_Enable feature flag will be cleared
(CPUID.06H: EAX[1]=0).
When set to a 0 on processors that support IDA,
CPUID.06H: EAX[1] reports the processor’s support of
turbo mode is enabled.
Note: The power-on default value is used by BIOS to
detect hardware support of turbo mode. If the power-on
default value is 1, turbo mode is available in the
processor. If the power-on default value is 0, turbo mode
is not available.
63:39
Reserved
1C8H
456
MSR_LBR_SELECT
Core
Last Branch Record Filtering Select Register (R/W)
See Section 18.9.2, “Filtering of Last Branch Records.”
0
CPL_EQ_0
1
CPL_NEQ_0
2
JCC
3
NEAR_REL_CALL
4
NEAR_IND_CALL
5
NEAR_RET
6
NEAR_IND_JMP
7
NEAR_REL_JMP
8
FAR_BRANCH
63:9
Reserved
1C9H
457
MSR_LASTBRANCH_TOS
Core
Last Branch Record Stack TOS (R/W)
Contains an index (bits 0-2) that points to the MSR
containing the most recent branch record.
See MSR_LASTBRANCH_0_FROM_IP.
38EH
910
IA32_PERF_GLOBAL_STATUS
Core
See Table 2-2. See Section 20.6.2.2, “Global Counter
Control Facilities.”
390H
912
IA32_PERF_GLOBAL_OVF_CTRL
Core
See Table 2-2. See Section 20.6.2.2, “Global Counter
Control Facilities.”
3F1H
1009
IA32_PEBS_ENABLE
Core
See Table 2-2. See Section 20.6.2.4, “Processor Event
Based Sampling (PEBS).”
(MSR_PEBS_ENABLE)
0
Enable PEBS for precise event on IA32_PMC0 (R/W)
3FAH
1018
MSR_PKG_C6_RESIDENCY
Package
Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-7. MSRs Common to the Silvermont and Airmont Microarchitectures
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
63:0
Package C6 Residency Counter (R/O)
Value since last reset that this package is in processor-
specific C6 states. Counts at the TSC Frequency.
664H
1636
MSR_MC6_RESIDENCY_COUNTER
Module
Module C6 Residency Counter (R/0)
Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
63:0
Time that this module is in module-specific C6 states
since last reset. Counts at 1 Mhz frequency.
2.4.1
MSRs with Model-Specific Behavior in the Silvermont Microarchitecture
Table 2-8 lists MSRs that are specific to the Intel Atom® processor E3000 Series (CPUID Signature
DisplayFamily_DisplayModel value of 06_37H) and Intel Atom processors (CPUID Signature
DisplayFamily_DisplayModel value of 06_4AH, 06_5AH, or 06_5DH).
Table 2-8. Specific MSRs Supported by Intel Atom® Processors with a CPUID Signature DisplayFamily_DisplayModel
Value of 06_37H, 06_4AH, 06_5AH, or 06_5DH
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
CDH
205
MSR_FSB_FREQ
Module
Scaleable Bus Speed (R/O)
This field indicates the intended scalable bus clock speed
for processors based on Silvermont microarchitecture.
2:0
•
100B: 080.0 MHz
•
000B: 083.3 MHz
•
001B: 100.0 MHz
•
010B: 133.3 MHz
•
011B: 116.7 MHz
63:3
Reserved
606H
1542
MSR_RAPL_POWER_UNIT
Package
Unit Multipliers used in RAPL Interfaces (R/O)
See Section 15.10.1, “RAPL Interfaces.”
3:0
Power Units
Power related information (in milliWatts) is based on the
multiplier,
2^PU; where PU is an unsigned integer
represented by bits 3:0. Default value is 0101b,
indicating power unit is in 32 milliWatts increment.
7:4
Reserved
12:8
Energy Status Units
Energy related information (in microJoules) is based on
the multiplier, 2^ESU; where ESU is an unsigned integer
represented by bits 12:8. Default value is 00101b,
indicating energy unit is in 32 microJoules increment.
15:13
Reserved
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-8. Specific MSRs Supported by Intel Atom® Processors with a CPUID Signature DisplayFamily_DisplayModel
Value of 06_37H, 06_4AH, 06_5AH, or 06_5DH (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
19:16
Time Unit
The value is 0000b, indicating time unit is in one second.
63:20
Reserved
610H
1552
MSR_PKG_POWER_LIMIT
Package
PKG RAPL Power Limit Control (R/W)
14:0
Package Power Limit #1 (R/W)
See Section 15.10.3, “Package RAPL Domain,” and
MSR_RAPL_POWER_UNIT in Table 2-8.
15
Enable Power Limit #1 (R/W)
See Section 15.10.3, “Package RAPL Domain.”
16
Package Clamping Limitation #1 (R/W)
See Section 15.10.3, “Package RAPL Domain.”
23:17
Time Window for Power Limit #1 (R/W)
In unit of second. If 0 is specified in bits [23:17], defaults
to 1 second window.
63:24
Reserved
611H
1553
MSR_PKG_ENERGY_STATUS
Package
PKG Energy Status (R/O)
See Section 15.10.3, “Package RAPL Domain,” and
MSR_RAPL_POWER_UNIT in Table 2-8.
639H
1593
MSR_PP0_ENERGY_STATUS
Package
PP0 Energy Status (R/O)
See Section 15.10.4, “PP0/PP1 RAPL Domains,” and
MSR_RAPL_POWER_UNIT in Table 2-8.
Table 2-9 lists model-specific registers (MSRs) that are specific to the Intel Atom® processor E3000 Series (CPUID
Signature DisplayFamily_DisplayModel value of 06_37H).
Table 2-9. Specific MSRs Supported by the Intel Atom® Processor E3000 Series with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_37H
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
668H
1640
MSR_CC6_DEMOTION_POLICY_CONFIG
Package
Core C6 Demotion Policy Config MSR
63:0
Controls per-core C6 demotion policy. Writing a value of
0 disables core level HW demotion policy.
669H
1641
MSR_MC6_DEMOTION_POLICY_CONFIG
Package
Module C6 Demotion Policy Config MSR
63:0
Controls module (i.e., two cores sharing the second-level
cache) C6 demotion policy. Writing a value of 0 disables
module level HW demotion policy.
664H
1636
MSR_MC6_RESIDENCY_COUNTER
Module
Module C6 Residency Counter (R/0)
Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-9. Specific MSRs Supported by the Intel Atom® Processor E3000 Series (Contd.)with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_37H
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
63:0
Time that this module is in module-specific C6 states
since last reset. Counts at 1 Mhz frequency.
Table 2-10 lists model-specific registers (MSRs) that are specific to Intel Atom® processor C2000 Series (CPUID
Signature DisplayFamily_DisplayModel value of 06_4DH).
Table 2-10. Specific MSRs Supported by Intel Atom® Processor C2000 Series with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_4DH
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
1A4H
420
MSR_MISC_FEATURE_CONTROL
Miscellaneous Feature Control (R/W)
0
Core
L2 Hardware Prefetcher Disable (R/W)
If 1, disables the L2 hardware prefetcher, which
fetches additional lines of code or data into the L2
cache.
1
Reserved
2
Core
DCU Hardware Prefetcher Disable (R/W)
If 1, disables the L1 data cache prefetcher, which
fetches the next cache line into L1 data cache.
63:3
Reserved
1ADH
429
MSR_TURBO_RATIO_LIMIT
Package
Maximum Ratio Limit of Turbo Mode (R/W)
7:0
Package
Maximum Ratio Limit for 1C
Maximum turbo ratio limit of 1 core active.
15:8
Package
Maximum Ratio Limit for 2C
Maximum turbo ratio limit of 2 core active.
23:16
Package
Maximum Ratio Limit for 3C
Maximum turbo ratio limit of 3 core active.
31:24
Package
Maximum Ratio Limit for 4C
Maximum turbo ratio limit of 4 core active.
39:32
Package
Maximum Ratio Limit for 5C
Maximum turbo ratio limit of 5 core active.
47:40
Package
Maximum Ratio Limit for 6C
Maximum turbo ratio limit of 6 core active.
55:48
Package
Maximum Ratio Limit for 7C
Maximum turbo ratio limit of 7 core active.
63:56
Package
Maximum Ratio Limit for 8C
Maximum turbo ratio limit of 8 core active.
606H
1542
MSR_RAPL_POWER_UNIT
Package
Unit Multipliers used in RAPL Interfaces (R/O)
See Section 15.10.1, “RAPL Interfaces.”
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-10. Specific MSRs Supported by Intel Atom® Processor C2000 Series (Contd.)with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_4DH
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
3:0
Power Units
Power related information (in milliWatts) is based on
the multiplier, 2^PU; where PU is an unsigned integer
represented by bits 3:0. Default value is 0101b,
indicating power unit is in 32 milliWatts increment.
7:4
Reserved
12:8
Energy Status Units.
Energy related information (in microJoules) is based on
the multiplier, 2^ESU; where ESU is an unsigned
integer represented by bits 12:8. Default value is
00101b, indicating energy unit is in 32 microJoules
increment.
15:13
Reserved
19:16
Time Unit
The value is 0000b, indicating time unit is in one
second.
63:20
Reserved
610H
1552
MSR_PKG_POWER_LIMIT
Package
PKG RAPL Power Limit Control (R/W)
See Section 15.10.3, “Package RAPL Domain.”
66EH
1646
MSR_PKG_POWER_INFO
Package
PKG RAPL Parameter (R/0)
14:0
Thermal Spec Power (R/0)
The unsigned integer value is the equivalent of the
thermal specification power of the package domain.
The unit of this field is specified by the “Power Units”
field of MSR_RAPL_POWER_UNIT.
63:15
Reserved
2.4.2
MSRs in Intel Atom® Processors Based on Airmont Microarchitecture
Intel Atom processor X7-Z8000 and X5-Z8000 series are based on the Airmont microarchitecture. These proces-
sors support MSRs listed in Table 2-6, Table 2-7, Table 2-8, and Table 2-11. These processors have a CPUID
Signature DisplayFamily_DisplayModel value of 06_4CH; see Table 2-1.
Table 2-11. MSRs in Intel Atom® Processors Based on Airmont Microarchitecture
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
CDH
205
MSR_FSB_FREQ
Module
Scaleable Bus Speed (R/O)
This field indicates the intended scalable bus clock
speed for processors based on Airmont
microarchitecture.
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-11. MSRs in Intel Atom® Processors Based on Airmont Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
3:0
•
0000B: 083.3 MHz
•
0001B: 100.0 MHz
•
0010B: 133.3 MHz
•
0011B: 116.7 MHz
•
0100B: 080.0 MHz
•
0101B: 093.3 MHz
•
0110B: 090.0 MHz
•
0111B: 088.9 MHz
•
1000B: 087.5 MHz
63:5
Reserved
E2H
226
MSR_PKG_CST_CONFIG_CONTROL
Module
C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state
code names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
2:0
Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code
name (consuming the least power) for the package.
The default is set as factory-configured package C-
state limit.
The following C-state code name encodings are
supported:
000b: No limit
001b: C1
010b: C2
110b: C6
111b: C7
9:3
Reserved
10
I/O MWAIT Redirection Enable (R/W)
When set, will map IO_read instructions sent to IO
register specified by MSR_PMG_IO_CAPTURE_BASE to
MWAIT instructions.
14:11
Reserved
15
CFG Lock (R/WO)
When set, locks bits 15:0 of this register until next
reset.
63:16
Reserved
E4H
228
MSR_PMG_IO_CAPTURE_BASE
Module
Power Management IO Redirection in C-state (R/W)
15:0
LVL_2 Base Address (R/W)
Specifies the base address visible to software for IO
redirection. If IO MWAIT Redirection is enabled, reads to
this address will be consumed by the power
management logic and decoded to MWAIT instructions.
When IO port address redirection is enabled, this is the
IO port address reported to the OS/software.
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-11. MSRs in Intel Atom® Processors Based on Airmont Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
18:16
C-state Range (R/W)
Specifies the encoding value of the maximum C-State
code name to be included when IO read to MWAIT
redirection is enabled by
MSR_PKG_CST_CONFIG_CONTROL[bit10]:
000b - C3 is the max C-State to include.
001b - Deep Power Down Technology is the max C-
State.
010b - C7 is the max C-State to include.
63:19
Reserved
638H
1592
MSR_PP0_POWER_LIMIT
Package
PP0 RAPL Power Limit Control (R/W)
14:0
PP0 Power Limit #1 (R/W)
See Section 15.10.4, “PP0/PP1 RAPL Domains,” and
MSR_RAPL_POWER_UNIT in Table 2-8.
15
Enable Power Limit #1 (R/W)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
16
Reserved
23:17
Time Window for Power Limit #1 (R/W)
Specifies the time duration over which the average
power must remain below PP0_POWER_LIMIT
#1(14:0). Supported Encodings:
0x0: 1 second time duration.
0x1: 5 second time duration (Default).
0x2: 10 second time duration.
0x3: 15 second time duration.
0x4: 20 second time duration.
0x5: 25 second time duration.
0x6: 30 second time duration.
0x7: 35 second time duration.
0x8: 40 second time duration.
0x9: 45 second time duration.
0xA: 50 second time duration.
0xB-0x7F - reserved.
63:24
Reserved
2.5
MSRS IN INTEL ATOM® PROCESSORS BASED ON GOLDMONT
MICROARCHITECTURE
Intel Atom processors based on the Goldmont microarchitecture support MSRs listed in Table 2-6 and Table 2-12.
These processors have a CPUID Signature DisplayFamily_DisplayModel value of 06_5CH; see Table 2-1.
In the Goldmont microarchitecture, the scope column indicates the following: “Core” means each processor core
has a separate MSR, or a bit field not shared with another processor core. “Module” means the MSR or the bit field
is shared by a subset of the processor cores in the physical package. The number of processor cores in this subset
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MODEL-SPECIFIC REGISTERS (MSRS)
is model specific and may differ between different processors. For all processors based on Goldmont microarchitec-
ture, the L2 cache is also shared between cores in a module and thus CPUID leaf 04H enumeration can be used to
figure out which processors are in the same module. “Package” means all processor cores in the physical package
share the same MSR or bit interface.
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
17H
23
MSR_PLATFORM_ID
Module
Model Specific Platform ID (R)
49:0
Reserved
52:50
See Table 2-2.
63:33
Reserved
3AH
58
IA32_FEATURE_CONTROL
Core
Control Features in Intel 64 Processor (R/W)
See Table 2-2.
0
Lock (R/WL)
1
Enable VMX inside SMX operation (R/WL)
2
Enable VMX outside SMX operation (R/WL)
14:8
SENTER local functions enables (R/WL)
15
SENTER global functions enable (R/WL)
18
SGX global functions enable (R/WL)
63:19
Reserved
3BH
59
IA32_TSC_ADJUST
Core
Per-Core TSC ADJUST (R/W)
See Table 2-2.
C3H
195
IA32_PMC2
Core
Performance Counter Register
See Table 2-2.
C4H
196
IA32_PMC3
Core
Performance Counter Register
See Table 2-2.
CEH
206
MSR_PLATFORM_INFO
Package
Platform Information
Contains power management and other model specific
features enumeration. See http://biosbits.org.
7:0
Reserved
15:8
Package
Maximum Non-Turbo Ratio (R/O)
This is the ratio of the maximum frequency that does
not require turbo. Frequency = ratio * 100 MHz.
27:16
Reserved
28
Package
Programmable Ratio Limit for Turbo Mode (R/O)
When set to 1, indicates that Programmable Ratio
Limit for Turbo mode is enabled. When set to 0,
indicates Programmable Ratio Limit for Turbo mode is
disabled.
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
29
Package
Programmable TDP Limit for Turbo Mode (R/O)
When set to 1, indicates that TDP Limit for Turbo
mode is programmable. When set to 0, indicates TDP
Limit for Turbo mode is not programmable.
30
Package
Programmable TJ OFFSET (R/O)
When set to 1, indicates that
MSR_TEMPERATURE_TARGET.[27:24] is valid and
writable to specify a temperature offset.
39:31
Reserved
47:40
Package
Maximum Efficiency Ratio (R/O)
This is the minimum ratio (maximum efficiency) that
the processor can operate, in units of 100MHz.
63:48
Reserved
E2H
226
MSR_PKG_CST_CONFIG_CONTROL
Core
C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state
code names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
3:0
Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code
name (consuming the least power) for the package.
The default is set as factory-configured package C-
state limit.
The following C-state code name encodings are
supported:
0000b: No limit
0001b: C1
0010b: C3
0011b: C6
0100b: C7
0101b: C7S
0110b: C8
0111b: C9
1000b: C10
9:3
Reserved
10
I/O MWAIT Redirection Enable (R/W)
When set, will map IO_read instructions sent to IO
register specified by MSR_PMG_IO_CAPTURE_BASE to
MWAIT instructions.
14:11
Reserved
15
CFG Lock (R/WO)
When set, locks bits 15:0 of this register until next
reset.
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
63:16
Reserved
17DH
381
MSR_SMM_MCA_CAP
Core
Enhanced SMM Capabilities (SMM-RO)
Reports SMM capability enhancement. Accessible only
while in SMM.
57:0
Reserved
58
SMM_Code_Access_Chk (SMM-RO)
If set to 1 indicates that the SMM code access
restriction is supported and the
MSR_SMM_FEATURE_CONTROL is supported.
59
Long_Flow_Indication (SMM-RO)
If set to 1 indicates that the SMM long flow indicator is
supported and the MSR_SMM_DELAYED is supported.
63:60
Reserved
188H
392
IA32_PERFEVTSEL2
Core
See Table 2-2.
189H
393
IA32_PERFEVTSEL3
Core
See Table 2-2.
1A0H
416
IA32_MISC_ENABLE
Enable Misc. Processor Features (R/W)
Allows a variety of processor functions to be enabled
and disabled.
0
Core
Fast-Strings Enable
See Table 2-2.
2:1
Reserved
3
Package
Automatic Thermal Control Circuit Enable (R/W)
See Table 2-2. Default value is 1.
6:4
Reserved
7
Core
Performance Monitoring Available (R)
See Table 2-2.
10:8
Reserved
11
Core
Branch Trace Storage Unavailable (R/O)
See Table 2-2.
12
Core
Processor Event Based Sampling Unavailable (R/O)
See Table 2-2.
15:13
Reserved
16
Package
Enhanced Intel SpeedStep Technology Enable (R/W)
See Table 2-2.
18
Core
ENABLE MONITOR FSM (R/W)
See Table 2-2.
21:19
Reserved
22
Core
Limit CPUID Maxval (R/W)
See Table 2-2.
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
23
Package
xTPR Message Disable (R/W)
See Table 2-2.
33:24
Reserved
34
Core
XD Bit Disable (R/W)
See Table 2-3.
37:35
Reserved
38
Package
Turbo Mode Disable (R/W)
When set to 1 on processors that support Intel Turbo
Boost Technology, the turbo mode feature is disabled
and the IDA_Enable feature flag will be clear
(CPUID.06H: EAX[1]=0).
When set to a 0 on processors that support IDA,
CPUID.06H: EAX[1] reports the processor’s support of
turbo mode is enabled.
Note: The power-on default value is used by BIOS to
detect hardware support of turbo mode. If the power-
on default value is 1, turbo mode is available in the
processor. If the power-on default value is 0, turbo
mode is not available.
63:39
Reserved
1A4H
420
MSR_MISC_FEATURE_CONTROL
Miscellaneous Feature Control (R/W)
0
Core
L2 Hardware Prefetcher Disable (R/W)
If 1, disables the L2 hardware prefetcher, which
fetches additional lines of code or data into the L2
cache.
1
Reserved
2
Core
DCU Hardware Prefetcher Disable (R/W)
If 1, disables the L1 data cache prefetcher, which
fetches the next cache line into L1 data cache.
63:3
Reserved
1AAH
426
MSR_MISC_PWR_MGMT
Package
Miscellaneous Power Management Control
Various model specific features enumeration. See
0
EIST Hardware Coordination Disable (R/W)
When 0, enables hardware coordination of Enhanced
Intel Speedstep Technology request from processor
cores. When 1, disables hardware coordination of
Enhanced Intel Speedstep Technology requests.
21:1
Reserved
22
Thermal Interrupt Coordination Enable (R/W)
If set, then thermal interrupt on one core is routed to
all cores.
63:23
Reserved
2-116 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
1ADH
429
MSR_TURBO_RATIO_LIMIT
Package
Maximum Ratio Limit of Turbo Mode by Core Groups
(R/W)
Specifies Maximum Ratio Limit for each Core Group.
Max ratio for groups with more cores must decrease
monotonically.
For groups with less than 4 cores, the max ratio must
be 32 or less. For groups with 4-5 cores, the max ratio
must be 22 or less. For groups with more than 5 cores,
the max ratio must be 16 or less.
7:0
Package
Maximum Ratio Limit for Active Cores in Group 0
Maximum turbo ratio limit when the number of active
cores is less than or equal to the Group 0 threshold.
15:8
Package
Maximum Ratio Limit for Active Cores in Group 1
Maximum turbo ratio limit when the number of active
cores is less than or equal to the Group 1 threshold,
and greater than the Group 0 threshold.
23:16
Package
Maximum Ratio Limit for Active Cores in Group 2
Maximum turbo ratio limit when the number of active
cores is less than or equal to the Group 2 threshold,
and greater than the Group 1 threshold.
31:24
Package
Maximum Ratio Limit for Active Cores in Group 3
Maximum turbo ratio limit when the number of active
cores is less than or equal to the Group 3 threshold,
and greater than the Group 2 threshold.
39:32
Package
Maximum Ratio Limit for Active Cores in Group 4
Maximum turbo ratio limit when the number of active
cores is less than or equal to the Group 4 threshold,
and greater than the Group 3 threshold.
47:40
Package
Maximum Ratio Limit for Active Cores in Group 5
Maximum turbo ratio limit when the number of active
cores is less than or equal to the Group 5 threshold,
and greater than the Group 4 threshold.
55:48
Package
Maximum Ratio Limit for Active Cores in Group 6
Maximum turbo ratio limit when the number of active
cores is less than or equal to the Group 6 threshold,
and greater than the Group 5 threshold.
63:56
Package
Maximum Ratio Limit for Active Cores in Group 7
Maximum turbo ratio limit when the number of active
cores is less than or equal to the Group 7 threshold,
and greater than the Group 6 threshold.
1AEH
430
MSR_TURBO_GROUP_CORECNT
Package
Group Size of Active Cores for Turbo Mode Operation
(R/W)
Writes of 0 threshold is ignored.
Vol. 4
2-117
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
7:0
Package
Group 0 Core Count Threshold
Maximum number of active cores to operate under the
Group 0 Max Turbo Ratio limit.
15:8
Package
Group 1 Core Count Threshold
Maximum number of active cores to operate under the
Group 1 Max Turbo Ratio limit. Must be greater than
the Group 0 Core Count.
23:16
Package
Group 2 Core Count Threshold
Maximum number of active cores to operate under the
Group 2 Max Turbo Ratio limit. Must be greater than
the Group 1 Core Count.
31:24
Package
Group 3 Core Count Threshold
Maximum number of active cores to operate under the
Group 3 Max Turbo Ratio limit. Must be greater than
the Group 2 Core Count.
39:32
Package
Group 4 Core Count Threshold
Maximum number of active cores to operate under the
Group 4 Max Turbo Ratio limit. Must be greater than
the Group 3 Core Count.
47:40
Package
Group 5 Core Count Threshold
Maximum number of active cores to operate under the
Group 5 Max Turbo Ratio limit. Must be greater than
the Group 4 Core Count.
55:48
Package
Group 6 Core Count Threshold
Maximum number of active cores to operate under the
Group 6 Max Turbo Ratio limit. Must be greater than
the Group 5 Core Count.
63:56
Package
Group 7 Core Count Threshold
Maximum number of active cores to operate under the
Group 7 Max Turbo Ratio limit. Must be greater than
the Group 6 Core Count, and not less than the total
number of processor cores in the package. E.g., specify
255.
1C8H
456
MSR_LBR_SELECT
Core
Last Branch Record Filtering Select Register (R/W)
See Section 18.9.2, “Filtering of Last Branch Records.”
0
CPL_EQ_0
1
CPL_NEQ_0
2
JCC
3
NEAR_REL_CALL
4
NEAR_IND_CALL
5
NEAR_RET
6
NEAR_IND_JMP
7
NEAR_REL_JMP
2-118 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
8
FAR_BRANCH
9
EN_CALL_STACK
63:10
Reserved
1C9H
457
MSR_LASTBRANCH_TOS
Core
Last Branch Record Stack TOS (R/W)
Contains an index (bits 0-4) that points to the MSR
containing the most recent branch record.
See MSR_LASTBRANCH_0_FROM_IP.
1FCH
508
MSR_POWER_CTL
Core
Power Control Register. See http://biosbits.org.
0
Reserved
1
Package
C1E Enable (R/W)
When set to ‘1’, will enable the CPU to switch to the
Minimum Enhanced Intel SpeedStep Technology
operating point when all execution cores enter MWAIT
(C1).
63:2
Reserved
210H
528
IA32_MTRR_PHYSBASE8
Core
See Table 2-2.
211H
529
IA32_MTRR_PHYSMASK8
Core
See Table 2-2.
212H
530
IA32_MTRR_PHYSBASE9
Core
See Table 2-2.
213H
531
IA32_MTRR_PHYSMASK9
Core
See Table 2-2.
280H
640
IA32_MC0_CTL2
Module
See Table 2-2.
281H
641
IA32_MC1_CTL2
Module
See Table 2-2.
282H
642
IA32_MC2_CTL2
Core
See Table 2-2.
283H
643
IA32_MC3_CTL2
Module
See Table 2-2.
284H
644
IA32_MC4_CTL2
Package
See Table 2-2.
285H
645
IA32_MC5_CTL2
Package
See Table 2-2.
286H
646
IA32_MC6_CTL2
Package
See Table 2-2.
300H
768
MSR_SGXOWNEREPOCH0
Package
Lower 64 Bit CR_SGXOWNEREPOCH (W)
Writes do not update CR_SGXOWNEREPOCH if
CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any
thread in the package.
63:0
Lower 64 bits of an 128-bit external entropy value for
key derivation of an enclave.
301H
769
MSR_SGXOWNEREPOCH1
Package
Upper 64 Bit CR_SGXOWNEREPOCH (W)
Writes do not update CR_SGXOWNEREPOCH if
CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any
thread in the package.
63:0
Upper 64 bits of an 128-bit external entropy value for
key derivation of an enclave.
38EH
910
IA32_PERF_GLOBAL_STATUS
Core
See Table 2-2. See Section 20.2.4, “Architectural
Performance Monitoring Version 4.”
0
Ovf_PMC0
Vol. 4
2-119
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
1
Ovf_PMC1
2
Ovf_PMC2
3
Ovf_PMC3
31:4
Reserved
32
Ovf_FixedCtr0
33
Ovf_FixedCtr1
34
Ovf_FixedCtr2
54:35
Reserved
55
Trace_ToPA_PMI
57:56
Reserved
58
LBR_Frz.
59
CTR_Frz.
60
ASCI
61
Ovf_Uncore
62
Ovf_BufDSSAVE
63
CondChgd
390H
912
IA32_PERF_GLOBAL_STATUS_RESET
Core
See Table 2-2. See Section 20.2.4, “Architectural
Performance Monitoring Version 4.”
0
Set 1 to clear Ovf_PMC0.
1
Set 1 to clear Ovf_PMC1.
2
Set 1 to clear Ovf_PMC2.
3
Set 1 to clear Ovf_PMC3.
31:4
Reserved
32
Set 1 to clear Ovf_FixedCtr0.
33
Set 1 to clear Ovf_FixedCtr1.
34
Set 1 to clear Ovf_FixedCtr2.
54:35
Reserved
55
Set 1 to clear Trace_ToPA_PMI.
57:56
Reserved
58
Set 1 to clear LBR_Frz.
59
Set 1 to clear CTR_Frz.
60
Set 1 to clear ASCI.
61
Set 1 to clear Ovf_Uncore.
62
Set 1 to clear Ovf_BufDSSAVE.
63
Set 1 to clear CondChgd.
391H
913
IA32_PERF_GLOBAL_STATUS_SET
Core
See Table 2-2. See Section 20.2.4, “Architectural
Performance Monitoring Version 4.”
2-120 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
0
Set 1 to cause Ovf_PMC0 = 1.
1
Set 1 to cause Ovf_PMC1 = 1.
2
Set 1 to cause Ovf_PMC2 = 1.
3
Set 1 to cause Ovf_PMC3 = 1.
31:4
Reserved
32
Set 1 to cause Ovf_FixedCtr0 = 1.
33
Set 1 to cause Ovf_FixedCtr1 = 1.
34
Set 1 to cause Ovf_FixedCtr2 = 1.
54:35
Reserved
55
Set 1 to cause Trace_ToPA_PMI = 1.
57:56
Reserved
58
Set 1 to cause LBR_Frz = 1.
59
Set 1 to cause CTR_Frz = 1.
60
Set 1 to cause ASCI = 1.
61
Set 1 to cause Ovf_Uncore.
62
Set 1 to cause Ovf_BufDSSAVE.
63
Reserved
392H
914
IA32_PERF_GLOBAL_INUSE
Core
See Table 2-2.
3F1H
1009
IA32_PEBS_ENABLE
Core
See Table 2-2. See Section 20.6.2.4, “Processor Event
Based Sampling (PEBS).”
(MSR_PEBS_ENABLE)
0
Enable PEBS trigger and recording for the
programmed event (precise or otherwise) on
IA32_PMC0. (R/W)
3F8H
1016
MSR_PKG_C3_RESIDENCY
Package
Note: C-state values are processor specific C-state
code names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
63:0
Package C3 Residency Counter (R/O)
Value since last reset that this package is in
processor-specific C3 states. Count at the same
frequency as the TSC.
3F9H
1017
MSR_PKG_C6_RESIDENCY
Package
Note: C-state values are processor specific C-state
code names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
63:0
Package C6 Residency Counter (R/O)
Value since last reset that this package is in
processor-specific C6 states. Count at the same
frequency as the TSC.
3FCH
1020
MSR_CORE_C3_RESIDENCY
Core
Note: C-state values are processor specific C-state
code names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
Vol. 4
2-121
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
63:0
CORE C3 Residency Counter (R/O)
Value since last reset that this core is in processor-
specific C3 states. Count at the same frequency as the
TSC.
406H
1030
IA32_MC1_ADDR
Module
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC2_ADDR register is either not
implemented or contains no address if the ADDRV flag
in the IA32_MC2_STATUS register is clear.
When not implemented in the processor, all reads and
writes to this MSR will cause a general-protection
exception.
418H
1048
IA32_MC6_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
419H
1049
IA32_MC6_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
41AH
1050
IA32_MC6_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
4C3H
1219
IA32_A_PMC2
Core
See Table 2-2.
4C4H
1220
IA32_A_PMC3
Core
See Table 2-2.
4E0H
1248
MSR_SMM_FEATURE_CONTROL
Package
Enhanced SMM Feature Control (SMM-RW)
Reports SMM capability Enhancement. Accessible only
while in SMM.
0
Lock (SMM-RWO)
When set to ‘1’ locks this register from further
changes.
1
Reserved
2
SMM_Code_Chk_En (SMM-RW)
This control bit is available only if
MSR_SMM_MCA_CAP[58] == 1. When set to ‘0’
(default) none of the logical processors are prevented
from executing SMM code outside the ranges defined
by the SMRR.
When set to ‘1’ any logical processor in the package
that attempts to execute SMM code not within the
ranges defined by the SMRR will assert an
unrecoverable MCE.
63:3
Reserved
4E2H
1250
MSR_SMM_DELAYED
Package
SMM Delayed (SMM-RO)
Reports the interruptible state of all logical processors
in the package. Available only while in SMM and
MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.
2-122 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
N-1:0
LOG_PROC_STATE (SMM-RO)
Each bit represents a processor core of its state in a
long flow of internal operation which delays servicing
an interrupt. The corresponding bit will be set at the
start of long events such as: Microcode Update Load,
C6, WBINVD, Ratio Change, Throttle.
The bit is automatically cleared at the end of each long
event. The reset value of this field is 0.
Only bit positions below N = CPUID.(EAX=0BH,
ECX=PKG_LVL):EBX[15:0] can be updated.
63:N
Reserved
4E3H
1251
MSR_SMM_BLOCKED
Package
SMM Blocked (SMM-RO)
Reports the blocked state of all logical processors in
the package. Available only while in SMM.
N-1:0
LOG_PROC_STATE (SMM-RO)
Each bit represents a processor core of its blocked
state to service an SMI. The corresponding bit will be
set if the logical processor is in one of the following
states: Wait For SIPI or SENTER Sleep.
The reset value of this field is 0FFFH.
Only bit positions below N = CPUID.(EAX=0BH,
ECX=PKG_LVL):EBX[15:0] can be updated.
63:N
Reserved
500H
1280
IA32_SGX_SVN_STATUS
Core
Status and SVN Threshold of SGX Support for ACM
(R/O)
0
Lock
See Section 39.11.3, “Interactions with Authenticated
Code Modules (ACMs).”
15:1
Reserved
23:16
SGX_SVN_SINIT
See Section 39.11.3, “Interactions with Authenticated
Code Modules (ACMs).”
63:24
Reserved
560H
1376
IA32_RTIT_OUTPUT_BASE
Core
Trace Output Base Register (R/W)
See Table 2-2.
561H
1377
IA32_RTIT_OUTPUT_MASK_PTRS
Core
Trace Output Mask Pointers Register (R/W)
See Table 2-2.
570H
1392
IA32_RTIT_CTL
Core
Trace Control Register (R/W)
0
TraceEn
1
CYCEn
2
OS
3
User
6:4
Reserved, must be zero.
Vol. 4
2-123
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
7
CR3Filter
8
ToPA
Writing 0 will #GP if also setting TraceEn.
9
MTCEn
10
TSCEn
11
DisRETC
12
Reserved, must be zero.
13
BranchEn
17:14
MTCFreq
18
Reserved, must be zero.
22:19
CycThresh
23
Reserved, must be zero.
27:24
PSBFreq
31:28
Reserved, must be zero.
35:32
ADDR0_CFG
39:36
ADDR1_CFG
63:40
Reserved, must be zero.
571H
1393
IA32_RTIT_STATUS
Core
Tracing Status Register (R/W)
0
FilterEn
Writes ignored.
1
ContexEn
Writes ignored.
2
TriggerEn
Writes ignored.
3
Reserved
4
Error (R/W)
5
Stopped
31:6
Reserved, must be zero.
48:32
PacketByteCnt
63:49
Reserved, must be zero.
572H
1394
IA32_RTIT_CR3_MATCH
Core
Trace Filter CR3 Match Register (R/W)
4:0
Reserved
63:5
CR3[63:5] value to match.
580H
1408
IA32_RTIT_ADDR0_A
Core
Region 0 Start Address (R/W)
63:0
See Table 2-2.
581H
1409
IA32_RTIT_ADDR0_B
Core
Region 0 End Address (R/W)
63:0
See Table 2-2.
2-124 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
582H
1410
IA32_RTIT_ADDR1_A
Core
Region 1 Start Address (R/W)
63:0
See Table 2-2.
583H
1411
IA32_RTIT_ADDR1_B
Core
Region 1 End Address (R/W)
63:0
See Table 2-2.
606H
1542
MSR_RAPL_POWER_UNIT
Package
Unit Multipliers used in RAPL Interfaces (R/O)
See Section 15.10.1, “RAPL Interfaces.”
3:0
Power Units
Power related information (in Watts) is in unit of
1W/2^PU; where PU is an unsigned integer
represented by bits 3:0. Default value is 1000b,
indicating power unit is in 3.9 milliWatts increment.
7:4
Reserved
12:8
Energy Status Units
Energy related information (in Joules) is in unit of
1Joule/ (2^ESU); where ESU is an unsigned integer
represented by bits 12:8. Default value is 01110b,
indicating energy unit is in 61 microJoules.
15:13
Reserved
19:16
Time Unit
Time related information (in seconds) is in unit of
1S/2^TU; where TU is an unsigned integer
represented by bits 19:16. Default value is 1010b,
indicating power unit is in 0.977 millisecond.
63:20
Reserved
60AH
1546
MSR_PKGC3_IRTL
Package
Package C3 Interrupt Response Limit (R/W)
Note: C-state values are processor specific C-state
code names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
9:0
Interrupt Response Time Limit (R/W)
Specifies the limit that should be used to decide if the
package should be put into a package C3 state.
12:10
Time Unit (R/W)
Specifies the encoding value of time unit of the
interrupt response time limit. See Table 2-20 for
supported time unit encodings.
14:13
Reserved
15
Valid (R/W)
Indicates whether the values in bits 12:0 are valid and
can be used by the processor for package C-sate
management.
63:16
Reserved
Vol. 4
2-125
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
60BH
1547
MSR_PKGC_IRTL1
Package
Package C6/C7S Interrupt Response Limit 1 (R/W)
This MSR defines the interrupt response time limit
used by the processor to manage a transition to a
package C6 or C7S state.
Note: C-state values are processor specific C-state
code names, unrelated to MWAIT extension C-state
parameters or ACPI C-states.
9:0
Interrupt Response Time Limit (R/W)
Specifies the limit that should be used to decide if the
package should be put into a package C6 or C7S state.
12:10
Time Unit (R/W)
Specifies the encoding value of time unit of the
interrupt response time limit. See Table 2-20 for
supported time unit encodings.
14:13
Reserved
15
Valid (R/W)
Indicates whether the values in bits 12:0 are valid and
can be used by the processor for package C-sate
management.
63:16
Reserved
60CH
1548
MSR_PKGC_IRTL2
Package
Package C7 Interrupt Response Limit 2 (R/W)
This MSR defines the interrupt response time limit
used by the processor to manage a transition to a
package C7 state.
Note: C-state values are processor specific C-state
code names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
9:0
Interrupt Response Time Limit (R/W)
Specifies the limit that should be used to decide if the
package should be put into a package C7 state.
12:10
Time Unit (R/W)
Specifies the encoding value of time unit of the
interrupt response time limit. See Table 2-20 for
supported time unit encodings.
14:13
Reserved
15
Valid (R/W)
Indicates whether the values in bits 12:0 are valid and
can be used by the processor for package C-sate
management.
63:16
Reserved
60DH
1549
MSR_PKG_C2_RESIDENCY
Package
Note: C-state values are processor specific C-state
code names, unrelated to MWAIT extension C-state
parameters or ACPI C-states.
2-126 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
63:0
Package C2 Residency Counter (R/O)
Value since last reset that this package is in
processor-specific C2 states. Count at the same
frequency as the TSC.
610H
1552
MSR_PKG_POWER_LIMIT
Package
PKG RAPL Power Limit Control (R/W)
See Section 15.10.3, “Package RAPL Domain.”
611H
1553
MSR_PKG_ENERGY_STATUS
Package
PKG Energy Status (R/O)
See Section 15.10.3, “Package RAPL Domain.”
613H
1555
MSR_PKG_PERF_STATUS
Package
PKG Perf Status (R/O)
See Section 15.10.3, “Package RAPL Domain.”
614H
1556
MSR_PKG_POWER_INFO
Package
PKG RAPL Parameters (R/W)
14:0
Thermal Spec Power (R/W)
See Section 15.10.3, “Package RAPL Domain.”
15
Reserved
30:16
Minimum Power (R/W)
See Section 15.10.3, “Package RAPL Domain.”
31
Reserved
46:32
Maximum Power (R/W)
See Section 15.10.3, “Package RAPL Domain.”
47
Reserved
54:48
Maximum Time Window (R/W)
Specified by 2^Y * (1.0 + Z/4.0) * Time_Unit, where
“Y” is the unsigned integer value represented by bits
52:48, “Z” is an unsigned integer represented by bits
54:53. “Time_Unit” is specified by the “Time Units”
field of MSR_RAPL_POWER_UNIT.
63:55
Reserved
618H
1560
MSR_DRAM_POWER_LIMIT
Package
DRAM RAPL Power Limit Control (R/W)
See Section 15.10.5, “DRAM RAPL Domain.”
619H
1561
MSR_DRAM_ENERGY_STATUS
Package
DRAM Energy Status (R/O)
See Section 15.10.5, “DRAM RAPL Domain.”
61BH
1563
MSR_DRAM_PERF_STATUS
Package
DRAM Performance Throttling Status (R/O)
See Section 15.10.5, “DRAM RAPL Domain.”
61CH
1564
MSR_DRAM_POWER_INFO
Package
DRAM RAPL Parameters (R/W)
See Section 15.10.5, “DRAM RAPL Domain.”
632H
1586
MSR_PKG_C10_RESIDENCY
Package
Note: C-state values are processor specific C-state
code names, unrelated to MWAIT extension C-state
parameters or ACPI C-states.
63:0
Package C10 Residency Counter (R/O)
Value since last reset that the entire SOC is in an S0i3
state. Count at the same frequency as the TSC.
Vol. 4
2-127
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
639H
1593
MSR_PP0_ENERGY_STATUS
Package
PP0 Energy Status (R/O)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
641H
1601
MSR_PP1_ENERGY_STATUS
Package
PP1 Energy Status (R/O)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
64CH
1612
MSR_TURBO_ACTIVATION_RATIO
Package
ConfigTDP Control (R/W)
7:0
MAX_NON_TURBO_RATIO (RW/L)
System BIOS can program this field.
30:8
Reserved
31
TURBO_ACTIVATION_RATIO_Lock (RW/L)
When this bit is set, the content of this register is
locked until a reset.
63:32
Reserved
64FH
1615
MSR_CORE_PERF_LIMIT_REASONS
Package
Indicator of Frequency Clipping in Processor Cores
(R/W)
(Frequency refers to processor core frequency.)
0
PROCHOT Status (R0)
When set, processor core frequency is reduced below
the operating system request due to assertion of
external PROCHOT.
1
Thermal Status (R0)
When set, frequency is reduced below the operating
system request due to a thermal event.
2
Package-Level Power Limiting PL1 Status (R0)
When set, frequency is reduced below the operating
system request due to package-level power limiting
PL1.
3
Package-Level PL2 Power Limiting Status (R0)
When set, frequency is reduced below the operating
system request due to package-level power limiting
PL2.
8:4
Reserved
9
Core Power Limiting Status (R0)
When set, frequency is reduced below the operating
system request due to domain-level power limiting.
10
VR Therm Alert Status (R0)
When set, frequency is reduced below the operating
system request due to a thermal alert from the
Voltage Regulator.
11
Max Turbo Limit Status (R0)
When set, frequency is reduced below the operating
system request due to multi-core turbo limits.
2-128 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
12
Electrical Design Point Status (R0)
When set, frequency is reduced below the operating
system request due to electrical design point
constraints (e.g., maximum electrical current
consumption).
13
Turbo Transition Attenuation Status (R0)
When set, frequency is reduced below the operating
system request due to Turbo transition attenuation.
This prevents performance degradation due to
frequent operating ratio changes.
14
Maximum Efficiency Frequency Status (R0)
When set, frequency is reduced below the maximum
efficiency frequency.
15
Reserved
16
PROCHOT Log
When set, indicates that the PROCHOT Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
17
Thermal Log
When set, indicates that the Thermal Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
18
Package-Level PL1 Power Limiting Log
When set, indicates that the Package Level PL1 Power
Limiting Status bit has asserted since the log bit was
last cleared.
This log bit will remain set until cleared by software
writing 0.
19
Package-Level PL2 Power Limiting Log
When set, indicates that the Package Level PL2 Power
Limiting Status bit has asserted since the log bit was
last cleared.
This log bit will remain set until cleared by software
writing 0.
24:20
Reserved
25
Core Power Limiting Log
When set, indicates that the Core Power Limiting
Status bit has asserted since the log bit was last
cleared.
This log bit will remain set until cleared by software
writing 0.
Vol. 4
2-129
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
26
VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit
has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
27
Max Turbo Limit Log
When set, indicates that the Max Turbo Limit Status
bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
28
Electrical Design Point Log
When set, indicates that the EDP Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software
writing 0.
29
Turbo Transition Attenuation Log
When set, indicates that the Turbo Transition
Attenuation Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software
writing 0.
30
Maximum Efficiency Frequency Log
When set, indicates that the Maximum Efficiency
Frequency Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software
writing 0.
63:31
Reserved
680H
1664
MSR_LASTBRANCH_0_FROM_IP
Core
Last Branch Record 0 From IP (R/W)
One of 32 pairs of last branch record registers on the
last branch record stack. The From_IP part of the stack
contains pointers to the source instruction . See also:
• Last Branch Record Stack TOS at 1C9H.
• Section 18.6 and record format in Section 18.4.8.1.
0:47
From Linear Address (R/W)
62:48
Signed extension of bits 47:0.
63
Mispred
681H
1665
MSR_LASTBRANCH_1_FROM_IP
Core
Last Branch Record 1 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
682H
1666
MSR_LASTBRANCH_2_FROM_IP
Core
Last Branch Record 2 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
683H
1667
MSR_LASTBRANCH_3_FROM_IP
Core
Last Branch Record 3 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
2-130 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
684H
1668
MSR_LASTBRANCH_4_FROM_IP
Core
Last Branch Record 4 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
685H
1669
MSR_LASTBRANCH_5_FROM_IP
Core
Last Branch Record 5 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
686H
1670
MSR_LASTBRANCH_6_FROM_IP
Core
Last Branch Record 6 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
687H
1671
MSR_LASTBRANCH_7_FROM_IP
Core
Last Branch Record 7 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
688H
1672
MSR_LASTBRANCH_8_FROM_IP
Core
Last Branch Record 8 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
689H
1673
MSR_LASTBRANCH_9_FROM_IP
Core
Last Branch Record 9 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
68AH
1674
MSR_LASTBRANCH_10_FROM_IP
Core
Last Branch Record 10 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
68BH
1675
MSR_LASTBRANCH_11_FROM_IP
Core
Last Branch Record 11 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
68CH
1676
MSR_LASTBRANCH_12_FROM_IP
Core
Last Branch Record 12 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
68DH
1677
MSR_LASTBRANCH_13_FROM_IP
Core
Last Branch Record 13 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
68EH
1678
MSR_LASTBRANCH_14_FROM_IP
Core
Last Branch Record 14 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
68FH
1679
MSR_LASTBRANCH_15_FROM_IP
Core
Last Branch Record 15 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
690H
1680
MSR_LASTBRANCH_16_FROM_IP
Core
Last Branch Record 16 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
691H
1681
MSR_LASTBRANCH_17_FROM_IP
Core
Last Branch Record 17 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
692H
1682
MSR_LASTBRANCH_18_FROM_IP
Core
Last Branch Record 18 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
693H
1683
MSR_LASTBRANCH_19_FROM_IP
Core
Last Branch Record 19From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
694H
1684
MSR_LASTBRANCH_20_FROM_IP
Core
Last Branch Record 20 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
695H
1685
MSR_LASTBRANCH_21_FROM_IP
Core
Last Branch Record 21 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
696H
1686
MSR_LASTBRANCH_22_FROM_IP
Core
Last Branch Record 22 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Vol. 4
2-131
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
697H
1687
MSR_LASTBRANCH_23_FROM_IP
Core
Last Branch Record 23 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
698H
1688
MSR_LASTBRANCH_24_FROM_IP
Core
Last Branch Record 24 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
699H
1689
MSR_LASTBRANCH_25_FROM_IP
Core
Last Branch Record 25 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
69AH
1690
MSR_LASTBRANCH_26_FROM_IP
Core
Last Branch Record 26 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
69BH
1691
MSR_LASTBRANCH_27_FROM_IP
Core
Last Branch Record 27 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
69CH
1692
MSR_LASTBRANCH_28_FROM_IP
Core
Last Branch Record 28 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
69DH
1693
MSR_LASTBRANCH_29_FROM_IP
Core
Last Branch Record 29 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
69EH
1694
MSR_LASTBRANCH_30_FROM_IP
Core
Last Branch Record 30 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
69FH
1695
MSR_LASTBRANCH_31_FROM_IP
Core
Last Branch Record 31 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
6C0H
1728
MSR_LASTBRANCH_0_TO_IP
Core
Last Branch Record 0 To IP (R/W)
One of 32 pairs of last branch record registers on the
last branch record stack. The To_IP part of the stack
contains pointers to the Destination instruction and
elapsed cycles from last LBR update. See Section 18.6.
0:47
Target Linear Address (R/W)
63:48
Elapsed cycles from last update to the LBR.
6C1H
1729
MSR_LASTBRANCH_1_TO_IP
Core
Last Branch Record 1 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C2H
1730
MSR_LASTBRANCH_2_TO_IP
Core
Last Branch Record 2 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C3H
1731
MSR_LASTBRANCH_3_TO_IP
Core
Last Branch Record 3 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C4H
1732
MSR_LASTBRANCH_4_TO_IP
Core
Last Branch Record 4 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C5H
1733
MSR_LASTBRANCH_5_TO_IP
Core
Last Branch Record 5 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C6H
1734
MSR_LASTBRANCH_6_TO_IP
Core
Last Branch Record 6 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C7H
1735
MSR_LASTBRANCH_7_TO_IP
Core
Last Branch Record 7 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
2-132 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
6C8H
1736
MSR_LASTBRANCH_8_TO_IP
Core
Last Branch Record 8 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C9H
1737
MSR_LASTBRANCH_9_TO_IP
Core
Last Branch Record 9 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6CAH
1738
MSR_LASTBRANCH_10_TO_IP
Core
Last Branch Record 10 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6CBH
1739
MSR_LASTBRANCH_11_TO_IP
Core
Last Branch Record 11 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6CCH
1740
MSR_LASTBRANCH_12_TO_IP
Core
Last Branch Record 12 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6CDH
1741
MSR_LASTBRANCH_13_TO_IP
Core
Last Branch Record 13 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6CEH
1742
MSR_LASTBRANCH_14_TO_IP
Core
Last Branch Record 14 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6CFH
1743
MSR_LASTBRANCH_15_TO_IP
Core
Last Branch Record 15 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D0H
1744
MSR_LASTBRANCH_16_TO_IP
Core
Last Branch Record 16 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D1H
1745
MSR_LASTBRANCH_17_TO_IP
Core
Last Branch Record 17 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D2H
1746
MSR_LASTBRANCH_18_TO_IP
Core
Last Branch Record 18 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D3H
1747
MSR_LASTBRANCH_19_TO_IP
Core
Last Branch Record 19To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D4H
1748
MSR_LASTBRANCH_20_TO_IP
Core
Last Branch Record 20 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D5H
1749
MSR_LASTBRANCH_21_TO_IP
Core
Last Branch Record 21 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D6H
1750
MSR_LASTBRANCH_22_TO_IP
Core
Last Branch Record 22 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D7H
1751
MSR_LASTBRANCH_23_TO_IP
Core
Last Branch Record 23 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D8H
1752
MSR_LASTBRANCH_24_TO_IP
Core
Last Branch Record 24 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6D9H
1753
MSR_LASTBRANCH_25_TO_IP
Core
Last Branch Record 25 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6DAH
1754
MSR_LASTBRANCH_26_TO_IP
Core
Last Branch Record 26 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Vol. 4
2-133
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
6DBH
1755
MSR_LASTBRANCH_27_TO_IP
Core
Last Branch Record 27 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6DCH
1756
MSR_LASTBRANCH_28_TO_IP
Core
Last Branch Record 28 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6DDH
1757
MSR_LASTBRANCH_29_TO_IP
Core
Last Branch Record 29 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6DEH
1758
MSR_LASTBRANCH_30_TO_IP
Core
Last Branch Record 30 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6DFH
1759
MSR_LASTBRANCH_31_TO_IP
Core
Last Branch Record 31 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
802H
2050
IA32_X2APIC_APICID
Core
x2APIC ID register (R/O)
803H
2051
IA32_X2APIC_VERSION
Core
x2APIC Version register (R/O)
808H
2056
IA32_X2APIC_TPR
Core
x2APIC Task Priority register (R/W)
80AH
2058
IA32_X2APIC_PPR
Core
x2APIC Processor Priority register (R/O)
80BH
2059
IA32_X2APIC_EOI
Core
x2APIC EOI register (W/O)
80DH
2061
IA32_X2APIC_LDR
Core
x2APIC Logical Destination register (R/O)
80FH
2063
IA32_X2APIC_SIVR
Core
x2APIC Spurious Interrupt Vector register (R/W)
810H
2064
IA32_X2APIC_ISR0
Core
x2APIC In-Service register bits [31:0] (R/O)
811H
2065
IA32_X2APIC_ISR1
Core
x2APIC In-Service register bits [63:32] (R/O)
812H
2066
IA32_X2APIC_ISR2
Core
x2APIC In-Service register bits [95:64] (R/O)
813H
2067
IA32_X2APIC_ISR3
Core
x2APIC In-Service register bits [127:96] (R/O)
814H
2068
IA32_X2APIC_ISR4
Core
x2APIC In-Service register bits [159:128] (R/O)
815H
2069
IA32_X2APIC_ISR5
Core
x2APIC In-Service register bits [191:160] (R/O)
816H
2070
IA32_X2APIC_ISR6
Core
x2APIC In-Service register bits [223:192] (R/O)
817H
2071
IA32_X2APIC_ISR7
Core
x2APIC In-Service register bits [255:224] (R/O)
818H
2072
IA32_X2APIC_TMR0
Core
x2APIC Trigger Mode register bits [31:0] (R/O)
819H
2073
IA32_X2APIC_TMR1
Core
x2APIC Trigger Mode register bits [63:32] (R/O)
81AH
2074
IA32_X2APIC_TMR2
Core
x2APIC Trigger Mode register bits [95:64] (R/O)
81BH
2075
IA32_X2APIC_TMR3
Core
x2APIC Trigger Mode register bits [127:96] (R/O)
81CH
2076
IA32_X2APIC_TMR4
Core
x2APIC Trigger Mode register bits [159:128] (R/O)
81DH
2077
IA32_X2APIC_TMR5
Core
x2APIC Trigger Mode register bits [191:160] (R/O)
81EH
2078
IA32_X2APIC_TMR6
Core
x2APIC Trigger Mode register bits [223:192] (R/O)
81FH
2079
IA32_X2APIC_TMR7
Core
x2APIC Trigger Mode register bits [255:224] (R/O)
820H
2080
IA32_X2APIC_IRR0
Core
x2APIC Interrupt Request register bits [31:0] (R/O)
821H
2081
IA32_X2APIC_IRR1
Core
x2APIC Interrupt Request register bits [63:32] (R/O)
822H
2082
IA32_X2APIC_IRR2
Core
x2APIC Interrupt Request register bits [95:64] (R/O)
823H
2083
IA32_X2APIC_IRR3
Core
x2APIC Interrupt Request register bits [127:96] (R/O)
2-134 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
824H
2084
IA32_X2APIC_IRR4
Core
x2APIC Interrupt Request register bits [159:128]
(R/O)
825H
2085
IA32_X2APIC_IRR5
Core
x2APIC Interrupt Request register bits [191:160]
(R/O)
826H
2086
IA32_X2APIC_IRR6
Core
x2APIC Interrupt Request register bits [223:192]
(R/O)
827H
2087
IA32_X2APIC_IRR7
Core
x2APIC Interrupt Request register bits [255:224]
(R/O)
828H
2088
IA32_X2APIC_ESR
Core
x2APIC Error Status register (R/W)
82FH
2095
IA32_X2APIC_LVT_CMCI
Core
x2APIC LVT Corrected Machine Check Interrupt
register (R/W)
830H
2096
IA32_X2APIC_ICR
Core
x2APIC Interrupt Command register (R/W)
832H
2098
IA32_X2APIC_LVT_TIMER
Core
x2APIC LVT Timer Interrupt register (R/W)
833H
2099
IA32_X2APIC_LVT_THERMAL
Core
x2APIC LVT Thermal Sensor Interrupt register (R/W)
834H
2100
IA32_X2APIC_LVT_PMI
Core
x2APIC LVT Performance Monitor register (R/W)
835H
2101
IA32_X2APIC_LVT_LINT0
Core
x2APIC LVT LINT0 register (R/W)
836H
2102
IA32_X2APIC_LVT_LINT1
Core
x2APIC LVT LINT1 register (R/W)
837H
2103
IA32_X2APIC_LVT_ERROR
Core
x2APIC LVT Error register (R/W)
838H
2104
IA32_X2APIC_INIT_COUNT
Core
x2APIC Initial Count register (R/W)
839H
2105
IA32_X2APIC_CUR_COUNT
Core
x2APIC Current Count register (R/O)
83EH
2110
IA32_X2APIC_DIV_CONF
Core
x2APIC Divide Configuration register (R/W)
83FH
2111
IA32_X2APIC_SELF_IPI
Core
x2APIC Self IPI register (W/O)
C8FH
3215
IA32_PQR_ASSOC
Core
Resource Association Register (R/W)
31:0
Reserved
33:32
COS (R/W)
63: 34
Reserved
D10H
3344
IA32_L2_QOS_MASK_0
Module
L2 Class Of Service Mask - COS 0 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=0.
0:7
CBM: Bit vector of available L2 ways for COS 0
enforcement.
63:8
Reserved
D11H
3345
IA32_L2_QOS_MASK_1
Module
L2 Class Of Service Mask - COS 1 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=1.
0:7
CBM: Bit vector of available L2 ways for COS 0
enforcement.
63:8
Reserved
D12H
3346
IA32_L2_QOS_MASK_2
Module
L2 Class Of Service Mask - COS 2 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=2.
0:7
CBM: Bit vector of available L2 ways for COS 0
enforcement.
Vol. 4
2-135
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
63:8
Reserved
D13H
3347
IA32_L2_QOS_MASK_3
Package
L2 Class Of Service Mask - COS 3 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=3.
0:19
CBM: Bit vector of available L2 ways for COS 3
enforcement.
63:20
Reserved
D90H
3472
IA32_BNDCFGS
Core
See Table 2-2.
DA0H
3488
IA32_XSS
Core
See Table 2-2.
See Table 2-6, and Table 2-12 for MSR definitions applicable to processors with a CPUID Signature DisplayFamily_DisplayModel value
of 06_5CH.
2.6
MSRS IN INTEL ATOM® PROCESSORS BASED ON GOLDMONT PLUS
MICROARCHITECTURE
Intel Atom processors based on the Goldmont Plus microarchitecture support MSRs listed in Table 2-6, Table 2-12,
and Table 2-13. These processors have a CPUID Signature DisplayFamily_DisplayModel value of 06_7AH; see Table
2-1. For an MSR listed in Table 2-13 that also appears in the model-specific tables of prior generations, Table 2-13
supersede prior generation tables.
In the Goldmont Plus microarchitecture, the scope column indicates the following: “Core” means each processor
core has a separate MSR, or a bit field not shared with another processor core. “Module” means the MSR or the bit
field is shared by a subset of the processor cores in the physical package. The number of processor cores in this
subset is model specific and may differ between different processors. For all processors based on Goldmont Plus
microarchitecture, the L2 cache is also shared between cores in a module and thus CPUID leaf 04H enumeration
can be used to figure out which processors are in the same module. “Package” means all processor cores in the
physical package share the same MSR or bit interface.
Table 2-13. MSRs in Intel Atom® Processors Based on Goldmont Plus Microarchitecture
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
3AH
58
IA32_FEATURE_CONTROL
Core
Control Features in Intel 64Processor (R/W)
See Table 2-2.
0
Lock (R/WL)
1
Enable VMX inside SMX operation (R/WL)
2
Enable VMX outside SMX operation (R/WL)
14:8
SENTER local functions enables (R/WL)
15
SENTER global functions enable (R/WL)
17
SGX Launch Control Enable (R/WL)
This bit must be set to enable runtime reconfiguration
of SGX Launch Control via IA32_SGXLEPUBKEYHASHn
MSR.
Valid if CPUID.(EAX=07H, ECX=0H): ECX[30] = 1.
2-136 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-13. MSRs in Intel Atom® Processors Based on Goldmont Plus Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
18
SGX global functions enable (R/WL)
63:19
Reserved
8CH
140
IA32_SGXLEPUBKEYHASH0
Core
See Table 2-2.
8DH
141
IA32_SGXLEPUBKEYHASH1
Core
See Table 2-2.
8EH
142
IA32_SGXLEPUBKEYHASH2
Core
See Table 2-2.
8FH
143
IA32_SGXLEPUBKEYHASH3
Core
See Table 2-2.
3F1H
1009
IA32_PEBS_ENABLE
Core
(R/W) See Table 2-2. See Section 20.6.2.4, “Processor
Event Based Sampling (PEBS).”
(MSR_PEBS_ENABLE)
0
Enable PEBS trigger and recording for the
programmed event (precise or otherwise) on
IA32_PMC0.
1
Enable PEBS trigger and recording for the
programmed event (precise or otherwise) on
IA32_PMC1.
2
Enable PEBS trigger and recording for the
programmed event (precise or otherwise) on
IA32_PMC2.
3
Enable PEBS trigger and recording for the
programmed event (precise or otherwise) on
IA32_PMC3.
31:4
Reserved
32
Enable PEBS trigger and recording for
IA32_FIXED_CTR0.
33
Enable PEBS trigger and recording for
IA32_FIXED_CTR1.
34
Enable PEBS trigger and recording for
IA32_FIXED_CTR2.
63:35
Reserved
570H
1392
IA32_RTIT_CTL
Core
Trace Control Register (R/W)
0
TraceEn
1
CYCEn
2
OS
3
User
4
PwrEvtEn
5
FUPonPTW
6
FabricEn
7
CR3Filter
8
ToPA
Writing 0 will #GP if also setting TraceEn.
9
MTCEn
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-13. MSRs in Intel Atom® Processors Based on Goldmont Plus Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
10
TSCEn
11
DisRETC
12
PTWEn
13
BranchEn
17:14
MTCFreq
18
Reserved, must be zero.
22:19
CycThresh
23
Reserved, must be zero.
27:24
PSBFreq
31:28
Reserved, must be zero.
35:32
ADDR0_CFG
39:36
ADDR1_CFG
63:40
Reserved, must be zero.
680H
1664
MSR_LASTBRANCH_0_FROM_IP
Core
Last Branch Record 0 From IP (R/W)
One of the three MSRs that make up the first entry of
the 32-entry LBR stack. The From_IP part of the stack
contains pointers to the source instruction. See also:
• Last Branch Record Stack TOS at 1C9H.
• Section 18.7, “Last Branch, Call Stack, Interrupt, and
Exception Recording for Processors based on
Goldmont Plus Microarchitecture.”
681H
1665
MSR_LASTBRANCH_i_FROM_IP
Core
Last Branch Record i From IP (R/W)
-
-
See description of MSR_LASTBRANCH_0_FROM_IP; i
69FH
1695
= 1-31.
6C0H
1728
MSR_LASTBRANCH_0_TO_IP
Core
Last Branch Record 0 To IP (R/W)
One of the three MSRs that make up the first entry of
the 32-entry LBR stack. The To_IP part of the stack
contains pointers to the Destination instruction. See
also:
• Section 18.7, “Last Branch, Call Stack, Interrupt, and
Exception Recording for Processors based on
Goldmont Plus Microarchitecture.”
6C1H
1729
MSR_LASTBRANCH_i_TO_IP
Core
Last Branch Record i To IP (R/W)
-
-
See description of MSR_LASTBRANCH_0_TO_IP; i = 1-
6DFH
1759
31.
DC0H
3520
MSR_LASTBRANCH_INFO_0
Core
Last Branch Record 0 Additional Information (R/W)
One of the three MSRs that make up the first entry of
the 32-entry LBR stack. This part of the stack
contains flag and elapsed cycle information. See also:
• Last Branch Record Stack TOS at 1C9H.
• Section 18.9.1, “LBR Stack.”
DC1H
3521
MSR_LASTBRANCH_INFO_1
Core
Last Branch Record 1 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
2-138 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-13. MSRs in Intel Atom® Processors Based on Goldmont Plus Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
DC2H
3522
MSR_LASTBRANCH_INFO_2
Core
Last Branch Record 2 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DC3H
3523
MSR_LASTBRANCH_INFO_3
Core
Last Branch Record 3 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DC4H
3524
MSR_LASTBRANCH_INFO_4
Core
Last Branch Record 4 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DC5H
3525
MSR_LASTBRANCH_INFO_5
Core
Last Branch Record 5 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DC6H
3526
MSR_LASTBRANCH_INFO_6
Core
Last Branch Record 6 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DC7H
3527
MSR_LASTBRANCH_INFO_7
Core
Last Branch Record 7 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DC8H
3528
MSR_LASTBRANCH_INFO_8
Core
Last Branch Record 8 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DC9H
3529
MSR_LASTBRANCH_INFO_9
Core
Last Branch Record 9 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DCAH
3530
MSR_LASTBRANCH_INFO_10
Core
Last Branch Record 10 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DCBH
3531
MSR_LASTBRANCH_INFO_11
Core
Last Branch Record 11 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DCCH
3532
MSR_LASTBRANCH_INFO_12
Core
Last Branch Record 12 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DCDH
3533
MSR_LASTBRANCH_INFO_13
Core
Last Branch Record 13 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DCEH
3534
MSR_LASTBRANCH_INFO_14
Core
Last Branch Record 14 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DCFH
3535
MSR_LASTBRANCH_INFO_15
Core
Last Branch Record 15 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DD0H
3536
MSR_LASTBRANCH_INFO_16
Core
Last Branch Record 16 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DD1H
3537
MSR_LASTBRANCH_INFO_17
Core
Last Branch Record 17 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DD2H
3538
MSR_LASTBRANCH_INFO_18
Core
Last Branch Record 18 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DD3H
3539
MSR_LASTBRANCH_INFO_19
Core
Last Branch Record 19 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DD4H
3520
MSR_LASTBRANCH_INFO_20
Core
Last Branch Record 20 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Vol. 4
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-13. MSRs in Intel Atom® Processors Based on Goldmont Plus Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
DD5H
3521
MSR_LASTBRANCH_INFO_21
Core
Last Branch Record 21 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DD6H
3522
MSR_LASTBRANCH_INFO_22
Core
Last Branch Record 22 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DD7H
3523
MSR_LASTBRANCH_INFO_23
Core
Last Branch Record 23 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DD8H
3524
MSR_LASTBRANCH_INFO_24
Core
Last Branch Record 24 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DD9H
3525
MSR_LASTBRANCH_INFO_25
Core
Last Branch Record 25 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DDAH
3526
MSR_LASTBRANCH_INFO_26
Core
Last Branch Record 26 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DDBH
3527
MSR_LASTBRANCH_INFO_27
Core
Last Branch Record 27 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DDCH
3528
MSR_LASTBRANCH_INFO_28
Core
Last Branch Record 28 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DDDH
3529
MSR_LASTBRANCH_INFO_29
Core
Last Branch Record 29 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DDEH
3530
MSR_LASTBRANCH_INFO_30
Core
Last Branch Record 30 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
DDFH
3531
MSR_LASTBRANCH_INFO_31
Core
Last Branch Record 31 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
See Table 2-6, Table 2-12, and Table 2-13 for MSR definitions applicable to processors with a CPUID Signature
DisplayFamily_DisplayModel value of 06_7AH.
2.7
MSRS IN INTEL ATOM® PROCESSORS BASED ON TREMONT
MICROARCHITECTURE
Processors based on the Tremont microarchitecture support MSRs listed in Table 2-6, Table 2-12, Table 2-13, and
Table 2-14. These processors have a CPUID Signature DisplayFamily_DisplayModel value of 06_86H, 06_96H, or
06_9CH; see Table 2-1. For an MSR listed in Table 2-14 that also appears in the model-specific tables of prior
generations, Table 2-14 supersede prior generation tables.
In the Tremont microarchitecture, the scope column indicates the following: “Core” means each processor core has
a separate MSR, or a bit field not shared with another processor core. “Module” means the MSR or the bit field is
shared by a subset of the processor cores in the physical package. The number of processor cores in this subset is
model specific and may differ between different processors. For all processors based on Tremont microarchitecture,
the L2 cache is also shared between cores in a module and thus CPUID leaf 04H enumeration can be used to figure
out which processors are in the same module. “Package” means all processor cores in the physical package share
the same MSR or bit interface.
2-140 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-14. MSRs in Intel Atom® Processors Based on Tremont Microarchitecture
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
33H
51
MSR_MEMORY_CTRL
Core
Memory Control Register
28:0
Reserved.
29
SPLIT_LOCK_DISABLE
If set to 1, a split lock will cause an #AC(0) exception.
See Section 9.1.2.3, “Features to Disable Bus Locks.”
30
Reserved.
31
Reserved.
CFH
207
IA32_CORE_CAPABILITIES
Core
IA32 Core Capabilities Register
If CPUID.(EAX=07H, ECX=0):EDX[30] = 1.
4:0
Reserved.
5
SPLIT_LOCK_DISABLE_SUPPORTED
When read as 1, software can set bit 29 of
MSR_MEMORY_CTRL (MSR address 33H).
63:6
Reserved.
2A0H
672
MSR_PRMRR_BASE_0
Core
Processor Reserved Memory Range Register - Physical
Base Control Register (R/W)
2:0
MEMTYPE: PRMRR BASE Memory Type.
3
CONFIGURED: PRMRR BASE Configured.
11:4
Reserved.
51:12
BASE: PRMRR Base Address.
63:52
Reserved.
3F1H
1009
IA32_PEBS_ENABLE
Core
(R/W) See Table 2-2. See Section 20.6.2.4, “Processor
Event Based Sampling (PEBS).”
(MSR_PEBS_ENABLE)
n:0
Enable PEBS trigger and recording for the programmed
event (precise or otherwise) on IA32_PMCx. The
maximum value n can be determined from
CPUID.0AH:EAX[15:8].
31:n+1
Reserved.
32+m:32
Enable PEBS trigger and recording for
IA32_FIXED_CTRx. The maximum value m can be
determined from CPUID.0AH:EDX[4:0].
59:33+m
Reserved.
60
Pend a PerfMon Interrupt (PMI) after each PEBS event.
62:61
Specifies PEBS output destination. Encodings:
00B: DS Save Area
01B: Intel PT trace output. Supported if
IA32_PERF_CAPABILITIES.PEBS_OUTPUT_PT_AVAIL[
16] and CPUID.07H.0.EBX[25] are set.
10B: Reserved
11B: Reserved
Vol. 4
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-14. MSRs in Intel Atom® Processors Based on Tremont Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
63
Reserved.
1309H
4873
MSR_RELOAD_FIXED_CTRx
Reload value for IA32_FIXED_CTRx (R/W)
-
-
47:0
Value loaded into IA32_FIXED_CTRx when a PEBS
130BH
4875
record is generated while PEBS_EN_FIXEDx = 1 and
PEBS_OUTPUT = 01B in IA32_PEBS_ENABLE, and
FIXED_CTRx is overflowed.
63:48
Reserved.
14C1H
5313
MSR_RELOAD_PMCx
Core
Reload value for IA32_PMCx (R/W)
-
-
47:0
Value loaded into IA32_PMCx when a PEBS record is
14C4H
5316
generated while PEBS_EN_PMCx = 1 and
PEBS_OUTPUT = 01B in IA32_PEBS_ENABLE, and
PMCx is overflowed.
63:48
Reserved.
See Table 2-6, Table 2-12, Table 2-13, and Table 2-14 for MSR definitions applicable to processors with a CPUID Signature
DisplayFamily_DisplayModel value of 06_86H.
2.8
MSRS IN PROCESSORS BASED ON NEHALEM MICROARCHITECTURE
Table 2-15 lists model-specific registers (MSRs) that are common for Nehalem microarchitecture. These include the
Intel Core i7 and i5 processor family. These processors have a CPUID Signature DisplayFamily_DisplayModel value
of 06_1AH, 06_1EH, 06_1FH, or 06_2EH; see Table 2-1. Additional MSRs specific to processors with a CPUID
Signature DisplayFamily_DisplayModel value of 06_1AH, 06_1EH, or 06_1FH are listed in Table 2-16. Some MSRs
listed in these tables are used by BIOS. More information about these MSR can be found at http://biosbits.org.
The column “Scope” represents the package/core/thread scope of individual bit field of an MSR. “Thread” means
this bit field must be programmed on each logical processor independently. “Core” means the bit field must be
programmed on each processor core independently, logical processors in the same core will be affected by change
of this bit on the other logical processor in the same core. “Package” means the bit field must be programmed once
for each physical package. Change of a bit filed with a package scope will affect all logical processors in that phys-
ical package.
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
0H
0
IA32_P5_MC_ADDR
Thread
See Section 2.23, “MSRs in Pentium Processors.”
1H
1
IA32_P5_MC_TYPE
Thread
See Section 2.23, “MSRs in Pentium Processors.”
6H
6
IA32_MONITOR_FILTER_SIZE
Thread
See Section 9.10.5, “Monitor/Mwait Address Range
Determination,” and Table 2-2.
10H
16
IA32_TIME_STAMP_COUNTER
Thread
See Section 18.17, “Time-Stamp Counter,” and see
Table 2-2.
17H
23
IA32_PLATFORM_ID
Package
Platform ID (R)
See Table 2-2.
17H
23
MSR_PLATFORM_ID
Package
Model Specific Platform ID (R)
2-142 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
49:0
Reserved
52:50
See Table 2-2.
63:53
Reserved
1BH
27
IA32_APIC_BASE
Thread
See Section 11.4.4, “Local APIC Status and Location,”
and Table 2-2.
34H
52
MSR_SMI_COUNT
Thread
SMI Counter (R/O)
31:0
SMI Count (R/O)
Running count of SMI events since last RESET.
63:32
Reserved
3AH
58
IA32_FEATURE_CONTROL
Thread
Control Features in Intel 64Processor (R/W)
See Table 2-2.
79H
121
IA32_BIOS_UPDT_TRIG
Core
BIOS Update Trigger Register (W)
See Table 2-2.
8BH
139
IA32_BIOS_SIGN_ID
Thread
BIOS Update Signature ID (R/W)
See Table 2-2.
C1H
193
IA32_PMC0
Thread
Performance Counter Register
See Table 2-2.
C2H
194
IA32_PMC1
Thread
Performance Counter Register
See Table 2-2.
C3H
195
IA32_PMC2
Thread
Performance Counter Register
See Table 2-2.
C4H
196
IA32_PMC3
Thread
Performance Counter Register
See Table 2-2.
CEH
206
MSR_PLATFORM_INFO
Package
Platform Information
Contains power management and other model specific
features enumeration. See http://biosbits.org.
7:0
Reserved
15:8
Package
Maximum Non-Turbo Ratio (R/O)
This is the ratio of the frequency that invariant TSC
runs at. The invariant TSC frequency can be computed
by multiplying this ratio by 133.33 MHz.
27:16
Reserved
28
Package
Programmable Ratio Limit for Turbo Mode (R/O)
When set to 1, indicates that Programmable Ratio Limit
for Turbo mode is enabled. When set to 0, indicates
Programmable Ratio Limit for Turbo mode is disabled.
Vol. 4
2-143
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
29
Package
Programmable TDC-TDP Limit for Turbo Mode (R/O)
When set to 1, indicates that TDC and TDP Limits for
Turbo mode are programmable. When set to 0, indicates
TDC and TDP Limits for Turbo mode are not
programmable.
39:30
Reserved
47:40
Package
Maximum Efficiency Ratio (R/O)
This is the minimum ratio (maximum efficiency) that the
processor can operate, in units of 133.33MHz.
63:48
Reserved
E2H
226
MSR_PKG_CST_CONFIG_CONTROL
Core
C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-States. See http://biosbits.org.
2:0
Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code
name (consuming the least power) for the package. The
default is set as factory-configured package C-state
limit.
The following C-state code name encodings are
supported:
000b: C0 (no package C-sate support)
001b: C1 (Behavior is the same as 000b)
010b: C3
011b: C6
100b: C7
101b and 110b: Reserved
111: No package C-state limit.
Note: This field cannot be used to limit package C-state
to C3.
9:3
Reserved
10
I/O MWAIT Redirection Enable (R/W)
When set, will map IO_read instructions sent to IO
register specified by MSR_PMG_IO_CAPTURE_BASE to
MWAIT instructions.
14:11
Reserved
15
CFG Lock (R/WO)
When set, locks bits 15:0 of this register until next
reset.
23:16
Reserved
2-144 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
24
Interrupt filtering enable (R/W)
When set, processor cores in a deep C-State will wake
only when the event message is destined for that core.
When 0, all processor cores in a deep C-State will wake
for an event message.
25
C3 state auto demotion enable (R/W)
When set, the processor will conditionally demote
C6/C7 requests to C3 based on uncore auto-demote
information.
26
C1 state auto demotion enable (R/W)
When set, the processor will conditionally demote
C3/C6/C7 requests to C1 based on uncore auto-demote
information.
27
Enable C3 Undemotion (R/W)
28
Enable C1 Undemotion (R/W)
29
Package C State Demotion Enable (R/W)
30
Package C State UnDemotion Enable (R/W)
63:31
Reserved
E4H
228
MSR_PMG_IO_CAPTURE_BASE
Core
Power Management IO Redirection in C-state (R/W)
15:0
LVL_2 Base Address (R/W)
Specifies the base address visible to software for IO
redirection. If IO MWAIT Redirection is enabled, reads to
this address will be consumed by the power
management logic and decoded to MWAIT instructions.
When IO port address redirection is enabled, this is the
IO port address reported to the OS/software.
18:16
C-state Range (R/W)
Specifies the encoding value of the maximum C-State
code name to be included when IO read to MWAIT
redirection is enabled by
MSR_PKG_CST_CONFIG_CONTROL[bit10]:
000b - C3 is the max C-State to include.
001b - C6 is the max C-State to include.
010b - C7 is the max C-State to include.
63:19
Reserved
E7H
231
IA32_MPERF
Thread
Maximum Performance Frequency Clock Count (R/W)
See Table 2-2.
E8H
232
IA32_APERF
Thread
Actual Performance Frequency Clock Count (R/W)
See Table 2-2.
FEH
254
IA32_MTRRCAP
Thread
See Table 2-2.
174H
372
IA32_SYSENTER_CS
Thread
See Table 2-2.
175H
373
IA32_SYSENTER_ESP
Thread
See Table 2-2.
Vol. 4
2-145
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
176H
374
IA32_SYSENTER_EIP
Thread
See Table 2-2.
179H
377
IA32_MCG_CAP
Thread
See Table 2-2.
17AH
378
IA32_MCG_STATUS
Thread
Global Machine Check Status
0
RIPV
When set, bit indicates that the instruction addressed
by the instruction pointer pushed on the stack (when
the machine check was generated) can be used to
restart the program. If cleared, the program cannot be
reliably restarted.
1
EIPV
When set, bit indicates that the instruction addressed
by the instruction pointer pushed on the stack (when
the machine check was generated) is directly
associated with the error.
2
MCIP
When set, bit indicates that a machine check has been
generated. If a second machine check is detected while
this bit is still set, the processor enters a shutdown
state. Software should write this bit to 0 after
processing a machine check exception.
63:3
Reserved
186H
390
IA32_PERFEVTSEL0
Thread
See Table 2-2.
7:0
Event Select
15:8
UMask
16
USR
17
OS
18
Edge
19
PC
20
INT
21
AnyThread
22
EN
23
INV
31:24
CMASK
63:32
Reserved
187H
391
IA32_PERFEVTSEL1
Thread
See Table 2-2.
188H
392
IA32_PERFEVTSEL2
Thread
See Table 2-2.
189H
393
IA32_PERFEVTSEL3
Thread
See Table 2-2.
198H
408
IA32_PERF_STATUS
Core
See Table 2-2.
15:0
Current Performance State Value.
63:16
Reserved
199H
409
IA32_PERF_CTL
Thread
See Table 2-2.
2-146 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
19AH
410
IA32_CLOCK_MODULATION
Thread
Clock Modulation (R/W)
See Table 2-2.
IA32_CLOCK_MODULATION MSR was originally named
IA32_THERM_CONTROL MSR.
0
Reserved
3:1
On demand Clock Modulation Duty Cycle (R/W)
4
On demand Clock Modulation Enable (R/W)
63:5
Reserved
19BH
411
IA32_THERM_INTERRUPT
Core
Thermal Interrupt Control (R/W)
See Table 2-2.
19CH
412
IA32_THERM_STATUS
Core
Thermal Monitor Status (R/W)
See Table 2-2.
1A0H
416
IA32_MISC_ENABLE
Enable Misc. Processor Features (R/W)
Allows a variety of processor functions to be enabled
and disabled.
0
Thread
Fast-Strings Enable
See Table 2-2.
2:1
Reserved
3
Thread
Automatic Thermal Control Circuit Enable (R/W)
See Table 2-2. Default value is 1.
6:4
Reserved
7
Thread
Performance Monitoring Available (R)
See Table 2-2.
10:8
Reserved
11
Thread
Branch Trace Storage Unavailable (R/O)
See Table 2-2.
12
Thread
Processor Event Based Sampling Unavailable (R/O)
See Table 2-2.
15:13
Reserved
16
Package
Enhanced Intel SpeedStep Technology Enable (R/W)
See Table 2-2.
18
Thread
ENABLE MONITOR FSM. (R/W) See Table 2-2.
21:19
Reserved
22
Thread
Limit CPUID Maxval (R/W)
See Table 2-2.
23
Thread
xTPR Message Disable (R/W)
See Table 2-2.
33:24
Reserved
Vol. 4
2-147
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
34
Thread
XD Bit Disable (R/W)
See Table 2-3.
37:35
Reserved
38
Package
Turbo Mode Disable (R/W)
When set to 1 on processors that support Intel Turbo
Boost Technology, the turbo mode feature is disabled
and the IDA_Enable feature flag will be clear
(CPUID.06H: EAX[1]=0).
When set to a 0 on processors that support IDA,
CPUID.06H: EAX[1] reports the processor’s support of
turbo mode is enabled.
Note: The power-on default value is used by BIOS to
detect hardware support of turbo mode. If the power-
on default value is 1, turbo mode is available in the
processor. If the power-on default value is 0, turbo
mode is not available.
63:39
Reserved
1A2H
418
MSR_TEMPERATURE_TARGET
Thread
Temperature Target
15:0
Reserved
23:16
Temperature Target (R)
The minimum temperature at which PROCHOT# will be
asserted. The value is degrees C.
63:24
Reserved
1A4H
420
MSR_MISC_FEATURE_CONTROL
Miscellaneous Feature Control (R/W)
0
Core
L2 Hardware Prefetcher Disable (R/W)
If 1, disables the L2 hardware prefetcher, which fetches
additional lines of code or data into the L2 cache.
1
Core
L2 Adjacent Cache Line Prefetcher Disable (R/W)
If 1, disables the adjacent cache line prefetcher, which
fetches the cache line that comprises a cache line pair
(128 bytes).
2
Core
DCU Hardware Prefetcher Disable (R/W)
If 1, disables the L1 data cache prefetcher, which
fetches the next cache line into L1 data cache.
3
Core
DCU IP Prefetcher Disable (R/W)
If 1, disables the L1 data cache IP prefetcher, which
uses sequential load history (based on instruction
pointer of previous loads) to determine whether to
prefetch additional lines.
63:4
Reserved
1A6H
422
MSR_OFFCORE_RSP_0
Thread
Offcore Response Event Select Register (R/W)
1AAH
426
MSR_MISC_PWR_MGMT
Miscellaneous Power Management Control
Various model specific features enumeration. See
2-148 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
0
Package
EIST Hardware Coordination Disable (R/W)
When 0, enables hardware coordination of Enhanced
Intel Speedstep Technology request from processor
cores. When 1, disables hardware coordination of
Enhanced Intel Speedstep Technology requests.
1
Thread
Energy/Performance Bias Enable (R/W)
This bit makes the IA32_ENERGY_PERF_BIAS register
(MSR 1B0h) visible to software with Ring 0 privileges.
This bit’s status (1 or 0) is also reflected by
CPUID.(EAX=06h):ECX[3].
63:2
Reserved
1ACH
428
MSR_TURBO_POWER_CURRENT_LIMIT
14:0
Package
TDP Limit (R/W)
TDP limit in 1/8 Watt granularity.
15
Package
TDP Limit Override Enable (R/W)
A value = 0 indicates override is not active; a value = 1
indicates override is active.
30:16
Package
TDC Limit (R/W)
TDC limit in 1/8 Amp granularity.
31
Package
TDC Limit Override Enable (R/W)
A value = 0 indicates override is not active; a value = 1
indicates override is active.
63:32
Reserved
1ADH
429
MSR_TURBO_RATIO_LIMIT
Package
Maximum Ratio Limit of Turbo Mode
R/O if MSR_PLATFORM_INFO.[28] = 0.
R/W if MSR_PLATFORM_INFO.[28] = 1.
7:0
Package
Maximum Ratio Limit for 1C
Maximum turbo ratio limit of 1 core active.
15:8
Package
Maximum Ratio Limit for 2C
Maximum turbo ratio limit of 2 core active.
23:16
Package
Maximum Ratio Limit for 3C
Maximum turbo ratio limit of 3 core active.
31:24
Package
Maximum Ratio Limit for 4C
Maximum turbo ratio limit of 4 core active.
63:32
Reserved
1C8H
456
MSR_LBR_SELECT
Core
Last Branch Record Filtering Select Register (R/W)
See Section 18.9.2, “Filtering of Last Branch Records.”
0
CPL_EQ_0
1
CPL_NEQ_0
2
JCC
3
NEAR_REL_CALL
Vol. 4
2-149
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
4
NEAR_IND_CALL
5
NEAR_RET
6
NEAR_IND_JMP
7
NEAR_REL_JMP
8
FAR_BRANCH
63:9
Reserved
1C9H
457
MSR_LASTBRANCH_TOS
Thread
Last Branch Record Stack TOS (R/W)
Contains an index (bits 0-3) that points to the MSR
containing the most recent branch record.
See MSR_LASTBRANCH_0_FROM_IP (at 680H).
1D9H
473
IA32_DEBUGCTL
Thread
Debug Control (R/W)
See Table 2-2.
1DDH
477
MSR_LER_FROM_LIP
Thread
Last Exception Record From Linear IP (R)
Contains a pointer to the last branch instruction that
the processor executed prior to the last exception that
was generated or the last interrupt that was handled.
1DEH
478
MSR_LER_TO_LIP
Thread
Last Exception Record To Linear IP (R)
This area contains a pointer to the target of the last
branch instruction that the processor executed prior to
the last exception that was generated or the last
interrupt that was handled.
1F2H
498
IA32_SMRR_PHYSBASE
Core
See Table 2-2.
1F3H
499
IA32_SMRR_PHYSMASK
Core
See Table 2-2.
1FCH
508
MSR_POWER_CTL
Core
Power Control Register
0
Reserved
1
Package
C1E Enable (R/W)
When set to ‘1’, will enable the CPU to switch to the
Minimum Enhanced Intel SpeedStep Technology
operating point when all execution cores enter MWAIT
(C1).
63:2
Reserved
200H
512
IA32_MTRR_PHYSBASE0
Thread
See Table 2-2.
201H
513
IA32_MTRR_PHYSMASK0
Thread
See Table 2-2.
202H
514
IA32_MTRR_PHYSBASE1
Thread
See Table 2-2.
203H
515
IA32_MTRR_PHYSMASK1
Thread
See Table 2-2.
204H
516
IA32_MTRR_PHYSBASE2
Thread
See Table 2-2.
205H
517
IA32_MTRR_PHYSMASK2
Thread
See Table 2-2.
206H
518
IA32_MTRR_PHYSBASE3
Thread
See Table 2-2.
2-150 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
207H
519
IA32_MTRR_PHYSMASK3
Thread
See Table 2-2.
208H
520
IA32_MTRR_PHYSBASE4
Thread
See Table 2-2.
209H
521
IA32_MTRR_PHYSMASK4
Thread
See Table 2-2.
20AH
522
IA32_MTRR_PHYSBASE5
Thread
See Table 2-2.
20BH
523
IA32_MTRR_PHYSMASK5
Thread
See Table 2-2.
20CH
524
IA32_MTRR_PHYSBASE6
Thread
See Table 2-2.
20DH
525
IA32_MTRR_PHYSMASK6
Thread
See Table 2-2.
20EH
526
IA32_MTRR_PHYSBASE7
Thread
See Table 2-2.
20FH
527
IA32_MTRR_PHYSMASK7
Thread
See Table 2-2.
210H
528
IA32_MTRR_PHYSBASE8
Thread
See Table 2-2.
211H
529
IA32_MTRR_PHYSMASK8
Thread
See Table 2-2.
212H
530
IA32_MTRR_PHYSBASE9
Thread
See Table 2-2.
213H
531
IA32_MTRR_PHYSMASK9
Thread
See Table 2-2.
250H
592
IA32_MTRR_FIX64K_00000
Thread
See Table 2-2.
258H
600
IA32_MTRR_FIX16K_80000
Thread
See Table 2-2.
259H
601
IA32_MTRR_FIX16K_A0000
Thread
See Table 2-2.
268H
616
IA32_MTRR_FIX4K_C0000
Thread
See Table 2-2.
269H
617
IA32_MTRR_FIX4K_C8000
Thread
See Table 2-2.
26AH
618
IA32_MTRR_FIX4K_D0000
Thread
See Table 2-2.
26BH
619
IA32_MTRR_FIX4K_D8000
Thread
See Table 2-2.
26CH
620
IA32_MTRR_FIX4K_E0000
Thread
See Table 2-2.
26DH
621
IA32_MTRR_FIX4K_E8000
Thread
See Table 2-2.
26EH
622
IA32_MTRR_FIX4K_F0000
Thread
See Table 2-2.
26FH
623
IA32_MTRR_FIX4K_F8000
Thread
See Table 2-2.
277H
631
IA32_PAT
Thread
See Table 2-2.
280H
640
IA32_MC0_CTL2
Package
See Table 2-2.
281H
641
IA32_MC1_CTL2
Package
See Table 2-2.
282H
642
IA32_MC2_CTL2
Core
See Table 2-2.
283H
643
IA32_MC3_CTL2
Core
See Table 2-2.
284H
644
IA32_MC4_CTL2
Core
See Table 2-2.
285H
645
IA32_MC5_CTL2
Core
See Table 2-2.
286H
646
IA32_MC6_CTL2
Package
See Table 2-2.
287H
647
IA32_MC7_CTL2
Package
See Table 2-2.
288H
648
IA32_MC8_CTL2
Package
See Table 2-2.
2FFH
767
IA32_MTRR_DEF_TYPE
Thread
Default Memory Types (R/W)
See Table 2-2.
Vol. 4
2-151
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
309H
777
IA32_FIXED_CTR0
Thread
Fixed-Function Performance Counter Register 0 (R/W)
See Table 2-2.
30AH
778
IA32_FIXED_CTR1
Thread
Fixed-Function Performance Counter Register 1 (R/W)
See Table 2-2.
30BH
779
IA32_FIXED_CTR2
Thread
Fixed-Function Performance Counter Register 2 (R/W)
See Table 2-2.
345H
837
IA32_PERF_CAPABILITIES
Thread
See Table 2-2. See Section 18.4.1, “IA32_DEBUGCTL
MSR.”
5:0
LBR Format
See Table 2-2.
6
PEBS Record Format
7
PEBSSaveArchRegs
See Table 2-2.
11:8
PEBS_REC_FORMAT
See Table 2-2.
12
SMM_FREEZE
See Table 2-2.
63:13
Reserved
38DH
909
IA32_FIXED_CTR_CTRL
Thread
Fixed-Function-Counter Control Register (R/W)
See Table 2-2.
38EH
910
IA32_PERF_GLOBAL_STATUS
Thread
See Table 2-2. See Section 20.6.2.2, “Global Counter
Control Facilities.”
38EH
910
MSR_PERF_GLOBAL_STATUS
Thread
Provides single-bit status used by software to query
the overflow condition of each performance counter.
(R/O)
61
UNC_Ovf
Uncore overflowed if 1.
38FH
911
IA32_PERF_GLOBAL_CTRL
Thread
See Table 2-2. See Section 20.6.2.2, “Global Counter
Control Facilities.”
390H
912
IA32_PERF_GLOBAL_OVF_CTRL
Thread
See Table 2-2. See Section 20.6.2.2, “Global Counter
Control Facilities.” Allows software to clear counter
overflow conditions on any combination of fixed-
function PMCs (IA32_FIXED_CTRx) or general-purpose
PMCs via a single WRMSR.
390H
912
MSR_PERF_GLOBAL_OVF_CTRL
Thread
(R/W)
61
CLR_UNC_Ovf
Set 1 to clear UNC_Ovf.
3F1H
1009
IA32_PEBS_ENABLE
Thread
See Section 20.3.1.1.1, “Processor Event Based
Sampling (PEBS).”
(MSR_PEBS_ENABLE)
0
Enable PEBS on IA32_PMC0 (R/W)
1
Enable PEBS on IA32_PMC1 (R/W)
2-152 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
2
Enable PEBS on IA32_PMC2 (R/W)
3
Enable PEBS on IA32_PMC3 (R/W)
31:4
Reserved
32
Enable Load Latency on IA32_PMC0 (R/W)
33
Enable Load Latency on IA32_PMC1 (R/W)
34
Enable Load Latency on IA32_PMC2 (R/W)
35
Enable Load Latency on IA32_PMC3 (R/W)
63:36
Reserved
3F6H
1014
MSR_PEBS_LD_LAT
Thread
See Section 20.3.1.1.2, “Load Latency Performance
Monitoring Facility.”
15:0
Minimum threshold latency value of tagged load
operation that will be counted. (R/W)
63:36
Reserved
3F8H
1016
MSR_PKG_C3_RESIDENCY
Package
Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
63:0
Package C3 Residency Counter (R/O)
Value since last reset that this package is in processor-
specific C3 states. Count at the same frequency as the
TSC.
3F9H
1017
MSR_PKG_C6_RESIDENCY
Package
Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
63:0
Package C6 Residency Counter (R/O)
Value since last reset that this package is in processor-
specific C6 states. Count at the same frequency as the
TSC.
3FAH
1018
MSR_PKG_C7_RESIDENCY
Package
Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
63:0
Package C7 Residency Counter (R/O)
Value since last reset that this package is in processor-
specific C7 states. Count at the same frequency as the
TSC.
3FCH
1020
MSR_CORE_C3_RESIDENCY
Core
Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
63:0
CORE C3 Residency Counter (R/O)
Value since last reset that this core is in processor-
specific C3 states. Count at the same frequency as the
TSC.
3FDH
1021
MSR_CORE_C6_RESIDENCY
Core
Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
Vol. 4
2-153
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
63:0
CORE C6 Residency Counter (R/O)
Value since last reset that this core is in processor-
specific C6 states. Count at the same frequency as the
TSC.
400H
1024
IA32_MC0_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
401H
1025
IA32_MC0_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”
402H
1026
IA32_MC0_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC0_ADDR register is either not
implemented or contains no address if the ADDRV flag
in the IA32_MC0_STATUS register is clear.
When not implemented in the processor, all reads and
writes to this MSR will cause a general-protection
exception.
403H
1027
IA32_MC0_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
404H
1028
IA32_MC1_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
405H
1029
IA32_MC1_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”
406H
1030
IA32_MC1_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC1_ADDR register is either not
implemented or contains no address if the ADDRV flag
in the IA32_MC1_STATUS register is clear.
When not implemented in the processor, all reads and
writes to this MSR will cause a general-protection
exception.
407H
1031
IA32_MC1_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
408H
1032
IA32_MC2_CTL
Core
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
409H
1033
IA32_MC2_STATUS
Core
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”
40AH
1034
IA32_MC2_ADDR
Core
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC2_ADDR register is either not
implemented or contains no address if the ADDRV flag
in the IA32_MC2_STATUS register is clear.
When not implemented in the processor, all reads and
writes to this MSR will cause a general-protection
exception.
40BH
1035
IA32_MC2_MISC
Core
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
40CH
1036
IA32_MC3_CTL
Core
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
40DH
1037
IA32_MC3_STATUS
Core
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”
40EH
1038
IA32_MC3_ADDR
Core
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC4_ADDR register is either not
implemented or contains no address if the ADDRV flag
in the MSR_MC4_STATUS register is clear.
When not implemented in the processor, all reads and
writes to this MSR will cause a general-protection
exception.
40FH
1039
IA32_MC3_MISC
Core
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
2-154 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
410H
1040
IA32_MC4_CTL
Core
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
411H
1041
IA32_MC4_STATUS
Core
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”
412H
1042
IA32_MC4_ADDR
Core
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC3_ADDR register is either not
implemented or contains no address if the ADDRV flag
in the MSR_MC3_STATUS register is clear.
When not implemented in the processor, all reads and
writes to this MSR will cause a general-protection
exception.
413H
1043
IA32_MC4_MISC
Core
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
414H
1044
IA32_MC5_CTL
Core
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
415H
1045
IA32_MC5_STATUS
Core
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”
416H
1046
IA32_MC5_ADDR
Core
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
417H
1047
IA32_MC5_MISC
Core
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
418H
1048
IA32_MC6_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
419H
1049
IA32_MC6_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
41AH
1050
IA32_MC6_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
41BH
1051
IA32_MC6_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
41CH
1052
IA32_MC7_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
41DH
1053
IA32_MC7_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
41EH
1054
IA32_MC7_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
41FH
1055
IA32_MC7_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
420H
1056
IA32_MC8_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
421H
1057
IA32_MC8_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
422H
1058
IA32_MC8_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
423H
1059
IA32_MC8_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
480H
1152
IA32_VMX_BASIC
Thread
Reporting Register of Basic VMX Capabilities (R/O)
See Table 2-2.
See Appendix A.1, “Basic VMX Information.”
481H
1153
IA32_VMX_PINBASED_CTLS
Thread
Capability Reporting Register of Pin-based
VM-execution Controls (R/O)
See Table 2-2.
See Appendix A.3, “VM-Execution Controls.”
482H
1154
IA32_VMX_PROCBASED_CTLS
Thread
Capability Reporting Register of Primary Processor-
Based VM-Execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”
Vol. 4
2-155
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
483H
1155
IA32_VMX_EXIT_CTLS
Thread
Capability Reporting Register of VM-Exit Controls (R/O)
See Table 2-2.
See Appendix A.4, “VM-Exit Controls.”
484H
1156
IA32_VMX_ENTRY_CTLS
Thread
Capability Reporting Register of VM-Entry Controls
(R/O)
See Table 2-2.
See Appendix A.5, “VM-Entry Controls.”
485H
1157
IA32_VMX_MISC
Thread
Reporting Register of Miscellaneous VMX Capabilities
(R/O)
See Table 2-2.
See Appendix A.6, “Miscellaneous Data.”
486H
1158
IA32_VMX_CR0_FIXED0
Thread
Capability Reporting Register of CR0 Bits Fixed to 0
(R/O)
See Table 2-2.
See Appendix A.7, “VMX-Fixed Bits in CR0.”
487H
1159
IA32_VMX_CR0_FIXED1
Thread
Capability Reporting Register of CR0 Bits Fixed to 1
(R/O)
See Table 2-2.
See Appendix A.7, “VMX-Fixed Bits in CR0.”
488H
1160
IA32_VMX_CR4_FIXED0
Thread
Capability Reporting Register of CR4 Bits Fixed to 0
(R/O)
See Table 2-2.
See Appendix A.8, “VMX-Fixed Bits in CR4.”
489H
1161
IA32_VMX_CR4_FIXED1
Thread
Capability Reporting Register of CR4 Bits Fixed to 1
(R/O)
See Table 2-2.
See Appendix A.8, “VMX-Fixed Bits in CR4.”
48AH
1162
IA32_VMX_VMCS_ENUM
Thread
Capability Reporting Register of VMCS Field
Enumeration (R/O)
See Table 2-2.
See Appendix A.9, “VMCS Enumeration.”
48BH
1163
IA32_VMX_PROCBASED_CTLS2
Thread
Capability Reporting Register of Secondary Processor-
Based VM-Execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”
600H
1536
IA32_DS_AREA
Thread
DS Save Area (R/W)
See Table 2-2.
See Section 20.6.3.4, “Debug Store (DS) Mechanism.”
2-156 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
680H
1664
MSR_LASTBRANCH_0_FROM_IP
Thread
Last Branch Record 0 From IP (R/W)
One of sixteen pairs of last branch record registers on
the last branch record stack. The From_IP part of the
stack contains pointers to the source instruction. See
also:
• Last Branch Record Stack TOS at 1C9H.
• Section 18.9.1 and record format in Section 18.4.8.1.
681H
1665
MSR_LASTBRANCH_1_FROM_IP
Thread
Last Branch Record 1 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
682H
1666
MSR_LASTBRANCH_2_FROM_IP
Thread
Last Branch Record 2 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
683H
1667
MSR_LASTBRANCH_3_FROM_IP
Thread
Last Branch Record 3 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
684H
1668
MSR_LASTBRANCH_4_FROM_IP
Thread
Last Branch Record 4 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
685H
1669
MSR_LASTBRANCH_5_FROM_IP
Thread
Last Branch Record 5 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
686H
1670
MSR_LASTBRANCH_6_FROM_IP
Thread
Last Branch Record 6 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
687H
1671
MSR_LASTBRANCH_7_FROM_IP
Thread
Last Branch Record 7 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
688H
1672
MSR_LASTBRANCH_8_FROM_IP
Thread
Last Branch Record 8 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
689H
1673
MSR_LASTBRANCH_9_FROM_IP
Thread
Last Branch Record 9 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
68AH
1674
MSR_LASTBRANCH_10_FROM_IP
Thread
Last Branch Record 10 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
68BH
1675
MSR_LASTBRANCH_11_FROM_IP
Thread
Last Branch Record 11 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
68CH
1676
MSR_LASTBRANCH_12_FROM_IP
Thread
Last Branch Record 12 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
68DH
1677
MSR_LASTBRANCH_13_FROM_IP
Thread
Last Branch Record 13 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
68EH
1678
MSR_LASTBRANCH_14_FROM_IP
Thread
Last Branch Record 14 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
68FH
1679
MSR_LASTBRANCH_15_FROM_IP
Thread
Last Branch Record 15 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
6C0H
1728
MSR_LASTBRANCH_0_TO_IP
Thread
Last Branch Record 0 To IP (R/W)
One of sixteen pairs of last branch record registers on
the last branch record stack. This part of the stack
contains pointers to the destination instruction.
Vol. 4
2-157
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
6C1H
1729
MSR_LASTBRANCH_1_TO_IP
Thread
Last Branch Record 1 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C2H
1730
MSR_LASTBRANCH_2_TO_IP
Thread
Last Branch Record 2 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C3H
1731
MSR_LASTBRANCH_3_TO_IP
Thread
Last Branch Record 3 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C4H
1732
MSR_LASTBRANCH_4_TO_IP
Thread
Last Branch Record 4 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C5H
1733
MSR_LASTBRANCH_5_TO_IP
Thread
Last Branch Record 5 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C6H
1734
MSR_LASTBRANCH_6_TO_IP
Thread
Last Branch Record 6 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C7H
1735
MSR_LASTBRANCH_7_TO_IP
Thread
Last Branch Record 7 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C8H
1736
MSR_LASTBRANCH_8_TO_IP
Thread
Last Branch Record 8 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C9H
1737
MSR_LASTBRANCH_9_TO_IP
Thread
Last Branch Record 9 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6CAH
1738
MSR_LASTBRANCH_10_TO_IP
Thread
Last Branch Record 10 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6CBH
1739
MSR_LASTBRANCH_11_TO_IP
Thread
Last Branch Record 11 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6CCH
1740
MSR_LASTBRANCH_12_TO_IP
Thread
Last Branch Record 12 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6CDH
1741
MSR_LASTBRANCH_13_TO_IP
Thread
Last Branch Record 13 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6CEH
1742
MSR_LASTBRANCH_14_TO_IP
Thread
Last Branch Record 14 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6CFH
1743
MSR_LASTBRANCH_15_TO_IP
Thread
Last Branch Record 15 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
802H
2050
IA32_X2APIC_APICID
Thread
x2APIC ID Register (R/O)
803H
2051
IA32_X2APIC_VERSION
Thread
x2APIC Version Register (R/O)
808H
2056
IA32_X2APIC_TPR
Thread
x2APIC Task Priority Register (R/W)
80AH
2058
IA32_X2APIC_PPR
Thread
x2APIC Processor Priority Register (R/O)
80BH
2059
IA32_X2APIC_EOI
Thread
x2APIC EOI Register (W/O)
80DH
2061
IA32_X2APIC_LDR
Thread
x2APIC Logical Destination Register (R/O)
80FH
2063
IA32_X2APIC_SIVR
Thread
x2APIC Spurious Interrupt Vector Register (R/W)
810H
2064
IA32_X2APIC_ISR0
Thread
x2APIC In-Service Register Bits [31:0] (R/O)
811H
2065
IA32_X2APIC_ISR1
Thread
x2APIC In-Service Register Bits [63:32] (R/O)
2-158 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
812H
2066
IA32_X2APIC_ISR2
Thread
x2APIC In-Service Register Bits [95:64] (R/O)
813H
2067
IA32_X2APIC_ISR3
Thread
x2APIC In-Service Register Bits [127:96] (R/O)
814H
2068
IA32_X2APIC_ISR4
Thread
x2APIC In-Service Register Bits [159:128] (R/O)
815H
2069
IA32_X2APIC_ISR5
Thread
x2APIC In-Service Register Bits [191:160] (R/O)
816H
2070
IA32_X2APIC_ISR6
Thread
x2APIC In-Service Register Bits [223:192] (R/O)
817H
2071
IA32_X2APIC_ISR7
Thread
x2APIC In-Service Register Bits [255:224] (R/O)
818H
2072
IA32_X2APIC_TMR0
Thread
x2APIC Trigger Mode Register Bits [31:0] (R/O)
819H
2073
IA32_X2APIC_TMR1
Thread
x2APIC Trigger Mode Register Bits [63:32] (R/O)
81AH
2074
IA32_X2APIC_TMR2
Thread
x2APIC Trigger Mode Register Bits [95:64] (R/O)
81BH
2075
IA32_X2APIC_TMR3
Thread
x2APIC Trigger Mode Register Bits [127:96] (R/O)
81CH
2076
IA32_X2APIC_TMR4
Thread
x2APIC Trigger Mode Register Bits [159:128] (R/O)
81DH
2077
IA32_X2APIC_TMR5
Thread
x2APIC Trigger Mode Register Bits [191:160] (R/O)
81EH
2078
IA32_X2APIC_TMR6
Thread
x2APIC Trigger Mode Register Bits [223:192] (R/O)
81FH
2079
IA32_X2APIC_TMR7
Thread
x2APIC Trigger Mode Register Bits [255:224] (R/O)
820H
2080
IA32_X2APIC_IRR0
Thread
x2APIC Interrupt Request Register Bits [31:0] (R/O)
821H
2081
IA32_X2APIC_IRR1
Thread
x2APIC Interrupt Request Register Bits [63:32] (R/O)
822H
2082
IA32_X2APIC_IRR2
Thread
x2APIC Interrupt Request Register Bits [95:64] (R/O)
823H
2083
IA32_X2APIC_IRR3
Thread
x2APIC Interrupt Request Register Bits [127:96] (R/O)
824H
2084
IA32_X2APIC_IRR4
Thread
x2APIC Interrupt Request Register Bits [159:128] (R/O)
825H
2085
IA32_X2APIC_IRR5
Thread
x2APIC Interrupt Request Register Bits [191:160] (R/O)
826H
2086
IA32_X2APIC_IRR6
Thread
x2APIC Interrupt Request Register Bits [223:192] (R/O)
827H
2087
IA32_X2APIC_IRR7
Thread
x2APIC Interrupt Request Register Bits [255:224] (R/O)
828H
2088
IA32_X2APIC_ESR
Thread
x2APIC Error Status Register (R/W)
82FH
2095
IA32_X2APIC_LVT_CMCI
Thread
x2APIC LVT Corrected Machine Check Interrupt Register
(R/W)
830H
2096
IA32_X2APIC_ICR
Thread
x2APIC Interrupt Command Register (R/W)
832H
2098
IA32_X2APIC_LVT_TIMER
Thread
x2APIC LVT Timer Interrupt Register (R/W)
833H
2099
IA32_X2APIC_LVT_THERMAL
Thread
x2APIC LVT Thermal Sensor Interrupt Register (R/W)
834H
2100
IA32_X2APIC_LVT_PMI
Thread
x2APIC LVT Performance Monitor Register (R/W)
835H
2101
IA32_X2APIC_LVT_LINT0
Thread
x2APIC LVT LINT0 Register (R/W)
836H
2102
IA32_X2APIC_LVT_LINT1
Thread
x2APIC LVT LINT1 Register (R/W)
837H
2103
IA32_X2APIC_LVT_ERROR
Thread
x2APIC LVT Error Register (R/W)
838H
2104
IA32_X2APIC_INIT_COUNT
Thread
x2APIC Initial Count Register (R/W)
839H
2105
IA32_X2APIC_CUR_COUNT
Thread
x2APIC Current Count Register (R/O)
83EH
2110
IA32_X2APIC_DIV_CONF
Thread
x2APIC Divide Configuration Register (R/W)
83FH
2111
IA32_X2APIC_SELF_IPI
Thread
x2APIC Self IPI Register (W/O)
Vol. 4
2-159
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
C000_
IA32_EFER
Thread
Extended Feature Enables
0080H
See Table 2-2.
C000_
IA32_STAR
Thread
System Call Target Address (R/W)
0081H
See Table 2-2.
C000_
IA32_LSTAR
Thread
IA-32e Mode System Call Target Address (R/W)
0082H
See Table 2-2.
C000_
IA32_FMASK
Thread
System Call Flag Mask (R/W)
0084H
See Table 2-2.
C000_
IA32_FS_BASE
Thread
Map of BASE Address of FS (R/W)
0100H
See Table 2-2.
C000_
IA32_GS_BASE
Thread
Map of BASE Address of GS (R/W)
0101H
See Table 2-2.
C000_
IA32_KERNEL_GS_BASE
Thread
Swap Target of BASE Address of GS (R/W)
0102H
See Table 2-2.
C000_
IA32_TSC_AUX
Thread
AUXILIARY TSC Signature (R/W)
0103H
See Table 2-2 and Section 18.17.2, “IA32_TSC_AUX
Register and RDTSCP Support.”
2.8.1
Additional MSRs in the Intel® Xeon® Processor 5500 and 3400 Series
The Intel Xeon Processor 5500 and 3400 series supports additional model-specific registers listed in Table 2-16.
These MSRs also apply to the Intel Core i7 and i5 processor family with a CPUID Signature
DisplayFamily_DisplayModel value of 06_1AH, 06_1EH, or 06_1FH; see Table 2-1.
Table 2-16. Additional MSRs in the Intel® Xeon® Processor 5500 and 3400 Series
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
1ADH
429
MSR_TURBO_RATIO_LIMIT
Package
Actual maximum turbo frequency is multiplied by
133.33MHz.
(Not available in model 06_2EH.)
7:0
Maximum Turbo Ratio Limit 1C (R/O)
Maximum Turbo mode ratio limit with 1 core active.
15:8
Maximum Turbo Ratio Limit 2C (R/O)
Maximum Turbo mode ratio limit with 2 cores active.
23:16
Maximum Turbo Ratio Limit 3C (R/O)
Maximum Turbo mode ratio limit with 3 cores active.
31:24
Maximum Turbo Ratio Limit 4C (R/O)
Maximum Turbo mode ratio limit with 4 cores active.
63:32
Reserved
301H
769
MSR_GQ_SNOOP_MESF
Package
2-160 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-16. Additional MSRs in the Intel® Xeon® Processor 5500 and 3400 Series (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
0
From M to S (R/W)
1
From E to S (R/W)
2
From S to S (R/W)
3
From F to S (R/W)
4
From M to I (R/W)
5
From E to I (R/W)
6
From S to I (R/W)
7
From F to I (R/W)
63:8
Reserved
391H
913
MSR_UNCORE_PERF_GLOBAL_CTRL
Package
See Section 20.3.1.2.1, “Uncore Performance
Monitoring Management Facility.”
392H
914
MSR_UNCORE_PERF_GLOBAL_STATUS
Package
See Section 20.3.1.2.1, “Uncore Performance
Monitoring Management Facility.”
393H
915
MSR_UNCORE_PERF_GLOBAL_OVF_CTRL
Package
See Section 20.3.1.2.1, “Uncore Performance
Monitoring Management Facility.”
394H
916
MSR_UNCORE_FIXED_CTR0
Package
See Section 20.3.1.2.1, “Uncore Performance
Monitoring Management Facility.”
395H
917
MSR_UNCORE_FIXED_CTR_CTRL
Package
See Section 20.3.1.2.1, “Uncore Performance
Monitoring Management Facility.”
396H
918
MSR_UNCORE_ADDR_OPCODE_MATCH
Package
See Section 20.3.1.2.3, “Uncore Address/Opcode
Match MSR.”
3B0H
960
MSR_UNCORE_PMC0
Package
See Section 20.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
3B1H
961
MSR_UNCORE_PMC1
Package
See Section 20.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
3B2H
962
MSR_UNCORE_PMC2
Package
See Section 20.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
3B3H
963
MSR_UNCORE_PMC3
Package
See Section 20.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
3B4H
964
MSR_UNCORE_PMC4
Package
See Section 20.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
3B5H
965
MSR_UNCORE_PMC5
Package
See Section 20.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
3B6H
966
MSR_UNCORE_PMC6
Package
See Section 20.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
3B7H
967
MSR_UNCORE_PMC7
Package
See Section 20.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
3C0H
944
MSR_UNCORE_PERFEVTSEL0
Package
See Section 20.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
3C1H
945
MSR_UNCORE_PERFEVTSEL1
Package
See Section 20.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
Vol. 4
2-161
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-16. Additional MSRs in the Intel® Xeon® Processor 5500 and 3400 Series (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
3C2H
946
MSR_UNCORE_PERFEVTSEL2
Package
See Section 20.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
3C3H
947
MSR_UNCORE_PERFEVTSEL3
Package
See Section 20.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
3C4H
948
MSR_UNCORE_PERFEVTSEL4
Package
See Section 20.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
3C5H
949
MSR_UNCORE_PERFEVTSEL5
Package
See Section 20.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
3C6H
950
MSR_UNCORE_PERFEVTSEL6
Package
See Section 20.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
3C7H
951
MSR_UNCORE_PERFEVTSEL7
Package
See Section 20.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
2.8.2
Additional MSRs in the Intel® Xeon® Processor 7500 Series
The Intel Xeon Processor 7500 series supports MSRs listed in Table 2-15 (except MSR address 1ADH) and additional
model-specific registers listed in Table 2-17. These processors have a CPUID Signature
DisplayFamily_DisplayModel value of 06_2EH.
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
1ADH
429
MSR_TURBO_RATIO_LIMIT
Package
Reserved
Attempt to read/write will cause #UD.
289H
649
IA32_MC9_CTL2
Package
See Table 2-2.
28AH
650
IA32_MC10_CTL2
Package
See Table 2-2.
28BH
651
IA32_MC11_CTL2
Package
See Table 2-2.
28CH
652
IA32_MC12_CTL2
Package
See Table 2-2.
28DH
653
IA32_MC13_CTL2
Package
See Table 2-2.
28EH
654
IA32_MC14_CTL2
Package
See Table 2-2.
28FH
655
IA32_MC15_CTL2
Package
See Table 2-2.
290H
656
IA32_MC16_CTL2
Package
See Table 2-2.
291H
657
IA32_MC17_CTL2
Package
See Table 2-2.
292H
658
IA32_MC18_CTL2
Package
See Table 2-2.
293H
659
IA32_MC19_CTL2
Package
See Table 2-2.
294H
660
IA32_MC20_CTL2
Package
See Table 2-2.
295H
661
IA32_MC21_CTL2
Package
See Table 2-2.
394H
816
MSR_W_PMON_FIXED_CTR
Package
Uncore W-box perfmon fixed counter.
395H
817
MSR_W_PMON_FIXED_CTR_CTL
Package
Uncore U-box perfmon fixed counter control MSR.
424H
1060
IA32_MC9_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
2-162 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
425H
1061
IA32_MC9_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
426H
1062
IA32_MC9_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
427H
1063
IA32_MC9_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
428H
1064
IA32_MC10_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
429H
1065
IA32_MC10_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
42AH
1066
IA32_MC10_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
42BH
1067
IA32_MC10_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
42CH
1068
IA32_MC11_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
42DH
1069
IA32_MC11_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
42EH
1070
IA32_MC11_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
42FH
1071
IA32_MC11_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
430H
1072
IA32_MC12_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
431H
1073
IA32_MC12_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
432H
1074
IA32_MC12_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
433H
1075
IA32_MC12_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
434H
1076
IA32_MC13_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
435H
1077
IA32_MC13_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
436H
1078
IA32_MC13_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
437H
1079
IA32_MC13_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
438H
1080
IA32_MC14_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
439H
1081
IA32_MC14_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
43AH
1082
IA32_MC14_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
43BH
1083
IA32_MC14_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
43CH
1084
IA32_MC15_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
43DH
1085
IA32_MC15_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
43EH
1086
IA32_MC15_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
43FH
1087
IA32_MC15_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
440H
1088
IA32_MC16_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
441H
1089
IA32_MC16_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
442H
1090
IA32_MC16_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
443H
1091
IA32_MC16_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Vol. 4
2-163
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
444H
1092
IA32_MC17_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
445H
1093
IA32_MC17_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
446H
1094
IA32_MC17_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
447H
1095
IA32_MC17_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
448H
1096
IA32_MC18_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
449H
1097
IA32_MC18_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
44AH
1098
IA32_MC18_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
44BH
1099
IA32_MC18_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
44CH
1100
IA32_MC19_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
44DH
1101
IA32_MC19_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
44EH
1102
IA32_MC19_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
44FH
1103
IA32_MC19_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
450H
1104
IA32_MC20_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
451H
1105
IA32_MC20_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
452H
1106
IA32_MC20_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
453H
1107
IA32_MC20_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
454H
1108
IA32_MC21_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
455H
1109
IA32_MC21_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
456H
1110
IA32_MC21_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
457H
1111
IA32_MC21_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
C00H
3072
MSR_U_PMON_GLOBAL_CTRL
Package
Uncore U-box perfmon global control MSR.
C01H
3073
MSR_U_PMON_GLOBAL_STATUS
Package
Uncore U-box perfmon global status MSR.
C02H
3074
MSR_U_PMON_GLOBAL_OVF_CTRL
Package
Uncore U-box perfmon global overflow control MSR.
C10H
3088
MSR_U_PMON_EVNT_SEL
Package
Uncore U-box perfmon event select MSR.
C11H
3089
MSR_U_PMON_CTR
Package
Uncore U-box perfmon counter MSR.
C20H
3104
MSR_B0_PMON_BOX_CTRL
Package
Uncore B-box 0 perfmon local box control MSR.
C21H
3105
MSR_B0_PMON_BOX_STATUS
Package
Uncore B-box 0 perfmon local box status MSR.
C22H
3106
MSR_B0_PMON_BOX_OVF_CTRL
Package
Uncore B-box 0 perfmon local box overflow control
MSR.
C30H
3120
MSR_B0_PMON_EVNT_SEL0
Package
Uncore B-box 0 perfmon event select MSR.
2-164 Vol. 4