Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 103
INSTRUCTION SET REFERENCE, V
VPMADD52HUQ—Packed Multiply of Unsigned 52-Bit Unsigned Integers and Add High 52-Bit
Products to 64-Bit Accumulators
Opcode/
Op/
32/64
CPUID
Description
Instruction
En
bit Mode
Support
EVEX.128.66.0F38.W1 B5 /r
A
V/V
AVX512_IFMA
Multiply unsigned 52-bit integers in xmm2 and
VPMADD52HUQ xmm1 {k1}{z}, xmm2,
AVX512VL
xmm3/m128 and add the high 52 bits of the 104-
xmm3/m128/m64bcst
bit product to the qword unsigned integers in
xmm1 using writemask k1.
EVEX.256.66.0F38.W1 B5 /r
A
V/V
AVX512_IFMA
Multiply unsigned 52-bit integers in ymm2 and
VPMADD52HUQ ymm1 {k1}{z}, ymm2,
AVX512VL
ymm3/m256 and add the high 52 bits of the 104-
ymm3/m256/m64bcst
bit product to the qword unsigned integers in
ymm1 using writemask k1.
EVEX.512.66.0F38.W1 B5 /r
A
V/V
AVX512_IFMA
Multiply unsigned 52-bit integers in zmm2 and
VPMADD52HUQ zmm1 {k1}{z}, zmm2,
zmm3/m512 and add the high 52 bits of the 104-
zmm3/m512/m64bcst
bit product to the qword unsigned integers in
zmm1 using writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m(r)
N/A
Description
Multiplies packed unsigned 52-bit integers in each qword element of the first source operand (the second oper-
and) with the packed unsigned 52-bit integers in the corresponding elements of the second source operand (the
third operand) to form packed 104-bit intermediate results. The high 52-bit, unsigned integer of each 104-bit
product is added to the corresponding qword unsigned integer of the destination operand (the first operand)
under the writemask k1.
The first source operand is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM reg-
ister, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-bit memory loca-
tion. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1 at 64-bit
granularity.
VPMADD52HUQ—Packed Multiply of Unsigned 52-Bit Unsigned Integers and Add High 52-Bit Products to 64-Bit Accumulators
Vol. 2C
5-527
INSTRUCTION SET REFERENCE, V
Operation
VPMADD52HUQ (EVEX encoded)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64;
IF k1[j] OR *no writemask* THEN
IF src2 is Memory AND EVEX.b=1 THEN
tsrc2[63:0] := ZeroExtend64(src2[51:0]);
ELSE
tsrc2[63:0] := ZeroExtend64(src2[i+51:i];
FI;
Temp128[127:0] := ZeroExtend64(src1[i+51:i]) * tsrc2[63:0];
Temp2[63:0] := DEST[i+63:i] + ZeroExtend64(temp128[103:52]) ;
DEST[i+63:i] := Temp2[63:0];
ELSE
IF *zeroing-masking* THEN
DEST[i+63:i] := 0;
ELSE *merge-masking*
DEST[i+63:i] is unchanged;
FI;
FI;
ENDFOR
DEST[MAX_VL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPMADD52HUQ __m512i _mm512_madd52hi_epu64( __m512i a, __m512i b, __m512i c);
VPMADD52HUQ __m512i _mm512_mask_madd52hi_epu64(__m512i s, __mmask8 k, __m512i a, __m512i b, __m512i c);
VPMADD52HUQ __m512i _mm512_maskz_madd52hi_epu64( __mmask8 k, __m512i a, __m512i b, __m512i c);
VPMADD52HUQ __m256i _mm256_madd52hi_epu64( __m256i a, __m256i b, __m256i c);
VPMADD52HUQ __m256i _mm256_mask_madd52hi_epu64(__m256i s, __mmask8 k, __m256i a, __m256i b, __m256i c);
VPMADD52HUQ __m256i _mm256_maskz_madd52hi_epu64( __mmask8 k, __m256i a, __m256i b, __m256i c);
VPMADD52HUQ __m128i _mm_madd52hi_epu64( __m128i a, __m128i b, __m128i c);
VPMADD52HUQ __m128i _mm_mask_madd52hi_epu64(__m128i s, __mmask8 k, __m128i a, __m128i b, __m128i c);
VPMADD52HUQ __m128i _mm_maskz_madd52hi_epu64( __mmask8 k, __m128i a, __m128i b, __m128i c);
Flags Affected
None.
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-49, “Type E4 Class Exception Conditions.”
VPMADD52HUQ—Packed Multiply of Unsigned 52-Bit Unsigned Integers and Add High 52-Bit Products to 64-Bit Accumulators
5-528
Vol. 2C
INSTRUCTION SET REFERENCE, V
VPMADD52LUQ—Packed Multiply of Unsigned 52-Bit Integers and Add the Low 52-Bit Products
to Qword Accumulators
Opcode/
Op/En
32/64
CPUID
Description
Instruction
bit Mode
Support
EVEX.128.66.0F38.W1 B4 /r
A
V/V
AVX512_IFMA
Multiply unsigned 52-bit integers in xmm2 and
VPMADD52LUQ xmm1 {k1}{z},
AVX512VL
xmm3/m128 and add the low 52 bits of the 104-bit
xmm2,xmm3/m128/m64bcst
product to the qword unsigned integers in xmm1
using writemask k1.
EVEX.256.66.0F38.W1 B4 /r
A
V/V
AVX512_IFMA
Multiply unsigned 52-bit integers in ymm2 and
VPMADD52LUQ ymm1 {k1}{z},
AVX512VL
ymm3/m256 and add the low 52 bits of the 104-bit
ymm2, ymm3/m256/m64bcst
product to the qword unsigned integers in ymm1
using writemask k1.
EVEX.512.66.0F38.W1 B4 /r
A
V/V
AVX512_IFMA
Multiply unsigned 52-bit integers in zmm2 and
VPMADD52LUQ zmm1 {k1}{z},
zmm3/m512 and add the low 52 bits of the 104-bit
zmm2,zmm3/m512/m64bcst
product to the qword unsigned integers in zmm1
using writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m(r)
N/A
Description
Multiplies packed unsigned 52-bit integers in each qword element of the first source operand (the second oper-
and) with the packed unsigned 52-bit integers in the corresponding elements of the second source operand (the
third operand) to form packed 104-bit intermediate results. The low 52-bit, unsigned integer of each 104-bit
product is added to the corresponding qword unsigned integer of the destination operand (the first operand)
under the writemask k1.
The first source operand is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM reg-
ister, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-bit memory loca-
tion. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1 at 64-bit
granularity.
VPMADD52LUQ—Packed Multiply of Unsigned 52-Bit Integers and Add the Low 52-Bit Products to Qword Accumulators
Vol. 2C
5-529
INSTRUCTION SET REFERENCE, V
Operation
VPMADD52LUQ (EVEX encoded)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64;
IF k1[j] OR *no writemask* THEN
IF src2 is Memory AND EVEX.b=1 THEN
tsrc2[63:0] := ZeroExtend64(src2[51:0]);
ELSE
tsrc2[63:0] := ZeroExtend64(src2[i+51:i];
FI;
Temp128[127:0] := ZeroExtend64(src1[i+51:i]) * tsrc2[63:0];
Temp2[63:0] := DEST[i+63:i] + ZeroExtend64(temp128[51:0]) ;
DEST[i+63:i] := Temp2[63:0];
ELSE
IF *zeroing-masking* THEN
DEST[i+63:i] := 0;
ELSE *merge-masking*
DEST[i+63:i] is unchanged;
FI;
FI;
ENDFOR
DEST[MAX_VL-1:VL] := 0;
Intel C/C++ Compiler Intrinsic Equivalent
VPMADD52LUQ __m512i _mm512_madd52lo_epu64( __m512i a, __m512i b, __m512i c);
VPMADD52LUQ __m512i _mm512_mask_madd52lo_epu64(__m512i s, __mmask8 k, __m512i a, __m512i b, __m512i c);
VPMADD52LUQ __m512i _mm512_maskz_madd52lo_epu64( __mmask8 k, __m512i a, __m512i b, __m512i c);
VPMADD52LUQ __m256i _mm256_madd52lo_epu64( __m256i a, __m256i b, __m256i c);
VPMADD52LUQ __m256i _mm256_mask_madd52lo_epu64(__m256i s, __mmask8 k, __m256i a, __m256i b, __m256i c);
VPMADD52LUQ __m256i _mm256_maskz_madd52lo_epu64( __mmask8 k, __m256i a, __m256i b, __m256i c);
VPMADD52LUQ __m128i _mm_madd52lo_epu64( __m128i a, __m128i b, __m128i c);
VPMADD52LUQ __m128i _mm_mask_madd52lo_epu64(__m128i s, __mmask8 k, __m128i a, __m128i b, __m128i c);
VPMADD52LUQ __m128i _mm_maskz_madd52lo_epu64( __mmask8 k, __m128i a, __m128i b, __m128i c);
Flags Affected
None.
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-49, “Type E4 Class Exception Conditions.”
5-530
Vol. 2C
VPMADD52LUQ—Packed Multiply of Unsigned 52-Bit Integers and Add the Low 52-Bit Products to Qword Accumulators
INSTRUCTION SET REFERENCE, V
VPMASKMOV—Conditional SIMD Integer Packed Loads and Stores
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
-bit
Feature
Mode
Flag
VEX.128.66.0F38.W0 8C /r
RVM
V/V
AVX2
Conditionally load dword values from m128 using mask
VPMASKMOVD xmm1, xmm2, m128
in xmm2 and store in xmm1.
VEX.256.66.0F38.W0 8C /r
RVM
V/V
AVX2
Conditionally load dword values from m256 using mask
VPMASKMOVD ymm1, ymm2, m256
in ymm2 and store in ymm1.
VEX.128.66.0F38.W1 8C /r
RVM
V/V
AVX2
Conditionally load qword values from m128 using mask
VPMASKMOVQ xmm1, xmm2, m128
in xmm2 and store in xmm1.
VEX.256.66.0F38.W1 8C /r
RVM
V/V
AVX2
Conditionally load qword values from m256 using mask
VPMASKMOVQ ymm1, ymm2, m256
in ymm2 and store in ymm1.
VEX.128.66.0F38.W0 8E /r
MVR
V/V
AVX2
Conditionally store dword values from xmm2 using
VPMASKMOVD m128, xmm1, xmm2
mask in xmm1.
VEX.256.66.0F38.W0 8E /r
MVR
V/V
AVX2
Conditionally store dword values from ymm2 using
VPMASKMOVD m256, ymm1, ymm2
mask in ymm1.
VEX.128.66.0F38.W1 8E /r
MVR
V/V
AVX2
Conditionally store qword values from xmm2 using
VPMASKMOVQ m128, xmm1, xmm2
mask in xmm1.
VEX.256.66.0F38.W1 8E /r
MVR
V/V
AVX2
Conditionally store qword values from ymm2 using
VPMASKMOVQ m256, ymm1, ymm2
mask in ymm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
MVR
ModRM:r/m (w)
VEX.vvvv (r)
ModRM:reg (r)
N/A
Description
Conditionally moves packed data elements from the second source operand into the corresponding data element
of the destination operand, depending on the mask bits associated with each data element. The mask bits are
specified in the first source operand.
The mask bit for each data element is the most significant bit of that element in the first source operand. If a mask
is 1, the corresponding data element is copied from the second source operand to the destination operand. If the
mask is 0, the corresponding data element is set to zero in the load form of these instructions, and unmodified in
the store form.
The second source operand is a memory address for the load form of these instructions. The destination operand
is a memory address for the store form of these instructions. The other operands are either XMM registers (for
VEX.128 version) or YMM registers (for VEX.256 version).
Faults occur only due to mask-bit required memory accesses that caused the faults. Faults will not occur due to
referencing any memory location if the corresponding mask bit for that memory location is 0. For example, no
faults will be detected if the mask bits are all zero.
Unlike previous MASKMOV instructions (MASKMOVQ and MASKMOVDQU), a nontemporal hint is not applied to
these instructions.
Instruction behavior on alignment check reporting with mask bits of less than all 1s are the same as with mask bits
of all 1s.
VPMASKMOV—Conditional SIMD Integer Packed Loads and Stores
Vol. 2C
5-531
INSTRUCTION SET REFERENCE, V
VMASKMOV should not be used to access memory mapped I/O as the ordering of the individual loads or stores it
does is implementation specific.
In cases where mask bits indicate data should not be loaded or stored paging A and D bits will be set in an imple-
mentation dependent way. However, A and D bits are always set for pages where data is actually loaded/stored.
Note: for load forms, the first source (the mask) is encoded in VEX.vvvv; the second source is encoded in rm_field,
and the destination register is encoded in reg_field.
Note: for store forms, the first source (the mask) is encoded in VEX.vvvv; the second source register is encoded in
reg_field, and the destination memory location is encoded in rm_field.
Operation
VPMASKMOVD - 256-bit load
DEST[31:0] := IF (SRC1[31]) Load_32(mem) ELSE 0
DEST[63:32] := IF (SRC1[63]) Load_32(mem + 4) ELSE 0
DEST[95:64] := IF (SRC1[95]) Load_32(mem + 8) ELSE 0
DEST[127:96] := IF (SRC1[127]) Load_32(mem + 12) ELSE 0
DEST[159:128] := IF (SRC1[159]) Load_32(mem + 16) ELSE 0
DEST[191:160] := IF (SRC1[191]) Load_32(mem + 20) ELSE 0
DEST[223:192] := IF (SRC1[223]) Load_32(mem + 24) ELSE 0
DEST[255:224] := IF (SRC1[255]) Load_32(mem + 28) ELSE 0
VPMASKMOVD -128-bit load
DEST[31:0] := IF (SRC1[31]) Load_32(mem) ELSE 0
DEST[63:32] := IF (SRC1[63]) Load_32(mem + 4) ELSE 0
DEST[95:64] := IF (SRC1[95]) Load_32(mem + 8) ELSE 0
DEST[127:97] := IF (SRC1[127]) Load_32(mem + 12) ELSE 0
DEST[MAXVL-1:128] := 0
VPMASKMOVQ - 256-bit load
DEST[63:0] := IF (SRC1[63]) Load_64(mem) ELSE 0
DEST[127:64] := IF (SRC1[127]) Load_64(mem + 8) ELSE 0
DEST[195:128] := IF (SRC1[191]) Load_64(mem + 16) ELSE 0
DEST[255:196] := IF (SRC1[255]) Load_64(mem + 24) ELSE 0
VPMASKMOVQ - 128-bit load
DEST[63:0] := IF (SRC1[63]) Load_64(mem) ELSE 0
DEST[127:64] := IF (SRC1[127]) Load_64(mem + 16) ELSE 0
DEST[MAXVL-1:128] := 0
VPMASKMOVD - 256-bit store
IF (SRC1[31]) DEST[31:0] := SRC2[31:0]
IF (SRC1[63]) DEST[63:32] := SRC2[63:32]
IF (SRC1[95]) DEST[95:64] := SRC2[95:64]
IF (SRC1[127]) DEST[127:96] := SRC2[127:96]
IF (SRC1[159]) DEST[159:128] :=SRC2[159:128]
IF (SRC1[191]) DEST[191:160] := SRC2[191:160]
IF (SRC1[223]) DEST[223:192] := SRC2[223:192]
IF (SRC1[255]) DEST[255:224] := SRC2[255:224]
5-532
Vol. 2C
VPMASKMOV—Conditional SIMD Integer Packed Loads and Stores
INSTRUCTION SET REFERENCE, V
VPMASKMOVD - 128-bit store
IF (SRC1[31]) DEST[31:0] := SRC2[31:0]
IF (SRC1[63]) DEST[63:32] := SRC2[63:32]
IF (SRC1[95]) DEST[95:64] := SRC2[95:64]
IF (SRC1[127]) DEST[127:96] := SRC2[127:96]
VPMASKMOVQ - 256-bit store
IF (SRC1[63]) DEST[63:0] := SRC2[63:0]
IF (SRC1[127]) DEST[127:64] :=SRC2[127:64]
IF (SRC1[191]) DEST[191:128] := SRC2[191:128]
IF (SRC1[255]) DEST[255:192] := SRC2[255:192]
VPMASKMOVQ - 128-bit store
IF (SRC1[63]) DEST[63:0] := SRC2[63:0]
IF (SRC1[127]) DEST[127:64] :=SRC2[127:64]
Intel C/C++ Compiler Intrinsic Equivalent
VPMASKMOVD: __m256i _mm256_maskload_epi32(int const *a, __m256i mask)
VPMASKMOVD: void
_mm256_maskstore_epi32(int *a, __m256i mask, __m256i b)
VPMASKMOVQ: __m256i _mm256_maskload_epi64(__int64 const *a, __m256i mask);
VPMASKMOVQ: void
_mm256_maskstore_epi64(__int64 *a, __m256i mask, __m256d b);
VPMASKMOVD: __m128i _mm_maskload_epi32(int const *a, __m128i mask)
VPMASKMOVD: void
_mm_maskstore_epi32(int *a, __m128i mask, __m128 b)
VPMASKMOVQ: __m128i _mm_maskload_epi64(__int cont *a, __m128i mask);
VPMASKMOVQ: void
_mm_maskstore_epi64(__int64 *a, __m128i mask, __m128i b);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-23, “Type 6 Class Exception Conditions” (No AC# reported for any mask bit combinations).
VPMASKMOV—Conditional SIMD Integer Packed Loads and Stores
Vol. 2C
5-533
INSTRUCTION SET REFERENCE, V
VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M—Convert a Vector Register to a Mask
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.F3.0F38.W0 29 /r
RM
V/V
AVX512VL
Sets each bit in k1 to 1 or 0 based on the value of the most
VPMOVB2M k1, xmm1
AVX512BW
significant bit of the corresponding byte in XMM1.
EVEX.256.F3.0F38.W0 29 /r
RM
V/V
AVX512VL
Sets each bit in k1 to 1 or 0 based on the value of the most
VPMOVB2M k1, ymm1
AVX512BW
significant bit of the corresponding byte in YMM1.
EVEX.512.F3.0F38.W0 29 /r
RM
V/V
AVX512BW
Sets each bit in k1 to 1 or 0 based on the value of the most
VPMOVB2M k1, zmm1
significant bit of the corresponding byte in ZMM1.
EVEX.128.F3.0F38.W1 29 /r
RM
V/V
AVX512VL
Sets each bit in k1 to 1 or 0 based on the value of the most
VPMOVW2M k1, xmm1
AVX512BW
significant bit of the corresponding word in XMM1.
EVEX.256.F3.0F38.W1 29 /r
RM
V/V
AVX512VL
Sets each bit in k1 to 1 or 0 based on the value of the most
VPMOVW2M k1, ymm1
AVX512BW
significant bit of the corresponding word in YMM1.
EVEX.512.F3.0F38.W1 29 /r
RM
V/V
AVX512BW
Sets each bit in k1 to 1 or 0 based on the value of the most
VPMOVW2M k1, zmm1
significant bit of the corresponding word in ZMM1.
EVEX.128.F3.0F38.W0 39 /r
RM
V/V
AVX512VL
Sets each bit in k1 to 1 or 0 based on the value of the most
VPMOVD2M k1, xmm1
AVX512DQ
significant bit of the corresponding doubleword in XMM1.
EVEX.256.F3.0F38.W0 39 /r
RM
V/V
AVX512VL
Sets each bit in k1 to 1 or 0 based on the value of the most
VPMOVD2M k1, ymm1
AVX512DQ
significant bit of the corresponding doubleword in YMM1.
EVEX.512.F3.0F38.W0 39 /r
RM
V/V
AVX512DQ
Sets each bit in k1 to 1 or 0 based on the value of the most
VPMOVD2M k1, zmm1
significant bit of the corresponding doubleword in ZMM1.
EVEX.128.F3.0F38.W1 39 /r
RM
V/V
AVX512VL
Sets each bit in k1 to 1 or 0 based on the value of the most
VPMOVQ2M k1, xmm1
AVX512DQ
significant bit of the corresponding quadword in XMM1.
EVEX.256.F3.0F38.W1 39 /r
RM
V/V
AVX512VL
Sets each bit in k1 to 1 or 0 based on the value of the most
VPMOVQ2M k1, ymm1
AVX512DQ
significant bit of the corresponding quadword in YMM1.
EVEX.512.F3.0F38.W1 39 /r
RM
V/V
AVX512DQ
Sets each bit in k1 to 1 or 0 based on the value of the most
VPMOVQ2M k1, zmm1
significant bit of the corresponding quadword in ZMM1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts a vector register to a mask register. Each element in the destination register is set to 1 or 0 depending on
the value of most significant bit of the corresponding element in the source register.
The source operand is a ZMM/YMM/XMM register. The destination operand is a mask register.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
5-534
Vol. 2C
VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M—Convert a Vector Register to a Mask
INSTRUCTION SET REFERENCE, V
Operation
VPMOVB2M (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j := 0 TO KL-1
i := j * 8
IF SRC[i+7]
THEN DEST[j] := 1
ELSE
DEST[j] := 0
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0
VPMOVW2M (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1
i := j * 16
IF SRC[i+15]
THEN DEST[j] := 1
ELSE
DEST[j] := 0
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0
VPMOVD2M (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF SRC[i+31]
THEN DEST[j] := 1
ELSE
DEST[j] := 0
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0
VPMOVQ2M (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF SRC[i+63]
THEN DEST[j] := 1
ELSE
DEST[j] := 0
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0
VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M—Convert a Vector Register to a Mask
Vol. 2C
5-535
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalents
VPMPOVB2M __mmask64 _mm512_movepi8_mask( __m512i );
VPMPOVD2M __mmask16 _mm512_movepi32_mask( __m512i );
VPMPOVQ2M __mmask8 _mm512_movepi64_mask( __m512i );
VPMPOVW2M __mmask32 _mm512_movepi16_mask( __m512i );
VPMPOVB2M __mmask32 _mm256_movepi8_mask( __m256i );
VPMPOVD2M __mmask8 _mm256_movepi32_mask( __m256i );
VPMPOVQ2M __mmask8 _mm256_movepi64_mask( __m256i );
VPMPOVW2M __mmask16 _mm256_movepi16_mask( __m256i );
VPMPOVB2M __mmask16 _mm_movepi8_mask( __m128i );
VPMPOVD2M __mmask8 _mm_movepi32_mask( __m128i );
VPMPOVQ2M __mmask8 _mm_movepi64_mask( __m128i );
VPMPOVW2M __mmask8 _mm_movepi16_mask( __m128i );
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Table 2-55, “Type E7NM Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
5-536
Vol. 2C
VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M—Convert a Vector Register to a Mask
INSTRUCTION SET REFERENCE, V
VPMOVDB/VPMOVSDB/VPMOVUSDB—Down Convert DWord to Byte
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.F3.0F38.W0 31 /r
A
V/V
AVX512VL
Converts 4 packed double-word integers from xmm2
VPMOVDB xmm1/m32 {k1}{z}, xmm2
AVX512F
into 4 packed byte integers in xmm1/m32 with
truncation under writemask k1.
EVEX.128.F3.0F38.W0 21 /r
A
V/V
AVX512VL
Converts 4 packed signed double-word integers from
VPMOVSDB xmm1/m32 {k1}{z}, xmm2
AVX512F
xmm2 into 4 packed signed byte integers in
xmm1/m32 using signed saturation under writemask
k1.
EVEX.128.F3.0F38.W0 11 /r
A
V/V
AVX512VL
Converts 4 packed unsigned double-word integers
VPMOVUSDB xmm1/m32 {k1}{z}, xmm2
AVX512F
from xmm2 into 4 packed unsigned byte integers in
xmm1/m32 using unsigned saturation under
writemask k1.
EVEX.256.F3.0F38.W0 31 /r
A
V/V
AVX512VL
Converts 8 packed double-word integers from ymm2
VPMOVDB xmm1/m64 {k1}{z}, ymm2
AVX512F
into 8 packed byte integers in xmm1/m64 with
truncation under writemask k1.
EVEX.256.F3.0F38.W0 21 /r
A
V/V
AVX512VL
Converts 8 packed signed double-word integers from
VPMOVSDB xmm1/m64 {k1}{z}, ymm2
AVX512F
ymm2 into 8 packed signed byte integers in
xmm1/m64 using signed saturation under writemask
k1.
EVEX.256.F3.0F38.W0 11 /r
A
V/V
AVX512VL
Converts 8 packed unsigned double-word integers
VPMOVUSDB xmm1/m64 {k1}{z}, ymm2
AVX512F
from ymm2 into 8 packed unsigned byte integers in
xmm1/m64 using unsigned saturation under
writemask k1.
EVEX.512.F3.0F38.W0 31 /r
A
V/V
AVX512F
Converts 16 packed double-word integers from zmm2
VPMOVDB xmm1/m128 {k1}{z}, zmm2
into 16 packed byte integers in xmm1/m128 with
truncation under writemask k1.
EVEX.512.F3.0F38.W0 21 /r
A
V/V
AVX512F
Converts 16 packed signed double-word integers
VPMOVSDB xmm1/m128 {k1}{z}, zmm2
from zmm2 into 16 packed signed byte integers in
xmm1/m128 using signed saturation under
writemask k1.
EVEX.512.F3.0F38.W0 11 /r
A
V/V
AVX512F
Converts 16 packed unsigned double-word integers
VPMOVUSDB xmm1/m128 {k1}{z},
from zmm2 into 16 packed unsigned byte integers in
zmm2
xmm1/m128 using unsigned saturation under
writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Quarter Mem
ModRM:r/m (w)
ModRM:reg (r)
N/A
N/A
Description
VPMOVDB down converts 32-bit integer elements in the source operand (the second operand) into packed bytes
using truncation. VPMOVSDB converts signed 32-bit integers into packed signed bytes using signed saturation.
VPMOVUSDB convert unsigned double-word values into unsigned byte values using unsigned saturation.
The source operand is a ZMM/YMM/XMM register. The destination operand is a XMM register or a 128/64/32-bit
memory location.
Down-converted byte elements are written to the destination operand (the first operand) from the least-significant
byte. Byte elements of the destination operand are updated according to the writemask. Bits (MAXVL-1:128/64/32)
of the register destination are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
VPMOVDB/VPMOVSDB/VPMOVUSDB—Down Convert DWord to Byte
Vol. 2C
5-537
INSTRUCTION SET REFERENCE, V
Operation
VPMOVDB instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 8
m := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := TruncateDoubleWordToByte (SRC[m+31:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/4] := 0;
VPMOVDB instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 8
m := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := TruncateDoubleWordToByte (SRC[m+31:m])
ELSE *DEST[i+7:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVSDB instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 8
m := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := SaturateSignedDoubleWordToByte (SRC[m+31:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/4] := 0;
5-538
Vol. 2C
VPMOVDB/VPMOVSDB/VPMOVUSDB—Down Convert DWord to Byte
INSTRUCTION SET REFERENCE, V
VPMOVSDB instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 8
m := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := SaturateSignedDoubleWordToByte (SRC[m+31:m])
ELSE *DEST[i+7:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVUSDB instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 8
m := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := SaturateUnsignedDoubleWordToByte (SRC[m+31:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/4] := 0;
VPMOVUSDB instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 8
m := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := SaturateUnsignedDoubleWordToByte (SRC[m+31:m])
ELSE *DEST[i+7:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVDB/VPMOVSDB/VPMOVUSDB—Down Convert DWord to Byte
Vol. 2C
5-539
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalents
VPMOVDB __m128i _mm512_cvtepi32_epi8( __m512i a);
VPMOVDB __m128i _mm512_mask_cvtepi32_epi8(__m128i s, __mmask16 k, __m512i a);
VPMOVDB __m128i _mm512_maskz_cvtepi32_epi8( __mmask16 k, __m512i a);
VPMOVDB void _mm512_mask_cvtepi32_storeu_epi8(void * d, __mmask16 k, __m512i a);
VPMOVSDB __m128i _mm512_cvtsepi32_epi8( __m512i a);
VPMOVSDB __m128i _mm512_mask_cvtsepi32_epi8(__m128i s, __mmask16 k, __m512i a);
VPMOVSDB __m128i _mm512_maskz_cvtsepi32_epi8( __mmask16 k, __m512i a);
VPMOVSDB void _mm512_mask_cvtsepi32_storeu_epi8(void * d, __mmask16 k, __m512i a);
VPMOVUSDB __m128i _mm512_cvtusepi32_epi8( __m512i a);
VPMOVUSDB __m128i _mm512_mask_cvtusepi32_epi8(__m128i s, __mmask16 k, __m512i a);
VPMOVUSDB __m128i _mm512_maskz_cvtusepi32_epi8( __mmask16 k, __m512i a);
VPMOVUSDB void _mm512_mask_cvtusepi32_storeu_epi8(void * d, __mmask16 k, __m512i a);
VPMOVUSDB __m128i _mm256_cvtusepi32_epi8(__m256i a);
VPMOVUSDB __m128i _mm256_mask_cvtusepi32_epi8(__m128i a, __mmask8 k, __m256i b);
VPMOVUSDB __m128i _mm256_maskz_cvtusepi32_epi8( __mmask8 k, __m256i b);
VPMOVUSDB void _mm256_mask_cvtusepi32_storeu_epi8(void * , __mmask8 k, __m256i b);
VPMOVUSDB __m128i _mm_cvtusepi32_epi8(__m128i a);
VPMOVUSDB __m128i _mm_mask_cvtusepi32_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVUSDB __m128i _mm_maskz_cvtusepi32_epi8( __mmask8 k, __m128i b);
VPMOVUSDB void _mm_mask_cvtusepi32_storeu_epi8(void * , __mmask8 k, __m128i b);
VPMOVSDB __m128i _mm256_cvtsepi32_epi8(__m256i a);
VPMOVSDB __m128i _mm256_mask_cvtsepi32_epi8(__m128i a, __mmask8 k, __m256i b);
VPMOVSDB __m128i _mm256_maskz_cvtsepi32_epi8( __mmask8 k, __m256i b);
VPMOVSDB void _mm256_mask_cvtsepi32_storeu_epi8(void * , __mmask8 k, __m256i b);
VPMOVSDB __m128i _mm_cvtsepi32_epi8(__m128i a);
VPMOVSDB __m128i _mm_mask_cvtsepi32_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVSDB __m128i _mm_maskz_cvtsepi32_epi8( __mmask8 k, __m128i b);
VPMOVSDB void _mm_mask_cvtsepi32_storeu_epi8(void * , __mmask8 k, __m128i b);
VPMOVDB __m128i _mm256_cvtepi32_epi8(__m256i a);
VPMOVDB __m128i _mm256_mask_cvtepi32_epi8(__m128i a, __mmask8 k, __m256i b);
VPMOVDB __m128i _mm256_maskz_cvtepi32_epi8( __mmask8 k, __m256i b);
VPMOVDB void _mm256_mask_cvtepi32_storeu_epi8(void * , __mmask8 k, __m256i b);
VPMOVDB __m128i _mm_cvtepi32_epi8(__m128i a);
VPMOVDB __m128i _mm_mask_cvtepi32_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVDB __m128i _mm_maskz_cvtepi32_epi8( __mmask8 k, __m128i b);
VPMOVDB void _mm_mask_cvtepi32_storeu_epi8(void * , __mmask8 k, __m128i b);
SIMD Floating-Point Exceptions
None.
Other Exceptions
EVEX-encoded instruction, see Table 2-53, “Type E6 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
5-540
Vol. 2C
VPMOVDB/VPMOVSDB/VPMOVUSDB—Down Convert DWord to Byte
INSTRUCTION SET REFERENCE, V
VPMOVDW/VPMOVSDW/VPMOVUSDW—Down Convert DWord to Word
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.F3.0F38.W0 33 /r
A
V/V
AVX512VL
Converts 4 packed double-word integers from
VPMOVDW xmm1/m64 {k1}{z}, xmm2
AVX512F
xmm2 into 4 packed word integers in xmm1/m64
with truncation under writemask k1.
EVEX.128.F3.0F38.W0 23 /r
A
V/V
AVX512VL
Converts 4 packed signed double-word integers
VPMOVSDW xmm1/m64 {k1}{z}, xmm2
AVX512F
from xmm2 into 4 packed signed word integers in
ymm1/m64 using signed saturation under
writemask k1.
EVEX.128.F3.0F38.W0 13 /r
A
V/V
AVX512VL
Converts 4 packed unsigned double-word integers
VPMOVUSDW xmm1/m64 {k1}{z}, xmm2
AVX512F
from xmm2 into 4 packed unsigned word integers
in xmm1/m64 using unsigned saturation under
writemask k1.
EVEX.256.F3.0F38.W0 33 /r
A
V/V
AVX512VL
Converts 8 packed double-word integers from
VPMOVDW xmm1/m128 {k1}{z}, ymm2
AVX512F
ymm2 into 8 packed word integers in xmm1/m128
with truncation under writemask k1.
EVEX.256.F3.0F38.W0 23 /r
A
V/V
AVX512VL
Converts 8 packed signed double-word integers
VPMOVSDW xmm1/m128 {k1}{z}, ymm2
AVX512F
from ymm2 into 8 packed signed word integers in
xmm1/m128 using signed saturation under
writemask k1.
EVEX.256.F3.0F38.W0 13 /r
A
V/V
AVX512VL
Converts 8 packed unsigned double-word integers
VPMOVUSDW xmm1/m128 {k1}{z},
AVX512F
from ymm2 into 8 packed unsigned word integers
ymm2
in xmm1/m128 using unsigned saturation under
writemask k1.
EVEX.512.F3.0F38.W0 33 /r
A
V/V
AVX512F
Converts 16 packed double-word integers from
VPMOVDW ymm1/m256 {k1}{z}, zmm2
zmm2 into 16 packed word integers in
ymm1/m256 with truncation under writemask k1.
EVEX.512.F3.0F38.W0 23 /r
A
V/V
AVX512F
Converts 16 packed signed double-word integers
VPMOVSDW ymm1/m256 {k1}{z}, zmm2
from zmm2 into 16 packed signed word integers in
ymm1/m256 using signed saturation under
writemask k1.
EVEX.512.F3.0F38.W0 13 /r
A
V/V
AVX512F
Converts 16 packed unsigned double-word integers
VPMOVUSDW ymm1/m256 {k1}{z},
from zmm2 into 16 packed unsigned word integers
zmm2
in ymm1/m256 using unsigned saturation under
writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Half Mem
ModRM:r/m (w)
ModRM:reg (r)
N/A
N/A
Description
VPMOVDW down converts 32-bit integer elements in the source operand (the second operand) into packed words
using truncation. VPMOVSDW converts signed 32-bit integers into packed signed words using signed saturation.
VPMOVUSDW convert unsigned double-word values into unsigned word values using unsigned saturation.
The source operand is a ZMM/YMM/XMM register. The destination operand is a YMM/XMM/XMM register or a
256/128/64-bit memory location.
Down-converted word elements are written to the destination operand (the first operand) from the least-significant
word. Word elements of the destination operand are updated according to the writemask. Bits (MAXVL-
1:256/128/64) of the register destination are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
VPMOVDW/VPMOVSDW/VPMOVUSDW—Down Convert DWord to Word
Vol. 2C
5-541
INSTRUCTION SET REFERENCE, V
Operation
VPMOVDW instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 16
m := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := TruncateDoubleWordToWord (SRC[m+31:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0;
VPMOVDW instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 16
m := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := TruncateDoubleWordToWord (SRC[m+31:m])
ELSE
*DEST[i+15:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVSDW instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 16
m := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := SaturateSignedDoubleWordToWord (SRC[m+31:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0;
5-542
Vol. 2C
VPMOVDW/VPMOVSDW/VPMOVUSDW—Down Convert DWord to Word
INSTRUCTION SET REFERENCE, V
VPMOVSDW instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 16
m := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := SaturateSignedDoubleWordToWord (SRC[m+31:m])
ELSE
*DEST[i+15:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVUSDW instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 16
m := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := SaturateUnsignedDoubleWordToWord (SRC[m+31:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0;
VPMOVUSDW instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 16
m := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := SaturateUnsignedDoubleWordToWord (SRC[m+31:m])
ELSE
*DEST[i+15:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVDW/VPMOVSDW/VPMOVUSDW—Down Convert DWord to Word
Vol. 2C
5-543
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalents
VPMOVDW __m256i _mm512_cvtepi32_epi16( __m512i a);
VPMOVDW __m256i _mm512_mask_cvtepi32_epi16(__m256i s, __mmask16 k, __m512i a);
VPMOVDW __m256i _mm512_maskz_cvtepi32_epi16( __mmask16 k, __m512i a);
VPMOVDW void _mm512_mask_cvtepi32_storeu_epi16(void * d, __mmask16 k, __m512i a);
VPMOVSDW __m256i _mm512_cvtsepi32_epi16( __m512i a);
VPMOVSDW __m256i _mm512_mask_cvtsepi32_epi16(__m256i s, __mmask16 k, __m512i a);
VPMOVSDW __m256i _mm512_maskz_cvtsepi32_epi16( __mmask16 k, __m512i a);
VPMOVSDW void _mm512_mask_cvtsepi32_storeu_epi16(void * d, __mmask16 k, __m512i a);
VPMOVUSDW __m256i _mm512_cvtusepi32_epi16 __m512i a);
VPMOVUSDW __m256i _mm512_mask_cvtusepi32_epi16(__m256i s, __mmask16 k, __m512i a);
VPMOVUSDW __m256i _mm512_maskz_cvtusepi32_epi16( __mmask16 k, __m512i a);
VPMOVUSDW void _mm512_mask_cvtusepi32_storeu_epi16(void * d, __mmask16 k, __m512i a);
VPMOVUSDW __m128i _mm256_cvtusepi32_epi16(__m256i a);
VPMOVUSDW __m128i _mm256_mask_cvtusepi32_epi16(__m128i a, __mmask8 k, __m256i b);
VPMOVUSDW __m128i _mm256_maskz_cvtusepi32_epi16( __mmask8 k, __m256i b);
VPMOVUSDW void _mm256_mask_cvtusepi32_storeu_epi16(void * , __mmask8 k, __m256i b);
VPMOVUSDW __m128i _mm_cvtusepi32_epi16(__m128i a);
VPMOVUSDW __m128i _mm_mask_cvtusepi32_epi16(__m128i a, __mmask8 k, __m128i b);
VPMOVUSDW __m128i _mm_maskz_cvtusepi32_epi16( __mmask8 k, __m128i b);
VPMOVUSDW void _mm_mask_cvtusepi32_storeu_epi16(void * , __mmask8 k, __m128i b);
VPMOVSDW __m128i _mm256_cvtsepi32_epi16(__m256i a);
VPMOVSDW __m128i _mm256_mask_cvtsepi32_epi16(__m128i a, __mmask8 k, __m256i b);
VPMOVSDW __m128i _mm256_maskz_cvtsepi32_epi16( __mmask8 k, __m256i b);
VPMOVSDW void _mm256_mask_cvtsepi32_storeu_epi16(void * , __mmask8 k, __m256i b);
VPMOVSDW __m128i _mm_cvtsepi32_epi16(__m128i a);
VPMOVSDW __m128i _mm_mask_cvtsepi32_epi16(__m128i a, __mmask8 k, __m128i b);
VPMOVSDW __m128i _mm_maskz_cvtsepi32_epi16( __mmask8 k, __m128i b);
VPMOVSDW void _mm_mask_cvtsepi32_storeu_epi16(void * , __mmask8 k, __m128i b);
VPMOVDW __m128i _mm256_cvtepi32_epi16(__m256i a);
VPMOVDW __m128i _mm256_mask_cvtepi32_epi16(__m128i a, __mmask8 k, __m256i b);
VPMOVDW __m128i _mm256_maskz_cvtepi32_epi16( __mmask8 k, __m256i b);
VPMOVDW void _mm256_mask_cvtepi32_storeu_epi16(void * , __mmask8 k, __m256i b);
VPMOVDW __m128i _mm_cvtepi32_epi16(__m128i a);
VPMOVDW __m128i _mm_mask_cvtepi32_epi16(__m128i a, __mmask8 k, __m128i b);
VPMOVDW __m128i _mm_maskz_cvtepi32_epi16( __mmask8 k, __m128i b);
VPMOVDW void _mm_mask_cvtepi32_storeu_epi16(void * , __mmask8 k, __m128i b);
SIMD Floating-Point Exceptions
None.
Other Exceptions
EVEX-encoded instruction, see Table 2-53, “Type E6 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
5-544
Vol. 2C
VPMOVDW/VPMOVSDW/VPMOVUSDW—Down Convert DWord to Word
INSTRUCTION SET REFERENCE, V
VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q—Convert a Mask Register to a Vector
Register
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.F3.0F38.W0 28 /r
RM
V/V
AVX512VL
Sets each byte in XMM1 to all 1’s or all 0’s based on the value
VPMOVM2B xmm1, k1
AVX512BW
of the corresponding bit in k1.
EVEX.256.F3.0F38.W0 28 /r
RM
V/V
AVX512VL
Sets each byte in YMM1 to all 1’s or all 0’s based on the value
VPMOVM2B ymm1, k1
AVX512BW
of the corresponding bit in k1.
EVEX.512.F3.0F38.W0 28 /r
RM
V/V
AVX512BW
Sets each byte in ZMM1 to all 1’s or all 0’s based on the value
VPMOVM2B zmm1, k1
of the corresponding bit in k1.
EVEX.128.F3.0F38.W1 28 /r
RM
V/V
AVX512VL
Sets each word in XMM1 to all 1’s or all 0’s based on the value
VPMOVM2W xmm1, k1
AVX512BW
of the corresponding bit in k1.
EVEX.256.F3.0F38.W1 28 /r
RM
V/V
AVX512VL
Sets each word in YMM1 to all 1’s or all 0’s based on the value
VPMOVM2W ymm1, k1
AVX512BW
of the corresponding bit in k1.
EVEX.512.F3.0F38.W1 28 /r
RM
V/V
AVX512BW
Sets each word in ZMM1 to all 1’s or all 0’s based on the value
VPMOVM2W zmm1, k1
of the corresponding bit in k1.
EVEX.128.F3.0F38.W0 38 /r
RM
V/V
AVX512VL
Sets each doubleword in XMM1 to all 1’s or all 0’s based on the
VPMOVM2D xmm1, k1
AVX512DQ
value of the corresponding bit in k1.
EVEX.256.F3.0F38.W0 38 /r
RM
V/V
AVX512VL
Sets each doubleword in YMM1 to all 1’s or all 0’s based on the
VPMOVM2D ymm1, k1
AVX512DQ
value of the corresponding bit in k1.
EVEX.512.F3.0F38.W0 38 /r
RM
V/V
AVX512DQ
Sets each doubleword in ZMM1 to all 1’s or all 0’s based on the
VPMOVM2D zmm1, k1
value of the corresponding bit in k1.
EVEX.128.F3.0F38.W1 38 /r
RM
V/V
AVX512VL
Sets each quadword in XMM1 to all 1’s or all 0’s based on the
VPMOVM2Q xmm1, k1
AVX512DQ
value of the corresponding bit in k1.
EVEX.256.F3.0F38.W1 38 /r
RM
V/V
AVX512VL
Sets each quadword in YMM1 to all 1’s or all 0’s based on the
VPMOVM2Q ymm1, k1
AVX512DQ
value of the corresponding bit in k1.
EVEX.512.F3.0F38.W1 38 /r
RM
V/V
AVX512DQ
Sets each quadword in ZMM1 to all 1’s or all 0’s based on the
VPMOVM2Q zmm1, k1
value of the corresponding bit in k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts a mask register to a vector register. Each element in the destination register is set to all 1’s or all 0’s
depending on the value of the corresponding bit in the source mask register.
The source operand is a mask register. The destination operand is a ZMM/YMM/XMM register.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q—Convert a Mask Register to a Vector Register
Vol. 2C
5-545
INSTRUCTION SET REFERENCE, V
Operation
VPMOVM2B (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j := 0 TO KL-1
i := j * 8
IF SRC[j]
THEN DEST[i+7:i] := -1
ELSE
DEST[i+7:i] := 0
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPMOVM2W (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1
i := j * 16
IF SRC[j]
THEN DEST[i+15:i] := -1
ELSE
DEST[i+15:i] := 0
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPMOVM2D (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF SRC[j]
THEN DEST[i+31:i] := -1
ELSE
DEST[i+31:i] := 0
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPMOVM2Q (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF SRC[j]
THEN DEST[i+63:i] := -1
ELSE
DEST[i+63:i] := 0
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
5-546
Vol. 2C
VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q—Convert a Mask Register to a Vector Register
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalents
VPMOVM2B __m512i _mm512_movm_epi8(__mmask64 );
VPMOVM2D __m512i _mm512_movm_epi32(__mmask8 );
VPMOVM2Q __m512i _mm512_movm_epi64(__mmask16 );
VPMOVM2W __m512i _mm512_movm_epi16(__mmask32 );
VPMOVM2B __m256i _mm256_movm_epi8(__mmask32 );
VPMOVM2D __m256i _mm256_movm_epi32(__mmask8 );
VPMOVM2Q __m256i _mm256_movm_epi64(__mmask8 );
VPMOVM2W __m256i _mm256_movm_epi16(__mmask16 );
VPMOVM2B __m128i _mm_movm_epi8(__mmask16 );
VPMOVM2D __m128i _mm_movm_epi32(__mmask8 );
VPMOVM2Q __m128i _mm_movm_epi64(__mmask8 );
VPMOVM2W __m128i _mm_movm_epi16(__mmask8 );
SIMD Floating-Point Exceptions
None.
Other Exceptions
EVEX-encoded instruction, see Table 2-55, “Type E7NM Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q—Convert a Mask Register to a Vector Register
Vol. 2C
5-547
INSTRUCTION SET REFERENCE, V
VPMOVQB/VPMOVSQB/VPMOVUSQB—Down Convert QWord to Byte
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.F3.0F38.W0 32 /r
A
V/V
AVX512VL
Converts 2 packed quad-word integers from xmm2
VPMOVQB xmm1/m16 {k1}{z}, xmm2
AVX512F
into 2 packed byte integers in xmm1/m16 with
truncation under writemask k1.
EVEX.128.F3.0F38.W0 22 /r
A
V/V
AVX512VL
Converts 2 packed signed quad-word integers from
VPMOVSQB xmm1/m16 {k1}{z}, xmm2
AVX512F
xmm2 into 2 packed signed byte integers in
xmm1/m16 using signed saturation under writemask
k1.
EVEX.128.F3.0F38.W0 12 /r
A
V/V
AVX512VL
Converts 2 packed unsigned quad-word integers
VPMOVUSQB xmm1/m16 {k1}{z}, xmm2
AVX512F
from xmm2 into 2 packed unsigned byte integers in
xmm1/m16 using unsigned saturation under
writemask k1.
EVEX.256.F3.0F38.W0 32 /r
A
V/V
AVX512VL
Converts 4 packed quad-word integers from ymm2
VPMOVQB xmm1/m32 {k1}{z}, ymm2
AVX512F
into 4 packed byte integers in xmm1/m32 with
truncation under writemask k1.
EVEX.256.F3.0F38.W0 22 /r
A
V/V
AVX512VL
Converts 4 packed signed quad-word integers from
VPMOVSQB xmm1/m32 {k1}{z}, ymm2
AVX512F
ymm2 into 4 packed signed byte integers in
xmm1/m32 using signed saturation under writemask
k1.
EVEX.256.F3.0F38.W0 12 /r
A
V/V
AVX512VL
Converts 4 packed unsigned quad-word integers
VPMOVUSQB xmm1/m32 {k1}{z}, ymm2
AVX512F
from ymm2 into 4 packed unsigned byte integers in
xmm1/m32 using unsigned saturation under
writemask k1.
EVEX.512.F3.0F38.W0 32 /r
A
V/V
AVX512F
Converts 8 packed quad-word integers from zmm2
VPMOVQB xmm1/m64 {k1}{z}, zmm2
into 8 packed byte integers in xmm1/m64 with
truncation under writemask k1.
EVEX.512.F3.0F38.W0 22 /r
A
V/V
AVX512F
Converts 8 packed signed quad-word integers from
VPMOVSQB xmm1/m64 {k1}{z}, zmm2
zmm2 into 8 packed signed byte integers in
xmm1/m64 using signed saturation under writemask
k1.
EVEX.512.F3.0F38.W0 12 /r
A
V/V
AVX512F
Converts 8 packed unsigned quad-word integers
VPMOVUSQB xmm1/m64 {k1}{z}, zmm2
from zmm2 into 8 packed unsigned byte integers in
xmm1/m64 using unsigned saturation under
writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Eighth Mem
ModRM:r/m (w)
ModRM:reg (r)
N/A
N/A
Description
VPMOVQB down converts 64-bit integer elements in the source operand (the second operand) into packed byte
elements using truncation. VPMOVSQB converts signed 64-bit integers into packed signed bytes using signed satu-
ration. VPMOVUSQB convert unsigned quad-word values into unsigned byte values using unsigned saturation. The
source operand is a vector register. The destination operand is an XMM register or a memory location.
Down-converted byte elements are written to the destination operand (the first operand) from the least-significant
byte. Byte elements of the destination operand are updated according to the writemask. Bits (MAXVL-1:64) of the
destination are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
5-548
Vol. 2C
VPMOVQB/VPMOVSQB/VPMOVUSQB—Down Convert QWord to Byte
INSTRUCTION SET REFERENCE, V
Operation
VPMOVQB instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 8
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := TruncateQuadWordToByte (SRC[m+63:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/8] := 0;
VPMOVQB instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 8
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := TruncateQuadWordToByte (SRC[m+63:m])
ELSE
*DEST[i+7:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVSQB instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 8
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := SaturateSignedQuadWordToByte (SRC[m+63:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/8] := 0;
VPMOVQB/VPMOVSQB/VPMOVUSQB—Down Convert QWord to Byte
Vol. 2C
5-549
INSTRUCTION SET REFERENCE, V
VPMOVSQB instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 8
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := SaturateSignedQuadWordToByte (SRC[m+63:m])
ELSE
*DEST[i+7:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVUSQB instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 8
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := SaturateUnsignedQuadWordToByte (SRC[m+63:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/8] := 0;
VPMOVUSQB instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 8
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := SaturateUnsignedQuadWordToByte (SRC[m+63:m])
ELSE
*DEST[i+7:i] remains unchanged*
; merging-masking
FI;
ENDFOR
5-550
Vol. 2C
VPMOVQB/VPMOVSQB/VPMOVUSQB—Down Convert QWord to Byte
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalents
VPMOVQB __m128i _mm512_cvtepi64_epi8( __m512i a);
VPMOVQB __m128i _mm512_mask_cvtepi64_epi8(__m128i s, __mmask8 k, __m512i a);
VPMOVQB __m128i _mm512_maskz_cvtepi64_epi8( __mmask8 k, __m512i a);
VPMOVQB void _mm512_mask_cvtepi64_storeu_epi8(void * d, __mmask8 k, __m512i a);
VPMOVSQB __m128i _mm512_cvtsepi64_epi8( __m512i a);
VPMOVSQB __m128i _mm512_mask_cvtsepi64_epi8(__m128i s, __mmask8 k, __m512i a);
VPMOVSQB __m128i _mm512_maskz_cvtsepi64_epi8( __mmask8 k, __m512i a);
VPMOVSQB void _mm512_mask_cvtsepi64_storeu_epi8(void * d, __mmask8 k, __m512i a);
VPMOVUSQB __m128i _mm512_cvtusepi64_epi8( __m512i a);
VPMOVUSQB __m128i _mm512_mask_cvtusepi64_epi8(__m128i s, __mmask8 k, __m512i a);
VPMOVUSQB __m128i _mm512_maskz_cvtusepi64_epi8( __mmask8 k, __m512i a);
VPMOVUSQB void _mm512_mask_cvtusepi64_storeu_epi8(void * d, __mmask8 k, __m512i a);
VPMOVUSQB __m128i _mm256_cvtusepi64_epi8(__m256i a);
VPMOVUSQB __m128i _mm256_mask_cvtusepi64_epi8(__m128i a, __mmask8 k, __m256i b);
VPMOVUSQB __m128i _mm256_maskz_cvtusepi64_epi8( __mmask8 k, __m256i b);
VPMOVUSQB void _mm256_mask_cvtusepi64_storeu_epi8(void * , __mmask8 k, __m256i b);
VPMOVUSQB __m128i _mm_cvtusepi64_epi8(__m128i a);
VPMOVUSQB __m128i _mm_mask_cvtusepi64_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVUSQB __m128i _mm_maskz_cvtusepi64_epi8( __mmask8 k, __m128i b);
VPMOVUSQB void _mm_mask_cvtusepi64_storeu_epi8(void * , __mmask8 k, __m128i b);
VPMOVSQB __m128i _mm256_cvtsepi64_epi8(__m256i a);
VPMOVSQB __m128i _mm256_mask_cvtsepi64_epi8(__m128i a, __mmask8 k, __m256i b);
VPMOVSQB __m128i _mm256_maskz_cvtsepi64_epi8( __mmask8 k, __m256i b);
VPMOVSQB void _mm256_mask_cvtsepi64_storeu_epi8(void * , __mmask8 k, __m256i b);
VPMOVSQB __m128i _mm_cvtsepi64_epi8(__m128i a);
VPMOVSQB __m128i _mm_mask_cvtsepi64_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVSQB __m128i _mm_maskz_cvtsepi64_epi8( __mmask8 k, __m128i b);
VPMOVSQB void _mm_mask_cvtsepi64_storeu_epi8(void * , __mmask8 k, __m128i b);
VPMOVQB __m128i _mm256_cvtepi64_epi8(__m256i a);
VPMOVQB __m128i _mm256_mask_cvtepi64_epi8(__m128i a, __mmask8 k, __m256i b);
VPMOVQB __m128i _mm256_maskz_cvtepi64_epi8( __mmask8 k, __m256i b);
VPMOVQB void _mm256_mask_cvtepi64_storeu_epi8(void * , __mmask8 k, __m256i b);
VPMOVQB __m128i _mm_cvtepi64_epi8(__m128i a);
VPMOVQB __m128i _mm_mask_cvtepi64_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVQB __m128i _mm_maskz_cvtepi64_epi8( __mmask8 k, __m128i b);
VPMOVQB void _mm_mask_cvtepi64_storeu_epi8(void * , __mmask8 k, __m128i b);
SIMD Floating-Point Exceptions
None.
Other Exceptions
EVEX-encoded instruction, see Table 2-53, “Type E6 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VPMOVQB/VPMOVSQB/VPMOVUSQB—Down Convert QWord to Byte
Vol. 2C
5-551
INSTRUCTION SET REFERENCE, V
VPMOVQD/VPMOVSQD/VPMOVUSQD—Down Convert QWord to DWord
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.F3.0F38.W0 35 /r
A
V/V
AVX512VL
Converts 2 packed quad-word integers from xmm2
VPMOVQD xmm1/m128 {k1}{z}, xmm2
AVX512F
into 2 packed double-word integers in xmm1/m128
with truncation subject to writemask k1.
EVEX.128.F3.0F38.W0 25 /r
A
V/V
AVX512VL
Converts 2 packed signed quad-word integers from
VPMOVSQD xmm1/m64 {k1}{z}, xmm2
AVX512F
xmm2 into 2 packed signed double-word integers in
xmm1/m64 using signed saturation subject to
writemask k1.
EVEX.128.F3.0F38.W0 15 /r
A
V/V
AVX512VL
Converts 2 packed unsigned quad-word integers
VPMOVUSQD xmm1/m64 {k1}{z}, xmm2
AVX512F
from xmm2 into 2 packed unsigned double-word
integers in xmm1/m64 using unsigned saturation
subject to writemask k1.
EVEX.256.F3.0F38.W0 35 /r
A
V/V
AVX512VL
Converts 4 packed quad-word integers from ymm2
VPMOVQD xmm1/m128 {k1}{z}, ymm2
AVX512F
into 4 packed double-word integers in xmm1/m128
with truncation subject to writemask k1.
EVEX.256.F3.0F38.W0 25 /r
A
V/V
AVX512VL
Converts 4 packed signed quad-word integers from
VPMOVSQD xmm1/m128 {k1}{z}, ymm2
AVX512F
ymm2 into 4 packed signed double-word integers in
xmm1/m128 using signed saturation subject to
writemask k1.
EVEX.256.F3.0F38.W0 15 /r
A
V/V
AVX512VL
Converts 4 packed unsigned quad-word integers
VPMOVUSQD xmm1/m128 {k1}{z}, ymm2
AVX512F
from ymm2 into 4 packed unsigned double-word
integers in xmm1/m128 using unsigned saturation
subject to writemask k1.
EVEX.512.F3.0F38.W0 35 /r
A
V/V
AVX512F
Converts 8 packed quad-word integers from zmm2
VPMOVQD ymm1/m256 {k1}{z}, zmm2
into 8 packed double-word integers in ymm1/m256
with truncation subject to writemask k1.
EVEX.512.F3.0F38.W0 25 /r
A
V/V
AVX512F
Converts 8 packed signed quad-word integers from
VPMOVSQD ymm1/m256 {k1}{z}, zmm2
zmm2 into 8 packed signed double-word integers in
ymm1/m256 using signed saturation subject to
writemask k1.
EVEX.512.F3.0F38.W0 15 /r
A
V/V
AVX512F
Converts 8 packed unsigned quad-word integers
VPMOVUSQD ymm1/m256 {k1}{z}, zmm2
from zmm2 into 8 packed unsigned double-word
integers in ymm1/m256 using unsigned saturation
subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Half Mem
ModRM:r/m (w)
ModRM:reg (r)
N/A
N/A
Description
VPMOVQW down converts 64-bit integer elements in the source operand (the second operand) into packed double-
words using truncation. VPMOVSQW converts signed 64-bit integers into packed signed doublewords using signed
saturation. VPMOVUSQW convert unsigned quad-word values into unsigned double-word values using unsigned
saturation.
The source operand is a ZMM/YMM/XMM register. The destination operand is a YMM/XMM/XMM register or a
256/128/64-bit memory location.
Down-converted doubleword elements are written to the destination operand (the first operand) from the least-
significant doubleword. Doubleword elements of the destination operand are updated according to the writemask.
Bits (MAXVL-1:256/128/64) of the register destination are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
5-552
Vol. 2C
VPMOVQD/VPMOVSQD/VPMOVUSQD—Down Convert QWord to DWord
INSTRUCTION SET REFERENCE, V
Operation
VPMOVQD instruction (EVEX encoded version) reg-reg form
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 32
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := TruncateQuadWordToDWord (SRC[m+63:m])
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0;
VPMOVQD instruction (EVEX encoded version) memory form
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 32
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := TruncateQuadWordToDWord (SRC[m+63:m])
ELSE *DEST[i+31:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVSQD instruction (EVEX encoded version) reg-reg form
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 32
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := SaturateSignedQuadWordToDWord (SRC[m+63:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0;
VPMOVQD/VPMOVSQD/VPMOVUSQD—Down Convert QWord to DWord
Vol. 2C
5-553
INSTRUCTION SET REFERENCE, V
VPMOVSQD instruction (EVEX encoded version) memory form
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 32
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := SaturateSignedQuadWordToDWord (SRC[m+63:m])
ELSE *DEST[i+31:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVUSQD instruction (EVEX encoded version) reg-reg form
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 32
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := SaturateUnsignedQuadWordToDWord (SRC[m+63:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0;
VPMOVUSQD instruction (EVEX encoded version) memory form
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 32
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := SaturateUnsignedQuadWordToDWord (SRC[m+63:m])
ELSE *DEST[i+31:i] remains unchanged*
; merging-masking
FI;
ENDFOR
5-554
Vol. 2C
VPMOVQD/VPMOVSQD/VPMOVUSQD—Down Convert QWord to DWord
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalents
VPMOVQD __m256i _mm512_cvtepi64_epi32( __m512i a);
VPMOVQD __m256i _mm512_mask_cvtepi64_epi32(__m256i s, __mmask8 k, __m512i a);
VPMOVQD __m256i _mm512_maskz_cvtepi64_epi32( __mmask8 k, __m512i a);
VPMOVQD void _mm512_mask_cvtepi64_storeu_epi32(void * d, __mmask8 k, __m512i a);
VPMOVSQD __m256i _mm512_cvtsepi64_epi32( __m512i a);
VPMOVSQD __m256i _mm512_mask_cvtsepi64_epi32(__m256i s, __mmask8 k, __m512i a);
VPMOVSQD __m256i _mm512_maskz_cvtsepi64_epi32( __mmask8 k, __m512i a);
VPMOVSQD void _mm512_mask_cvtsepi64_storeu_epi32(void * d, __mmask8 k, __m512i a);
VPMOVUSQD __m256i _mm512_cvtusepi64_epi32( __m512i a);
VPMOVUSQD __m256i _mm512_mask_cvtusepi64_epi32(__m256i s, __mmask8 k, __m512i a);
VPMOVUSQD __m256i _mm512_maskz_cvtusepi64_epi32( __mmask8 k, __m512i a);
VPMOVUSQD void _mm512_mask_cvtusepi64_storeu_epi32(void * d, __mmask8 k, __m512i a);
VPMOVUSQD __m128i _mm256_cvtusepi64_epi32(__m256i a);
VPMOVUSQD __m128i _mm256_mask_cvtusepi64_epi32(__m128i a, __mmask8 k, __m256i b);
VPMOVUSQD __m128i _mm256_maskz_cvtusepi64_epi32( __mmask8 k, __m256i b);
VPMOVUSQD void _mm256_mask_cvtusepi64_storeu_epi32(void * , __mmask8 k, __m256i b);
VPMOVUSQD __m128i _mm_cvtusepi64_epi32(__m128i a);
VPMOVUSQD __m128i _mm_mask_cvtusepi64_epi32(__m128i a, __mmask8 k, __m128i b);
VPMOVUSQD __m128i _mm_maskz_cvtusepi64_epi32( __mmask8 k, __m128i b);
VPMOVUSQD void _mm_mask_cvtusepi64_storeu_epi32(void * , __mmask8 k, __m128i b);
VPMOVSQD __m128i _mm256_cvtsepi64_epi32(__m256i a);
VPMOVSQD __m128i _mm256_mask_cvtsepi64_epi32(__m128i a, __mmask8 k, __m256i b);
VPMOVSQD __m128i _mm256_maskz_cvtsepi64_epi32( __mmask8 k, __m256i b);
VPMOVSQD void _mm256_mask_cvtsepi64_storeu_epi32(void * , __mmask8 k, __m256i b);
VPMOVSQD __m128i _mm_cvtsepi64_epi32(__m128i a);
VPMOVSQD __m128i _mm_mask_cvtsepi64_epi32(__m128i a, __mmask8 k, __m128i b);
VPMOVSQD __m128i _mm_maskz_cvtsepi64_epi32( __mmask8 k, __m128i b);
VPMOVSQD void _mm_mask_cvtsepi64_storeu_epi32(void * , __mmask8 k, __m128i b);
VPMOVQD __m128i _mm256_cvtepi64_epi32(__m256i a);
VPMOVQD __m128i _mm256_mask_cvtepi64_epi32(__m128i a, __mmask8 k, __m256i b);
VPMOVQD __m128i _mm256_maskz_cvtepi64_epi32( __mmask8 k, __m256i b);
VPMOVQD void _mm256_mask_cvtepi64_storeu_epi32(void * , __mmask8 k, __m256i b);
VPMOVQD __m128i _mm_cvtepi64_epi32(__m128i a);
VPMOVQD __m128i _mm_mask_cvtepi64_epi32(__m128i a, __mmask8 k, __m128i b);
VPMOVQD __m128i _mm_maskz_cvtepi64_epi32( __mmask8 k, __m128i b);
VPMOVQD void _mm_mask_cvtepi64_storeu_epi32(void * , __mmask8 k, __m128i b);
SIMD Floating-Point Exceptions
None.
Other Exceptions
EVEX-encoded instruction, see Table 2-53, “Type E6 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VPMOVQD/VPMOVSQD/VPMOVUSQD—Down Convert QWord to DWord
Vol. 2C
5-555
INSTRUCTION SET REFERENCE, V
VPMOVQW/VPMOVSQW/VPMOVUSQW—Down Convert QWord to Word
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.F3.0F38.W0 34 /r
A
V/V
AVX512VL
Converts 2 packed quad-word integers from xmm2
VPMOVQW xmm1/m32 {k1}{z}, xmm2
AVX512F
into 2 packed word integers in xmm1/m32 with
truncation under writemask k1.
EVEX.128.F3.0F38.W0 24 /r
A
V/V
AVX512VL
Converts 8 packed signed quad-word integers from
VPMOVSQW xmm1/m32 {k1}{z}, xmm2
AVX512F
zmm2 into 8 packed signed word integers in
xmm1/m32 using signed saturation under writemask
k1.
EVEX.128.F3.0F38.W0 14 /r
A
V/V
AVX512VL
Converts 2 packed unsigned quad-word integers from
VPMOVUSQW xmm1/m32 {k1}{z}, xmm2
AVX512F
xmm2 into 2 packed unsigned word integers in
xmm1/m32 using unsigned saturation under
writemask k1.
EVEX.256.F3.0F38.W0 34 /r
A
V/V
AVX512VL
Converts 4 packed quad-word integers from ymm2
VPMOVQW xmm1/m64 {k1}{z}, ymm2
AVX512F
into 4 packed word integers in xmm1/m64 with
truncation under writemask k1.
EVEX.256.F3.0F38.W0 24 /r
A
V/V
AVX512VL
Converts 4 packed signed quad-word integers from
VPMOVSQW xmm1/m64 {k1}{z}, ymm2
AVX512F
ymm2 into 4 packed signed word integers in
xmm1/m64 using signed saturation under writemask
k1.
EVEX.256.F3.0F38.W0 14 /r
A
V/V
AVX512VL
Converts 4 packed unsigned quad-word integers from
VPMOVUSQW xmm1/m64 {k1}{z}, ymm2
AVX512F
ymm2 into 4 packed unsigned word integers in
xmm1/m64 using unsigned saturation under
writemask k1.
EVEX.512.F3.0F38.W0 34 /r
A
V/V
AVX512F
Converts 8 packed quad-word integers from zmm2
VPMOVQW xmm1/m128 {k1}{z}, zmm2
into 8 packed word integers in xmm1/m128 with
truncation under writemask k1.
EVEX.512.F3.0F38.W0 24 /r
A
V/V
AVX512F
Converts 8 packed signed quad-word integers from
VPMOVSQW xmm1/m128 {k1}{z}, zmm2
zmm2 into 8 packed signed word integers in
xmm1/m128 using signed saturation under
writemask k1.
EVEX.512.F3.0F38.W0 14 /r
A
V/V
AVX512F
Converts 8 packed unsigned quad-word integers from
VPMOVUSQW xmm1/m128 {k1}{z},
zmm2 into 8 packed unsigned word integers in
zmm2
xmm1/m128 using unsigned saturation under
writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Quarter Mem
ModRM:r/m (w)
ModRM:reg (r)
N/A
N/A
Description
VPMOVQW down converts 64-bit integer elements in the source operand (the second operand) into packed words
using truncation. VPMOVSQW converts signed 64-bit integers into packed signed words using signed saturation.
VPMOVUSQW convert unsigned quad-word values into unsigned word values using unsigned saturation.
The source operand is a ZMM/YMM/XMM register. The destination operand is a XMM register or a 128/64/32-bit
memory location.
Down-converted word elements are written to the destination operand (the first operand) from the least-significant
word. Word elements of the destination operand are updated according to the writemask. Bits (MAXVL-
1:128/64/32) of the register destination are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
5-556
Vol. 2C
VPMOVQW/VPMOVSQW/VPMOVUSQW—Down Convert QWord to Word
INSTRUCTION SET REFERENCE, V
Operation
VPMOVQW instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 16
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := TruncateQuadWordToWord (SRC[m+63:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/4] := 0;
VPMOVQW instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 16
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := TruncateQuadWordToWord (SRC[m+63:m])
ELSE
*DEST[i+15:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVSQW instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 16
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := SaturateSignedQuadWordToWord (SRC[m+63:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/4] := 0;
VPMOVQW/VPMOVSQW/VPMOVUSQW—Down Convert QWord to Word
Vol. 2C
5-557
INSTRUCTION SET REFERENCE, V
VPMOVSQW instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 16
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := SaturateSignedQuadWordToWord (SRC[m+63:m])
ELSE
*DEST[i+15:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVUSQW instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 16
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := SaturateUnsignedQuadWordToWord (SRC[m+63:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+15:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/4] := 0;
VPMOVUSQW instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 16
m := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := SaturateUnsignedQuadWordToWord (SRC[m+63:m])
ELSE
*DEST[i+15:i] remains unchanged*
; merging-masking
FI;
ENDFOR
5-558
Vol. 2C
VPMOVQW/VPMOVSQW/VPMOVUSQW—Down Convert QWord to Word
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalents
VPMOVQW __m128i _mm512_cvtepi64_epi16( __m512i a);
VPMOVQW __m128i _mm512_mask_cvtepi64_epi16(__m128i s, __mmask8 k, __m512i a);
VPMOVQW __m128i _mm512_maskz_cvtepi64_epi16( __mmask8 k, __m512i a);
VPMOVQW void _mm512_mask_cvtepi64_storeu_epi16(void * d, __mmask8 k, __m512i a);
VPMOVSQW __m128i _mm512_cvtsepi64_epi16( __m512i a);
VPMOVSQW __m128i _mm512_mask_cvtsepi64_epi16(__m128i s, __mmask8 k, __m512i a);
VPMOVSQW __m128i _mm512_maskz_cvtsepi64_epi16( __mmask8 k, __m512i a);
VPMOVSQW void _mm512_mask_cvtsepi64_storeu_epi16(void * d, __mmask8 k, __m512i a);
VPMOVUSQW __m128i _mm512_cvtusepi64_epi16( __m512i a);
VPMOVUSQW __m128i _mm512_mask_cvtusepi64_epi16(__m128i s, __mmask8 k, __m512i a);
VPMOVUSQW __m128i _mm512_maskz_cvtusepi64_epi16( __mmask8 k, __m512i a);
VPMOVUSQW void _mm512_mask_cvtusepi64_storeu_epi16(void * d, __mmask8 k, __m512i a);
VPMOVUSQD __m128i _mm256_cvtusepi64_epi32(__m256i a);
VPMOVUSQD __m128i _mm256_mask_cvtusepi64_epi32(__m128i a, __mmask8 k, __m256i b);
VPMOVUSQD __m128i _mm256_maskz_cvtusepi64_epi32( __mmask8 k, __m256i b);
VPMOVUSQD void _mm256_mask_cvtusepi64_storeu_epi32(void * , __mmask8 k, __m256i b);
VPMOVUSQD __m128i _mm_cvtusepi64_epi32(__m128i a);
VPMOVUSQD __m128i _mm_mask_cvtusepi64_epi32(__m128i a, __mmask8 k, __m128i b);
VPMOVUSQD __m128i _mm_maskz_cvtusepi64_epi32( __mmask8 k, __m128i b);
VPMOVUSQD void _mm_mask_cvtusepi64_storeu_epi32(void * , __mmask8 k, __m128i b);
VPMOVSQD __m128i _mm256_cvtsepi64_epi32(__m256i a);
VPMOVSQD __m128i _mm256_mask_cvtsepi64_epi32(__m128i a, __mmask8 k, __m256i b);
VPMOVSQD __m128i _mm256_maskz_cvtsepi64_epi32( __mmask8 k, __m256i b);
VPMOVSQD void _mm256_mask_cvtsepi64_storeu_epi32(void * , __mmask8 k, __m256i b);
VPMOVSQD __m128i _mm_cvtsepi64_epi32(__m128i a);
VPMOVSQD __m128i _mm_mask_cvtsepi64_epi32(__m128i a, __mmask8 k, __m128i b);
VPMOVSQD __m128i _mm_maskz_cvtsepi64_epi32( __mmask8 k, __m128i b);
VPMOVSQD void _mm_mask_cvtsepi64_storeu_epi32(void * , __mmask8 k, __m128i b);
VPMOVQD __m128i _mm256_cvtepi64_epi32(__m256i a);
VPMOVQD __m128i _mm256_mask_cvtepi64_epi32(__m128i a, __mmask8 k, __m256i b);
VPMOVQD __m128i _mm256_maskz_cvtepi64_epi32( __mmask8 k, __m256i b);
VPMOVQD void _mm256_mask_cvtepi64_storeu_epi32(void * , __mmask8 k, __m256i b);
VPMOVQD __m128i _mm_cvtepi64_epi32(__m128i a);
VPMOVQD __m128i _mm_mask_cvtepi64_epi32(__m128i a, __mmask8 k, __m128i b);
VPMOVQD __m128i _mm_maskz_cvtepi64_epi32( __mmask8 k, __m128i b);
VPMOVQD void _mm_mask_cvtepi64_storeu_epi32(void * , __mmask8 k, __m128i b);
SIMD Floating-Point Exceptions
None.
Other Exceptions
EVEX-encoded instruction, see Table 2-53, “Type E6 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VPMOVQW/VPMOVSQW/VPMOVUSQW—Down Convert QWord to Word
Vol. 2C
5-559
INSTRUCTION SET REFERENCE, V
VPMOVWB/VPMOVSWB/VPMOVUSWB—Down Convert Word to Byte
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.F3.0F38.W0 30 /r
A
V/V
AVX512VL
Converts 8 packed word integers from xmm2 into 8
VPMOVWB xmm1/m64 {k1}{z}, xmm2
AVX512BW
packed bytes in xmm1/m64 with truncation under
writemask k1.
EVEX.128.F3.0F38.W0 20 /r
A
V/V
AVX512VL
Converts 8 packed signed word integers from xmm2
VPMOVSWB xmm1/m64 {k1}{z},
AVX512BW
into 8 packed signed bytes in xmm1/m64 using
xmm2
signed saturation under writemask k1.
EVEX.128.F3.0F38.W0 10 /r
A
V/V
AVX512VL
Converts 8 packed unsigned word integers from
VPMOVUSWB xmm1/m64 {k1}{z},
AVX512BW
xmm2 into 8 packed unsigned bytes in 8mm1/m64
xmm2
using unsigned saturation under writemask k1.
EVEX.256.F3.0F38.W0 30 /r
A
V/V
AVX512VL
Converts 16 packed word integers from ymm2 into
VPMOVWB xmm1/m128 {k1}{z},
AVX512BW
16 packed bytes in xmm1/m128 with truncation
ymm2
under writemask k1.
EVEX.256.F3.0F38.W0 20 /r
A
V/V
AVX512VL
Converts 16 packed signed word integers from ymm2
VPMOVSWB xmm1/m128 {k1}{z},
AVX512BW
into 16 packed signed bytes in xmm1/m128 using
ymm2
signed saturation under writemask k1.
EVEX.256.F3.0F38.W0 10 /r
A
V/V
AVX512VL
Converts 16 packed unsigned word integers from
VPMOVUSWB xmm1/m128 {k1}{z},
AVX512BW
ymm2 into 16 packed unsigned bytes in xmm1/m128
ymm2
using unsigned saturation under writemask k1.
EVEX.512.F3.0F38.W0 30 /r
A
V/V
AVX512BW
Converts 32 packed word integers from zmm2 into
VPMOVWB ymm1/m256 {k1}{z},
32 packed bytes in ymm1/m256 with truncation
zmm2
under writemask k1.
EVEX.512.F3.0F38.W0 20 /r
A
V/V
AVX512BW
Converts 32 packed signed word integers from zmm2
VPMOVSWB ymm1/m256 {k1}{z},
into 32 packed signed bytes in ymm1/m256 using
zmm2
signed saturation under writemask k1.
EVEX.512.F3.0F38.W0 10 /r
A
V/V
AVX512BW
Converts 32 packed unsigned word integers from
VPMOVUSWB ymm1/m256 {k1}{z},
zmm2 into 32 packed unsigned bytes in ymm1/m256
zmm2
using unsigned saturation under writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Half Mem
ModRM:r/m (w)
ModRM:reg (r)
N/A
N/A
Description
VPMOVWB down converts 16-bit integers into packed bytes using truncation. VPMOVSWB converts signed 16-bit
integers into packed signed bytes using signed saturation. VPMOVUSWB convert unsigned word values into
unsigned byte values using unsigned saturation.
The source operand is a ZMM/YMM/XMM register. The destination operand is a YMM/XMM/XMM register or a
256/128/64-bit memory location.
Down-converted byte elements are written to the destination operand (the first operand) from the least-significant
byte. Byte elements of the destination operand are updated according to the writemask. Bits (MAXVL-
1:256/128/64) of the register destination are zeroed.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
5-560
Vol. 2C
VPMOVWB/VPMOVSWB/VPMOVUSWB—Down Convert Word to Byte
INSTRUCTION SET REFERENCE, V
Operation
VPMOVWB instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO Kl-1
i := j * 8
m := j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := TruncateWordToByte (SRC[m+15:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] = 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0;
VPMOVWB instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO Kl-1
i := j * 8
m := j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := TruncateWordToByte (SRC[m+15:m])
ELSE
*DEST[i+7:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVSWB instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO Kl-1
i := j * 8
m := j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := SaturateSignedWordToByte (SRC[m+15:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] = 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0;
VPMOVWB/VPMOVSWB/VPMOVUSWB—Down Convert Word to Byte
Vol. 2C
5-561
INSTRUCTION SET REFERENCE, V
VPMOVSWB instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO Kl-1
i := j * 8
m := j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := SaturateSignedWordToByte (SRC[m+15:m])
ELSE
*DEST[i+7:i] remains unchanged*
; merging-masking
FI;
ENDFOR
VPMOVUSWB instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO Kl-1
i := j * 8
m := j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := SaturateUnsignedWordToByte (SRC[m+15:m])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+7:i] = 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0;
VPMOVUSWB instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO Kl-1
i := j * 8
m := j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := SaturateUnsignedWordToByte (SRC[m+15:m])
ELSE
*DEST[i+7:i] remains unchanged*
; merging-masking
FI;
ENDFOR
5-562
Vol. 2C
VPMOVWB/VPMOVSWB/VPMOVUSWB—Down Convert Word to Byte
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalents
VPMOVUSWB __m256i _mm512_cvtusepi16_epi8(__m512i a);
VPMOVUSWB __m256i _mm512_mask_cvtusepi16_epi8(__m256i a, __mmask32 k, __m512i b);
VPMOVUSWB __m256i _mm512_maskz_cvtusepi16_epi8( __mmask32 k, __m512i b);
VPMOVUSWB void _mm512_mask_cvtusepi16_storeu_epi8(void * , __mmask32 k, __m512i b);
VPMOVSWB __m256i _mm512_cvtsepi16_epi8(__m512i a);
VPMOVSWB __m256i _mm512_mask_cvtsepi16_epi8(__m256i a, __mmask32 k, __m512i b);
VPMOVSWB __m256i _mm512_maskz_cvtsepi16_epi8( __mmask32 k, __m512i b);
VPMOVSWB void _mm512_mask_cvtsepi16_storeu_epi8(void * , __mmask32 k, __m512i b);
VPMOVWB __m256i _mm512_cvtepi16_epi8(__m512i a);
VPMOVWB __m256i _mm512_mask_cvtepi16_epi8(__m256i a, __mmask32 k, __m512i b);
VPMOVWB __m256i _mm512_maskz_cvtepi16_epi8( __mmask32 k, __m512i b);
VPMOVWB void _mm512_mask_cvtepi16_storeu_epi8(void * , __mmask32 k, __m512i b);
VPMOVUSWB __m128i _mm256_cvtusepi16_epi8(__m256i a);
VPMOVUSWB __m128i _mm256_mask_cvtusepi16_epi8(__m128i a, __mmask16 k, __m256i b);
VPMOVUSWB __m128i _mm256_maskz_cvtusepi16_epi8( __mmask16 k, __m256i b);
VPMOVUSWB void _mm256_mask_cvtusepi16_storeu_epi8(void * , __mmask16 k, __m256i b);
VPMOVUSWB __m128i _mm_cvtusepi16_epi8(__m128i a);
VPMOVUSWB __m128i _mm_mask_cvtusepi16_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVUSWB __m128i _mm_maskz_cvtusepi16_epi8( __mmask8 k, __m128i b);
VPMOVUSWB void _mm_mask_cvtusepi16_storeu_epi8(void * , __mmask8 k, __m128i b);
VPMOVSWB __m128i _mm256_cvtsepi16_epi8(__m256i a);
VPMOVSWB __m128i _mm256_mask_cvtsepi16_epi8(__m128i a, __mmask16 k, __m256i b);
VPMOVSWB __m128i _mm256_maskz_cvtsepi16_epi8( __mmask16 k, __m256i b);
VPMOVSWB void _mm256_mask_cvtsepi16_storeu_epi8(void * , __mmask16 k, __m256i b);
VPMOVSWB __m128i _mm_cvtsepi16_epi8(__m128i a);
VPMOVSWB __m128i _mm_mask_cvtsepi16_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVSWB __m128i _mm_maskz_cvtsepi16_epi8( __mmask8 k, __m128i b);
VPMOVSWB void _mm_mask_cvtsepi16_storeu_epi8(void * , __mmask8 k, __m128i b);
VPMOVWB __m128i _mm256_cvtepi16_epi8(__m256i a);
VPMOVWB __m128i _mm256_mask_cvtepi16_epi8(__m128i a, __mmask16 k, __m256i b);
VPMOVWB __m128i _mm256_maskz_cvtepi16_epi8( __mmask16 k, __m256i b);
VPMOVWB void _mm256_mask_cvtepi16_storeu_epi8(void * , __mmask16 k, __m256i b);
VPMOVWB __m128i _mm_cvtepi16_epi8(__m128i a);
VPMOVWB __m128i _mm_mask_cvtepi16_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVWB __m128i _mm_maskz_cvtepi16_epi8( __mmask8 k, __m128i b);
VPMOVWB void _mm_mask_cvtepi16_storeu_epi8(void * , __mmask8 k, __m128i b);
SIMD Floating-Point Exceptions
None.
Other Exceptions
EVEX-encoded instruction, see Table 2-53, “Type E6 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VPMOVWB/VPMOVSWB/VPMOVUSWB—Down Convert Word to Byte
Vol. 2C
5-563
INSTRUCTION SET REFERENCE, V
VPMULTISHIFTQB—Select Packed Unaligned Bytes From Quadword Sources
Opcode /
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.66.0F38.W1 83 /r
A
V/V
AVX512_VBMI
Select unaligned bytes from qwords in
VPMULTISHIFTQB xmm1 {k1}{z},
AVX512VL
xmm3/m128/m64bcst using control bytes in
xmm2,xmm3/m128/m64bcst
xmm2, write byte results to xmm1 under k1.
EVEX.256.66.0F38.W1 83 /r
A
V/V
AVX512_VBMI
Select unaligned bytes from qwords in
VPMULTISHIFTQB ymm1 {k1}{z},
AVX512VL
ymm3/m256/m64bcst using control bytes in
ymm2,ymm3/m256/m64bcst
ymm2, write byte results to ymm1 under k1.
EVEX.512.66.0F38.W1 83 /r
A
V/V
AVX512_VBMI
Select unaligned bytes from qwords in
VPMULTISHIFTQB zmm1 {k1}{z},
zmm3/m512/m64bcst using control bytes in
zmm2,zmm3/m512/m64bcst
zmm2, write byte results to zmm1 under k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
This instruction selects eight unaligned bytes from each input qword element of the second source operand (the
third operand) and writes eight assembled bytes for each qword element in the destination operand (the first
operand). Each byte result is selected using a byte-granular shift control within the corresponding qword element
of the first source operand (the second operand). Each byte result in the destination operand is updated under the
writemask k1.
Only the low 6 bits of each control byte are used to select an 8-bit slot to extract the output byte from the qword
data in the second source operand. The starting bit of the 8-bit slot can be unaligned relative to any byte boundary
and is extracted from the input qword source at the location specified in the low 6-bit of the control byte. If the 8-
bit slot would exceed the qword boundary, the out-of-bound portion of the 8-bit slot is wrapped back to start from
bit 0 of the input qword element.
The first source operand is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM reg-
ister, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-bit memory loca-
tion. The destination operand is a ZMM/YMM/XMM register.
5-564
Vol. 2C
VPMULTISHIFTQB—Select Packed Unaligned Bytes From Quadword Sources
INSTRUCTION SET REFERENCE, V
Operation
VPMULTISHIFTQB DEST, SRC1, SRC2 (EVEX encoded version)
(KL, VL) = (2, 128),(4, 256), (8, 512)
FOR i := 0 TO KL-1
IF EVEX.b=1 AND src2 is memory THEN
tcur := src2.qword[0]; //broadcasting
ELSE
tcur := src2.qword[i];
FI;
FOR j := 0 to 7
ctrl := src1.qword[i].byte[j] & 63;
FOR k := 0 to 7
res.bit[k] := tcur.bit[ (ctrl+k) mod 64 ];
ENDFOR
IF k1[i*8+j] or no writemask THEN
DEST.qword[i].byte[j] := res;
ELSE IF zeroing-masking THEN
DEST.qword[i].byte[j] := 0;
ENDFOR
ENDFOR
DEST.qword[MAX_VL-1:VL] := 0;
Intel C/C++ Compiler Intrinsic Equivalent
VPMULTISHIFTQB __m512i _mm512_multishift_epi64_epi8( __m512i a, __m512i b);
VPMULTISHIFTQB __m512i _mm512_mask_multishift_epi64_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);
VPMULTISHIFTQB __m512i _mm512_maskz_multishift_epi64_epi8( __mmask64 k, __m512i a, __m512i b);
VPMULTISHIFTQB __m256i _mm256_multishift_epi64_epi8( __m256i a, __m256i b);
VPMULTISHIFTQB __m256i _mm256_mask_multishift_epi64_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);
VPMULTISHIFTQB __m256i _mm256_maskz_multishift_epi64_epi8( __mmask32 k, __m256i a, __m256i b);
VPMULTISHIFTQB __m128i _mm_multishift_epi64_epi8( __m128i a, __m128i b);
VPMULTISHIFTQB __m128i _mm_mask_multishift_epi64_epi8(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMULTISHIFTQB __m128i _mm_maskz_multishift_epi64_epi8( __mmask8 k, __m128i a, __m128i b);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-50, “Type E4NF Class Exception Conditions.”
VPMULTISHIFTQB—Select Packed Unaligned Bytes From Quadword Sources
Vol. 2C
5-565
INSTRUCTION SET REFERENCE, V
VPOPCNT—Return the Count of Number of Bits Set to 1 in BYTE/WORD/DWORD/QWORD
Opcode/
Op/
64/32
CPUID Feature Flag
Description
Instruction
En
bit Mode
Support
EVEX.128.66.0F38.W0 54 /r
A
V/V
AVX512_BITALG
Counts the number of bits set to one in
VPOPCNTB xmm1{k1}{z},
AVX512VL
xmm2/m128 and puts the result in xmm1 with
xmm2/m128
writemask k1.
EVEX.256.66.0F38.W0 54 /r
A
V/V
AVX512_BITALG
Counts the number of bits set to one in
VPOPCNTB ymm1{k1}{z},
AVX512VL
ymm2/m256 and puts the result in ymm1 with
ymm2/m256
writemask k1.
EVEX.512.66.0F38.W0 54 /r
A
V/V
AVX512_BITALG
Counts the number of bits set to one in
VPOPCNTB zmm1{k1}{z},
zmm2/m512 and puts the result in zmm1 with
zmm2/m512
writemask k1.
EVEX.128.66.0F38.W1 54 /r
A
V/V
AVX512_BITALG
Counts the number of bits set to one in
VPOPCNTW xmm1{k1}{z},
AVX512VL
xmm2/m128 and puts the result in xmm1 with
xmm2/m128
writemask k1.
EVEX.256.66.0F38.W1 54 /r
A
V/V
AVX512_BITALG
Counts the number of bits set to one in
VPOPCNTW ymm1{k1}{z},
AVX512VL
ymm2/m256 and puts the result in ymm1 with
ymm2/m256
writemask k1.
EVEX.512.66.0F38.W1 54 /r
A
V/V
AVX512_BITALG
Counts the number of bits set to one in
VPOPCNTW zmm1{k1}{z},
zmm2/m512 and puts the result in zmm1 with
zmm2/m512
writemask k1.
EVEX.128.66.0F38.W0 55 /r
B
V/V
AVX512_VPOPCNTDQ
Counts the number of bits set to one in
VPOPCNTD xmm1{k1}{z},
AVX512VL
xmm2/m128/m32bcst and puts the result in
xmm2/m128/m32bcst
xmm1 with writemask k1.
EVEX.256.66.0F38.W0 55 /r
B
V/V
AVX512_VPOPCNTDQ
Counts the number of bits set to one in
VPOPCNTD ymm1{k1}{z},
AVX512VL
ymm2/m256/m32bcst and puts the result in
ymm2/m256/m32bcst
ymm1 with writemask k1.
EVEX.512.66.0F38.W0 55 /r
B
V/V
AVX512_VPOPCNTDQ
Counts the number of bits set to one in
VPOPCNTD zmm1{k1}{z},
zmm2/m512/m32bcst and puts the result in
zmm2/m512/m32bcst
zmm1 with writemask k1.
EVEX.128.66.0F38.W1 55 /r
B
V/V
AVX512_VPOPCNTDQ
Counts the number of bits set to one in
VPOPCNTQ xmm1{k1}{z},
AVX512VL
xmm2/m128/m32bcst and puts the result in
xmm2/m128/m64bcst
xmm1 with writemask k1.
EVEX.256.66.0F38.W1 55 /r
B
V/V
AVX512_VPOPCNTDQ
Counts the number of bits set to one in
VPOPCNTQ ymm1{k1}{z},
AVX512VL
ymm2/m256/m32bcst and puts the result in
ymm2/m256/m64bcst
ymm1 with writemask k1.
EVEX.512.66.0F38.W1 55 /r
B
V/V
AVX512_VPOPCNTDQ
Counts the number of bits set to one in
VPOPCNTQ zmm1{k1}{z},
zmm2/m512/m64bcst and puts the result in
zmm2/m512/m64bcst
zmm1 with writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full Mem
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
B
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction counts the number of bits set to one in each byte, word, dword or qword element of its source (e.g.,
zmm2 or memory) and places the results in the destination register (zmm1). This instruction supports memory
fault suppression.
5-566
Vol. 2C
VPOPCNT—Return the Count of Number of Bits Set to 1 in BYTE/WORD/DWORD/QWORD
INSTRUCTION SET REFERENCE, V
Operation
VPOPCNTB
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j := 0 TO KL-1:
IF MaskBit(j) OR *no writemask*:
DEST.byte[j] := POPCNT(SRC.byte[j])
ELSE IF *merging-masking*:
*DEST.byte[j] remains unchanged*
ELSE:
DEST.byte[j] := 0
DEST[MAX_VL-1:VL] := 0
VPOPCNTW
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1:
IF MaskBit(j) OR *no writemask*:
DEST.word[j] := POPCNT(SRC.word[j])
ELSE IF *merging-masking*:
*DEST.word[j] remains unchanged*
ELSE:
DEST.word[j] := 0
DEST[MAX_VL-1:VL] := 0
VPOPCNTD
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1:
IF MaskBit(j) OR *no writemask*:
IF SRC is broadcast memop:
t := SRC.dword[0]
ELSE:
t := SRC.dword[j]
DEST.dword[j] := POPCNT(t)
ELSE IF *merging-masking*:
*DEST..dword[j] remains unchanged*
ELSE:
DEST..dword[j] := 0
DEST[MAX_VL-1:VL] := 0
VPOPCNTQ
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1:
IF MaskBit(j) OR *no writemask*:
IF SRC is broadcast memop:
t := SRC.qword[0]
ELSE:
t := SRC.qword[j]
DEST.qword[j] := POPCNT(t)
ELSE IF *merging-masking*:
*DEST..qword[j] remains unchanged*
ELSE:
DEST..qword[j] := 0
DEST[MAX_VL-1:VL] := 0
VPOPCNT—Return the Count of Number of Bits Set to 1 in BYTE/WORD/DWORD/QWORD
Vol. 2C
5-567
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VPOPCNTW __m128i _mm_popcnt_epi16(__m128i);
VPOPCNTW __m128i _mm_mask_popcnt_epi16(__m128i, __mmask8, __m128i);
VPOPCNTW __m128i _mm_maskz_popcnt_epi16(__mmask8, __m128i);
VPOPCNTW __m256i _mm256_popcnt_epi16(__m256i);
VPOPCNTW __m256i _mm256_mask_popcnt_epi16(__m256i, __mmask16, __m256i);
VPOPCNTW __m256i _mm256_maskz_popcnt_epi16(__mmask16, __m256i);
VPOPCNTW __m512i _mm512_popcnt_epi16(__m512i);
VPOPCNTW __m512i _mm512_mask_popcnt_epi16(__m512i, __mmask32, __m512i);
VPOPCNTW __m512i _mm512_maskz_popcnt_epi16(__mmask32, __m512i);
VPOPCNTQ __m128i _mm_popcnt_epi64(__m128i);
VPOPCNTQ __m128i _mm_mask_popcnt_epi64(__m128i, __mmask8, __m128i);
VPOPCNTQ __m128i _mm_maskz_popcnt_epi64(__mmask8, __m128i);
VPOPCNTQ __m256i _mm256_popcnt_epi64(__m256i);
VPOPCNTQ __m256i _mm256_mask_popcnt_epi64(__m256i, __mmask8, __m256i);
VPOPCNTQ __m256i _mm256_maskz_popcnt_epi64(__mmask8, __m256i);
VPOPCNTQ __m512i _mm512_popcnt_epi64(__m512i);
VPOPCNTQ __m512i _mm512_mask_popcnt_epi64(__m512i, __mmask8, __m512i);
VPOPCNTQ __m512i _mm512_maskz_popcnt_epi64(__mmask8, __m512i);
VPOPCNTD __m128i _mm_popcnt_epi32(__m128i);
VPOPCNTD __m128i _mm_mask_popcnt_epi32(__m128i, __mmask8, __m128i);
VPOPCNTD __m128i _mm_maskz_popcnt_epi32(__mmask8, __m128i);
VPOPCNTD __m256i _mm256_popcnt_epi32(__m256i);
VPOPCNTD __m256i _mm256_mask_popcnt_epi32(__m256i, __mmask8, __m256i);
VPOPCNTD __m256i _mm256_maskz_popcnt_epi32(__mmask8, __m256i);
VPOPCNTD __m512i _mm512_popcnt_epi32(__m512i);
VPOPCNTD __m512i _mm512_mask_popcnt_epi32(__m512i, __mmask16, __m512i);
VPOPCNTD __m512i _mm512_maskz_popcnt_epi32(__mmask16, __m512i);
VPOPCNTB __m128i _mm_popcnt_epi8(__m128i);
VPOPCNTB __m128i _mm_mask_popcnt_epi8(__m128i, __mmask16, __m128i);
VPOPCNTB __m128i _mm_maskz_popcnt_epi8(__mmask16, __m128i);
VPOPCNTB __m256i _mm256_popcnt_epi8(__m256i);
VPOPCNTB __m256i _mm256_mask_popcnt_epi8(__m256i, __mmask32, __m256i);
VPOPCNTB __m256i _mm256_maskz_popcnt_epi8(__mmask32, __m256i);
VPOPCNTB __m512i _mm512_popcnt_epi8(__m512i);
VPOPCNTB __m512i _mm512_mask_popcnt_epi8(__m512i, __mmask64, __m512i);
VPOPCNTB __m512i _mm512_maskz_popcnt_epi8(__mmask64, __m512i);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-49, “Type E4 Class Exception Conditions.”
5-568
Vol. 2C
VPOPCNT—Return the Count of Number of Bits Set to 1 in BYTE/WORD/DWORD/QWORD
INSTRUCTION SET REFERENCE, V
VPROLD/VPROLVD/VPROLQ/VPROLVQ—Bit Rotate Left
Opcode/
Op / En
64/32
CPUID
Description
Instruction
bit Mode
Feature
Support
Flag
EVEX.128.66.0F38.W0 15 /r
B
V/V
AVX512VL
Rotate doublewords in xmm2 left by count in the
VPROLVD xmm1 {k1}{z}, xmm2,
AVX512F
corresponding element of xmm3/m128/m32bcst.
xmm3/m128/m32bcst
Result written to xmm1 under writemask k1.
EVEX.128.66.0F.W0 72 /1 ib
A
V/V
AVX512VL
Rotate doublewords in xmm2/m128/m32bcst left
VPROLD xmm1 {k1}{z},
AVX512F
by imm8. Result written to xmm1 using
xmm2/m128/m32bcst, imm8
writemask k1.
EVEX.128.66.0F38.W1 15 /r
B
V/V
AVX512VL
Rotate quadwords in xmm2 left by count in the
VPROLVQ xmm1 {k1}{z}, xmm2,
AVX512F
corresponding element of xmm3/m128/m64bcst.
xmm3/m128/m64bcst
Result written to xmm1 under writemask k1.
EVEX.128.66.0F.W1 72 /1 ib
A
V/V
AVX512VL
Rotate quadwords in xmm2/m128/m64bcst left
VPROLQ xmm1 {k1}{z},
AVX512F
by imm8. Result written to xmm1 using
xmm2/m128/m64bcst, imm8
writemask k1.
EVEX.256.66.0F38.W0 15 /r
B
V/V
AVX512VL
Rotate doublewords in ymm2 left by count in the
VPROLVD ymm1 {k1}{z}, ymm2,
AVX512F
corresponding element of ymm3/m256/m32bcst.
ymm3/m256/m32bcst
Result written to ymm1 under writemask k1.
EVEX.256.66.0F.W0 72 /1 ib
A
V/V
AVX512VL
Rotate doublewords in ymm2/m256/m32bcst left
VPROLD ymm1 {k1}{z},
AVX512F
by imm8. Result written to ymm1 using
ymm2/m256/m32bcst, imm8
writemask k1.
EVEX.256.66.0F38.W1 15 /r
B
V/V
AVX512VL
Rotate quadwords in ymm2 left by count in the
VPROLVQ ymm1 {k1}{z}, ymm2,
AVX512F
corresponding element of ymm3/m256/m64bcst.
ymm3/m256/m64bcst
Result written to ymm1 under writemask k1.
EVEX.256.66.0F.W1 72 /1 ib
A
V/V
AVX512VL
Rotate quadwords in ymm2/m256/m64bcst left
VPROLQ ymm1 {k1}{z},
AVX512F
by imm8. Result written to ymm1 using
ymm2/m256/m64bcst, imm8
writemask k1.
EVEX.512.66.0F38.W0 15 /r
B
V/V
AVX512F
Rotate left of doublewords in zmm2 by count in
VPROLVD zmm1 {k1}{z}, zmm2,
the corresponding element of
zmm3/m512/m32bcst
zmm3/m512/m32bcst. Result written to zmm1
using writemask k1.
EVEX.512.66.0F.W0 72 /1 ib
A
V/V
AVX512F
Rotate left of doublewords in
VPROLD zmm1 {k1}{z},
zmm3/m512/m32bcst by imm8. Result written to
zmm2/m512/m32bcst, imm8
zmm1 using writemask k1.
EVEX.512.66.0F38.W1 15 /r
B
V/V
AVX512F
Rotate quadwords in zmm2 left by count in the
VPROLVQ zmm1 {k1}{z}, zmm2,
corresponding element of zmm3/m512/m64bcst.
zmm3/m512/m64bcst
Result written to zmm1under writemask k1.
EVEX.512.66.0F.W1 72 /1 ib
A
V/V
AVX512F
Rotate quadwords in zmm2/m512/m64bcst left
VPROLQ zmm1 {k1}{z},
by imm8. Result written to zmm1 using
zmm2/m512/m64bcst, imm8
writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
VEX.vvvv (w)
ModRM:r/m (R)
imm8
N/A
B
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
VPROLD/VPROLVD/VPROLQ/VPROLVQ—Bit Rotate Left
Vol. 2C
5-569
INSTRUCTION SET REFERENCE, V
Description
Rotates the bits in the individual data elements (doublewords, or quadword) in the first source operand to the left
by the number of bits specified in the count operand. If the value specified by the count operand is greater than 31
(for doublewords), or 63 (for a quadword), then the count operand modulo the data size (32 or 64) is used.
EVEX.128 encoded version: The destination operand is a XMM register. The source operand is a XMM register or a
memory location (for immediate form). The count operand can come either from an XMM register or a memory
location or an 8-bit immediate. Bits (MAXVL-1:128) of the corresponding ZMM register are zeroed.
EVEX.256 encoded version: The destination operand is a YMM register. The source operand is a YMM register or a
memory location (for immediate form). The count operand can come either from an XMM register or a memory
location or an 8-bit immediate. Bits (MAXVL-1:256) of the corresponding ZMM register are zeroed.
EVEX.512 encoded version: The destination operand is a ZMM register updated according to the writemask. For the
count operand in immediate form, the source operand can be a ZMM register, a 512-bit memory location or a 512-
bit vector broadcasted from a 32/64-bit memory location, the count operand is an 8-bit immediate. For the count
operand in variable form, the first source operand (the second operand) is a ZMM register and the counter operand
(the third operand) is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32/64-bit
memory location.
Operation
LEFT_ROTATE_DWORDS(SRC, COUNT_SRC)
COUNT := COUNT_SRC modulo 32;
DEST[31:0] := (SRC << COUNT) | (SRC >> (32 - COUNT));
LEFT_ROTATE_QWORDS(SRC, COUNT_SRC)
COUNT := COUNT_SRC modulo 64;
DEST[63:0] := (SRC << COUNT) | (SRC >> (64 - COUNT));
VPROLD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC1 *is memory*)
THEN DEST[i+31:i] := LEFT_ROTATE_DWORDS(SRC1[31:0], imm8)
ELSE DEST[i+31:i] := LEFT_ROTATE_DWORDS(SRC1[i+31:i], imm8)
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPROLVD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+31:i] := LEFT_ROTATE_DWORDS(SRC1[i+31:i], SRC2[31:0])
ELSE DEST[i+31:i] := LEFT_ROTATE_DWORDS(SRC1[i+31:i], SRC2[i+31:i])
FI;
5-570
Vol. 2C
VPROLD/VPROLVD/VPROLQ/VPROLVQ—Bit Rotate Left
INSTRUCTION SET REFERENCE, V
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPROLQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC1 *is memory*)
THEN DEST[i+63:i] := LEFT_ROTATE_QWORDS(SRC1[63:0], imm8)
ELSE DEST[i+63:i] := LEFT_ROTATE_QWORDS(SRC1[i+63:i], imm8)
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPROLVQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+63:i] := LEFT_ROTATE_QWORDS(SRC1[i+63:i], SRC2[63:0])
ELSE DEST[i+63:i] := LEFT_ROTATE_QWORDS(SRC1[i+63:i], SRC2[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPROLD/VPROLVD/VPROLQ/VPROLVQ—Bit Rotate Left
Vol. 2C
5-571
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VPROLD __m512i _mm512_rol_epi32(__m512i a, int imm);
VPROLD __m512i _mm512_mask_rol_epi32(__m512i a, __mmask16 k, __m512i b, int imm);
VPROLD __m512i _mm512_maskz_rol_epi32( __mmask16 k, __m512i a, int imm);
VPROLD __m256i _mm256_rol_epi32(__m256i a, int imm);
VPROLD __m256i _mm256_mask_rol_epi32(__m256i a, __mmask8 k, __m256i b, int imm);
VPROLD __m256i _mm256_maskz_rol_epi32( __mmask8 k, __m256i a, int imm);
VPROLD __m128i _mm_rol_epi32(__m128i a, int imm);
VPROLD __m128i _mm_mask_rol_epi32(__m128i a, __mmask8 k, __m128i b, int imm);
VPROLD __m128i _mm_maskz_rol_epi32( __mmask8 k, __m128i a, int imm);
VPROLQ __m512i _mm512_rol_epi64(__m512i a, int imm);
VPROLQ __m512i _mm512_mask_rol_epi64(__m512i a, __mmask8 k, __m512i b, int imm);
VPROLQ __m512i _mm512_maskz_rol_epi64(__mmask8 k, __m512i a, int imm);
VPROLQ __m256i _mm256_rol_epi64(__m256i a, int imm);
VPROLQ __m256i _mm256_mask_rol_epi64(__m256i a, __mmask8 k, __m256i b, int imm);
VPROLQ __m256i _mm256_maskz_rol_epi64( __mmask8 k, __m256i a, int imm);
VPROLQ __m128i _mm_rol_epi64(__m128i a, int imm);
VPROLQ __m128i _mm_mask_rol_epi64(__m128i a, __mmask8 k, __m128i b, int imm);
VPROLQ __m128i _mm_maskz_rol_epi64( __mmask8 k, __m128i a, int imm);
VPROLVD __m512i _mm512_rolv_epi32(__m512i a, __m512i cnt);
VPROLVD __m512i _mm512_mask_rolv_epi32(__m512i a, __mmask16 k, __m512i b, __m512i cnt);
VPROLVD __m512i _mm512_maskz_rolv_epi32(__mmask16 k, __m512i a, __m512i cnt);
VPROLVD __m256i _mm256_rolv_epi32(__m256i a, __m256i cnt);
VPROLVD __m256i _mm256_mask_rolv_epi32(__m256i a, __mmask8 k, __m256i b, __m256i cnt);
VPROLVD __m256i _mm256_maskz_rolv_epi32(__mmask8 k, __m256i a, __m256i cnt);
VPROLVD __m128i _mm_rolv_epi32(__m128i a, __m128i cnt);
VPROLVD __m128i _mm_mask_rolv_epi32(__m128i a, __mmask8 k, __m128i b, __m128i cnt);
VPROLVD __m128i _mm_maskz_rolv_epi32(__mmask8 k, __m128i a, __m128i cnt);
VPROLVQ __m512i _mm512_rolv_epi64(__m512i a, __m512i cnt);
VPROLVQ __m512i _mm512_mask_rolv_epi64(__m512i a, __mmask8 k, __m512i b, __m512i cnt);
VPROLVQ __m512i _mm512_maskz_rolv_epi64( __mmask8 k, __m512i a, __m512i cnt);
VPROLVQ __m256i _mm256_rolv_epi64(__m256i a, __m256i cnt);
VPROLVQ __m256i _mm256_mask_rolv_epi64(__m256i a, __mmask8 k, __m256i b, __m256i cnt);
VPROLVQ __m256i _mm256_maskz_rolv_epi64(__mmask8 k, __m256i a, __m256i cnt);
VPROLVQ __m128i _mm_rolv_epi64(__m128i a, __m128i cnt);
VPROLVQ __m128i _mm_mask_rolv_epi64(__m128i a, __mmask8 k, __m128i b, __m128i cnt);
VPROLVQ __m128i _mm_maskz_rolv_epi64(__mmask8 k, __m128i a, __m128i cnt);
SIMD Floating-Point Exceptions
None.
Other Exceptions
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”
5-572
Vol. 2C
VPROLD/VPROLVD/VPROLQ/VPROLVQ—Bit Rotate Left
INSTRUCTION SET REFERENCE, V
VPRORD/VPRORVD/VPRORQ/VPRORVQ—Bit Rotate Right
Opcode/
Op / En
64/32
CPUID
Description
Instruction
bit Mode
Feature
Support
Flag
EVEX.128.66.0F38.W0 14 /r
B
V/V
AVX512VL
Rotate doublewords in xmm2 right by count in
VPRORVD xmm1 {k1}{z}, xmm2,
AVX512F
the corresponding element of
xmm3/m128/m32bcst
xmm3/m128/m32bcst, store result using
writemask k1.
EVEX.128.66.0F.W0 72 /0 ib
A
V/V
AVX512VL
Rotate doublewords in xmm2/m128/m32bcst
VPRORD xmm1 {k1}{z},
AVX512F
right by imm8, store result using writemask k1.
xmm2/m128/m32bcst, imm8
EVEX.128.66.0F38.W1 14 /r
B
V/V
AVX512VL
Rotate quadwords in xmm2 right by count in the
VPRORVQ xmm1 {k1}{z}, xmm2,
AVX512F
corresponding element of xmm3/m128/m64bcst,
xmm3/m128/m64bcst
store result using writemask k1.
EVEX.128.66.0F.W1 72 /0 ib
A
V/V
AVX512VL
Rotate quadwords in xmm2/m128/m64bcst right
VPRORQ xmm1 {k1}{z},
AVX512F
by imm8, store result using writemask k1.
xmm2/m128/m64bcst, imm8
EVEX.256.66.0F38.W0 14 /r
B
V/V
AVX512VL
Rotate doublewords in ymm2 right by count in
VPRORVD ymm1 {k1}{z}, ymm2,
AVX512F
the corresponding element of
ymm3/m256/m32bcst
ymm3/m256/m32bcst, store using result
writemask k1.
EVEX.256.66.0F.W0 72 /0 ib
A
V/V
AVX512VL
Rotate doublewords in ymm2/m256/m32bcst
VPRORD ymm1 {k1}{z},
AVX512F
right by imm8, store result using writemask k1.
ymm2/m256/m32bcst, imm8
EVEX.256.66.0F38.W1 14 /r
B
V/V
AVX512VL
Rotate quadwords in ymm2 right by count in the
VPRORVQ ymm1 {k1}{z}, ymm2,
AVX512F
corresponding element of ymm3/m256/m64bcst,
ymm3/m256/m64bcst
store result using writemask k1.
EVEX.256.66.0F.W1 72 /0 ib
A
V/V
AVX512VL
Rotate quadwords in ymm2/m256/m64bcst right
VPRORQ ymm1 {k1}{z},
AVX512F
by imm8, store result using writemask k1.
ymm2/m256/m64bcst, imm8
EVEX.512.66.0F38.W0 14 /r
B
V/V
AVX512F
Rotate doublewords in zmm2 right by count in
VPRORVD zmm1 {k1}{z}, zmm2,
the corresponding element of
zmm3/m512/m32bcst
zmm3/m512/m32bcst, store result using
writemask k1.
EVEX.512.66.0F.W0 72 /0 ib
A
V/V
AVX512F
Rotate doublewords in zmm2/m512/m32bcst
VPRORD zmm1 {k1}{z},
right by imm8, store result using writemask k1.
zmm2/m512/m32bcst, imm8
EVEX.512.66.0F38.W1 14 /r
B
V/V
AVX512F
Rotate quadwords in zmm2 right by count in the
VPRORVQ zmm1 {k1}{z}, zmm2,
corresponding element of zmm3/m512/m64bcst,
zmm3/m512/m64bcst
store result using writemask k1.
EVEX.512.66.0F.W1 72 /0 ib
A
V/V
AVX512F
Rotate quadwords in zmm2/m512/m64bcst right
VPRORQ zmm1 {k1}{z},
by imm8, store result using writemask k1.
zmm2/m512/m64bcst, imm8
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
VEX.vvvv (w)
ModRM:r/m (R)
imm8
N/A
B
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
VPRORD/VPRORVD/VPRORQ/VPRORVQ—Bit Rotate Right
Vol. 2C
5-573
INSTRUCTION SET REFERENCE, V
Description
Rotates the bits in the individual data elements (doublewords, or quadword) in the first source operand to the right
by the number of bits specified in the count operand. If the value specified by the count operand is greater than 31
(for doublewords), or 63 (for a quadword), then the count operand modulo the data size (32 or 64) is used.
EVEX.128 encoded version: The destination operand is a XMM register. The source operand is a XMM register or a
memory location (for immediate form). The count operand can come either from an XMM register or a memory
location or an 8-bit immediate. Bits (MAXVL-1:128) of the corresponding ZMM register are zeroed.
EVEX.256 encoded version: The destination operand is a YMM register. The source operand is a YMM register or a
memory location (for immediate form). The count operand can come either from an XMM register or a memory
location or an 8-bit immediate. Bits (MAXVL-1:256) of the corresponding ZMM register are zeroed.
EVEX.512 encoded version: The destination operand is a ZMM register updated according to the writemask. For the
count operand in immediate form, the source operand can be a ZMM register, a 512-bit memory location or a 512-
bit vector broadcasted from a 32/64-bit memory location, the count operand is an 8-bit immediate. For the count
operand in variable form, the first source operand (the second operand) is a ZMM register and the counter operand
(the third operand) is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32/64-bit
memory location.
Operation
RIGHT_ROTATE_DWORDS(SRC, COUNT_SRC)
COUNT := COUNT_SRC modulo 32;
DEST[31:0] := (SRC >> COUNT) | (SRC << (32 - COUNT));
RIGHT_ROTATE_QWORDS(SRC, COUNT_SRC)
COUNT := COUNT_SRC modulo 64;
DEST[63:0] := (SRC >> COUNT) | (SRC << (64 - COUNT));
VPRORD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC1 *is memory*)
THEN DEST[i+31:i] := RIGHT_ROTATE_DWORDS( SRC1[31:0], imm8)
ELSE DEST[i+31:i] := RIGHT_ROTATE_DWORDS(SRC1[i+31:i], imm8)
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPRORVD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+31:i] := RIGHT_ROTATE_DWORDS(SRC1[i+31:i], SRC2[31:0])
ELSE DEST[i+31:i] := RIGHT_ROTATE_DWORDS(SRC1[i+31:i], SRC2[i+31:i])
FI;
5-574
Vol. 2C
VPRORD/VPRORVD/VPRORQ/VPRORVQ—Bit Rotate Right
INSTRUCTION SET REFERENCE, V
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPRORQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC1 *is memory*)
THEN DEST[i+63:i] := RIGHT_ROTATE_QWORDS(SRC1[63:0], imm8)
ELSE DEST[i+63:i] := RIGHT_ROTATE_QWORDS(SRC1[i+63:i], imm8])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPRORVQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+63:i] := RIGHT_ROTATE_QWORDS(SRC1[i+63:i], SRC2[63:0])
ELSE DEST[i+63:i] := RIGHT_ROTATE_QWORDS(SRC1[i+63:i], SRC2[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE *zeroing-masking*
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPRORD/VPRORVD/VPRORQ/VPRORVQ—Bit Rotate Right
Vol. 2C
5-575
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VPRORD __m512i _mm512_ror_epi32(__m512i a, int imm);
VPRORD __m512i _mm512_mask_ror_epi32(__m512i a, __mmask16 k, __m512i b, int imm);
VPRORD __m512i _mm512_maskz_ror_epi32( __mmask16 k, __m512i a, int imm);
VPRORD __m256i _mm256_ror_epi32(__m256i a, int imm);
VPRORD __m256i _mm256_mask_ror_epi32(__m256i a, __mmask8 k, __m256i b, int imm);
VPRORD __m256i _mm256_maskz_ror_epi32( __mmask8 k, __m256i a, int imm);
VPRORD __m128i _mm_ror_epi32(__m128i a, int imm);
VPRORD __m128i _mm_mask_ror_epi32(__m128i a, __mmask8 k, __m128i b, int imm);
VPRORD __m128i _mm_maskz_ror_epi32( __mmask8 k, __m128i a, int imm);
VPRORQ __m512i _mm512_ror_epi64(__m512i a, int imm);
VPRORQ __m512i _mm512_mask_ror_epi64(__m512i a, __mmask8 k, __m512i b, int imm);
VPRORQ __m512i _mm512_maskz_ror_epi64(__mmask8 k, __m512i a, int imm);
VPRORQ __m256i _mm256_ror_epi64(__m256i a, int imm);
VPRORQ __m256i _mm256_mask_ror_epi64(__m256i a, __mmask8 k, __m256i b, int imm);
VPRORQ __m256i _mm256_maskz_ror_epi64( __mmask8 k, __m256i a, int imm);
VPRORQ __m128i _mm_ror_epi64(__m128i a, int imm);
VPRORQ __m128i _mm_mask_ror_epi64(__m128i a, __mmask8 k, __m128i b, int imm);
VPRORQ __m128i _mm_maskz_ror_epi64( __mmask8 k, __m128i a, int imm);
VPRORVD __m512i _mm512_rorv_epi32(__m512i a, __m512i cnt);
VPRORVD __m512i _mm512_mask_rorv_epi32(__m512i a, __mmask16 k, __m512i b, __m512i cnt);
VPRORVD __m512i _mm512_maskz_rorv_epi32(__mmask16 k, __m512i a, __m512i cnt);
VPRORVD __m256i _mm256_rorv_epi32(__m256i a, __m256i cnt);
VPRORVD __m256i _mm256_mask_rorv_epi32(__m256i a, __mmask8 k, __m256i b, __m256i cnt);
VPRORVD __m256i _mm256_maskz_rorv_epi32(__mmask8 k, __m256i a, __m256i cnt);
VPRORVD __m128i _mm_rorv_epi32(__m128i a, __m128i cnt);
VPRORVD __m128i _mm_mask_rorv_epi32(__m128i a, __mmask8 k, __m128i b, __m128i cnt);
VPRORVD __m128i _mm_maskz_rorv_epi32(__mmask8 k, __m128i a, __m128i cnt);
VPRORVQ __m512i _mm512_rorv_epi64(__m512i a, __m512i cnt);
VPRORVQ __m512i _mm512_mask_rorv_epi64(__m512i a, __mmask8 k, __m512i b, __m512i cnt);
VPRORVQ __m512i _mm512_maskz_rorv_epi64( __mmask8 k, __m512i a, __m512i cnt);
VPRORVQ __m256i _mm256_rorv_epi64(__m256i a, __m256i cnt);
VPRORVQ __m256i _mm256_mask_rorv_epi64(__m256i a, __mmask8 k, __m256i b, __m256i cnt);
VPRORVQ __m256i _mm256_maskz_rorv_epi64(__mmask8 k, __m256i a, __m256i cnt);
VPRORVQ __m128i _mm_rorv_epi64(__m128i a, __m128i cnt);
VPRORVQ __m128i _mm_mask_rorv_epi64(__m128i a, __mmask8 k, __m128i b, __m128i cnt);
VPRORVQ __m128i _mm_maskz_rorv_epi64(__mmask8 k, __m128i a, __m128i cnt);
SIMD Floating-Point Exceptions
None.
Other Exceptions
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”
5-576
Vol. 2C
VPRORD/VPRORVD/VPRORQ/VPRORVQ—Bit Rotate Right