Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 101
INSTRUCTION SET REFERENCE, V
VBROADCASTI32x2 __m512i _mm512_mask_broadcast_i32x2(__m512i s, __mmask16 k, __m128i a);
VBROADCASTI32x2 __m512i _mm512_maskz_broadcast_i32x2( __mmask16 k, __m128i a);
VBROADCASTI32x2 __m256i _mm256_broadcast_i32x2( __m128i a);
VBROADCASTI32x2 __m256i _mm256_mask_broadcast_i32x2(__m256i s, __mmask8 k, __m128i a);
VBROADCASTI32x2 __m256i _mm256_maskz_broadcast_i32x2( __mmask8 k, __m128i a);
VBROADCASTI32x2 __m128i _mm_broadcast_i32x2(__m128i a);
VBROADCASTI32x2 __m128i _mm_mask_broadcast_i32x2(__m128i s, __mmask8 k, __m128i a);
VBROADCASTI32x2 __m128i _mm_maskz_broadcast_i32x2( __mmask8 k, __m128i a);
VBROADCASTI32x4 __m512i _mm512_broadcast_i32x4( __m128i a);
VBROADCASTI32x4 __m512i _mm512_mask_broadcast_i32x4(__m512i s, __mmask16 k, __m128i a);
VBROADCASTI32x4 __m512i _mm512_maskz_broadcast_i32x4( __mmask16 k, __m128i a);
VBROADCASTI32x4 __m256i _mm256_broadcast_i32x4( __m128i a);
VBROADCASTI32x4 __m256i _mm256_mask_broadcast_i32x4(__m256i s, __mmask8 k, __m128i a);
VBROADCASTI32x4 __m256i _mm256_maskz_broadcast_i32x4( __mmask8 k, __m128i a);
VBROADCASTI32x8 __m512i _mm512_broadcast_i32x8( __m256i a);
VBROADCASTI32x8 __m512i _mm512_mask_broadcast_i32x8(__m512i s, __mmask16 k, __m256i a);
VBROADCASTI32x8 __m512i _mm512_maskz_broadcast_i32x8( __mmask16 k, __m256i a);
VBROADCASTI64x2 __m512i _mm512_broadcast_i64x2( __m128i a);
VBROADCASTI64x2 __m512i _mm512_mask_broadcast_i64x2(__m512i s, __mmask8 k, __m128i a);
VBROADCASTI64x2 __m512i _mm512_maskz_broadcast_i64x2( __mmask8 k, __m128i a);
VBROADCASTI64x2 __m256i _mm256_broadcast_i64x2( __m128i a);
VBROADCASTI64x2 __m256i _mm256_mask_broadcast_i64x2(__m256i s, __mmask8 k, __m128i a);
VBROADCASTI64x2 __m256i _mm256_maskz_broadcast_i64x2( __mmask8 k, __m128i a);
VBROADCASTI64x4 __m512i _mm512_broadcast_i64x4( __m256i a);
VBROADCASTI64x4 __m512i _mm512_mask_broadcast_i64x4(__m512i s, __mmask8 k, __m256i a);
VBROADCASTI64x4 __m512i _mm512_maskz_broadcast_i64x4( __mmask8 k, __m256i a);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instructions, see Table 2-23, “Type 6 Class Exception Conditions.”
EVEX-encoded instructions, syntax with reg/mem operand, see Table 2-53, “Type E6 Class Exception Conditions.”
Additionally:
#UD
If VEX.L = 0 for VPBROADCASTQ, VPBROADCASTI128.
If EVEX.L’L = 0 for VBROADCASTI32X4/VBROADCASTI64X2.
If EVEX.L’L < 10b for VBROADCASTI32X8/VBROADCASTI64X4.
VPBROADCAST—Load Integer and Broadcast
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5-427
INSTRUCTION SET REFERENCE, V
VPBROADCASTM—Broadcast Mask to Vector Register
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.F3.0F38.W1 2A /r
RM
V/V
AVX512VL
Broadcast low byte value in k1 to two locations in xmm1.
VPBROADCASTMB2Q xmm1, k1
AVX512CD
EVEX.256.F3.0F38.W1 2A /r
RM
V/V
AVX512VL
Broadcast low byte value in k1 to four locations in ymm1.
VPBROADCASTMB2Q ymm1, k1
AVX512CD
EVEX.512.F3.0F38.W1 2A /r
RM
V/V
AVX512CD
Broadcast low byte value in k1 to eight locations in zmm1.
VPBROADCASTMB2Q zmm1, k1
EVEX.128.F3.0F38.W0 3A /r
RM
V/V
AVX512VL
Broadcast low word value in k1 to four locations in xmm1.
VPBROADCASTMW2D xmm1, k1
AVX512CD
EVEX.256.F3.0F38.W0 3A /r
RM
V/V
AVX512VL
Broadcast low word value in k1 to eight locations in ymm1.
VPBROADCASTMW2D ymm1, k1
AVX512CD
EVEX.512.F3.0F38.W0 3A /r
RM
V/V
AVX512CD
Broadcast low word value in k1 to sixteen locations in
VPBROADCASTMW2D zmm1, k1
zmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Broadcasts the zero-extended 64/32 bit value of the low byte/word of the source operand (the second operand) to
each 64/32 bit element of the destination operand (the first operand). The source operand is an opmask register.
The destination operand is a ZMM register (EVEX.512), YMM register (EVEX.256), or XMM register (EVEX.128).
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VPBROADCASTMB2Q
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j*64
DEST[i+63:i] := ZeroExtend(SRC[7:0])
ENDFOR
DEST[MAXVL-1:VL] := 0
VPBROADCASTMW2D
(KL, VL) = (4, 128), (8, 256),(16, 512)
FOR j := 0 TO KL-1
i := j*32
DEST[i+31:i] := ZeroExtend(SRC[15:0])
ENDFOR
DEST[MAXVL-1:VL] := 0
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Vol. 2C
VPBROADCASTM—Broadcast Mask to Vector Register
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VPBROADCASTMB2Q __m512i _mm512_broadcastmb_epi64( __mmask8);
VPBROADCASTMW2D __m512i _mm512_broadcastmw_epi32( __mmask16);
VPBROADCASTMB2Q __m256i _mm256_broadcastmb_epi64( __mmask8);
VPBROADCASTMW2D __m256i _mm256_broadcastmw_epi32( __mmask8);
VPBROADCASTMB2Q __m128i _mm_broadcastmb_epi64( __mmask8);
VPBROADCASTMW2D __m128i _mm_broadcastmw_epi32( __mmask8);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Table 2-54, “Type E6NF Class Exception Conditions.”
VPBROADCASTM—Broadcast Mask to Vector Register
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5-429
INSTRUCTION SET REFERENCE, V
VPCMPB/VPCMPUB—Compare Packed Byte Values Into Mask
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F3A.W0 3F /r ib
A
V/V
AVX512VL
Compare packed signed byte values in xmm3/m128 and
VPCMPB k1 {k2}, xmm2,
AVX512BW
xmm2 using bits 2:0 of imm8 as a comparison predicate
xmm3/m128, imm8
with writemask k2 and leave the result in mask register
k1.
EVEX.256.66.0F3A.W0 3F /r ib
A
V/V
AVX512VL
Compare packed signed byte values in ymm3/m256 and
VPCMPB k1 {k2}, ymm2,
AVX512BW
ymm2 using bits 2:0 of imm8 as a comparison predicate
ymm3/m256, imm8
with writemask k2 and leave the result in mask register
k1.
EVEX.512.66.0F3A.W0 3F /r ib
A
V/V
AVX512BW
Compare packed signed byte values in zmm3/m512 and
VPCMPB k1 {k2}, zmm2,
zmm2 using bits 2:0 of imm8 as a comparison predicate
zmm3/m512, imm8
with writemask k2 and leave the result in mask register
k1.
EVEX.128.66.0F3A.W0 3E /r ib
A
V/V
AVX512VL
Compare packed unsigned byte values in xmm3/m128
VPCMPUB k1 {k2}, xmm2,
AVX512BW
and xmm2 using bits 2:0 of imm8 as a comparison
xmm3/m128, imm8
predicate with writemask k2 and leave the result in mask
register k1.
EVEX.256.66.0F3A.W0 3E /r ib
A
V/V
AVX512VL
Compare packed unsigned byte values in ymm3/m256
VPCMPUB k1 {k2}, ymm2,
AVX512BW
and ymm2 using bits 2:0 of imm8 as a comparison
ymm3/m256, imm8
predicate with writemask k2 and leave the result in mask
register k1.
EVEX.512.66.0F3A.W0 3E /r ib
A
V/V
AVX512BW
Compare packed unsigned byte values in zmm3/m512
VPCMPUB k1 {k2}, zmm2,
and zmm2 using bits 2:0 of imm8 as a comparison
zmm3/m512, imm8
predicate with writemask k2 and leave the result in mask
register k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full Mem
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Performs a SIMD compare of the packed byte values in the second source operand and the first source operand and
returns the results of the comparison to the mask destination operand. The comparison predicate operand (imme-
diate byte) specifies the type of comparison performed on each pair of packed values in the two source operands.
The result of each comparison is a single mask bit result of 1 (comparison true) or 0 (comparison false).
VPCMPB performs a comparison between pairs of signed byte values.
VPCMPUB performs a comparison between pairs of unsigned byte values.
The first source operand (second operand) is a ZMM/YMM/XMM register. The second source operand can be a
ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand (first operand) is a mask
register k1. Up to 64/32/16 comparisons are performed with results written to the destination operand under the
writemask k2.
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VPCMPB/VPCMPUB—Compare Packed Byte Values Into Mask
INSTRUCTION SET REFERENCE, V
The comparison predicate operand is an 8-bit immediate: bits 2:0 define the type of comparison to be performed.
Bits 3 through 7 of the immediate are reserved. Compiler can implement the pseudo-op mnemonic listed in Table
5-11.
:
Table 5-11. Pseudo-Op and VPCMP* Implementation
Pseudo-Op
PCMPM Implementation
VPCMPEQ* reg1, reg2, reg3
VPCMP* reg1, reg2, reg3, 0
VPCMPLT* reg1, reg2, reg3
VPCMP*reg1, reg2, reg3, 1
VPCMPLE* reg1, reg2, reg3
VPCMP* reg1, reg2, reg3, 2
VPCMPNEQ* reg1, reg2, reg3
VPCMP* reg1, reg2, reg3, 4
VPPCMPNLT* reg1, reg2, reg3
VPCMP* reg1, reg2, reg3, 5
VPCMPNLE* reg1, reg2, reg3
VPCMP* reg1, reg2, reg3, 6
Operation
CASE (COMPARISON PREDICATE) OF
0: OP := EQ;
1: OP := LT;
2: OP := LE;
3: OP := FALSE;
4: OP := NEQ;
5: OP := NLT;
6: OP := NLE;
7: OP := TRUE;
ESAC;
VPCMPB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j := 0 TO KL-1
i := j * 8
IF k2[j] OR *no writemask*
THEN
CMP := SRC1[i+7:i] OP SRC2[i+7:i];
IF CMP = TRUE
THEN DEST[j] := 1;
ELSE DEST[j] := 0; FI;
ELSE
DEST[j] = 0
; zeroing-masking onlyFI;
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0
VPCMPB/VPCMPUB—Compare Packed Byte Values Into Mask
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INSTRUCTION SET REFERENCE, V
VPCMPUB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j := 0 TO KL-1
i := j * 8
IF k2[j] OR *no writemask*
THEN
CMP := SRC1[i+7:i] OP SRC2[i+7:i];
IF CMP = TRUE
THEN DEST[j] := 1;
ELSE DEST[j] := 0; FI;
ELSE
DEST[j] = 0
; zeroing-masking onlyFI;
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPCMPB __mmask64 _mm512_cmp_epi8_mask( __m512i a, __m512i b, int cmp);
VPCMPB __mmask64 _mm512_mask_cmp_epi8_mask( __mmask64 m, __m512i a, __m512i b, int cmp);
VPCMPB __mmask32 _mm256_cmp_epi8_mask( __m256i a, __m256i b, int cmp);
VPCMPB __mmask32 _mm256_mask_cmp_epi8_mask( __mmask32 m, __m256i a, __m256i b, int cmp);
VPCMPB __mmask16 _mm_cmp_epi8_mask( __m128i a, __m128i b, int cmp);
VPCMPB __mmask16 _mm_mask_cmp_epi8_mask( __mmask16 m, __m128i a, __m128i b, int cmp);
VPCMPB __mmask64 _mm512_cmp[eq|ge|gt|le|lt|neq]_epi8_mask( __m512i a, __m512i b);
VPCMPB __mmask64 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epi8_mask( __mmask64 m, __m512i a, __m512i b);
VPCMPB __mmask32 _mm256_cmp[eq|ge|gt|le|lt|neq]_epi8_mask( __m256i a, __m256i b);
VPCMPB __mmask32 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epi8_mask( __mmask32 m, __m256i a, __m256i b);
VPCMPB __mmask16 _mm_cmp[eq|ge|gt|le|lt|neq]_epi8_mask( __m128i a, __m128i b);
VPCMPB __mmask16 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epi8_mask( __mmask16 m, __m128i a, __m128i b);
VPCMPUB __mmask64 _mm512_cmp_epu8_mask( __m512i a, __m512i b, int cmp);
VPCMPUB __mmask64 _mm512_mask_cmp_epu8_mask( __mmask64 m, __m512i a, __m512i b, int cmp);
VPCMPUB __mmask32 _mm256_cmp_epu8_mask( __m256i a, __m256i b, int cmp);
VPCMPUB __mmask32 _mm256_mask_cmp_epu8_mask( __mmask32 m, __m256i a, __m256i b, int cmp);
VPCMPUB __mmask16 _mm_cmp_epu8_mask( __m128i a, __m128i b, int cmp);
VPCMPUB __mmask16 _mm_mask_cmp_epu8_mask( __mmask16 m, __m128i a, __m128i b, int cmp);
VPCMPUB __mmask64 _mm512_cmp[eq|ge|gt|le|lt|neq]_epu8_mask( __m512i a, __m512i b, int cmp);
VPCMPUB __mmask64 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epu8_mask( __mmask64 m, __m512i a, __m512i b, int cmp);
VPCMPUB __mmask32 _mm256_cmp[eq|ge|gt|le|lt|neq]_epu8_mask( __m256i a, __m256i b, int cmp);
VPCMPUB __mmask32 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epu8_mask( __mmask32 m, __m256i a, __m256i b, int cmp);
VPCMPUB __mmask16 _mm_cmp[eq|ge|gt|le|lt|neq]_epu8_mask( __m128i a, __m128i b, int cmp);
VPCMPUB __mmask16 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epu8_mask( __mmask16 m, __m128i a, __m128i b, int cmp);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”
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VPCMPB/VPCMPUB—Compare Packed Byte Values Into Mask
INSTRUCTION SET REFERENCE, V
VPCMPD/VPCMPUD—Compare Packed Integer Values Into Mask
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F3A.W0 1F /r ib
A
V/V
AVX512VL
Compare packed signed doubleword integer values in
VPCMPD k1 {k2}, xmm2,
AVX512F
xmm3/m128/m32bcst and xmm2 using bits 2:0 of imm8
xmm3/m128/m32bcst, imm8
as a comparison predicate with writemask k2 and leave
the result in mask register k1.
EVEX.256.66.0F3A.W0 1F /r ib
A
V/V
AVX512VL
Compare packed signed doubleword integer values in
VPCMPD k1 {k2}, ymm2,
AVX512F
ymm3/m256/m32bcst and ymm2 using bits 2:0 of imm8
ymm3/m256/m32bcst, imm8
as a comparison predicate with writemask k2 and leave
the result in mask register k1.
EVEX.512.66.0F3A.W0 1F /r ib
A
V/V
AVX512F
Compare packed signed doubleword integer values in
VPCMPD k1 {k2}, zmm2,
zmm2 and zmm3/m512/m32bcst using bits 2:0 of imm8
zmm3/m512/m32bcst, imm8
as a comparison predicate. The comparison results are
written to the destination k1 under writemask k2.
EVEX.128.66.0F3A.W0 1E /r ib
A
V/V
AVX512VL
Compare packed unsigned doubleword integer values in
VPCMPUD k1 {k2}, xmm2,
AVX512F
xmm3/m128/m32bcst and xmm2 using bits 2:0 of imm8
xmm3/m128/m32bcst, imm8
as a comparison predicate with writemask k2 and leave
the result in mask register k1.
EVEX.256.66.0F3A.W0 1E /r ib
A
V/V
AVX512VL
Compare packed unsigned doubleword integer values in
VPCMPUD k1 {k2}, ymm2,
AVX512F
ymm3/m256/m32bcst and ymm2 using bits 2:0 of imm8
ymm3/m256/m32bcst, imm8
as a comparison predicate with writemask k2 and leave
the result in mask register k1.
EVEX.512.66.0F3A.W0 1E /r ib
A
V/V
AVX512F
Compare packed unsigned doubleword integer values in
VPCMPUD k1 {k2}, zmm2,
zmm2 and zmm3/m512/m32bcst using bits 2:0 of imm8
zmm3/m512/m32bcst, imm8
as a comparison predicate. The comparison results are
written to the destination k1 under writemask k2.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
imm8
Description
Performs a SIMD compare of the packed integer values in the second source operand and the first source operand
and returns the results of the comparison to the mask destination operand. The comparison predicate operand
(immediate byte) specifies the type of comparison performed on each pair of packed values in the two source oper-
ands. The result of each comparison is a single mask bit result of 1 (comparison true) or 0 (comparison false).
VPCMPD/VPCMPUD performs a comparison between pairs of signed/unsigned doubleword integer values.
The first source operand (second operand) is a ZMM/YMM/XMM register. The second source operand can be a
ZMM/YMM/XMM register or a 512/256/128-bit memory location or a 512-bit vector broadcasted from a 32-bit
memory location. The destination operand (first operand) is a mask register k1. Up to 16/8/4 comparisons are
performed with results written to the destination operand under the writemask k2.
The comparison predicate operand is an 8-bit immediate: bits 2:0 define the type of comparison to be performed.
Bits 3 through 7 of the immediate are reserved. Compiler can implement the pseudo-op mnemonic listed in Table
5-11.
VPCMPD/VPCMPUD—Compare Packed Integer Values Into Mask
Vol. 2C
5-433
INSTRUCTION SET REFERENCE, V
Operation
CASE (COMPARISON PREDICATE) OF
0: OP := EQ;
1: OP := LT;
2: OP := LE;
3: OP := FALSE;
4: OP := NEQ;
5: OP := NLT;
6: OP := NLE;
7: OP := TRUE;
ESAC;
VPCMPD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k2[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN CMP := SRC1[i+31:i] OP SRC2[31:0];
ELSE CMP := SRC1[i+31:i] OP SRC2[i+31:i];
FI;
IF CMP = TRUE
THEN DEST[j] := 1;
ELSE DEST[j] := 0; FI;
ELSE
DEST[j] := 0
; zeroing-masking onlyFI;
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0
VPCMPUD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k2[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN CMP := SRC1[i+31:i] OP SRC2[31:0];
ELSE CMP := SRC1[i+31:i] OP SRC2[i+31:i];
FI;
IF CMP = TRUE
THEN DEST[j] := 1;
ELSE DEST[j] := 0; FI;
ELSE
DEST[j] := 0
; zeroing-masking onlyFI;
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0
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Vol. 2C
VPCMPD/VPCMPUD—Compare Packed Integer Values Into Mask
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VPCMPD __mmask16 _mm512_cmp_epi32_mask( __m512i a, __m512i b, int imm);
VPCMPD __mmask16 _mm512_mask_cmp_epi32_mask(__mmask16 k, __m512i a, __m512i b, int imm);
VPCMPD __mmask16 _mm512_cmp[eq|ge|gt|le|lt|neq]_epi32_mask( __m512i a, __m512i b);
VPCMPD __mmask16 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epi32_mask(__mmask16 k, __m512i a, __m512i b);
VPCMPUD __mmask16 _mm512_cmp_epu32_mask( __m512i a, __m512i b, int imm);
VPCMPUD __mmask16 _mm512_mask_cmp_epu32_mask(__mmask16 k, __m512i a, __m512i b, int imm);
VPCMPUD __mmask16 _mm512_cmp[eq|ge|gt|le|lt|neq]_epu32_mask( __m512i a, __m512i b);
VPCMPUD __mmask16 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epu32_mask(__mmask16 k, __m512i a, __m512i b);
VPCMPD __mmask8 _mm256_cmp_epi32_mask( __m256i a, __m256i b, int imm);
VPCMPD __mmask8 _mm256_mask_cmp_epi32_mask(__mmask8 k, __m256i a, __m256i b, int imm);
VPCMPD __mmask8 _mm256_cmp[eq|ge|gt|le|lt|neq]_epi32_mask( __m256i a, __m256i b);
VPCMPD __mmask8 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epi32_mask(__mmask8 k, __m256i a, __m256i b);
VPCMPUD __mmask8 _mm256_cmp_epu32_mask( __m256i a, __m256i b, int imm);
VPCMPUD __mmask8 _mm256_mask_cmp_epu32_mask(__mmask8 k, __m256i a, __m256i b, int imm);
VPCMPUD __mmask8 _mm256_cmp[eq|ge|gt|le|lt|neq]_epu32_mask( __m256i a, __m256i b);
VPCMPUD __mmask8 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epu32_mask(__mmask8 k, __m256i a, __m256i b);
VPCMPD __mmask8 _mm_cmp_epi32_mask( __m128i a, __m128i b, int imm);
VPCMPD __mmask8 _mm_mask_cmp_epi32_mask(__mmask8 k, __m128i a, __m128i b, int imm);
VPCMPD __mmask8 _mm_cmp[eq|ge|gt|le|lt|neq]_epi32_mask( __m128i a, __m128i b);
VPCMPD __mmask8 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epi32_mask(__mmask8 k, __m128i a, __m128i b);
VPCMPUD __mmask8 _mm_cmp_epu32_mask( __m128i a, __m128i b, int imm);
VPCMPUD __mmask8 _mm_mask_cmp_epu32_mask(__mmask8 k, __m128i a, __m128i b, int imm);
VPCMPUD __mmask8 _mm_cmp[eq|ge|gt|le|lt|neq]_epu32_mask( __m128i a, __m128i b);
VPCMPUD __mmask8 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epu32_mask(__mmask8 k, __m128i a, __m128i b);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”
VPCMPD/VPCMPUD—Compare Packed Integer Values Into Mask
Vol. 2C
5-435
INSTRUCTION SET REFERENCE, V
VPCMPQ/VPCMPUQ—Compare Packed Integer Values Into Mask
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F3A.W1 1F /r ib
A
V/V
AVX512VL
Compare packed signed quadword integer values in
VPCMPQ k1 {k2}, xmm2,
AVX512F
xmm3/m128/m64bcst and xmm2 using bits 2:0 of imm8
xmm3/m128/m64bcst, imm8
as a comparison predicate with writemask k2 and leave
the result in mask register k1.
EVEX.256.66.0F3A.W1 1F /r ib
A
V/V
AVX512VL
Compare packed signed quadword integer values in
VPCMPQ k1 {k2}, ymm2,
AVX512F
ymm3/m256/m64bcst and ymm2 using bits 2:0 of imm8
ymm3/m256/m64bcst, imm8
as a comparison predicate with writemask k2 and leave
the result in mask register k1.
EVEX.512.66.0F3A.W1 1F /r ib
A
V/V
AVX512F
Compare packed signed quadword integer values in
VPCMPQ k1 {k2}, zmm2,
zmm3/m512/m64bcst and zmm2 using bits 2:0 of imm8
zmm3/m512/m64bcst, imm8
as a comparison predicate with writemask k2 and leave
the result in mask register k1.
EVEX.128.66.0F3A.W1 1E /r ib
A
V/V
AVX512VL
Compare packed unsigned quadword integer values in
VPCMPUQ k1 {k2}, xmm2,
AVX512F
xmm3/m128/m64bcst and xmm2 using bits 2:0 of imm8
xmm3/m128/m64bcst, imm8
as a comparison predicate with writemask k2 and leave
the result in mask register k1.
EVEX.256.66.0F3A.W1 1E /r ib
A
V/V
AVX512VL
Compare packed unsigned quadword integer values in
VPCMPUQ k1 {k2}, ymm2,
AVX512F
ymm3/m256/m64bcst and ymm2 using bits 2:0 of imm8
ymm3/m256/m64bcst, imm8
as a comparison predicate with writemask k2 and leave
the result in mask register k1.
EVEX.512.66.0F3A.W1 1E /r ib
A
V/V
AVX512F
Compare packed unsigned quadword integer values in
VPCMPUQ k1 {k2}, zmm2,
zmm3/m512/m64bcst and zmm2 using bits 2:0 of imm8
zmm3/m512/m64bcst, imm8
as a comparison predicate with writemask k2 and leave
the result in mask register k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
imm8
Description
Performs a SIMD compare of the packed integer values in the second source operand and the first source operand
and returns the results of the comparison to the mask destination operand. The comparison predicate operand
(immediate byte) specifies the type of comparison performed on each pair of packed values in the two source oper-
ands. The result of each comparison is a single mask bit result of 1 (comparison true) or 0 (comparison false).
VPCMPQ/VPCMPUQ performs a comparison between pairs of signed/unsigned quadword integer values.
The first source operand (second operand) is a ZMM/YMM/XMM register. The second source operand can be a
ZMM/YMM/XMM register or a 512/256/128-bit memory location or a 512-bit vector broadcasted from a 64-bit
memory location. The destination operand (first operand) is a mask register k1. Up to 8/4/2 comparisons are
performed with results written to the destination operand under the writemask k2.
The comparison predicate operand is an 8-bit immediate: bits 2:0 define the type of comparison to be performed.
Bits 3 through 7 of the immediate are reserved. Compiler can implement the pseudo-op mnemonic listed in Table
5-11.
5-436
Vol. 2C
VPCMPQ/VPCMPUQ—Compare Packed Integer Values Into Mask
INSTRUCTION SET REFERENCE, V
Operation
CASE (COMPARISON PREDICATE) OF
0: OP := EQ;
1: OP := LT;
2: OP := LE;
3: OP := FALSE;
4: OP := NEQ;
5: OP := NLT;
6: OP := NLE;
7: OP := TRUE;
ESAC;
VPCMPQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k2[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN CMP := SRC1[i+63:i] OP SRC2[63:0];
ELSE CMP := SRC1[i+63:i] OP SRC2[i+63:i];
FI;
IF CMP = TRUE
THEN DEST[j] := 1;
ELSE DEST[j] := 0; FI;
ELSE
DEST[j] := 0
; zeroing-masking only
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0
VPCMPUQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k2[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN CMP := SRC1[i+63:i] OP SRC2[63:0];
ELSE CMP := SRC1[i+63:i] OP SRC2[i+63:i];
FI;
IF CMP = TRUE
THEN DEST[j] := 1;
ELSE DEST[j] := 0; FI;
ELSE
DEST[j] := 0
; zeroing-masking only
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0
VPCMPQ/VPCMPUQ—Compare Packed Integer Values Into Mask
Vol. 2C
5-437
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VPCMPQ __mmask8 _mm512_cmp_epi64_mask( __m512i a, __m512i b, int imm);
VPCMPQ __mmask8 _mm512_mask_cmp_epi64_mask(__mmask8 k, __m512i a, __m512i b, int imm);
VPCMPQ __mmask8 _mm512_cmp[eq|ge|gt|le|lt|neq]_epi64_mask( __m512i a, __m512i b);
VPCMPQ __mmask8 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epi64_mask(__mmask8 k, __m512i a, __m512i b);
VPCMPUQ __mmask8 _mm512_cmp_epu64_mask( __m512i a, __m512i b, int imm);
VPCMPUQ __mmask8 _mm512_mask_cmp_epu64_mask(__mmask8 k, __m512i a, __m512i b, int imm);
VPCMPUQ __mmask8 _mm512_cmp[eq|ge|gt|le|lt|neq]_epu64_mask( __m512i a, __m512i b);
VPCMPUQ __mmask8 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epu64_mask(__mmask8 k, __m512i a, __m512i b);
VPCMPQ __mmask8 _mm256_cmp_epi64_mask( __m256i a, __m256i b, int imm);
VPCMPQ __mmask8 _mm256_mask_cmp_epi64_mask(__mmask8 k, __m256i a, __m256i b, int imm);
VPCMPQ __mmask8 _mm256_cmp[eq|ge|gt|le|lt|neq]_epi64_mask( __m256i a, __m256i b);
VPCMPQ __mmask8 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epi64_mask(__mmask8 k, __m256i a, __m256i b);
VPCMPUQ __mmask8 _mm256_cmp_epu64_mask( __m256i a, __m256i b, int imm);
VPCMPUQ __mmask8 _mm256_mask_cmp_epu64_mask(__mmask8 k, __m256i a, __m256i b, int imm);
VPCMPUQ __mmask8 _mm256_cmp[eq|ge|gt|le|lt|neq]_epu64_mask( __m256i a, __m256i b);
VPCMPUQ __mmask8 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epu64_mask(__mmask8 k, __m256i a, __m256i b);
VPCMPQ __mmask8 _mm_cmp_epi64_mask( __m128i a, __m128i b, int imm);
VPCMPQ __mmask8 _mm_mask_cmp_epi64_mask(__mmask8 k, __m128i a, __m128i b, int imm);
VPCMPQ __mmask8 _mm_cmp[eq|ge|gt|le|lt|neq]_epi64_mask( __m128i a, __m128i b);
VPCMPQ __mmask8 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epi64_mask(__mmask8 k, __m128i a, __m128i b);
VPCMPUQ __mmask8 _mm_cmp_epu64_mask( __m128i a, __m128i b, int imm);
VPCMPUQ __mmask8 _mm_mask_cmp_epu64_mask(__mmask8 k, __m128i a, __m128i b, int imm);
VPCMPUQ __mmask8 _mm_cmp[eq|ge|gt|le|lt|neq]_epu64_mask( __m128i a, __m128i b);
VPCMPUQ __mmask8 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epu64_mask(__mmask8 k, __m128i a, __m128i b);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”
5-438
Vol. 2C
VPCMPQ/VPCMPUQ—Compare Packed Integer Values Into Mask
INSTRUCTION SET REFERENCE, V
VPCMPW/VPCMPUW—Compare Packed Word Values Into Mask
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F3A.W1 3F /r ib
A
V/V
AVX512VL
Compare packed signed word integers in xmm3/m128
VPCMPW k1 {k2}, xmm2,
AVX512BW
and xmm2 using bits 2:0 of imm8 as a comparison
xmm3/m128, imm8
predicate with writemask k2 and leave the result in
mask register k1.
EVEX.256.66.0F3A.W1 3F /r ib
A
V/V
AVX512VL
Compare packed signed word integers in ymm3/m256
VPCMPW k1 {k2}, ymm2,
AVX512BW
and ymm2 using bits 2:0 of imm8 as a comparison
ymm3/m256, imm8
predicate with writemask k2 and leave the result in
mask register k1.
EVEX.512.66.0F3A.W1 3F /r ib
A
V/V
AVX512BW
Compare packed signed word integers in zmm3/m512
VPCMPW k1 {k2}, zmm2,
and zmm2 using bits 2:0 of imm8 as a comparison
zmm3/m512, imm8
predicate with writemask k2 and leave the result in
mask register k1.
EVEX.128.66.0F3A.W1 3E /r ib
A
V/V
AVX512VL
Compare packed unsigned word integers in xmm3/m128
VPCMPUW k1 {k2}, xmm2,
AVX512BW
and xmm2 using bits 2:0 of imm8 as a comparison
xmm3/m128, imm8
predicate with writemask k2 and leave the result in
mask register k1.
EVEX.256.66.0F3A.W1 3E /r ib
A
V/V
AVX512VL
Compare packed unsigned word integers in ymm3/m256
VPCMPUW k1 {k2}, ymm2,
AVX512BW
and ymm2 using bits 2:0 of imm8 as a comparison
ymm3/m256, imm8
predicate with writemask k2 and leave the result in
mask register k1.
EVEX.512.66.0F3A.W1 3E /r ib
A
V/V
AVX512BW
Compare packed unsigned word integers in zmm3/m512
VPCMPUW k1 {k2}, zmm2,
and zmm2 using bits 2:0 of imm8 as a comparison
zmm3/m512, imm8
predicate with writemask k2 and leave the result in
mask register k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full Mem
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Performs a SIMD compare of the packed integer word in the second source operand and the first source operand
and returns the results of the comparison to the mask destination operand. The comparison predicate operand
(immediate byte) specifies the type of comparison performed on each pair of packed values in the two source oper-
ands. The result of each comparison is a single mask bit result of 1 (comparison true) or 0 (comparison false).
VPCMPW performs a comparison between pairs of signed word values.
VPCMPUW performs a comparison between pairs of unsigned word values.
The first source operand (second operand) is a ZMM/YMM/XMM register. The second source operand can be a
ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand (first operand) is a mask
register k1. Up to 32/16/8 comparisons are performed with results written to the destination operand under the
writemask k2.
The comparison predicate operand is an 8-bit immediate: bits 2:0 define the type of comparison to be performed.
Bits 3 through 7 of the immediate are reserved. Compiler can implement the pseudo-op mnemonic listed in Table
5-11.
VPCMPW/VPCMPUW—Compare Packed Word Values Into Mask
Vol. 2C
5-439
INSTRUCTION SET REFERENCE, V
Operation
CASE (COMPARISON PREDICATE) OF
0: OP := EQ;
1: OP := LT;
2: OP := LE;
3: OP := FALSE;
4: OP := NEQ;
5: OP := NLT;
6: OP := NLE;
7: OP := TRUE;
ESAC;
VPCMPW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1
i := j * 16
IF k2[j] OR *no writemask*
THEN
ICMP := SRC1[i+15:i] OP SRC2[i+15:i];
IF CMP = TRUE
THEN DEST[j] := 1;
ELSE DEST[j] := 0; FI;
ELSE
DEST[j] = 0
; zeroing-masking only
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0
VPCMPUW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1
i := j * 16
IF k2[j] OR *no writemask*
THEN
CMP := SRC1[i+15:i] OP SRC2[i+15:i];
IF CMP = TRUE
THEN DEST[j] := 1;
ELSE DEST[j] := 0; FI;
ELSE
DEST[j] = 0
; zeroing-masking only
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0
5-440
Vol. 2C
VPCMPW/VPCMPUW—Compare Packed Word Values Into Mask
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VPCMPW __mmask32 _mm512_cmp_epi16_mask( __m512i a, __m512i b, int cmp);
VPCMPW __mmask32 _mm512_mask_cmp_epi16_mask( __mmask32 m, __m512i a, __m512i b, int cmp);
VPCMPW __mmask16 _mm256_cmp_epi16_mask( __m256i a, __m256i b, int cmp);
VPCMPW __mmask16 _mm256_mask_cmp_epi16_mask( __mmask16 m, __m256i a, __m256i b, int cmp);
VPCMPW __mmask8 _mm_cmp_epi16_mask( __m128i a, __m128i b, int cmp);
VPCMPW __mmask8 _mm_mask_cmp_epi16_mask( __mmask8 m, __m128i a, __m128i b, int cmp);
VPCMPW __mmask32 _mm512_cmp[eq|ge|gt|le|lt|neq]_epi16_mask( __m512i a, __m512i b);
VPCMPW __mmask32 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epi16_mask( __mmask32 m, __m512i a, __m512i b);
VPCMPW __mmask16 _mm256_cmp[eq|ge|gt|le|lt|neq]_epi16_mask( __m256i a, __m256i b);
VPCMPW __mmask16 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epi16_mask( __mmask16 m, __m256i a, __m256i b);
VPCMPW __mmask8 _mm_cmp[eq|ge|gt|le|lt|neq]_epi16_mask( __m128i a, __m128i b);
VPCMPW __mmask8 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epi16_mask( __mmask8 m, __m128i a, __m128i b);
VPCMPUW __mmask32 _mm512_cmp_epu16_mask( __m512i a, __m512i b, int cmp);
VPCMPUW __mmask32 _mm512_mask_cmp_epu16_mask( __mmask32 m, __m512i a, __m512i b, int cmp);
VPCMPUW __mmask16 _mm256_cmp_epu16_mask( __m256i a, __m256i b, int cmp);
VPCMPUW __mmask16 _mm256_mask_cmp_epu16_mask( __mmask16 m, __m256i a, __m256i b, int cmp);
VPCMPUW __mmask8 _mm_cmp_epu16_mask( __m128i a, __m128i b, int cmp);
VPCMPUW __mmask8 _mm_mask_cmp_epu16_mask( __mmask8 m, __m128i a, __m128i b, int cmp);
VPCMPUW __mmask32 _mm512_cmp[eq|ge|gt|le|lt|neq]_epu16_mask( __m512i a, __m512i b, int cmp);
VPCMPUW __mmask32 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epu16_mask( __mmask32 m, __m512i a, __m512i b, int cmp);
VPCMPUW __mmask16 _mm256_cmp[eq|ge|gt|le|lt|neq]_epu16_mask( __m256i a, __m256i b, int cmp);
VPCMPUW __mmask16 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epu16_mask( __mmask16 m, __m256i a, __m256i b, int cmp);
VPCMPUW __mmask8 _mm_cmp[eq|ge|gt|le|lt|neq]_epu16_mask( __m128i a, __m128i b, int cmp);
VPCMPUW __mmask8 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epu16_mask( __mmask8 m, __m128i a, __m128i b, int cmp);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”
VPCMPW/VPCMPUW—Compare Packed Word Values Into Mask
Vol. 2C
5-441
INSTRUCTION SET REFERENCE, V
VPCOMPRESSB/VCOMPRESSW—Store Sparse Packed Byte/Word Integer Values Into Dense
Memory/Register
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.66.0F38.W0 63 /r
A
V/V
AVX512_VBMI2
Compress up to 128 bits of packed byte values
VPCOMPRESSB m128{k1}, xmm1
AVX512VL
from xmm1 to m128 with writemask k1.
EVEX.128.66.0F38.W0 63 /r
B
V/V
AVX512_VBMI2
Compress up to 128 bits of packed byte values
VPCOMPRESSB xmm1{k1}{z}, xmm2
AVX512VL
from xmm2 to xmm1 with writemask k1.
EVEX.256.66.0F38.W0 63 /r
A
V/V
AVX512_VBMI2
Compress up to 256 bits of packed byte values
VPCOMPRESSB m256{k1}, ymm1
AVX512VL
from ymm1 to m256 with writemask k1.
EVEX.256.66.0F38.W0 63 /r
B
V/V
AVX512_VBMI2
Compress up to 256 bits of packed byte values
VPCOMPRESSB ymm1{k1}{z}, ymm2
AVX512VL
from ymm2 to ymm1 with writemask k1.
EVEX.512.66.0F38.W0 63 /r
A
V/V
AVX512_VBMI2
Compress up to 512 bits of packed byte values
VPCOMPRESSB m512{k1}, zmm1
from zmm1 to m512 with writemask k1.
EVEX.512.66.0F38.W0 63 /r
B
V/V
AVX512_VBMI2
Compress up to 512 bits of packed byte values
VPCOMPRESSB zmm1{k1}{z}, zmm2
from zmm2 to zmm1 with writemask k1.
EVEX.128.66.0F38.W1 63 /r
A
V/V
AVX512_VBMI2
Compress up to 128 bits of packed word values
VPCOMPRESSW m128{k1}, xmm1
AVX512VL
from xmm1 to m128 with writemask k1.
EVEX.128.66.0F38.W1 63 /r
B
V/V
AVX512_VBMI2
Compress up to 128 bits of packed word values
VPCOMPRESSW xmm1{k1}{z}, xmm2
AVX512VL
from xmm2 to xmm1 with writemask k1.
EVEX.256.66.0F38.W1 63 /r
A
V/V
AVX512_VBMI2
Compress up to 256 bits of packed word values
VPCOMPRESSW m256{k1}, ymm1
AVX512VL
from ymm1 to m256 with writemask k1.
EVEX.256.66.0F38.W1 63 /r
B
V/V
AVX512_VBMI2
Compress up to 256 bits of packed word values
VPCOMPRESSW ymm1{k1}{z}, ymm2
AVX512VL
from ymm2 to ymm1 with writemask k1.
EVEX.512.66.0F38.W1 63 /r
A
V/V
AVX512_VBMI2
Compress up to 512 bits of packed word values
VPCOMPRESSW m512{k1}, zmm1
from zmm1 to m512 with writemask k1.
EVEX.512.66.0F38.W1 63 /r
B
V/V
AVX512_VBMI2
Compress up to 512 bits of packed word values
VPCOMPRESSW zmm1{k1}{z}, zmm2
from zmm2 to zmm1 with writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Scalar
ModRM:r/m (w)
ModRM:reg (r)
N/A
N/A
B
N/A
ModRM:r/m (w)
ModRM:reg (r)
N/A
N/A
Description
Compress (stores) up to 64 byte values or 32 word values from the source operand (second operand) to the desti-
nation operand (first operand), based on the active elements determined by the writemask operand. Note:
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Moves up to 512 bits of packed byte values from the source operand (second operand) to the destination operand
(first operand). This instruction is used to store partial contents of a vector register into a byte vector or single
memory location using the active elements in operand writemask.
Memory destination version: Only the contiguous vector is written to the destination memory location. EVEX.z
must be zero.
Register destination version: If the vector length of the contiguous vector is less than that of the input vector in the
source operand, the upper bits of the destination register are unmodified if EVEX.z is not set, otherwise the upper
bits are zeroed.
This instruction supports memory fault suppression.
5-442
Vol. 2C
VPCOMPRESSB/VCOMPRESSW—Store Sparse Packed Byte/Word Integer Values Into Dense Memory/Register
INSTRUCTION SET REFERENCE, V
Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element
instead of the size of the full vector.
Operation
VPCOMPRESSB store form
(KL, VL) = (16, 128), (32, 256), (64, 512)
k := 0
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
DEST.byte[k] := SRC.byte[j]
k := k +1
VPCOMPRESSB reg-reg form
(KL, VL) = (16, 128), (32, 256), (64, 512)
k := 0
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
DEST.byte[k] := SRC.byte[j]
k := k + 1
IF *merging-masking*:
*DEST[VL-1:k*8] remains unchanged*
ELSE DEST[VL-1:k*8] := 0
DEST[MAX_VL-1:VL] := 0
VPCOMPRESSW store form
(KL, VL) = (8, 128), (16, 256), (32, 512)
k := 0
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
DEST.word[k] := SRC.word[j]
k := k + 1
VPCOMPRESSW reg-reg form
(KL, VL) = (8, 128), (16, 256), (32, 512)
k := 0
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
DEST.word[k] := SRC.word[j]
k := k + 1
IF *merging-masking*:
*DEST[VL-1:k*16] remains unchanged*
ELSE DEST[VL-1:k*16] := 0
DEST[MAX_VL-1:VL] := 0
VPCOMPRESSB/VCOMPRESSW—Store Sparse Packed Byte/Word Integer Values Into Dense Memory/Register
Vol. 2C
5-443
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VPCOMPRESSB __m128i _mm_mask_compress_epi8(__m128i, __mmask16, __m128i);
VPCOMPRESSB __m128i _mm_maskz_compress_epi8(__mmask16, __m128i);
VPCOMPRESSB __m256i _mm256_mask_compress_epi8(__m256i, __mmask32, __m256i);
VPCOMPRESSB __m256i _mm256_maskz_compress_epi8(__mmask32, __m256i);
VPCOMPRESSB __m512i _mm512_mask_compress_epi8(__m512i, __mmask64, __m512i);
VPCOMPRESSB __m512i _mm512_maskz_compress_epi8(__mmask64, __m512i);
VPCOMPRESSB void _mm_mask_compressstoreu_epi8(void*, __mmask16, __m128i);
VPCOMPRESSB void _mm256_mask_compressstoreu_epi8(void*, __mmask32, __m256i);
VPCOMPRESSB void _mm512_mask_compressstoreu_epi8(void*, __mmask64, __m512i);
VPCOMPRESSW __m128i _mm_mask_compress_epi16(__m128i, __mmask8, __m128i);
VPCOMPRESSW __m128i _mm_maskz_compress_epi16(__mmask8, __m128i);
VPCOMPRESSW __m256i _mm256_mask_compress_epi16(__m256i, __mmask16, __m256i);
VPCOMPRESSW __m256i _mm256_maskz_compress_epi16(__mmask16, __m256i);
VPCOMPRESSW __m512i _mm512_mask_compress_epi16(__m512i, __mmask32, __m512i);
VPCOMPRESSW __m512i _mm512_maskz_compress_epi16(__mmask32, __m512i);
VPCOMPRESSW void _mm_mask_compressstoreu_epi16(void*, __mmask8, __m128i);
VPCOMPRESSW void _mm256_mask_compressstoreu_epi16(void*, __mmask16, __m256i);
VPCOMPRESSW void _mm512_mask_compressstoreu_epi16(void*, __mmask32, __m512i);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-49, “Type E4 Class Exception Conditions.”
5-444
Vol. 2C
VPCOMPRESSB/VCOMPRESSW—Store Sparse Packed Byte/Word Integer Values Into Dense Memory/Register
INSTRUCTION SET REFERENCE, V
VPCOMPRESSD—Store Sparse Packed Doubleword Integer Values Into Dense Memory/Register
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F38.W0 8B /r
A
V/V
AVX512VL
Compress packed doubleword integer values from
VPCOMPRESSD xmm1/m128 {k1}{z}, xmm2
AVX512F
xmm2 to xmm1/m128 using control mask k1.
EVEX.256.66.0F38.W0 8B /r
A
V/V
AVX512VL
Compress packed doubleword integer values from
VPCOMPRESSD ymm1/m256 {k1}{z}, ymm2
AVX512F
ymm2 to ymm1/m256 using control mask k1.
EVEX.512.66.0F38.W0 8B /r
A
V/V
AVX512F
Compress packed doubleword integer values from
VPCOMPRESSD zmm1/m512 {k1}{z}, zmm2
zmm2 to zmm1/m512 using control mask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Scalar
ModRM:r/m (w)
ModRM:reg (r)
N/A
N/A
Description
Compress (store) up to 16/8/4 doubleword integer values from the source operand (second operand) to the desti-
nation operand (first operand). The source operand is a ZMM/YMM/XMM register, the destination operand can be a
ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The opmask register k1 selects the active elements (partial vector or possibly non-contiguous if less than 16 active
elements) from the source operand to compress into a contiguous vector. The contiguous vector is written to the
destination starting from the low element of the destination operand.
Memory destination version: Only the contiguous vector is written to the destination memory location. EVEX.z
must be zero.
Register destination version: If the vector length of the contiguous vector is less than that of the input vector in the
source operand, the upper bits of the destination register are unmodified if EVEX.z is not set, otherwise the upper
bits are zeroed.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element
instead of the size of the full vector.
Operation
VPCOMPRESSD (EVEX encoded versions) store form
(KL, VL) = (4, 128), (8, 256), (16, 512)
SIZE := 32
k := 0
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no controlmask*
THEN
DEST[k+SIZE-1:k] := SRC[i+31:i]
k := k + SIZE
FI;
ENDFOR;
VPCOMPRESSD—Store Sparse Packed Doubleword Integer Values Into Dense Memory/Register
Vol. 2C
5-445
INSTRUCTION SET REFERENCE, V
VPCOMPRESSD (EVEX encoded versions) reg-reg form
(KL, VL) = (4, 128), (8, 256), (16, 512)
SIZE := 32
k := 0
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no controlmask*
THEN
DEST[k+SIZE-1:k] := SRC[i+31:i]
k := k + SIZE
FI;
ENDFOR
IF *merging-masking*
THEN *DEST[VL-1:k] remains unchanged*
ELSE DEST[VL-1:k] := 0
FI
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPCOMPRESSD __m512i _mm512_mask_compress_epi32(__m512i s, __mmask16 c, __m512i a);
VPCOMPRESSD __m512i _mm512_maskz_compress_epi32( __mmask16 c, __m512i a);
VPCOMPRESSD void _mm512_mask_compressstoreu_epi32(void * a, __mmask16 c, __m512i s);
VPCOMPRESSD __m256i _mm256_mask_compress_epi32(__m256i s, __mmask8 c, __m256i a);
VPCOMPRESSD __m256i _mm256_maskz_compress_epi32( __mmask8 c, __m256i a);
VPCOMPRESSD void _mm256_mask_compressstoreu_epi32(void * a, __mmask8 c, __m256i s);
VPCOMPRESSD __m128i _mm_mask_compress_epi32(__m128i s, __mmask8 c, __m128i a);
VPCOMPRESSD __m128i _mm_maskz_compress_epi32( __mmask8 c, __m128i a);
VPCOMPRESSD void _mm_mask_compressstoreu_epi32(void * a, __mmask8 c, __m128i s);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”
5-446
Vol. 2C
VPCOMPRESSD—Store Sparse Packed Doubleword Integer Values Into Dense Memory/Register
INSTRUCTION SET REFERENCE, V
VPCOMPRESSQ—Store Sparse Packed Quadword Integer Values Into Dense Memory/Register
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F38.W1 8B /r
A
V/V
AVX512VL
Compress packed quadword integer values from
VPCOMPRESSQ xmm1/m128 {k1}{z}, xmm2
AVX512F
xmm2 to xmm1/m128 using control mask k1.
EVEX.256.66.0F38.W1 8B /r
A
V/V
AVX512VL
Compress packed quadword integer values from
VPCOMPRESSQ ymm1/m256 {k1}{z}, ymm2
AVX512F
ymm2 to ymm1/m256 using control mask k1.
EVEX.512.66.0F38.W1 8B /r
A
V/V
AVX512F
Compress packed quadword integer values from
VPCOMPRESSQ zmm1/m512 {k1}{z}, zmm2
zmm2 to zmm1/m512 using control mask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Scalar
ModRM:r/m (w)
ModRM:reg (r)
N/A
N/A
Description
Compress (stores) up to 8/4/2 quadword integer values from the source operand (second operand) to the destina-
tion operand (first operand). The source operand is a ZMM/YMM/XMM register, the destination operand can be a
ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The opmask register k1 selects the active elements (partial vector or possibly non-contiguous if less than 8 active
elements) from the source operand to compress into a contiguous vector. The contiguous vector is written to the
destination starting from the low element of the destination operand.
Memory destination version: Only the contiguous vector is written to the destination memory location. EVEX.z
must be zero.
Register destination version: If the vector length of the contiguous vector is less than that of the input vector in the
source operand, the upper bits of the destination register are unmodified if EVEX.z is not set, otherwise the upper
bits are zeroed.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element
instead of the size of the full vector.
Operation
VPCOMPRESSQ (EVEX encoded versions) store form
(KL, VL) = (2, 128), (4, 256), (8, 512)
SIZE := 64
k := 0
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no controlmask*
THEN
DEST[k+SIZE-1:k] := SRC[i+63:i]
k := k + SIZE
FI;
ENFOR
VPCOMPRESSQ—Store Sparse Packed Quadword Integer Values Into Dense Memory/Register
Vol. 2C
5-447
INSTRUCTION SET REFERENCE, V
VPCOMPRESSQ (EVEX encoded versions) reg-reg form
(KL, VL) = (2, 128), (4, 256), (8, 512)
SIZE := 64
k := 0
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no controlmask*
THEN
DEST[k+SIZE-1:k] := SRC[i+63:i]
k := k + SIZE
FI;
ENDFOR
IF *merging-masking*
THEN *DEST[VL-1:k] remains unchanged*
ELSE DEST[VL-1:k] := 0
FI
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPCOMPRESSQ __m512i _mm512_mask_compress_epi64(__m512i s, __mmask8 c, __m512i a);
VPCOMPRESSQ __m512i _mm512_maskz_compress_epi64( __mmask8 c, __m512i a);
VPCOMPRESSQ void _mm512_mask_compressstoreu_epi64(void * a, __mmask8 c, __m512i s);
VPCOMPRESSQ __m256i _mm256_mask_compress_epi64(__m256i s, __mmask8 c, __m256i a);
VPCOMPRESSQ __m256i _mm256_maskz_compress_epi64( __mmask8 c, __m256i a);
VPCOMPRESSQ void _mm256_mask_compressstoreu_epi64(void * a, __mmask8 c, __m256i s);
VPCOMPRESSQ __m128i _mm_mask_compress_epi64(__m128i s, __mmask8 c, __m128i a);
VPCOMPRESSQ __m128i _mm_maskz_compress_epi64( __mmask8 c, __m128i a);
VPCOMPRESSQ void _mm_mask_compressstoreu_epi64(void * a, __mmask8 c, __m128i s);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”
5-448
Vol. 2C
VPCOMPRESSQ—Store Sparse Packed Quadword Integer Values Into Dense Memory/Register
INSTRUCTION SET REFERENCE, V
VPCONFLICTD/Q—Detect Conflicts Within a Vector of Packed Dword/Qword Values Into Dense
Memory/ Register
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F38.W0 C4 /r
A
V/V
AVX512VL
Detect duplicate double-word values in
VPCONFLICTD xmm1 {k1}{z},
AVX512CD
xmm2/m128/m32bcst using writemask k1.
xmm2/m128/m32bcst
EVEX.256.66.0F38.W0 C4 /r
A
V/V
AVX512VL
Detect duplicate double-word values in
VPCONFLICTD ymm1 {k1}{z},
AVX512CD
ymm2/m256/m32bcst using writemask k1.
ymm2/m256/m32bcst
EVEX.512.66.0F38.W0 C4 /r
A
V/V
AVX512CD
Detect duplicate double-word values in
VPCONFLICTD zmm1 {k1}{z},
zmm2/m512/m32bcst using writemask k1.
zmm2/m512/m32bcst
EVEX.128.66.0F38.W1 C4 /r
A
V/V
AVX512VL
Detect duplicate quad-word values in
VPCONFLICTQ xmm1 {k1}{z},
AVX512CD
xmm2/m128/m64bcst using writemask k1.
xmm2/m128/m64bcst
EVEX.256.66.0F38.W1 C4 /r
A
V/V
AVX512VL
Detect duplicate quad-word values in
VPCONFLICTQ ymm1 {k1}{z},
AVX512CD
ymm2/m256/m64bcst using writemask k1.
ymm2/m256/m64bcst
EVEX.512.66.0F38.W1 C4 /r
A
V/V
AVX512CD
Detect duplicate quad-word values in
VPCONFLICTQ zmm1 {k1}{z},
zmm2/m512/m64bcst using writemask k1.
zmm2/m512/m64bcst
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Test each dword/qword element of the source operand (the second operand) for equality with all other elements in
the source operand closer to the least significant element. Each element’s comparison results form a bit vector,
which is then zero extended and written to the destination according to the writemask.
EVEX.512 encoded version: The source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector
broadcasted from a 32/64-bit memory location. The destination operand is a ZMM register, conditionally updated
using writemask k1.
EVEX.256 encoded version: The source operand is a YMM register, a 256-bit memory location, or a 256-bit vector
broadcasted from a 32/64-bit memory location. The destination operand is a YMM register, conditionally updated
using writemask k1.
EVEX.128 encoded version: The source operand is a XMM register, a 128-bit memory location, or a 128-bit vector
broadcasted from a 32/64-bit memory location. The destination operand is a XMM register, conditionally updated
using writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
VPCONFLICTD/Q—Detect Conflicts Within a Vector of Packed Dword/Qword Values Into Dense Memory/ Register
Vol. 2C
5-449
INSTRUCTION SET REFERENCE, V
Operation
VPCONFLICTD
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j*32
IF MaskBit(j) OR *no writemask*THEN
FOR k := 0 TO j-1
m := k*32
IF ((SRC[i+31:i] = SRC[m+31:m])) THEN
DEST[i+k] := 1
ELSE
DEST[i+k] := 0
FI
ENDFOR
DEST[i+31:i+j] := 0
ELSE
IF *merging-masking* THEN
*DEST[i+31:i] remains unchanged*
ELSE
DEST[i+31:i] := 0
FI
FI
ENDFOR
DEST[MAXVL-1:VL] := 0
VPCONFLICTQ
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j*64
IF MaskBit(j) OR *no writemask*THEN
FOR k := 0 TO j-1
m := k*64
IF ((SRC[i+63:i] = SRC[m+63:m])) THEN
DEST[i+k] := 1
ELSE
DEST[i+k] := 0
FI
ENDFOR
DEST[i+63:i+j] := 0
ELSE
IF *merging-masking* THEN
*DEST[i+63:i] remains unchanged*
ELSE
DEST[i+63:i] := 0
FI
FI
ENDFOR
DEST[MAXVL-1:VL] := 0
5-450
Vol. 2C
VPCONFLICTD/Q—Detect Conflicts Within a Vector of Packed Dword/Qword Values Into Dense Memory/ Register
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VPCONFLICTD __m512i _mm512_conflict_epi32( __m512i a);
VPCONFLICTD __m512i _mm512_mask_conflict_epi32(__m512i s, __mmask16 m, __m512i a);
VPCONFLICTD __m512i _mm512_maskz_conflict_epi32(__mmask16 m, __m512i a);
VPCONFLICTQ __m512i _mm512_conflict_epi64( __m512i a);
VPCONFLICTQ __m512i _mm512_mask_conflict_epi64(__m512i s, __mmask8 m, __m512i a);
VPCONFLICTQ __m512i _mm512_maskz_conflict_epi64(__mmask8 m, __m512i a);
VPCONFLICTD __m256i _mm256_conflict_epi32( __m256i a);
VPCONFLICTD __m256i _mm256_mask_conflict_epi32(__m256i s, __mmask8 m, __m256i a);
VPCONFLICTD __m256i _mm256_maskz_conflict_epi32(__mmask8 m, __m256i a);
VPCONFLICTQ __m256i _mm256_conflict_epi64( __m256i a);
VPCONFLICTQ __m256i _mm256_mask_conflict_epi64(__m256i s, __mmask8 m, __m256i a);
VPCONFLICTQ __m256i _mm256_maskz_conflict_epi64(__mmask8 m, __m256i a);
VPCONFLICTD __m128i _mm_conflict_epi32( __m128i a);
VPCONFLICTD __m128i _mm_mask_conflict_epi32(__m128i s, __mmask8 m, __m128i a);
VPCONFLICTD __m128i _mm_maskz_conflict_epi32(__mmask8 m, __m128i a);
VPCONFLICTQ __m128i _mm_conflict_epi64( __m128i a);
VPCONFLICTQ __m128i _mm_mask_conflict_epi64(__m128i s, __mmask8 m, __m128i a);
VPCONFLICTQ __m128i _mm_maskz_conflict_epi64(__mmask8 m, __m128i a);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Table 2-50, “Type E4NF Class Exception Conditions.”
VPCONFLICTD/Q—Detect Conflicts Within a Vector of Packed Dword/Qword Values Into Dense Memory/ Register
Vol. 2C
5-451
INSTRUCTION SET REFERENCE, V
VPDPBUSD—Multiply and Add Unsigned and Signed Bytes
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
VEX.128.66.0F38.W0 50 /r
A
V/V
AVX-VNNI
Multiply groups of 4 pairs of signed bytes in
VPDPBUSD xmm1, xmm2,
xmm3/m128 with corresponding unsigned bytes of
xmm3/m128
xmm2, summing those products and adding them
to doubleword result in xmm1.
VEX.256.66.0F38.W0 50 /r
A
V/V
AVX-VNNI
Multiply groups of 4 pairs of signed bytes in
VPDPBUSD ymm1, ymm2,
ymm3/m256 with corresponding unsigned bytes of
ymm3/m256
ymm2, summing those products and adding them
to doubleword result in ymm1.
EVEX.128.66.0F38.W0 50 /r
B
V/V
AVX512_VNNI
Multiply groups of 4 pairs of signed bytes in
VPDPBUSD xmm1{k1}{z}, xmm2,
AVX512VL
xmm3/m128/m32bcst with corresponding
xmm3/m128/m32bcst
unsigned bytes of xmm2, summing those products
and adding them to doubleword result in xmm1
under writemask k1.
EVEX.256.66.0F38.W0 50 /r
B
V/V
AVX512_VNNI
Multiply groups of 4 pairs of signed bytes in
VPDPBUSD ymm1{k1}{z}, ymm2,
AVX512VL
ymm3/m256/m32bcst with corresponding
ymm3/m256/m32bcst
unsigned bytes of ymm2, summing those products
and adding them to doubleword result in ymm1
under writemask k1.
EVEX.512.66.0F38.W0 50 /r
B
V/V
AVX512_VNNI
Multiply groups of 4 pairs of signed bytes in
VPDPBUSD zmm1{k1}{z}, zmm2,
zmm3/m512/m32bcst with corresponding
zmm3/m512/m32bcst
unsigned bytes of zmm2, summing those products
and adding them to doubleword result in zmm1
under writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (r, w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
B
Full
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Multiplies the individual unsigned bytes of the first source operand by the corresponding signed bytes of the second
source operand, producing intermediate signed word results. The word results are then summed and accumulated
in the destination dword element size operand.
This instruction supports memory fault suppression.
Operation
VPDPBUSD dest, src1, src2 (VEX encoded versions)
VL=(128, 256)
KL=VL/32
ORIGDEST := DEST
FOR i := 0 TO KL-1:
// Extending to 16b
// src1extend := ZERO_EXTEND
// src2extend := SIGN_EXTEND
p1word := src1extend(SRC1.byte[4*i+0]) * src2extend(SRC2.byte[4*i+0])
5-452
Vol. 2C
VPDPBUSD—Multiply and Add Unsigned and Signed Bytes
INSTRUCTION SET REFERENCE, V
p2word := src1extend(SRC1.byte[4*i+1]) * src2extend(SRC2.byte[4*i+1])
p3word := src1extend(SRC1.byte[4*i+2]) * src2extend(SRC2.byte[4*i+2])
p4word := src1extend(SRC1.byte[4*i+3]) * src2extend(SRC2.byte[4*i+3])
DEST.dword[i] := ORIGDEST.dword[i] + p1word + p2word + p3word + p4word
DEST[MAX_VL-1:VL] := 0
VPDPBUSD dest, src1, src2 (EVEX encoded versions)
(KL,VL)=(4,128), (8,256), (16,512)
ORIGDEST := DEST
FOR i := 0 TO KL-1:
IF k1[i] or *no writemask*:
// Byte elements of SRC1 are zero-extended to 16b and
// byte elements of SRC2 are sign extended to 16b before multiplication.
IF SRC2 is memory and EVEX.b == 1:
t := SRC2.dword[0]
ELSE:
t := SRC2.dword[i]
p1word := ZERO_EXTEND(SRC1.byte[4*i]) * SIGN_EXTEND(t.byte[0])
p2word := ZERO_EXTEND(SRC1.byte[4*i+1]) * SIGN_EXTEND(t.byte[1])
p3word := ZERO_EXTEND(SRC1.byte[4*i+2]) * SIGN_EXTEND(t.byte[2])
p4word := ZERO_EXTEND(SRC1.byte[4*i+3]) * SIGN_EXTEND(t.byte[3])
DEST.dword[i] := ORIGDEST.dword[i] + p1word + p2word + p3word + p4word
ELSE IF *zeroing*:
DEST.dword[i] := 0
ELSE:
// Merge masking, dest element unchanged
DEST.dword[i] := ORIGDEST.dword[i]
DEST[MAX_VL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPDPBUSD __m128i _mm_dpbusd_avx_epi32(__m128i, __m128i, __m128i);
VPDPBUSD __m128i _mm_dpbusd_epi32(__m128i, __m128i, __m128i);
VPDPBUSD __m128i _mm_mask_dpbusd_epi32(__m128i, __mmask8, __m128i, __m128i);
VPDPBUSD __m128i _mm_maskz_dpbusd_epi32(__mmask8, __m128i, __m128i, __m128i);
VPDPBUSD __m256i _mm256_dpbusd_avx_epi32(__m256i, __m256i, __m256i);
VPDPBUSD __m256i _mm256_dpbusd_epi32(__m256i, __m256i, __m256i);
VPDPBUSD __m256i _mm256_mask_dpbusd_epi32(__m256i, __mmask8, __m256i, __m256i);
VPDPBUSD __m256i _mm256_maskz_dpbusd_epi32(__mmask8, __m256i, __m256i, __m256i);
VPDPBUSD __m512i _mm512_dpbusd_epi32(__m512i, __m512i, __m512i);
VPDPBUSD __m512i _mm512_mask_dpbusd_epi32(__m512i, __mmask16, __m512i, __m512i);
VPDPBUSD __m512i _mm512_maskz_dpbusd_epi32(__mmask16, __m512i, __m512i, __m512i);
SIMD Floating-Point Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions.”
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”
VPDPBUSD—Multiply and Add Unsigned and Signed Bytes
Vol. 2C
5-453
INSTRUCTION SET REFERENCE, V
VPDPBUSDS—Multiply and Add Unsigned and Signed Bytes With Saturation
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
VEX.128.66.0F38.W0 51 /r
A
V/V
AVX-VNNI
Multiply groups of 4 pairs signed bytes in
VPDPBUSDS xmm1, xmm2,
xmm3/m128 with corresponding unsigned
xmm3/m128
bytes of xmm2, summing those products and
adding them to doubleword result, with signed
saturation in xmm1.
VEX.256.66.0F38.W0 51 /r
A
V/V
AVX-VNNI
Multiply groups of 4 pairs signed bytes in
VPDPBUSDS ymm1, ymm2,
ymm3/m256 with corresponding unsigned
ymm3/m256
bytes of ymm2, summing those products and
adding them to doubleword result, with signed
saturation in ymm1.
EVEX.128.66.0F38.W0 51 /r
B
V/V
AVX512_VNNI
Multiply groups of 4 pairs signed bytes in
VPDPBUSDS xmm1{k1}{z}, xmm2,
AVX512VL
xmm3/m128/m32bcst with corresponding
xmm3/m128/m32bcst
unsigned bytes of xmm2, summing those
products and adding them to doubleword
result, with signed saturation in xmm1, under
writemask k1.
EVEX.256.66.0F38.W0 51 /r
B
V/V
AVX512_VNNI
Multiply groups of 4 pairs signed bytes in
VPDPBUSDS ymm1{k1}{z}, ymm2,
AVX512VL
ymm3/m256/m32bcst with corresponding
ymm3/m256/m32bcst
unsigned bytes of ymm2, summing those
products and adding them to doubleword
result, with signed saturation in ymm1, under
writemask k1.
EVEX.512.66.0F38.W0 51 /r
B
V/V
AVX512_VNNI
Multiply groups of 4 pairs signed bytes in
VPDPBUSDS zmm1{k1}{z}, zmm2,
zmm3/m512/m32bcst with corresponding
zmm3/m512/m32bcst
unsigned bytes of zmm2, summing those
products and adding them to doubleword
result, with signed saturation in zmm1, under
writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (r, w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
B
Full
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Multiplies the individual unsigned bytes of the first source operand by the corresponding signed bytes of the second
source operand, producing intermediate signed word results. The word results are then summed and accumulated
in the destination dword element size operand. If the intermediate sum overflows a 32b signed number the result
is saturated to either 0x7FFF_FFFF for positive numbers of 0x8000_0000 for negative numbers.
This instruction supports memory fault suppression.
Operation
VPDPBUSDS dest, src1, src2 (VEX encoded versions)
VL=(128, 256)
KL=VL/32
ORIGDEST := DEST
FOR i := 0 TO KL-1:
5-454
Vol. 2C
VPDPBUSDS—Multiply and Add Unsigned and Signed Bytes With Saturation
INSTRUCTION SET REFERENCE, V
// Extending to 16b
// src1extend := ZERO_EXTEND
// src2extend := SIGN_EXTEND
p1word := src1extend(SRC1.byte[4*i+0]) * src2extend(SRC2.byte[4*i+0])
p2word := src1extend(SRC1.byte[4*i+1]) * src2extend(SRC2.byte[4*i+1])
p3word := src1extend(SRC1.byte[4*i+2]) * src2extend(SRC2.byte[4*i+2])
p4word := src1extend(SRC1.byte[4*i+3]) * src2extend(SRC2.byte[4*i+3])
DEST.dword[i] := SIGNED_DWORD_SATURATE(ORIGDEST.dword[i] + p1word + p2word + p3word + p4word)
DEST[MAX_VL-1:VL] := 0
VPDPBUSDS dest, src1, src2 (EVEX encoded versions)
(KL,VL)=(4,128), (8,256), (16,512)
ORIGDEST := DEST
FOR i := 0 TO KL-1:
IF k1[i] or *no writemask*:
// Byte elements of SRC1 are zero-extended to 16b and
// byte elements of SRC2 are sign extended to 16b before multiplication.
IF SRC2 is memory and EVEX.b == 1:
t := SRC2.dword[0]
ELSE:
t := SRC2.dword[i]
p1word := ZERO_EXTEND(SRC1.byte[4*i]) * SIGN_EXTEND(t.byte[0])
p2word := ZERO_EXTEND(SRC1.byte[4*i+1]) * SIGN_EXTEND(t.byte[1])
p3word := ZERO_EXTEND(SRC1.byte[4*i+2]) * SIGN_EXTEND(t.byte[2])
p4word := ZERO_EXTEND(SRC1.byte[4*i+3]) *SIGN_EXTEND(t.byte[3])
DEST.dword[i] := SIGNED_DWORD_SATURATE(ORIGDEST.dword[i] + p1word + p2word + p3word + p4word)
ELSE IF *zeroing*:
DEST.dword[i] := 0
ELSE:
// Merge masking, dest element unchanged
DEST.dword[i] := ORIGDEST.dword[i]
DEST[MAX_VL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPDPBUSDS __m128i _mm_dpbusds_avx_epi32(__m128i, __m128i, __m128i);
VPDPBUSDS __m128i _mm_dpbusds_epi32(__m128i, __m128i, __m128i);
VPDPBUSDS __m128i _mm_mask_dpbusds_epi32(__m128i, __mmask8, __m128i, __m128i);
VPDPBUSDS __m128i _mm_maskz_dpbusds_epi32(__mmask8, __m128i, __m128i, __m128i);
VPDPBUSDS __m256i _mm256_dpbusds_avx_epi32(__m256i, __m256i, __m256i);
VPDPBUSDS __m256i _mm256_dpbusds_epi32(__m256i, __m256i, __m256i);
VPDPBUSDS __m256i _mm256_mask_dpbusds_epi32(__m256i, __mmask8, __m256i, __m256i);
VPDPBUSDS __m256i _mm256_maskz_dpbusds_epi32(__mmask8, __m256i, __m256i, __m256i);
VPDPBUSDS __m512i _mm512_dpbusds_epi32(__m512i, __m512i, __m512i);
VPDPBUSDS __m512i _mm512_mask_dpbusds_epi32(__m512i, __mmask16, __m512i, __m512i);
VPDPBUSDS __m512i _mm512_maskz_dpbusds_epi32(__mmask16, __m512i, __m512i, __m512i);
SIMD Floating-Point Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions.”
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”
VPDPBUSDS—Multiply and Add Unsigned and Signed Bytes With Saturation
Vol. 2C
5-455
INSTRUCTION SET REFERENCE, V
VPDPWSSD—Multiply and Add Signed Word Integers
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
VEX.128.66.0F38.W0 52 /r
A
V/V
AVX-VNNI
Multiply groups of 2 pairs signed words in
VPDPWSSD xmm1, xmm2,
xmm3/m128 with corresponding signed words
xmm3/m128
of xmm2, summing those products and adding
them to doubleword result in xmm1.
VEX.256.66.0F38.W0 52 /r
A
V/V
AVX-VNNI
Multiply groups of 2 pairs signed words in
VPDPWSSD ymm1, ymm2,
ymm3/m256 with corresponding signed words
ymm3/m256
of ymm2, summing those products and adding
them to doubleword result in ymm1.
EVEX.128.66.0F38.W0 52 /r
B
V/V
AVX512_VNNI
Multiply groups of 2 pairs signed words in
VPDPWSSD xmm1{k1}{z}, xmm2,
AVX512VL
xmm3/m128/m32bcst with corresponding
xmm3/m128/m32bcst
signed words of xmm2, summing those
products and adding them to doubleword result
in xmm1, under writemask k1.
EVEX.256.66.0F38.W0 52 /r
B
V/V
AVX512_VNNI
Multiply groups of 2 pairs signed words in
VPDPWSSD ymm1{k1}{z}, ymm2,
AVX512VL
ymm3/m256/m32bcst with corresponding
ymm3/m256/m32bcst
signed words of ymm2, summing those
products and adding them to doubleword result
in ymm1, under writemask k1.
EVEX.512.66.0F38.W0 52 /r
B
V/V
AVX512_VNNI
Multiply groups of 2 pairs signed words in
VPDPWSSD zmm1{k1}{z}, zmm2,
zmm3/m512/m32bcst with corresponding
zmm3/m512/m32bcst
signed words of zmm2, summing those
products and adding them to doubleword result
in zmm1, under writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (r, w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
B
Full
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Multiplies the individual signed words of the first source operand by the corresponding signed words of the second
source operand, producing intermediate signed, doubleword results. The adjacent doubleword results are then
summed and accumulated in the destination operand.
This instruction supports memory fault suppression.
Operation
VPDPWSSD dest, src1, src2 (VEX encoded versions)
VL=(128, 256)
KL=VL/32
ORIGDEST := DEST
FOR i := 0 TO KL-1:
p1dword := SIGN_EXTEND(SRC1.word[2*i+0]) * SIGN_EXTEND(SRC2.word[2*i+0] )
p2dword := SIGN_EXTEND(SRC1.word[2*i+1]) * SIGN_EXTEND(SRC2.word[2*i+1] )
DEST.dword[i] := ORIGDEST.dword[i] + p1dword + p2dword
DEST[MAX_VL-1:VL] := 0
5-456
Vol. 2C
VPDPWSSD—Multiply and Add Signed Word Integers
INSTRUCTION SET REFERENCE, V
VPDPWSSD dest, src1, src2 (EVEX encoded versions)
(KL,VL)=(4,128), (8,256), (16,512)
ORIGDEST := DEST
FOR i := 0 TO KL-1:
IF k1[i] or *no writemask*:
IF SRC2 is memory and EVEX.b == 1:
t := SRC2.dword[0]
ELSE:
t := SRC2.dword[i]
p1dword := SIGN_EXTEND(SRC1.word[2*i]) * SIGN_EXTEND(t.word[0])
p2dword := SIGN_EXTEND(SRC1.word[2*i+1]) * SIGN_EXTEND(t.word[1])
DEST.dword[i] := ORIGDEST.dword[i] + p1dword + p2dword
ELSE IF *zeroing*:
DEST.dword[i] := 0
ELSE:
// Merge masking, dest element unchanged
DEST.dword[i] := ORIGDEST.dword[i]
DEST[MAX_VL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPDPWSSD __m128i _mm_dpwssd_avx_epi32(__m128i, __m128i, __m128i);
VPDPWSSD __m128i _mm_dpwssd_epi32(__m128i, __m128i, __m128i);
VPDPWSSD __m128i _mm_mask_dpwssd_epi32(__m128i, __mmask8, __m128i, __m128i);
VPDPWSSD __m128i _mm_maskz_dpwssd_epi32(__mmask8, __m128i, __m128i, __m128i);
VPDPWSSD __m256i _mm256_dpwssd_avx_epi32(__m256i, __m256i, __m256i);
VPDPWSSD __m256i _mm256_dpwssd_epi32(__m256i, __m256i, __m256i);
VPDPWSSD __m256i _mm256_mask_dpwssd_epi32(__m256i, __mmask8, __m256i, __m256i);
VPDPWSSD __m256i _mm256_maskz_dpwssd_epi32(__mmask8, __m256i, __m256i, __m256i);
VPDPWSSD __m512i _mm512_dpwssd_epi32(__m512i, __m512i, __m512i);
VPDPWSSD __m512i _mm512_mask_dpwssd_epi32(__m512i, __mmask16, __m512i, __m512i);
VPDPWSSD __m512i _mm512_maskz_dpwssd_epi32(__mmask16, __m512i, __m512i, __m512i);
SIMD Floating-Point Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions.”
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”
VPDPWSSD—Multiply and Add Signed Word Integers
Vol. 2C
5-457
INSTRUCTION SET REFERENCE, V
VPDPWSSDS—Multiply and Add Signed Word Integers With Saturation
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
VEX.128.66.0F38.W0 53 /r
A
V/V
AVX-VNNI
Multiply groups of 2 pairs of signed words in
VPDPWSSDS xmm1, xmm2,
xmm3/m128 with corresponding signed words
xmm3/m128
of xmm2, summing those products and adding
them to doubleword result in xmm1, with
signed saturation.
VEX.256.66.0F38.W0 53 /r
A
V/V
AVX-VNNI
Multiply groups of 2 pairs of signed words in
VPDPWSSDS ymm1, ymm2,
ymm3/m256 with corresponding signed words
ymm3/m256
of ymm2, summing those products and adding
them to doubleword result in ymm1, with
signed saturation.
EVEX.128.66.0F38.W0 53 /r
B
V/V
AVX512_VNNI
Multiply groups of 2 pairs of signed words in
VPDPWSSDS xmm1{k1}{z}, xmm2,
AVX512VL
xmm3/m128/m32bcst with corresponding
xmm3/m128/m32bcst
signed words of xmm2, summing those
products and adding them to doubleword result
in xmm1, with signed saturation, under
writemask k1.
EVEX.256.66.0F38.W0 53 /r
B
V/V
AVX512_VNNI
Multiply groups of 2 pairs of signed words in
VPDPWSSDS ymm1{k1}{z}, ymm2,
AVX512VL
ymm3/m256/m32bcst with corresponding
ymm3/m256/m32bcst
signed words of ymm2, summing those
products and adding them to doubleword result
in ymm1, with signed saturation, under
writemask k1.
EVEX.512.66.0F38.W0 53 /r
B
V/V
AVX512_VNNI
Multiply groups of 2 pairs of signed words in
VPDPWSSDS zmm1{k1}{z}, zmm2,
zmm3/m512/m32bcst with corresponding
zmm3/m512/m32bcst
signed words of zmm2, summing those
products and adding them to doubleword result
in zmm1, with signed saturation, under
writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (r, w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
B
Full
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Multiplies the individual signed words of the first source operand by the corresponding signed words of the second
source operand, producing intermediate signed, doubleword results. The adjacent doubleword results are then
summed and accumulated in the destination operand. If the intermediate sum overflows a 32b signed number, the
result is saturated to either 0x7FFF_FFFF for positive numbers of 0x8000_0000 for negative numbers.
This instruction supports memory fault suppression.
5-458
Vol. 2C
VPDPWSSDS—Multiply and Add Signed Word Integers With Saturation
INSTRUCTION SET REFERENCE, V
Operation
VPDPWSSDS dest, src1, src2 (VEX encoded versions)
VL=(128, 256)
KL=VL/32
ORIGDEST := DEST
FOR i := 0 TO KL-1:
p1dword := SIGN_EXTEND(SRC1.word[2*i+0]) * SIGN_EXTEND(SRC2.word[2*i+0])
p2dword := SIGN_EXTEND(SRC1.word[2*i+1]) * SIGN_EXTEND(SRC2.word[2*i+1])
DEST.dword[i] := SIGNED_DWORD_SATURATE(ORIGDEST.dword[i] + p1dword + p2dword)
DEST[MAX_VL-1:VL] := 0
VPDPWSSDS dest, src1, src2 (EVEX encoded versions)
(KL,VL)=(4,128), (8,256), (16,512)
ORIGDEST := DEST
FOR i := 0 TO KL-1:
IF k1[i] or *no writemask*:
IF SRC2 is memory and EVEX.b == 1:
t := SRC2.dword[0]
ELSE:
t := SRC2.dword[i]
p1dword := SIGN_EXTEND(SRC1.word[2*i]) * SIGN_EXTEND(t.word[0])
p2dword := SIGN_EXTEND(SRC1.word[2*i+1]) * SIGN_EXTEND(t.word[1])
DEST.dword[i] := SIGNED_DWORD_SATURATE(ORIGDEST.dword[i] + p1dword + p2dword)
ELSE IF *zeroing*:
DEST.dword[i] := 0
ELSE:
// Merge masking, dest element unchanged
DEST.dword[i] := ORIGDEST.dword[i]
DEST[MAX_VL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPDPWSSDS __m128i _mm_dpwssds_avx_epi32(__m128i, __m128i, __m128i);
VPDPWSSDS __m128i _mm_dpwssds_epi32(__m128i, __m128i, __m128i);
VPDPWSSDS __m128i _mm_mask_dpwssd_epi32(__m128i, __mmask8, __m128i, __m128i);
VPDPWSSDS __m128i _mm_maskz_dpwssd_epi32(__mmask8, __m128i, __m128i, __m128i);
VPDPWSSDS __m256i _mm256_dpwssds_avx_epi32(__m256i, __m256i, __m256i);
VPDPWSSDS __m256i _mm256_dpwssd_epi32(__m256i, __m256i, __m256i);
VPDPWSSDS __m256i _mm256_mask_dpwssd_epi32(__m256i, __mmask8, __m256i, __m256i);
VPDPWSSDS __m256i _mm256_maskz_dpwssd_epi32(__mmask8, __m256i, __m256i, __m256i);
VPDPWSSDS __m512i _mm512_dpwssd_epi32(__m512i, __m512i, __m512i);
VPDPWSSDS __m512i _mm512_mask_dpwssd_epi32(__m512i, __mmask16, __m512i, __m512i);
VPDPWSSDS __m512i _mm512_maskz_dpwssd_epi32(__mmask16, __m512i, __m512i, __m512i);
SIMD Floating-Point Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions.”
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”
VPDPWSSDS—Multiply and Add Signed Word Integers With Saturation
Vol. 2C
5-459
INSTRUCTION SET REFERENCE, V
VPERM2F128—Permute Floating-Point Values
Opcode/
Op/
64/32 bit
CPUID
Description
Instruction
En
Mode
Feature
Support
Flag
VEX.256.66.0F3A.W0 06 /r ib
RVMI
V/V
AVX
Permute 128-bit floating-point fields in ymm2
VPERM2F128 ymm1, ymm2, ymm3/m256, imm8
and ymm3/mem using controls from imm8 and
store result in ymm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVMI
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
imm8
Description
Permute 128 bit floating-point-containing fields from the first source operand (second operand) and second source
operand (third operand) using bits in the 8-bit immediate and store results in the destination operand (first
operand). The first source operand is a YMM register, the second source operand is a YMM register or a 256-bit
memory location, and the destination operand is a YMM register.
SRC2
Y1
Y0
SRC1
X1
X0
DEST
X0, X1, Y0, or Y1
X0, X1, Y0, or Y1
Figure 5-21. VPERM2F128 Operation
Imm8[1:0] select the source for the first destination 128-bit field, imm8[5:4] select the source for the second
destination field. If imm8[3] is set, the low 128-bit field is zeroed. If imm8[7] is set, the high 128-bit field is zeroed.
VEX.L must be 1, otherwise the instruction will #UD.
5-460
Vol. 2C
VPERM2F128—Permute Floating-Point Values
INSTRUCTION SET REFERENCE, V
Operation
VPERM2F128
CASE IMM8[1:0] of
0: DEST[127:0] := SRC1[127:0]
1: DEST[127:0] := SRC1[255:128]
2: DEST[127:0] := SRC2[127:0]
3: DEST[127:0] := SRC2[255:128]
ESAC
CASE IMM8[5:4] of
0: DEST[255:128] := SRC1[127:0]
1: DEST[255:128] := SRC1[255:128]
2: DEST[255:128] := SRC2[127:0]
3: DEST[255:128] := SRC2[255:128]
ESAC
IF (imm8[3])
DEST[127:0] := 0
FI
IF (imm8[7])
DEST[MAXVL-1:128] := 0
FI
Intel C/C++ Compiler Intrinsic Equivalent
VPERM2F128:
__m256 _mm256_permute2f128_ps (__m256 a, __m256 b, int control)
VPERM2F128:
__m256d _mm256_permute2f128_pd (__m256d a, __m256d b, int control)
VPERM2F128:
__m256i _mm256_permute2f128_si256 (__m256i a, __m256i b, int control)
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-23, “Type 6 Class Exception Conditions.”
Additionally:
#UD
If VEX.L = 0
If VEX.W = 1.
VPERM2F128—Permute Floating-Point Values
Vol. 2C
5-461
INSTRUCTION SET REFERENCE, V
VPERM2I128—Permute Integer Values
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
-bit
Feature
Mode
Flag
VEX.256.66.0F3A.W0 46 /r ib
RVMI
V/V
AVX2
Permute 128-bit integer data in ymm2 and
VPERM2I128 ymm1, ymm2, ymm3/m256, imm8
ymm3/mem using controls from imm8 and
store result in ymm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVMI
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
imm8
Description
Permute 128 bit integer data from the first source operand (second operand) and second source operand (third
operand) using bits in the 8-bit immediate and store results in the destination operand (first operand). The first
source operand is a YMM register, the second source operand is a YMM register or a 256-bit memory location, and
the destination operand is a YMM register.
SRC2
Y1
Y0
SRC1
X1
X0
DEST
X0, X1, Y0, or Y1
X0, X1, Y0, or Y1
Figure 5-22. VPERM2I128 Operation
Imm8[1:0] select the source for the first destination 128-bit field, imm8[5:4] select the source for the second
destination field. If imm8[3] is set, the low 128-bit field is zeroed. If imm8[7] is set, the high 128-bit field is zeroed.
VEX.L must be 1, otherwise the instruction will #UD.
5-462
Vol. 2C
VPERM2I128—Permute Integer Values
INSTRUCTION SET REFERENCE, V
Operation
VPERM2I128
CASE IMM8[1:0] of
0: DEST[127:0] := SRC1[127:0]
1: DEST[127:0] := SRC1[255:128]
2: DEST[127:0] := SRC2[127:0]
3: DEST[127:0] := SRC2[255:128]
ESAC
CASE IMM8[5:4] of
0: DEST[255:128] := SRC1[127:0]
1: DEST[255:128] := SRC1[255:128]
2: DEST[255:128] := SRC2[127:0]
3: DEST[255:128] := SRC2[255:128]
ESAC
IF (imm8[3])
DEST[127:0] := 0
FI
IF (imm8[7])
DEST[255:128] := 0
FI
Intel C/C++ Compiler Intrinsic Equivalent
VPERM2I128: __m256i _mm256_permute2x128_si256 (__m256i a, __m256i b, int control)
SIMD Floating-Point Exceptions
None
Other Exceptions
See Table 2-23, “Type 6 Class Exception Conditions.”
Additionally:
#UD
If VEX.L = 0,
If VEX.W = 1.
VPERM2I128—Permute Integer Values
Vol. 2C
5-463
INSTRUCTION SET REFERENCE, V
VPERMB—Permute Packed Bytes Elements
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.66.0F38.W0 8D /r
A
V/V
AVX512VL
Permute bytes in xmm3/m128 using byte indexes in
VPERMB xmm1 {k1}{z}, xmm2,
AVX512_VBMI
xmm2 and store the result in xmm1 using writemask
xmm3/m128
k1.
EVEX.256.66.0F38.W0 8D /r
A
V/V
AVX512VL
Permute bytes in ymm3/m256 using byte indexes in
VPERMB ymm1 {k1}{z}, ymm2,
AVX512_VBMI
ymm2 and store the result in ymm1 using writemask
ymm3/m256
k1.
EVEX.512.66.0F38.W0 8D /r
A
V/V
AVX512_VBMI
Permute bytes in zmm3/m512 using byte indexes in
VPERMB zmm1 {k1}{z}, zmm2,
zmm2 and store the result in zmm1 using writemask
zmm3/m512
k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full Mem
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Copies bytes from the second source operand (the third operand) to the destination operand (the first operand)
according to the byte indices in the first source operand (the second operand). Note that this instruction permits a
byte in the source operand to be copied to more than one location in the destination operand.
Only the low 6(EVEX.512)/5(EVEX.256)/4(EVEX.128) bits of each byte index is used to select the location of the
source byte from the second source operand.
The first source operand is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM reg-
ister, a 512/256/128-bit memory location. The destination operand is a ZMM/YMM/XMM register updated at byte
granularity by the writemask k1.
Operation
VPERMB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
IF VL = 128:
n := 3;
ELSE IF VL = 256:
n := 4;
ELSE IF VL = 512:
n := 5;
FI;
FOR j := 0 TO KL-1:
id := SRC1[j*8 + n : j*8] ; // location of the source byte
IF k1[j] OR *no writemask* THEN
DEST[j*8 + 7: j*8] := SRC2[id*8 +7: id*8];
ELSE IF zeroing-masking THEN
DEST[j*8 + 7: j*8] := 0;
*ELSE
DEST[j*8 + 7: j*8] remains unchanged*
FI
ENDFOR
DEST[MAX_VL-1:VL] := 0;
5-464
Vol. 2C
VPERMB—Permute Packed Bytes Elements
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VPERMB __m512i _mm512_permutexvar_epi8( __m512i idx, __m512i a);
VPERMB __m512i _mm512_mask_permutexvar_epi8(__m512i s, __mmask64 k, __m512i idx, __m512i a);
VPERMB __m512i _mm512_maskz_permutexvar_epi8( __mmask64 k, __m512i idx, __m512i a);
VPERMB __m256i _mm256_permutexvar_epi8( __m256i idx, __m256i a);
VPERMB __m256i _mm256_mask_permutexvar_epi8(__m256i s, __mmask32 k, __m256i idx, __m256i a);
VPERMB __m256i _mm256_maskz_permutexvar_epi8( __mmask32 k, __m256i idx, __m256i a);
VPERMB __m128i _mm_permutexvar_epi8( __m128i idx, __m128i a);
VPERMB __m128i _mm_mask_permutexvar_epi8(__m128i s, __mmask16 k, __m128i idx, __m128i a);
VPERMB __m128i _mm_maskz_permutexvar_epi8( __mmask16 k, __m128i idx, __m128i a);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Exceptions Type E4NF.nb in Table 2-50, “Type E4NF Class Exception Conditions.”
VPERMB—Permute Packed Bytes Elements
Vol. 2C
5-465
INSTRUCTION SET REFERENCE, V
VPERMD/VPERMW—Permute Packed Doubleword/Word Elements
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
VEX.256.66.0F38.W0 36 /r
A
V/V
AVX2
Permute doublewords in ymm3/m256 using indices in
VPERMD ymm1, ymm2, ymm3/m256
ymm2 and store the result in ymm1.
EVEX.256.66.0F38.W0 36 /r
B
V/V
AVX512VL
Permute doublewords in ymm3/m256/m32bcst using
VPERMD ymm1 {k1}{z}, ymm2,
AVX512F
indexes in ymm2 and store the result in ymm1 using
ymm3/m256/m32bcst
writemask k1.
EVEX.512.66.0F38.W0 36 /r
B
V/V
AVX512F
Permute doublewords in zmm3/m512/m32bcst using
VPERMD zmm1 {k1}{z}, zmm2,
indices in zmm2 and store the result in zmm1 using
zmm3/m512/m32bcst
writemask k1.
EVEX.128.66.0F38.W1 8D /r
C
V/V
AVX512VL
Permute word integers in xmm3/m128 using indexes
VPERMW xmm1 {k1}{z}, xmm2,
AVX512BW
in xmm2 and store the result in xmm1 using writemask
xmm3/m128
k1.
EVEX.256.66.0F38.W1 8D /r
C
V/V
AVX512VL
Permute word integers in ymm3/m256 using indexes
VPERMW ymm1 {k1}{z}, ymm2,
AVX512BW
in ymm2 and store the result in ymm1 using writemask
ymm3/m256
k1.
EVEX.512.66.0F38.W1 8D /r
C
V/V
AVX512BW
Permute word integers in zmm3/m512 using indexes
VPERMW zmm1 {k1}{z}, zmm2,
in zmm2 and store the result in zmm1 using writemask
zmm3/m512
k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
B
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
C
Full Mem
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Copies doublewords (or words) from the second source operand (the third operand) to the destination operand (the
first operand) according to the indices in the first source operand (the second operand). Note that this instruction
permits a doubleword (word) in the source operand to be copied to more than one location in the destination
operand.
VEX.256 encoded VPERMD: The first and second operands are YMM registers, the third operand can be a YMM
register or memory location. Bits (MAXVL-1:256) of the corresponding destination register are zeroed.
EVEX encoded VPERMD: The first and second operands are ZMM/YMM registers, the third operand can be a
ZMM/YMM register, a 512/256-bit memory location or a 512/256-bit vector broadcasted from a 32-bit memory
location. The elements in the destination are updated using the writemask k1.
VPERMW: first and second operands are ZMM/YMM/XMM registers, the third operand can be a ZMM/YMM/XMM
register, or a 512/256/128-bit memory location. The destination is updated using the writemask k1.
EVEX.128 encoded versions: Bits (MAXVL-1:128) of the corresponding ZMM register are zeroed.
5-466
Vol. 2C
VPERMD/VPERMW—Permute Packed Doubleword/Word Elements
INSTRUCTION SET REFERENCE, V
Operation
VPERMD (EVEX encoded versions)
(KL, VL) = (8, 256), (16, 512)
IF VL = 256 THEN n := 2; FI;
IF VL = 512 THEN n := 3; FI;
FOR j := 0 TO KL-1
i := j * 32
id := 32*SRC1[i+n:i]
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+31:i] := SRC2[31:0];
ELSE DEST[i+31:i] := SRC2[id+31:id];
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPERMD (VEX.256 encoded version)
DEST[31:0] := (SRC2[255:0] >> (SRC1[2:0] * 32))[31:0];
DEST[63:32] := (SRC2[255:0] >> (SRC1[34:32] * 32))[31:0];
DEST[95:64] := (SRC2[255:0] >> (SRC1[66:64] * 32))[31:0];
DEST[127:96] := (SRC2[255:0] >> (SRC1[98:96] * 32))[31:0];
DEST[159:128] := (SRC2[255:0] >> (SRC1[130:128] * 32))[31:0];
DEST[191:160] := (SRC2[255:0] >> (SRC1[162:160] * 32))[31:0];
DEST[223:192] := (SRC2[255:0] >> (SRC1[194:192] * 32))[31:0];
DEST[255:224] := (SRC2[255:0] >> (SRC1[226:224] * 32))[31:0];
DEST[MAXVL-1:256] := 0
VPERMW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
IF VL = 128 THEN n := 2; FI;
IF VL = 256 THEN n := 3; FI;
IF VL = 512 THEN n := 4; FI;
FOR j := 0 TO KL-1
i := j * 16
id := 16*SRC1[i+n:i]
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := SRC2[id+15:id]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+15:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPERMD/VPERMW—Permute Packed Doubleword/Word Elements
Vol. 2C
5-467
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VPERMD __m512i _mm512_permutexvar_epi32( __m512i idx, __m512i a);
VPERMD __m512i _mm512_mask_permutexvar_epi32(__m512i s, __mmask16 k, __m512i idx, __m512i a);
VPERMD __m512i _mm512_maskz_permutexvar_epi32( __mmask16 k, __m512i idx, __m512i a);
VPERMD __m256i _mm256_permutexvar_epi32( __m256i idx, __m256i a);
VPERMD __m256i _mm256_mask_permutexvar_epi32(__m256i s, __mmask8 k, __m256i idx, __m256i a);
VPERMD __m256i _mm256_maskz_permutexvar_epi32( __mmask8 k, __m256i idx, __m256i a);
VPERMW __m512i _mm512_permutexvar_epi16( __m512i idx, __m512i a);
VPERMW __m512i _mm512_mask_permutexvar_epi16(__m512i s, __mmask32 k, __m512i idx, __m512i a);
VPERMW __m512i _mm512_maskz_permutexvar_epi16( __mmask32 k, __m512i idx, __m512i a);
VPERMW __m256i _mm256_permutexvar_epi16( __m256i idx, __m256i a);
VPERMW __m256i _mm256_mask_permutexvar_epi16(__m256i s, __mmask16 k, __m256i idx, __m256i a);
VPERMW __m256i _mm256_maskz_permutexvar_epi16( __mmask16 k, __m256i idx, __m256i a);
VPERMW __m128i _mm_permutexvar_epi16( __m128i idx, __m128i a);
VPERMW __m128i _mm_mask_permutexvar_epi16(__m128i s, __mmask8 k, __m128i idx, __m128i a);
VPERMW __m128i _mm_maskz_permutexvar_epi16( __mmask8 k, __m128i idx, __m128i a);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions.”
EVEX-encoded VPERMD, see Table 2-50, “Type E4NF Class Exception Conditions.”
EVEX-encoded VPERMW, see Exceptions Type E4NF.nb in Table 2-50, “Type E4NF Class Exception Conditions.”
Additionally:
#UD
If VEX.L = 0.
If EVEX.L’L = 0 for VPERMD.
5-468
Vol. 2C
VPERMD/VPERMW—Permute Packed Doubleword/Word Elements
INSTRUCTION SET REFERENCE, V
VPERMI2B—Full Permute of Bytes From Two Tables Overwriting the Index
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.66.0F38.W0 75 /r
A
V/V
AVX512VL
Permute bytes in xmm3/m128 and xmm2 using
VPERMI2B xmm1 {k1}{z}, xmm2,
AVX512_VBMI
byte indexes in xmm1 and store the byte results
xmm3/m128
in xmm1 using writemask k1.
EVEX.256.66.0F38.W0 75 /r
A
V/V
AVX512VL
Permute bytes in ymm3/m256 and ymm2 using
VPERMI2B ymm1 {k1}{z}, ymm2,
AVX512_VBMI
byte indexes in ymm1 and store the byte results
ymm3/m256
in ymm1 using writemask k1.
EVEX.512.66.0F38.W0 75 /r
A
V/V
AVX512_VBMI
Permute bytes in zmm3/m512 and zmm2 using
VPERMI2B zmm1 {k1}{z}, zmm2,
byte indexes in zmm1 and store the byte results
zmm3/m512
in zmm1 using writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full Mem
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Permutes byte values in the second operand (the first source operand) and the third operand (the second source
operand) using the byte indices in the first operand (the destination operand) to select byte elements from the
second or third source operands. The selected byte elements are written to the destination at byte granularity
under the writemask k1.
The first and second operands are ZMM/YMM/XMM registers. The first operand contains input indices to select
elements from the two input tables in the 2nd and 3rd operands. The first operand is also the destination of the
result. The third operand can be a ZMM/YMM/XMM register, or a 512/256/128-bit memory location. In each index
byte, the id bit for table selection is bit 6/5/4, and bits [5:0]/[4:0]/[3:0] selects element within each input table.
Note that these instructions permit a byte value in the source operands to be copied to more than one location in
the destination operand. Also, the same tables can be reused in subsequent iterations, but the index elements are
overwritten.
Bits (MAX_VL-1:256/128) of the destination are zeroed for VL=256,128.
VPERMI2B—Full Permute of Bytes From Two Tables Overwriting the Index
Vol. 2C
5-469
INSTRUCTION SET REFERENCE, V
Operation
VPERMI2B (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
IF VL = 128:
id := 3;
ELSE IF VL = 256:
id := 4;
ELSE IF VL = 512:
id := 5;
FI;
TMP_DEST[VL-1:0] := DEST[VL-1:0];
FOR j := 0 TO KL-1
off := 8*SRC1[j*8 + id: j*8] ;
IF k1[j] OR *no writemask*:
DEST[j*8 + 7: j*8] := TMP_DEST[j*8+id+1]? SRC2[off+7:off] : SRC1[off+7:off];
ELSE IF *zeroing-masking*
DEST[j*8 + 7: j*8] := 0;
*ELSE
DEST[j*8 + 7: j*8] remains unchanged*
FI;
ENDFOR
DEST[MAX_VL-1:VL] := 0;
Intel C/C++ Compiler Intrinsic Equivalent
VPERMI2B __m512i _mm512_permutex2var_epi8(__m512i a, __m512i idx, __m512i b);
VPERMI2B __m512i _mm512_mask2_permutex2var_epi8(__m512i a, __m512i idx, __mmask64 k, __m512i b);
VPERMI2B __m512i _mm512_maskz_permutex2var_epi8(__mmask64 k, __m512i a, __m512i idx, __m512i b);
VPERMI2B __m256i _mm256_permutex2var_epi8(__m256i a, __m256i idx, __m256i b);
VPERMI2B __m256i _mm256_mask2_permutex2var_epi8(__m256i a, __m256i idx, __mmask32 k, __m256i b);
VPERMI2B __m256i _mm256_maskz_permutex2var_epi8(__mmask32 k, __m256i a, __m256i idx, __m256i b);
VPERMI2B __m128i _mm_permutex2var_epi8(__m128i a, __m128i idx, __m128i b);
VPERMI2B __m128i _mm_mask2_permutex2var_epi8(__m128i a, __m128i idx, __mmask16 k, __m128i b);
VPERMI2B __m128i _mm_maskz_permutex2var_epi8(__mmask16 k, __m128i a, __m128i idx, __m128i b);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Exceptions Type E4NF.nb in Table 2-50, “Type E4NF Class Exception Conditions.”
5-470
Vol. 2C
VPERMI2B—Full Permute of Bytes From Two Tables Overwriting the Index
INSTRUCTION SET REFERENCE, V
VPERMI2W/D/Q/PS/PD—Full Permute From Two Tables Overwriting the Index
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F38.W1 75 /r
A
V/V
AVX512VL
Permute word integers from two tables in
VPERMI2W xmm1 {k1}{z}, xmm2,
AVX512BW
xmm3/m128 and xmm2 using indexes in xmm1 and
xmm3/m128
store the result in xmm1 using writemask k1.
EVEX.256.66.0F38.W1 75 /r
A
V/V
AVX512VL
Permute word integers from two tables in
VPERMI2W ymm1 {k1}{z}, ymm2,
AVX512BW
ymm3/m256 and ymm2 using indexes in ymm1 and
ymm3/m256
store the result in ymm1 using writemask k1.
EVEX.512.66.0F38.W1 75 /r
A
V/V
AVX512BW
Permute word integers from two tables in
VPERMI2W zmm1 {k1}{z}, zmm2,
zmm3/m512 and zmm2 using indexes in zmm1 and
zmm3/m512
store the result in zmm1 using writemask k1.
EVEX.128.66.0F38.W0 76 /r
B
V/V
AVX512VL
Permute double-words from two tables in
VPERMI2D xmm1 {k1}{z}, xmm2,
AVX512F
xmm3/m128/m32bcst and xmm2 using indexes in
xmm3/m128/m32bcst
xmm1 and store the result in xmm1 using writemask
k1.
EVEX.256.66.0F38.W0 76 /r
B
V/V
AVX512VL
Permute double-words from two tables in
VPERMI2D ymm1 {k1}{z}, ymm2,
AVX512F
ymm3/m256/m32bcst and ymm2 using indexes in
ymm3/m256/m32bcst
ymm1 and store the result in ymm1 using writemask
k1.
EVEX.512.66.0F38.W0 76 /r
B
V/V
AVX512F
Permute double-words from two tables in
VPERMI2D zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst and zmm2 using indices in
zmm3/m512/m32bcst
zmm1 and store the result in zmm1 using writemask
k1.
EVEX.128.66.0F38.W1 76 /r
B
V/V
AVX512VL
Permute quad-words from two tables in
VPERMI2Q xmm1 {k1}{z}, xmm2,
AVX512F
xmm3/m128/m64bcst and xmm2 using indexes in
xmm3/m128/m64bcst
xmm1 and store the result in xmm1 using writemask
k1.
EVEX.256.66.0F38.W1 76 /r
B
V/V
AVX512VL
Permute quad-words from two tables in
VPERMI2Q ymm1 {k1}{z}, ymm2,
AVX512F
ymm3/m256/m64bcst and ymm2 using indexes in
ymm3/m256/m64bcst
ymm1 and store the result in ymm1 using writemask
k1.
EVEX.512.66.0F38.W1 76 /r
B
V/V
AVX512F
Permute quad-words from two tables in
VPERMI2Q zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst and zmm2 using indices in
zmm3/m512/m64bcst
zmm1 and store the result in zmm1 using writemask
k1.
EVEX.128.66.0F38.W0 77 /r
B
V/V
AVX512VL
Permute single-precision floating-point values from
VPERMI2PS xmm1 {k1}{z}, xmm2,
AVX512F
two tables in xmm3/m128/m32bcst and xmm2 using
xmm3/m128/m32bcst
indexes in xmm1 and store the result in xmm1 using
writemask k1.
EVEX.256.66.0F38.W0 77 /r
B
V/V
AVX512VL
Permute single-precision floating-point values from
VPERMI2PS ymm1 {k1}{z}, ymm2,
AVX512F
two tables in ymm3/m256/m32bcst and ymm2 using
ymm3/m256/m32bcst
indexes in ymm1 and store the result in ymm1 using
writemask k1.
EVEX.512.66.0F38.W0 77 /r
B
V/V
AVX512F
Permute single-precision floating-point values from
VPERMI2PS zmm1 {k1}{z}, zmm2,
two tables in zmm3/m512/m32bcst and zmm2 using
zmm3/m512/m32bcst
indices in zmm1 and store the result in zmm1 using
writemask k1.
VPERMI2W/D/Q/PS/PD—Full Permute From Two Tables Overwriting the Index
Vol. 2C
5-471
INSTRUCTION SET REFERENCE, V
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F38.W1 77 /r
B
V/V
AVX512VL
Permute double precision floating-point values from
VPERMI2PD xmm1 {k1}{z}, xmm2,
AVX512F
two tables in xmm3/m128/m64bcst and xmm2 using
xmm3/m128/m64bcst
indexes in xmm1 and store the result in xmm1 using
writemask k1.
EVEX.256.66.0F38.W1 77 /r
B
V/V
AVX512VL
Permute double precision floating-point values from
VPERMI2PD ymm1 {k1}{z}, ymm2,
AVX512F
two tables in ymm3/m256/m64bcst and ymm2 using
ymm3/m256/m64bcst
indexes in ymm1 and store the result in ymm1 using
writemask k1.
EVEX.512.66.0F38.W1 77 /r
B
V/V
AVX512F
Permute double precision floating-point values from
VPERMI2PD zmm1 {k1}{z}, zmm2,
two tables in zmm3/m512/m64bcst and zmm2 using
zmm3/m512/m64bcst
indices in zmm1 and store the result in zmm1 using
writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full Mem
ModRM:reg (r,w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
B
Full
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Permutes 16-bit/32-bit/64-bit values in the second operand (the first source operand) and the third operand (the
second source operand) using indices in the first operand to select elements from the second and third operands.
The selected elements are written to the destination operand (the first operand) according to the writemask k1.
The first and second operands are ZMM/YMM/XMM registers. The first operand contains input indices to select
elements from the two input tables in the 2nd and 3rd operands. The first operand is also the destination of the
result.
D/Q/PS/PD element versions: The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit
memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. Broadcast from the
low 32/64-bit memory location is performed if EVEX.b and the id bit for table selection are set (selecting table_2).
Dword/PS versions: The id bit for table selection is bit 4/3/2, depending on VL=512, 256, 128. Bits
[3:0]/[2:0]/[1:0] of each element in the input index vector select an element within the two source operands, If
the id bit is 0, table_1 (the first source) is selected; otherwise the second source operand is selected.
Qword/PD versions: The id bit for table selection is bit 3/2/1, and bits [2:0]/[1:0] /bit 0 selects element within each
input table.
Word element versions: The second source operand can be a ZMM/YMM/XMM register, or a 512/256/128-bit
memory location. The id bit for table selection is bit 5/4/3, and bits [4:0]/[3:0]/[2:0] selects element within each
input table.
Note that these instructions permit a 16-bit/32-bit/64-bit value in the source operands to be copied to more than
one location in the destination operand. Note also that in this case, the same table can be reused for example for a
second iteration, while the index elements are overwritten.
Bits (MAXVL-1:256/128) of the destination are zeroed for VL=256,128.
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INSTRUCTION SET REFERENCE, V
Operation
VPERMI2W (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
IF VL = 128
id := 2
FI;
IF VL = 256
id := 3
FI;
IF VL = 512
id := 4
FI;
TMP_DEST := DEST
FOR j := 0 TO KL-1
i := j * 16
off := 16*TMP_DEST[i+id:i]
IF k1[j] OR *no writemask*
THEN
DEST[i+15:i]=TMP_DEST[i+id+1] ? SRC2[off+15:off]
: SRC1[off+15:off]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+15:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPERMI2D/VPERMI2PS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF VL = 128
id := 1
FI;
IF VL = 256
id := 2
FI;
IF VL = 512
id := 3
FI;
TMP_DEST := DEST
FOR j := 0 TO KL-1
i := j * 32
off := 32*TMP_DEST[i+id:i]
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
DEST[i+31:i] := TMP_DEST[i+id+1] ? SRC2[31:0]
: SRC1[off+31:off]
ELSE
DEST[i+31:i] := TMP_DEST[i+id+1] ? SRC2[off+31:off]
: SRC1[off+31:off]
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INSTRUCTION SET REFERENCE, V
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPERMI2Q/VPERMI2PD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8 512)
IF VL = 128
id := 0
FI;
IF VL = 256
id := 1
FI;
IF VL = 512
id := 2
FI;
TMP_DEST:= DEST
FOR j := 0 TO KL-1
i := j * 64
off := 64*TMP_DEST[i+id:i]
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
DEST[i+63:i] := TMP_DEST[i+id+1] ? SRC2[63:0]
: SRC1[off+63:off]
ELSE
DEST[i+63:i] := TMP_DEST[i+id+1] ? SRC2[off+63:off]
: SRC1[off+63:off]
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
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INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VPERMI2D __m512i _mm512_permutex2var_epi32(__m512i a, __m512i idx, __m512i b);
VPERMI2D __m512i _mm512_mask_permutex2var_epi32(__m512i a, __mmask16 k, __m512i idx, __m512i b);
VPERMI2D __m512i _mm512_mask2_permutex2var_epi32(__m512i a, __m512i idx, __mmask16 k, __m512i b);
VPERMI2D __m512i _mm512_maskz_permutex2var_epi32(__mmask16 k, __m512i a, __m512i idx, __m512i b);
VPERMI __m256i _mm256_permutex2var_epi32(__m256i a, __m256i idx, __m256i b);
VPERMI2D __m256i _mm256_mask_permutex2var_epi32(__m256i a, __mmask8 k, __m256i idx, __m256i b);
VPERMI2D __m256i _mm256_mask2_permutex2var_epi32(__m256i a, __m256i idx, __mmask8 k, __m256i b);
VPERMI2D __m256i _mm256_maskz_permutex2var_epi32(__mmask8 k, __m256i a, __m256i idx, __m256i b);
VPERMI2D __m128i _mm_permutex2var_epi32(__m128i a, __m128i idx, __m128i b);
VPERMI2D __m128i _mm_mask_permutex2var_epi32(__m128i a, __mmask8 k, __m128i idx, __m128i b);
VPERMI2D __m128i _mm_mask2_permutex2var_epi32(__m128i a, __m128i idx, __mmask8 k, __m128i b);
VPERMI2D __m128i _mm_maskz_permutex2var_epi32(__mmask8 k, __m128i a, __m128i idx, __m128i b);
VPERMI2PD __m512d _mm512_permutex2var_pd(__m512d a, __m512i idx, __m512d b);
VPERMI2PD __m512d _mm512_mask_permutex2var_pd(__m512d a, __mmask8 k, __m512i idx, __m512d b);
VPERMI2PD __m512d _mm512_mask2_permutex2var_pd(__m512d a, __m512i idx, __mmask8 k, __m512d b);
VPERMI2PD __m512d _mm512_maskz_permutex2var_pd(__mmask8 k, __m512d a, __m512i idx, __m512d b);
VPERMI2PD __m256d _mm256_permutex2var_pd(__m256d a, __m256i idx, __m256d b);
VPERMI2PD __m256d _mm256_mask_permutex2var_pd(__m256d a, __mmask8 k, __m256i idx, __m256d b);
VPERMI2PD __m256d _mm256_mask2_permutex2var_pd(__m256d a, __m256i idx, __mmask8 k, __m256d b);
VPERMI2PD __m256d _mm256_maskz_permutex2var_pd(__mmask8 k, __m256d a, __m256i idx, __m256d b);
VPERMI2PD __m128d _mm_permutex2var_pd(__m128d a, __m128i idx, __m128d b);
VPERMI2PD __m128d _mm_mask_permutex2var_pd(__m128d a, __mmask8 k, __m128i idx, __m128d b);
VPERMI2PD __m128d _mm_mask2_permutex2var_pd(__m128d a, __m128i idx, __mmask8 k, __m128d b);
VPERMI2PD __m128d _mm_maskz_permutex2var_pd(__mmask8 k, __m128d a, __m128i idx, __m128d b);
VPERMI2PS __m512 _mm512_permutex2var_ps(__m512 a, __m512i idx, __m512 b);
VPERMI2PS __m512 _mm512_mask_permutex2var_ps(__m512 a, __mmask16 k, __m512i idx, __m512 b);
VPERMI2PS __m512 _mm512_mask2_permutex2var_ps(__m512 a, __m512i idx, __mmask16 k, __m512 b);
VPERMI2PS __m512 _mm512_maskz_permutex2var_ps(__mmask16 k, __m512 a, __m512i idx, __m512 b);
VPERMI2PS __m256 _mm256_permutex2var_ps(__m256 a, __m256i idx, __m256 b);
VPERMI2PS __m256 _mm256_mask_permutex2var_ps(__m256 a, __mmask8 k, __m256i idx, __m256 b);
VPERMI2PS __m256 _mm256_mask2_permutex2var_ps(__m256 a, __m256i idx, __mmask8 k, __m256 b);
VPERMI2PS __m256 _mm256_maskz_permutex2var_ps(__mmask8 k, __m256 a, __m256i idx, __m256 b);
VPERMI2PS __m128 _mm_permutex2var_ps(__m128 a, __m128i idx, __m128 b);
VPERMI2PS __m128 _mm_mask_permutex2var_ps(__m128 a, __mmask8 k, __m128i idx, __m128 b);
VPERMI2PS __m128 _mm_mask2_permutex2var_ps(__m128 a, __m128i idx, __mmask8 k, __m128 b);
VPERMI2PS __m128 _mm_maskz_permutex2var_ps(__mmask8 k, __m128 a, __m128i idx, __m128 b);
VPERMI2Q __m512i _mm512_permutex2var_epi64(__m512i a, __m512i idx, __m512i b);
VPERMI2Q __m512i _mm512_mask_permutex2var_epi64(__m512i a, __mmask8 k, __m512i idx, __m512i b);
VPERMI2Q __m512i _mm512_mask2_permutex2var_epi64(__m512i a, __m512i idx, __mmask8 k, __m512i b);
VPERMI2Q __m512i _mm512_maskz_permutex2var_epi64(__mmask8 k, __m512i a, __m512i idx, __m512i b);
VPERMI2Q __m256i _mm256_permutex2var_epi64(__m256i a, __m256i idx, __m256i b);
VPERMI2Q __m256i _mm256_mask_permutex2var_epi64(__m256i a, __mmask8 k, __m256i idx, __m256i b);
VPERMI2Q __m256i _mm256_mask2_permutex2var_epi64(__m256i a, __m256i idx, __mmask8 k, __m256i b);
VPERMI2Q __m256i _mm256_maskz_permutex2var_epi64(__mmask8 k, __m256i a, __m256i idx, __m256i b);
VPERMI2Q __m128i _mm_permutex2var_epi64(__m128i a, __m128i idx, __m128i b);
VPERMI2Q __m128i _mm_mask_permutex2var_epi64(__m128i a, __mmask8 k, __m128i idx, __m128i b);
VPERMI2Q __m128i _mm_mask2_permutex2var_epi64(__m128i a, __m128i idx, __mmask8 k, __m128i b);
VPERMI2Q __m128i _mm_maskz_permutex2var_epi64(__mmask8 k, __m128i a, __m128i idx, __m128i b);
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INSTRUCTION SET REFERENCE, V
VPERMI2W __m512i _mm512_permutex2var_epi16(__m512i a, __m512i idx, __m512i b);
VPERMI2W __m512i _mm512_mask_permutex2var_epi16(__m512i a, __mmask32 k, __m512i idx, __m512i b);
VPERMI2W __m512i _mm512_mask2_permutex2var_epi16(__m512i a, __m512i idx, __mmask32 k, __m512i b);
VPERMI2W __m512i _mm512_maskz_permutex2var_epi16(__mmask32 k, __m512i a, __m512i idx, __m512i b);
VPERMI2W __m256i _mm256_permutex2var_epi16(__m256i a, __m256i idx, __m256i b);
VPERMI2W __m256i _mm256_mask_permutex2var_epi16(__m256i a, __mmask16 k, __m256i idx, __m256i b);
VPERMI2W __m256i _mm256_mask2_permutex2var_epi16(__m256i a, __m256i idx, __mmask16 k, __m256i b);
VPERMI2W __m256i _mm256_maskz_permutex2var_epi16(__mmask16 k, __m256i a, __m256i idx, __m256i b);
VPERMI2W __m128i _mm_permutex2var_epi16(__m128i a, __m128i idx, __m128i b);
VPERMI2W __m128i _mm_mask_permutex2var_epi16(__m128i a, __mmask8 k, __m128i idx, __m128i b);
VPERMI2W __m128i _mm_mask2_permutex2var_epi16(__m128i a, __m128i idx, __mmask8 k, __m128i b);
VPERMI2W __m128i _mm_maskz_permutex2var_epi16(__mmask8 k, __m128i a, __m128i idx, __m128i b);
SIMD Floating-Point Exceptions
None
Other Exceptions
VPERMI2D/Q/PS/PD: See Table 2-50, “Type E4NF Class Exception Conditions.”
VPERMI2W: See Exceptions Type E4NF.nb in Table 2-50, “Type E4NF Class Exception Conditions.”
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