Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 100
INSTRUCTION SET REFERENCE, V
Operation
// getmant_fp64(src, sign_control, normalization_interval) is defined in the operation section of VGETMANTPD
VGETMANTSD (EVEX encoded version)
SignCtrl[1:0] := IMM8[3:2];
Interv[1:0] := IMM8[1:0];
IF k1[0] OR *no writemask*
THEN DEST[63:0] :=
getmant_fp64(src, sign_control, normalization_interval)
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
DEST[63:0] := 0
FI
FI;
DEST[127:64] := SRC1[127:64]
DEST[MAXVL-1:128] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VGETMANTSD __m128d _mm_getmant_sd( __m128d a, __m128 b, enum intv, enum sgn);
VGETMANTSD __m128d _mm_mask_getmant_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, enum intv, enum sgn);
VGETMANTSD __m128d _mm_maskz_getmant_sd( __mmask8 k, __m128 a, __m128d b, enum intv, enum sgn);
VGETMANTSD __m128d _mm_getmant_round_sd( __m128d a, __m128 b, enum intv, enum sgn, int r);
VGETMANTSD __m128d _mm_mask_getmant_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, enum intv, enum sgn, int r);
VGETMANTSD __m128d _mm_maskz_getmant_round_sd( __mmask8 k, __m128d a, __m128d b, enum intv, enum sgn, int r);
SIMD Floating-Point Exceptions
Denormal, Invalid
Other Exceptions
See Table 2-47, “Type E3 Class Exception Conditions.”
VGETMANTSD—Extract Float64 of Normalized Mantissas From Float64 Scalar
Vol. 2C
5-377
INSTRUCTION SET REFERENCE, V
VGETMANTSH—Extract FP16 of Normalized Mantissa from FP16 Scalar
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.LLIG.NP.0F3A.W0 27 /r /ib
A
V/V
AVX512-FP16
Extract the normalized mantissa of the low FP16
VGETMANTSH xmm1{k1}{z}, xmm2,
element in xmm3/m16 using imm8 for sign
xmm3/m16 {sae}, imm8
control and mantissa interval normalization. Store
the mantissa to xmm1 subject to writemask k1
and merge with the other elements of xmm2. Bits
127:16 of xmm2 are copied to xmm1[127:16].
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
imm8 (r)
Description
This instruction converts the FP16 value in the low element of the second source operand to FP16 values with the
mantissa normalization and sign control specified by the imm8 byte, see Table 5-9. The converted result is written
to the low element of the destination operand using writemask k1. The normalized mantissa is specified by interv
(imm8[1:0]) and the sign control (SC) is specified by bits 3:2 of the immediate byte.
Bits 127:16 of the destination operand are copied from the corresponding bits of the first source operand. Bits
MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the destination is updated according
to the writemask.
For each input FP16 value x, The conversion operation is:
GetMant(x) = ±2k|x.significand|
where:
1 ≤ |x.significand| < 2
Unbiased exponent k depends on the interval range defined by interv and whether the exponent of the source is
even or odd. The sign of the final result is determined by the sign control and the source sign and the leading frac-
tion bit.
The encoded value of imm8[1:0] and sign control are shown in Table 5-9.
Each converted FP16 result is encoded according to the sign control, the unbiased exponent k (adding bias) and a
mantissa normalized to the range specified by interv.
The GetMant() function follows Table 5-10 when dealing with floating-point special numbers.
Operation
VGETMANTSH dest{k1}, src1, src2, imm8
sign_control := imm8[3:2]
normalization_interval := imm8[1:0]
IF k1[0] or *no writemask*:
dest.fp16[0] := getmant_fp16(src2.fp16[0],
// see VGETMANTPH
sign_control,
normalization_interval)
ELSE IF *zeroing*:
dest.fp16[0] := 0
//else dest.fp16[0] remains unchanged
DEST[127:16] := src1[127:16]
DEST[MAXVL-1:128] := 0
5-378
Vol. 2C
VGETMANTSH—Extract FP16 of Normalized Mantissa from FP16 Scalar
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VGETMANTSH __m128h _mm_getmant_round_sh (__m128h a, __m128h b, _MM_MANTISSA_NORM_ENUM norm,
_MM_MANTISSA_SIGN_ENUM sign, const int sae);
VGETMANTSH __m128h _mm_mask_getmant_round_sh (__m128h src, __mmask8 k, __m128h a, __m128h b,
_MM_MANTISSA_NORM_ENUM norm, _MM_MANTISSA_SIGN_ENUM sign, const int sae);
VGETMANTSH __m128h _mm_maskz_getmant_round_sh (__mmask8 k, __m128h a, __m128h b, _MM_MANTISSA_NORM_ENUM norm,
_MM_MANTISSA_SIGN_ENUM sign, const int sae);
VGETMANTSH __m128h _mm_getmant_sh (__m128h a, __m128h b, _MM_MANTISSA_NORM_ENUM norm,
_MM_MANTISSA_SIGN_ENUM sign);
VGETMANTSH __m128h _mm_mask_getmant_sh (__m128h src, __mmask8 k, __m128h a, __m128h b, _MM_MANTISSA_NORM_ENUM
norm, _MM_MANTISSA_SIGN_ENUM sign);
VGETMANTSH __m128h _mm_maskz_getmant_sh (__mmask8 k, __m128h a, __m128h b, _MM_MANTISSA_NORM_ENUM norm,
_MM_MANTISSA_SIGN_ENUM sign);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”
VGETMANTSH—Extract FP16 of Normalized Mantissa from FP16 Scalar
Vol. 2C
5-379
INSTRUCTION SET REFERENCE, V
VGETMANTSS—Extract Float32 Vector of Normalized Mantissa From Float32 Vector
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.LLIG.66.0F3A.W0 27 /r ib
A
V/V
AVX512F
Extract the normalized mantissa from the low float32
VGETMANTSS xmm1 {k1}{z}, xmm2,
element of xmm3/m32 using imm8 for sign control and
xmm3/m32{sae}, imm8
mantissa interval normalization, store the mantissa to
xmm1 under the writemask k1 and merge with the
other elements of xmm2.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Scalar
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Convert the single-precision floating values in the low doubleword element of the second source operand (the third
operand) to single-precision floating-point value with the mantissa normalization and sign control specified by the
imm8 byte, see Figure 5-15. The converted result is written to the low doubleword element of the destination
operand (the first operand) using writemask k1. Bits (127:32) of the XMM register destination are copied from
corresponding bits in the first source operand. The normalized mantissa is specified by interv (imm8[1:0]) and the
sign control (sc) is specified by bits 3:2 of the immediate byte.
The conversion operation is:
GetMant(x) = ±2k|x.significand|
where:
1 <= |x.significand| < 2
Unbiased exponent k can be either 0 or -1, depending on the interval range defined by interv, the range of the
significand and whether the exponent of the source is even or odd. The sign of the final result is determined by sc
and the source sign. The encoded value of imm8[1:0] and sign control are shown in Figure 5-15.
The converted single-precision floating-point result is encoded according to the sign control, the unbiased expo-
nent k (adding bias) and a mantissa normalized to the range specified by interv.
The GetMant() function follows Table 5-8 when dealing with floating-point special numbers.
If writemasking is used, the low doubleword element of the destination operand is conditionally updated depending
on the value of writemask register k1. If writemasking is not used, the low doubleword element of the destination
operand is unconditionally updated.
5-380
Vol. 2C
VGETMANTSS—Extract Float32 Vector of Normalized Mantissa From Float32 Vector
INSTRUCTION SET REFERENCE, V
Operation
// getmant_fp32(src, sign_control, normalization_interval) is defined in the operation section of VGETMANTPS
VGETMANTSS (EVEX encoded version)
SignCtrl[1:0] := IMM8[3:2];
Interv[1:0] := IMM8[1:0];
IF k1[0] OR *no writemask*
THEN DEST[31:0] :=
getmant_fp32(src, sign_control, normalization_interval)
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
DEST[31:0] := 0
FI
FI;
DEST[127:32] := SRC1[127:32]
DEST[MAXVL-1:128] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VGETMANTSS __m128 _mm_getmant_ss( __m128 a, __m128 b, enum intv, enum sgn);
VGETMANTSS __m128 _mm_mask_getmant_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn);
VGETMANTSS __m128 _mm_maskz_getmant_ss( __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn);
VGETMANTSS __m128 _mm_getmant_round_ss( __m128 a, __m128 b, enum intv, enum sgn, int r);
VGETMANTSS __m128 _mm_mask_getmant_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn, int r);
VGETMANTSS __m128 _mm_maskz_getmant_round_ss( __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn, int r);
SIMD Floating-Point Exceptions
Denormal, Invalid
Other Exceptions
See Table 2-47, “Type E3 Class Exception Conditions.”
VGETMANTSS—Extract Float32 Vector of Normalized Mantissa From Float32 Vector
Vol. 2C
5-381
INSTRUCTION SET REFERENCE, V
VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4—Insert Packed
Floating-Point Values
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
VEX.256.66.0F3A.W0 18 /r ib
A
V/V
AVX
Insert 128 bits of packed floating-point values from
VINSERTF128 ymm1, ymm2,
xmm3/m128 and the remaining values from ymm2
xmm3/m128, imm8
into ymm1.
EVEX.256.66.0F3A.W0 18 /r ib
C
V/V
AVX512VL
Insert 128 bits of packed single-precision floating-
VINSERTF32X4 ymm1 {k1}{z}, ymm2,
AVX512F
point values from xmm3/m128 and the remaining
xmm3/m128, imm8
values from ymm2 into ymm1 under writemask k1.
EVEX.512.66.0F3A.W0 18 /r ib
C
V/V
AVX512F
Insert 128 bits of packed single-precision floating-
VINSERTF32X4 zmm1 {k1}{z}, zmm2,
point values from xmm3/m128 and the remaining
xmm3/m128, imm8
values from zmm2 into zmm1 under writemask k1.
EVEX.256.66.0F3A.W1 18 /r ib
B
V/V
AVX512VL
Insert 128 bits of packed double precision floating-
VINSERTF64X2 ymm1 {k1}{z}, ymm2,
AVX512DQ
point values from xmm3/m128 and the remaining
xmm3/m128, imm8
values from ymm2 into ymm1 under writemask k1.
EVEX.512.66.0F3A.W1 18 /r ib
B
V/V
AVX512DQ
Insert 128 bits of packed double precision floating-
VINSERTF64X2 zmm1 {k1}{z}, zmm2,
point values from xmm3/m128 and the remaining
xmm3/m128, imm8
values from zmm2 into zmm1 under writemask k1.
EVEX.512.66.0F3A.W0 1A /r ib
D
V/V
AVX512DQ
Insert 256 bits of packed single-precision floating-
VINSERTF32X8 zmm1 {k1}{z}, zmm2,
point values from ymm3/m256 and the remaining
ymm3/m256, imm8
values from zmm2 into zmm1 under writemask k1.
EVEX.512.66.0F3A.W1 1A /r ib
C
V/V
AVX512F
Insert 256 bits of packed double precision floating-
VINSERTF64X4 zmm1 {k1}{z}, zmm2,
point values from ymm3/m256 and the remaining
ymm3/m256, imm8
values from zmm2 into zmm1 under writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
imm8
B
Tuple2
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
imm8
C
Tuple4
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
imm8
D
Tuple8
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
imm8
Description
VINSERTF128/VINSERTF32x4 and VINSERTF64x2 insert 128-bits of packed floating-point values from the second
source operand (the third operand) into the destination operand (the first operand) at an 128-bit granularity offset
multiplied by imm8[0] (256-bit) or imm8[1:0]. The remaining portions of the destination operand are copied from
the corresponding fields of the first source operand (the second operand). The second source operand can be either
an XMM register or a 128-bit memory location. The destination and first source operands are vector registers.
VINSERTF32x4: The destination operand is a ZMM/YMM register and updated at 32-bit granularity according to the
writemask. The high 6/7 bits of the immediate are ignored.
VINSERTF64x2: The destination operand is a ZMM/YMM register and updated at 64-bit granularity according to the
writemask. The high 6/7 bits of the immediate are ignored.
VINSERTF32x8 and VINSERTF64x4 inserts 256-bits of packed floating-point values from the second source operand
(the third operand) into the destination operand (the first operand) at a 256-bit granular offset multiplied by
imm8[0]. The remaining portions of the destination are copied from the corresponding fields of the first source
operand (the second operand). The second source operand can be either an YMM register or a 256-bit memory
location. The high 7 bits of the immediate are ignored. The destination operand is a ZMM register and updated at
32/64-bit granularity according to the writemask.
5-382
Vol. 2C
VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4—Insert Packed Floating-Point Values
INSTRUCTION SET REFERENCE, V
Operation
VINSERTF32x4 (EVEX encoded versions)
(KL, VL) = (8, 256), (16, 512)
TEMP_DEST[VL-1:0] := SRC1[VL-1:0]
IF VL = 256
CASE (imm8[0]) OF
0: TMP_DEST[127:0] := SRC2[127:0]
1: TMP_DEST[255:128] := SRC2[127:0]
ESAC.
FI;
IF VL = 512
CASE (imm8[1:0]) OF
00: TMP_DEST[127:0] := SRC2[127:0]
01: TMP_DEST[255:128] := SRC2[127:0]
10: TMP_DEST[383:256] := SRC2[127:0]
11: TMP_DEST[511:384] := SRC2[127:0]
ESAC.
FI;
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VINSERTF64x2 (EVEX encoded versions)
(KL, VL) = (4, 256), (8, 512)
TEMP_DEST[VL-1:0] := SRC1[VL-1:0]
IF VL = 256
CASE (imm8[0]) OF
0: TMP_DEST[127:0] := SRC2[127:0]
1: TMP_DEST[255:128] := SRC2[127:0]
ESAC.
FI;
IF VL = 512
CASE (imm8[1:0]) OF
00: TMP_DEST[127:0] := SRC2[127:0]
01: TMP_DEST[255:128] := SRC2[127:0]
10: TMP_DEST[383:256] := SRC2[127:0]
11: TMP_DEST[511:384] := SRC2[127:0]
ESAC.
FI;
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] := TMP_DEST[i+63:i]
ELSE
VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4—Insert Packed Floating-Point Values
Vol. 2C
5-383
INSTRUCTION SET REFERENCE, V
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VINSERTF32x8 (EVEX.U1.512 encoded version)
TEMP_DEST[VL-1:0] := SRC1[VL-1:0]
CASE (imm8[0]) OF
0: TMP_DEST[255:0] := SRC2[255:0]
1: TMP_DEST[511:256] := SRC2[255:0]
ESAC.
FOR j := 0 TO 15
i := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VINSERTF64x4 (EVEX.512 encoded version)
VL = 512
TEMP_DEST[VL-1:0] := SRC1[VL-1:0]
CASE (imm8[0]) OF
0: TMP_DEST[255:0] := SRC2[255:0]
1: TMP_DEST[511:256] := SRC2[255:0]
ESAC.
FOR j := 0 TO 7
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] := TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
5-384
Vol. 2C
VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4—Insert Packed Floating-Point Values
INSTRUCTION SET REFERENCE, V
VINSERTF128 (VEX encoded version)
TEMP[255:0] := SRC1[255:0]
CASE (imm8[0]) OF
0: TEMP[127:0] := SRC2[127:0]
1: TEMP[255:128] := SRC2[127:0]
ESAC
DEST := TEMP
Intel C/C++ Compiler Intrinsic Equivalent
VINSERTF32x4 __m512 _mm512_insertf32x4( __m512 a, __m128 b, int imm);
VINSERTF32x4 __m512 _mm512_mask_insertf32x4(__m512 s, __mmask16 k, __m512 a, __m128 b, int imm);
VINSERTF32x4 __m512 _mm512_maskz_insertf32x4( __mmask16 k, __m512 a, __m128 b, int imm);
VINSERTF32x4 __m256 _mm256_insertf32x4( __m256 a, __m128 b, int imm);
VINSERTF32x4 __m256 _mm256_mask_insertf32x4(__m256 s, __mmask8 k, __m256 a, __m128 b, int imm);
VINSERTF32x4 __m256 _mm256_maskz_insertf32x4( __mmask8 k, __m256 a, __m128 b, int imm);
VINSERTF32x8 __m512 _mm512_insertf32x8( __m512 a, __m256 b, int imm);
VINSERTF32x8 __m512 _mm512_mask_insertf32x8(__m512 s, __mmask16 k, __m512 a, __m256 b, int imm);
VINSERTF32x8 __m512 _mm512_maskz_insertf32x8( __mmask16 k, __m512 a, __m256 b, int imm);
VINSERTF64x2 __m512d _mm512_insertf64x2( __m512d a, __m128d b, int imm);
VINSERTF64x2 __m512d _mm512_mask_insertf64x2(__m512d s, __mmask8 k, __m512d a, __m128d b, int imm);
VINSERTF64x2 __m512d _mm512_maskz_insertf64x2( __mmask8 k, __m512d a, __m128d b, int imm);
VINSERTF64x2 __m256d _mm256_insertf64x2( __m256d a, __m128d b, int imm);
VINSERTF64x2 __m256d _mm256_mask_insertf64x2(__m256d s, __mmask8 k, __m256d a, __m128d b, int imm);
VINSERTF64x2 __m256d _mm256_maskz_insertf64x2( __mmask8 k, __m256d a, __m128d b, int imm);
VINSERTF64x4 __m512d _mm512_insertf64x4( __m512d a, __m256d b, int imm);
VINSERTF64x4 __m512d _mm512_mask_insertf64x4(__m512d s, __mmask8 k, __m512d a, __m256d b, int imm);
VINSERTF64x4 __m512d _mm512_maskz_insertf64x4( __mmask8 k, __m512d a, __m256d b, int imm);
VINSERTF128 __m256 _mm256_insertf128_ps (__m256 a, __m128 b, int offset);
VINSERTF128 __m256d _mm256_insertf128_pd (__m256d a, __m128d b, int offset);
VINSERTF128 __m256i _mm256_insertf128_si256 (__m256i a, __m128i b, int offset);
SIMD Floating-Point Exceptions
None
Other Exceptions
VEX-encoded instruction, see Table 2-23, “Type 6 Class Exception Conditions.”
Additionally:
#UD
If VEX.L = 0.
EVEX-encoded instruction, see Table 2-54, “Type E6NF Class Exception Conditions.”
VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4—Insert Packed Floating-Point Values
Vol. 2C
5-385
INSTRUCTION SET REFERENCE, V
VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4—Insert Packed
Integer Values
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
VEX.256.66.0F3A.W0 38 /r ib
A
V/V
AVX2
Insert 128 bits of integer data from xmm3/m128 and
VINSERTI128 ymm1, ymm2,
the remaining values from ymm2 into ymm1.
xmm3/m128, imm8
EVEX.256.66.0F3A.W0 38 /r ib
C
V/V
AVX512VL
Insert 128 bits of packed doubleword integer values
VINSERTI32X4 ymm1 {k1}{z}, ymm2,
AVX512F
from xmm3/m128 and the remaining values from
xmm3/m128, imm8
ymm2 into ymm1 under writemask k1.
EVEX.512.66.0F3A.W0 38 /r ib
C
V/V
AVX512F
Insert 128 bits of packed doubleword integer values
VINSERTI32X4 zmm1 {k1}{z}, zmm2,
from xmm3/m128 and the remaining values from
xmm3/m128, imm8
zmm2 into zmm1 under writemask k1.
EVEX.256.66.0F3A.W1 38 /r ib
B
V/V
AVX512VL
Insert 128 bits of packed quadword integer values
VINSERTI64X2 ymm1 {k1}{z}, ymm2,
AVX512DQ
from xmm3/m128 and the remaining values from
xmm3/m128, imm8
ymm2 into ymm1 under writemask k1.
EVEX.512.66.0F3A.W1 38 /r ib
B
V/V
AVX512DQ
Insert 128 bits of packed quadword integer values
VINSERTI64X2 zmm1 {k1}{z}, zmm2,
from xmm3/m128 and the remaining values from
xmm3/m128, imm8
zmm2 into zmm1 under writemask k1.
EVEX.512.66.0F3A.W0 3A /r ib
D
V/V
AVX512DQ
Insert 256 bits of packed doubleword integer values
VINSERTI32X8 zmm1 {k1}{z}, zmm2,
from ymm3/m256 and the remaining values from
ymm3/m256, imm8
zmm2 into zmm1 under writemask k1.
EVEX.512.66.0F3A.W1 3A /r ib
C
V/V
AVX512F
Insert 256 bits of packed quadword integer values
VINSERTI64X4 zmm1 {k1}{z}, zmm2,
from ymm3/m256 and the remaining values from
ymm3/m256, imm8
zmm2 into zmm1 under writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
imm8
B
Tuple2
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
imm8
C
Tuple4
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
imm8
D
Tuple8
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
imm8
Description
VINSERTI32x4 and VINSERTI64x2 inserts 128-bits of packed integer values from the second source operand (the
third operand) into the destination operand (the first operand) at an 128-bit granular offset multiplied by imm8[0]
(256-bit) or imm8[1:0]. The remaining portions of the destination are copied from the corresponding fields of the
first source operand (the second operand). The second source operand can be either an XMM register or a 128-bit
memory location. The high 6/7bits of the immediate are ignored. The destination operand is a ZMM/YMM register
and updated at 32 and 64-bit granularity according to the writemask.
VINSERTI32x8 and VINSERTI64x4 inserts 256-bits of packed integer values from the second source operand (the
third operand) into the destination operand (the first operand) at a 256-bit granular offset multiplied by imm8[0].
The remaining portions of the destination are copied from the corresponding fields of the first source operand (the
second operand). The second source operand can be either an YMM register or a 256-bit memory location. The
upper bits of the immediate are ignored. The destination operand is a ZMM register and updated at 32 and 64-bit
granularity according to the writemask.
VINSERTI128 inserts 128-bits of packed integer data from the second source operand (the third operand) into the
destination operand (the first operand) at a 128-bit granular offset multiplied by imm8[0]. The remaining portions
of the destination are copied from the corresponding fields of the first source operand (the second operand). The
second source operand can be either an XMM register or a 128-bit memory location. The high 7 bits of the imme-
diate are ignored. VEX.L must be 1, otherwise attempt to execute this instruction with VEX.L=0 will cause #UD.
5-386
Vol. 2C
VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4—Insert Packed Integer Values
INSTRUCTION SET REFERENCE, V
Operation
VINSERTI32x4 (EVEX encoded versions)
(KL, VL) = (8, 256), (16, 512)
TEMP_DEST[VL-1:0] := SRC1[VL-1:0]
IF VL = 256
CASE (imm8[0]) OF
0: TMP_DEST[127:0] := SRC2[127:0]
1: TMP_DEST[255:128] := SRC2[127:0]
ESAC.
FI;
IF VL = 512
CASE (imm8[1:0]) OF
00: TMP_DEST[127:0] := SRC2[127:0]
01: TMP_DEST[255:128] := SRC2[127:0]
10: TMP_DEST[383:256] := SRC2[127:0]
11: TMP_DEST[511:384] := SRC2[127:0]
ESAC.
FI;
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VINSERTI64x2 (EVEX encoded versions)
(KL, VL) = (4, 256), (8, 512)
TEMP_DEST[VL-1:0] := SRC1[VL-1:0]
IF VL = 256
CASE (imm8[0]) OF
0: TMP_DEST[127:0] := SRC2[127:0]
1: TMP_DEST[255:128] := SRC2[127:0]
ESAC.
FI;
IF VL = 512
CASE (imm8[1:0]) OF
00: TMP_DEST[127:0] := SRC2[127:0]
01: TMP_DEST[255:128] := SRC2[127:0]
10: TMP_DEST[383:256] := SRC2[127:0]
11: TMP_DEST[511:384] := SRC2[127:0]
ESAC.
FI;
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] := TMP_DEST[i+63:i]
ELSE
VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4—Insert Packed Integer Values
Vol. 2C
5-387
INSTRUCTION SET REFERENCE, V
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VINSERTI32x8 (EVEX.U1.512 encoded version)
TEMP_DEST[VL-1:0] := SRC1[VL-1:0]
CASE (imm8[0]) OF
0: TMP_DEST[255:0] := SRC2[255:0]
1: TMP_DEST[511:256] := SRC2[255:0]
ESAC.
FOR j := 0 TO 15
i := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VINSERTI64x4 (EVEX.512 encoded version)
VL = 512
TEMP_DEST[VL-1:0] := SRC1[VL-1:0]
CASE (imm8[0]) OF
0: TMP_DEST[255:0] := SRC2[255:0]
1: TMP_DEST[511:256] := SRC2[255:0]
ESAC.
FOR j := 0 TO 7
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] := TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
5-388
Vol. 2C
VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4—Insert Packed Integer Values
INSTRUCTION SET REFERENCE, V
VINSERTI128
TEMP[255:0] := SRC1[255:0]
CASE (imm8[0]) OF
0: TEMP[127:0] := SRC2[127:0]
1: TEMP[255:128] := SRC2[127:0]
ESAC
DEST := TEMP
Intel C/C++ Compiler Intrinsic Equivalent
VINSERTI32x4 _mm512i _inserti32x4( __m512i a, __m128i b, int imm);
VINSERTI32x4 _mm512i _mask_inserti32x4(__m512i s, __mmask16 k, __m512i a, __m128i b, int imm);
VINSERTI32x4 _mm512i _maskz_inserti32x4( __mmask16 k, __m512i a, __m128i b, int imm);
VINSERTI32x4 __m256i _mm256_inserti32x4( __m256i a, __m128i b, int imm);
VINSERTI32x4 __m256i _mm256_mask_inserti32x4(__m256i s, __mmask8 k, __m256i a, __m128i b, int imm);
VINSERTI32x4 __m256i _mm256_maskz_inserti32x4( __mmask8 k, __m256i a, __m128i b, int imm);
VINSERTI32x8 __m512i _mm512_inserti32x8( __m512i a, __m256i b, int imm);
VINSERTI32x8 __m512i _mm512_mask_inserti32x8(__m512i s, __mmask16 k, __m512i a, __m256i b, int imm);
VINSERTI32x8 __m512i _mm512_maskz_inserti32x8( __mmask16 k, __m512i a, __m256i b, int imm);
VINSERTI64x2 __m512i _mm512_inserti64x2( __m512i a, __m128i b, int imm);
VINSERTI64x2 __m512i _mm512_mask_inserti64x2(__m512i s, __mmask8 k, __m512i a, __m128i b, int imm);
VINSERTI64x2 __m512i _mm512_maskz_inserti64x2( __mmask8 k, __m512i a, __m128i b, int imm);
VINSERTI64x2 __m256i _mm256_inserti64x2( __m256i a, __m128i b, int imm);
VINSERTI64x2 __m256i _mm256_mask_inserti64x2(__m256i s, __mmask8 k, __m256i a, __m128i b, int imm);
VINSERTI64x2 __m256i _mm256_maskz_inserti64x2( __mmask8 k, __m256i a, __m128i b, int imm);
VINSERTI64x4 _mm512_inserti64x4( __m512i a, __m256i b, int imm);
VINSERTI64x4 _mm512_mask_inserti64x4(__m512i s, __mmask8 k, __m512i a, __m256i b, int imm);
VINSERTI64x4 _mm512_maskz_inserti64x4( __mmask m, __m512i a, __m256i b, int imm);
VINSERTI128 __m256i _mm256_insertf128_si256 (__m256i a, __m128i b, int offset);
SIMD Floating-Point Exceptions
None
Other Exceptions
VEX-encoded instruction, see Table 2-23, “Type 6 Class Exception Conditions.”
Additionally:
#UD
If VEX.L = 0.
EVEX-encoded instruction, see Table 2-54, “Type E6NF Class Exception Conditions.”
VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4—Insert Packed Integer Values
Vol. 2C
5-389
INSTRUCTION SET REFERENCE, V
VMASKMOV—Conditional SIMD Packed Loads and Stores
Opcode/
Op/
64/32-bit
CPUID
Description
Instruction
En
Mode
Feature
Flag
VEX.128.66.0F38.W0 2C /r
RVM
V/V
AVX
Conditionally load packed single-precision values from
m128 using mask in xmm2 and store in xmm1.
VMASKMOVPS xmm1, xmm2, m128
VEX.256.66.0F38.W0 2C /r
RVM
V/V
AVX
Conditionally load packed single-precision values from
m256 using mask in ymm2 and store in ymm1.
VMASKMOVPS ymm1, ymm2, m256
VEX.128.66.0F38.W0 2D /r
RVM
V/V
AVX
Conditionally load packed double precision values from
m128 using mask in xmm2 and store in xmm1.
VMASKMOVPD xmm1, xmm2, m128
VEX.256.66.0F38.W0 2D /r
RVM
V/V
AVX
Conditionally load packed double precision values from
m256 using mask in ymm2 and store in ymm1.
VMASKMOVPD ymm1, ymm2, m256
VEX.128.66.0F38.W0 2E /r
MVR
V/V
AVX
Conditionally store packed single-precision values from
xmm2 using mask in xmm1.
VMASKMOVPS m128, xmm1, xmm2
VEX.256.66.0F38.W0 2E /r
MVR
V/V
AVX
Conditionally store packed single-precision values from
ymm2 using mask in ymm1.
VMASKMOVPS m256, ymm1, ymm2
VEX.128.66.0F38.W0 2F /r
MVR
V/V
AVX
Conditionally store packed double precision values from
xmm2 using mask in xmm1.
VMASKMOVPD m128, xmm1, xmm2
VEX.256.66.0F38.W0 2F /r
MVR
V/V
AVX
Conditionally store packed double precision values from
ymm2 using mask in ymm1.
VMASKMOVPD m256, ymm1, ymm2
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
MVR
ModRM:r/m (w)
VEX.vvvv (r)
ModRM:reg (r)
N/A
Description
Conditionally moves packed data elements from the second source operand into the corresponding data element of
the destination operand, depending on the mask bits associated with each data element. The mask bits are speci-
fied in the first source operand.
The mask bit for each data element is the most significant bit of that element in the first source operand. If a mask
is 1, the corresponding data element is copied from the second source operand to the destination operand. If the
mask is 0, the corresponding data element is set to zero in the load form of these instructions, and unmodified in
the store form.
The second source operand is a memory address for the load form of these instruction. The destination operand is
a memory address for the store form of these instructions. The other operands are both XMM registers (for
VEX.128 version) or YMM registers (for VEX.256 version).
Faults occur only due to mask-bit required memory accesses that caused the faults. Faults will not occur due to
referencing any memory location if the corresponding mask bit for that memory location is 0. For example, no
faults will be detected if the mask bits are all zero.
Unlike previous MASKMOV instructions (MASKMOVQ and MASKMOVDQU), a nontemporal hint is not applied to
these instructions.
Instruction behavior on alignment check reporting with mask bits of less than all 1s are the same as with mask bits
of all 1s.
VMASKMOV should not be used to access memory mapped I/O and un-cached memory as the access and the
ordering of the individual loads or stores it does is implementation specific.
5-390
Vol. 2C
VMASKMOV—Conditional SIMD Packed Loads and Stores
INSTRUCTION SET REFERENCE, V
In cases where mask bits indicate data should not be loaded or stored paging A and D bits will be set in an imple-
mentation dependent way. However, A and D bits are always set for pages where data is actually loaded/stored.
Note: for load forms, the first source (the mask) is encoded in VEX.vvvv; the second source is encoded in rm_field,
and the destination register is encoded in reg_field.
Note: for store forms, the first source (the mask) is encoded in VEX.vvvv; the second source register is encoded in
reg_field, and the destination memory location is encoded in rm_field.
Operation
VMASKMOVPS -128-bit load
DEST[31:0] := IF (SRC1[31]) Load_32(mem) ELSE 0
DEST[63:32] := IF (SRC1[63]) Load_32(mem + 4) ELSE 0
DEST[95:64] := IF (SRC1[95]) Load_32(mem + 8) ELSE 0
DEST[127:97] := IF (SRC1[127]) Load_32(mem + 12) ELSE 0
DEST[MAXVL-1:128] := 0
VMASKMOVPS - 256-bit load
DEST[31:0] := IF (SRC1[31]) Load_32(mem) ELSE 0
DEST[63:32] := IF (SRC1[63]) Load_32(mem + 4) ELSE 0
DEST[95:64] := IF (SRC1[95]) Load_32(mem + 8) ELSE 0
DEST[127:96] := IF (SRC1[127]) Load_32(mem + 12) ELSE 0
DEST[159:128] := IF (SRC1[159]) Load_32(mem + 16) ELSE 0
DEST[191:160] := IF (SRC1[191]) Load_32(mem + 20) ELSE 0
DEST[223:192] := IF (SRC1[223]) Load_32(mem + 24) ELSE 0
DEST[255:224] := IF (SRC1[255]) Load_32(mem + 28) ELSE 0
VMASKMOVPD - 128-bit load
DEST[63:0] := IF (SRC1[63]) Load_64(mem) ELSE 0
DEST[127:64] := IF (SRC1[127]) Load_64(mem + 16) ELSE 0
DEST[MAXVL-1:128] := 0
VMASKMOVPD - 256-bit load
DEST[63:0] := IF (SRC1[63]) Load_64(mem) ELSE 0
DEST[127:64] := IF (SRC1[127]) Load_64(mem + 8) ELSE 0
DEST[195:128] := IF (SRC1[191]) Load_64(mem + 16) ELSE 0
DEST[255:196] := IF (SRC1[255]) Load_64(mem + 24) ELSE 0
VMASKMOVPS - 128-bit store
IF (SRC1[31]) DEST[31:0] := SRC2[31:0]
IF (SRC1[63]) DEST[63:32] := SRC2[63:32]
IF (SRC1[95]) DEST[95:64] := SRC2[95:64]
IF (SRC1[127]) DEST[127:96] := SRC2[127:96]
VMASKMOVPS - 256-bit store
IF (SRC1[31]) DEST[31:0] := SRC2[31:0]
IF (SRC1[63]) DEST[63:32] := SRC2[63:32]
IF (SRC1[95]) DEST[95:64] := SRC2[95:64]
IF (SRC1[127]) DEST[127:96] := SRC2[127:96]
IF (SRC1[159]) DEST[159:128] :=SRC2[159:128]
IF (SRC1[191]) DEST[191:160] := SRC2[191:160]
IF (SRC1[223]) DEST[223:192] := SRC2[223:192]
IF (SRC1[255]) DEST[255:224] := SRC2[255:224]
VMASKMOV—Conditional SIMD Packed Loads and Stores
Vol. 2C
5-391
INSTRUCTION SET REFERENCE, V
VMASKMOVPD - 128-bit store
IF (SRC1[63]) DEST[63:0] := SRC2[63:0]
IF (SRC1[127]) DEST[127:64] := SRC2[127:64]
VMASKMOVPD - 256-bit store
IF (SRC1[63]) DEST[63:0] := SRC2[63:0]
IF (SRC1[127]) DEST[127:64] := SRC2[127:64]
IF (SRC1[191]) DEST[191:128] := SRC2[191:128]
IF (SRC1[255]) DEST[255:192] := SRC2[255:192]
Intel C/C++ Compiler Intrinsic Equivalent
__m256 _mm256_maskload_ps(float const *a, __m256i mask)
void
_mm256_maskstore_ps(float *a, __m256i mask, __m256 b)
__m256d _mm256_maskload_pd(double *a, __m256i mask);
void
_mm256_maskstore_pd(double *a, __m256i mask, __m256d b);
__m128 _mm_maskload_ps(float const *a, __m128i mask)
void
_mm_maskstore_ps(float *a, __m128i mask, __m128 b)
__m128d _mm_maskload_pd(double const *a, __m128i mask);
void
_mm_maskstore_pd(double *a, __m128i mask, __m128d b);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Table 2-23, “Type 6 Class Exception Conditions” (No AC# reported for any mask bit combinations).
Additionally:
#UD
If VEX.W = 1.
5-392
Vol. 2C
VMASKMOV—Conditional SIMD Packed Loads and Stores
INSTRUCTION SET REFERENCE, V
VMAXPH—Return Maximum of Packed FP16 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.NP.MAP5.W0 5F /r
A
V/V
AVX512-FP16
Return the maximum packed FP16 values
VMAXPH xmm1{k1}{z}, xmm2,
AVX512VL
between xmm2 and xmm3/m128/m16bcst and
xmm3/m128/m16bcst
store the result in xmm1 subject to writemask k1.
EVEX.256.NP.MAP5.W0 5F /r
A
V/V
AVX512-FP16
Return the maximum packed FP16 values
VMAXPH ymm1{k1}{z}, ymm2,
AVX512VL
between ymm2 and ymm3/m256/m16bcst and
ymm3/m256/m16bcst
store the result in ymm1 subject to writemask k1.
EVEX.512.NP.MAP5.W0 5F /r
A
V/V
AVX512-FP16
Return the maximum packed FP16 values
VMAXPH zmm1{k1}{z}, zmm2,
between zmm2 and zmm3/m512/m16bcst and
zmm3/m512/m16bcst {sae}
store the result in zmm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
This instruction performs a SIMD compare of the packed FP16 values in the first source operand and the second
source operand and returns the maximum value for each pair of values to the destination operand.
If the values being compared are both 0.0s (of either sign), the value in the second operand (source operand) is
returned. If a value in the second operand is an SNaN, then SNaN is forwarded unchanged to the destination (that
is, a QNaN version of the SNaN is not returned).
If only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN
or a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source
operand (from either the first or second operand) be returned, the action of VMAXPH can be emulated using a
sequence of instructions, such as, a comparison followed by AND, ANDN and OR.
EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcast from a 16-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
Operation
def MAX(SRC1, SRC2):
IF (SRC1 = 0.0) and (SRC2 = 0.0):
DEST := SRC2
ELSE IF (SRC1 = NaN):
DEST := SRC2
ELSE IF (SRC2 = NaN):
DEST := SRC2
ELSE IF (SRC1 > SRC2):
DEST := SRC1
ELSE:
DEST := SRC2
VMAXPH—Return Maximum of Packed FP16 Values
Vol. 2C
5-393
INSTRUCTION SET REFERENCE, V
VMAXPH dest, src1, src2
VL = 128, 256 or 512
KL := VL/16
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF EVEX.b = 1:
tsrc2 := SRC2.fp16[0]
ELSE:
tsrc2 := SRC2.fp16[j]
DEST.fp16[j] := MAX(SRC1.fp16[j], tsrc2)
ELSE IF *zeroing*:
DEST.fp16[j] := 0
// else dest.fp16[j] remains unchanged
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VMAXPH __m128h _mm_mask_max_ph (__m128h src, __mmask8 k, __m128h a, __m128h b);
VMAXPH __m128h _mm_maskz_max_ph (__mmask8 k, __m128h a, __m128h b);
VMAXPH __m128h _mm_max_ph (__m128h a, __m128h b);
VMAXPH __m256h _mm256_mask_max_ph (__m256h src, __mmask16 k, __m256h a, __m256h b);
VMAXPH __m256h _mm256_maskz_max_ph (__mmask16 k, __m256h a, __m256h b);
VMAXPH __m256h _mm256_max_ph (__m256h a, __m256h b);
VMAXPH __m512h _mm512_mask_max_ph (__m512h src, __mmask32 k, __m512h a, __m512h b);
VMAXPH __m512h _mm512_maskz_max_ph (__mmask32 k, __m512h a, __m512h b);
VMAXPH __m512h _mm512_max_ph (__m512h a, __m512h b);
VMAXPH __m512h _mm512_mask_max_round_ph (__m512h src, __mmask32 k, __m512h a, __m512h b, int sae);
VMAXPH __m512h _mm512_maskz_max_round_ph (__mmask32 k, __m512h a, __m512h b, int sae);
VMAXPH __m512h _mm512_max_round_ph (__m512h a, __m512h b, int sae);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
5-394
Vol. 2C
VMAXPH—Return Maximum of Packed FP16 Values
INSTRUCTION SET REFERENCE, V
VMAXSH—Return Maximum of Scalar FP16 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.LLIG.F3.MAP5.W0 5F /r
A
V/V
AVX512-FP16
Return the maximum low FP16 value between
VMAXSH xmm1{k1}{z}, xmm2,
xmm3/m16 and xmm2 and store the result in
xmm3/m16 {sae}
xmm1 subject to writemask k1. Bits 127:16 of
xmm2 are copied to xmm1[127:16].
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
This instruction performs a compare of the low packed FP16 values in the first source operand and the second
source operand and returns the maximum value for the pair of values to the destination operand.
If the values being compared are both 0.0s (of either sign), the value in the second operand (source operand) is
returned. If a value in the second operand is an SNaN, then SNaN is forwarded unchanged to the destination (that
is, a QNaN version of the SNaN is not returned).
If only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN
or a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source
operand (from either the first or second operand) be returned, the action of VMAXSH can be emulated using a
sequence of instructions, such as, a comparison followed by AND, ANDN, and OR.
Bits 127:16 of the destination operand are copied from the corresponding bits of the first source operand. Bits
MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the destination is updated according
to the writemask.
Operation
def MAX(SRC1, SRC2):
IF (SRC1 = 0.0) and (SRC2 = 0.0):
DEST := SRC2
ELSE IF (SRC1 = NaN):
DEST := SRC2
ELSE IF (SRC2 = NaN):
DEST := SRC2
ELSE IF (SRC1 > SRC2):
DEST := SRC1
ELSE:
DEST := SRC2
VMAXSH dest, src1, src2
IF k1[0] OR *no writemask*:
DEST.fp16[0] := MAX(SRC1.fp16[0], SRC2.fp16[0])
ELSE IF *zeroing*:
DEST.fp16[0] := 0
// else dest.fp16[j] remains unchanged
DEST[127:16] := SRC1[127:16]
DEST[MAXVL-1:128] := 0
VMAXSH—Return Maximum of Scalar FP16 Values
Vol. 2C
5-395
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VMAXSH __m128h _mm_mask_max_round_sh (__m128h src, __mmask8 k, __m128h a, __m128h b, int sae);
VMAXSH __m128h _mm_maskz_max_round_sh (__mmask8 k, __m128h a, __m128h b, int sae);
VMAXSH __m128h _mm_max_round_sh (__m128h a, __m128h b, int sae);
VMAXSH __m128h _mm_mask_max_sh (__m128h src, __mmask8 k, __m128h a, __m128h b);
VMAXSH __m128h _mm_maskz_max_sh (__mmask8 k, __m128h a, __m128h b);
VMAXSH __m128h _mm_max_sh (__m128h a, __m128h b);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”
5-396
Vol. 2C
VMAXSH—Return Maximum of Scalar FP16 Values
INSTRUCTION SET REFERENCE, V
VMINPH—Return Minimum of Packed FP16 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.NP.MAP5.W0 5D /r
A
V/V
AVX512-FP16
Return the minimum packed FP16 values between
VMINPH xmm1{k1}{z}, xmm2, xmm3/
AVX512VL
xmm2 and xmm3/m128/m16bcst and store the
m128/m16bcst
result in xmm1 subject to writemask k1.
EVEX.256.NP.MAP5.W0 5D /r
A
V/V
AVX512-FP16
Return the minimum packed FP16 values between
VMINPH ymm1{k1}{z}, ymm2, ymm3/
AVX512VL
ymm2 and ymm3/m256/m16bcst and store the
m256/m16bcst
result in ymm1 subject to writemask k1.
EVEX.512.NP.MAP5.W0 5D /r
A
V/V
AVX512-FP16
Return the minimum packed FP16 values between
VMINPH zmm1{k1}{z}, zmm2, zmm3/
zmm2 and zmm3/m512/m16bcst and store the
m512/m16bcst {sae}
result in zmm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
This instruction performs a SIMD compare of the packed FP16 values in the first source operand and the second
source operand and returns the minimum value for each pair of values to the destination operand.
If the values being compared are both 0.0s (of either sign), the value in the second operand (source operand) is
returned. If a value in the second operand is an SNaN, then SNaN is forwarded unchanged to the destination (that
is, a QNaN version of the SNaN is not returned).
If only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN
or a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source
operand (from either the first or second operand) be returned, the action of VMINPH can be emulated using a
sequence of instructions, such as, a comparison followed by AND, ANDN and OR.
EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcast from a 16-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
Operation
def MIN(SRC1, SRC2):
IF (SRC1 = 0.0) and (SRC2 = 0.0):
DEST := SRC2
ELSE IF (SRC1 = NaN):
DEST := SRC2
ELSE IF (SRC2 = NaN):
DEST := SRC2
ELSE IF (SRC1 < SRC2):
DEST := SRC1
ELSE:
DEST := SRC2
VMINPH—Return Minimum of Packed FP16 Values
Vol. 2C
5-397
INSTRUCTION SET REFERENCE, V
VMINPH dest, src1, src2
VL = 128, 256 or 512
KL := VL/16
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF EVEX.b = 1:
tsrc2 := SRC2.fp16[0]
ELSE:
tsrc2 := SRC2.fp16[j]
DEST.fp16[j] := MIN(SRC1.fp16[j], tsrc2)
ELSE IF *zeroing*:
DEST.fp16[j] := 0
// else dest.fp16[j] remains unchanged
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VMINPH __m128h _mm_mask_min_ph (__m128h src, __mmask8 k, __m128h a, __m128h b);
VMINPH __m128h _mm_maskz_min_ph (__mmask8 k, __m128h a, __m128h b);
VMINPH __m128h _mm_min_ph (__m128h a, __m128h b);
VMINPH __m256h _mm256_mask_min_ph (__m256h src, __mmask16 k, __m256h a, __m256h b);
VMINPH __m256h _mm256_maskz_min_ph (__mmask16 k, __m256h a, __m256h b);
VMINPH __m256h _mm256_min_ph (__m256h a, __m256h b);
VMINPH __m512h _mm512_mask_min_ph (__m512h src, __mmask32 k, __m512h a, __m512h b);
VMINPH __m512h _mm512_maskz_min_ph (__mmask32 k, __m512h a, __m512h b);
VMINPH __m512h _mm512_min_ph (__m512h a, __m512h b);
VMINPH __m512h _mm512_mask_min_round_ph (__m512h src, __mmask32 k, __m512h a, __m512h b, int sae);
VMINPH __m512h _mm512_maskz_min_round_ph (__mmask32 k, __m512h a, __m512h b, int sae);
VMINPH __m512h _mm512_min_round_ph (__m512h a, __m512h b, int sae);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
5-398
Vol. 2C
VMINPH—Return Minimum of Packed FP16 Values
INSTRUCTION SET REFERENCE, V
VMINSH—Return Minimum Scalar FP16 Value
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.LLIG.F3.MAP5.W0 5D /r
A
V/V
AVX512-FP16
Return the minimum low FP16 value between
VMINSH xmm1{k1}{z}, xmm2, xmm3/
xmm3/m16 and xmm2. Stores the result in
m16 {sae}
xmm1 subject to writemask k1. Bits 127:16 of
xmm2 are copied to xmm1[127:16].
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
This instruction performs a compare of the low packed FP16 values in the first source operand and the second
source operand and returns the minimum value for the pair of values to the destination operand.
If the values being compared are both 0.0s (of either sign), the value in the second operand (source operand) is
returned. If a value in the second operand is an SNaN, then SNaN is forwarded unchanged to the destination (that
is, a QNaN version of the SNaN is not returned).
If only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN
or a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source
operand (from either the first or second operand) be returned, the action of VMINSH can be emulated using a
sequence of instructions, such as, a comparison followed by AND, ANDN, and OR.
EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcast from a 16-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
Bits 127:16 of the destination operand are copied from the corresponding bits of the first source operand. Bits
MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the destination is updated according
to the writemask.
Operation
def MIN(SRC1, SRC2):
IF (SRC1 = 0.0) and (SRC2 = 0.0):
DEST := SRC2
ELSE IF (SRC1 = NaN):
DEST := SRC2
ELSE IF (SRC2 = NaN):
DEST := SRC2
ELSE IF (SRC1 < SRC2):
DEST := SRC1
ELSE:
DEST := SRC2
VMINSH—Return Minimum Scalar FP16 Value
Vol. 2C
5-399
INSTRUCTION SET REFERENCE, V
VMINSH dest, src1, src2
IF k1[0] OR *no writemask*:
DEST.fp16[0] := MIN(SRC1.fp16[0], SRC2.fp16[0])
ELSE IF *zeroing*:
DEST.fp16[0] := 0
// else dest.fp16[j] remains unchanged
DEST[127:16] := SRC1[127:16]
DEST[MAXVL-1:128] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VMINSH __m128h _mm_mask_min_round_sh (__m128h src, __mmask8 k, __m128h a, __m128h b, int sae);
VMINSH __m128h _mm_maskz_min_round_sh (__mmask8 k, __m128h a, __m128h b, int sae);
VMINSH __m128h _mm_min_round_sh (__m128h a, __m128h b, int sae);
VMINSH __m128h _mm_mask_min_sh (__m128h src, __mmask8 k, __m128h a, __m128h b);
VMINSH __m128h _mm_maskz_min_sh (__mmask8 k, __m128h a, __m128h b);
VMINSH __m128h _mm_min_sh (__m128h a, __m128h b);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”
5-400
Vol. 2C
VMINSH—Return Minimum Scalar FP16 Value
INSTRUCTION SET REFERENCE, V
VMOVSH—Move Scalar FP16 Value
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.LLIG.F3.MAP5.W0 10 /r
A
V/V
AVX512-FP16
Move FP16 value from m16 to xmm1 subject to
VMOVSH xmm1{k1}{z}, m16
writemask k1.
EVEX.LLIG.F3.MAP5.W0 11 /r
B
V/V
AVX512-FP16
Move low FP16 value from xmm1 to m16 subject
VMOVSH m16{k1}, xmm1
to writemask k1.
EVEX.LLIG.F3.MAP5.W0 10 /r
C
V/V
AVX512-FP16
Move low FP16 values from xmm3 to xmm1
VMOVSH xmm1{k1}{z}, xmm2, xmm3
subject to writemask k1. Bits 127:16 of xmm2
are copied to xmm1[127:16].
EVEX.LLIG.F3.MAP5.W0 11 /r
D
V/V
AVX512-FP16
Move low FP16 values from xmm3 to xmm1
VMOVSH xmm1{k1}{z}, xmm2, xmm3
subject to writemask k1. Bits 127:16 of xmm2
are copied to xmm1[127:16].
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
B
Scalar
ModRM:r/m (w)
ModRM:reg (r)
N/A
N/A
C
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
D
N/A
ModRM:r/m (w)
VEX.vvvv (r)
ModRM:reg (r)
N/A
Description
This instruction moves a FP16 value to a register or memory location.
The two register-only forms are aliases and differ only in where their operands are encoded; this is a side effect of
the encodings selected.
Operation
VMOVSH dest, src (two operand load)
IF k1[0] or no writemask:
DEST.fp16[0] := SRC.fp16[0]
ELSE IF *zeroing*:
DEST.fp16[0] := 0
// ELSE DEST.fp16[0] remains unchanged
DEST[MAXVL:16] := 0
VMOVSH dest, src (two operand store)
IF k1[0] or no writemask:
DEST.fp16[0] := SRC.fp16[0]
// ELSE DEST.fp16[0] remains unchanged
VMOVSH—Move Scalar FP16 Value
Vol. 2C
5-401
INSTRUCTION SET REFERENCE, V
VMOVSH dest, src1, src2 (three operand copy)
IF k1[0] or no writemask:
DEST.fp16[0] := SRC2.fp16[0]
ELSE IF *zeroing*:
DEST.fp16[0] := 0
// ELSE DEST.fp16[0] remains unchanged
DEST[127:16] := SRC1[127:16]
DEST[MAXVL:128] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VMOVSH __m128h _mm_load_sh (void const* mem_addr);
VMOVSH __m128h _mm_mask_load_sh (__m128h src, __mmask8 k, void const* mem_addr);
VMOVSH __m128h _mm_maskz_load_sh (__mmask8 k, void const* mem_addr);
VMOVSH __m128h _mm_mask_move_sh (__m128h src, __mmask8 k, __m128h a, __m128h b);
VMOVSH __m128h _mm_maskz_move_sh (__mmask8 k, __m128h a, __m128h b);
VMOVSH __m128h _mm_move_sh (__m128h a, __m128h b);
VMOVSH void _mm_mask_store_sh (void * mem_addr, __mmask8 k, __m128h a);
VMOVSH void _mm_store_sh (void * mem_addr, __m128h a);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Table 2-51, “Type E5 Class Exception Conditions.”
5-402
Vol. 2C
VMOVSH—Move Scalar FP16 Value
INSTRUCTION SET REFERENCE, V
VMOVW—Move Word
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.66.MAP5.WIG 6E /r
A
V/V
AVX512-FP16
Copy word from reg/m16 to xmm1.
VMOVW xmm1, reg/m16
EVEX.128.66.MAP5.WIG 7E /r
B
V/V
AVX512-FP16
Copy word from xmm1 to reg/m16.
VMOVW reg/m16, xmm1
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
B
Scalar
ModRM:r/m (w)
ModRM:reg (r)
N/A
N/A
Description
This instruction either (a) copies one word element from an XMM register to a general-purpose register or memory
location or (b) copies one word element from a general-purpose register or memory location to an XMM register.
When writing a general-purpose register, the lower 16-bits of the register will contain the word value. The upper bits
of the general-purpose register are written with zeros.
Operation
VMOVW dest, src (two operand load)
DEST.word[0] := SRC.word[0]
DEST[MAXVL:16] := 0
VMOVW dest, src (two operand store)
DEST.word[0] := SRC.word[0]
// upper bits of GPR DEST are zeroed
Intel C/C++ Compiler Intrinsic Equivalent
VMOVW short _mm_cvtsi128_si16 (__m128i a);
VMOVW __m128i _mm_cvtsi16_si128 (short a);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instructions, see Table 2-57, “Type E9NF Class Exception Conditions.”
VMOVW—Move Word
Vol. 2C
5-403
INSTRUCTION SET REFERENCE, V
VMULPH—Multiply Packed FP16 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.NP.MAP5.W0 59 /r
A
V/V
AVX512-FP16
Multiply packed FP16 values from xmm3/m128/
VMULPH xmm1{k1}{z}, xmm2, xmm3/
AVX512VL
m16bcst to xmm2 and store the result in xmm1
m128/m16bcst
subject to writemask k1.
EVEX.256.NP.MAP5.W0 59 /r
A
V/V
AVX512-FP16
Multiply packed FP16 values from ymm3/m256/
VMULPH ymm1{k1}{z}, ymm2, ymm3/
AVX512VL
m16bcst to ymm2 and store the result in ymm1
m256/m16bcst
subject to writemask k1.
EVEX.512.NP.MAP5.W0 59 /r
A
V/V
AVX512-FP16
Multiply packed FP16 values in zmm3/m512/
VMULPH zmm1{k1}{z}, zmm2, zmm3/
m16bcst with zmm2 and store the result in
m512/m16bcst {er}
zmm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
This instruction multiplies packed FP16 values from source operands and stores the packed FP16 result in the desti-
nation operand. The destination elements are updated according to the writemask.
Operation
VMULPH (EVEX encoded versions) when src2 operand is a register
VL = 128, 256 or 512
KL := VL/16
IF (VL = 512) AND (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE
SET_RM(MXCSR.RC)
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
DEST.fp16[j] := SRC1.fp16[j] * SRC2.fp16[j]
ELSE IF *zeroing*:
DEST.fp16[j] := 0
// else dest.fp16[j] remains unchanged
DEST[MAXVL-1:VL] := 0
5-404
Vol. 2C
VMULPH—Multiply Packed FP16 Values
INSTRUCTION SET REFERENCE, V
VMULPH (EVEX encoded versions) when src2 operand is a memory source
VL = 128, 256 or 512
KL := VL/16
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF EVEX.b = 1:
DEST.fp16[j] := SRC1.fp16[j] * SRC2.fp16[0]
ELSE:
DEST.fp16[j] := SRC1.fp16[j] * SRC2.fp16[j]
ELSE IF *zeroing*:
DEST.fp16[j] := 0
// else dest.fp16[j] remains unchanged
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VMULPH __m128h _mm_mask_mul_ph (__m128h src, __mmask8 k, __m128h a, __m128h b);
VMULPH __m128h _mm_maskz_mul_ph (__mmask8 k, __m128h a, __m128h b);
VMULPH __m128h _mm_mul_ph (__m128h a, __m128h b);
VMULPH __m256h _mm256_mask_mul_ph (__m256h src, __mmask16 k, __m256h a, __m256h b);
VMULPH __m256h _mm256_maskz_mul_ph (__mmask16 k, __m256h a, __m256h b);
VMULPH __m256h _mm256_mul_ph (__m256h a, __m256h b);
VMULPH __m512h _mm512_mask_mul_ph (__m512h src, __mmask32 k, __m512h a, __m512h b);
VMULPH __m512h _mm512_maskz_mul_ph (__mmask32 k, __m512h a, __m512h b);
VMULPH __m512h _mm512_mul_ph (__m512h a, __m512h b);
VMULPH __m512h _mm512_mask_mul_round_ph (__m512h src, __mmask32 k, __m512h a, __m512h b, int rounding);
VMULPH __m512h _mm512_maskz_mul_round_ph (__mmask32 k, __m512h a, __m512h b, int rounding);
VMULPH __m512h _mm512_mul_round_ph (__m512h a, __m512h b, int rounding);
SIMD Floating-Point Exceptions
Invalid, Underflow, Overflow, Precision, Denormal
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
VMULPH—Multiply Packed FP16 Values
Vol. 2C
5-405
INSTRUCTION SET REFERENCE, V
VMULSH—Multiply Scalar FP16 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.LLIG.F3.MAP5.W0 59 /r
A
V/V
AVX512-FP16
Multiply the low FP16 value in xmm3/m16 by low
VMULSH xmm1{k1}{z}, xmm2,
FP16 value in xmm2, and store the result in
xmm3/m16 {er}
xmm1 subject to writemask k1. Bits 127:16 of
xmm2 are copied to xmm1[127:16].
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
This instruction multiplies the low FP16 value from the source operands and stores the FP16 result in the destina-
tion operand. Bits 127:16 of the destination operand are copied from the corresponding bits of the first source
operand. Bits MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the destination is
updated according to the writemask.
Operation
VMULSH (EVEX encoded versions)
IF EVEX.b = 1 and SRC2 is a register:
SET_RM(EVEX.RC)
ELSE
SET_RM(MXCSR.RC)
IF k1[0] OR *no writemask*:
DEST.fp16[0] := SRC1.fp16[0] * SRC2.fp16[0]
ELSE IF *zeroing*:
DEST.fp16[0] := 0
// else dest.fp16[0] remains unchanged
DEST[127:16] := SRC1[127:16]
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VMULSH __m128h _mm_mask_mul_round_sh (__m128h src, __mmask8 k, __m128h a, __m128h b, int rounding);
VMULSH __m128h _mm_maskz_mul_round_sh (__mmask8 k, __m128h a, __m128h b, int rounding);
VMULSH __m128h _mm_mul_round_sh (__m128h a, __m128h b, int rounding);
VMULSH __m128h _mm_mask_mul_sh (__m128h src, __mmask8 k, __m128h a, __m128h b);
VMULSH __m128h _mm_maskz_mul_sh (__mmask8 k, __m128h a, __m128h b);
VMULSH __m128h _mm_mul_sh (__m128h a, __m128h b);
SIMD Floating-Point Exceptions
Invalid, Underflow, Overflow, Precision, Denormal
Other Exceptions
EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”
5-406
Vol. 2C
VMULSH—Multiply Scalar FP16 Values
INSTRUCTION SET REFERENCE, V
VP2INTERSECTD/VP2INTERSECTQ—Compute Intersection Between DWORDS/QUADWORDS to a
Pair of Mask Registers
Opcode/
Op/
64/32
CPUID Feature Flag
Description
Instruction
En
bit Mode
Support
EVEX.NDS.128.F2.0F38.W0 68 /r
A
V/V
AVX512VL
Store, in an even/odd pair of mask registers,
VP2INTERSECTD k1+1, xmm2,
AVX512_VP2INTERSECT
the indicators of the locations of value
xmm3/m128/m32bcst
matches between dwords in
xmm3/m128/m32bcst and xmm2.
EVEX.NDS.256.F2.0F38.W0 68 /r
A
V/V
AVX512VL
Store, in an even/odd pair of mask registers,
VP2INTERSECTD k1+1, ymm2,
AVX512_VP2INTERSECT
the indicators of the locations of value
ymm3/m256/m32bcst
matches between dwords in
ymm3/m256/m32bcst and ymm2.
EVEX.NDS.512.F2.0F38.W0 68 /r
A
V/V
AVX512F
Store, in an even/odd pair of mask registers,
VP2INTERSECTD k1+1, zmm2,
AVX512_VP2INTERSECT
the indicators of the locations of value
zmm3/m512/m32bcst
matches between dwords in
zmm3/m512/m32bcst and zmm2.
EVEX.NDS.128.F2.0F38.W1 68 /r
A
V/V
AVX512VL
Store, in an even/odd pair of mask registers,
VP2INTERSECTQ k1+1, xmm2,
AVX512_VP2INTERSECT
the indicators of the locations of value
xmm3/m128/m64bcst
matches between quadwords in
xmm3/m128/m64bcst and xmm2.
EVEX.NDS.256.F2.0F38.W1 68 /r
A
V/V
AVX512VL
Store, in an even/odd pair of mask registers,
VP2INTERSECTQ k1+1, ymm2,
AVX512_VP2INTERSECT
the indicators of the locations of value
ymm3/m256/m64bcst
matches between quadwords in
ymm3/m256/m64bcst and ymm2.
EVEX.NDS.512.F2.0F38.W1 68 /r
A
V/V
AVX512F
Store, in an even/odd pair of mask registers,
VP2INTERSECTQ k1+1, zmm2,
AVX512_VP2INTERSECT
the indicators of the locations of value
zmm3/m512/m64bcst
matches between quadwords in
zmm3/m512/m64bcst and zmm2.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
This instruction writes an even/odd pair of mask registers. The mask register destination indicated in the
MODRM.REG field is used to form the basis of the register pair. The low bit of that field is masked off (set to zero)
to create the first register of the pair.
EVEX.aaa and EVEX.z must be zero.
VP2INTERSECTD/VP2INTERSECTQ—Compute Intersection Between DWORDS/QUADWORDS to a Pair of Mask Registers
Vol. 2C
5-407
INSTRUCTION SET REFERENCE, V
Operation
VP2INTERSECTD destmask, src1, src2
(KL, VL) = (4, 128), (8, 256), (16, 512)
// dest_mask_reg_id is the register id specified in the instruction for destmask
dest_base := dest_mask_reg_id & ~1
// maskregs[ ] is an array representing the mask registers
maskregs[dest_base+0][MAX_KL-1:0] := 0
maskregs[dest_base+1][MAX_KL-1:0] := 0
FOR i := 0 to KL-1:
FOR j := 0 to KL-1:
match := (src1.dword[i] == src2.dword[j])
maskregs[dest_base+0].bit[i] |= match
maskregs[dest_base+1].bit[j] |= match
VP2INTERSECTQ destmask, src1, src2
(KL, VL) = (2, 128), (4, 256), (8, 512)
// dest_mask_reg_id is the register id specified in the instruction for destmask
dest_base := dest_mask_reg_id & ~1
// maskregs[ ] is an array representing the mask registers
maskregs[dest_base+0][MAX_KL-1:0] := 0
maskregs[dest_base+1][MAX_KL-1:0] := 0
FOR i = 0 to KL-1:
FOR j = 0 to KL-1:
match := (src1.qword[i] == src2.qword[j])
maskregs[dest_base+0].bit[i] |= match
maskregs[dest_base+1].bit[j] |= match
Intel C/C++ Compiler Intrinsic Equivalent
VP2INTERSECTD void _mm_2intersect_epi32(__m128i, __m128i, __mmask8 *, __mmask8 *);
VP2INTERSECTD void _mm256_2intersect_epi32(__m256i, __m256i, __mmask8 *, __mmask8 *);
VP2INTERSECTD void _mm512_2intersect_epi32(__m512i, __m512i, __mmask16 *, __mmask16 *);
VP2INTERSECTQ void _mm_2intersect_epi64(__m128i, __m128i, __mmask8 *, __mmask8 *);
VP2INTERSECTQ void _mm256_2intersect_epi64(__m256i, __m256i, __mmask8 *, __mmask8 *);
VP2INTERSECTQ void _mm512_2intersect_epi64(__m512i, __m512i, __mmask8 *, __mmask8 *);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-50, “Type E4NF Class Exception Conditions.”
5-408
Vol. 2C
VP2INTERSECTD/VP2INTERSECTQ—Compute Intersection Between DWORDS/QUADWORDS to a Pair of Mask Registers
INSTRUCTION SET REFERENCE, V
VPBLENDD—Blend Packed Dwords
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
-bit
Feature
Mode
Flag
VEX.128.66.0F3A.W0 02 /r ib
RVMI
V/V
AVX2
Select dwords from xmm2 and xmm3/m128 from
VPBLENDD xmm1, xmm2, xmm3/m128, imm8
mask specified in imm8 and store the values into
xmm1.
VEX.256.66.0F3A.W0 02 /r ib
RVMI
V/V
AVX2
Select dwords from ymm2 and ymm3/m256 from
VPBLENDD ymm1, ymm2, ymm3/m256, imm8
mask specified in imm8 and store the values into
ymm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVMI
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
imm8
Description
Dword elements from the source operand (second operand) are conditionally written to the destination operand
(first operand) depending on bits in the immediate operand (third operand). The immediate bits (bits 7:0) form a
mask that determines whether the corresponding word in the destination is copied from the source. If a bit in the
mask, corresponding to a word, is “1", then the word is copied, else the word is unchanged.
VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The
first source and destination operands are XMM registers. Bits (MAXVL-1:128) of the corresponding YMM register
are zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register.
Operation
VPBLENDD (VEX.256 encoded version)
IF (imm8[0] == 1) THEN DEST[31:0] := SRC2[31:0]
ELSE DEST[31:0] := SRC1[31:0]
IF (imm8[1] == 1) THEN DEST[63:32] := SRC2[63:32]
ELSE DEST[63:32] := SRC1[63:32]
IF (imm8[2] == 1) THEN DEST[95:64] := SRC2[95:64]
ELSE DEST[95:64] := SRC1[95:64]
IF (imm8[3] == 1) THEN DEST[127:96] := SRC2[127:96]
ELSE DEST[127:96] := SRC1[127:96]
IF (imm8[4] == 1) THEN DEST[159:128] := SRC2[159:128]
ELSE DEST[159:128] := SRC1[159:128]
IF (imm8[5] == 1) THEN DEST[191:160] := SRC2[191:160]
ELSE DEST[191:160] := SRC1[191:160]
IF (imm8[6] == 1) THEN DEST[223:192] := SRC2[223:192]
ELSE DEST[223:192] := SRC1[223:192]
IF (imm8[7] == 1) THEN DEST[255:224] := SRC2[255:224]
ELSE DEST[255:224] := SRC1[255:224]
VPBLENDD—Blend Packed Dwords
Vol. 2C
5-409
INSTRUCTION SET REFERENCE, V
VPBLENDD (VEX.128 encoded version)
IF (imm8[0] == 1) THEN DEST[31:0] := SRC2[31:0]
ELSE DEST[31:0] := SRC1[31:0]
IF (imm8[1] == 1) THEN DEST[63:32] := SRC2[63:32]
ELSE DEST[63:32] := SRC1[63:32]
IF (imm8[2] == 1) THEN DEST[95:64] := SRC2[95:64]
ELSE DEST[95:64] := SRC1[95:64]
IF (imm8[3] == 1) THEN DEST[127:96] := SRC2[127:96]
ELSE DEST[127:96] := SRC1[127:96]
DEST[MAXVL-1:128] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPBLENDD:
__m128i _mm_blend_epi32 (__m128i v1, __m128i v2, const int mask)
VPBLENDD:
__m256i _mm256_blend_epi32 (__m256i v1, __m256i v2, const int mask)
SIMD Floating-Point Exceptions
None
Other Exceptions
See Table 2-21, “Type 4 Class Exception Conditions.”
Additionally:
#UD
If VEX.W = 1.
5-410
Vol. 2C
VPBLENDD—Blend Packed Dwords
INSTRUCTION SET REFERENCE, V
VPBLENDMB/VPBLENDMW—Blend Byte/Word Vectors Using an Opmask Control
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F38.W0 66 /r
A
V/V
AVX512VL
Blend byte integer vector xmm2 and byte vector
VPBLENDMB xmm1 {k1}{z},
AVX512BW
xmm3/m128 and store the result in xmm1, under control
xmm2, xmm3/m128
mask.
EVEX.256.66.0F38.W0 66 /r
A
V/V
AVX512VL
Blend byte integer vector ymm2 and byte vector
VPBLENDMB ymm1 {k1}{z},
AVX512BW
ymm3/m256 and store the result in ymm1, under control
ymm2, ymm3/m256
mask.
EVEX.512.66.0F38.W0 66 /r
A
V/V
AVX512BW
Blend byte integer vector zmm2 and byte vector
VPBLENDMB zmm1 {k1}{z},
zmm3/m512 and store the result in zmm1, under control
zmm2, zmm3/m512
mask.
EVEX.128.66.0F38.W1 66 /r
A
V/V
AVX512VL
Blend word integer vector xmm2 and word vector
VPBLENDMW xmm1 {k1}{z},
AVX512BW
xmm3/m128 and store the result in xmm1, under control
xmm2, xmm3/m128
mask.
EVEX.256.66.0F38.W1 66 /r
A
V/V
AVX512VL
Blend word integer vector ymm2 and word vector
VPBLENDMW ymm1 {k1}{z},
AVX512BW
ymm3/m256 and store the result in ymm1, under control
ymm2, ymm3/m256
mask.
EVEX.512.66.0F38.W1 66 /r
A
V/V
AVX512BW
Blend word integer vector zmm2 and word vector
VPBLENDMW zmm1 {k1}{z},
zmm3/m512 and store the result in zmm1, under control
zmm2, zmm3/m512
mask.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full Mem
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Performs an element-by-element blending of byte/word elements between the first source operand byte vector
register and the second source operand byte vector from memory or register, using the instruction mask as
selector. The result is written into the destination byte vector register.
The destination and first source operands are ZMM/YMM/XMM registers. The second source operand can be a
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit memory location.
The mask is not used as a writemask for this instruction. Instead, the mask is used as an element selector: every
element of the destination is conditionally selected between first source or second source using the value of the
related mask bit (0 for first source, 1 for second source).
VPBLENDMB/VPBLENDMW—Blend Byte/Word Vectors Using an Opmask Control
Vol. 2C
5-411
INSTRUCTION SET REFERENCE, V
Operation
VPBLENDMB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j := 0 TO KL-1
i := j * 8
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := SRC2[i+7:i]
ELSE
IF *merging-masking*
; merging-masking
THEN DEST[i+7:i] := SRC1[i+7:i]
ELSE
; zeroing-masking
DEST[i+7:i] := 0
FI;
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0;
VPBLENDMW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1
i := j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := SRC2[i+15:i]
ELSE
IF *merging-masking*
; merging-masking
THEN DEST[i+15:i] := SRC1[i+15:i]
ELSE
; zeroing-masking
DEST[i+15:i] := 0
FI;
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPBLENDMB __m512i _mm512_mask_blend_epi8(__mmask64 m, __m512i a, __m512i b);
VPBLENDMB __m256i _mm256_mask_blend_epi8(__mmask32 m, __m256i a, __m256i b);
VPBLENDMB __m128i _mm_mask_blend_epi8(__mmask16 m, __m128i a, __m128i b);
VPBLENDMW __m512i _mm512_mask_blend_epi16(__mmask32 m, __m512i a, __m512i b);
VPBLENDMW __m256i _mm256_mask_blend_epi16(__mmask16 m, __m256i a, __m256i b);
VPBLENDMW __m128i _mm_mask_blend_epi16(__mmask8 m, __m128i a, __m128i b);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Table 2-49, “Type E4 Class Exception Conditions.”
5-412
Vol. 2C
VPBLENDMB/VPBLENDMW—Blend Byte/Word Vectors Using an Opmask Control
INSTRUCTION SET REFERENCE, V
VPBLENDMD/VPBLENDMQ—Blend Int32/Int64 Vectors Using an OpMask Control
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F38.W0 64 /r
A
V/V
AVX512VL
Blend doubleword integer vector xmm2 and doubleword
VPBLENDMD xmm1 {k1}{z},
AVX512F
vector xmm3/m128/m32bcst and store the result in
xmm2, xmm3/m128/m32bcst
xmm1, under control mask.
EVEX.256.66.0F38.W0 64 /r
A
V/V
AVX512VL
Blend doubleword integer vector ymm2 and doubleword
VPBLENDMD ymm1 {k1}{z}, ymm2,
AVX512F
vector ymm3/m256/m32bcst and store the result in
ymm3/m256/m32bcst
ymm1, under control mask.
EVEX.512.66.0F38.W0 64 /r
A
V/V
AVX512F
Blend doubleword integer vector zmm2 and doubleword
VPBLENDMD zmm1 {k1}{z}, zmm2,
vector zmm3/m512/m32bcst and store the result in
zmm3/m512/m32bcst
zmm1, under control mask.
EVEX.128.66.0F38.W1 64 /r
A
V/V
AVX512VL
Blend quadword integer vector xmm2 and quadword
VPBLENDMQ xmm1 {k1}{z},
AVX512F
vector xmm3/m128/m64bcst and store the result in
xmm2, xmm3/m128/m64bcst
xmm1, under control mask.
EVEX.256.66.0F38.W1 64 /r
A
V/V
AVX512VL
Blend quadword integer vector ymm2 and quadword
VPBLENDMQ ymm1 {k1}{z},
AVX512F
vector ymm3/m256/m64bcst and store the result in
ymm2, ymm3/m256/m64bcst
ymm1, under control mask.
EVEX.512.66.0F38.W1 64 /r
A
V/V
AVX512F
Blend quadword integer vector zmm2 and quadword
VPBLENDMQ zmm1 {k1}{z}, zmm2,
vector zmm3/m512/m64bcst and store the result in
zmm3/m512/m64bcst
zmm1, under control mask.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Performs an element-by-element blending of dword/qword elements between the first source operand (the second
operand) and the elements of the second source operand (the third operand) using an opmask register as select
control. The blended result is written into the destination.
The destination and first source operands are ZMM registers. The second source operand can be a ZMM register, a
512-bit memory location or a 512-bit vector broadcasted from a 32-bit memory location.
The opmask register is not used as a writemask for this instruction. Instead, the mask is used as an element
selector: every element of the destination is conditionally selected between first source or second source using the
value of the related mask bit (0 for the first source operand, 1 for the second source operand).
If EVEX.z is set, the elements with corresponding mask bit value of 0 in the destination operand are zeroed.
VPBLENDMD/VPBLENDMQ—Blend Int32/Int64 Vectors Using an OpMask Control
Vol. 2C
5-413
INSTRUCTION SET REFERENCE, V
Operation
VPBLENDMD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no controlmask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
DEST[i+31:i] := SRC2[31:0]
ELSE
DEST[i+31:i] := SRC2[i+31:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN DEST[i+31:i] := SRC1[i+31:i]
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI;
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0;
VPBLENDMD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no controlmask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
DEST[i+31:i] := SRC2[31:0]
ELSE
DEST[i+31:i] := SRC2[i+31:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN DEST[i+31:i] := SRC1[i+31:i]
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI;
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
5-414
Vol. 2C
VPBLENDMD/VPBLENDMQ—Blend Int32/Int64 Vectors Using an OpMask Control
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VPBLENDMD __m512i _mm512_mask_blend_epi32(__mmask16 k, __m512i a, __m512i b);
VPBLENDMD __m256i _mm256_mask_blend_epi32(__mmask8 m, __m256i a, __m256i b);
VPBLENDMD __m128i _mm_mask_blend_epi32(__mmask8 m, __m128i a, __m128i b);
VPBLENDMQ __m512i _mm512_mask_blend_epi64(__mmask8 k, __m512i a, __m512i b);
VPBLENDMQ __m256i _mm256_mask_blend_epi64(__mmask8 m, __m256i a, __m256i b);
VPBLENDMQ __m128i _mm_mask_blend_epi64(__mmask8 m, __m128i a, __m128i b);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Table 2-49, “Type E4 Class Exception Conditions.”
VPBLENDMD/VPBLENDMQ—Blend Int32/Int64 Vectors Using an OpMask Control
Vol. 2C
5-415
INSTRUCTION SET REFERENCE, V
VPBROADCASTB/W/D/Q—Load With Broadcast Integer Data From General Purpose Register
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit
Feature
Mode
Flag
Support
EVEX.128.66.0F38.W0 7A /r
A
V/V
AVX512VL
Broadcast an 8-bit value from a GPR to all bytes in the
VPBROADCASTB xmm1 {k1}{z}, reg
AVX512BW
128-bit destination subject to writemask k1.
EVEX.256.66.0F38.W0 7A /r
A
V/V
AVX512VL
Broadcast an 8-bit value from a GPR to all bytes in the
VPBROADCASTB ymm1 {k1}{z}, reg
AVX512BW
256-bit destination subject to writemask k1.
EVEX.512.66.0F38.W0 7A /r
A
V/V
AVX512BW
Broadcast an 8-bit value from a GPR to all bytes in the
VPBROADCASTB zmm1 {k1}{z}, reg
512-bit destination subject to writemask k1.
EVEX.128.66.0F38.W0 7B /r
A
V/V
AVX512VL
Broadcast a 16-bit value from a GPR to all words in the
VPBROADCASTW xmm1 {k1}{z}, reg
AVX512BW
128-bit destination subject to writemask k1.
EVEX.256.66.0F38.W0 7B /r
A
V/V
AVX512VL
Broadcast a 16-bit value from a GPR to all words in the
VPBROADCASTW ymm1 {k1}{z}, reg
AVX512BW
256-bit destination subject to writemask k1.
EVEX.512.66.0F38.W0 7B /r
A
V/V
AVX512BW
Broadcast a 16-bit value from a GPR to all words in the
VPBROADCASTW zmm1 {k1}{z}, reg
512-bit destination subject to writemask k1.
EVEX.128.66.0F38.W0 7C /r
A
V/V
AVX512VL
Broadcast a 32-bit value from a GPR to all doublewords
VPBROADCASTD xmm1 {k1}{z}, r32
AVX512F
in the 128-bit destination subject to writemask k1.
EVEX.256.66.0F38.W0 7C /r
A
V/V
AVX512VL
Broadcast a 32-bit value from a GPR to all doublewords
VPBROADCASTD ymm1 {k1}{z}, r32
AVX512F
in the 256-bit destination subject to writemask k1.
EVEX.512.66.0F38.W0 7C /r
A
V/V
AVX512F
Broadcast a 32-bit value from a GPR to all doublewords
VPBROADCASTD zmm1 {k1}{z}, r32
in the 512-bit destination subject to writemask k1.
EVEX.128.66.0F38.W1 7C /r
A
V/N.E.1
AVX512VL
Broadcast a 64-bit value from a GPR to all quadwords in
VPBROADCASTQ xmm1 {k1}{z}, r64
AVX512F
the 128-bit destination subject to writemask k1.
EVEX.256.66.0F38.W1 7C /r
A
V/N.E.1
AVX512VL
Broadcast a 64-bit value from a GPR to all quadwords in
VPBROADCASTQ ymm1 {k1}{z}, r64
AVX512F
the 256-bit destination subject to writemask k1.
EVEX.512.66.0F38.W1 7C /r
A
V/N.E.1
AVX512F
Broadcast a 64-bit value from a GPR to all quadwords in
VPBROADCASTQ zmm1 {k1}{z}, r64
the 512-bit destination subject to writemask k1.
NOTES:
1. EVEX.W in non-64 bit is ignored; the instruction behaves as if the W0 version is used.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Scalar
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Broadcasts a 8-bit, 16-bit, 32-bit or 64-bit value from a general-purpose register (the second operand) to all the
locations in the destination vector register (the first operand) using the writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
5-416
Vol. 2C
VPBROADCASTB/W/D/Q—Load With Broadcast Integer Data From General Purpose Register
INSTRUCTION SET REFERENCE, V
Operation
VPBROADCASTB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j := 0 TO KL-1
i := j * 8
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := SRC[7:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+7:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPBROADCASTW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1
i := j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := SRC[15:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+15:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPBROADCASTD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := SRC[31:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPBROADCASTB/W/D/Q—Load With Broadcast Integer Data From General Purpose Register
Vol. 2C
5-417
INSTRUCTION SET REFERENCE, V
VPBROADCASTQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] := SRC[63:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPBROADCASTB __m512i _mm512_mask_set1_epi8(__m512i s, __mmask64 k, int a);
VPBROADCASTB __m512i _mm512_maskz_set1_epi8( __mmask64 k, int a);
VPBROADCASTB __m256i _mm256_mask_set1_epi8(__m256i s, __mmask32 k, int a);
VPBROADCASTB __m256i _mm256_maskz_set1_epi8( __mmask32 k, int a);
VPBROADCASTB __m128i _mm_mask_set1_epi8(__m128i s, __mmask16 k, int a);
VPBROADCASTB __m128i _mm_maskz_set1_epi8( __mmask16 k, int a);
VPBROADCASTD __m512i _mm512_mask_set1_epi32(__m512i s, __mmask16 k, int a);
VPBROADCASTD __m512i _mm512_maskz_set1_epi32( __mmask16 k, int a);
VPBROADCASTD __m256i _mm256_mask_set1_epi32(__m256i s, __mmask8 k, int a);
VPBROADCASTD __m256i _mm256_maskz_set1_epi32( __mmask8 k, int a);
VPBROADCASTD __m128i _mm_mask_set1_epi32(__m128i s, __mmask8 k, int a);
VPBROADCASTD __m128i _mm_maskz_set1_epi32( __mmask8 k, int a);
VPBROADCASTQ __m512i _mm512_mask_set1_epi64(__m512i s, __mmask8 k, __int64 a);
VPBROADCASTQ __m512i _mm512_maskz_set1_epi64( __mmask8 k, __int64 a);
VPBROADCASTQ __m256i _mm256_mask_set1_epi64(__m256i s, __mmask8 k, __int64 a);
VPBROADCASTQ __m256i _mm256_maskz_set1_epi64( __mmask8 k, __int64 a);
VPBROADCASTQ __m128i _mm_mask_set1_epi64(__m128i s, __mmask8 k, __int64 a);
VPBROADCASTQ __m128i _mm_maskz_set1_epi64( __mmask8 k, __int64 a);
VPBROADCASTW __m512i _mm512_mask_set1_epi16(__m512i s, __mmask32 k, int a);
VPBROADCASTW __m512i _mm512_maskz_set1_epi16( __mmask32 k, int a);
VPBROADCASTW __m256i _mm256_mask_set1_epi16(__m256i s, __mmask16 k, int a);
VPBROADCASTW __m256i _mm256_maskz_set1_epi16( __mmask16 k, int a);
VPBROADCASTW __m128i _mm_mask_set1_epi16(__m128i s, __mmask8 k, int a);
VPBROADCASTW __m128i _mm_maskz_set1_epi16( __mmask8 k, int a);
Exceptions
EVEX-encoded instructions, see Table 2-55, “Type E7NM Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
5-418
Vol. 2C
VPBROADCASTB/W/D/Q—Load With Broadcast Integer Data From General Purpose Register
INSTRUCTION SET REFERENCE, V
VPBROADCAST—Load Integer and Broadcast
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
VEX.128.66.0F38.W0 78 /r
A
V/V
AVX2
Broadcast a byte integer in the source operand
VPBROADCASTB xmm1, xmm2/m8
to sixteen locations in xmm1.
VEX.256.66.0F38.W0 78 /r
A
V/V
AVX2
Broadcast a byte integer in the source operand
VPBROADCASTB ymm1, xmm2/m8
to thirty-two locations in ymm1.
EVEX.128.66.0F38.W0 78 /r
B
V/V
AVX512VL
Broadcast a byte integer in the source operand
VPBROADCASTB xmm1{k1}{z}, xmm2/m8
AVX512BW
to locations in xmm1 subject to writemask k1.
EVEX.256.66.0F38.W0 78 /r
B
V/V
AVX512VL
Broadcast a byte integer in the source operand
VPBROADCASTB ymm1{k1}{z}, xmm2/m8
AVX512BW
to locations in ymm1 subject to writemask k1.
EVEX.512.66.0F38.W0 78 /r
B
V/V
AVX512BW
Broadcast a byte integer in the source operand
VPBROADCASTB zmm1{k1}{z}, xmm2/m8
to 64 locations in zmm1 subject to writemask
k1.
VEX.128.66.0F38.W0 79 /r
A
V/V
AVX2
Broadcast a word integer in the source
VPBROADCASTW xmm1, xmm2/m16
operand to eight locations in xmm1.
VEX.256.66.0F38.W0 79 /r
A
V/V
AVX2
Broadcast a word integer in the source
VPBROADCASTW ymm1, xmm2/m16
operand to sixteen locations in ymm1.
EVEX.128.66.0F38.W0 79 /r
B
V/V
AVX512VL
Broadcast a word integer in the source
VPBROADCASTW xmm1{k1}{z}, xmm2/m16
AVX512BW
operand to locations in xmm1 subject to
writemask k1.
EVEX.256.66.0F38.W0 79 /r
B
V/V
AVX512VL
Broadcast a word integer in the source
VPBROADCASTW ymm1{k1}{z}, xmm2/m16
AVX512BW
operand to locations in ymm1 subject to
writemask k1.
EVEX.512.66.0F38.W0 79 /r
B
V/V
AVX512BW
Broadcast a word integer in the source
VPBROADCASTW zmm1{k1}{z}, xmm2/m16
operand to 32 locations in zmm1 subject to
writemask k1.
VEX.128.66.0F38.W0 58 /r
A
V/V
AVX2
Broadcast a dword integer in the source
VPBROADCASTD xmm1, xmm2/m32
operand to four locations in xmm1.
VEX.256.66.0F38.W0 58 /r
A
V/V
AVX2
Broadcast a dword integer in the source
VPBROADCASTD ymm1, xmm2/m32
operand to eight locations in ymm1.
EVEX.128.66.0F38.W0 58 /r
B
V/V
AVX512VL
Broadcast a dword integer in the source
VPBROADCASTD xmm1 {k1}{z}, xmm2/m32
AVX512F
operand to locations in xmm1 subject to
writemask k1.
EVEX.256.66.0F38.W0 58 /r
B
V/V
AVX512VL
Broadcast a dword integer in the source
VPBROADCASTD ymm1 {k1}{z}, xmm2/m32
AVX512F
operand to locations in ymm1 subject to
writemask k1.
EVEX.512.66.0F38.W0 58 /r
B
V/V
AVX512F
Broadcast a dword integer in the source
VPBROADCASTD zmm1 {k1}{z}, xmm2/m32
operand to locations in zmm1 subject to
writemask k1.
VEX.128.66.0F38.W0 59 /r
A
V/V
AVX2
Broadcast a qword element in source operand
VPBROADCASTQ xmm1, xmm2/m64
to two locations in xmm1.
VEX.256.66.0F38.W0 59 /r
A
V/V
AVX2
Broadcast a qword element in source operand
VPBROADCASTQ ymm1, xmm2/m64
to four locations in ymm1.
EVEX.128.66.0F38.W1 59 /r
B
V/V
AVX512VL
Broadcast a qword element in source operand
VPBROADCASTQ xmm1 {k1}{z}, xmm2/m64
AVX512F
to locations in xmm1 subject to writemask k1.
EVEX.256.66.0F38.W1 59 /r
B
V/V
AVX512VL
Broadcast a qword element in source operand
VPBROADCASTQ ymm1 {k1}{z}, xmm2/m64
AVX512F
to locations in ymm1 subject to writemask k1.
EVEX.512.66.0F38.W1 59 /r
B
V/V
AVX512F
Broadcast a qword element in source operand
VPBROADCASTQ zmm1 {k1}{z}, xmm2/m64
to locations in zmm1 subject to writemask k1.
EVEX.128.66.0F38.W0 59 /r
C
V/V
AVX512VL
Broadcast two dword elements in source
VBROADCASTI32x2 xmm1 {k1}{z}, xmm2/m64
AVX512DQ
operand to locations in xmm1 subject to
writemask k1.
VPBROADCAST—Load Integer and Broadcast
Vol. 2C
5-419
INSTRUCTION SET REFERENCE, V
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.256.66.0F38.W0 59 /r
C
V/V
AVX512VL
Broadcast two dword elements in source
VBROADCASTI32x2 ymm1 {k1}{z}, xmm2/m64
AVX512DQ
operand to locations in ymm1 subject to
writemask k1.
EVEX.512.66.0F38.W0 59 /r
C
V/V
AVX512DQ
Broadcast two dword elements in source
VBROADCASTI32x2 zmm1 {k1}{z}, xmm2/m64
operand to locations in zmm1 subject to
writemask k1.
VEX.256.66.0F38.W0 5A /r
A
V/V
AVX2
Broadcast 128 bits of integer data in mem to
VBROADCASTI128 ymm1, m128
low and high 128-bits in ymm1.
EVEX.256.66.0F38.W0 5A /r
D
V/V
AVX512VL
Broadcast 128 bits of 4 doubleword integer
VBROADCASTI32X4 ymm1 {k1}{z}, m128
AVX512F
data in mem to locations in ymm1 using
writemask k1.
EVEX.512.66.0F38.W0 5A /r
D
V/V
AVX512F
Broadcast 128 bits of 4 doubleword integer
VBROADCASTI32X4 zmm1 {k1}{z}, m128
data in mem to locations in zmm1 using
writemask k1.
EVEX.256.66.0F38.W1 5A /r
C
V/V
AVX512VL
Broadcast 128 bits of 2 quadword integer data
VBROADCASTI64X2 ymm1 {k1}{z}, m128
AVX512DQ
in mem to locations in ymm1 using writemask
k1.
EVEX.512.66.0F38.W1 5A /r
C
V/V
AVX512DQ
Broadcast 128 bits of 2 quadword integer data
VBROADCASTI64X2 zmm1 {k1}{z}, m128
in mem to locations in zmm1 using writemask
k1.
EVEX.512.66.0F38.W0 5B /r
E
V/V
AVX512DQ
Broadcast 256 bits of 8 doubleword integer
VBROADCASTI32X8 zmm1 {k1}{z}, m256
data in mem to locations in zmm1 using
writemask k1.
EVEX.512.66.0F38.W1 5B /r
D
V/V
AVX512F
Broadcast 256 bits of 4 quadword integer data
VBROADCASTI64X4 zmm1 {k1}{z}, m256
in mem to locations in zmm1 using writemask
k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
B
Tuple1 Scalar
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
C
Tuple2
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
D
Tuple4
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
E
Tuple8
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Load integer data from the source operand (the second operand) and broadcast to all elements of the destination
operand (the first operand).
VEX256-encoded VPBROADCASTB/W/D/Q: The source operand is 8-bit, 16-bit, 32-bit, 64-bit memory location or
the low 8-bit, 16-bit 32-bit, 64-bit data in an XMM register. The destination operand is a YMM register.
VPBROADCASTI128 support the source operand of 128-bit memory location. Register source encodings for
VPBROADCASTI128 is reserved and will #UD. Bits (MAXVL-1:256) of the destination register are zeroed.
EVEX-encoded VPBROADCASTD/Q: The source operand is a 32-bit, 64-bit memory location or the low 32-bit, 64-
bit data in an XMM register. The destination operand is a ZMM/YMM/XMM register and updated according to the
writemask k1.
VPBROADCASTI32X4 and VPBROADCASTI64X4: The destination operand is a ZMM register and updated according
to the writemask k1. The source operand is 128-bit or 256-bit memory location. Register source encodings for
VBROADCASTI32X4 and VBROADCASTI64X4 are reserved and will #UD.
5-420
Vol. 2C
VPBROADCAST—Load Integer and Broadcast
INSTRUCTION SET REFERENCE, V
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
If VPBROADCASTI128 is encoded with VEX.L= 0, an attempt to execute the instruction encoded with VEX.L= 0 will
cause an #UD exception.
m32
X0
DEST
X0
X0
X0
X0
X0
X0
X0
X0
Figure 5-16. VPBROADCASTD Operation (VEX.256 encoded version)
m32
X0
DEST
0
0
0
0
X0
X0
X0
X0
Figure 5-17. VPBROADCASTD Operation (128-bit version)
m64
X0
DEST
X0
X0
X0
X0
Figure 5-18. VPBROADCASTQ Operation (256-bit version)
VPBROADCAST—Load Integer and Broadcast
Vol. 2C
5-421
INSTRUCTION SET REFERENCE, V
m128
X0
DEST
X0
X0
Figure 5-19. VBROADCASTI128 Operation (256-bit version)
m256
X0
DEST
X0
X0
Figure 5-20. VBROADCASTI256 Operation (512-bit version)
Operation
VPBROADCASTB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j := 0 TO KL-1
i := j * 8
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := SRC[7:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+7:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
5-422
Vol. 2C
VPBROADCAST—Load Integer and Broadcast
INSTRUCTION SET REFERENCE, V
VPBROADCASTW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1
i := j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := SRC[15:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+15:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPBROADCASTD (128 bit version)
temp := SRC[31:0]
DEST[31:0] := temp
DEST[63:32] := temp
DEST[95:64] := temp
DEST[127:96] := temp
DEST[MAXVL-1:128] := 0
VPBROADCASTD (VEX.256 encoded version)
temp := SRC[31:0]
DEST[31:0] := temp
DEST[63:32] := temp
DEST[95:64] := temp
DEST[127:96] := temp
DEST[159:128] := temp
DEST[191:160] := temp
DEST[223:192] := temp
DEST[255:224] := temp
DEST[MAXVL-1:256] := 0
VPBROADCASTD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := SRC[31:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPBROADCAST—Load Integer and Broadcast
Vol. 2C
5-423
INSTRUCTION SET REFERENCE, V
VPBROADCASTQ (VEX.256 encoded version)
temp := SRC[63:0]
DEST[63:0] := temp
DEST[127:64] := temp
DEST[191:128] := temp
DEST[255:192] := temp
DEST[MAXVL-1:256] := 0
VPBROADCASTQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] := SRC[63:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VBROADCASTI32x2 (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
n := (j mod 2) * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := SRC[n+31:n]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VBROADCASTI128 (VEX.256 encoded version)
temp := SRC[127:0]
DEST[127:0] := temp
DEST[255:128] := temp
DEST[MAXVL-1:256] := 0
5-424
Vol. 2C
VPBROADCAST—Load Integer and Broadcast
INSTRUCTION SET REFERENCE, V
VBROADCASTI32X4 (EVEX encoded versions)
(KL, VL) = (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j* 32
n := (j modulo 4) * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := SRC[n+31:n]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VBROADCASTI64X2 (EVEX encoded versions)
(KL, VL) = (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 64
n := (j modulo 2) * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] := SRC[n+63:n]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] = 0
FI
FI;
ENDFOR;
VBROADCASTI32X8 (EVEX.U1.512 encoded version)
FOR j := 0 TO 15
i := j * 32
n := (j modulo 8) * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := SRC[n+31:n]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPBROADCAST—Load Integer and Broadcast
Vol. 2C
5-425
INSTRUCTION SET REFERENCE, V
VBROADCASTI64X4 (EVEX.512 encoded version)
FOR j := 0 TO 7
i := j * 64
n := (j modulo 4) * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] := SRC[n+63:n]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPBROADCASTB __m512i _mm512_broadcastb_epi8( __m128i a);
VPBROADCASTB __m512i _mm512_mask_broadcastb_epi8(__m512i s, __mmask64 k, __m128i a);
VPBROADCASTB __m512i _mm512_maskz_broadcastb_epi8( __mmask64 k, __m128i a);
VPBROADCASTB __m256i _mm256_broadcastb_epi8(__m128i a);
VPBROADCASTB __m256i _mm256_mask_broadcastb_epi8(__m256i s, __mmask32 k, __m128i a);
VPBROADCASTB __m256i _mm256_maskz_broadcastb_epi8( __mmask32 k, __m128i a);
VPBROADCASTB __m128i _mm_mask_broadcastb_epi8(__m128i s, __mmask16 k, __m128i a);
VPBROADCASTB __m128i _mm_maskz_broadcastb_epi8( __mmask16 k, __m128i a);
VPBROADCASTB __m128i _mm_broadcastb_epi8(__m128i a);
VPBROADCASTD __m512i _mm512_broadcastd_epi32( __m128i a);
VPBROADCASTD __m512i _mm512_mask_broadcastd_epi32(__m512i s, __mmask16 k, __m128i a);
VPBROADCASTD __m512i _mm512_maskz_broadcastd_epi32( __mmask16 k, __m128i a);
VPBROADCASTD __m256i _mm256_broadcastd_epi32( __m128i a);
VPBROADCASTD __m256i _mm256_mask_broadcastd_epi32(__m256i s, __mmask8 k, __m128i a);
VPBROADCASTD __m256i _mm256_maskz_broadcastd_epi32( __mmask8 k, __m128i a);
VPBROADCASTD __m128i _mm_broadcastd_epi32(__m128i a);
VPBROADCASTD __m128i _mm_mask_broadcastd_epi32(__m128i s, __mmask8 k, __m128i a);
VPBROADCASTD __m128i _mm_maskz_broadcastd_epi32( __mmask8 k, __m128i a);
VPBROADCASTQ __m512i _mm512_broadcastq_epi64( __m128i a);
VPBROADCASTQ __m512i _mm512_mask_broadcastq_epi64(__m512i s, __mmask8 k, __m128i a);
VPBROADCASTQ __m512i _mm512_maskz_broadcastq_epi64( __mmask8 k, __m128i a);
VPBROADCASTQ __m256i _mm256_broadcastq_epi64(__m128i a);
VPBROADCASTQ __m256i _mm256_mask_broadcastq_epi64(__m256i s, __mmask8 k, __m128i a);
VPBROADCASTQ __m256i _mm256_maskz_broadcastq_epi64( __mmask8 k, __m128i a);
VPBROADCASTQ __m128i _mm_broadcastq_epi64(__m128i a);
VPBROADCASTQ __m128i _mm_mask_broadcastq_epi64(__m128i s, __mmask8 k, __m128i a);
VPBROADCASTQ __m128i _mm_maskz_broadcastq_epi64( __mmask8 k, __m128i a);
VPBROADCASTW __m512i _mm512_broadcastw_epi16(__m128i a);
VPBROADCASTW __m512i _mm512_mask_broadcastw_epi16(__m512i s, __mmask32 k, __m128i a);
VPBROADCASTW __m512i _mm512_maskz_broadcastw_epi16( __mmask32 k, __m128i a);
VPBROADCASTW __m256i _mm256_broadcastw_epi16(__m128i a);
VPBROADCASTW __m256i _mm256_mask_broadcastw_epi16(__m256i s, __mmask16 k, __m128i a);
VPBROADCASTW __m256i _mm256_maskz_broadcastw_epi16( __mmask16 k, __m128i a);
VPBROADCASTW __m128i _mm_broadcastw_epi16(__m128i a);
VPBROADCASTW __m128i _mm_mask_broadcastw_epi16(__m128i s, __mmask8 k, __m128i a);
VPBROADCASTW __m128i _mm_maskz_broadcastw_epi16( __mmask8 k, __m128i a);
VBROADCASTI32x2 __m512i _mm512_broadcast_i32x2( __m128i a);
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Vol. 2C
VPBROADCAST—Load Integer and Broadcast