Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023)

INSTRUCTION SET REFERENCE, M-U

PSRLW/PSRLD/PSRLQ—Shift Packed Data Right Logical

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

NP 0F D1 /r¹

V/V

MMX

Shift words in mm right by amount specified in

mm/m64 while shifting in 0s.

PSRLW mm, mm/m64

66 0F D1 /r

V/V

SSE2

Shift words in xmm1 right by amount specified

in xmm2/m128 while shifting in 0s.

PSRLW xmm1, xmm2/m128

NP 0F 71 /2 ib¹

V/V

MMX

Shift words in mm right by imm8 while shifting

in 0s.

PSRLW mm, imm8

66 0F 71 /2 ib

V/V

SSE2

Shift words in xmm1 right by imm8 while

shifting in 0s.

PSRLW xmm1, imm8

NP 0F D2 /r¹

V/V

MMX

Shift doublewords in mm right by amount

specified in mm/m64 while shifting in 0s.

PSRLD mm, mm/m64

66 0F D2 /r

V/V

SSE2

Shift doublewords in xmm1 right by amount

specified in xmm2 /m128 while shifting in 0s.

PSRLD xmm1, xmm2/m128

NP 0F 72 /2 ib¹

V/V

MMX

Shift doublewords in mm right by imm8 while

shifting in 0s.

PSRLD mm, imm8

66 0F 72 /2 ib

V/V

SSE2

Shift doublewords in xmm1 right by imm8

while shifting in 0s.

PSRLD xmm1, imm8

NP 0F D3 /r¹

V/V

MMX

Shift mm right by amount specified in

mm/m64 while shifting in 0s.

PSRLQ mm, mm/m64

66 0F D3 /r

V/V

SSE2

Shift quadwords in xmm1 right by amount

specified in xmm2/m128 while shifting in 0s.

PSRLQ xmm1, xmm2/m128

NP 0F 73 /2 ib¹

V/V

MMX

Shift mm right by imm8 while shifting in 0s.

PSRLQ mm, imm8

66 0F 73 /2 ib

V/V

SSE2

Shift quadwords in xmm1 right by imm8 while

shifting in 0s.

PSRLQ xmm1, imm8

VEX.128.66.0F.WIG D1 /r

V/V

AVX

Shift words in xmm2 right by amount specified

in xmm3/m128 while shifting in 0s.

VPSRLW xmm1, xmm2, xmm3/m128

VEX.128.66.0F.WIG 71 /2 ib

V/V

AVX

Shift words in xmm2 right by imm8 while

shifting in 0s.

VPSRLW xmm1, xmm2, imm8

VEX.128.66.0F.WIG D2 /r

V/V

AVX

Shift doublewords in xmm2 right by amount

specified in xmm3/m128 while shifting in 0s.

VPSRLD xmm1, xmm2, xmm3/m128

VEX.128.66.0F.WIG 72 /2 ib

V/V

AVX

Shift doublewords in xmm2 right by imm8

while shifting in 0s.

VPSRLD xmm1, xmm2, imm8

VEX.128.66.0F.WIG D3 /r

V/V

AVX

Shift quadwords in xmm2 right by amount

specified in xmm3/m128 while shifting in 0s.

VPSRLQ xmm1, xmm2, xmm3/m128

VEX.128.66.0F.WIG 73 /2 ib

V/V

AVX

Shift quadwords in xmm2 right by imm8 while

shifting in 0s.

VPSRLQ xmm1, xmm2, imm8

VEX.256.66.0F.WIG D1 /r

V/V

AVX2

Shift words in ymm2 right by amount specified

in xmm3/m128 while shifting in 0s.

VPSRLW ymm1, ymm2, xmm3/m128

VEX.256.66.0F.WIG 71 /2 ib

V/V

AVX2

Shift words in ymm2 right by imm8 while

shifting in 0s.

VPSRLW ymm1, ymm2, imm8

PSRLW/PSRLD/PSRLQ—Shift Packed Data Right Logical

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INSTRUCTION SET REFERENCE, M-U

VEX.256.66.0F.WIG D2 /r

V/V

AVX2

Shift doublewords in ymm2 right by amount

VPSRLD ymm1, ymm2, xmm3/m128

specified in xmm3/m128 while shifting in 0s.

VEX.256.66.0F.WIG 72 /2 ib

V/V

AVX2

Shift doublewords in ymm2 right by imm8

while shifting in 0s.

VPSRLD ymm1, ymm2, imm8

VEX.256.66.0F.WIG D3 /r

V/V

AVX2

Shift quadwords in ymm2 right by amount

specified in xmm3/m128 while shifting in 0s.

VPSRLQ ymm1, ymm2, xmm3/m128

VEX.256.66.0F.WIG 73 /2 ib

V/V

AVX2

Shift quadwords in ymm2 right by imm8 while

shifting in 0s.

VPSRLQ ymm1, ymm2, imm8

EVEX.128.66.0F.WIG D1 /r

V/V

AVX512VL

Shift words in xmm2 right by amount specified

VPSRLW xmm1 {k1}{z}, xmm2, xmm3/m128

AVX512BW

in xmm3/m128 while shifting in 0s using

writemask k1.

EVEX.256.66.0F.WIG D1 /r

V/V

AVX512VL

Shift words in ymm2 right by amount specified

VPSRLW ymm1 {k1}{z}, ymm2, xmm3/m128

AVX512BW

in xmm3/m128 while shifting in 0s using

writemask k1.

EVEX.512.66.0F.WIG D1 /r

V/V

AVX512BW

Shift words in zmm2 right by amount specified

VPSRLW zmm1 {k1}{z}, zmm2, xmm3/m128

in xmm3/m128 while shifting in 0s using

writemask k1.

EVEX.128.66.0F.WIG 71 /2 ib

V/V

AVX512VL

Shift words in xmm2/m128 right by imm8

VPSRLW xmm1 {k1}{z}, xmm2/m128, imm8

AVX512BW

while shifting in 0s using writemask k1.

EVEX.256.66.0F.WIG 71 /2 ib

V/V

AVX512VL

Shift words in ymm2/m256 right by imm8

VPSRLW ymm1 {k1}{z}, ymm2/m256, imm8

AVX512BW

while shifting in 0s using writemask k1.

EVEX.512.66.0F.WIG 71 /2 ib

V/V

AVX512BW

Shift words in zmm2/m512 right by imm8

VPSRLW zmm1 {k1}{z}, zmm2/m512, imm8

while shifting in 0s using writemask k1.

EVEX.128.66.0F.W0 D2 /r

V/V

AVX512VL

Shift doublewords in xmm2 right by amount

VPSRLD xmm1 {k1}{z}, xmm2, xmm3/m128

AVX512F

specified in xmm3/m128 while shifting in 0s

using writemask k1.

EVEX.256.66.0F.W0 D2 /r

V/V

AVX512VL

Shift doublewords in ymm2 right by amount

VPSRLD ymm1 {k1}{z}, ymm2, xmm3/m128

AVX512F

specified in xmm3/m128 while shifting in 0s

using writemask k1.

EVEX.512.66.0F.W0 D2 /r

V/V

AVX512F

Shift doublewords in zmm2 right by amount

VPSRLD zmm1 {k1}{z}, zmm2, xmm3/m128

specified in xmm3/m128 while shifting in 0s

using writemask k1.

EVEX.128.66.0F.W0 72 /2 ib

V/V

AVX512VL

Shift doublewords in xmm2/m128/m32bcst

VPSRLD xmm1 {k1}{z}, xmm2/m128/m32bcst,

AVX512F

right by imm8 while shifting in 0s using

imm8

writemask k1.

EVEX.256.66.0F.W0 72 /2 ib

V/V

AVX512VL

Shift doublewords in ymm2/m256/m32bcst

VPSRLD ymm1 {k1}{z}, ymm2/m256/m32bcst,

AVX512F

right by imm8 while shifting in 0s using

imm8

writemask k1.

EVEX.512.66.0F.W0 72 /2 ib

V/V

AVX512F

Shift doublewords in zmm2/m512/m32bcst

VPSRLD zmm1 {k1}{z}, zmm2/m512/m32bcst,

right by imm8 while shifting in 0s using

imm8

writemask k1.

EVEX.128.66.0F.W1 D3 /r

V/V

AVX512VL

Shift quadwords in xmm2 right by amount

VPSRLQ xmm1 {k1}{z}, xmm2, xmm3/m128

AVX512F

specified in xmm3/m128 while shifting in 0s

using writemask k1.

EVEX.256.66.0F.W1 D3 /r

V/V

AVX512VL

Shift quadwords in ymm2 right by amount

VPSRLQ ymm1 {k1}{z}, ymm2, xmm3/m128

AVX512F

specified in xmm3/m128 while shifting in 0s

using writemask k1.

EVEX.512.66.0F.W1 D3 /r

V/V

AVX512F

Shift quadwords in zmm2 right by amount

VPSRLQ zmm1 {k1}{z}, zmm2, xmm3/m128

specified in xmm3/m128 while shifting in 0s

using writemask k1.

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PSRLW/PSRLD/PSRLQ—Shift Packed Data Right Logical

INSTRUCTION SET REFERENCE, M-U

EVEX.128.66.0F.W1 73 /2 ib

V/V

AVX512VL

Shift quadwords in xmm2/m128/m64bcst

VPSRLQ xmm1 {k1}{z}, xmm2/m128/m64bcst,

AVX512F

right by imm8 while shifting in 0s using

imm8

writemask k1.

EVEX.256.66.0F.W1 73 /2 ib

V/V

AVX512VL

Shift quadwords in ymm2/m256/m64bcst

VPSRLQ ymm1 {k1}{z}, ymm2/m256/m64bcst,

AVX512F

right by imm8 while shifting in 0s using

imm8

writemask k1.

EVEX.512.66.0F.W1 73 /2 ib

V/V

AVX512F

Shift quadwords in zmm2/m512/m64bcst

VPSRLQ zmm1 {k1}{z}, zmm2/m512/m64bcst,

right by imm8 while shifting in 0s using

imm8

writemask k1.

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2A and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Reg-

isters” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:r/m (r, w)

imm8

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

VEX.vvvv (w)

ModRM:r/m (r)

imm8

N/A

Full Mem

EVEX.vvvv (w)

ModRM:r/m (r)

imm8

N/A

Full

EVEX.vvvv (w)

ModRM:r/m (r)

imm8

N/A

Mem128

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Shifts the bits in the individual data elements (words, doublewords, or quadword) in the destination operand (first

operand) to the right by the number of bits specified in the count operand (second operand). As the bits in the data

elements are shifted right, the empty high-order bits are cleared (set to 0). If the value specified by the count

operand is greater than 15 (for words), 31 (for doublewords), or 63 (for a quadword), then the destination operand

is set to all 0s. Figure 4-19 gives an example of shifting words in a 64-bit operand.

Note that only the low 64-bits of a 128-bit count operand are checked to compute the count.

Pre-Shift

DEST

Shift Right

with Zero

Extension

Post-Shift

X3 >> COUNT

X2 >> COUNT

X1 >> COUNT

X0 >> COUNT

DEST

Figure 4-19. PSRLW, PSRLD, and PSRLQ Instruction Operation Using 64-bit Operand

The (V)PSRLW instruction shifts each of the words in the destination operand to the right by the number of bits

specified in the count operand; the (V)PSRLD instruction shifts each of the doublewords in the destination operand;

and the PSRLQ instruction shifts the quadword (or quadwords) in the destination operand.

In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to

access additional registers (XMM8-XMM15).

PSRLW/PSRLD/PSRLQ—Shift Packed Data Right Logical

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INSTRUCTION SET REFERENCE, M-U

Legacy SSE instruction 64-bit operand: The destination operand is an MMX technology register; the count operand

can be either an MMX technology register or an 64-bit memory location.

128-bit Legacy SSE version: The destination operand is an XMM register; the count operand can be either an XMM

are loaded but the upper 64 bits are ignored. Bits (MAXVL-1:128) of the corresponding YMM destination register

remain unchanged.

VEX.128 encoded version: The destination operand is an XMM register; the count operand can be either an XMM

are loaded but the upper 64 bits are ignored. Bits (MAXVL-1:128) of the destination YMM register are zeroed.

VEX.256 encoded version: The destination operand is a YMM register. The source operand is a YMM register or a

memory location. The count operand can come either from an XMM register or a memory location or an 8-bit imme-

diate. Bits (MAXVL-1:256) of the corresponding ZMM register are zeroed.

EVEX encoded versions: The destination operand is a ZMM register updated according to the writemask. The count

operand is either an 8-bit immediate (the immediate count version) or an 8-bit value from an XMM register or a

memory location (the variable count version). For the immediate count version, the source operand (the second

operand) can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32/64-bit

memory location. For the variable count version, the first source operand (the second operand) is a ZMM register,

the second source operand (the third operand, 8-bit variable count) can be an XMM register or a memory location.

Note: In VEX/EVEX encoded versions of shifts with an immediate count, vvvv of VEX/EVEX encode the destination

Note: For shifts with an immediate count (VEX.128.66.0F 71-73 /2, or EVEX.128.66.0F 71-73 /2),

VEX.vvvv/EVEX.vvvv encodes the destination register.

Operation

PSRLW (with 64-bit operand)

IF (COUNT > 15)

THEN

DEST[64:0] := 0000000000000000H

ELSE

DEST[15:0] := ZeroExtend(DEST[15:0] >> COUNT);

(* Repeat shift operation for 2nd and 3rd words *)

DEST[63:48] := ZeroExtend(DEST[63:48] >> COUNT);

FI;

PSRLD (with 64-bit operand)

IF (COUNT > 31)

THEN

DEST[64:0] := 0000000000000000H

ELSE

DEST[31:0] := ZeroExtend(DEST[31:0] >> COUNT);

DEST[63:32] := ZeroExtend(DEST[63:32] >> COUNT);

FI;

PSRLQ (with 64-bit operand)

IF (COUNT > 63)

THEN

DEST[64:0] := 0000000000000000H

ELSE

DEST := ZeroExtend(DEST >> COUNT);

FI;

LOGICAL_RIGHT_SHIFT_DWORDS1(SRC, COUNT_SRC)

COUNT := COUNT_SRC[63:0];

IF (COUNT > 31)

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PSRLW/PSRLD/PSRLQ—Shift Packed Data Right Logical

INSTRUCTION SET REFERENCE, M-U

THEN

DEST[31:0] := 0

ELSE

DEST[31:0] := ZeroExtend(SRC[31:0] >> COUNT);

FI;

LOGICAL_RIGHT_SHIFT_QWORDS1(SRC, COUNT_SRC)

COUNT := COUNT_SRC[63:0];

IF (COUNT > 63)

THEN

DEST[63:0] := 0

ELSE

DEST[63:0] := ZeroExtend(SRC[63:0] >> COUNT);

FI;

LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC, COUNT_SRC)

COUNT := COUNT_SRC[63:0];

IF (COUNT > 15)

THEN

DEST[255:0] := 0

ELSE

DEST[15:0] := ZeroExtend(SRC[15:0] >> COUNT);

(* Repeat shift operation for 2nd through 15th words *)

DEST[255:240] := ZeroExtend(SRC[255:240] >> COUNT);

FI;

LOGICAL_RIGHT_SHIFT_WORDS(SRC, COUNT_SRC)

COUNT := COUNT_SRC[63:0];

IF (COUNT > 15)

THEN

DEST[127:0] := 00000000000000000000000000000000H

ELSE

DEST[15:0] := ZeroExtend(SRC[15:0] >> COUNT);

(* Repeat shift operation for 2nd through 7th words *)

DEST[127:112] := ZeroExtend(SRC[127:112] >> COUNT);

FI;

LOGICAL_RIGHT_SHIFT_DWORDS_256b(SRC, COUNT_SRC)

COUNT := COUNT_SRC[63:0];

IF (COUNT > 31)

THEN

DEST[255:0] := 0

ELSE

DEST[31:0] := ZeroExtend(SRC[31:0] >> COUNT);

(* Repeat shift operation for 2nd through 3rd words *)

DEST[255:224] := ZeroExtend(SRC[255:224] >> COUNT);

FI;

LOGICAL_RIGHT_SHIFT_DWORDS(SRC, COUNT_SRC)

COUNT := COUNT_SRC[63:0];

IF (COUNT > 31)

THEN

DEST[127:0] := 00000000000000000000000000000000H

ELSE

DEST[31:0] := ZeroExtend(SRC[31:0] >> COUNT);

PSRLW/PSRLD/PSRLQ—Shift Packed Data Right Logical

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INSTRUCTION SET REFERENCE, M-U

(* Repeat shift operation for 2nd through 3rd words *)

DEST[127:96] := ZeroExtend(SRC[127:96] >> COUNT);

FI;

LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC, COUNT_SRC)

COUNT := COUNT_SRC[63:0];

IF (COUNT > 63)

THEN

DEST[255:0] := 0

ELSE

DEST[63:0] := ZeroExtend(SRC[63:0] >> COUNT);

DEST[127:64] := ZeroExtend(SRC[127:64] >> COUNT);

DEST[191:128] := ZeroExtend(SRC[191:128] >> COUNT);

DEST[255:192] := ZeroExtend(SRC[255:192] >> COUNT);

FI;

LOGICAL_RIGHT_SHIFT_QWORDS(SRC, COUNT_SRC)

COUNT := COUNT_SRC[63:0];

IF (COUNT > 63)

THEN

DEST[127:0] := 00000000000000000000000000000000H

ELSE

DEST[63:0] := ZeroExtend(SRC[63:0] >> COUNT);

DEST[127:64] := ZeroExtend(SRC[127:64] >> COUNT);

FI;

VPSRLW (EVEX versions, xmm/m128)

(KL, VL) = (8, 128), (16, 256), (32, 512)

IF VL = 128

TMP_DEST[127:0] := LOGICAL_RIGHT_SHIFT_WORDS_128b(SRC1[127:0], SRC2)

FI;

IF VL = 256

TMP_DEST[255:0] := LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], SRC2)

FI;

IF VL = 512

TMP_DEST[255:0] := LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], SRC2)

TMP_DEST[511:256] := LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1[511:256], SRC2)

FI;

FOR j := 0 TO KL-1

i := j * 16

IF k1[j] OR *no writemask*

THEN DEST[i+15:i] := TMP_DEST[i+15:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+15:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+15:i] = 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

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INSTRUCTION SET REFERENCE, M-U

VPSRLW (EVEX versions, imm8)

(KL, VL) = (8, 128), (16, 256), (32, 512)

IF VL = 128

TMP_DEST[127:0] := LOGICAL_RIGHT_SHIFT_WORDS_128b(SRC1[127:0], imm8)

FI;

IF VL = 256

TMP_DEST[255:0] := LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], imm8)

FI;

IF VL = 512

TMP_DEST[255:0] := LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], imm8)

TMP_DEST[511:256] := LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1[511:256], imm8)

FI;

FOR j := 0 TO KL-1

i := j * 16

IF k1[j] OR *no writemask*

THEN DEST[i+15:i] := TMP_DEST[i+15:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+15:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+15:i] = 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VPSRLW (ymm, ymm, xmm/m128) - VEX.256 encoding

DEST[255:0] := LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1, SRC2)

DEST[MAXVL-1:256] := 0;

VPSRLW (ymm, imm8) - VEX.256 encoding

DEST[255:0] := LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1, imm8)

DEST[MAXVL-1:256] := 0;

VPSRLW (xmm, xmm, xmm/m128) - VEX.128 encoding

DEST[127:0] := LOGICAL_RIGHT_SHIFT_WORDS(SRC1, SRC2)

DEST[MAXVL-1:128] := 0

VPSRLW (xmm, imm8) - VEX.128 encoding

DEST[127:0] := LOGICAL_RIGHT_SHIFT_WORDS(SRC1, imm8)

DEST[MAXVL-1:128] := 0

PSRLW (xmm, xmm, xmm/m128)

DEST[127:0] := LOGICAL_RIGHT_SHIFT_WORDS(DEST, SRC)

DEST[MAXVL-1:128] (Unmodified)

PSRLW (xmm, imm8)

DEST[127:0] := LOGICAL_RIGHT_SHIFT_WORDS(DEST, imm8)

DEST[MAXVL-1:128] (Unmodified)

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INSTRUCTION SET REFERENCE, M-U

VPSRLD (EVEX versions, xmm/m128)

(KL, VL) = (4, 128), (8, 256), (16, 512)

IF VL = 128

TMP_DEST[127:0] := LOGICAL_RIGHT_SHIFT_DWORDS_128b(SRC1[127:0], SRC2)

FI;

IF VL = 256

TMP_DEST[255:0] := LOGICAL_RIGHT_SHIFT_DWORDS_256b(SRC1[255:0], SRC2)

FI;

IF VL = 512

TMP_DEST[255:0] := LOGICAL_RIGHT_SHIFT_DWORDS_256b(SRC1[255:0], SRC2)

TMP_DEST[511:256] := LOGICAL_RIGHT_SHIFT_DWORDS_256b(SRC1[511:256], SRC2)

FI;

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] := TMP_DEST[i+31:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VPSRLD (EVEX versions, imm8)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) AND (SRC1 *is memory*)

THEN DEST[i+31:i] := LOGICAL_RIGHT_SHIFT_DWORDS1(SRC1[31:0], imm8)

ELSE DEST[i+31:i] := LOGICAL_RIGHT_SHIFT_DWORDS1(SRC1[i+31:i], imm8)

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VPSRLD (ymm, ymm, xmm/m128) - VEX.256 encoding

DEST[255:0] := LOGICAL_RIGHT_SHIFT_DWORDS_256b(SRC1, SRC2)

DEST[MAXVL-1:256] := 0;

VPSRLD (ymm, imm8) - VEX.256 encoding

DEST[255:0] := LOGICAL_RIGHT_SHIFT_DWORDS_256b(SRC1, imm8)

DEST[MAXVL-1:256] := 0;

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INSTRUCTION SET REFERENCE, M-U

VPSRLD (xmm, xmm, xmm/m128) - VEX.128 encoding

DEST[127:0] := LOGICAL_RIGHT_SHIFT_DWORDS(SRC1, SRC2)

DEST[MAXVL-1:128] := 0

VPSRLD (xmm, imm8) - VEX.128 encoding

DEST[127:0] := LOGICAL_RIGHT_SHIFT_DWORDS(SRC1, imm8)

DEST[MAXVL-1:128] := 0

PSRLD (xmm, xmm, xmm/m128)

DEST[127:0] := LOGICAL_RIGHT_SHIFT_DWORDS(DEST, SRC)

DEST[MAXVL-1:128] (Unmodified)

PSRLD (xmm, imm8)

DEST[127:0] := LOGICAL_RIGHT_SHIFT_DWORDS(DEST, imm8)

DEST[MAXVL-1:128] (Unmodified)

VPSRLQ (EVEX versions, xmm/m128)

(KL, VL) = (2, 128), (4, 256), (8, 512)

TMP_DEST[255:0] := LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1[255:0], SRC2)

TMP_DEST[511:256] := LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1[511:256], SRC2)

IF VL = 128

TMP_DEST[127:0] := LOGICAL_RIGHT_SHIFT_QWORDS_128b(SRC1[127:0], SRC2)

FI;

IF VL = 256

TMP_DEST[255:0] := LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1[255:0], SRC2)

FI;

IF VL = 512

TMP_DEST[255:0] := LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1[255:0], SRC2)

TMP_DEST[511:256] := LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1[511:256], SRC2)

FI;

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i] := TMP_DEST[i+63:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

PSRLW/PSRLD/PSRLQ—Shift Packed Data Right Logical

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INSTRUCTION SET REFERENCE, M-U

VPSRLQ (EVEX versions, imm8)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) AND (SRC1 *is memory*)

THEN DEST[i+63:i] := LOGICAL_RIGHT_SHIFT_QWORDS1(SRC1[63:0], imm8)

ELSE DEST[i+63:i] := LOGICAL_RIGHT_SHIFT_QWORDS1(SRC1[i+63:i], imm8)

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VPSRLQ (ymm, ymm, xmm/m128) - VEX.256 encoding

DEST[255:0] := LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1, SRC2)

DEST[MAXVL-1:256] := 0;

VPSRLQ (ymm, imm8) - VEX.256 encoding

DEST[255:0] := LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1, imm8)

DEST[MAXVL-1:256] := 0;

VPSRLQ (xmm, xmm, xmm/m128) - VEX.128 encoding

DEST[127:0] := LOGICAL_RIGHT_SHIFT_QWORDS(SRC1, SRC2)

DEST[MAXVL-1:128] := 0

VPSRLQ (xmm, imm8) - VEX.128 encoding

DEST[127:0] := LOGICAL_RIGHT_SHIFT_QWORDS(SRC1, imm8)

DEST[MAXVL-1:128] := 0

PSRLQ (xmm, xmm, xmm/m128)

DEST[127:0] := LOGICAL_RIGHT_SHIFT_QWORDS(DEST, SRC)

DEST[MAXVL-1:128] (Unmodified)

PSRLQ (xmm, imm8)

DEST[127:0] := LOGICAL_RIGHT_SHIFT_QWORDS(DEST, imm8)

DEST[MAXVL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalents

VPSRLD __m512i _mm512_srli_epi32(__m512i a, unsigned int imm);

VPSRLD __m512i _mm512_mask_srli_epi32(__m512i s, __mmask16 k, __m512i a, unsigned int imm);

VPSRLD __m512i _mm512_maskz_srli_epi32( __mmask16 k, __m512i a, unsigned int imm);

VPSRLD __m256i _mm256_mask_srli_epi32(__m256i s, __mmask8 k, __m256i a, unsigned int imm);

VPSRLD __m256i _mm256_maskz_srli_epi32( __mmask8 k, __m256i a, unsigned int imm);

VPSRLD __m128i _mm_mask_srli_epi32(__m128i s, __mmask8 k, __m128i a, unsigned int imm);

VPSRLD __m128i _mm_maskz_srli_epi32( __mmask8 k, __m128i a, unsigned int imm);

VPSRLD __m512i _mm512_srl_epi32(__m512i a, __m128i cnt);

VPSRLD __m512i _mm512_mask_srl_epi32(__m512i s, __mmask16 k, __m512i a, __m128i cnt);

VPSRLD __m512i _mm512_maskz_srl_epi32( __mmask16 k, __m512i a, __m128i cnt);

VPSRLD __m256i _mm256_mask_srl_epi32(__m256i s, __mmask8 k, __m256i a, __m128i cnt);

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INSTRUCTION SET REFERENCE, M-U

VPSRLD __m256i _mm256_maskz_srl_epi32( __mmask8 k, __m256i a, __m128i cnt);

VPSRLD __m128i _mm_mask_srl_epi32(__m128i s, __mmask8 k, __m128i a, __m128i cnt);

VPSRLD __m128i _mm_maskz_srl_epi32( __mmask8 k, __m128i a, __m128i cnt);

VPSRLQ __m512i _mm512_srli_epi64(__m512i a, unsigned int imm);

VPSRLQ __m512i _mm512_mask_srli_epi64(__m512i s, __mmask8 k, __m512i a, unsigned int imm);

VPSRLQ __m512i _mm512_mask_srli_epi64( __mmask8 k, __m512i a, unsigned int imm);

VPSRLQ __m256i _mm256_mask_srli_epi64(__m256i s, __mmask8 k, __m256i a, unsigned int imm);

VPSRLQ __m256i _mm256_maskz_srli_epi64( __mmask8 k, __m256i a, unsigned int imm);

VPSRLQ __m128i _mm_mask_srli_epi64(__m128i s, __mmask8 k, __m128i a, unsigned int imm);

VPSRLQ __m128i _mm_maskz_srli_epi64( __mmask8 k, __m128i a, unsigned int imm);

VPSRLQ __m512i _mm512_srl_epi64(__m512i a, __m128i cnt);

VPSRLQ __m512i _mm512_mask_srl_epi64(__m512i s, __mmask8 k, __m512i a, __m128i cnt);

VPSRLQ __m512i _mm512_mask_srl_epi64( __mmask8 k, __m512i a, __m128i cnt);

VPSRLQ __m256i _mm256_mask_srl_epi64(__m256i s, __mmask8 k, __m256i a, __m128i cnt);

VPSRLQ __m256i _mm256_maskz_srl_epi64( __mmask8 k, __m256i a, __m128i cnt);

VPSRLQ __m128i _mm_mask_srl_epi64(__m128i s, __mmask8 k, __m128i a, __m128i cnt);

VPSRLQ __m128i _mm_maskz_srl_epi64( __mmask8 k, __m128i a, __m128i cnt);

VPSRLW __m512i _mm512_srli_epi16(__m512i a, unsigned int imm);

VPSRLW __m512i _mm512_mask_srli_epi16(__m512i s, __mmask32 k, __m512i a, unsigned int imm);

VPSRLW __m512i _mm512_maskz_srli_epi16( __mmask32 k, __m512i a, unsigned int imm);

VPSRLW __m256i _mm256_mask_srli_epi16(__m256i s, __mmask16 k, __m256i a, unsigned int imm);

VPSRLW __m256i _mm256_maskz_srli_epi16( __mmask16 k, __m256i a, unsigned int imm);

VPSRLW __m128i _mm_mask_srli_epi16(__m128i s, __mmask8 k, __m128i a, unsigned int imm);

VPSRLW __m128i _mm_maskz_srli_epi16( __mmask8 k, __m128i a, unsigned int imm);

VPSRLW __m512i _mm512_srl_epi16(__m512i a, __m128i cnt);

VPSRLW __m512i _mm512_mask_srl_epi16(__m512i s, __mmask32 k, __m512i a, __m128i cnt);

VPSRLW __m512i _mm512_maskz_srl_epi16( __mmask32 k, __m512i a, __m128i cnt);

VPSRLW __m256i _mm256_mask_srl_epi16(__m256i s, __mmask16 k, __m256i a, __m128i cnt);

VPSRLW __m256i _mm256_maskz_srl_epi16( __mmask8 k, __mmask16 a, __m128i cnt);

VPSRLW __m128i _mm_mask_srl_epi16(__m128i s, __mmask8 k, __m128i a, __m128i cnt);

VPSRLW __m128i _mm_maskz_srl_epi16( __mmask8 k, __m128i a, __m128i cnt);

PSRLW:__m64 _mm_srli_pi16(__m64 m, int count)

PSRLW:__m64 _mm_srl_pi16 (__m64 m, __m64 count)

(V)PSRLW:__m128i _mm_srli_epi16 (__m128i m, int count)

(V)PSRLW:__m128i _mm_srl_epi16 (__m128i m, __m128i count)

VPSRLW:__m256i _mm256_srli_epi16 (__m256i m, int count)

VPSRLW:__m256i _mm256_srl_epi16 (__m256i m, __m128i count)

PSRLD:__m64 _mm_srli_pi32 (__m64 m, int count)

PSRLD:__m64 _mm_srl_pi32 (__m64 m, __m64 count)

(V)PSRLD:__m128i _mm_srli_epi32 (__m128i m, int count)

(V)PSRLD:__m128i _mm_srl_epi32 (__m128i m, __m128i count)

VPSRLD:__m256i _mm256_srli_epi32 (__m256i m, int count)

VPSRLD:__m256i _mm256_srl_epi32 (__m256i m, __m128i count)

PSRLQ:__m64 _mm_srli_si64 (__m64 m, int count)

PSRLQ:__m64 _mm_srl_si64 (__m64 m, __m64 count)

(V)PSRLQ:__m128i _mm_srli_epi64 (__m128i m, int count)

(V)PSRLQ:__m128i _mm_srl_epi64 (__m128i m, __m128i count)

VPSRLQ:__m256i _mm256_srli_epi64 (__m256i m, int count)

VPSRLQ:__m256i _mm256_srl_epi64 (__m256i m, __m128i count)

Flags Affected

None.

PSRLW/PSRLD/PSRLQ—Shift Packed Data Right Logical

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INSTRUCTION SET REFERENCE, M-U

Numeric Exceptions

None.

Other Exceptions

VEX-encoded instructions:

Syntax with RM/RVM operand encoding (A/C in the operand encoding table), see Table 2-21, “Type 4 Class Excep-

tion Conditions”.

Syntax with MI/VMI operand encoding (B/D in the operand encoding table), see Table 2-24, “Type 7 Class Excep-

tion Conditions”.

EVEX-encoded VPSRLW (E in the operand encoding table), see Exceptions Type E4NF.nb in Table 2-50, “Type E4NF

Class Exception Conditions”.

EVEX-encoded VPSRLD/Q:

Syntax with Mem128 tuple type (G in the operand encoding table), see Exceptions Type E4NF.nb in Table 2-50,

“Type E4NF Class Exception Conditions”.

Syntax with Full tuple type (F in the operand encoding table), see Table 2-49, “Type E4 Class Exception Conditions”.

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INSTRUCTION SET REFERENCE, M-U

PSUBB/PSUBW/PSUBD—Subtract Packed Integers

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

NP 0F F8 /r¹

V/V

MMX

Subtract packed byte integers in mm/m64

from packed byte integers in mm.

PSUBB mm, mm/m64

66 0F F8 /r

V/V

SSE2

Subtract packed byte integers in xmm2/m128

from packed byte integers in xmm1.

PSUBB xmm1, xmm2/m128

NP 0F F9 /r¹

V/V

MMX

Subtract packed word integers in mm/m64

from packed word integers in mm.

PSUBW mm, mm/m64

66 0F F9 /r

V/V

SSE2

Subtract packed word integers in

xmm2/m128 from packed word integers in

PSUBW xmm1, xmm2/m128

xmm1.

NP 0F FA /r¹

V/V

MMX

Subtract packed doubleword integers in

mm/m64 from packed doubleword integers in

PSUBD mm, mm/m64

mm.

66 0F FA /r

V/V

SSE2

Subtract packed doubleword integers in

xmm2/mem128 from packed doubleword

PSUBD xmm1, xmm2/m128

integers in xmm1.

VEX.128.66.0F.WIG F8 /r

V/V

AVX

Subtract packed byte integers in xmm3/m128

VPSUBB xmm1, xmm2, xmm3/m128

from xmm2.

VEX.128.66.0F.WIG F9 /r

V/V

AVX

Subtract packed word integers in

xmm3/m128 from xmm2.

VPSUBW xmm1, xmm2, xmm3/m128

VEX.128.66.0F.WIG FA /r

V/V

AVX

Subtract packed doubleword integers in

VPSUBD xmm1, xmm2, xmm3/m128

xmm3/m128 from xmm2.

VEX.256.66.0F.WIG F8 /r

V/V

AVX2

Subtract packed byte integers in ymm3/m256

VPSUBB ymm1, ymm2, ymm3/m256

from ymm2.

VEX.256.66.0F.WIG F9 /r

V/V

AVX2

Subtract packed word integers in

VPSUBW ymm1, ymm2, ymm3/m256

ymm3/m256 from ymm2.

VEX.256.66.0F.WIG FA /r

V/V

AVX2

Subtract packed doubleword integers in

VPSUBD ymm1, ymm2, ymm3/m256

ymm3/m256 from ymm2.

EVEX.128.66.0F.WIG F8 /r

V/V

AVX512VL

Subtract packed byte integers in xmm3/m128

VPSUBB xmm1 {k1}{z}, xmm2, xmm3/m128

AVX512BW

from xmm2 and store in xmm1 using

writemask k1.

EVEX.256.66.0F.WIG F8 /r

V/V

AVX512VL

Subtract packed byte integers in ymm3/m256

VPSUBB ymm1 {k1}{z}, ymm2, ymm3/m256

AVX512BW

from ymm2 and store in ymm1 using

writemask k1.

EVEX.512.66.0F.WIG F8 /r

V/V

AVX512BW

Subtract packed byte integers in zmm3/m512

VPSUBB zmm1 {k1}{z}, zmm2, zmm3/m512

from zmm2 and store in zmm1 using

writemask k1.

EVEX.128.66.0F.WIG F9 /r

V/V

AVX512VL

Subtract packed word integers in

VPSUBW xmm1 {k1}{z}, xmm2, xmm3/m128

AVX512BW

xmm3/m128 from xmm2 and store in xmm1

using writemask k1.

EVEX.256.66.0F.WIG F9 /r

V/V

AVX512VL

Subtract packed word integers in

VPSUBW ymm1 {k1}{z}, ymm2, ymm3/m256

AVX512BW

ymm3/m256 from ymm2 and store in ymm1

using writemask k1.

EVEX.512.66.0F.WIG F9 /r

V/V

AVX512BW

Subtract packed word integers in

VPSUBW zmm1 {k1}{z}, zmm2, zmm3/m512

zmm3/m512 from zmm2 and store in zmm1

using writemask k1.

PSUBB/PSUBW/PSUBD—Subtract Packed Integers

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INSTRUCTION SET REFERENCE, M-U

EVEX.128.66.0F.W0 FA /r

V/V

AVX512VL

Subtract packed doubleword integers in

VPSUBD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst

AVX512F

xmm3/m128/m32bcst from xmm2 and store

in xmm1 using writemask k1.

EVEX.256.66.0F.W0 FA /r

V/V

AVX512VL

Subtract packed doubleword integers in

VPSUBD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst

AVX512F

ymm3/m256/m32bcst from ymm2 and store

in ymm1 using writemask k1.

EVEX.512.66.0F.W0 FA /r

V/V

AVX512F

Subtract packed doubleword integers in

VPSUBD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst

zmm3/m512/m32bcst from zmm2 and store

in zmm1 using writemask k1

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2A and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Reg-

isters” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full Mem

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs a SIMD subtract of the packed integers of the source operand (second operand) from the packed integers

of the destination operand (first operand), and stores the packed integer results in the destination operand. See

Figure 9-4 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an illustration of a

SIMD operation. Overflow is handled with wraparound, as described in the following paragraphs.

The (V)PSUBB instruction subtracts packed byte integers. When an individual result is too large or too small to be

represented in a byte, the result is wrapped around and the low 8 bits are written to the destination element.

The (V)PSUBW instruction subtracts packed word integers. When an individual result is too large or too small to be

represented in a word, the result is wrapped around and the low 16 bits are written to the destination element.

The (V)PSUBD instruction subtracts packed doubleword integers. When an individual result is too large or too small

to be represented in a doubleword, the result is wrapped around and the low 32 bits are written to the destination

element.

Note that the (V)PSUBB, (V)PSUBW, and (V)PSUBD instructions can operate on either unsigned or signed (two's

complement notation) packed integers; however, it does not set bits in the EFLAGS register to indicate overflow

and/or a carry. To prevent undetected overflow conditions, software must control the ranges of values upon which

it operates.

In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to

access additional registers (XMM8-XMM15).

Legacy SSE version 64-bit operand: The destination operand must be an MMX technology register and the source

operand can be either an MMX technology register or a 64-bit memory location.

128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first

source operand and destination operands are XMM registers. Bits (MAXVL-1:128) of the corresponding YMM desti-

nation register remain unchanged.

VEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first

source operand and destination operands are XMM registers. Bits (MAXVL-1:128) of the destination YMM register

are zeroed.

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PSUBB/PSUBW/PSUBD—Subtract Packed Integers

INSTRUCTION SET REFERENCE, M-U

VEX.256 encoded versions: The second source operand is an YMM register or an 256-bit memory location. The first

source operand and destination operands are YMM registers. Bits (MAXVL-1:256) of the corresponding ZMM

EVEX encoded VPSUBD: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-

tion or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The first source operand and

destination operands are ZMM/YMM/XMM registers. The destination is conditionally updated with writemask k1.

EVEX encoded VPSUBB/W: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory

location. The first source operand and destination operands are ZMM/YMM/XMM registers. The destination is condi-

tionally updated with writemask k1.

Operation

PSUBB (with 64-bit operands)

DEST[7:0] := DEST[7:0] − SRC[7:0];

(* Repeat subtract operation for 2nd through 7th byte *)

DEST[63:56] := DEST[63:56] − SRC[63:56];

PSUBW (with 64-bit operands)

DEST[15:0] := DEST[15:0] − SRC[15:0];

(* Repeat subtract operation for 2nd and 3rd word *)

DEST[63:48] := DEST[63:48] − SRC[63:48];

PSUBD (with 64-bit operands)

DEST[31:0] := DEST[31:0] − SRC[31:0];

DEST[63:32] := DEST[63:32] − SRC[63:32];

PSUBD (with 128-bit operands)

DEST[31:0] := DEST[31:0] − SRC[31:0];

(* Repeat subtract operation for 2nd and 3rd doubleword *)

DEST[127:96] := DEST[127:96] − SRC[127:96];

VPSUBB (EVEX encoded versions)

(KL, VL) = (16, 128), (32, 256), (64, 512)

FOR j := 0 TO KL-1

i := j * 8

IF k1[j] OR *no writemask*

THEN DEST[i+7:i] := SRC1[i+7:i] - SRC2[i+7:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+7:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+7:i] = 0

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

VPSUBW (EVEX encoded versions)

(KL, VL) = (8, 128), (16, 256), (32, 512)

FOR j := 0 TO KL-1

i := j * 16

IF k1[j] OR *no writemask*

THEN DEST[i+15:i] := SRC1[i+15:i] - SRC2[i+15:i]

ELSE

IF *merging-masking*

; merging-masking

PSUBB/PSUBW/PSUBD—Subtract Packed Integers

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INSTRUCTION SET REFERENCE, M-U

THEN *DEST[i+15:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+15:i] = 0

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

VPSUBD (EVEX encoded versions)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) AND (SRC2 *is memory*)

THEN DEST[i+31:i] := SRC1[i+31:i] - SRC2[31:0]

ELSE DEST[i+31:i] := SRC1[i+31:i] - SRC2[i+31:i]

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

VPSUBB (VEX.256 encoded version)

DEST[7:0] := SRC1[7:0]-SRC2[7:0]

DEST[15:8] := SRC1[15:8]-SRC2[15:8]

DEST[23:16] := SRC1[23:16]-SRC2[23:16]

DEST[31:24] := SRC1[31:24]-SRC2[31:24]

DEST[39:32] := SRC1[39:32]-SRC2[39:32]

DEST[47:40] := SRC1[47:40]-SRC2[47:40]

DEST[55:48] := SRC1[55:48]-SRC2[55:48]

DEST[63:56] := SRC1[63:56]-SRC2[63:56]

DEST[71:64] := SRC1[71:64]-SRC2[71:64]

DEST[79:72] := SRC1[79:72]-SRC2[79:72]

DEST[87:80] := SRC1[87:80]-SRC2[87:80]

DEST[95:88] := SRC1[95:88]-SRC2[95:88]

DEST[103:96] := SRC1[103:96]-SRC2[103:96]

DEST[111:104] := SRC1[111:104]-SRC2[111:104]

DEST[119:112] := SRC1[119:112]-SRC2[119:112]

DEST[127:120] := SRC1[127:120]-SRC2[127:120]

DEST[135:128] := SRC1[135:128]-SRC2[135:128]

DEST[143:136] := SRC1[143:136]-SRC2[143:136]

DEST[151:144] := SRC1[151:144]-SRC2[151:144]

DEST[159:152] := SRC1[159:152]-SRC2[159:152]

DEST[167:160] := SRC1[167:160]-SRC2[167:160]

DEST[175:168] := SRC1[175:168]-SRC2[175:168]

DEST[183:176] := SRC1[183:176]-SRC2[183:176]

DEST[191:184] := SRC1[191:184]-SRC2[191:184]

DEST[199:192] := SRC1[199:192]-SRC2[199:192]

DEST[207:200] := SRC1[207:200]-SRC2[207:200]

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INSTRUCTION SET REFERENCE, M-U

DEST[215:208] := SRC1[215:208]-SRC2[215:208]

DEST[223:216] := SRC1[223:216]-SRC2[223:216]

DEST[231:224] := SRC1[231:224]-SRC2[231:224]

DEST[239:232] := SRC1[239:232]-SRC2[239:232]

DEST[247:240] := SRC1[247:240]-SRC2[247:240]

DEST[255:248] := SRC1[255:248]-SRC2[255:248]

DEST[MAXVL-1:256] := 0

VPSUBB (VEX.128 encoded version)

DEST[7:0] := SRC1[7:0]-SRC2[7:0]

DEST[15:8] := SRC1[15:8]-SRC2[15:8]

DEST[23:16] := SRC1[23:16]-SRC2[23:16]

DEST[31:24] := SRC1[31:24]-SRC2[31:24]

DEST[39:32] := SRC1[39:32]-SRC2[39:32]

DEST[47:40] := SRC1[47:40]-SRC2[47:40]

DEST[55:48] := SRC1[55:48]-SRC2[55:48]

DEST[63:56] := SRC1[63:56]-SRC2[63:56]

DEST[71:64] := SRC1[71:64]-SRC2[71:64]

DEST[79:72] := SRC1[79:72]-SRC2[79:72]

DEST[87:80] := SRC1[87:80]-SRC2[87:80]

DEST[95:88] := SRC1[95:88]-SRC2[95:88]

DEST[103:96] := SRC1[103:96]-SRC2[103:96]

DEST[111:104] := SRC1[111:104]-SRC2[111:104]

DEST[119:112] := SRC1[119:112]-SRC2[119:112]

DEST[127:120] := SRC1[127:120]-SRC2[127:120]

DEST[MAXVL-1:128] := 0

PSUBB (128-bit Legacy SSE version)

DEST[7:0] := DEST[7:0]-SRC[7:0]

DEST[15:8] := DEST[15:8]-SRC[15:8]

DEST[23:16] := DEST[23:16]-SRC[23:16]

DEST[31:24] := DEST[31:24]-SRC[31:24]

DEST[39:32] := DEST[39:32]-SRC[39:32]

DEST[47:40] := DEST[47:40]-SRC[47:40]

DEST[55:48] := DEST[55:48]-SRC[55:48]

DEST[63:56] := DEST[63:56]-SRC[63:56]

DEST[71:64] := DEST[71:64]-SRC[71:64]

DEST[79:72] := DEST[79:72]-SRC[79:72]

DEST[87:80] := DEST[87:80]-SRC[87:80]

DEST[95:88] := DEST[95:88]-SRC[95:88]

DEST[103:96] := DEST[103:96]-SRC[103:96]

DEST[111:104] := DEST[111:104]-SRC[111:104]

DEST[119:112] := DEST[119:112]-SRC[119:112]

DEST[127:120] := DEST[127:120]-SRC[127:120]

DEST[MAXVL-1:128] (Unmodified)

VPSUBW (VEX.256 encoded version)

DEST[15:0] := SRC1[15:0]-SRC2[15:0]

DEST[31:16] := SRC1[31:16]-SRC2[31:16]

DEST[47:32] := SRC1[47:32]-SRC2[47:32]

DEST[63:48] := SRC1[63:48]-SRC2[63:48]

DEST[79:64] := SRC1[79:64]-SRC2[79:64]

DEST[95:80] := SRC1[95:80]-SRC2[95:80]

DEST[111:96] := SRC1[111:96]-SRC2[111:96]

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INSTRUCTION SET REFERENCE, M-U

DEST[127:112] := SRC1[127:112]-SRC2[127:112]

DEST[143:128] := SRC1[143:128]-SRC2[143:128]

DEST[159:144] := SRC1[159:144]-SRC2[159:144]

DEST[175:160] := SRC1[175:160]-SRC2[175:160]

DEST[191:176] := SRC1[191:176]-SRC2[191:176]

DEST[207:192] := SRC1207:192]-SRC2[207:192]

DEST[223:208] := SRC1[223:208]-SRC2[223:208]

DEST[239:224] := SRC1[239:224]-SRC2[239:224]

DEST[255:240] := SRC1[255:240]-SRC2[255:240]

DEST[MAXVL-1:256] := 0

VPSUBW (VEX.128 encoded version)

DEST[15:0] := SRC1[15:0]-SRC2[15:0]

DEST[31:16] := SRC1[31:16]-SRC2[31:16]

DEST[47:32] := SRC1[47:32]-SRC2[47:32]

DEST[63:48] := SRC1[63:48]-SRC2[63:48]

DEST[79:64] := SRC1[79:64]-SRC2[79:64]

DEST[95:80] := SRC1[95:80]-SRC2[95:80]

DEST[111:96] := SRC1[111:96]-SRC2[111:96]

DEST[127:112] := SRC1[127:112]-SRC2[127:112]

DEST[MAXVL-1:128] := 0

PSUBW (128-bit Legacy SSE version)

DEST[15:0] := DEST[15:0]-SRC[15:0]

DEST[31:16] := DEST[31:16]-SRC[31:16]

DEST[47:32] := DEST[47:32]-SRC[47:32]

DEST[63:48] := DEST[63:48]-SRC[63:48]

DEST[79:64] := DEST[79:64]-SRC[79:64]

DEST[95:80] := DEST[95:80]-SRC[95:80]

DEST[111:96] := DEST[111:96]-SRC[111:96]

DEST[127:112] := DEST[127:112]-SRC[127:112]

DEST[MAXVL-1:128] (Unmodified)

VPSUBD (VEX.256 encoded version)

DEST[31:0] := SRC1[31:0]-SRC2[31:0]

DEST[63:32] := SRC1[63:32]-SRC2[63:32]

DEST[95:64] := SRC1[95:64]-SRC2[95:64]

DEST[127:96] := SRC1[127:96]-SRC2[127:96]

DEST[159:128] := SRC1[159:128]-SRC2[159:128]

DEST[191:160] := SRC1[191:160]-SRC2[191:160]

DEST[223:192] := SRC1[223:192]-SRC2[223:192]

DEST[255:224] := SRC1[255:224]-SRC2[255:224]

DEST[MAXVL-1:256] := 0

VPSUBD (VEX.128 encoded version)

DEST[31:0] := SRC1[31:0]-SRC2[31:0]

DEST[63:32] := SRC1[63:32]-SRC2[63:32]

DEST[95:64] := SRC1[95:64]-SRC2[95:64]

DEST[127:96] := SRC1[127:96]-SRC2[127:96]

DEST[MAXVL-1:128] := 0

PSUBD (128-bit Legacy SSE version)

DEST[31:0] := DEST[31:0]-SRC[31:0]

DEST[63:32] := DEST[63:32]-SRC[63:32]

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INSTRUCTION SET REFERENCE, M-U

DEST[95:64] := DEST[95:64]-SRC[95:64]

DEST[127:96] := DEST[127:96]-SRC[127:96]

DEST[MAXVL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalents

VPSUBB __m512i _mm512_sub_epi8(__m512i a, __m512i b);

VPSUBB __m512i _mm512_mask_sub_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);

VPSUBB __m512i _mm512_maskz_sub_epi8( __mmask64 k, __m512i a, __m512i b);

VPSUBB __m256i _mm256_mask_sub_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);

VPSUBB __m256i _mm256_maskz_sub_epi8( __mmask32 k, __m256i a, __m256i b);

VPSUBB __m128i _mm_mask_sub_epi8(__m128i s, __mmask16 k, __m128i a, __m128i b);

VPSUBB __m128i _mm_maskz_sub_epi8( __mmask16 k, __m128i a, __m128i b);

VPSUBW __m512i _mm512_sub_epi16(__m512i a, __m512i b);

VPSUBW __m512i _mm512_mask_sub_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);

VPSUBW __m512i _mm512_maskz_sub_epi16( __mmask32 k, __m512i a, __m512i b);

VPSUBW __m256i _mm256_mask_sub_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);

VPSUBW __m256i _mm256_maskz_sub_epi16( __mmask16 k, __m256i a, __m256i b);

VPSUBW __m128i _mm_mask_sub_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);

VPSUBW __m128i _mm_maskz_sub_epi16( __mmask8 k, __m128i a, __m128i b);

VPSUBD __m512i _mm512_sub_epi32(__m512i a, __m512i b);

VPSUBD __m512i _mm512_mask_sub_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);

VPSUBD __m512i _mm512_maskz_sub_epi32( __mmask16 k, __m512i a, __m512i b);

VPSUBD __m256i _mm256_mask_sub_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);

VPSUBD __m256i _mm256_maskz_sub_epi32( __mmask8 k, __m256i a, __m256i b);

VPSUBD __m128i _mm_mask_sub_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);

VPSUBD __m128i _mm_maskz_sub_epi32( __mmask8 k, __m128i a, __m128i b);

PSUBB:__m64 _mm_sub_pi8(__m64 m1, __m64 m2)

(V)PSUBB:__m128i _mm_sub_epi8 ( __m128i a, __m128i b)

VPSUBB:__m256i _mm256_sub_epi8 ( __m256i a, __m256i b)

PSUBW:__m64 _mm_sub_pi16(__m64 m1, __m64 m2)

(V)PSUBW:__m128i _mm_sub_epi16 ( __m128i a, __m128i b)

VPSUBW:__m256i _mm256_sub_epi16 ( __m256i a, __m256i b)

PSUBD:__m64 _mm_sub_pi32(__m64 m1, __m64 m2)

(V)PSUBD:__m128i _mm_sub_epi32 ( __m128i a, __m128i b)

VPSUBD:__m256i _mm256_sub_epi32 ( __m256i a, __m256i b)

Flags Affected

None.

Numeric Exceptions

None.

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions”.

EVEX-encoded VPSUBD, see Table 2-49, “Type E4 Class Exception Conditions”.

EVEX-encoded VPSUBB/W, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions”.

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INSTRUCTION SET REFERENCE, M-U

PSUBQ—Subtract Packed Quadword Integers

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

NP 0F FB /r¹

V/V

SSE2

Subtract quadword integer in mm1 from mm2

/m64.

PSUBQ mm1, mm2/m64

66 0F FB /r

V/V

SSE2

Subtract packed quadword integers in xmm1

from xmm2 /m128.

PSUBQ xmm1, xmm2/m128

VEX.128.66.0F.WIG FB/r

V/V

AVX

Subtract packed quadword integers in

xmm3/m128 from xmm2.

VPSUBQ xmm1, xmm2, xmm3/m128

VEX.256.66.0F.WIG FB /r

V/V

AVX2

Subtract packed quadword integers in

ymm3/m256 from ymm2.

VPSUBQ ymm1, ymm2, ymm3/m256

EVEX.128.66.0F.W1 FB /r

V/V

AVX512VL

Subtract packed quadword integers in

VPSUBQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst

AVX512F

xmm3/m128/m64bcst from xmm2 and store

in xmm1 using writemask k1.

EVEX.256.66.0F.W1 FB /r

V/V

AVX512VL

Subtract packed quadword integers in

VPSUBQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst

AVX512F

ymm3/m256/m64bcst from ymm2 and store

in ymm1 using writemask k1.

EVEX.512.66.0F.W1 FB/r

V/V

AVX512F

Subtract packed quadword integers in

VPSUBQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst

zmm3/m512/m64bcst from zmm2 and store

in zmm1 using writemask k1.

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2A and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Reg-

isters” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Subtracts the second operand (source operand) from the first operand (destination operand) and stores the result

in the destination operand. When packed quadword operands are used, a SIMD subtract is performed. When a

quadword result is too large to be represented in 64 bits (overflow), the result is wrapped around and the low 64

bits are written to the destination element (that is, the carry is ignored).

Note that the (V)PSUBQ instruction can operate on either unsigned or signed (two’s complement notation) inte-

gers; however, it does not set bits in the EFLAGS register to indicate overflow and/or a carry. To prevent undetected

overflow conditions, software must control the ranges of the values upon which it operates.

In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to

access additional registers (XMM8-XMM15).

Legacy SSE version 64-bit operand: The source operand can be a quadword integer stored in an MMX technology

128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first

source operand and destination operands are XMM registers. Bits (MAXVL-1:128) of the corresponding YMM desti-

nation register remain unchanged.

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INSTRUCTION SET REFERENCE, M-U

VEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first

source operand and destination operands are XMM registers. Bits (MAXVL-1:128) of the destination YMM register

are zeroed.

VEX.256 encoded versions: The second source operand is an YMM register or an 256-bit memory location. The first

source operand and destination operands are YMM registers. Bits (MAXVL-1:256) of the corresponding ZMM

EVEX encoded VPSUBQ: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-

tion or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The first source operand and

destination operands are ZMM/YMM/XMM registers. The destination is conditionally updated with writemask k1.

Operation

PSUBQ (with 64-Bit operands)

DEST[63:0] := DEST[63:0] − SRC[63:0];

PSUBQ (with 128-Bit operands)

DEST[63:0] := DEST[63:0] − SRC[63:0];

DEST[127:64] := DEST[127:64] − SRC[127:64];

VPSUBQ (VEX.128 encoded version)

DEST[63:0] := SRC1[63:0]-SRC2[63:0]

DEST[127:64] := SRC1[127:64]-SRC2[127:64]

DEST[MAXVL-1:128] := 0

VPSUBQ (VEX.256 encoded version)

DEST[63:0] := SRC1[63:0]-SRC2[63:0]

DEST[127:64] := SRC1[127:64]-SRC2[127:64]

DEST[191:128] := SRC1[191:128]-SRC2[191:128]

DEST[255:192] := SRC1[255:192]-SRC2[255:192]

DEST[MAXVL-1:256] := 0

VPSUBQ (EVEX encoded versions)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) AND (SRC2 *is memory*)

THEN DEST[i+63:i] := SRC1[i+63:i] - SRC2[63:0]

ELSE DEST[i+63:i] := SRC1[i+63:i] - SRC2[i+63:i]

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

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INSTRUCTION SET REFERENCE, M-U

Intel C/C++ Compiler Intrinsic Equivalents

VPSUBQ __m512i _mm512_sub_epi64(__m512i a, __m512i b);

VPSUBQ __m512i _mm512_mask_sub_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);

VPSUBQ __m512i _mm512_maskz_sub_epi64( __mmask8 k, __m512i a, __m512i b);

VPSUBQ __m256i _mm256_mask_sub_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);

VPSUBQ __m256i _mm256_maskz_sub_epi64( __mmask8 k, __m256i a, __m256i b);

VPSUBQ __m128i _mm_mask_sub_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);

VPSUBQ __m128i _mm_maskz_sub_epi64( __mmask8 k, __m128i a, __m128i b);

PSUBQ:__m64 _mm_sub_si64(__m64 m1, __m64 m2)

(V)PSUBQ:__m128i _mm_sub_epi64(__m128i m1, __m128i m2)

VPSUBQ:__m256i _mm256_sub_epi64(__m256i m1, __m256i m2)

Flags Affected

None.

Numeric Exceptions

None.

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions”.

EVEX-encoded VPSUBQ, see Table 2-49, “Type E4 Class Exception Conditions”.

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INSTRUCTION SET REFERENCE, M-U

PSUBSB/PSUBSW—Subtract Packed Signed Integers With Signed Saturation

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

NP 0F E8 /r¹

V/V

MMX

Subtract signed packed bytes in mm/m64 from

signed packed bytes in mm and saturate results.

PSUBSB mm, mm/m64

66 0F E8 /r

V/V

SSE2

Subtract packed signed byte integers in

xmm2/m128 from packed signed byte integers

PSUBSB xmm1, xmm2/m128

in xmm1 and saturate results.

NP 0F E9 /r¹

V/V

MMX

Subtract signed packed words in mm/m64 from

signed packed words in mm and saturate

PSUBSW mm, mm/m64

results.

66 0F E9 /r

V/V

SSE2

Subtract packed signed word integers in

xmm2/m128 from packed signed word integers

PSUBSW xmm1, xmm2/m128

in xmm1 and saturate results.

VEX.128.66.0F.WIG E8 /r

V/V

AVX

Subtract packed signed byte integers in

xmm3/m128 from packed signed byte integers

VPSUBSB xmm1, xmm2, xmm3/m128

in xmm2 and saturate results.

VEX.128.66.0F.WIG E9 /r

V/V

AVX

Subtract packed signed word integers in

xmm3/m128 from packed signed word integers

VPSUBSW xmm1, xmm2, xmm3/m128

in xmm2 and saturate results.

VEX.256.66.0F.WIG E8 /r

V/V

AVX2

Subtract packed signed byte integers in

ymm3/m256 from packed signed byte integers

VPSUBSB ymm1, ymm2, ymm3/m256

in ymm2 and saturate results.

VEX.256.66.0F.WIG E9 /r

V/V

AVX2

Subtract packed signed word integers in

ymm3/m256 from packed signed word integers

VPSUBSW ymm1, ymm2, ymm3/m256

in ymm2 and saturate results.

EVEX.128.66.0F.WIG E8 /r

V/V

AVX512VL

Subtract packed signed byte integers in

VPSUBSB xmm1 {k1}{z}, xmm2, xmm3/m128

AVX512BW

xmm3/m128 from packed signed byte integers

in xmm2 and saturate results and store in

xmm1 using writemask k1.

EVEX.256.66.0F.WIG E8 /r

V/V

AVX512VL

Subtract packed signed byte integers in

VPSUBSB ymm1 {k1}{z}, ymm2, ymm3/m256

AVX512BW

ymm3/m256 from packed signed byte integers

in ymm2 and saturate results and store in

ymm1 using writemask k1.

EVEX.512.66.0F.WIG E8 /r

V/V

AVX512BW

Subtract packed signed byte integers in

VPSUBSB zmm1 {k1}{z}, zmm2, zmm3/m512

zmm3/m512 from packed signed byte integers

in zmm2 and saturate results and store in zmm1

using writemask k1.

EVEX.128.66.0F.WIG E9 /r

V/V

AVX512VL

Subtract packed signed word integers in

VPSUBSW xmm1 {k1}{z}, xmm2, xmm3/m128

AVX512BW

xmm3/m128 from packed signed word integers

in xmm2 and saturate results and store in

xmm1 using writemask k1.

EVEX.256.66.0F.WIG E9 /r

V/V

AVX512VL

Subtract packed signed word integers in

VPSUBSW ymm1 {k1}{z}, ymm2, ymm3/m256

AVX512BW

ymm3/m256 from packed signed word integers

in ymm2 and saturate results and store in

ymm1 using writemask k1.

EVEX.512.66.0F.WIG E9 /r

V/V

AVX512BW

Subtract packed signed word integers in

VPSUBSW zmm1 {k1}{z}, zmm2, zmm3/m512

zmm3/m512 from packed signed word integers

in zmm2 and saturate results and store in zmm1

using writemask k1.

PSUBSB/PSUBSW—Subtract Packed Signed Integers With Signed Saturation

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INSTRUCTION SET REFERENCE, M-U

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2A and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Reg-

isters” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full Mem

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs a SIMD subtract of the packed signed integers of the source operand (second operand) from the packed

signed integers of the destination operand (first operand), and stores the packed integer results in the destination

operand. See Figure 9-4 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an

illustration of a SIMD operation. Overflow is handled with signed saturation, as described in the following para-

graphs.

The (V)PSUBSB instruction subtracts packed signed byte integers. When an individual byte result is beyond the

range of a signed byte integer (that is, greater than 7FH or less than 80H), the saturated value of 7FH or 80H,

respectively, is written to the destination operand.

The (V)PSUBSW instruction subtracts packed signed word integers. When an individual word result is beyond the

range of a signed word integer (that is, greater than 7FFFH or less than 8000H), the saturated value of 7FFFH or

8000H, respectively, is written to the destination operand.

In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to

access additional registers (XMM8-XMM15).

Legacy SSE version 64-bit operand: The destination operand must be an MMX technology register and the source

operand can be either an MMX technology register or a 64-bit memory location.

128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first

source operand and destination operands are XMM registers. Bits (MAXVL-1:128) of the corresponding YMM desti-

nation register remain unchanged.

VEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first

source operand and destination operands are XMM registers. Bits (MAXVL-1:128) of the destination YMM register

are zeroed.

VEX.256 encoded versions: The second source operand is an YMM register or an 256-bit memory location. The first

source operand and destination operands are YMM registers. Bits (MAXVL-1:256) of the corresponding ZMM

EVEX encoded version: The second source operand is an ZMM/YMM/XMM register or an 512/256/128-bit memory

location. The first source operand and destination operands are ZMM/YMM/XMM registers. The destination is condi-

tionally updated with writemask k1.

Operation

PSUBSB (with 64-bit operands)

DEST[7:0] := SaturateToSignedByte (DEST[7:0] − SRC (7:0]);

(* Repeat subtract operation for 2nd through 7th bytes *)

DEST[63:56] := SaturateToSignedByte (DEST[63:56] − SRC[63:56] );

PSUBSW (with 64-bit operands)

DEST[15:0] := SaturateToSignedWord (DEST[15:0] − SRC[15:0] );

(* Repeat subtract operation for 2nd and 7th words *)

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INSTRUCTION SET REFERENCE, M-U

DEST[63:48] := SaturateToSignedWord (DEST[63:48] − SRC[63:48] );

VPSUBSB (EVEX encoded versions)

(KL, VL) = (16, 128), (32, 256), (64, 512)

FOR j := 0 TO KL-1

i := j * 8;

IF k1[j] OR *no writemask*

THEN DEST[i+7:i] := SaturateToSignedByte (SRC1[i+7:i] - SRC2[i+7:i])

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+7:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+7:i] := 0;

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

VPSUBSW (EVEX encoded versions)

(KL, VL) = (8, 128), (16, 256), (32, 512)

FOR j := 0 TO KL-1

i := j * 16

IF k1[j] OR *no writemask*

THEN DEST[i+15:i] := SaturateToSignedWord (SRC1[i+15:i] - SRC2[i+15:i])

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+15:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+15:i] := 0;

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0;

VPSUBSB (VEX.256 encoded version)

DEST[7:0] := SaturateToSignedByte (SRC1[7:0] - SRC2[7:0]);

(* Repeat subtract operation for 2nd through 31th bytes *)

DEST[255:248] := SaturateToSignedByte (SRC1[255:248] - SRC2[255:248]);

DEST[MAXVL-1:256] := 0;

VPSUBSB (VEX.128 encoded version)

DEST[7:0] := SaturateToSignedByte (SRC1[7:0] - SRC2[7:0]);

(* Repeat subtract operation for 2nd through 14th bytes *)

DEST[127:120] := SaturateToSignedByte (SRC1[127:120] - SRC2[127:120]);

DEST[MAXVL-1:128] := 0;

PSUBSB (128-bit Legacy SSE Version)

DEST[7:0] := SaturateToSignedByte (DEST[7:0] - SRC[7:0]);

(* Repeat subtract operation for 2nd through 14th bytes *)

DEST[127:120] := SaturateToSignedByte (DEST[127:120] - SRC[127:120]);

DEST[MAXVL-1:128] (Unmodified);

VPSUBSW (VEX.256 encoded version)

DEST[15:0] := SaturateToSignedWord (SRC1[15:0] - SRC2[15:0]);

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INSTRUCTION SET REFERENCE, M-U

(* Repeat subtract operation for 2nd through 15th words *)

DEST[255:240] := SaturateToSignedWord (SRC1[255:240] - SRC2[255:240]);

DEST[MAXVL-1:256] := 0;

VPSUBSW (VEX.128 encoded version)

DEST[15:0] := SaturateToSignedWord (SRC1[15:0] - SRC2[15:0]);

(* Repeat subtract operation for 2nd through 7th words *)

DEST[127:112] := SaturateToSignedWord (SRC1[127:112] - SRC2[127:112]);

DEST[MAXVL-1:128] := 0;

PSUBSW (128-bit Legacy SSE Version)

DEST[15:0] := SaturateToSignedWord (DEST[15:0] - SRC[15:0]);

(* Repeat subtract operation for 2nd through 7th words *)

DEST[127:112] := SaturateToSignedWord (DEST[127:112] - SRC[127:112]);

DEST[MAXVL-1:128] (Unmodified);

Intel C/C++ Compiler Intrinsic Equivalents

VPSUBSB __m512i _mm512_subs_epi8(__m512i a, __m512i b);

VPSUBSB __m512i _mm512_mask_subs_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);

VPSUBSB __m512i _mm512_maskz_subs_epi8( __mmask64 k, __m512i a, __m512i b);

VPSUBSB __m256i _mm256_mask_subs_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);

VPSUBSB __m256i _mm256_maskz_subs_epi8( __mmask32 k, __m256i a, __m256i b);

VPSUBSB __m128i _mm_mask_subs_epi8(__m128i s, __mmask16 k, __m128i a, __m128i b);

VPSUBSB __m128i _mm_maskz_subs_epi8( __mmask16 k, __m128i a, __m128i b);

VPSUBSW __m512i _mm512_subs_epi16(__m512i a, __m512i b);

VPSUBSW __m512i _mm512_mask_subs_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);

VPSUBSW __m512i _mm512_maskz_subs_epi16( __mmask32 k, __m512i a, __m512i b);

VPSUBSW __m256i _mm256_mask_subs_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);

VPSUBSW __m256i _mm256_maskz_subs_epi16( __mmask16 k, __m256i a, __m256i b);

VPSUBSW __m128i _mm_mask_subs_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);

VPSUBSW __m128i _mm_maskz_subs_epi16( __mmask8 k, __m128i a, __m128i b);

PSUBSB:__m64 _mm_subs_pi8(__m64 m1, __m64 m2)

(V)PSUBSB:__m128i _mm_subs_epi8(__m128i m1, __m128i m2)

VPSUBSB:__m256i _mm256_subs_epi8(__m256i m1, __m256i m2)

PSUBSW:__m64 _mm_subs_pi16(__m64 m1, __m64 m2)

(V)PSUBSW:__m128i _mm_subs_epi16(__m128i m1, __m128i m2)

VPSUBSW:__m256i _mm256_subs_epi16(__m256i m1, __m256i m2)

Flags Affected

None.

Numeric Exceptions

None.

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions”.

EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions”.

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INSTRUCTION SET REFERENCE, M-U

PSUBUSB/PSUBUSW—Subtract Packed Unsigned Integers With Unsigned Saturation

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

NP 0F D8 /r¹

V/V

MMX

Subtract unsigned packed bytes in mm/m64

from unsigned packed bytes in mm and

PSUBUSB mm, mm/m64

saturate result.

66 0F D8 /r

V/V

SSE2

Subtract packed unsigned byte integers in

xmm2/m128 from packed unsigned byte

PSUBUSB xmm1, xmm2/m128

integers in xmm1 and saturate result.

NP 0F D9 /r¹

V/V

MMX

Subtract unsigned packed words in mm/m64

from unsigned packed words in mm and

PSUBUSW mm, mm/m64

saturate result.

66 0F D9 /r

V/V

SSE2

Subtract packed unsigned word integers in

xmm2/m128 from packed unsigned word

PSUBUSW xmm1, xmm2/m128

integers in xmm1 and saturate result.

VEX.128.66.0F.WIG D8 /r

V/V

AVX

Subtract packed unsigned byte integers in

xmm3/m128 from packed unsigned byte

VPSUBUSB xmm1, xmm2, xmm3/m128

integers in xmm2 and saturate result.

VEX.128.66.0F.WIG D9 /r

V/V

AVX

Subtract packed unsigned word integers in

xmm3/m128 from packed unsigned word

VPSUBUSW xmm1, xmm2, xmm3/m128

integers in xmm2 and saturate result.

VEX.256.66.0F.WIG D8 /r

V/V

AVX2

Subtract packed unsigned byte integers in

ymm3/m256 from packed unsigned byte

VPSUBUSB ymm1, ymm2, ymm3/m256

integers in ymm2 and saturate result.

VEX.256.66.0F.WIG D9 /r

V/V

AVX2

Subtract packed unsigned word integers in

ymm3/m256 from packed unsigned word

VPSUBUSW ymm1, ymm2, ymm3/m256

integers in ymm2 and saturate result.

EVEX.128.66.0F.WIG D8 /r

V/V

AVX512VL

Subtract packed unsigned byte integers in

VPSUBUSB xmm1 {k1}{z}, xmm2, xmm3/m128

AVX512BW

xmm3/m128 from packed unsigned byte

integers in xmm2, saturate results and store

in xmm1 using writemask k1.

EVEX.256.66.0F.WIG D8 /r

V/V

AVX512VL

Subtract packed unsigned byte integers in

VPSUBUSB ymm1 {k1}{z}, ymm2, ymm3/m256

AVX512BW

ymm3/m256 from packed unsigned byte

integers in ymm2, saturate results and store

in ymm1 using writemask k1.

EVEX.512.66.0F.WIG D8 /r

V/V

AVX512BW

Subtract packed unsigned byte integers in

VPSUBUSB zmm1 {k1}{z}, zmm2, zmm3/m512

zmm3/m512 from packed unsigned byte

integers in zmm2, saturate results and store

in zmm1 using writemask k1.

EVEX.128.66.0F.WIG D9 /r

V/V

AVX512VL

Subtract packed unsigned word integers in

VPSUBUSW xmm1 {k1}{z}, xmm2, xmm3/m128

AVX512BW

xmm3/m128 from packed unsigned word

integers in xmm2 and saturate results and

store in xmm1 using writemask k1.

EVEX.256.66.0F.WIG D9 /r

V/V

AVX512VL

Subtract packed unsigned word integers in

VPSUBUSW ymm1 {k1}{z}, ymm2, ymm3/m256

AVX512BW

ymm3/m256 from packed unsigned word

integers in ymm2, saturate results and store

in ymm1 using writemask k1.

EVEX.512.66.0F.WIG D9 /r

V/V

AVX512BW

Subtract packed unsigned word integers in

VPSUBUSW zmm1 {k1}{z}, zmm2, zmm3/m512

zmm3/m512 from packed unsigned word

integers in zmm2, saturate results and store

in zmm1 using writemask k1.

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INSTRUCTION SET REFERENCE, M-U

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2A and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Reg-

isters” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full Mem

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs a SIMD subtract of the packed unsigned integers of the source operand (second operand) from the

packed unsigned integers of the destination operand (first operand), and stores the packed unsigned integer

results in the destination operand. See Figure 9-4 in the Intel® 64 and IA-32 Architectures Software Developer’s

Manual, Volume 1, for an illustration of a SIMD operation. Overflow is handled with unsigned saturation, as

described in the following paragraphs.

These instructions can operate on either 64-bit or 128-bit operands.

The (V)PSUBUSB instruction subtracts packed unsigned byte integers. When an individual byte result is less than

zero, the saturated value of 00H is written to the destination operand.

The (V)PSUBUSW instruction subtracts packed unsigned word integers. When an individual word result is less than

zero, the saturated value of 0000H is written to the destination operand.

In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to

access additional registers (XMM8-XMM15).

Legacy SSE version 64-bit operand: The destination operand must be an MMX technology register and the source

operand can be either an MMX technology register or a 64-bit memory location.

128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first

source operand and destination operands are XMM registers. Bits (MAXVL-1:128) of the corresponding YMM desti-

nation register remain unchanged.

VEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first

source operand and destination operands are XMM registers. Bits (MAXVL-1:128) of the destination YMM register

are zeroed.

VEX.256 encoded versions: The second source operand is an YMM register or an 256-bit memory location. The first

source operand and destination operands are YMM registers. Bits (MAXVL-1:256) of the corresponding ZMM

EVEX encoded version: The second source operand is an ZMM/YMM/XMM register or an 512/256/128-bit memory

location. The first source operand and destination operands are ZMM/YMM/XMM registers. The destination is condi-

tionally updated with writemask k1.

Operation

PSUBUSB (with 64-bit operands)

DEST[7:0] := SaturateToUnsignedByte (DEST[7:0] − SRC (7:0] );

(* Repeat add operation for 2nd through 7th bytes *)

DEST[63:56] := SaturateToUnsignedByte (DEST[63:56] − SRC[63:56];

PSUBUSW (with 64-bit operands)

DEST[15:0] := SaturateToUnsignedWord (DEST[15:0] − SRC[15:0] );

(* Repeat add operation for 2nd and 3rd words *)

DEST[63:48] := SaturateToUnsignedWord (DEST[63:48] − SRC[63:48] );

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INSTRUCTION SET REFERENCE, M-U

VPSUBUSB (EVEX encoded versions)

(KL, VL) = (16, 128), (32, 256), (64, 512)

FOR j := 0 TO KL-1

i := j * 8;

IF k1[j] OR *no writemask*

THEN DEST[i+7:i] := SaturateToUnsignedByte (SRC1[i+7:i] - SRC2[i+7:i])

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+7:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+7:i] := 0;

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0;

VPSUBUSW (EVEX encoded versions)

(KL, VL) = (8, 128), (16, 256), (32, 512)

FOR j := 0 TO KL-1

i := j * 16;

IF k1[j] OR *no writemask*

THEN DEST[i+15:i] := SaturateToUnsignedWord (SRC1[i+15:i] - SRC2[i+15:i])

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+15:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+15:i] := 0;

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0;

VPSUBUSB (VEX.256 encoded version)

DEST[7:0] := SaturateToUnsignedByte (SRC1[7:0] - SRC2[7:0]);

(* Repeat subtract operation for 2nd through 31st bytes *)

DEST[255:148] := SaturateToUnsignedByte (SRC1[255:248] - SRC2[255:248]);

DEST[MAXVL-1:256] := 0;

VPSUBUSB (VEX.128 encoded version)

DEST[7:0] := SaturateToUnsignedByte (SRC1[7:0] - SRC2[7:0]);

(* Repeat subtract operation for 2nd through 14th bytes *)

DEST[127:120] := SaturateToUnsignedByte (SRC1[127:120] - SRC2[127:120]);

DEST[MAXVL-1:128] := 0

PSUBUSB (128-bit Legacy SSE Version)

DEST[7:0] := SaturateToUnsignedByte (DEST[7:0] - SRC[7:0]);

(* Repeat subtract operation for 2nd through 14th bytes *)

DEST[127:120] := SaturateToUnsignedByte (DEST[127:120] - SRC[127:120]);

DEST[MAXVL-1:128] (Unmodified)

VPSUBUSW (VEX.256 encoded version)

DEST[15:0] := SaturateToUnsignedWord (SRC1[15:0] - SRC2[15:0]);

(* Repeat subtract operation for 2nd through 15th words *)

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4-495

INSTRUCTION SET REFERENCE, M-U

DEST[255:240] := SaturateToUnsignedWord (SRC1[255:240] - SRC2[255:240]);

DEST[MAXVL-1:256] := 0;

VPSUBUSW (VEX.128 encoded version)

DEST[15:0] := SaturateToUnsignedWord (SRC1[15:0] - SRC2[15:0]);

(* Repeat subtract operation for 2nd through 7th words *)

DEST[127:112] := SaturateToUnsignedWord (SRC1[127:112] - SRC2[127:112]);

DEST[MAXVL-1:128] := 0

PSUBUSW (128-bit Legacy SSE Version)

DEST[15:0] := SaturateToUnsignedWord (DEST[15:0] - SRC[15:0]);

(* Repeat subtract operation for 2nd through 7th words *)

DEST[127:112] := SaturateToUnsignedWord (DEST[127:112] - SRC[127:112]);

DEST[MAXVL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalents

VPSUBUSB __m512i _mm512_subs_epu8(__m512i a, __m512i b);

VPSUBUSB __m512i _mm512_mask_subs_epu8(__m512i s, __mmask64 k, __m512i a, __m512i b);

VPSUBUSB __m512i _mm512_maskz_subs_epu8( __mmask64 k, __m512i a, __m512i b);

VPSUBUSB __m256i _mm256_mask_subs_epu8(__m256i s, __mmask32 k, __m256i a, __m256i b);

VPSUBUSB __m256i _mm256_maskz_subs_epu8( __mmask32 k, __m256i a, __m256i b);

VPSUBUSB __m128i _mm_mask_subs_epu8(__m128i s, __mmask16 k, __m128i a, __m128i b);

VPSUBUSB __m128i _mm_maskz_subs_epu8( __mmask16 k, __m128i a, __m128i b);

VPSUBUSW __m512i _mm512_subs_epu16(__m512i a, __m512i b);

VPSUBUSW __m512i _mm512_mask_subs_epu16(__m512i s, __mmask32 k, __m512i a, __m512i b);

VPSUBUSW __m512i _mm512_maskz_subs_epu16( __mmask32 k, __m512i a, __m512i b);

VPSUBUSW __m256i _mm256_mask_subs_epu16(__m256i s, __mmask16 k, __m256i a, __m256i b);

VPSUBUSW __m256i _mm256_maskz_subs_epu16( __mmask16 k, __m256i a, __m256i b);

VPSUBUSW __m128i _mm_mask_subs_epu16(__m128i s, __mmask8 k, __m128i a, __m128i b);

VPSUBUSW __m128i _mm_maskz_subs_epu16( __mmask8 k, __m128i a, __m128i b);

PSUBUSB:__m64 _mm_subs_pu8(__m64 m1, __m64 m2)

(V)PSUBUSB:__m128i _mm_subs_epu8(__m128i m1, __m128i m2)

VPSUBUSB:__m256i _mm256_subs_epu8(__m256i m1, __m256i m2)

PSUBUSW:__m64 _mm_subs_pu16(__m64 m1, __m64 m2)

(V)PSUBUSW:__m128i _mm_subs_epu16(__m128i m1, __m128i m2)

VPSUBUSW:__m256i _mm256_subs_epu16(__m256i m1, __m256i m2)

Flags Affected

None.

Numeric Exceptions

None.

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions”.

EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions”.

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INSTRUCTION SET REFERENCE, M-U

PTEST—Logical Compare

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

66 0F 38 17 /r

V/V

SSE4_1

Set ZF if xmm2/m128 AND xmm1 result is all

PTEST xmm1, xmm2/m128

0s. Set CF if xmm2/m128 AND NOT xmm1

result is all 0s.

VEX.128.66.0F38.WIG 17 /r

V/V

AVX

Set ZF and CF depending on bitwise AND and

VPTEST xmm1, xmm2/m128

ANDN of sources.

VEX.256.66.0F38.WIG 17 /r

V/V

AVX

Set ZF and CF depending on bitwise AND and

VPTEST ymm1, ymm2/m256

ANDN of sources.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (r)

ModRM:r/m (r)

N/A

Description

PTEST and VPTEST set the ZF flag if all bits in the result are 0 of the bitwise AND of the first source operand (first

operand) and the second source operand (second operand). VPTEST sets the CF flag if all bits in the result are 0 of

the bitwise AND of the second source operand (second operand) and the logical NOT of the destination operand.

The first source register is specified by the ModR/M reg field.

128-bit versions: The first source register is an XMM register. The second source register can be an XMM register

or a 128-bit memory location. The destination register is not modified.

VEX.256 encoded version: The first source register is a YMM register. The second source register can be a YMM

Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation

(V)PTEST (128-bit version)

IF (SRC[127:0] BITWISE AND DEST[127:0] = 0)

THEN ZF := 1;

ELSE ZF := 0;

IF (SRC[127:0] BITWISE AND NOT DEST[127:0] = 0)

THEN CF := 1;

ELSE CF := 0;

DEST (unmodified)

AF := OF := PF := SF := 0;

VPTEST (VEX.256 encoded version)

IF (SRC[255:0] BITWISE AND DEST[255:0] = 0) THEN ZF := 1;

ELSE ZF := 0;

IF (SRC[255:0] BITWISE AND NOT DEST[255:0] = 0) THEN CF := 1;

ELSE CF := 0;

DEST (unmodified)

AF := OF := PF := SF := 0;

PTEST—Logical Compare

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INSTRUCTION SET REFERENCE, M-U

Intel C/C++ Compiler Intrinsic Equivalent

PTEST

int _mm_testz_si128 (__m128i s1, __m128i s2);

int _mm_testc_si128 (__m128i s1, __m128i s2);

int _mm_testnzc_si128 (__m128i s1, __m128i s2);

VPTEST

int _mm256_testz_si256 (__m256i s1, __m256i s2);

int _mm256_testc_si256 (__m256i s1, __m256i s2);

int _mm256_testnzc_si256 (__m256i s1, __m256i s2);

int _mm_testz_si128 (__m128i s1, __m128i s2);

int _mm_testc_si128 (__m128i s1, __m128i s2);

int _mm_testnzc_si128 (__m128i s1, __m128i s2);

Flags Affected

The OF, AF, PF, SF flags are cleared and the ZF, CF flags are set according to the operation.

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-21, “Type 4 Class Exception Conditions”; additionally:

#UD

If VEX.vvvv ≠ 1111B.

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PTEST—Logical Compare

INSTRUCTION SET REFERENCE, M-U

PTWRITE—Write Data to a Processor Trace Packet

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

F3 REX.W 0F AE /4

V/N.E

Reads the data from r64/m64 to encode into a

PTWRITE r64/m64

PTW packet if dependencies are met (see

details below).

F3 0F AE /4

V/V

Reads the data from r32/m32 to encode into a

PTWRITE r32/m32

PTW packet if dependencies are met (see

details below).

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:rm (r)

N/A

Description

This instruction reads data in the source operand and sends it to the Intel Processor Trace hardware to be encoded

in a PTW packet if TriggerEn, ContextEn, FilterEn, and PTWEn are all set to 1. For more details on these values, see

Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C, Section 33.2.2, “Software Trace

Instrumentation with PTWRITE.” The size of data is 64-bit if using REX.W in 64-bit mode, otherwise 32-bits of data

are copied from the source operand.

Note: The instruction will #UD if prefix 66H is used.

Operation

IF (IA32_RTIT_STATUS.TriggerEn & IA32_RTIT_STATUS.ContextEn & IA32_RTIT_STATUS.FilterEn & IA32_RTIT_CTL.PTWEn) = 1

PTW.PayloadBytes := Encoded payload size;

PTW.IP := IA32_RTIT_CTL.FUPonPTW

IF IA32_RTIT_CTL.FUPonPTW = 1

Insert FUP packet with IP of PTWRITE;

FI;

Flags Affected

None.

Other Exceptions

#GP(0)

If a memory operand effective address is outside the CS, DS, ES, FS or GS segments.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#PF (fault-code)

For a page fault.

#AC(0)

If an unaligned memory reference is made while the current privilege level is 3 and alignment

checking is enabled.

#UD

If CPUID.(EAX=14H, ECX=0):EBX.PTWRITE [Bit 4] = 0.

If LOCK prefix is used.

If 66H prefix is used.

PTWRITE—Write Data to a Processor Trace Packet

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INSTRUCTION SET REFERENCE, M-U

Real-Address Mode Exceptions

#GP(0)

If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#UD

If CPUID.(EAX=14H, ECX=0):EBX.PTWRITE [Bit 4] = 0.

If LOCK prefix is used.

If 66H prefix is used.

Virtual 8086 Mode Exceptions

#GP(0)

If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#PF (fault-code)

For a page fault.

#AC(0)

If an unaligned memory reference is made while alignment checking is enabled.

#UD

If CPUID.(EAX=14H, ECX=0):EBX.PTWRITE [Bit 4] = 0.

If LOCK prefix is used.

If 66H prefix is used.

Compatibility Mode Exceptions

Same exceptions as in Protected Mode.

64-Bit Mode Exceptions

#GP(0)

If the memory address is in a non-canonical form.

#SS(0)

If a memory address referencing the SS segment is in a non-canonical form.

#PF (fault-code)

For a page fault.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If CPUID.(EAX=14H, ECX=0):EBX.PTWRITE [Bit 4] = 0.

If LOCK prefix is used.

If 66H prefix is used.

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PTWRITE—Write Data to a Processor Trace Packet

INSTRUCTION SET REFERENCE, M-U

PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High Data

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

NP 0F 68 /r¹

V/V

MMX

Unpack and interleave high-order bytes from

mm and mm/m64 into mm.

PUNPCKHBW mm, mm/m64

66 0F 68 /r

V/V

SSE2

Unpack and interleave high-order bytes from

xmm1 and xmm2/m128 into xmm1.

PUNPCKHBW xmm1, xmm2/m128

NP 0F 69 /r¹

V/V

MMX

Unpack and interleave high-order words from

mm and mm/m64 into mm.

PUNPCKHWD mm, mm/m64

66 0F 69 /r

V/V

SSE2

Unpack and interleave high-order words from

xmm1 and xmm2/m128 into xmm1.

PUNPCKHWD xmm1, xmm2/m128

NP 0F 6A /r¹

V/V

MMX

Unpack and interleave high-order

doublewords from mm and mm/m64 into mm.

PUNPCKHDQ mm, mm/m64

66 0F 6A /r

V/V

SSE2

Unpack and interleave high-order

doublewords from xmm1 and xmm2/m128

PUNPCKHDQ xmm1, xmm2/m128

into xmm1.

66 0F 6D /r

V/V

SSE2

Unpack and interleave high-order quadwords

from xmm1 and xmm2/m128 into xmm1.

PUNPCKHQDQ xmm1, xmm2/m128

VEX.128.66.0F.WIG 68/r

V/V

AVX

Interleave high-order bytes from xmm2 and

xmm3/m128 into xmm1.

VPUNPCKHBW xmm1,xmm2, xmm3/m128

VEX.128.66.0F.WIG 69/r

V/V

AVX

Interleave high-order words from xmm2 and

xmm3/m128 into xmm1.

VPUNPCKHWD xmm1,xmm2, xmm3/m128

VEX.128.66.0F.WIG 6A/r

V/V

AVX

Interleave high-order doublewords from

xmm2 and xmm3/m128 into xmm1.

VPUNPCKHDQ xmm1, xmm2, xmm3/m128

VEX.128.66.0F.WIG 6D/r

V/V

AVX

Interleave high-order quadword from xmm2

VPUNPCKHQDQ xmm1, xmm2, xmm3/m128

and xmm3/m128 into xmm1 register.

VEX.256.66.0F.WIG 68 /r

V/V

AVX2

Interleave high-order bytes from ymm2 and

VPUNPCKHBW ymm1, ymm2, ymm3/m256

ymm3/m256 into ymm1 register.

VEX.256.66.0F.WIG 69 /r

V/V

AVX2

Interleave high-order words from ymm2 and

VPUNPCKHWD ymm1, ymm2, ymm3/m256

ymm3/m256 into ymm1 register.

VEX.256.66.0F.WIG 6A /r

V/V

AVX2

Interleave high-order doublewords from

VPUNPCKHDQ ymm1, ymm2, ymm3/m256

ymm2 and ymm3/m256 into ymm1 register.

VEX.256.66.0F.WIG 6D /r

V/V

AVX2

Interleave high-order quadword from ymm2

VPUNPCKHQDQ ymm1, ymm2, ymm3/m256

and ymm3/m256 into ymm1 register.

EVEX.128.66.0F.WIG 68 /r

V/V

AVX512VL

Interleave high-order bytes from xmm2 and

VPUNPCKHBW xmm1 {k1}{z}, xmm2, xmm3/m128

AVX512BW

xmm3/m128 into xmm1 register using k1

write mask.

EVEX.128.66.0F.WIG 69 /r

V/V

AVX512VL

Interleave high-order words from xmm2 and

VPUNPCKHWD xmm1 {k1}{z}, xmm2, xmm3/m128

AVX512BW

xmm3/m128 into xmm1 register using k1

write mask.

EVEX.128.66.0F.W0 6A /r

V/V

AVX512VL

Interleave high-order doublewords from

VPUNPCKHDQ xmm1 {k1}{z}, xmm2,

AVX512F

xmm2 and xmm3/m128/m32bcst into xmm1

xmm3/m128/m32bcst

EVEX.128.66.0F.W1 6D /r

V/V

AVX512VL

Interleave high-order quadword from xmm2

VPUNPCKHQDQ xmm1 {k1}{z}, xmm2,

AVX512F

and xmm3/m128/m64bcst into xmm1

xmm3/m128/m64bcst

PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High Data

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INSTRUCTION SET REFERENCE, M-U

EVEX.256.66.0F.WIG 68 /r

V/V

AVX512VL

Interleave high-order bytes from ymm2 and

VPUNPCKHBW ymm1 {k1}{z}, ymm2, ymm3/m256

AVX512BW

ymm3/m256 into ymm1 register using k1

write mask.

EVEX.256.66.0F.WIG 69 /r

V/V

AVX512VL

Interleave high-order words from ymm2 and

VPUNPCKHWD ymm1 {k1}{z}, ymm2, ymm3/m256

AVX512BW

ymm3/m256 into ymm1 register using k1

write mask.

EVEX.256.66.0F.W0 6A /r

V/V

AVX512VL

Interleave high-order doublewords from

VPUNPCKHDQ ymm1 {k1}{z}, ymm2,

AVX512F

ymm2 and ymm3/m256/m32bcst into ymm1

ymm3/m256/m32bcst

EVEX.256.66.0F.W1 6D /r

V/V

AVX512VL

Interleave high-order quadword from ymm2

VPUNPCKHQDQ ymm1 {k1}{z}, ymm2,

AVX512F

and ymm3/m256/m64bcst into ymm1

ymm3/m256/m64bcst

EVEX.512.66.0F.WIG 68/r

V/V

AVX512BW

Interleave high-order bytes from zmm2 and

VPUNPCKHBW zmm1 {k1}{z}, zmm2, zmm3/m512

zmm3/m512 into zmm1 register.

EVEX.512.66.0F.WIG 69/r

V/V

AVX512BW

Interleave high-order words from zmm2 and

VPUNPCKHWD zmm1 {k1}{z}, zmm2, zmm3/m512

zmm3/m512 into zmm1 register.

EVEX.512.66.0F.W0 6A /r

V/V

AVX512F

Interleave high-order doublewords from

VPUNPCKHDQ zmm1 {k1}{z}, zmm2,

zmm2 and zmm3/m512/m32bcst into zmm1

zmm3/m512/m32bcst

EVEX.512.66.0F.W1 6D /r

V/V

AVX512F

Interleave high-order quadword from zmm2

VPUNPCKHQDQ zmm1 {k1}{z}, zmm2,

and zmm3/m512/m64bcst into zmm1 register

zmm3/m512/m64bcst

using k1 write mask.

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2A and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Reg-

isters” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full Mem

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Unpacks and interleaves the high-order data elements (bytes, words, doublewords, or quadwords) of the destina-

tion operand (first operand) and source operand (second operand) into the destination operand. Figure 4-20 shows

the unpack operation for bytes in 64-bit operands. The low-order data elements are ignored.

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PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High Data

INSTRUCTION SET REFERENCE, M-U

SRC

DEST

Figure 4-20. PUNPCKHBW Instruction Operation Using 64-bit Operands

255

SRC

255

DEST

Figure 4-21. 256-bit VPUNPCKHDQ Instruction Operation

When the source data comes from a 64-bit memory operand, the full 64-bit operand is accessed from memory, but

the instruction uses only the high-order 32 bits. When the source data comes from a 128-bit memory operand, an

implementation may fetch only the appropriate 64 bits; however, alignment to a 16-byte boundary and normal

segment checking will still be enforced.

The (V)PUNPCKHBW instruction interleaves the high-order bytes of the source and destination operands, the

(V)PUNPCKHWD instruction interleaves the high-order words of the source and destination operands, the

(V)PUNPCKHDQ instruction interleaves the high-order doubleword (or doublewords) of the source and destination

operands, and the (V)PUNPCKHQDQ instruction interleaves the high-order quadwords of the source and destina-

tion operands.

These instructions can be used to convert bytes to words, words to doublewords, doublewords to quadwords, and

quadwords to double quadwords, respectively, by placing all 0s in the source operand. Here, if the source operand

contains all 0s, the result (stored in the destination operand) contains zero extensions of the high-order data

elements from the original value in the destination operand. For example, with the (V)PUNPCKHBW instruction the

high-order bytes are zero extended (that is, unpacked into unsigned word integers), and with the (V)PUNPCKHWD

instruction, the high-order words are zero extended (unpacked into unsigned doubleword integers).

In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to

access additional registers (XMM8-XMM15).

Legacy SSE versions 64-bit operand: The source operand can be an MMX technology register or a 64-bit memory

location. The destination operand is an MMX technology register.

128-bit Legacy SSE versions: The second source operand is an XMM register or a 128-bit memory location. The

first source operand and destination operands are XMM registers. Bits (MAXVL-1:128) of the corresponding YMM

destination register remain unchanged.

VEX.128 encoded versions: The second source operand is an XMM register or a 128-bit memory location. The first

source operand and destination operands are XMM registers. Bits (MAXVL-1:128) of the destination YMM register

are zeroed.

VEX.256 encoded version: The second source operand is an YMM register or an 256-bit memory location. The first

source operand and destination operands are YMM registers.

PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High Data

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INSTRUCTION SET REFERENCE, M-U

EVEX encoded VPUNPCKHDQ/QDQ: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit

memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The first source

operand and destination operands are ZMM/YMM/XMM registers. The destination is conditionally updated with

writemask k1.

EVEX encoded VPUNPCKHWD/BW: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit

memory location. The first source operand and destination operands are ZMM/YMM/XMM registers. The destination

is conditionally updated with writemask k1.

Operation

PUNPCKHBW instruction with 64-bit operands:

DEST[7:0] := DEST[39:32];

DEST[15:8] := SRC[39:32];

DEST[23:16] := DEST[47:40];

DEST[31:24] := SRC[47:40];

DEST[39:32] := DEST[55:48];

DEST[47:40] := SRC[55:48];

DEST[55:48] := DEST[63:56];

DEST[63:56] := SRC[63:56];

PUNPCKHW instruction with 64-bit operands:

DEST[15:0] := DEST[47:32];

DEST[31:16] := SRC[47:32];

DEST[47:32] := DEST[63:48];

DEST[63:48] := SRC[63:48];

PUNPCKHDQ instruction with 64-bit operands:

DEST[31:0] := DEST[63:32];

DEST[63:32] := SRC[63:32];

INTERLEAVE_HIGH_BYTES_512b (SRC1, SRC2)

TMP_DEST[255:0] := INTERLEAVE_HIGH_BYTES_256b(SRC1[255:0], SRC[255:0])

TMP_DEST[511:256] := INTERLEAVE_HIGH_BYTES_256b(SRC1[511:256], SRC[511:256])

INTERLEAVE_HIGH_BYTES_256b (SRC1, SRC2)

DEST[7:0] := SRC1[71:64]

DEST[15:8] := SRC2[71:64]

DEST[23:16] := SRC1[79:72]

DEST[31:24] := SRC2[79:72]

DEST[39:32] := SRC1[87:80]

DEST[47:40] := SRC2[87:80]

DEST[55:48] := SRC1[95:88]

DEST[63:56] := SRC2[95:88]

DEST[71:64] := SRC1[103:96]

DEST[79:72] := SRC2[103:96]

DEST[87:80] := SRC1[111:104]

DEST[95:88] := SRC2[111:104]

DEST[103:96] := SRC1[119:112]

DEST[111:104] := SRC2[119:112]

DEST[119:112] := SRC1[127:120]

DEST[127:120] := SRC2[127:120]

DEST[135:128] := SRC1[199:192]

DEST[143:136] := SRC2[199:192]

DEST[151:144] := SRC1[207:200]

DEST[159:152] := SRC2[207:200]

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PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High Data

INSTRUCTION SET REFERENCE, M-U

DEST[167:160] := SRC1[215:208]

DEST[175:168] := SRC2[215:208]

DEST[183:176] := SRC1[223:216]

DEST[191:184] := SRC2[223:216]

DEST[199:192] := SRC1[231:224]

DEST[207:200] := SRC2[231:224]

DEST[215:208] := SRC1[239:232]

DEST[223:216] := SRC2[239:232]

DEST[231:224] := SRC1[247:240]

DEST[239:232] := SRC2[247:240]

DEST[247:240] := SRC1[255:248]

DEST[255:248] := SRC2[255:248]

INTERLEAVE_HIGH_BYTES (SRC1, SRC2)

DEST[7:0] := SRC1[71:64]

DEST[15:8] := SRC2[71:64]

DEST[23:16] := SRC1[79:72]

DEST[31:24] := SRC2[79:72]

DEST[39:32] := SRC1[87:80]

DEST[47:40] := SRC2[87:80]

DEST[55:48] := SRC1[95:88]

DEST[63:56] := SRC2[95:88]

DEST[71:64] := SRC1[103:96]

DEST[79:72] := SRC2[103:96]

DEST[87:80] := SRC1[111:104]

DEST[95:88] := SRC2[111:104]

DEST[103:96] := SRC1[119:112]

DEST[111:104] := SRC2[119:112]

DEST[119:112] := SRC1[127:120]

DEST[127:120] := SRC2[127:120]

INTERLEAVE_HIGH_WORDS_512b (SRC1, SRC2)

TMP_DEST[255:0] := INTERLEAVE_HIGH_WORDS_256b(SRC1[255:0], SRC[255:0])

TMP_DEST[511:256] := INTERLEAVE_HIGH_WORDS_256b(SRC1[511:256], SRC[511:256])

INTERLEAVE_HIGH_WORDS_256b(SRC1, SRC2)

DEST[15:0] := SRC1[79:64]

DEST[31:16] := SRC2[79:64]

DEST[47:32] := SRC1[95:80]

DEST[63:48] := SRC2[95:80]

DEST[79:64] := SRC1[111:96]

DEST[95:80] := SRC2[111:96]

DEST[111:96] := SRC1[127:112]

DEST[127:112] := SRC2[127:112]

DEST[143:128] := SRC1[207:192]

DEST[159:144] := SRC2[207:192]

DEST[175:160] := SRC1[223:208]

DEST[191:176] := SRC2[223:208]

DEST[207:192] := SRC1[239:224]

DEST[223:208] := SRC2[239:224]

DEST[239:224] := SRC1[255:240]

DEST[255:240] := SRC2[255:240]

INTERLEAVE_HIGH_WORDS (SRC1, SRC2)

PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High Data

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INSTRUCTION SET REFERENCE, M-U

DEST[15:0] := SRC1[79:64]

DEST[31:16] := SRC2[79:64]

DEST[47:32] := SRC1[95:80]

DEST[63:48] := SRC2[95:80]

DEST[79:64] := SRC1[111:96]

DEST[95:80] := SRC2[111:96]

DEST[111:96] := SRC1[127:112]

DEST[127:112] := SRC2[127:112]

INTERLEAVE_HIGH_DWORDS_512b (SRC1, SRC2)

TMP_DEST[255:0] := INTERLEAVE_HIGH_DWORDS_256b(SRC1[255:0], SRC2[255:0])

TMP_DEST[511:256] := INTERLEAVE_HIGH_DWORDS_256b(SRC1[511:256], SRC2[511:256])

INTERLEAVE_HIGH_DWORDS_256b(SRC1, SRC2)

DEST[31:0] := SRC1[95:64]

DEST[63:32] := SRC2[95:64]

DEST[95:64] := SRC1[127:96]

DEST[127:96] := SRC2[127:96]

DEST[159:128] := SRC1[223:192]

DEST[191:160] := SRC2[223:192]

DEST[223:192] := SRC1[255:224]

DEST[255:224] := SRC2[255:224]

INTERLEAVE_HIGH_DWORDS(SRC1, SRC2)

DEST[31:0] := SRC1[95:64]

DEST[63:32] := SRC2[95:64]

DEST[95:64] := SRC1[127:96]

DEST[127:96] := SRC2[127:96]

INTERLEAVE_HIGH_QWORDS_512b (SRC1, SRC2)

TMP_DEST[255:0] := INTERLEAVE_HIGH_QWORDS_256b(SRC1[255:0], SRC2[255:0])

TMP_DEST[511:256] := INTERLEAVE_HIGH_QWORDS_256b(SRC1[511:256], SRC2[511:256])

INTERLEAVE_HIGH_QWORDS_256b(SRC1, SRC2)

DEST[63:0] := SRC1[127:64]

DEST[127:64] := SRC2[127:64]

DEST[191:128] := SRC1[255:192]

DEST[255:192] := SRC2[255:192]

INTERLEAVE_HIGH_QWORDS(SRC1, SRC2)

DEST[63:0] := SRC1[127:64]

DEST[127:64] := SRC2[127:64]

PUNPCKHBW (128-bit Legacy SSE Version)

DEST[127:0] := INTERLEAVE_HIGH_BYTES(DEST, SRC)

DEST[255:127] (Unmodified)

VPUNPCKHBW (VEX.128 encoded version)

DEST[127:0] := INTERLEAVE_HIGH_BYTES(SRC1, SRC2)

DEST[MAXVL-1:127] := 0

VPUNPCKHBW (VEX.256 encoded version)

DEST[255:0] := INTERLEAVE_HIGH_BYTES_256b(SRC1, SRC2)

DEST[MAXVL-1:256] := 0

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PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High Data

INSTRUCTION SET REFERENCE, M-U

VPUNPCKHBW (EVEX encoded versions)

(KL, VL) = (16, 128), (32, 256), (64, 512)

IF VL = 128

TMP_DEST[VL-1:0] := INTERLEAVE_HIGH_BYTES(SRC1[VL-1:0], SRC2[VL-1:0])

FI;

IF VL = 256

TMP_DEST[VL-1:0] := INTERLEAVE_HIGH_BYTES_256b(SRC1[VL-1:0], SRC2[VL-1:0])

FI;

IF VL = 512

TMP_DEST[VL-1:0] := INTERLEAVE_HIGH_BYTES_512b(SRC1[VL-1:0], SRC2[VL-1:0])

FI;

FOR j := 0 TO KL-1

i := j * 8

IF k1[j] OR *no writemask*

THEN DEST[i+7:i] := TMP_DEST[i+7:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+7:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+7:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

PUNPCKHWD (128-bit Legacy SSE Version)

DEST[127:0] := INTERLEAVE_HIGH_WORDS(DEST, SRC)

DEST[255:127] (Unmodified)

VPUNPCKHWD (VEX.128 encoded version)

DEST[127:0] := INTERLEAVE_HIGH_WORDS(SRC1, SRC2)

DEST[MAXVL-1:127] := 0

VPUNPCKHWD (VEX.256 encoded version)

DEST[255:0] := INTERLEAVE_HIGH_WORDS_256b(SRC1, SRC2)

DEST[MAXVL-1:256] := 0

VPUNPCKHWD (EVEX encoded versions)

(KL, VL) = (8, 128), (16, 256), (32, 512)

IF VL = 128

TMP_DEST[VL-1:0] := INTERLEAVE_HIGH_WORDS(SRC1[VL-1:0], SRC2[VL-1:0])

FI;

IF VL = 256

TMP_DEST[VL-1:0] := INTERLEAVE_HIGH_WORDS_256b(SRC1[VL-1:0], SRC2[VL-1:0])

FI;

IF VL = 512

TMP_DEST[VL-1:0] := INTERLEAVE_HIGH_WORDS_512b(SRC1[VL-1:0], SRC2[VL-1:0])

FI;

FOR j := 0 TO KL-1

i := j * 16

IF k1[j] OR *no writemask*

PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High Data

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INSTRUCTION SET REFERENCE, M-U

THEN DEST[i+15:i] := TMP_DEST[i+15:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+15:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+15:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

PUNPCKHDQ (128-bit Legacy SSE Version)

DEST[127:0] := INTERLEAVE_HIGH_DWORDS(DEST, SRC)

DEST[255:127] (Unmodified)

VPUNPCKHDQ (VEX.128 encoded version)

DEST[127:0] := INTERLEAVE_HIGH_DWORDS(SRC1, SRC2)

DEST[MAXVL-1:127] := 0

VPUNPCKHDQ (VEX.256 encoded version)

DEST[255:0] := INTERLEAVE_HIGH_DWORDS_256b(SRC1, SRC2)

DEST[MAXVL-1:256] := 0

VPUNPCKHDQ (EVEX.512 encoded version)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF (EVEX.b = 1) AND (SRC2 *is memory*)

THEN TMP_SRC2[i+31:i] := SRC2[31:0]

ELSE TMP_SRC2[i+31:i] := SRC2[i+31:i]

FI;

ENDFOR;

IF VL = 128

TMP_DEST[VL-1:0] := INTERLEAVE_HIGH_DWORDS(SRC1[VL-1:0], TMP_SRC2[VL-1:0])

FI;

IF VL = 256

TMP_DEST[VL-1:0] := INTERLEAVE_HIGH_DWORDS_256b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])

FI;

IF VL = 512

TMP_DEST[VL-1:0] := INTERLEAVE_HIGH_DWORDS_512b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])

FI;

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] := TMP_DEST[i+31:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

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PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High Data

INSTRUCTION SET REFERENCE, M-U

DEST[MAXVL-1:VL] := 0

PUNPCKHQDQ (128-bit Legacy SSE Version)

DEST[127:0] := INTERLEAVE_HIGH_QWORDS(DEST, SRC)

DEST[MAXVL-1:128] (Unmodified)

VPUNPCKHQDQ (VEX.128 encoded version)

DEST[127:0] := INTERLEAVE_HIGH_QWORDS(SRC1, SRC2)

DEST[MAXVL-1:128] := 0

VPUNPCKHQDQ (VEX.256 encoded version)

DEST[255:0] := INTERLEAVE_HIGH_QWORDS_256b(SRC1, SRC2)

DEST[MAXVL-1:256] := 0

VPUNPCKHQDQ (EVEX encoded versions)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF (EVEX.b = 1) AND (SRC2 *is memory*)

THEN TMP_SRC2[i+63:i] := SRC2[63:0]

ELSE TMP_SRC2[i+63:i] := SRC2[i+63:i]

FI;

ENDFOR;

IF VL = 128

TMP_DEST[VL-1:0] := INTERLEAVE_HIGH_QWORDS(SRC1[VL-1:0], TMP_SRC2[VL-1:0])

FI;

IF VL = 256

TMP_DEST[VL-1:0] := INTERLEAVE_HIGH_QWORDS_256b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])

FI;

IF VL = 512

TMP_DEST[VL-1:0] := INTERLEAVE_HIGH_QWORDS_512b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])

FI;

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i] := TMP_DEST[i+63:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

Intel C/C++ Compiler Intrinsic Equivalents

VPUNPCKHBW __m512i _mm512_unpackhi_epi8(__m512i a, __m512i b);

VPUNPCKHBW __m512i _mm512_mask_unpackhi_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);

VPUNPCKHBW __m512i _mm512_maskz_unpackhi_epi8( __mmask64 k, __m512i a, __m512i b);

VPUNPCKHBW __m256i _mm256_mask_unpackhi_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);

VPUNPCKHBW __m256i _mm256_maskz_unpackhi_epi8( __mmask32 k, __m256i a, __m256i b);

VPUNPCKHBW __m128i _mm_mask_unpackhi_epi8(v s, __mmask16 k, __m128i a, __m128i b);

PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High Data

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INSTRUCTION SET REFERENCE, M-U

VPUNPCKHBW __m128i _mm_maskz_unpackhi_epi8( __mmask16 k, __m128i a, __m128i b);

VPUNPCKHWD __m512i _mm512_unpackhi_epi16(__m512i a, __m512i b);

VPUNPCKHWD __m512i _mm512_mask_unpackhi_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);

VPUNPCKHWD __m512i _mm512_maskz_unpackhi_epi16( __mmask32 k, __m512i a, __m512i b);

VPUNPCKHWD __m256i _mm256_mask_unpackhi_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);

VPUNPCKHWD __m256i _mm256_maskz_unpackhi_epi16( __mmask16 k, __m256i a, __m256i b);

VPUNPCKHWD __m128i _mm_mask_unpackhi_epi16(v s, __mmask8 k, __m128i a, __m128i b);

VPUNPCKHWD __m128i _mm_maskz_unpackhi_epi16( __mmask8 k, __m128i a, __m128i b);

VPUNPCKHDQ __m512i _mm512_unpackhi_epi32(__m512i a, __m512i b);

VPUNPCKHDQ __m512i _mm512_mask_unpackhi_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);

VPUNPCKHDQ __m512i _mm512_maskz_unpackhi_epi32( __mmask16 k, __m512i a, __m512i b);

VPUNPCKHDQ __m256i _mm256_mask_unpackhi_epi32(__m512i s, __mmask8 k, __m512i a, __m512i b);

VPUNPCKHDQ __m256i _mm256_maskz_unpackhi_epi32( __mmask8 k, __m512i a, __m512i b);

VPUNPCKHDQ __m128i _mm_mask_unpackhi_epi32(__m512i s, __mmask8 k, __m512i a, __m512i b);

VPUNPCKHDQ __m128i _mm_maskz_unpackhi_epi32( __mmask8 k, __m512i a, __m512i b);

VPUNPCKHQDQ __m512i _mm512_unpackhi_epi64(__m512i a, __m512i b);

VPUNPCKHQDQ __m512i _mm512_mask_unpackhi_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);

VPUNPCKHQDQ __m512i _mm512_maskz_unpackhi_epi64( __mmask8 k, __m512i a, __m512i b);

VPUNPCKHQDQ __m256i _mm256_mask_unpackhi_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);

VPUNPCKHQDQ __m256i _mm256_maskz_unpackhi_epi64( __mmask8 k, __m512i a, __m512i b);

VPUNPCKHQDQ __m128i _mm_mask_unpackhi_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);

VPUNPCKHQDQ __m128i _mm_maskz_unpackhi_epi64( __mmask8 k, __m512i a, __m512i b);

PUNPCKHBW:__m64 _mm_unpackhi_pi8(__m64 m1, __m64 m2)

(V)PUNPCKHBW:__m128i _mm_unpackhi_epi8(__m128i m1, __m128i m2)

VPUNPCKHBW:__m256i _mm256_unpackhi_epi8(__m256i m1, __m256i m2)

PUNPCKHWD:__m64 _mm_unpackhi_pi16(__m64 m1,__m64 m2)

(V)PUNPCKHWD:__m128i _mm_unpackhi_epi16(__m128i m1,__m128i m2)

VPUNPCKHWD:__m256i _mm256_unpackhi_epi16(__m256i m1,__m256i m2)

PUNPCKHDQ:__m64 _mm_unpackhi_pi32(__m64 m1, __m64 m2)

(V)PUNPCKHDQ:__m128i _mm_unpackhi_epi32(__m128i m1, __m128i m2)

VPUNPCKHDQ:__m256i _mm256_unpackhi_epi32(__m256i m1, __m256i m2)

(V)PUNPCKHQDQ:__m128i _mm_unpackhi_epi64 ( __m128i a, __m128i b)

VPUNPCKHQDQ:__m256i _mm256_unpackhi_epi64 ( __m256i a, __m256i b)

Flags Affected

None.

Numeric Exceptions

None.

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions”.

EVEX-encoded VPUNPCKHQDQ/QDQ, see Table 2-50, “Type E4NF Class Exception Conditions”.

EVEX-encoded VPUNPCKHBW/WD, see Exceptions Type E4NF.nb in Table 2-50, “Type E4NF Class Exception Condi-

tions”.

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INSTRUCTION SET REFERENCE, M-U

PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ—Unpack Low Data

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

NP 0F 60 /r¹

V/V

MMX

Interleave low-order bytes from mm and

mm/m32 into mm.

PUNPCKLBW mm, mm/m32

66 0F 60 /r

V/V

SSE2

Interleave low-order bytes from xmm1 and

xmm2/m128 into xmm1.

PUNPCKLBW xmm1, xmm2/m128

NP 0F 61 /r¹

V/V

MMX

Interleave low-order words from mm and

mm/m32 into mm.

PUNPCKLWD mm, mm/m32

66 0F 61 /r

V/V

SSE2

Interleave low-order words from xmm1 and

xmm2/m128 into xmm1.

PUNPCKLWD xmm1, xmm2/m128

NP 0F 62 /r¹

V/V

MMX

Interleave low-order doublewords from mm

and mm/m32 into mm.

PUNPCKLDQ mm, mm/m32

66 0F 62 /r

V/V

SSE2

Interleave low-order doublewords from xmm1

and xmm2/m128 into xmm1.

PUNPCKLDQ xmm1, xmm2/m128

66 0F 6C /r

V/V

SSE2

Interleave low-order quadword from xmm1

and xmm2/m128 into xmm1 register.

PUNPCKLQDQ xmm1, xmm2/m128

VEX.128.66.0F.WIG 60/r

V/V

AVX

Interleave low-order bytes from xmm2 and

xmm3/m128 into xmm1.

VPUNPCKLBW xmm1,xmm2, xmm3/m128

VEX.128.66.0F.WIG 61/r

V/V

AVX

Interleave low-order words from xmm2 and

xmm3/m128 into xmm1.

VPUNPCKLWD xmm1,xmm2, xmm3/m128

VEX.128.66.0F.WIG 62/r

V/V

AVX

Interleave low-order doublewords from xmm2

and xmm3/m128 into xmm1.

VPUNPCKLDQ xmm1, xmm2, xmm3/m128

VEX.128.66.0F.WIG 6C/r

V/V

AVX

Interleave low-order quadword from xmm2

and xmm3/m128 into xmm1 register.

VPUNPCKLQDQ xmm1, xmm2, xmm3/m128

VEX.256.66.0F.WIG 60 /r

V/V

AVX2

Interleave low-order bytes from ymm2 and

ymm3/m256 into ymm1 register.

VPUNPCKLBW ymm1, ymm2, ymm3/m256

VEX.256.66.0F.WIG 61 /r

V/V

AVX2

Interleave low-order words from ymm2 and

ymm3/m256 into ymm1 register.

VPUNPCKLWD ymm1, ymm2, ymm3/m256

VEX.256.66.0F.WIG 62 /r

V/V

AVX2

Interleave low-order doublewords from ymm2

and ymm3/m256 into ymm1 register.

VPUNPCKLDQ ymm1, ymm2, ymm3/m256

VEX.256.66.0F.WIG 6C /r

V/V

AVX2

Interleave low-order quadword from ymm2

and ymm3/m256 into ymm1 register.

VPUNPCKLQDQ ymm1, ymm2, ymm3/m256

EVEX.128.66.0F.WIG 60 /r

V/V

AVX512VL

Interleave low-order bytes from xmm2 and

VPUNPCKLBW xmm1 {k1}{z}, xmm2, xmm3/m128

AVX512BW

xmm3/m128 into xmm1 register subject to

write mask k1.

EVEX.128.66.0F.WIG 61 /r

V/V

AVX512VL

Interleave low-order words from xmm2 and

VPUNPCKLWD xmm1 {k1}{z}, xmm2, xmm3/m128

AVX512BW

xmm3/m128 into xmm1 register subject to

write mask k1.

EVEX.128.66.0F.W0 62 /r

V/V

AVX512VL

Interleave low-order doublewords from xmm2

VPUNPCKLDQ xmm1 {k1}{z}, xmm2,

AVX512F

and xmm3/m128/m32bcst into xmm1

xmm3/m128/m32bcst

EVEX.128.66.0F.W1 6C /r

V/V

AVX512VL

Interleave low-order quadword from zmm2

VPUNPCKLQDQ xmm1 {k1}{z}, xmm2,

AVX512F

and zmm3/m512/m64bcst into zmm1

xmm3/m128/m64bcst

PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ—Unpack Low Data

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INSTRUCTION SET REFERENCE, M-U

EVEX.256.66.0F.WIG 60 /r

V/V

AVX512VL

Interleave low-order bytes from ymm2 and

VPUNPCKLBW ymm1 {k1}{z}, ymm2, ymm3/m256

AVX512BW

ymm3/m256 into ymm1 register subject to

write mask k1.

EVEX.256.66.0F.WIG 61 /r

V/V

AVX512VL

Interleave low-order words from ymm2 and

VPUNPCKLWD ymm1 {k1}{z}, ymm2, ymm3/m256

AVX512BW

ymm3/m256 into ymm1 register subject to

write mask k1.

EVEX.256.66.0F.W0 62 /r

V/V

AVX512VL

Interleave low-order doublewords from ymm2

VPUNPCKLDQ ymm1 {k1}{z}, ymm2,

AVX512F

and ymm3/m256/m32bcst into ymm1

ymm3/m256/m32bcst

EVEX.256.66.0F.W1 6C /r

V/V

AVX512VL

Interleave low-order quadword from ymm2

VPUNPCKLQDQ ymm1 {k1}{z}, ymm2,

AVX512F

and ymm3/m256/m64bcst into ymm1

ymm3/m256/m64bcst

EVEX.512.66.0F.WIG 60/r

V/V

AVX512BW

Interleave low-order bytes from zmm2 and

VPUNPCKLBW zmm1 {k1}{z}, zmm2, zmm3/m512

zmm3/m512 into zmm1 register subject to

write mask k1.

EVEX.512.66.0F.WIG 61/r

V/V

AVX512BW

Interleave low-order words from zmm2 and

VPUNPCKLWD zmm1 {k1}{z}, zmm2, zmm3/m512

zmm3/m512 into zmm1 register subject to

write mask k1.

EVEX.512.66.0F.W0 62 /r

V/V

AVX512F

Interleave low-order doublewords from zmm2

VPUNPCKLDQ zmm1 {k1}{z}, zmm2,

and zmm3/m512/m32bcst into zmm1

zmm3/m512/m32bcst

EVEX.512.66.0F.W1 6C /r

V/V

AVX512F

Interleave low-order quadword from zmm2

VPUNPCKLQDQ zmm1 {k1}{z}, zmm2,

and zmm3/m512/m64bcst into zmm1

zmm3/m512/m64bcst

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2A and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Reg-

isters” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full Mem

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Unpacks and interleaves the low-order data elements (bytes, words, doublewords, and quadwords) of the destina-

tion operand (first operand) and source operand (second operand) into the destination operand. (Figure 4-22

shows the unpack operation for bytes in 64-bit operands.). The high-order data elements are ignored.

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INSTRUCTION SET REFERENCE, M-U

SRC

DEST

Figure 4-22. PUNPCKLBW Instruction Operation Using 64-bit Operands

255

SRC

255

DEST

Figure 4-23. 256-bit VPUNPCKLDQ Instruction Operation

When the source data comes from a 128-bit memory operand, an implementation may fetch only the appropriate

64 bits; however, alignment to a 16-byte boundary and normal segment checking will still be enforced.

The (V)PUNPCKLBW instruction interleaves the low-order bytes of the source and destination operands, the

(V)PUNPCKLWD instruction interleaves the low-order words of the source and destination operands, the

(V)PUNPCKLDQ instruction interleaves the low-order doubleword (or doublewords) of the source and destination

operands, and the (V)PUNPCKLQDQ instruction interleaves the low-order quadwords of the source and destination

operands.

These instructions can be used to convert bytes to words, words to doublewords, doublewords to quadwords, and

quadwords to double quadwords, respectively, by placing all 0s in the source operand. Here, if the source operand

contains all 0s, the result (stored in the destination operand) contains zero extensions of the high-order data

elements from the original value in the destination operand. For example, with the (V)PUNPCKLBW instruction the

high-order bytes are zero extended (that is, unpacked into unsigned word integers), and with the (V)PUNPCKLWD

instruction, the high-order words are zero extended (unpacked into unsigned doubleword integers).

In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to

access additional registers (XMM8-XMM15).

Legacy SSE versions 64-bit operand: The source operand can be an MMX technology register or a 32-bit memory

location. The destination operand is an MMX technology register.

128-bit Legacy SSE versions: The second source operand is an XMM register or a 128-bit memory location. The

first source operand and destination operands are XMM registers. Bits (MAXVL-1:128) of the corresponding YMM

destination register remain unchanged.

VEX.128 encoded versions: The second source operand is an XMM register or a 128-bit memory location. The first

source operand and destination operands are XMM registers. Bits (MAXVL-1:128) of the destination YMM register

are zeroed.

VEX.256 encoded version: The second source operand is an YMM register or an 256-bit memory location. The first

source operand and destination operands are YMM registers. Bits (MAXVL-1:256) of the corresponding ZMM

PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ—Unpack Low Data

Vol. 2B

4-513

INSTRUCTION SET REFERENCE, M-U

EVEX encoded VPUNPCKLDQ/QDQ: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit

memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The first source

operand and destination operands are ZMM/YMM/XMM registers. The destination is conditionally updated with

writemask k1.

EVEX encoded VPUNPCKLWD/BW: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit

memory location. The first source operand and destination operands are ZMM/YMM/XMM registers. The destination

is conditionally updated with writemask k1.

Operation

PUNPCKLBW instruction with 64-bit operands:

DEST[63:56] := SRC[31:24];

DEST[55:48] := DEST[31:24];

DEST[47:40] := SRC[23:16];

DEST[39:32] := DEST[23:16];

DEST[31:24] := SRC[15:8];

DEST[23:16] := DEST[15:8];

DEST[15:8] := SRC[7:0];

DEST[7:0] := DEST[7:0];

PUNPCKLWD instruction with 64-bit operands:

DEST[63:48] := SRC[31:16];

DEST[47:32] := DEST[31:16];

DEST[31:16] := SRC[15:0];

DEST[15:0] := DEST[15:0];

PUNPCKLDQ instruction with 64-bit operands:

DEST[63:32] := SRC[31:0];

DEST[31:0] := DEST[31:0];

INTERLEAVE_BYTES_512b (SRC1, SRC2)

TMP_DEST[255:0] := INTERLEAVE_BYTES_256b(SRC1[255:0], SRC[255:0])

TMP_DEST[511:256] := INTERLEAVE_BYTES_256b(SRC1[511:256], SRC[511:256])

INTERLEAVE_BYTES_256b (SRC1, SRC2)

DEST[7:0] := SRC1[7:0]

DEST[15:8] := SRC2[7:0]

DEST[23:16] := SRC1[15:8]

DEST[31:24] := SRC2[15:8]

DEST[39:32] := SRC1[23:16]

DEST[47:40] := SRC2[23:16]

DEST[55:48] := SRC1[31:24]

DEST[63:56] := SRC2[31:24]

DEST[71:64] := SRC1[39:32]

DEST[79:72] := SRC2[39:32]

DEST[87:80] := SRC1[47:40]

DEST[95:88] := SRC2[47:40]

DEST[103:96] := SRC1[55:48]

DEST[111:104] := SRC2[55:48]

DEST[119:112] := SRC1[63:56]

DEST[127:120] := SRC2[63:56]

DEST[135:128] := SRC1[135:128]

DEST[143:136] := SRC2[135:128]

DEST[151:144] := SRC1[143:136]

DEST[159:152] := SRC2[143:136]

DEST[167:160] := SRC1[151:144]

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INSTRUCTION SET REFERENCE, M-U

DEST[175:168] := SRC2[151:144]

DEST[183:176] := SRC1[159:152]

DEST[191:184] := SRC2[159:152]

DEST[199:192] := SRC1[167:160]

DEST[207:200] := SRC2[167:160]

DEST[215:208] := SRC1[175:168]

DEST[223:216] := SRC2[175:168]

DEST[231:224] := SRC1[183:176]

DEST[239:232] := SRC2[183:176]

DEST[247:240] := SRC1[191:184]

DEST[255:248] := SRC2[191:184]

INTERLEAVE_BYTES (SRC1, SRC2)

DEST[7:0] := SRC1[7:0]

DEST[15:8] := SRC2[7:0]

DEST[23:16] := SRC1[15:8]

DEST[31:24] := SRC2[15:8]

DEST[39:32] := SRC1[23:16]

DEST[47:40] := SRC2[23:16]

DEST[55:48] := SRC1[31:24]

DEST[63:56] := SRC2[31:24]

DEST[71:64] := SRC1[39:32]

DEST[79:72] := SRC2[39:32]

DEST[87:80] := SRC1[47:40]

DEST[95:88] := SRC2[47:40]

DEST[103:96] := SRC1[55:48]

DEST[111:104] := SRC2[55:48]

DEST[119:112] := SRC1[63:56]

DEST[127:120] := SRC2[63:56]

INTERLEAVE_WORDS_512b (SRC1, SRC2)

TMP_DEST[255:0] := INTERLEAVE_WORDS_256b(SRC1[255:0], SRC[255:0])

TMP_DEST[511:256] := INTERLEAVE_WORDS_256b(SRC1[511:256], SRC[511:256])

INTERLEAVE_WORDS_256b(SRC1, SRC2)

DEST[15:0] := SRC1[15:0]

DEST[31:16] := SRC2[15:0]

DEST[47:32] := SRC1[31:16]

DEST[63:48] := SRC2[31:16]

DEST[79:64] := SRC1[47:32]

DEST[95:80] := SRC2[47:32]

DEST[111:96] := SRC1[63:48]

DEST[127:112] := SRC2[63:48]

DEST[143:128] := SRC1[143:128]

DEST[159:144] := SRC2[143:128]

DEST[175:160] := SRC1[159:144]

DEST[191:176] := SRC2[159:144]

DEST[207:192] := SRC1[175:160]

DEST[223:208] := SRC2[175:160]

DEST[239:224] := SRC1[191:176]

DEST[255:240] := SRC2[191:176]

INTERLEAVE_WORDS (SRC1, SRC2)

DEST[15:0] := SRC1[15:0]

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INSTRUCTION SET REFERENCE, M-U

DEST[31:16] := SRC2[15:0]

DEST[47:32] := SRC1[31:16]

DEST[63:48] := SRC2[31:16]

DEST[79:64] := SRC1[47:32]

DEST[95:80] := SRC2[47:32]

DEST[111:96] := SRC1[63:48]

DEST[127:112] := SRC2[63:48]

INTERLEAVE_DWORDS_512b (SRC1, SRC2)

TMP_DEST[255:0] := INTERLEAVE_DWORDS_256b(SRC1[255:0], SRC2[255:0])

TMP_DEST[511:256] := INTERLEAVE_DWORDS_256b(SRC1[511:256], SRC2[511:256])

INTERLEAVE_DWORDS_256b(SRC1, SRC2)

DEST[31:0] := SRC1[31:0]

DEST[63:32] := SRC2[31:0]

DEST[95:64] := SRC1[63:32]

DEST[127:96] := SRC2[63:32]

DEST[159:128] := SRC1[159:128]

DEST[191:160] := SRC2[159:128]

DEST[223:192] := SRC1[191:160]

DEST[255:224] := SRC2[191:160]

INTERLEAVE_DWORDS(SRC1, SRC2)

DEST[31:0] := SRC1[31:0]

DEST[63:32] := SRC2[31:0]

DEST[95:64] := SRC1[63:32]

DEST[127:96] := SRC2[63:32]

INTERLEAVE_QWORDS_512b (SRC1, SRC2)

TMP_DEST[255:0] := INTERLEAVE_QWORDS_256b(SRC1[255:0], SRC2[255:0])

TMP_DEST[511:256] := INTERLEAVE_QWORDS_256b(SRC1[511:256], SRC2[511:256])

INTERLEAVE_QWORDS_256b(SRC1, SRC2)

DEST[63:0] := SRC1[63:0]

DEST[127:64] := SRC2[63:0]

DEST[191:128] := SRC1[191:128]

DEST[255:192] := SRC2[191:128]

INTERLEAVE_QWORDS(SRC1, SRC2)

DEST[63:0] := SRC1[63:0]

DEST[127:64] := SRC2[63:0]

PUNPCKLBW

DEST[127:0] := INTERLEAVE_BYTES(DEST, SRC)

DEST[255:127] (Unmodified)

VPUNPCKLBW (VEX.128 encoded instruction)

DEST[127:0] := INTERLEAVE_BYTES(SRC1, SRC2)

DEST[MAXVL-1:127] := 0

VPUNPCKLBW (VEX.256 encoded instruction)

DEST[255:0] := INTERLEAVE_BYTES_256b(SRC1, SRC2)

DEST[MAXVL-1:256] := 0

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Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 86