Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023)

INSTRUCTION SET REFERENCE, M-U

PSADBW—Compute Sum of Absolute Differences

Opcode/

Op/

64/32 bit

CPUID Feature

Description

Instruction

Mode

Flag

Support

NP 0F F6 /r¹

V/V

SSE

Computes the absolute differences of the

packed unsigned byte integers from mm2

PSADBW mm1, mm2/m64

/m64 and mm1; differences are then summed

to produce an unsigned word integer result.

66 0F F6 /r

V/V

SSE2

Computes the absolute differences of the

packed unsigned byte integers from xmm2

PSADBW xmm1, xmm2/m128

/m128 and xmm1; the 8 low differences and 8

high differences are then summed separately

to produce two unsigned word integer results.

VEX.128.66.0F.WIG F6 /r

V/V

AVX

Computes the absolute differences of the

packed unsigned byte integers from xmm3

VPSADBW xmm1, xmm2, xmm3/m128

/m128 and xmm2; the 8 low differences and 8

high differences are then summed separately

to produce two unsigned word integer results.

VEX.256.66.0F.WIG F6 /r

V/V

AVX2

Computes the absolute differences of the

packed unsigned byte integers from ymm3

VPSADBW ymm1, ymm2, ymm3/m256

/m256 and ymm2; then each consecutive 8

differences are summed separately to produce

four unsigned word integer results.

EVEX.128.66.0F.WIG F6 /r

V/V

AVX512VL

Computes the absolute differences of the

VPSADBW xmm1, xmm2, xmm3/m128

AVX512BW

packed unsigned byte integers from xmm3

/m128 and xmm2; then each consecutive 8

differences are summed separately to produce

two unsigned word integer results.

EVEX.256.66.0F.WIG F6 /r

V/V

AVX512VL

Computes the absolute differences of the

VPSADBW ymm1, ymm2, ymm3/m256

AVX512BW

packed unsigned byte integers from ymm3

/m256 and ymm2; then each consecutive 8

differences are summed separately to produce

four unsigned word integer results.

EVEX.512.66.0F.WIG F6 /r

V/V

AVX512BW

Computes the absolute differences of the

VPSADBW zmm1, zmm2, zmm3/m512

packed unsigned byte integers from zmm3

/m512 and zmm2; then each consecutive 8

differences are summed separately to produce

eight unsigned word integer results.

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2A and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX

Registers” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full Mem

ModRM:reg (w)

EVEX.vvvv

ModRM:r/m (r)

N/A

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PSADBW—Compute Sum of Absolute Differences

INSTRUCTION SET REFERENCE, M-U

Description

Computes the absolute value of the difference of 8 unsigned byte integers from the source operand (second

operand) and from the destination operand (first operand). These 8 differences are then summed to produce an

unsigned word integer result that is stored in the destination operand. Figure 4-14 shows the operation of the

PSADBW instruction when using 64-bit operands.

When operating on 64-bit operands, the word integer result is stored in the low word of the destination operand,

and the remaining bytes in the destination operand are cleared to all 0s.

When operating on 128-bit operands, two packed results are computed. Here, the 8 low-order bytes of the source

and destination operands are operated on to produce a word result that is stored in the low word of the destination

operand, and the 8 high-order bytes are operated on to produce a word result that is stored in bits 64 through 79

of the destination operand. The remaining bytes of the destination operand are cleared.

For 256-bit version, the third group of 8 differences are summed to produce an unsigned word in bits[143:128] of

the destination register and the fourth group of 8 differences are summed to produce an unsigned word in

bits[207:192] of the destination register. The remaining words of the destination are set to 0.

For 512-bit version, the fifth group result is stored in bits [271:256] of the destination. The result from the sixth

group is stored in bits [335:320]. The results for the seventh and eighth group are stored respectively in bits

[399:384] and bits [463:447], respectively. The remaining bits in the destination are set to 0.

In 64-bit mode and not encoded by VEX/EVEX prefix, using a REX prefix in the form of REX.R permits this instruc-

tion to access additional registers (XMM8-XMM15).

Legacy SSE version: The source operand can be an MMX technology register or a 64-bit memory location. The

destination operand is an MMX technology register.

128-bit Legacy SSE version: The first source operand and destination register are XMM registers. The second

source operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding ZMM

destination register remain unchanged.

VEX.128 and EVEX.128 encoded versions: The first source operand and destination register are XMM registers. The

second source operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding

ZMM register are zeroed.

VEX.256 and EVEX.256 encoded versions: The first source operand and destination register are YMM registers. The

second source operand is an YMM register or a 256-bit memory location. Bits (MAXVL-1:256) of the corresponding

ZMM register are zeroed.

EVEX.512 encoded version: The first source operand and destination register are ZMM registers. The second

source operand is a ZMM register or a 512-bit memory location.

SRC

DEST

TEMP

ABS(X7:Y7)

ABS(X6:Y6)

ABS(X5:Y5)

ABS(X4:Y4)

ABS(X3:Y3)

ABS(X2:Y2)

ABS(X1:Y1)

ABS(X0:Y0)

DEST

00H

SUM(TEMP7...TEMP0)

Figure 4-14. PSADBW Instruction Operation Using 64-bit Operands

PSADBW—Compute Sum of Absolute Differences

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INSTRUCTION SET REFERENCE, M-U

Operation

VPSADBW (EVEX encoded versions)

VL = 128, 256, 512

TEMP0 := ABS(SRC1[7:0] - SRC2[7:0])

(* Repeat operation for bytes 1 through 15 *)

TEMP15 := ABS(SRC1[127:120] - SRC2[127:120])

DEST[15:0] := SUM(TEMP0:TEMP7)

DEST[63:16] := 000000000000H

DEST[79:64] := SUM(TEMP8:TEMP15)

DEST[127:80] := 00000000000H

IF VL >= 256

(* Repeat operation for bytes 16 through 31*)

TEMP31 := ABS(SRC1[255:248] - SRC2[255:248])

DEST[143:128] := SUM(TEMP16:TEMP23)

DEST[191:144] := 000000000000H

DEST[207:192] := SUM(TEMP24:TEMP31)

DEST[223:208] := 00000000000H

FI;

IF VL >= 512

(* Repeat operation for bytes 32 through 63*)

TEMP63 := ABS(SRC1[511:504] - SRC2[511:504])

DEST[271:256] := SUM(TEMP0:TEMP7)

DEST[319:272] := 000000000000H

DEST[335:320] := SUM(TEMP8:TEMP15)

DEST[383:336] := 00000000000H

DEST[399:384] := SUM(TEMP16:TEMP23)

DEST[447:400] := 000000000000H

DEST[463:448] := SUM(TEMP24:TEMP31)

DEST[511:464] := 00000000000H

FI;

DEST[MAXVL-1:VL] := 0

VPSADBW (VEX.256 encoded version)

TEMP0 := ABS(SRC1[7:0] - SRC2[7:0])

(* Repeat operation for bytes 2 through 30*)

TEMP31 := ABS(SRC1[255:248] - SRC2[255:248])

DEST[15:0] := SUM(TEMP0:TEMP7)

DEST[63:16] := 000000000000H

DEST[79:64] := SUM(TEMP8:TEMP15)

DEST[127:80] := 00000000000H

DEST[143:128] := SUM(TEMP16:TEMP23)

DEST[191:144] := 000000000000H

DEST[207:192] := SUM(TEMP24:TEMP31)

DEST[223:208] := 00000000000H

DEST[MAXVL-1:256] := 0

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PSADBW—Compute Sum of Absolute Differences

INSTRUCTION SET REFERENCE, M-U

VPSADBW (VEX.128 encoded version)

TEMP0 := ABS(SRC1[7:0] - SRC2[7:0])

(* Repeat operation for bytes 2 through 14 *)

TEMP15 := ABS(SRC1[127:120] - SRC2[127:120])

DEST[15:0] := SUM(TEMP0:TEMP7)

DEST[63:16] := 000000000000H

DEST[79:64] := SUM(TEMP8:TEMP15)

DEST[127:80] := 00000000000H

DEST[MAXVL-1:128] := 0

PSADBW (128-bit Legacy SSE version)

TEMP0 := ABS(DEST[7:0] - SRC[7:0])

(* Repeat operation for bytes 2 through 14 *)

TEMP15 := ABS(DEST[127:120] - SRC[127:120])

DEST[15:0] := SUM(TEMP0:TEMP7)

DEST[63:16] := 000000000000H

DEST[79:64] := SUM(TEMP8:TEMP15)

DEST[127:80] := 00000000000

DEST[MAXVL-1:128] (Unmodified)

PSADBW (64-bit operand)

TEMP0 := ABS(DEST[7:0] - SRC[7:0])

(* Repeat operation for bytes 2 through 6 *)

TEMP7 := ABS(DEST[63:56] - SRC[63:56])

DEST[15:0] := SUM(TEMP0:TEMP7)

DEST[63:16] := 000000000000H

Intel C/C++ Compiler Intrinsic Equivalent

VPSADBW __m512i _mm512_sad_epu8( __m512i a, __m512i b)

PSADBW:__m64 _mm_sad_pu8(__m64 a,__m64 b)

(V)PSADBW:__m128i _mm_sad_epu8(__m128i a, __m128i b)

VPSADBW:__m256i _mm256_sad_epu8( __m256i a, __m256i b)

Flags Affected

None.

SIMD Floating-Point Exceptions

None.

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions”.

EVEX-encoded instruction, see Exceptions Type E4NF.nb in Table 2-50, “Type E4NF Class Exception Conditions”.

PSADBW—Compute Sum of Absolute Differences

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INSTRUCTION SET REFERENCE, M-U

PSHUFB—Packed Shuffle Bytes

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

NP 0F 38 00 /r¹

V/V

SSSE3

Shuffle bytes in mm1 according to contents of

mm2/m64.

PSHUFB mm1, mm2/m64

66 0F 38 00 /r

V/V

SSSE3

Shuffle bytes in xmm1 according to contents of

xmm2/m128.

PSHUFB xmm1, xmm2/m128

VEX.128.66.0F38.WIG 00 /r

V/V

AVX

Shuffle bytes in xmm2 according to contents of

xmm3/m128.

VPSHUFB xmm1, xmm2, xmm3/m128

VEX.256.66.0F38.WIG 00 /r

V/V

AVX2

Shuffle bytes in ymm2 according to contents of

ymm3/m256.

VPSHUFB ymm1, ymm2, ymm3/m256

EVEX.128.66.0F38.WIG 00 /r

V/V

AVX512VL

Shuffle bytes in xmm2 according to contents of

VPSHUFB xmm1 {k1}{z}, xmm2, xmm3/m128

AVX512BW

xmm3/m128 under write mask k1.

EVEX.256.66.0F38.WIG 00 /r

V/V

AVX512VL

Shuffle bytes in ymm2 according to contents of

VPSHUFB ymm1 {k1}{z}, ymm2, ymm3/m256

AVX512BW

ymm3/m256 under write mask k1.

EVEX.512.66.0F38.WIG 00 /r

V/V

AVX512BW

Shuffle bytes in zmm2 according to contents of

VPSHUFB zmm1 {k1}{z}, zmm2, zmm3/m512

zmm3/m512 under write mask k1.

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2A and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Reg-

isters” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full Mem

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

PSHUFB performs in-place shuffles of bytes in the destination operand (the first operand) according to the shuffle

control mask in the source operand (the second operand). The instruction permutes the data in the destination

operand, leaving the shuffle mask unaffected. If the most significant bit (bit[7]) of each byte of the shuffle control

mask is set, then constant zero is written in the result byte. Each byte in the shuffle control mask forms an index

to permute the corresponding byte in the destination operand. The value of each index is the least significant 4 bits

(128-bit operation) or 3 bits (64-bit operation) of the shuffle control byte. When the source operand is a 128-bit

memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will

be generated.

In 64-bit mode and not encoded with VEX/EVEX, use the REX prefix to access XMM8-XMM15 registers.

Legacy SSE version 64-bit operand: Both operands can be MMX registers.

128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAXVL-

1:128) of the corresponding YMM destination register remain unchanged.

VEX.128 encoded version: The destination operand is the first operand, the first source operand is the second

operand, the second source operand is the third operand. Bits (MAXVL-1:128) of the destination YMM register are

zeroed.

VEX.256 encoded version: Bits (255:128) of the destination YMM register stores the 16-byte shuffle result of the

upper 16 bytes of the first source operand, using the upper 16-bytes of the second source operand as control mask.

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PSHUFB—Packed Shuffle Bytes

INSTRUCTION SET REFERENCE, M-U

The value of each index is for the high 128-bit lane is the least significant 4 bits of the respective shuffle control

byte. The index value selects a source data element within each 128-bit lane.

EVEX encoded version: The second source operand is an ZMM/YMM/XMM register or an 512/256/128-bit memory

location. The first source operand and destination operands are ZMM/YMM/XMM registers. The destination is condi-

tionally updated with writemask k1.

EVEX and VEX encoded version: Four/two in-lane 128-bit shuffles.

Operation

PSHUFB (with 64 bit operands)

TEMP := DEST

for i = 0 to 7 {

if (SRC[(i * 8)+7] = 1 ) then

DEST[(i*8)+7...(i*8)+0] := 0;

else

index[2..0] := SRC[(i*8)+2 .. (i*8)+0];

DEST[(i*8)+7...(i*8)+0] := TEMP[(index*8+7)..(index*8+0)];

endif;

}

PSHUFB (with 128 bit operands)

TEMP := DEST

for i = 0 to 15 {

if (SRC[(i * 8)+7] = 1 ) then

DEST[(i*8)+7..(i*8)+0] := 0;

else

index[3..0] := SRC[(i*8)+3 .. (i*8)+0];

DEST[(i*8)+7..(i*8)+0] := TEMP[(index*8+7)..(index*8+0)];

endif

}

VPSHUFB (VEX.128 encoded version)

for i = 0 to 15 {

if (SRC2[(i * 8)+7] = 1) then

DEST[(i*8)+7..(i*8)+0] := 0;

else

index[3..0] := SRC2[(i*8)+3 .. (i*8)+0];

DEST[(i*8)+7..(i*8)+0] := SRC1[(index*8+7)..(index*8+0)];

endif

}

DEST[MAXVL-1:128] := 0

VPSHUFB (VEX.256 encoded version)

for i = 0 to 15 {

if (SRC2[(i * 8)+7] == 1 ) then

DEST[(i*8)+7..(i*8)+0] := 0;

else

index[3..0] := SRC2[(i*8)+3 .. (i*8)+0];

DEST[(i*8)+7..(i*8)+0] := SRC1[(index*8+7)..(index*8+0)];

endif

if (SRC2[128 + (i * 8)+7] == 1 ) then

DEST[128 + (i*8)+7..(i*8)+0] := 0;

else

index[3..0] := SRC2[128 + (i*8)+3 .. (i*8)+0];

DEST[128 + (i*8)+7..(i*8)+0] := SRC1[128 + (index*8+7)..(index*8+0)];

PSHUFB—Packed Shuffle Bytes

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4-423

INSTRUCTION SET REFERENCE, M-U

endif

}

VPSHUFB (EVEX encoded versions)

(KL, VL) = (16, 128), (32, 256), (64, 512)

jmask := (KL-1) & ~0xF

// 0x00, 0x10, 0x30 depending on the VL

FOR j = 0 TO KL-1

// dest

IF kl[ i ] or no_masking

index := src.byte[ j ];

IF index & 0x80

Dest.byte[ j ] := 0;

ELSE

index := (index & 0xF) + (j & jmask);

// 16-element in-lane lookup

Dest.byte[ j ] := src.byte[ index ];

ELSE if zeroing

Dest.byte[ j ] := 0;

DEST[MAXVL-1:VL] := 0;

MM2

07H

FFH

80H

01H

00H

MM1

04H

01H

07H

03H

02H

FFH

01H

MM1

04H

00H

FFH

01H

Figure 4-15. PSHUFB with 64-Bit Operands

Intel C/C++ Compiler Intrinsic Equivalent

VPSHUFB __m512i _mm512_shuffle_epi8(__m512i a, __m512i b);

VPSHUFB __m512i _mm512_mask_shuffle_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);

VPSHUFB __m512i _mm512_maskz_shuffle_epi8( __mmask64 k, __m512i a, __m512i b);

VPSHUFB __m256i _mm256_mask_shuffle_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);

VPSHUFB __m256i _mm256_maskz_shuffle_epi8( __mmask32 k, __m256i a, __m256i b);

VPSHUFB __m128i _mm_mask_shuffle_epi8(__m128i s, __mmask16 k, __m128i a, __m128i b);

VPSHUFB __m128i _mm_maskz_shuffle_epi8( __mmask16 k, __m128i a, __m128i b);

PSHUFB: __m64 _mm_shuffle_pi8 (__m64 a, __m64 b)

(V)PSHUFB: __m128i _mm_shuffle_epi8 (__m128i a, __m128i b)

VPSHUFB:__m256i _mm256_shuffle_epi8(__m256i a, __m256i b)

SIMD Floating-Point Exceptions

None.

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PSHUFB—Packed Shuffle Bytes

INSTRUCTION SET REFERENCE, M-U

PSHUFD—Shuffle Packed Doublewords

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

66 0F 70 /r ib

V/V

SSE2

Shuffle the doublewords in xmm2/m128 based on

the encoding in imm8 and store the result in xmm1.

PSHUFD xmm1, xmm2/m128, imm8

VEX.128.66.0F.WIG 70 /r ib

V/V

AVX

Shuffle the doublewords in xmm2/m128 based on

the encoding in imm8 and store the result in xmm1.

VPSHUFD xmm1, xmm2/m128, imm8

VEX.256.66.0F.WIG 70 /r ib

V/V

AVX2

Shuffle the doublewords in ymm2/m256 based on

the encoding in imm8 and store the result in ymm1.

VPSHUFD ymm1, ymm2/m256, imm8

EVEX.128.66.0F.W0 70 /r ib

V/V

AVX512VL

Shuffle the doublewords in xmm2/m128/m32bcst

VPSHUFD xmm1 {k1}{z}, xmm2/m128/m32bcst,

AVX512F

based on the encoding in imm8 and store the result

imm8

in xmm1 using writemask k1.

EVEX.256.66.0F.W0 70 /r ib

V/V

AVX512VL

Shuffle the doublewords in ymm2/m256/m32bcst

VPSHUFD ymm1 {k1}{z}, ymm2/m256/m32bcst,

AVX512F

based on the encoding in imm8 and store the result

imm8

in ymm1 using writemask k1.

EVEX.512.66.0F.W0 70 /r ib

V/V

AVX512F

Shuffle the doublewords in zmm2/m512/m32bcst

VPSHUFD zmm1 {k1}{z}, zmm2/m512/m32bcst,

based on the encoding in imm8 and store the result

imm8

in zmm1 using writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

imm8

N/A

Full

ModRM:reg (w)

ModRM:r/m (r)

imm8

N/A

Description

Copies doublewords from source operand (second operand) and inserts them in the destination operand (first

operand) at the locations selected with the order operand (third operand). Figure 4-16 shows the operation of the

256-bit VPSHUFD instruction and the encoding of the order operand. Each 2-bit field in the order operand selects

the contents of one doubleword location within a 128-bit lane and copy to the target element in the destination

operand. For example, bits 0 and 1 of the order operand targets the first doubleword element in the low and high

128-bit lane of the destination operand for 256-bit VPSHUFD. The encoded value of bits 1:0 of the order operand

(see the field encoding in Figure 4-16) determines which doubleword element (from the respective 128-bit lane) of

the source operand will be copied to doubleword 0 of the destination operand.

For 128-bit operation, only the low 128-bit lane are operative. The source operand can be an XMM register or a

128-bit memory location. The destination operand is an XMM register. The order operand is an 8-bit immediate.

Note that this instruction permits a doubleword in the source operand to be copied to more than one doubleword

location in the destination operand.

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PSHUFD—Shuffle Packed Doublewords

INSTRUCTION SET REFERENCE, M-U

SRC

DEST

Encoding

00B - X4

Encoding

00B - X0

of Fields in

01B - X5

ORDER

of Fields in

01B - X1

ORDER

10B - X6

ORDER

10B - X2

Operand

11B - X7

6 5

4 3

Operand

11B - X3

Figure 4-16. 256-bit VPSHUFD Instruction Operation

The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM

operand to be copied to more than one doubleword location in the destination operand.

In 64-bit mode and not encoded in VEX/EVEX, using REX.R permits this instruction to access XMM8-XMM15.

128-bit Legacy SSE version: Bits (MAXVL-1:128) of the corresponding YMM destination register remain

unchanged.

VEX.128 encoded version: The source operand can be an XMM register or a 128-bit memory location. The destina-

tion operand is an XMM register. Bits (MAXVL-1:128) of the corresponding ZMM register are zeroed.

VEX.256 encoded version: The source operand can be an YMM register or a 256-bit memory location. The destina-

tion operand is an YMM register. Bits (MAXVL-1:256) of the corresponding ZMM register are zeroed. Bits (255-

1:128) of the destination stores the shuffled results of the upper 16 bytes of the source operand using the imme-

diate byte as the order operand.

EVEX encoded version: The source operand can be an ZMM/YMM/XMM register, a 512/256/128-bit memory loca-

tion, or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a

ZMM/YMM/XMM register updated according to the writemask.

Each 128-bit lane of the destination stores the shuffled results of the respective lane of the source operand using

the immediate byte as the order operand.

Note: EVEX.vvvv and VEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.

Operation

PSHUFD (128-bit Legacy SSE version)

DEST[31:0] := (SRC >> (ORDER[1:0] * 32))[31:0];

DEST[63:32] := (SRC >> (ORDER[3:2] * 32))[31:0];

DEST[95:64] := (SRC >> (ORDER[5:4] * 32))[31:0];

DEST[127:96] := (SRC >> (ORDER[7:6] * 32))[31:0];

DEST[MAXVL-1:128] (Unmodified)

VPSHUFD (VEX.128 encoded version)

DEST[31:0] := (SRC >> (ORDER[1:0] * 32))[31:0];

DEST[63:32] := (SRC >> (ORDER[3:2] * 32))[31:0];

DEST[95:64] := (SRC >> (ORDER[5:4] * 32))[31:0];

DEST[127:96] := (SRC >> (ORDER[7:6] * 32))[31:0];

DEST[MAXVL-1:128] := 0

PSHUFD—Shuffle Packed Doublewords

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4-427

INSTRUCTION SET REFERENCE, M-U

VPSHUFD (VEX.256 encoded version)

DEST[31:0] := (SRC[127:0] >> (ORDER[1:0] * 32))[31:0];

DEST[63:32] := (SRC[127:0] >> (ORDER[3:2] * 32))[31:0];

DEST[95:64] := (SRC[127:0] >> (ORDER[5:4] * 32))[31:0];

DEST[127:96] := (SRC[127:0] >> (ORDER[7:6] * 32))[31:0];

DEST[159:128] := (SRC[255:128] >> (ORDER[1:0] * 32))[31:0];

DEST[191:160] := (SRC[255:128] >> (ORDER[3:2] * 32))[31:0];

DEST[223:192] := (SRC[255:128] >> (ORDER[5:4] * 32))[31:0];

DEST[255:224] := (SRC[255:128] >> (ORDER[7:6] * 32))[31:0];

DEST[MAXVL-1:256] := 0

VPSHUFD (EVEX encoded versions)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF (EVEX.b = 1) AND (SRC *is memory*)

THEN TMP_SRC[i+31:i] := SRC[31:0]

ELSE TMP_SRC[i+31:i] := SRC[i+31:i]

FI;

ENDFOR;

IF VL >= 128

TMP_DEST[31:0] := (TMP_SRC[127:0] >> (ORDER[1:0] * 32))[31:0];

TMP_DEST[63:32] := (TMP_SRC[127:0] >> (ORDER[3:2] * 32))[31:0];

TMP_DEST[95:64] := (TMP_SRC[127:0] >> (ORDER[5:4] * 32))[31:0];

TMP_DEST[127:96] := (TMP_SRC[127:0] >> (ORDER[7:6] * 32))[31:0];

FI;

IF VL >= 256

TMP_DEST[159:128] := (TMP_SRC[255:128] >> (ORDER[1:0] * 32))[31:0];

TMP_DEST[191:160] := (TMP_SRC[255:128] >> (ORDER[3:2] * 32))[31:0];

TMP_DEST[223:192] := (TMP_SRC[255:128] >> (ORDER[5:4] * 32))[31:0];

TMP_DEST[255:224] := (TMP_SRC[255:128] >> (ORDER[7:6] * 32))[31:0];

FI;

IF VL >= 512

TMP_DEST[287:256] := (TMP_SRC[383:256] >> (ORDER[1:0] * 32))[31:0];

TMP_DEST[319:288] := (TMP_SRC[383:256] >> (ORDER[3:2] * 32))[31:0];

TMP_DEST[351:320] := (TMP_SRC[383:256] >> (ORDER[5:4] * 32))[31:0];

TMP_DEST[383:352] := (TMP_SRC[383:256] >> (ORDER[7:6] * 32))[31:0];

TMP_DEST[415:384] := (TMP_SRC[511:384] >> (ORDER[1:0] * 32))[31:0];

TMP_DEST[447:416] := (TMP_SRC[511:384] >> (ORDER[3:2] * 32))[31:0];

TMP_DEST[479:448] := (TMP_SRC[511:384] >> (ORDER[5:4] * 32))[31:0];

TMP_DEST[511:480] := (TMP_SRC[511:384] >> (ORDER[7:6] * 32))[31:0];

FI;

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] := TMP_DEST[i+31:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

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Vol. 2B

PSHUFD—Shuffle Packed Doublewords

INSTRUCTION SET REFERENCE, M-U

DEST[MAXVL-1:VL] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VPSHUFD __m512i _mm512_shuffle_epi32(__m512i a, int n );

VPSHUFD __m512i _mm512_mask_shuffle_epi32(__m512i s, __mmask16 k, __m512i a, int n );

VPSHUFD __m512i _mm512_maskz_shuffle_epi32( __mmask16 k, __m512i a, int n );

VPSHUFD __m256i _mm256_mask_shuffle_epi32(__m256i s, __mmask8 k, __m256i a, int n );

VPSHUFD __m256i _mm256_maskz_shuffle_epi32( __mmask8 k, __m256i a, int n );

VPSHUFD __m128i _mm_mask_shuffle_epi32(__m128i s, __mmask8 k, __m128i a, int n );

VPSHUFD __m128i _mm_maskz_shuffle_epi32( __mmask8 k, __m128i a, int n );

(V)PSHUFD:__m128i _mm_shuffle_epi32(__m128i a, int n)

VPSHUFD:__m256i _mm256_shuffle_epi32(__m256i a, const int n)

Flags Affected

None.

SIMD Floating-Point Exceptions

None.

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions”.

EVEX-encoded instruction, see Table 2-50, “Type E4NF Class Exception Conditions”.

Additionally:

#UD

If VEX.vvvv ≠ 1111B or EVEX.vvvv ≠ 1111B.

PSHUFD—Shuffle Packed Doublewords

Vol. 2B

4-429

INSTRUCTION SET REFERENCE, M-U

PSHUFHW—Shuffle Packed High Words

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

F3 0F 70 /r ib

V/V

SSE2

Shuffle the high words in xmm2/m128 based

on the encoding in imm8 and store the result in

PSHUFHW xmm1, xmm2/m128, imm8

xmm1.

VEX.128.F3.0F.WIG 70 /r ib

V/V

AVX

Shuffle the high words in xmm2/m128 based

on the encoding in imm8 and store the result in

VPSHUFHW xmm1, xmm2/m128, imm8

xmm1.

VEX.256.F3.0F.WIG 70 /r ib

V/V

AVX2

Shuffle the high words in ymm2/m256 based

on the encoding in imm8 and store the result in

VPSHUFHW ymm1, ymm2/m256, imm8

ymm1.

EVEX.128.F3.0F.WIG 70 /r ib

V/V

AVX512VL

Shuffle the high words in xmm2/m128 based

VPSHUFHW xmm1 {k1}{z}, xmm2/m128, imm8

AVX512BW

on the encoding in imm8 and store the result in

xmm1 under write mask k1.

EVEX.256.F3.0F.WIG 70 /r ib

V/V

AVX512VL

Shuffle the high words in ymm2/m256 based

VPSHUFHW ymm1 {k1}{z}, ymm2/m256, imm8

AVX512BW

on the encoding in imm8 and store the result in

ymm1 under write mask k1.

EVEX.512.F3.0F.WIG 70 /r ib

V/V

AVX512BW

Shuffle the high words in zmm2/m512 based

VPSHUFHW zmm1 {k1}{z}, zmm2/m512, imm8

on the encoding in imm8 and store the result in

zmm1 under write mask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

imm8

N/A

Full Mem

ModRM:reg (w)

ModRM:r/m (r)

imm8

N/A

Description

Copies words from the high quadword of a 128-bit lane of the source operand and inserts them in the high quad-

word of the destination operand at word locations (of the respective lane) selected with the immediate operand.

This 256-bit operation is similar to the in-lane operation used by the 256-bit VPSHUFD instruction, which is illus-

trated in Figure 4-16. For 128-bit operation, only the low 128-bit lane is operative. Each 2-bit field in the immediate

operand selects the contents of one word location in the high quadword of the destination operand. The binary

encodings of the immediate operand fields select words (0, 1, 2 or 3, 4) from the high quadword of the source

operand to be copied to the destination operand. The low quadword of the source operand is copied to the low

quadword of the destination operand, for each 128-bit lane.

Note that this instruction permits a word in the high quadword of the source operand to be copied to more than one

word location in the high quadword of the destination operand.

In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to

access additional registers (XMM8-XMM15).

128-bit Legacy SSE version: The destination operand is an XMM register. The source operand can be an XMM

unchanged.

VEX.128 encoded version: The destination operand is an XMM register. The source operand can be an XMM register

or a 128-bit memory location. Bits (MAXVL-1:128) of the destination YMM register are zeroed. VEX.vvvv is

reserved and must be 1111b, VEX.L must be 0, otherwise the instruction will #UD.

VEX.256 encoded version: The destination operand is an YMM register. The source operand can be an YMM register

or a 256-bit memory location.

4-430

Vol. 2B

PSHUFHW—Shuffle Packed High Words

INSTRUCTION SET REFERENCE, M-U

EVEX encoded version: The destination operand is a ZMM/YMM/XMM registers. The source operand can be a

ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination is updated according to the

writemask.

Note: In VEX encoded versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Operation

PSHUFHW (128-bit Legacy SSE version)

DEST[63:0] := SRC[63:0]

DEST[79:64] := (SRC >> (imm[1:0] *16))[79:64]

DEST[95:80] := (SRC >> (imm[3:2] * 16))[79:64]

DEST[111:96] := (SRC >> (imm[5:4] * 16))[79:64]

DEST[127:112] := (SRC >> (imm[7:6] * 16))[79:64]

DEST[MAXVL-1:128] (Unmodified)

VPSHUFHW (VEX.128 encoded version)

DEST[63:0] := SRC1[63:0]

DEST[79:64] := (SRC1 >> (imm[1:0] *16))[79:64]

DEST[95:80] := (SRC1 >> (imm[3:2] * 16))[79:64]

DEST[111:96] := (SRC1 >> (imm[5:4] * 16))[79:64]

DEST[127:112] := (SRC1 >> (imm[7:6] * 16))[79:64]

DEST[MAXVL-1:128] := 0

VPSHUFHW (VEX.256 encoded version)

DEST[63:0] := SRC1[63:0]

DEST[79:64] := (SRC1 >> (imm[1:0] *16))[79:64]

DEST[95:80] := (SRC1 >> (imm[3:2] * 16))[79:64]

DEST[111:96] := (SRC1 >> (imm[5:4] * 16))[79:64]

DEST[127:112] := (SRC1 >> (imm[7:6] * 16))[79:64]

DEST[191:128] := SRC1[191:128]

DEST[207192] := (SRC1 >> (imm[1:0] *16))[207:192]

DEST[223:208] := (SRC1 >> (imm[3:2] * 16))[207:192]

DEST[239:224] := (SRC1 >> (imm[5:4] * 16))[207:192]

DEST[255:240] := (SRC1 >> (imm[7:6] * 16))[207:192]

DEST[MAXVL-1:256] := 0

VPSHUFHW (EVEX encoded versions)

(KL, VL) = (8, 128), (16, 256), (32, 512)

IF VL >= 128

TMP_DEST[63:0] := SRC1[63:0]

TMP_DEST[79:64] := (SRC1 >> (imm[1:0] *16))[79:64]

TMP_DEST[95:80] := (SRC1 >> (imm[3:2] * 16))[79:64]

TMP_DEST[111:96] := (SRC1 >> (imm[5:4] * 16))[79:64]

TMP_DEST[127:112] := (SRC1 >> (imm[7:6] * 16))[79:64]

FI;

IF VL >= 256

TMP_DEST[191:128] := SRC1[191:128]

TMP_DEST[207:192] := (SRC1 >> (imm[1:0] *16))[207:192]

TMP_DEST[223:208] := (SRC1 >> (imm[3:2] * 16))[207:192]

TMP_DEST[239:224] := (SRC1 >> (imm[5:4] * 16))[207:192]

TMP_DEST[255:240] := (SRC1 >> (imm[7:6] * 16))[207:192]

FI;

IF VL >= 512

TMP_DEST[319:256] := SRC1[319:256]

TMP_DEST[335:320] := (SRC1 >> (imm[1:0] *16))[335:320]

PSHUFHW—Shuffle Packed High Words

Vol. 2B

4-431

INSTRUCTION SET REFERENCE, M-U

TMP_DEST[351:336] := (SRC1 >> (imm[3:2] * 16))[335:320]

TMP_DEST[367:352] := (SRC1 >> (imm[5:4] * 16))[335:320]

TMP_DEST[383:368] := (SRC1 >> (imm[7:6] * 16))[335:320]

TMP_DEST[447:384] := SRC1[447:384]

TMP_DEST[463:448] := (SRC1 >> (imm[1:0] *16))[463:448]

TMP_DEST[479:464] := (SRC1 >> (imm[3:2] * 16))[463:448]

TMP_DEST[495:480] := (SRC1 >> (imm[5:4] * 16))[463:448]

TMP_DEST[511:496] := (SRC1 >> (imm[7:6] * 16))[463:448]

FI;

FOR j := 0 TO KL-1

i := j * 16

IF k1[j] OR *no writemask*

THEN DEST[i+15:i] := TMP_DEST[i+15:i];

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+15:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+15:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VPSHUFHW __m512i _mm512_shufflehi_epi16(__m512i a, int n);

VPSHUFHW __m512i _mm512_mask_shufflehi_epi16(__m512i s, __mmask16 k, __m512i a, int n );

VPSHUFHW __m512i _mm512_maskz_shufflehi_epi16( __mmask16 k, __m512i a, int n );

VPSHUFHW __m256i _mm256_mask_shufflehi_epi16(__m256i s, __mmask8 k, __m256i a, int n );

VPSHUFHW __m256i _mm256_maskz_shufflehi_epi16( __mmask8 k, __m256i a, int n );

VPSHUFHW __m128i _mm_mask_shufflehi_epi16(__m128i s, __mmask8 k, __m128i a, int n );

VPSHUFHW __m128i _mm_maskz_shufflehi_epi16( __mmask8 k, __m128i a, int n );

(V)PSHUFHW:__m128i _mm_shufflehi_epi16(__m128i a, int n)

VPSHUFHW:__m256i _mm256_shufflehi_epi16(__m256i a, const int n)

Flags Affected

None.

SIMD Floating-Point Exceptions

None.

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions”.

EVEX-encoded instruction, see Exceptions Type E4NF.nb in Table 2-50, “Type E4NF Class Exception Conditions”.

Additionally:

#UD

If VEX.vvvv != 1111B, or EVEX.vvvv != 1111B.

4-432

Vol. 2B

PSHUFHW—Shuffle Packed High Words

INSTRUCTION SET REFERENCE, M-U

PSHUFLW—Shuffle Packed Low Words

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

F2 0F 70 /r ib

V/V

SSE2

Shuffle the low words in xmm2/m128 based on

the encoding in imm8 and store the result in

PSHUFLW xmm1, xmm2/m128, imm8

xmm1.

VEX.128.F2.0F.WIG 70 /r ib

V/V

AVX

Shuffle the low words in xmm2/m128 based on

the encoding in imm8 and store the result in

VPSHUFLW xmm1, xmm2/m128, imm8

xmm1.

VEX.256.F2.0F.WIG 70 /r ib

V/V

AVX2

Shuffle the low words in ymm2/m256 based on

the encoding in imm8 and store the result in

VPSHUFLW ymm1, ymm2/m256, imm8

ymm1.

EVEX.128.F2.0F.WIG 70 /r ib

V/V

AVX512VL

Shuffle the low words in xmm2/m128 based on

VPSHUFLW xmm1 {k1}{z}, xmm2/m128, imm8

AVX512BW

the encoding in imm8 and store the result in

xmm1 under write mask k1.

EVEX.256.F2.0F.WIG 70 /r ib

V/V

AVX512VL

Shuffle the low words in ymm2/m256 based on

VPSHUFLW ymm1 {k1}{z}, ymm2/m256, imm8

AVX512BW

the encoding in imm8 and store the result in

ymm1 under write mask k1.

EVEX.512.F2.0F.WIG 70 /r ib

V/V

AVX512BW

Shuffle the low words in zmm2/m512 based on

VPSHUFLW zmm1 {k1}{z}, zmm2/m512, imm8

the encoding in imm8 and store the result in

zmm1 under write mask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

imm8

N/A

Full Mem

ModRM:reg (w)

ModRM:r/m (r)

imm8

N/A

Description

Copies words from the low quadword of a 128-bit lane of the source operand and inserts them in the low quadword

of the destination operand at word locations (of the respective lane) selected with the immediate operand. The

256-bit operation is similar to the in-lane operation used by the 256-bit VPSHUFD instruction, which is illustrated

in Figure 4-16. For 128-bit operation, only the low 128-bit lane is operative. Each 2-bit field in the immediate

operand selects the contents of one word location in the low quadword of the destination operand. The binary

encodings of the immediate operand fields select words (0, 1, 2 or 3) from the low quadword of the source operand

to be copied to the destination operand. The high quadword of the source operand is copied to the high quadword

of the destination operand, for each 128-bit lane.

Note that this instruction permits a word in the low quadword of the source operand to be copied to more than one

word location in the low quadword of the destination operand.

In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to

access additional registers (XMM8-XMM15).

128-bit Legacy SSE version: The destination operand is an XMM register. The source operand can be an XMM

unchanged.

VEX.128 encoded version: The destination operand is an XMM register. The source operand can be an XMM register

or a 128-bit memory location. Bits (MAXVL-1:128) of the destination YMM register are zeroed.

VEX.256 encoded version: The destination operand is an YMM register. The source operand can be an YMM register

or a 256-bit memory location.

EVEX encoded version: The destination operand is a ZMM/YMM/XMM registers. The source operand can be a

ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination is updated according to the

writemask.

PSHUFLW—Shuffle Packed Low Words

Vol. 2B

4-433

INSTRUCTION SET REFERENCE, M-U

Note: In VEX encoded versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Operation

PSHUFLW (128-bit Legacy SSE version)

DEST[15:0] := (SRC >> (imm[1:0] *16))[15:0]

DEST[31:16] := (SRC >> (imm[3:2] * 16))[15:0]

DEST[47:32] := (SRC >> (imm[5:4] * 16))[15:0]

DEST[63:48] := (SRC >> (imm[7:6] * 16))[15:0]

DEST[127:64] := SRC[127:64]

DEST[MAXVL-1:128] (Unmodified)

VPSHUFLW (VEX.128 encoded version)

DEST[15:0] := (SRC1 >> (imm[1:0] *16))[15:0]

DEST[31:16] := (SRC1 >> (imm[3:2] * 16))[15:0]

DEST[47:32] := (SRC1 >> (imm[5:4] * 16))[15:0]

DEST[63:48] := (SRC1 >> (imm[7:6] * 16))[15:0]

DEST[127:64] := SRC[127:64]

DEST[MAXVL-1:128] := 0

VPSHUFLW (VEX.256 encoded version)

DEST[15:0] := (SRC1 >> (imm[1:0] *16))[15:0]

DEST[31:16] := (SRC1 >> (imm[3:2] * 16))[15:0]

DEST[47:32] := (SRC1 >> (imm[5:4] * 16))[15:0]

DEST[63:48] := (SRC1 >> (imm[7:6] * 16))[15:0]

DEST[127:64] := SRC1[127:64]

DEST[143:128] := (SRC1 >> (imm[1:0] *16))[143:128]

DEST[159:144] := (SRC1 >> (imm[3:2] * 16))[143:128]

DEST[175:160] := (SRC1 >> (imm[5:4] * 16))[143:128]

DEST[191:176] := (SRC1 >> (imm[7:6] * 16))[143:128]

DEST[255:192] := SRC1[255:192]

DEST[MAXVL-1:256] := 0

VPSHUFLW (EVEX.U1.512 encoded version)

(KL, VL) = (8, 128), (16, 256), (32, 512)

IF VL >= 128

TMP_DEST[15:0] := (SRC1 >> (imm[1:0] *16))[15:0]

TMP_DEST[31:16] := (SRC1 >> (imm[3:2] * 16))[15:0]

TMP_DEST[47:32] := (SRC1 >> (imm[5:4] * 16))[15:0]

TMP_DEST[63:48] := (SRC1 >> (imm[7:6] * 16))[15:0]

TMP_DEST[127:64] := SRC1[127:64]

FI;

IF VL >= 256

TMP_DEST[143:128] := (SRC1 >> (imm[1:0] *16))[143:128]

TMP_DEST[159:144] := (SRC1 >> (imm[3:2] * 16))[143:128]

TMP_DEST[175:160] := (SRC1 >> (imm[5:4] * 16))[143:128]

TMP_DEST[191:176] := (SRC1 >> (imm[7:6] * 16))[143:128]

TMP_DEST[255:192] := SRC1[255:192]

FI;

IF VL >= 512

TMP_DEST[271:256] := (SRC1 >> (imm[1:0] *16))[271:256]

TMP_DEST[287:272] := (SRC1 >> (imm[3:2] * 16))[271:256]

TMP_DEST[303:288] := (SRC1 >> (imm[5:4] * 16))[271:256]

TMP_DEST[319:304] := (SRC1 >> (imm[7:6] * 16))[271:256]

TMP_DEST[383:320] := SRC1[383:320]

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Vol. 2B

PSHUFLW—Shuffle Packed Low Words

INSTRUCTION SET REFERENCE, M-U

TMP_DEST[399:384] := (SRC1 >> (imm[1:0] *16))[399:384]

TMP_DEST[415:400] := (SRC1 >> (imm[3:2] * 16))[399:384]

TMP_DEST[431:416] := (SRC1 >> (imm[5:4] * 16))[399:384]

TMP_DEST[447:432] := (SRC1 >> (imm[7:6] * 16))[399:384]

TMP_DEST[511:448] := SRC1[511:448]

FI;

FOR j := 0 TO KL-1

i := j * 16

IF k1[j] OR *no writemask*

THEN DEST[i+15:i] := TMP_DEST[i+15:i];

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+15:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+15:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VPSHUFLW __m512i _mm512_shufflelo_epi16(__m512i a, int n);

VPSHUFLW __m512i _mm512_mask_shufflelo_epi16(__m512i s, __mmask16 k, __m512i a, int n );

VPSHUFLW __m512i _mm512_maskz_shufflelo_epi16( __mmask16 k, __m512i a, int n );

VPSHUFLW __m256i _mm256_mask_shufflelo_epi16(__m256i s, __mmask8 k, __m256i a, int n );

VPSHUFLW __m256i _mm256_maskz_shufflelo_epi16( __mmask8 k, __m256i a, int n );

VPSHUFLW __m128i _mm_mask_shufflelo_epi16(__m128i s, __mmask8 k, __m128i a, int n );

VPSHUFLW __m128i _mm_maskz_shufflelo_epi16( __mmask8 k, __m128i a, int n );

(V)PSHUFLW:__m128i _mm_shufflelo_epi16(__m128i a, int n)

VPSHUFLW:__m256i _mm256_shufflelo_epi16(__m256i a, const int n)

Flags Affected

None.

SIMD Floating-Point Exceptions

None.

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions”.

EVEX-encoded instruction, see Exceptions Type E4NF.nb in Table 2-50, “Type E4NF Class Exception Conditions”.

Additionally:

#UD

If VEX.vvvv != 1111B, or EVEX.vvvv != 1111B.

PSHUFLW—Shuffle Packed Low Words

Vol. 2B

4-435

INSTRUCTION SET REFERENCE, M-U

PSHUFW—Shuffle Packed Words

Opcode/

Op/

64-Bit

Compat/

Description

Instruction

Mode

Leg Mode

NP 0F 70 /r ib

RMI

Valid

Shuffle the words in mm2/m64 based on the

encoding in imm8 and store the result in mm1.

PSHUFW mm1, mm2/m64, imm8

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RMI

ModRM:reg (w)

ModRM:r/m (r)

imm8

N/A

Description

Copies words from the source operand (second operand) and inserts them in the destination operand (first

operand) at word locations selected with the order operand (third operand). This operation is similar to the opera-

tion used by the PSHUFD instruction, which is illustrated in Figure 4-16. For the PSHUFW instruction, each 2-bit

field in the order operand selects the contents of one word location in the destination operand. The encodings of the

order operand fields select words from the source operand to be copied to the destination operand.

The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an

MMX technology register. The order operand is an 8-bit immediate. Note that this instruction permits a word in the

source operand to be copied to more than one word location in the destination operand.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers

(XMM8-XMM15).

Operation

DEST[15:0] := (SRC >> (ORDER[1:0] * 16))[15:0];

DEST[31:16] := (SRC >> (ORDER[3:2] * 16))[15:0];

DEST[47:32] := (SRC >> (ORDER[5:4] * 16))[15:0];

DEST[63:48] := (SRC >> (ORDER[7:6] * 16))[15:0];

Intel C/C++ Compiler Intrinsic Equivalent

PSHUFW:

__m64 _mm_shuffle_pi16(__m64 a, int n)

Flags Affected

None.

Numeric Exceptions

None.

Other Exceptions

See Table 23-7, “Exception Conditions for SIMD/MMX Instructions with Memory Reference” in the Intel® 64 and

IA-32 Architectures Software Developer’s Manual, Volume 3A.

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Vol. 2B

PSHUFW—Shuffle Packed Words

INSTRUCTION SET REFERENCE, M-U

PSIGNB/PSIGNW/PSIGND—Packed SIGN

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

NP 0F 38 08 /r¹

V/V

SSSE3

Negate/zero/preserve packed byte integers in

PSIGNB mm1, mm2/m64

mm1 depending on the corresponding sign in

mm2/m64.

66 0F 38 08 /r

V/V

SSSE3

Negate/zero/preserve packed byte integers in

xmm1 depending on the corresponding sign in

PSIGNB xmm1, xmm2/m128

xmm2/m128.

NP 0F 38 09 /r¹

V/V

SSSE3

Negate/zero/preserve packed word integers

in mm1 depending on the corresponding sign

PSIGNW mm1, mm2/m64

in mm2/m128.

66 0F 38 09 /r

V/V

SSSE3

Negate/zero/preserve packed word integers

in xmm1 depending on the corresponding sign

PSIGNW xmm1, xmm2/m128

in xmm2/m128.

NP 0F 38 0A /r¹

V/V

SSSE3

Negate/zero/preserve packed doubleword

integers in mm1 depending on the

PSIGND mm1, mm2/m64

corresponding sign in mm2/m128.

66 0F 38 0A /r

V/V

SSSE3

Negate/zero/preserve packed doubleword

integers in xmm1 depending on the

PSIGND xmm1, xmm2/m128

corresponding sign in xmm2/m128.

VEX.128.66.0F38.WIG 08 /r

RVM

V/V

AVX

Negate/zero/preserve packed byte integers in

xmm2 depending on the corresponding sign in

VPSIGNB xmm1, xmm2, xmm3/m128

xmm3/m128.

VEX.128.66.0F38.WIG 09 /r

RVM

V/V

AVX

Negate/zero/preserve packed word integers

in xmm2 depending on the corresponding sign

VPSIGNW xmm1, xmm2, xmm3/m128

in xmm3/m128.

VEX.128.66.0F38.WIG 0A /r

RVM

V/V

AVX

Negate/zero/preserve packed doubleword

integers in xmm2 depending on the

VPSIGND xmm1, xmm2, xmm3/m128

corresponding sign in xmm3/m128.

VEX.256.66.0F38.WIG 08 /r

RVM

V/V

AVX2

Negate packed byte integers in ymm2 if the

corresponding sign in ymm3/m256 is less

VPSIGNB ymm1, ymm2, ymm3/m256

than zero.

VEX.256.66.0F38.WIG 09 /r

RVM

V/V

AVX2

Negate packed 16-bit integers in ymm2 if the

corresponding sign in ymm3/m256 is less

VPSIGNW ymm1, ymm2, ymm3/m256

than zero.

VEX.256.66.0F38.WIG 0A /r

RVM

V/V

AVX2

Negate packed doubleword integers in ymm2

if the corresponding sign in ymm3/m256 is

VPSIGND ymm1, ymm2, ymm3/m256

less than zero.

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2A and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX

Registers” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

RVM

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

PSIGNB/PSIGNW/PSIGND—Packed SIGN

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4-437

INSTRUCTION SET REFERENCE, M-U

Description

(V)PSIGNB/(V)PSIGNW/(V)PSIGND negates each data element of the destination operand (the first operand) if the

signed integer value of the corresponding data element in the source operand (the second operand) is less than

zero. If the signed integer value of a data element in the source operand is positive, the corresponding data

element in the destination operand is unchanged. If a data element in the source operand is zero, the corre-

sponding data element in the destination operand is set to zero.

(V)PSIGNB operates on signed bytes. (V)PSIGNW operates on 16-bit signed words. (V)PSIGND operates on signed

32-bit integers.

Legacy SSE instructions: Both operands can be MMX registers. In 64-bit mode, use the REX prefix to access addi-

tional registers.

128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source

operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding YMM destina-

tion register remain unchanged.

VEX.128 encoded version: The first source and destination operands are XMM registers. The second source

operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the destination YMM register are

zeroed. VEX.L must be 0, otherwise instructions will #UD.

VEX.256 encoded version: The first source and destination operands are YMM registers. The second source

operand is an YMM register or a 256-bit memory location.

Operation

def byte_sign(control, input_val):

if control<0:

return negate(input_val)

elif control==0:

return 0

return input_val

def word_sign(control, input_val):

if control<0:

return negate(input_val)

elif control==0:

return 0

return input_val

def dword_sign(control, input_val):

if control<0:

return negate(input_val)

elif control==0:

return 0

return input_val

PSIGNB srcdest, src

// MMX 64-bit operands

VL=64

KL := VL/8

for i in 0...KL-1:

srcdest.byte[i] := byte_sign(src.byte[i], srcdest.byte[i])

PSIGNW srcdest, src

// MMX 64-bit operands

VL=64

KL := VL/16

FOR i in 0...KL-1:

srcdest.word[i] := word_sign(src.word[i], srcdest.word[i])

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PSIGNB/PSIGNW/PSIGND—Packed SIGN

INSTRUCTION SET REFERENCE, M-U

PSIGND srcdest, src

// MMX 64-bit operands

VL=64

KL := VL/32

FOR i in 0...KL-1:

srcdest.dword[i] := dword_sign(src.dword[i], srcdest.dword[i])

PSIGNB srcdest, src

// SSE 128-bit operands

VL=128

KL := VL/8

FOR i in 0...KL-1:

srcdest.byte[i] := byte_sign(src.byte[i], srcdest.byte[i])

PSIGNW srcdest, src

// SSE 128-bit operands

VL=128

KL := VL/16

FOR i in 0...KL-1:

srcdest.word[i] := word_sign(src.word[i], srcdest.word[i])

PSIGND srcdest, src

// SSE 128-bit operands

VL=128

KL := VL/32

FOR i in 0...KL-1:

srcdest.dword[i] := dword_sign(src.dword[i], srcdest.dword[i])

VPSIGNB dest, src1, src2

// AVX 128-bit or 256-bit operands

VL=(128,256)

KL := VL/8

FOR i in 0...KL-1:

dest.byte[i] := byte_sign(src2.byte[i], src1.byte[i])

DEST[MAXVL-1:VL] := 0

VPSIGNW dest, src1, src2

// AVX 128-bit or 256-bit operands

VL=(128,256)

KL := VL/16

FOR i in 0...KL-1:

dest.word[i] := word_sign(src2.word[i], src1.word[i])

DEST[MAXVL-1:VL] := 0

VPSIGND dest, src1, src2

// AVX 128-bit or 256-bit operands

VL=(128,256)

KL := VL/32

FOR i in 0...KL-1:

dest.dword[i] := dword_sign(src2.dword[i], src1.dword[i])

DEST[MAXVL-1:VL] := 0

PSIGNB/PSIGNW/PSIGND—Packed SIGN

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INSTRUCTION SET REFERENCE, M-U

Intel C/C++ Compiler Intrinsic Equivalent

PSIGNB:

__m64 _mm_sign_pi8 (__m64 a, __m64 b)

(V)PSIGNB:

__m128i _mm_sign_epi8 (__m128i a, __m128i b)

VPSIGNB:

__m256i _mm256_sign_epi8 (__m256i a, __m256i b)

PSIGNW:

__m64 _mm_sign_pi16 (__m64 a, __m64 b)

(V)PSIGNW:

__m128i _mm_sign_epi16 (__m128i a, __m128i b)

VPSIGNW:

__m256i _mm256_sign_epi16 (__m256i a, __m256i b)

PSIGND:

__m64 _mm_sign_pi32 (__m64 a, __m64 b)

(V)PSIGND:

__m128i _mm_sign_epi32 (__m128i a, __m128i b)

VPSIGND:

__m256i _mm256_sign_epi32 (__m256i a, __m256i b)

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-21, “Type 4 Class Exception Conditions”; additionally:

#UD

If VEX.L = 1.

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PSIGNB/PSIGNW/PSIGND—Packed SIGN

INSTRUCTION SET REFERENCE, M-U

PSLLDQ—Shift Double Quadword Left Logical

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

66 0F 73 /7 ib

V/V

SSE2

Shift xmm1 left by imm8 bytes while shifting

in 0s.

PSLLDQ xmm1, imm8

VEX.128.66.0F.WIG 73 /7 ib

V/V

AVX

Shift xmm2 left by imm8 bytes while shifting

in 0s and store result in xmm1.

VPSLLDQ xmm1, xmm2, imm8

VEX.256.66.0F.WIG 73 /7 ib

V/V

AVX2

Shift ymm2 left by imm8 bytes while shifting

in 0s and store result in ymm1.

VPSLLDQ ymm1, ymm2, imm8

EVEX.128.66.0F.WIG 73 /7 ib

V/V

AVX512VL

Shift xmm2/m128 left by imm8 bytes while

VPSLLDQ xmm1,xmm2/ m128, imm8

AVX512BW

shifting in 0s and store result in xmm1.

EVEX.256.66.0F.WIG 73 /7 ib

V/V

AVX512VL

Shift ymm2/m256 left by imm8 bytes while

VPSLLDQ ymm1, ymm2/m256, imm8

AVX512BW

shifting in 0s and store result in ymm1.

EVEX.512.66.0F.WIG 73 /7 ib

V/V

AVX512BW

Shift zmm2/m512 left by imm8 bytes while

VPSLLDQ zmm1, zmm2/m512, imm8

shifting in 0s and store result in zmm1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:r/m (r, w)

imm8

N/A

VEX.vvvv (w)

ModRM:r/m (r)

imm8

N/A

Full Mem

EVEX.vvvv (w)

ModRM:r/m (r)

imm8

N/A

Description

Shifts the destination operand (first operand) to the left by the number of bytes specified in the count operand

(second operand). The empty low-order bytes are cleared (set to all 0s). If the value specified by the count operand

is greater than 15, the destination operand is set to all 0s. The count operand is an 8-bit immediate.

128-bit Legacy SSE version: The source and destination operands are the same. Bits (MAXVL-1:128) of the corre-

sponding YMM destination register remain unchanged.

VEX.128 encoded version: The source and destination operands are XMM registers. Bits (MAXVL-1:128) of the

destination YMM register are zeroed.

VEX.256 encoded version: The source operand is YMM register. The destination operand is an YMM register. Bits

(MAXVL-1:256) of the corresponding ZMM register are zeroed. The count operand applies to both the low and high

128-bit lanes.

EVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location.

The destination operand is a ZMM/YMM/XMM register. The count operand applies to each 128-bit lanes.

Operation

VPSLLDQ (EVEX.U1.512 encoded version)

TEMP := COUNT

IF (TEMP > 15) THEN TEMP := 16; FI

DEST[127:0] := SRC[127:0] << (TEMP * 8)

DEST[255:128] := SRC[255:128] << (TEMP * 8)

DEST[383:256] := SRC[383:256] << (TEMP * 8)

DEST[511:384] := SRC[511:384] << (TEMP * 8)

DEST[MAXVL-1:512] := 0

PSLLDQ—Shift Double Quadword Left Logical

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INSTRUCTION SET REFERENCE, M-U

VPSLLDQ (VEX.256 and EVEX.256 encoded version)

TEMP := COUNT

IF (TEMP > 15) THEN TEMP := 16; FI

DEST[127:0] := SRC[127:0] << (TEMP * 8)

DEST[255:128] := SRC[255:128] << (TEMP * 8)

DEST[MAXVL-1:256] := 0

VPSLLDQ (VEX.128 and EVEX.128 encoded version)

TEMP := COUNT

IF (TEMP > 15) THEN TEMP := 16; FI

DEST := SRC << (TEMP * 8)

DEST[MAXVL-1:128] := 0

PSLLDQ(128-bit Legacy SSE version)

TEMP := COUNT

IF (TEMP > 15) THEN TEMP := 16; FI

DEST := DEST << (TEMP * 8)

DEST[MAXVL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

(V)PSLLDQ:__m128i _mm_slli_si128 ( __m128i a, int imm)

VPSLLDQ:__m256i _mm256_slli_si256 ( __m256i a, const int imm)

VPSLLDQ __m512i _mm512_bslli_epi128 ( __m512i a, const int imm)

Flags Affected

None.

Numeric Exceptions

None.

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-24, “Type 7 Class Exception Conditions”.

EVEX-encoded instruction, see Exceptions Type E4NF.nb in Table 2-50, “Type E4NF Class Exception Conditions”.

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PSLLDQ—Shift Double Quadword Left Logical

INSTRUCTION SET REFERENCE, M-U

PSLLW/PSLLD/PSLLQ—Shift Packed Data Left Logical

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

NP 0F F1 /r¹

V/V

MMX

Shift words in mm left mm/m64 while shifting in

0s.

PSLLW mm, mm/m64

66 0F F1 /r

V/V

SSE2

Shift words in xmm1 left by xmm2/m128 while

shifting in 0s.

PSLLW xmm1, xmm2/m128

NP 0F 71 /6 ib

V/V

MMX

Shift words in mm left by imm8 while shifting in

0s.

PSLLW mm1, imm8

66 0F 71 /6 ib

V/V

SSE2

Shift words in xmm1 left by imm8 while shifting

in 0s.

PSLLW xmm1, imm8

NP 0F F2 /r¹

V/V

MMX

Shift doublewords in mm left by mm/m64 while

shifting in 0s.

PSLLD mm, mm/m64

66 0F F2 /r

V/V

SSE2

Shift doublewords in xmm1 left by xmm2/m128

while shifting in 0s.

PSLLD xmm1, xmm2/m128

NP 0F 72 /6 ib¹

V/V

MMX

Shift doublewords in mm left by imm8 while

shifting in 0s.

PSLLD mm, imm8

66 0F 72 /6 ib

V/V

SSE2

Shift doublewords in xmm1 left by imm8 while

shifting in 0s.

PSLLD xmm1, imm8

NP 0F F3 /r¹

V/V

MMX

Shift quadword in mm left by mm/m64 while

shifting in 0s.

PSLLQ mm, mm/m64

66 0F F3 /r

V/V

SSE2

Shift quadwords in xmm1 left by xmm2/m128

while shifting in 0s.

PSLLQ xmm1, xmm2/m128

NP 0F 73 /6 ib¹

V/V

MMX

Shift quadword in mm left by imm8 while

shifting in 0s.

PSLLQ mm, imm8

66 0F 73 /6 ib

V/V

SSE2

Shift quadwords in xmm1 left by imm8 while

shifting in 0s.

PSLLQ xmm1, imm8

VEX.128.66.0F.WIG F1 /r

V/V

AVX

Shift words in xmm2 left by amount specified in

xmm3/m128 while shifting in 0s.

VPSLLW xmm1, xmm2, xmm3/m128

VEX.128.66.0F.WIG 71 /6 ib

V/V

AVX

Shift words in xmm2 left by imm8 while shifting

in 0s.

VPSLLW xmm1, xmm2, imm8

VEX.128.66.0F.WIG F2 /r

V/V

AVX

Shift doublewords in xmm2 left by amount

specified in xmm3/m128 while shifting in 0s.

VPSLLD xmm1, xmm2, xmm3/m128

VEX.128.66.0F.WIG 72 /6 ib

V/V

AVX

Shift doublewords in xmm2 left by imm8 while

shifting in 0s.

VPSLLD xmm1, xmm2, imm8

VEX.128.66.0F.WIG F3 /r

V/V

AVX

Shift quadwords in xmm2 left by amount

specified in xmm3/m128 while shifting in 0s.

VPSLLQ xmm1, xmm2, xmm3/m128

VEX.128.66.0F.WIG 73 /6 ib

V/V

AVX

Shift quadwords in xmm2 left by imm8 while

shifting in 0s.

VPSLLQ xmm1, xmm2, imm8

VEX.256.66.0F.WIG F1 /r

V/V

AVX2

Shift words in ymm2 left by amount specified in

xmm3/m128 while shifting in 0s.

VPSLLW ymm1, ymm2, xmm3/m128

VEX.256.66.0F.WIG 71 /6 ib

V/V

AVX2

Shift words in ymm2 left by imm8 while shifting

in 0s.

VPSLLW ymm1, ymm2, imm8

PSLLW/PSLLD/PSLLQ—Shift Packed Data Left Logical

Vol. 2B

4-443

INSTRUCTION SET REFERENCE, M-U

VEX.256.66.0F.WIG F2 /r

V/V

AVX2

Shift doublewords in ymm2 left by amount

VPSLLD ymm1, ymm2, xmm3/m128

specified in xmm3/m128 while shifting in 0s.

VEX.256.66.0F.WIG 72 /6 ib

V/V

AVX2

Shift doublewords in ymm2 left by imm8 while

shifting in 0s.

VPSLLD ymm1, ymm2, imm8

VEX.256.66.0F.WIG F3 /r

V/V

AVX2

Shift quadwords in ymm2 left by amount

specified in xmm3/m128 while shifting in 0s.

VPSLLQ ymm1, ymm2, xmm3/m128

VEX.256.66.0F.WIG 73 /6 ib

V/V

AVX2

Shift quadwords in ymm2 left by imm8 while

shifting in 0s.

VPSLLQ ymm1, ymm2, imm8

EVEX.128.66.0F.WIG F1 /r

V/V

AVX512VL

Shift words in xmm2 left by amount specified in

VPSLLW xmm1 {k1}{z}, xmm2, xmm3/m128

AVX512BW

xmm3/m128 while shifting in 0s using

writemask k1.

EVEX.256.66.0F.WIG F1 /r

V/V

AVX512VL

Shift words in ymm2 left by amount specified in

VPSLLW ymm1 {k1}{z}, ymm2, xmm3/m128

AVX512BW

xmm3/m128 while shifting in 0s using

writemask k1.

EVEX.512.66.0F.WIG F1 /r

V/V

AVX512BW

Shift words in zmm2 left by amount specified in

VPSLLW zmm1 {k1}{z}, zmm2, xmm3/m128

xmm3/m128 while shifting in 0s using

writemask k1.

EVEX.128.66.0F.WIG 71 /6 ib

V/V

AVX512VL

Shift words in xmm2/m128 left by imm8 while

VPSLLW xmm1 {k1}{z}, xmm2/m128, imm8

AVX512BW

shifting in 0s using writemask k1.

EVEX.256.66.0F.WIG 71 /6 ib

V/V

AVX512VL

Shift words in ymm2/m256 left by imm8 while

VPSLLW ymm1 {k1}{z}, ymm2/m256, imm8

AVX512BW

shifting in 0s using writemask k1.

EVEX.512.66.0F.WIG 71 /6 ib

V/V

AVX512BW

Shift words in zmm2/m512 left by imm8 while

VPSLLW zmm1 {k1}{z}, zmm2/m512, imm8

shifting in 0 using writemask k1.

EVEX.128.66.0F.W0 F2 /r

V/V

AVX512VL

Shift doublewords in xmm2 left by amount

VPSLLD xmm1 {k1}{z}, xmm2, xmm3/m128

AVX512F

specified in xmm3/m128 while shifting in 0s

under writemask k1.

EVEX.256.66.0F.W0 F2 /r

V/V

AVX512VL

Shift doublewords in ymm2 left by amount

VPSLLD ymm1 {k1}{z}, ymm2, xmm3/m128

AVX512F

specified in xmm3/m128 while shifting in 0s

under writemask k1.

EVEX.512.66.0F.W0 F2 /r

V/V

AVX512F

Shift doublewords in zmm2 left by amount

VPSLLD zmm1 {k1}{z}, zmm2, xmm3/m128

specified in xmm3/m128 while shifting in 0s

under writemask k1.

EVEX.128.66.0F.W0 72 /6 ib

V/V

AVX512VL

Shift doublewords in xmm2/m128/m32bcst left

VPSLLD xmm1 {k1}{z}, xmm2/m128/m32bcst,

AVX512F

by imm8 while shifting in 0s using writemask k1.

imm8

EVEX.256.66.0F.W0 72 /6 ib

V/V

AVX512VL

Shift doublewords in ymm2/m256/m32bcst left

VPSLLD ymm1 {k1}{z}, ymm2/m256/m32bcst,

AVX512F

by imm8 while shifting in 0s using writemask k1.

imm8

EVEX.512.66.0F.W0 72 /6 ib

V/V

AVX512F

Shift doublewords in zmm2/m512/m32bcst left

VPSLLD zmm1 {k1}{z}, zmm2/m512/m32bcst,

by imm8 while shifting in 0s using writemask k1.

imm8

EVEX.128.66.0F.W1 F3 /r

V/V

AVX512VL

Shift quadwords in xmm2 left by amount

VPSLLQ xmm1 {k1}{z}, xmm2, xmm3/m128

AVX512F

specified in xmm3/m128 while shifting in 0s

using writemask k1.

EVEX.256.66.0F.W1 F3 /r

V/V

AVX512VL

Shift quadwords in ymm2 left by amount

VPSLLQ ymm1 {k1}{z}, ymm2, xmm3/m128

AVX512F

specified in xmm3/m128 while shifting in 0s

using writemask k1.

EVEX.512.66.0F.W1 F3 /r

V/V

AVX512F

Shift quadwords in zmm2 left by amount

VPSLLQ zmm1 {k1}{z}, zmm2, xmm3/m128

specified in xmm3/m128 while shifting in 0s

using writemask k1.

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PSLLW/PSLLD/PSLLQ—Shift Packed Data Left Logical

INSTRUCTION SET REFERENCE, M-U

EVEX.128.66.0F.W1 73 /6 ib

V/V

AVX512VL

Shift quadwords in xmm2/m128/m64bcst left

VPSLLQ xmm1 {k1}{z}, xmm2/m128/m64bcst,

AVX512F

by imm8 while shifting in 0s using writemask k1.

imm8

EVEX.256.66.0F.W1 73 /6 ib

V/V

AVX512VL

Shift quadwords in ymm2/m256/m64bcst left

VPSLLQ ymm1 {k1}{z}, ymm2/m256/m64bcst,

AVX512F

by imm8 while shifting in 0s using writemask k1.

imm8

EVEX.512.66.0F.W1 73 /6 ib

V/V

AVX512F

Shift quadwords in zmm2/m512/m64bcst left

VPSLLQ zmm1 {k1}{z}, zmm2/m512/m64bcst,

by imm8 while shifting in 0s using writemask k1.

imm8

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2A and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Reg-

isters” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:r/m (r, w)

imm8

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

VEX.vvvv (w)

ModRM:r/m (r)

imm8

N/A

Full Mem

EVEX.vvvv (w)

ModRM:r/m (r)

imm8

N/A

Full

EVEX.vvvv (w)

ModRM:r/m (r)

imm8

N/A

Mem128

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Shifts the bits in the individual data elements (words, doublewords, or quadword) in the destination operand (first

operand) to the left by the number of bits specified in the count operand (second operand). As the bits in the data

elements are shifted left, the empty low-order bits are cleared (set to 0). If the value specified by the count

operand is greater than 15 (for words), 31 (for doublewords), or 63 (for a quadword), then the destination operand

is set to all 0s. Figure 4-17 gives an example of shifting words in a 64-bit operand.

Pre-Shift

DEST

Shift Left

with Zero

Extension

Post-Shift

X3 << COUNT

X2 << COUNT

X1 << COUNT

X0 << COUNT

DEST

Figure 4-17. PSLLW, PSLLD, and PSLLQ Instruction Operation Using 64-bit Operand

The (V)PSLLW instruction shifts each of the words in the destination operand to the left by the number of bits spec-

ified in the count operand; the (V)PSLLD instruction shifts each of the doublewords in the destination operand; and

the (V)PSLLQ instruction shifts the quadword (or quadwords) in the destination operand.

In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to

access additional registers (XMM8-XMM15).

Legacy SSE instructions 64-bit operand: The destination operand is an MMX technology register; the count

operand can be either an MMX technology register or an 64-bit memory location.

PSLLW/PSLLD/PSLLQ—Shift Packed Data Left Logical

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4-445

INSTRUCTION SET REFERENCE, M-U

128-bit Legacy SSE version: The destination and first source operands are XMM registers. Bits (MAXVL-1:128) of

the corresponding YMM destination register remain unchanged. The count operand can be either an XMM register

or a 128-bit memory location or an 8-bit immediate. If the count operand is a memory address, 128 bits are loaded

but the upper 64 bits are ignored.

VEX.128 encoded version: The destination and first source operands are XMM registers. Bits (MAXVL-1:128) of the

destination YMM register are zeroed. The count operand can be either an XMM register or a 128-bit memory loca-

tion or an 8-bit immediate. If the count operand is a memory address, 128 bits are loaded but the upper 64 bits are

ignored.

VEX.256 encoded version: The destination operand is a YMM register. The source operand is a YMM register or a

memory location. The count operand can come either from an XMM register or a memory location or an 8-bit imme-

diate. Bits (MAXVL-1:256) of the corresponding ZMM register are zeroed.

EVEX encoded versions: The destination operand is a ZMM register updated according to the writemask. The count

operand is either an 8-bit immediate (the immediate count version) or an 8-bit value from an XMM register or a

memory location (the variable count version). For the immediate count version, the source operand (the second

operand) can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32/64-bit

memory location. For the variable count version, the first source operand (the second operand) is a ZMM register,

the second source operand (the third operand, 8-bit variable count) can be an XMM register or a memory location.

Note: In VEX/EVEX encoded versions of shifts with an immediate count, vvvv of VEX/EVEX encode the destination

Note: For shifts with an immediate count (VEX.128.66.0F 71-73 /6, or EVEX.128.66.0F 71-73 /6),

VEX.vvvv/EVEX.vvvv encodes the destination register.

Operation

PSLLW (with 64-bit operand)

IF (COUNT > 15)

THEN

DEST[64:0] := 0000000000000000H;

ELSE

DEST[15:0] := ZeroExtend(DEST[15:0] << COUNT);

(* Repeat shift operation for 2nd and 3rd words *)

DEST[63:48] := ZeroExtend(DEST[63:48] << COUNT);

FI;

PSLLD (with 64-bit operand)

IF (COUNT > 31)

THEN

DEST[64:0] := 0000000000000000H;

ELSE

DEST[31:0] := ZeroExtend(DEST[31:0] << COUNT);

DEST[63:32] := ZeroExtend(DEST[63:32] << COUNT);

FI;

PSLLQ (with 64-bit operand)

IF (COUNT > 63)

THEN

DEST[64:0] := 0000000000000000H;

ELSE

DEST := ZeroExtend(DEST << COUNT);

FI;

LOGICAL_LEFT_SHIFT_WORDS(SRC, COUNT_SRC)

COUNT := COUNT_SRC[63:0];

IF (COUNT > 15)

THEN

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INSTRUCTION SET REFERENCE, M-U

DEST[127:0] := 00000000000000000000000000000000H

ELSE

DEST[15:0] := ZeroExtend(SRC[15:0] << COUNT);

(* Repeat shift operation for 2nd through 7th words *)

DEST[127:112] := ZeroExtend(SRC[127:112] << COUNT);

FI;

LOGICAL_LEFT_SHIFT_DWORDS1(SRC, COUNT_SRC)

COUNT := COUNT_SRC[63:0];

IF (COUNT > 31)

THEN

DEST[31:0] := 0

ELSE

DEST[31:0] := ZeroExtend(SRC[31:0] << COUNT);

FI;

LOGICAL_LEFT_SHIFT_DWORDS(SRC, COUNT_SRC)

COUNT := COUNT_SRC[63:0];

IF (COUNT > 31)

THEN

DEST[127:0] := 00000000000000000000000000000000H

ELSE

DEST[31:0] := ZeroExtend(SRC[31:0] << COUNT);

(* Repeat shift operation for 2nd through 3rd words *)

DEST[127:96] := ZeroExtend(SRC[127:96] << COUNT);

FI;

LOGICAL_LEFT_SHIFT_QWORDS1(SRC, COUNT_SRC)

COUNT := COUNT_SRC[63:0];

IF (COUNT > 63)

THEN

DEST[63:0] := 0

ELSE

DEST[63:0] := ZeroExtend(SRC[63:0] << COUNT);

FI;

LOGICAL_LEFT_SHIFT_QWORDS(SRC, COUNT_SRC)

COUNT := COUNT_SRC[63:0];

IF (COUNT > 63)

THEN

DEST[127:0] := 00000000000000000000000000000000H

ELSE

DEST[63:0] := ZeroExtend(SRC[63:0] << COUNT);

DEST[127:64] := ZeroExtend(SRC[127:64] << COUNT);

FI;

LOGICAL_LEFT_SHIFT_WORDS_256b(SRC, COUNT_SRC)

COUNT := COUNT_SRC[63:0];

IF (COUNT > 15)

THEN

DEST[127:0] := 00000000000000000000000000000000H

DEST[255:128] := 00000000000000000000000000000000H

ELSE

DEST[15:0] := ZeroExtend(SRC[15:0] << COUNT);

(* Repeat shift operation for 2nd through 15th words *)

PSLLW/PSLLD/PSLLQ—Shift Packed Data Left Logical

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INSTRUCTION SET REFERENCE, M-U

DEST[255:240] := ZeroExtend(SRC[255:240] << COUNT);

FI;

LOGICAL_LEFT_SHIFT_DWORDS_256b(SRC, COUNT_SRC)

COUNT := COUNT_SRC[63:0];

IF (COUNT > 31)

THEN

DEST[127:0] := 00000000000000000000000000000000H

DEST[255:128] := 00000000000000000000000000000000H

ELSE

DEST[31:0] := ZeroExtend(SRC[31:0] << COUNT);

(* Repeat shift operation for 2nd through 7th words *)

DEST[255:224] := ZeroExtend(SRC[255:224] << COUNT);

FI;

LOGICAL_LEFT_SHIFT_QWORDS_256b(SRC, COUNT_SRC)

COUNT := COUNT_SRC[63:0];

IF (COUNT > 63)

THEN

DEST[127:0] := 00000000000000000000000000000000H

DEST[255:128] := 00000000000000000000000000000000H

ELSE

DEST[63:0] := ZeroExtend(SRC[63:0] << COUNT);

DEST[127:64] := ZeroExtend(SRC[127:64] << COUNT)

DEST[191:128] := ZeroExtend(SRC[191:128] << COUNT);

DEST[255:192] := ZeroExtend(SRC[255:192] << COUNT);

FI;

VPSLLW (EVEX versions, xmm/m128)

(KL, VL) = (8, 128), (16, 256), (32, 512)

IF VL = 128

TMP_DEST[127:0] := LOGICAL_LEFT_SHIFT_WORDS_128b(SRC1[127:0], SRC2)

FI;

IF VL = 256

TMP_DEST[255:0] := LOGICAL_LEFT_SHIFT_WORDS_256b(SRC1[255:0], SRC2)

FI;

IF VL = 512

TMP_DEST[255:0] := LOGICAL_LEFT_SHIFT_WORDS_256b(SRC1[255:0], SRC2)

TMP_DEST[511:256] := LOGICAL_LEFT_SHIFT_WORDS_256b(SRC1[511:256], SRC2)

FI;

FOR j := 0 TO KL-1

i := j * 16

IF k1[j] OR *no writemask*

THEN DEST[i+15:i] := TMP_DEST[i+15:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+15:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+15:i] = 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

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INSTRUCTION SET REFERENCE, M-U

VPSLLW (EVEX versions, imm8)

(KL, VL) = (8, 128), (16, 256), (32, 512)

IF VL = 128

TMP_DEST[127:0] := LOGICAL_LEFT_SHIFT_WORDS_128b(SRC1[127:0], imm8)

FI;

IF VL = 256

TMP_DEST[255:0] := LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], imm8)

FI;

IF VL = 512

TMP_DEST[255:0] := LOGICAL_LEFT_SHIFT_WORDS_256b(SRC1[255:0], imm8)

TMP_DEST[511:256] := LOGICAL_LEFT_SHIFT_WORDS_256b(SRC1[511:256], imm8)

FI;

FOR j := 0 TO KL-1

i := j * 16

IF k1[j] OR *no writemask*

THEN DEST[i+15:i] := TMP_DEST[i+15:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+15:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+15:i] = 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VPSLLW (ymm, ymm, xmm/m128) - VEX.256 encoding

DEST[255:0] := LOGICAL_LEFT_SHIFT_WORDS_256b(SRC1, SRC2)

DEST[MAXVL-1:256] := 0;

VPSLLW (ymm, imm8) - VEX.256 encoding

DEST[255:0] := LOGICAL_LEFT_SHIFT_WORD_256b(SRC1, imm8)

DEST[MAXVL-1:256] := 0;

VPSLLW (xmm, xmm, xmm/m128) - VEX.128 encoding

DEST[127:0] := LOGICAL_LEFT_SHIFT_WORDS(SRC1, SRC2)

DEST[MAXVL-1:128] := 0

VPSLLW (xmm, imm8) - VEX.128 encoding

DEST[127:0] := LOGICAL_LEFT_SHIFT_WORDS(SRC1, imm8)

DEST[MAXVL-1:128] := 0

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INSTRUCTION SET REFERENCE, M-U

PSLLW (xmm, xmm, xmm/m128)

DEST[127:0] := LOGICAL_LEFT_SHIFT_WORDS(DEST, SRC)

DEST[MAXVL-1:128] (Unmodified)

PSLLW (xmm, imm8)

DEST[127:0] := LOGICAL_LEFT_SHIFT_WORDS(DEST, imm8)

DEST[MAXVL-1:128] (Unmodified)

VPSLLD (EVEX versions, imm8)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) AND (SRC1 *is memory*)

THEN DEST[i+31:i] := LOGICAL_LEFT_SHIFT_DWORDS1(SRC1[31:0], imm8)

ELSE DEST[i+31:i] := LOGICAL_LEFT_SHIFT_DWORDS1(SRC1[i+31:i], imm8)

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VPSLLD (EVEX versions, xmm/m128)

(KL, VL) = (4, 128), (8, 256), (16, 512)

IF VL = 128

TMP_DEST[127:0] := LOGICAL_LEFT_SHIFT_DWORDS_128b(SRC1[127:0], SRC2)

FI;

IF VL = 256

TMP_DEST[255:0] := LOGICAL_LEFT_SHIFT_DWORDS_256b(SRC1[255:0], SRC2)

FI;

IF VL = 512

TMP_DEST[255:0] := LOGICAL_LEFT_SHIFT_DWORDS_256b(SRC1[255:0], SRC2)

TMP_DEST[511:256] := LOGICAL_LEFT_SHIFT_DWORDS_256b(SRC1[511:256], SRC2)

FI;

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] := TMP_DEST[i+31:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

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INSTRUCTION SET REFERENCE, M-U

VPSLLD (ymm, ymm, xmm/m128) - VEX.256 encoding

DEST[255:0] := LOGICAL_LEFT_SHIFT_DWORDS_256b(SRC1, SRC2)

DEST[MAXVL-1:256] := 0;

VPSLLD (ymm, imm8) - VEX.256 encoding

DEST[255:0] := LOGICAL_LEFT_SHIFT_DWORDS_256b(SRC1, imm8)

DEST[MAXVL-1:256] := 0;

VPSLLD (xmm, xmm, xmm/m128) - VEX.128 encoding

DEST[127:0] := LOGICAL_LEFT_SHIFT_DWORDS(SRC1, SRC2)

DEST[MAXVL-1:128] := 0

VPSLLD (xmm, imm8) - VEX.128 encoding

DEST[127:0] := LOGICAL_LEFT_SHIFT_DWORDS(SRC1, imm8)

DEST[MAXVL-1:128] := 0

PSLLD (xmm, xmm, xmm/m128)

DEST[127:0] := LOGICAL_LEFT_SHIFT_DWORDS(DEST, SRC)

DEST[MAXVL-1:128] (Unmodified)

PSLLD (xmm, imm8)

DEST[127:0] := LOGICAL_LEFT_SHIFT_DWORDS(DEST, imm8)

DEST[MAXVL-1:128] (Unmodified)

VPSLLQ (EVEX versions, imm8)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) AND (SRC1 *is memory*)

THEN DEST[i+63:i] := LOGICAL_LEFT_SHIFT_QWORDS1(SRC1[63:0], imm8)

ELSE DEST[i+63:i] := LOGICAL_LEFT_SHIFT_QWORDS1(SRC1[i+63:i], imm8)

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR

VPSLLQ (EVEX versions, xmm/m128)

(KL, VL) = (2, 128), (4, 256), (8, 512)

IF VL = 128

TMP_DEST[127:0] := LOGICAL_LEFT_SHIFT_QWORDS_128b(SRC1[127:0], SRC2)

FI;

IF VL = 256

TMP_DEST[255:0] := LOGICAL_LEFT_SHIFT_QWORDS_256b(SRC1[255:0], SRC2)

FI;

IF VL = 512

TMP_DEST[255:0] := LOGICAL_LEFT_SHIFT_QWORDS_256b(SRC1[255:0], SRC2)

TMP_DEST[511:256] := LOGICAL_LEFT_SHIFT_QWORDS_256b(SRC1[511:256], SRC2)

FI;

PSLLW/PSLLD/PSLLQ—Shift Packed Data Left Logical

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4-451

INSTRUCTION SET REFERENCE, M-U

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i] := TMP_DEST[i+63:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VPSLLQ (ymm, ymm, xmm/m128) - VEX.256 encoding

DEST[255:0] := LOGICAL_LEFT_SHIFT_QWORDS_256b(SRC1, SRC2)

DEST[MAXVL-1:256] := 0;

VPSLLQ (ymm, imm8) - VEX.256 encoding

DEST[255:0] := LOGICAL_LEFT_SHIFT_QWORDS_256b(SRC1, imm8)

DEST[MAXVL-1:256] := 0;

VPSLLQ (xmm, xmm, xmm/m128) - VEX.128 encoding

DEST[127:0] := LOGICAL_LEFT_SHIFT_QWORDS(SRC1, SRC2)

DEST[MAXVL-1:128] := 0

VPSLLQ (xmm, imm8) - VEX.128 encoding

DEST[127:0] := LOGICAL_LEFT_SHIFT_QWORDS(SRC1, imm8)

DEST[MAXVL-1:128] := 0

PSLLQ (xmm, xmm, xmm/m128)

DEST[127:0] := LOGICAL_LEFT_SHIFT_QWORDS(DEST, SRC)

DEST[MAXVL-1:128] (Unmodified)

PSLLQ (xmm, imm8)

DEST[127:0] := LOGICAL_LEFT_SHIFT_QWORDS(DEST, imm8)

DEST[MAXVL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalents

VPSLLD __m512i _mm512_slli_epi32(__m512i a, unsigned int imm);

VPSLLD __m512i _mm512_mask_slli_epi32(__m512i s, __mmask16 k, __m512i a, unsigned int imm);

VPSLLD __m512i _mm512_maskz_slli_epi32( __mmask16 k, __m512i a, unsigned int imm);

VPSLLD __m256i _mm256_mask_slli_epi32(__m256i s, __mmask8 k, __m256i a, unsigned int imm);

VPSLLD __m256i _mm256_maskz_slli_epi32( __mmask8 k, __m256i a, unsigned int imm);

VPSLLD __m128i _mm_mask_slli_epi32(__m128i s, __mmask8 k, __m128i a, unsigned int imm);

VPSLLD __m128i _mm_maskz_slli_epi32( __mmask8 k, __m128i a, unsigned int imm);

VPSLLD __m512i _mm512_sll_epi32(__m512i a, __m128i cnt);

VPSLLD __m512i _mm512_mask_sll_epi32(__m512i s, __mmask16 k, __m512i a, __m128i cnt);

VPSLLD __m512i _mm512_maskz_sll_epi32( __mmask16 k, __m512i a, __m128i cnt);

VPSLLD __m256i _mm256_mask_sll_epi32(__m256i s, __mmask8 k, __m256i a, __m128i cnt);

VPSLLD __m256i _mm256_maskz_sll_epi32( __mmask8 k, __m256i a, __m128i cnt);

VPSLLD __m128i _mm_mask_sll_epi32(__m128i s, __mmask8 k, __m128i a, __m128i cnt);

VPSLLD __m128i _mm_maskz_sll_epi32( __mmask8 k, __m128i a, __m128i cnt);

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INSTRUCTION SET REFERENCE, M-U

VPSLLQ __m512i _mm512_mask_slli_epi64(__m512i a, unsigned int imm);

VPSLLQ __m512i _mm512_mask_slli_epi64(__m512i s, __mmask8 k, __m512i a, unsigned int imm);

VPSLLQ __m512i _mm512_maskz_slli_epi64( __mmask8 k, __m512i a, unsigned int imm);

VPSLLQ __m256i _mm256_mask_slli_epi64(__m256i s, __mmask8 k, __m256i a, unsigned int imm);

VPSLLQ __m256i _mm256_maskz_slli_epi64( __mmask8 k, __m256i a, unsigned int imm);

VPSLLQ __m128i _mm_mask_slli_epi64(__m128i s, __mmask8 k, __m128i a, unsigned int imm);

VPSLLQ __m128i _mm_maskz_slli_epi64( __mmask8 k, __m128i a, unsigned int imm);

VPSLLQ __m512i _mm512_mask_sll_epi64(__m512i a, __m128i cnt);

VPSLLQ __m512i _mm512_mask_sll_epi64(__m512i s, __mmask8 k, __m512i a, __m128i cnt);

VPSLLQ __m512i _mm512_maskz_sll_epi64( __mmask8 k, __m512i a, __m128i cnt);

VPSLLQ __m256i _mm256_mask_sll_epi64(__m256i s, __mmask8 k, __m256i a, __m128i cnt);

VPSLLQ __m256i _mm256_maskz_sll_epi64( __mmask8 k, __m256i a, __m128i cnt);

VPSLLQ __m128i _mm_mask_sll_epi64(__m128i s, __mmask8 k, __m128i a, __m128i cnt);

VPSLLQ __m128i _mm_maskz_sll_epi64( __mmask8 k, __m128i a, __m128i cnt);

VPSLLW __m512i _mm512_slli_epi16(__m512i a, unsigned int imm);

VPSLLW __m512i _mm512_mask_slli_epi16(__m512i s, __mmask32 k, __m512i a, unsigned int imm);

VPSLLW __m512i _mm512_maskz_slli_epi16( __mmask32 k, __m512i a, unsigned int imm);

VPSLLW __m256i _mm256_mask_slli_epi16(__m256i s, __mmask16 k, __m256i a, unsigned int imm);

VPSLLW __m256i _mm256_maskz_slli_epi16( __mmask16 k, __m256i a, unsigned int imm);

VPSLLW __m128i _mm_mask_slli_epi16(__m128i s, __mmask8 k, __m128i a, unsigned int imm);

VPSLLW __m128i _mm_maskz_slli_epi16( __mmask8 k, __m128i a, unsigned int imm);

VPSLLW __m512i _mm512_sll_epi16(__m512i a, __m128i cnt);

VPSLLW __m512i _mm512_mask_sll_epi16(__m512i s, __mmask32 k, __m512i a, __m128i cnt);

VPSLLW __m512i _mm512_maskz_sll_epi16( __mmask32 k, __m512i a, __m128i cnt);

VPSLLW __m256i _mm256_mask_sll_epi16(__m256i s, __mmask16 k, __m256i a, __m128i cnt);

VPSLLW __m256i _mm256_maskz_sll_epi16( __mmask16 k, __m256i a, __m128i cnt);

VPSLLW __m128i _mm_mask_sll_epi16(__m128i s, __mmask8 k, __m128i a, __m128i cnt);

VPSLLW __m128i _mm_maskz_sll_epi16( __mmask8 k, __m128i a, __m128i cnt);

PSLLW:__m64 _mm_slli_pi16 (__m64 m, int count)

PSLLW:__m64 _mm_sll_pi16(__m64 m, __m64 count)

(V)PSLLW:__m128i _mm_slli_epi16(__m64 m, int count)

(V)PSLLW:__m128i _mm_sll_epi16(__m128i m, __m128i count)

VPSLLW:__m256i _mm256_slli_epi16 (__m256i m, int count)

VPSLLW:__m256i _mm256_sll_epi16 (__m256i m, __m128i count)

PSLLD:__m64 _mm_slli_pi32(__m64 m, int count)

PSLLD:__m64 _mm_sll_pi32(__m64 m, __m64 count)

(V)PSLLD:__m128i _mm_slli_epi32(__m128i m, int count)

(V)PSLLD:__m128i _mm_sll_epi32(__m128i m, __m128i count)

VPSLLD:__m256i _mm256_slli_epi32 (__m256i m, int count)

VPSLLD:__m256i _mm256_sll_epi32 (__m256i m, __m128i count)

PSLLQ:__m64 _mm_slli_si64(__m64 m, int count)

PSLLQ:__m64 _mm_sll_si64(__m64 m, __m64 count)

(V)PSLLQ:__m128i _mm_slli_epi64(__m128i m, int count)

(V)PSLLQ:__m128i _mm_sll_epi64(__m128i m, __m128i count)

VPSLLQ:__m256i _mm256_slli_epi64 (__m256i m, int count)

VPSLLQ:__m256i _mm256_sll_epi64 (__m256i m, __m128i count)

Flags Affected

None.

Numeric Exceptions

None.

PSLLW/PSLLD/PSLLQ—Shift Packed Data Left Logical

Vol. 2B

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INSTRUCTION SET REFERENCE, M-U

Other Exceptions

VEX-encoded instructions:

Syntax with RM/RVM operand encoding (A/C in the operand encoding table), see Table 2-21, “Type 4 Class

Exception Conditions”.

Syntax with MI/VMI operand encoding (B/D in the operand encoding table), see Table 2-24, “Type 7 Class

Exception Conditions”.

EVEX-encoded VPSLLW (E in the operand encoding table), see Exceptions Type E4NF.nb in Table 2-50, “Type E4NF

Class Exception Conditions”.

EVEX-encoded VPSLLD/Q:

Syntax with Mem128 tuple type (G in the operand encoding table), see Exceptions Type E4NF.nb in

Table 2-50, “Type E4NF Class Exception Conditions”.

Syntax with Full tuple type (F in the operand encoding table), see Table 2-49, “Type E4 Class Exception Condi-

tions”.

4-454

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PSLLW/PSLLD/PSLLQ—Shift Packed Data Left Logical

INSTRUCTION SET REFERENCE, M-U

PSRAW/PSRAD/PSRAQ—Shift Packed Data Right Arithmetic

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

NP 0F E1 /r¹

V/V

MMX

Shift words in mm right by mm/m64 while shifting

in sign bits.

PSRAW mm, mm/m64

66 0F E1 /r

V/V

SSE2

Shift words in xmm1 right by xmm2/m128 while

shifting in sign bits.

PSRAW xmm1, xmm2/m128

NP 0F 71 /4 ib¹

V/V

MMX

Shift words in mm right by imm8 while shifting in

sign bits

PSRAW mm, imm8

66 0F 71 /4 ib

V/V

SSE2

Shift words in xmm1 right by imm8 while shifting

in sign bits

PSRAW xmm1, imm8

NP 0F E2 /r¹

V/V

MMX

Shift doublewords in mm right by mm/m64 while

shifting in sign bits.

PSRAD mm, mm/m64

66 0F E2 /r

V/V

SSE2

Shift doubleword in xmm1 right by xmm2 /m128

while shifting in sign bits.

PSRAD xmm1, xmm2/m128

NP 0F 72 /4 ib¹

V/V

MMX

Shift doublewords in mm right by imm8 while

shifting in sign bits.

PSRAD mm, imm8

66 0F 72 /4 ib

V/V

SSE2

Shift doublewords in xmm1 right by imm8 while

shifting in sign bits.

PSRAD xmm1, imm8

VEX.128.66.0F.WIG E1 /r

V/V

AVX

Shift words in xmm2 right by amount specified in

xmm3/m128 while shifting in sign bits.

VPSRAW xmm1, xmm2, xmm3/m128

VEX.128.66.0F.WIG 71 /4 ib

V/V

AVX

Shift words in xmm2 right by imm8 while shifting

in sign bits.

VPSRAW xmm1, xmm2, imm8

VEX.128.66.0F.WIG E2 /r

V/V

AVX

Shift doublewords in xmm2 right by amount

specified in xmm3/m128 while shifting in sign

VPSRAD xmm1, xmm2, xmm3/m128

bits.

VEX.128.66.0F.WIG 72 /4 ib

V/V

AVX

Shift doublewords in xmm2 right by imm8 while

shifting in sign bits.

VPSRAD xmm1, xmm2, imm8

VEX.256.66.0F.WIG E1 /r

V/V

AVX2

Shift words in ymm2 right by amount specified in

xmm3/m128 while shifting in sign bits.

VPSRAW ymm1, ymm2, xmm3/m128

VEX.256.66.0F.WIG 71 /4 ib

V/V

AVX2

Shift words in ymm2 right by imm8 while shifting

in sign bits.

VPSRAW ymm1, ymm2, imm8

VEX.256.66.0F.WIG E2 /r

V/V

AVX2

Shift doublewords in ymm2 right by amount

specified in xmm3/m128 while shifting in sign

VPSRAD ymm1, ymm2, xmm3/m128

bits.

VEX.256.66.0F.WIG 72 /4 ib

V/V

AVX2

Shift doublewords in ymm2 right by imm8 while

shifting in sign bits.

VPSRAD ymm1, ymm2, imm8

EVEX.128.66.0F.WIG E1 /r

V/V

AVX512VL

Shift words in xmm2 right by amount specified in

VPSRAW xmm1 {k1}{z}, xmm2, xmm3/m128

AVX512BW

xmm3/m128 while shifting in sign bits using

writemask k1.

EVEX.256.66.0F.WIG E1 /r

V/V

AVX512VL

Shift words in ymm2 right by amount specified in

VPSRAW ymm1 {k1}{z}, ymm2, xmm3/m128

AVX512BW

xmm3/m128 while shifting in sign bits using

writemask k1.

EVEX.512.66.0F.WIG E1 /r

V/V

AVX512BW

Shift words in zmm2 right by amount specified in

VPSRAW zmm1 {k1}{z}, zmm2, xmm3/m128

xmm3/m128 while shifting in sign bits using

writemask k1.

PSRAW/PSRAD/PSRAQ—Shift Packed Data Right Arithmetic

Vol. 2B

4-455

INSTRUCTION SET REFERENCE, M-U

EVEX.128.66.0F.WIG 71 /4 ib

V/V

AVX512VL

Shift words in xmm2/m128 right by imm8 while

VPSRAW xmm1 {k1}{z}, xmm2/m128, imm8

AVX512BW

shifting in sign bits using writemask k1.

EVEX.256.66.0F.WIG 71 /4 ib

V/V

AVX512VL

Shift words in ymm2/m256 right by imm8 while

VPSRAW ymm1 {k1}{z}, ymm2/m256, imm8

AVX512BW

shifting in sign bits using writemask k1.

EVEX.512.66.0F.WIG 71 /4 ib

V/V

AVX512BW

Shift words in zmm2/m512 right by imm8 while

VPSRAW zmm1 {k1}{z}, zmm2/m512, imm8

shifting in sign bits using writemask k1.

EVEX.128.66.0F.W0 E2 /r

V/V

AVX512VL

Shift doublewords in xmm2 right by amount

VPSRAD xmm1 {k1}{z}, xmm2, xmm3/m128

AVX512F

specified in xmm3/m128 while shifting in sign bits

using writemask k1.

EVEX.256.66.0F.W0 E2 /r

V/V

AVX512VL

Shift doublewords in ymm2 right by amount

VPSRAD ymm1 {k1}{z}, ymm2, xmm3/m128

AVX512F

specified in xmm3/m128 while shifting in sign bits

using writemask k1.

EVEX.512.66.0F.W0 E2 /r

V/V

AVX512F

Shift doublewords in zmm2 right by amount

VPSRAD zmm1 {k1}{z}, zmm2, xmm3/m128

specified in xmm3/m128 while shifting in sign bits

using writemask k1.

EVEX.128.66.0F.W0 72 /4 ib

V/V

AVX512VL

Shift doublewords in xmm2/m128/m32bcst right

VPSRAD xmm1 {k1}{z}, xmm2/m128/m32bcst,

AVX512F

by imm8 while shifting in sign bits using

imm8

writemask k1.

EVEX.256.66.0F.W0 72 /4 ib

V/V

AVX512VL

Shift doublewords in ymm2/m256/m32bcst right

VPSRAD ymm1 {k1}{z}, ymm2/m256/m32bcst,

AVX512F

by imm8 while shifting in sign bits using

imm8

writemask k1.

EVEX.512.66.0F.W0 72 /4 ib

V/V

AVX512F

Shift doublewords in zmm2/m512/m32bcst right

VPSRAD zmm1 {k1}{z}, zmm2/m512/m32bcst,

by imm8 while shifting in sign bits using

imm8

writemask k1.

EVEX.128.66.0F.W1 E2 /r

V/V

AVX512VL

Shift quadwords in xmm2 right by amount

VPSRAQ xmm1 {k1}{z}, xmm2, xmm3/m128

AVX512F

specified in xmm3/m128 while shifting in sign bits

using writemask k1.

EVEX.256.66.0F.W1 E2 /r

V/V

AVX512VL

Shift quadwords in ymm2 right by amount

VPSRAQ ymm1 {k1}{z}, ymm2, xmm3/m128

AVX512F

specified in xmm3/m128 while shifting in sign bits

using writemask k1.

EVEX.512.66.0F.W1 E2 /r

V/V

AVX512F

Shift quadwords in zmm2 right by amount

VPSRAQ zmm1 {k1}{z}, zmm2, xmm3/m128

specified in xmm3/m128 while shifting in sign bits

using writemask k1.

EVEX.128.66.0F.W1 72 /4 ib

V/V

AVX512VL

Shift quadwords in xmm2/m128/m64bcst right by

VPSRAQ xmm1 {k1}{z}, xmm2/m128/m64bcst,

AVX512F

imm8 while shifting in sign bits using writemask

imm8

k1.

EVEX.256.66.0F.W1 72 /4 ib

V/V

AVX512VL

Shift quadwords in ymm2/m256/m64bcst right by

VPSRAQ ymm1 {k1}{z}, ymm2/m256/m64bcst,

AVX512F

imm8 while shifting in sign bits using writemask

imm8

k1.

EVEX.512.66.0F.W1 72 /4 ib

V/V

AVX512F

Shift quadwords in zmm2/m512/m64bcst right by

VPSRAQ zmm1 {k1}{z}, zmm2/m512/m64bcst,

imm8 while shifting in sign bits using writemask

imm8

k1.

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software

Developer’s Manual, Volume 2A and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”

in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

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PSRAW/PSRAD/PSRAQ—Shift Packed Data Right Arithmetic

INSTRUCTION SET REFERENCE, M-U

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:r/m (r, w)

imm8

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

VEX.vvvv (w)

ModRM:r/m (r)

imm8

N/A

Full Mem

EVEX.vvvv (w)

ModRM:r/m (r)

imm8

N/A

Full

EVEX.vvvv (w)

ModRM:r/m (r)

imm8

N/A

Mem128

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Shifts the bits in the individual data elements (words, doublewords or quadwords) in the destination operand (first

operand) to the right by the number of bits specified in the count operand (second operand). As the bits in the data

elements are shifted right, the empty high-order bits are filled with the initial value of the sign bit of the data

element. If the value specified by the count operand is greater than 15 (for words), 31 (for doublewords), or 63 (for

quadwords), each destination data element is filled with the initial value of the sign bit of the element. (Figure 4-18

gives an example of shifting words in a 64-bit operand.)

Pre-Shift

DEST

Shift Right

with Sign

Extension

Post-Shift

X3 >> COUNT

X2 >> COUNT

X1 >> COUNT

X0 >> COUNT

DEST

Figure 4-18. PSRAW and PSRAD Instruction Operation Using a 64-bit Operand

Note that only the first 64-bits of a 128-bit count operand are checked to compute the count. If the second source

operand is a memory address, 128 bits are loaded.

The (V)PSRAW instruction shifts each of the words in the destination operand to the right by the number of bits

specified in the count operand, and the (V)PSRAD instruction shifts each of the doublewords in the destination

operand.

In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to

access additional registers (XMM8-XMM15).

Legacy SSE instructions 64-bit operand: The destination operand is an MMX technology register; the count

operand can be either an MMX technology register or an 64-bit memory location.

128-bit Legacy SSE version: The destination and first source operands are XMM registers. Bits (MAXVL-1:128) of

the corresponding YMM destination register remain unchanged. The count operand can be either an XMM register

or a 128-bit memory location or an 8-bit immediate. If the count operand is a memory address, 128 bits are loaded

but the upper 64 bits are ignored.

VEX.128 encoded version: The destination and first source operands are XMM registers. Bits (MAXVL-1:128) of the

destination YMM register are zeroed. The count operand can be either an XMM register or a 128-bit memory loca-

tion or an 8-bit immediate. If the count operand is a memory address, 128 bits are loaded but the upper 64 bits are

ignored.

VEX.256 encoded version: The destination operand is a YMM register. The source operand is a YMM register or a

memory location. The count operand can come either from an XMM register or a memory location or an 8-bit

immediate. Bits (MAXVL-1:256) of the corresponding ZMM register are zeroed.

PSRAW/PSRAD/PSRAQ—Shift Packed Data Right Arithmetic

Vol. 2B

4-457

INSTRUCTION SET REFERENCE, M-U

EVEX encoded versions: The destination operand is a ZMM register updated according to the writemask. The count

operand is either an 8-bit immediate (the immediate count version) or an 8-bit value from an XMM register or a

memory location (the variable count version). For the immediate count version, the source operand (the second

operand) can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32/64-bit

memory location. For the variable count version, the first source operand (the second operand) is a ZMM register,

the second source operand (the third operand, 8-bit variable count) can be an XMM register or a memory location.

Note: In VEX/EVEX encoded versions of shifts with an immediate count, vvvv of VEX/EVEX encode the destination

Note: For shifts with an immediate count (VEX.128.66.0F 71-73 /4, EVEX.128.66.0F 71-73 /4),

VEX.vvvv/EVEX.vvvv encodes the destination register.

Operation

PSRAW (with 64-bit operand)

IF (COUNT > 15)

THEN COUNT := 16;

FI;

DEST[15:0] := SignExtend(DEST[15:0] >> COUNT);

(* Repeat shift operation for 2nd and 3rd words *)

DEST[63:48] := SignExtend(DEST[63:48] >> COUNT);

PSRAD (with 64-bit operand)

IF (COUNT > 31)

THEN COUNT := 32;

FI;

DEST[31:0] := SignExtend(DEST[31:0] >> COUNT);

DEST[63:32] := SignExtend(DEST[63:32] >> COUNT);

ARITHMETIC_RIGHT_SHIFT_DWORDS1(SRC, COUNT_SRC)

COUNT := COUNT_SRC[63:0];

IF (COUNT > 31)

THEN

DEST[31:0] := SignBit

ELSE

DEST[31:0] := SignExtend(SRC[31:0] >> COUNT);

FI;

ARITHMETIC_RIGHT_SHIFT_QWORDS1(SRC, COUNT_SRC)

COUNT := COUNT_SRC[63:0];

IF (COUNT > 63)

THEN

DEST[63:0] := SignBit

ELSE

DEST[63:0] := SignExtend(SRC[63:0] >> COUNT);

FI;

ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC, COUNT_SRC)

COUNT := COUNT_SRC[63:0];

IF (COUNT > 15)

THEN COUNT := 16;

FI;

DEST[15:0] := SignExtend(SRC[15:0] >> COUNT);

(* Repeat shift operation for 2nd through 15th words *)

DEST[255:240] := SignExtend(SRC[255:240] >> COUNT);

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PSRAW/PSRAD/PSRAQ—Shift Packed Data Right Arithmetic

INSTRUCTION SET REFERENCE, M-U

ARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC, COUNT_SRC)

COUNT := COUNT_SRC[63:0];

IF (COUNT > 31)

THEN COUNT := 32;

FI;

DEST[31:0] := SignExtend(SRC[31:0] >> COUNT);

(* Repeat shift operation for 2nd through 7th words *)

DEST[255:224] := SignExtend(SRC[255:224] >> COUNT);

ARITHMETIC_RIGHT_SHIFT_QWORDS(SRC, COUNT_SRC, VL)

; VL: 128b, 256b or 512b

COUNT := COUNT_SRC[63:0];

IF (COUNT > 63)

THEN COUNT := 64;

FI;

DEST[63:0] := SignExtend(SRC[63:0] >> COUNT);

(* Repeat shift operation for 2nd through 7th words *)

DEST[VL-1:VL-64] := SignExtend(SRC[VL-1:VL-64] >> COUNT);

ARITHMETIC_RIGHT_SHIFT_WORDS(SRC, COUNT_SRC)

COUNT := COUNT_SRC[63:0];

IF (COUNT > 15)

THEN COUNT := 16;

FI;

DEST[15:0] := SignExtend(SRC[15:0] >> COUNT);

(* Repeat shift operation for 2nd through 7th words *)

DEST[127:112] := SignExtend(SRC[127:112] >> COUNT);

ARITHMETIC_RIGHT_SHIFT_DWORDS(SRC, COUNT_SRC)

COUNT := COUNT_SRC[63:0];

IF (COUNT > 31)

THEN COUNT := 32;

FI;

DEST[31:0] := SignExtend(SRC[31:0] >> COUNT);

(* Repeat shift operation for 2nd through 3rd words *)

DEST[127:96] := SignExtend(SRC[127:96] >> COUNT);

PSRAW/PSRAD/PSRAQ—Shift Packed Data Right Arithmetic

Vol. 2B

4-459

INSTRUCTION SET REFERENCE, M-U

VPSRAW (EVEX versions, xmm/m128)

(KL, VL) = (8, 128), (16, 256), (32, 512)

IF VL = 128

TMP_DEST[127:0] := ARITHMETIC_RIGHT_SHIFT_WORDS_128b(SRC1[127:0], SRC2)

FI;

IF VL = 256

TMP_DEST[255:0] := ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], SRC2)

FI;

IF VL = 512

TMP_DEST[255:0] := ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], SRC2)

TMP_DEST[511:256] := ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[511:256], SRC2)

FI;

FOR j := 0 TO KL-1

i := j * 16

IF k1[j] OR *no writemask*

THEN DEST[i+15:i] := TMP_DEST[i+15:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+15:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+15:i] = 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VPSRAW (EVEX versions, imm8)

(KL, VL) = (8, 128), (16, 256), (32, 512)

IF VL = 128

TMP_DEST[127:0] := ARITHMETIC_RIGHT_SHIFT_WORDS_128b(SRC1[127:0], imm8)

FI;

IF VL = 256

TMP_DEST[255:0] := ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], imm8)

FI;

IF VL = 512

TMP_DEST[255:0] := ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], imm8)

TMP_DEST[511:256] := ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[511:256], imm8)

FI;

FOR j := 0 TO KL-1

i := j * 16

IF k1[j] OR *no writemask*

THEN DEST[i+15:i] := TMP_DEST[i+15:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+15:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+15:i] = 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

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PSRAW/PSRAD/PSRAQ—Shift Packed Data Right Arithmetic

INSTRUCTION SET REFERENCE, M-U

VPSRAW (ymm, ymm, xmm/m128) - VEX

DEST[255:0] := ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1, SRC2)

DEST[MAXVL-1:256] := 0

VPSRAW (ymm, imm8) - VEX

DEST[255:0] := ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1, imm8)

DEST[MAXVL-1:256] := 0

VPSRAW (xmm, xmm, xmm/m128) - VEX

DEST[127:0] := ARITHMETIC_RIGHT_SHIFT_WORDS(SRC1, SRC2)

DEST[MAXVL-1:128] := 0

VPSRAW (xmm, imm8) - VEX

DEST[127:0] := ARITHMETIC_RIGHT_SHIFT_WORDS(SRC1, imm8)

DEST[MAXVL-1:128] := 0

PSRAW (xmm, xmm, xmm/m128)

DEST[127:0] := ARITHMETIC_RIGHT_SHIFT_WORDS(DEST, SRC)

DEST[MAXVL-1:128] (Unmodified)

PSRAW (xmm, imm8)

DEST[127:0] := ARITHMETIC_RIGHT_SHIFT_WORDS(DEST, imm8)

DEST[MAXVL-1:128] (Unmodified)

VPSRAD (EVEX versions, imm8)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) AND (SRC1 *is memory*)

THEN DEST[i+31:i] := ARITHMETIC_RIGHT_SHIFT_DWORDS1(SRC1[31:0], imm8)

ELSE DEST[i+31:i] := ARITHMETIC_RIGHT_SHIFT_DWORDS1(SRC1[i+31:i], imm8)

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VPSRAD (EVEX versions, xmm/m128)

(KL, VL) = (4, 128), (8, 256), (16, 512)

IF VL = 128

TMP_DEST[127:0] := ARITHMETIC_RIGHT_SHIFT_DWORDS_128b(SRC1[127:0], SRC2)

FI;

IF VL = 256

TMP_DEST[255:0] := ARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC1[255:0], SRC2)

FI;

IF VL = 512

TMP_DEST[255:0] := ARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC1[255:0], SRC2)

TMP_DEST[511:256] := ARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC1[511:256], SRC2)

PSRAW/PSRAD/PSRAQ—Shift Packed Data Right Arithmetic

Vol. 2B

4-461

INSTRUCTION SET REFERENCE, M-U

FI;

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] := TMP_DEST[i+31:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VPSRAD (ymm, ymm, xmm/m128) - VEX

DEST[255:0] := ARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC1, SRC2)

DEST[MAXVL-1:256] := 0

VPSRAD (ymm, imm8) - VEX

DEST[255:0] := ARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC1, imm8)

DEST[MAXVL-1:256] := 0

VPSRAD (xmm, xmm, xmm/m128) - VEX

DEST[127:0] := ARITHMETIC_RIGHT_SHIFT_DWORDS(SRC1, SRC2)

DEST[MAXVL-1:128] := 0

VPSRAD (xmm, imm8) - VEX

DEST[127:0] := ARITHMETIC_RIGHT_SHIFT_DWORDS(SRC1, imm8)

DEST[MAXVL-1:128] := 0

PSRAD (xmm, xmm, xmm/m128)

DEST[127:0] := ARITHMETIC_RIGHT_SHIFT_DWORDS(DEST, SRC)

DEST[MAXVL-1:128] (Unmodified)

PSRAD (xmm, imm8)

DEST[127:0] := ARITHMETIC_RIGHT_SHIFT_DWORDS(DEST, imm8)

DEST[MAXVL-1:128] (Unmodified)

VPSRAQ (EVEX versions, imm8)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) AND (SRC1 *is memory*)

THEN DEST[i+63:i] := ARITHMETIC_RIGHT_SHIFT_QWORDS1(SRC1[63:0], imm8)

ELSE DEST[i+63:i] := ARITHMETIC_RIGHT_SHIFT_QWORDS1(SRC1[i+63:i], imm8)

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+63:i] := 0

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INSTRUCTION SET REFERENCE, M-U

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VPSRAQ (EVEX versions, xmm/m128)

(KL, VL) = (2, 128), (4, 256), (8, 512)

TMP_DEST[VL-1:0] := ARITHMETIC_RIGHT_SHIFT_QWORDS(SRC1[VL-1:0], SRC2, VL)

FOR j := 0 TO 7

i := j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i] := TMP_DEST[i+63:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

Intel C/C++ Compiler Intrinsic Equivalents

VPSRAD __m512i _mm512_srai_epi32(__m512i a, unsigned int imm);

VPSRAD __m512i _mm512_mask_srai_epi32(__m512i s, __mmask16 k, __m512i a, unsigned int imm);

VPSRAD __m512i _mm512_maskz_srai_epi32( __mmask16 k, __m512i a, unsigned int imm);

VPSRAD __m256i _mm256_mask_srai_epi32(__m256i s, __mmask8 k, __m256i a, unsigned int imm);

VPSRAD __m256i _mm256_maskz_srai_epi32( __mmask8 k, __m256i a, unsigned int imm);

VPSRAD __m128i _mm_mask_srai_epi32(__m128i s, __mmask8 k, __m128i a, unsigned int imm);

VPSRAD __m128i _mm_maskz_srai_epi32( __mmask8 k, __m128i a, unsigned int imm);

VPSRAD __m512i _mm512_sra_epi32(__m512i a, __m128i cnt);

VPSRAD __m512i _mm512_mask_sra_epi32(__m512i s, __mmask16 k, __m512i a, __m128i cnt);

VPSRAD __m512i _mm512_maskz_sra_epi32( __mmask16 k, __m512i a, __m128i cnt);

VPSRAD __m256i _mm256_mask_sra_epi32(__m256i s, __mmask8 k, __m256i a, __m128i cnt);

VPSRAD __m256i _mm256_maskz_sra_epi32( __mmask8 k, __m256i a, __m128i cnt);

VPSRAD __m128i _mm_mask_sra_epi32(__m128i s, __mmask8 k, __m128i a, __m128i cnt);

VPSRAD __m128i _mm_maskz_sra_epi32( __mmask8 k, __m128i a, __m128i cnt);

VPSRAQ __m512i _mm512_srai_epi64(__m512i a, unsigned int imm);

VPSRAQ __m512i _mm512_mask_srai_epi64(__m512i s, __mmask8 k, __m512i a, unsigned int imm)

VPSRAQ __m512i _mm512_maskz_srai_epi64( __mmask8 k, __m512i a, unsigned int imm)

VPSRAQ __m256i _mm256_mask_srai_epi64(__m256i s, __mmask8 k, __m256i a, unsigned int imm);

VPSRAQ __m256i _mm256_maskz_srai_epi64( __mmask8 k, __m256i a, unsigned int imm);

VPSRAQ __m128i _mm_mask_srai_epi64(__m128i s, __mmask8 k, __m128i a, unsigned int imm);

VPSRAQ __m128i _mm_maskz_srai_epi64( __mmask8 k, __m128i a, unsigned int imm);

VPSRAQ __m512i _mm512_sra_epi64(__m512i a, __m128i cnt);

VPSRAQ __m512i _mm512_mask_sra_epi64(__m512i s, __mmask8 k, __m512i a, __m128i cnt)

VPSRAQ __m512i _mm512_maskz_sra_epi64( __mmask8 k, __m512i a, __m128i cnt)

VPSRAQ __m256i _mm256_mask_sra_epi64(__m256i s, __mmask8 k, __m256i a, __m128i cnt);

VPSRAQ __m256i _mm256_maskz_sra_epi64( __mmask8 k, __m256i a, __m128i cnt);

VPSRAQ __m128i _mm_mask_sra_epi64(__m128i s, __mmask8 k, __m128i a, __m128i cnt);

VPSRAQ __m128i _mm_maskz_sra_epi64( __mmask8 k, __m128i a, __m128i cnt);

VPSRAW __m512i _mm512_srai_epi16(__m512i a, unsigned int imm);

VPSRAW __m512i _mm512_mask_srai_epi16(__m512i s, __mmask32 k, __m512i a, unsigned int imm);

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INSTRUCTION SET REFERENCE, M-U

VPSRAW __m512i _mm512_maskz_srai_epi16( __mmask32 k, __m512i a, unsigned int imm);

VPSRAW __m256i _mm256_mask_srai_epi16(__m256i s, __mmask16 k, __m256i a, unsigned int imm);

VPSRAW __m256i _mm256_maskz_srai_epi16( __mmask16 k, __m256i a, unsigned int imm);

VPSRAW __m128i _mm_mask_srai_epi16(__m128i s, __mmask8 k, __m128i a, unsigned int imm);

VPSRAW __m128i _mm_maskz_srai_epi16( __mmask8 k, __m128i a, unsigned int imm);

VPSRAW __m512i _mm512_sra_epi16(__m512i a, __m128i cnt);

VPSRAW __m512i _mm512_mask_sra_epi16(__m512i s, __mmask16 k, __m512i a, __m128i cnt);

VPSRAW __m512i _mm512_maskz_sra_epi16( __mmask16 k, __m512i a, __m128i cnt);

VPSRAW __m256i _mm256_mask_sra_epi16(__m256i s, __mmask8 k, __m256i a, __m128i cnt);

VPSRAW __m256i _mm256_maskz_sra_epi16( __mmask8 k, __m256i a, __m128i cnt);

VPSRAW __m128i _mm_mask_sra_epi16(__m128i s, __mmask8 k, __m128i a, __m128i cnt);

VPSRAW __m128i _mm_maskz_sra_epi16( __mmask8 k, __m128i a, __m128i cnt);

PSRAW:__m64 _mm_srai_pi16 (__m64 m, int count)

PSRAW:__m64 _mm_sra_pi16 (__m64 m, __m64 count)

(V)PSRAW:__m128i _mm_srai_epi16(__m128i m, int count)

(V)PSRAW:__m128i _mm_sra_epi16(__m128i m, __m128i count)

VPSRAW:__m256i _mm256_srai_epi16 (__m256i m, int count)

VPSRAW:__m256i _mm256_sra_epi16 (__m256i m, __m128i count)

PSRAD:__m64 _mm_srai_pi32 (__m64 m, int count)

PSRAD:__m64 _mm_sra_pi32 (__m64 m, __m64 count)

(V)PSRAD:__m128i _mm_srai_epi32 (__m128i m, int count)

(V)PSRAD:__m128i _mm_sra_epi32 (__m128i m, __m128i count)

VPSRAD:__m256i _mm256_srai_epi32 (__m256i m, int count)

VPSRAD:__m256i _mm256_sra_epi32 (__m256i m, __m128i count)

Flags Affected

None.

Numeric Exceptions

None.

Other Exceptions

VEX-encoded instructions:

Syntax with RM/RVM operand encoding (A/C in the operand encoding table), see Table

2-21, “Type 4 Class

Exception Conditions”.

Syntax with MI/VMI operand encoding (B/D in the operand encoding table), see Table

2-24, “Type 7 Class

Exception Conditions”.

EVEX-encoded VPSRAW (E in the operand encoding table), see Exceptions Type E4NF.nb in Table 2-50, “Type E4NF

Class Exception Conditions”.

EVEX-encoded VPSRAD/Q:

Syntax with Mem128 tuple type (G in the operand encoding table), see Exceptions Type E4NF.nb in

Table 2-50, “Type E4NF Class Exception Conditions”.

Syntax with Full tuple type (F in the operand encoding table), see Table 2-49, “Type E4 Class Exception Condi-

tions”.

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INSTRUCTION SET REFERENCE, M-U

PSRLDQ—Shift Double Quadword Right Logical

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

66 0F 73 /3 ib

V/V

SSE2

Shift xmm1 right by imm8 while shifting in 0s.

PSRLDQ xmm1, imm8

VEX.128.66.0F.WIG 73 /3 ib

V/V

AVX

Shift xmm2 right by imm8 bytes while shifting in

0s.

VPSRLDQ xmm1, xmm2, imm8

VEX.256.66.0F.WIG 73 /3 ib

V/V

AVX2

Shift ymm1 right by imm8 bytes while shifting in

0s.

VPSRLDQ ymm1, ymm2, imm8

EVEX.128.66.0F.WIG 73 /3 ib

V/V

AVX512VL

Shift xmm2/m128 right by imm8 bytes while

VPSRLDQ xmm1, xmm2/m128, imm8

AVX512BW

shifting in 0s and store result in xmm1.

EVEX.256.66.0F.WIG 73 /3 ib

V/V

AVX512VL

Shift ymm2/m256 right by imm8 bytes while

VPSRLDQ ymm1, ymm2/m256, imm8

AVX512BW

shifting in 0s and store result in ymm1.

EVEX.512.66.0F.WIG 73 /3 ib

V/V

AVX512BW

Shift zmm2/m512 right by imm8 bytes while

VPSRLDQ zmm1, zmm2/m512, imm8

shifting in 0s and store result in zmm1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:r/m (r, w)

imm8

N/A

VEX.vvvv (w)

ModRM:r/m (r)

imm8

N/A

Full Mem

EVEX.vvvv (w)

ModRM:r/m (r)

imm8

N/A

Description

Shifts the destination operand (first operand) to the right by the number of bytes specified in the count operand

(second operand). The empty high-order bytes are cleared (set to all 0s). If the value specified by the count

operand is greater than 15, the destination operand is set to all 0s. The count operand is an 8-bit immediate.

In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to

access additional registers (XMM8-XMM15).

128-bit Legacy SSE version: The source and destination operands are the same. Bits (MAXVL-1:128) of the corre-

sponding YMM destination register remain unchanged.

VEX.128 encoded version: The source and destination operands are XMM registers. Bits (MAXVL-1:128) of the

destination YMM register are zeroed.

VEX.256 encoded version: The source operand is a YMM register. The destination operand is a YMM register. The

count operand applies to both the low and high 128-bit lanes.

VEX.256 encoded version: The source operand is YMM register. The destination operand is an YMM register. Bits

(MAXVL-1:256) of the corresponding ZMM register are zeroed. The count operand applies to both the low and high

128-bit lanes.

EVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location.

The destination operand is a ZMM/YMM/XMM register. The count operand applies to each 128-bit lanes.

Note: VEX.vvvv/EVEX.vvvv encodes the destination register.

PSRLDQ—Shift Double Quadword Right Logical

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INSTRUCTION SET REFERENCE, M-U

Operation

VPSRLDQ (EVEX.512 encoded version)

TEMP := COUNT

IF (TEMP > 15) THEN TEMP := 16; FI

DEST[127:0] := SRC[127:0] >> (TEMP * 8)

DEST[255:128] := SRC[255:128] >> (TEMP * 8)

DEST[383:256] := SRC[383:256] >> (TEMP * 8)

DEST[511:384] := SRC[511:384] >> (TEMP * 8)

DEST[MAXVL-1:512] := 0;

VPSRLDQ (VEX.256 and EVEX.256 encoded version)

TEMP := COUNT

IF (TEMP > 15) THEN TEMP := 16; FI

DEST[127:0] := SRC[127:0] >> (TEMP * 8)

DEST[255:128] := SRC[255:128] >> (TEMP * 8)

DEST[MAXVL-1:256] := 0;

VPSRLDQ (VEX.128 and EVEX.128 encoded version)

TEMP := COUNT

IF (TEMP > 15) THEN TEMP := 16; FI

DEST := SRC >> (TEMP * 8)

DEST[MAXVL-1:128] := 0;

PSRLDQ(128-bit Legacy SSE version)

TEMP := COUNT

IF (TEMP > 15) THEN TEMP := 16; FI

DEST := DEST >> (TEMP * 8)

DEST[MAXVL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalents

(V)PSRLDQ __m128i _mm_srli_si128 ( __m128i a, int imm)

VPSRLDQ __m256i _mm256_bsrli_epi128 ( __m256i, const int)

VPSRLDQ __m512i _mm512_bsrli_epi128 ( __m512i, int)

Flags Affected

None.

Numeric Exceptions

None.

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-24, “Type 7 Class Exception Conditions”.

EVEX-encoded instruction, see Exceptions Type E4NF.nb in Table 2-50, “Type E4NF Class Exception Conditions”.

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Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 85