Content      ..     80      81      82      83     ..

Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 82

INSTRUCTION SET REFERENCE, M-U

PCMPGTQ—Compare Packed Data for Greater Than

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

En

Mode

Feature

Support

Flag

66 0F 38 37 /r

A

V/V

SSE4_2

Compare packed signed qwords in xmm2/m128

PCMPGTQ xmm1,xmm2/m128

and xmm1 for greater than.

VEX.128.66.0F38.WIG 37 /r

B

V/V

AVX

Compare packed signed qwords in xmm2 and

VPCMPGTQ xmm1, xmm2, xmm3/m128

xmm3/m128 for greater than.

VEX.256.66.0F38.WIG 37 /r

B

V/V

AVX2

Compare packed signed qwords in ymm2 and

VPCMPGTQ ymm1, ymm2, ymm3/m256

ymm3/m256 for greater than.

EVEX.128.66.0F38.W1 37 /r

C

V/V

AVX512VL

Compare Greater between int64 vector xmm2 and

VPCMPGTQ k1 {k2}, xmm2,

AVX512F

int64 vector xmm3/m128/m64bcst, and set

xmm3/m128/m64bcst

vector mask k1 to reflect the zero/nonzero status

of each element of the result, under writemask.

EVEX.256.66.0F38.W1 37 /r

C

V/V

AVX512VL

Compare Greater between int64 vector ymm2 and

VPCMPGTQ k1 {k2}, ymm2,

AVX512F

int64 vector ymm3/m256/m64bcst, and set

ymm3/m256/m64bcst

vector mask k1 to reflect the zero/nonzero status

of each element of the result, under writemask.

EVEX.512.66.0F38.W1 37 /r

C

V/V

AVX512F

Compare Greater between int64 vector zmm2 and

VPCMPGTQ k1 {k2}, zmm2, zmm3/m512/m64bcst

int64 vector zmm3/m512/m64bcst, and set

vector mask k1 to reflect the zero/nonzero status

of each element of the result, under writemask.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

N/A

B

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

C

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs an SIMD signed compare for the packed quadwords in the destination operand (first operand) and the

source operand (second operand). If the data element in the first (destination) operand is greater than the

corresponding element in the second (source) operand, the corresponding data element in the destination is set

to all 1s; otherwise, it is set to 0s.

128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The

first source operand and destination operand are XMM registers. Bits (MAXVL-1:128) of the corresponding YMM

destination register remain unchanged.

VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The

first source operand and destination operand are XMM registers. Bits (MAXVL-1:128) of the corresponding YMM

register are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register

or a 256-bit memory location. The destination operand is a YMM register.

EVEX encoded VPCMPGTD/Q: The first source operand (second operand) is a ZMM/YMM/XMM register. The second

source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector

broadcasted from a 64-bit memory location. The destination operand (first operand) is a mask register updated

according to the writemask k2.

4-270

Vol. 2B

PCMPGTQ—Compare Packed Data for Greater Than

INSTRUCTION SET REFERENCE, M-U

PCMPISTRI—Packed Compare Implicit Length Strings, Return Index

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

En

Mode

Feature

Support

Flag

66 0F 3A 63 /r imm8

RM

V/V

SSE4_2

Perform a packed comparison of string data

PCMPISTRI xmm1, xmm2/m128, imm8

with implicit lengths, generating an index, and

storing the result in ECX.

VEX.128.66.0F3A.WIG 63 /r ib

RM

V/V

AVX

Perform a packed comparison of string data

VPCMPISTRI xmm1, xmm2/m128, imm8

with implicit lengths, generating an index, and

storing the result in ECX.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RM

ModRM:reg (r)

ModRM:r/m (r)

imm8

N/A

Description

The instruction compares data from two strings based on the encoded value in the imm8 control byte (see Section

4.1, “Imm8 Control Byte Operation for PCMPESTRI / PCMPESTRM / PCMPISTRI / PCMPISTRM”), and generates an

index stored to ECX.

Each string is represented by a single value. The value is an xmm (or possibly m128 for the second operand) which

contains the data elements of the string (byte or word data). Each input byte/word is augmented with a

valid/invalid tag. A byte/word is considered valid only if it has a lower index than the least significant null

byte/word. (The least significant null byte/word is also considered invalid.)

The comparison and aggregation operations are performed according to the encoded value of imm8 bit fields (see

Section 4.1). The index of the first (or last, according to imm8[6]) set bit of IntRes2 is returned in ECX. If no bits

are set in IntRes2, ECX is set to 16 (8).

Note that the Arithmetic Flags are written in a non-standard manner in order to supply the most relevant informa-

tion:

CFlag - Reset if IntRes2 is equal to zero, set otherwise

ZFlag - Set if any byte/word of xmm2/mem128 is null, reset otherwise

SFlag - Set if any byte/word of xmm1 is null, reset otherwise

OFlag -IntRes2[0]

AFlag - Reset

PFlag - Reset

Note: In VEX.128 encoded version, VEX.vvvv is reserved and must be 1111b, VEX.L must be 0, otherwise the

instruction will #UD.

Effective Operand Size

Operating mode/size

Operand 1

Operand 2

Result

16 bit

xmm

xmm/m128

ECX

32 bit

xmm

xmm/m128

ECX

64 bit

xmm

xmm/m128

ECX

Intel C/C++ Compiler Intrinsic Equivalent For Returning Index

int

_mm_cmpistri (__m128i a, __m128i b, const int mode);

PCMPISTRI—Packed Compare Implicit Length Strings, Return Index

Vol. 2B

4-273

INSTRUCTION SET REFERENCE, M-U

PCMPISTRM—Packed Compare Implicit Length Strings, Return Mask

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

En

Mode

Feature

Support

Flag

66 0F 3A 62 /r imm8

RM

V/V

SSE4_2

Perform a packed comparison of string data

PCMPISTRM xmm1, xmm2/m128, imm8

with implicit lengths, generating a mask, and

storing the result in XMM0.

VEX.128.66.0F3A.WIG 62 /r ib

RM

V/V

AVX

Perform a packed comparison of string data

VPCMPISTRM xmm1, xmm2/m128, imm8

with implicit lengths, generating a Mask, and

storing the result in XMM0.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RM

ModRM:reg (r)

ModRM:r/m (r)

imm8

N/A

Description

The instruction compares data from two strings based on the encoded value in the imm8 byte (see Section 4.1,

“Imm8 Control Byte Operation for PCMPESTRI / PCMPESTRM / PCMPISTRI / PCMPISTRM”) generating a mask

stored to XMM0.

Each string is represented by a single value. The value is an xmm (or possibly m128 for the second operand) which

contains the data elements of the string (byte or word data). Each input byte/word is augmented with a

valid/invalid tag. A byte/word is considered valid only if it has a lower index than the least significant null

byte/word. (The least significant null byte/word is also considered invalid.)

The comparison and aggregation operation are performed according to the encoded value of imm8 bit fields (see

Section 4.1). As defined by imm8[6], IntRes2 is then either stored to the least significant bits of XMM0 (zero

extended to 128 bits) or expanded into a byte/word-mask and then stored to XMM0.

Note that the Arithmetic Flags are written in a non-standard manner in order to supply the most relevant informa-

tion:

CFlag - Reset if IntRes2 is equal to zero, set otherwise

ZFlag - Set if any byte/word of xmm2/mem128 is null, reset otherwise

SFlag - Set if any byte/word of xmm1 is null, reset otherwise

OFlag - IntRes2[0]

AFlag - Reset

PFlag - Reset

Note: In VEX.128 encoded versions, bits (MAXVL-1:128) of XMM0 are zeroed. VEX.vvvv is reserved and must be

1111b, VEX.L must be 0, otherwise the instruction will #UD.

Effective Operand Size

Operating mode/size

Operand 1

Operand 2

Result

16 bit

xmm

xmm/m128

XMM0

32 bit

xmm

xmm/m128

XMM0

64 bit

xmm

xmm/m128

XMM0

Intel C/C++ Compiler Intrinsic Equivalent For Returning Mask

__m128i _mm_cmpistrm (__m128i a, __m128i b, const int mode);

PCMPISTRM—Packed Compare Implicit Length Strings, Return Mask

Vol. 2B

4-275

INSTRUCTION SET REFERENCE, M-U

PCONFIG—Platform Configuration

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

NP 0F 01 C5

A

V/V

PCONFIG

This instruction is used to execute functions for

PCONFIG

configuring platform features.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

N/A

N/A

N/A

N/A

Description

PCONFIG allows software to configure certain platform features. PCONFIG supports multiple leaf functions, with a

leaf function identified by the value in EAX. The registers RBX, RCX, and RDX may provide input or output informa-

tion for certain leaves. All leaves write status information to EAX but do not modify RBX, RCX, or RDX unless they

are being used as leaf-specific output.

Each PCONFIG leaf function applies to a specific hardware block called a PCONFIG target, and each PCONFIG target

is associated with a numerical target identifier. Supported target identifiers are enumerated, along with other

PCONFIG capabilities, in the sub-leaves of the PCONFIG-information leaf of CPUID (EAX = 1BH). An attempt to

execute an undefined leaf function, or a leaf function that applies to an unsupported target identifier, results in a

general-protection exception (#GP). (In the future, the PCONFIG-information leaf of CPUID may enumerate

PCONFIG capabilities in addition to the supported target identifiers.)

Addresses and operands are 32 bits outside 64-bit mode and are 64 bits in 64-bit mode. The value of CS.D does

not affect operand size or address size.

Table 4-15 shows the leaf encodings for PCONFIG, and Table 4-16 shows the leaf register usage for PCONFIG.

Table 4-15. PCONFIG Leaf Encodings

Leaf

Encoding

Description

MKTME_KEY_PROGRAM

00000000H

This leaf is used to program the key and encryption mode associated

with a KeyID.

RESERVED

00000001H - FFFFFFFFH

Reserved for future use (#GP(0) if used).

Table 4-16. PCONFIG Leaf Register Usage

Leaf

RBX

RCX

RDX

MKTME_KEY_PROGRAM

Input only.

Input only.

Input only.

RESERVED

Reserved for future use.

Reserved for future use.

Reserved for future use.

The MKTME_KEY_PROGRAM leaf of PCONFIG pertains to the MKTME¹ target, which has target identifier 1. It is used

by software to manage the key associated with a KeyID. The leaf function is invoked by setting the leaf value of 0

in EAX and the address of MKTME_KEY_PROGRAM_STRUCT in RBX. Successful execution of the leaf clears RAX (set

to zero) and ZF, CF, PF, AF, OF, and SF are cleared. In case of failure, the failure reason is indicated in RAX with ZF

set to 1 and CF, PF, AF, OF, and SF are cleared. The MKTME_KEY_PROGRAM leaf uses the

MKTME_KEY_PROGRAM_STRUCT in memory shown in Table 4-17.

1. Further details on MKTME usage can be found here:

https://software.intel.com/sites/default/files/managed/a5/16/Multi-Key-Total-Memory-Encryption-Spec.pdf

PCONFIG—Platform Configuration

Vol. 2B

4-277

INSTRUCTION SET REFERENCE, M-U

Table 4-17. MKTME_KEY_PROGRAM_STRUCT Format

Field

Offset (bytes)

Size (bytes)

Comments

KEYID

0

2

Key Identifier.

KEYID_CTRL

2

4

KeyID control:

• Bits [7:0]: COMMAND.

• Bits [23:8]: ENC_ALG.

• Bits [31:24]: Reserved, must be zero.

RESERVED

6

58

Reserved, must be zero.

KEY_FIELD_1

64

64

Software supplied KeyID data key or entropy for KeyID data key.

KEY_FIELD_2

128

64

Software supplied KeyID tweak key or entropy for KeyID tweak key.

A description of each of the fields in MKTME_KEY_PROGRAM_STRUCT is provided below:

• KEYID: Key Identifier being programmed to the MKTME engine.

• KEYID_CTRL: The KEYID_CTRL field carries two sub-fields used by software to control the behavior of a

KeyID: Command and KeyID encryption algorithm.

The command used controls the encryption mode for a KeyID. Table 4-18 provides a summary of the

commands supported.

Table 4-18. Supported Key Programming Commands

Command

Encoding

Description

KEYID_SET_KEY_DIRECT

0

Software uses this mode to directly program a key for use with KeyID.

KEYID_SET_KEY_RANDOM

1

CPU generates and assigns an ephemeral key for use with a KeyID. Each time the

instruction is executed, the CPU generates a new key using a hardware random

number generator and the keys are discarded on reset.

KEYID_CLEAR_KEY

2

Clear the (software programmed) key associated with the KeyID. On execution of this

command, the KeyID gets TME behavior (encrypt with platform TME key or bypass

TME encryption).

KEYID_NO_ENCRYPT

3

Do not encrypt memory when this KeyID is in use.

The encryption algorithm field (ENC_ALG) allows software to select one of the activated encryption algorithms

for the KeyID. The BIOS can activate a set of algorithms to allow for use when programming keys using the

IA32_TME_ACTIVATE MSR (does not apply to KeyID 0 which uses the TME policy when TME encryption is not

bypassed). The processor checks to ensure that the algorithm selected by software is one of the algorithms

that has been activated by the BIOS.

• KEY_FIELD_1: This field carries the software supplied data key to be used for the KeyID if the direct key

programming option is used (KEYID_SET_KEY_DIRECT). When the random key programming option is used

(KEYID_SET_KEY_RANDOM), this field carries the software supplied entropy to be mixed in the CPU generated

random data key. It is software's responsibility to ensure that the key supplied for the direct programming

option or the entropy supplied for the random programming option does not result in weak keys. There are no

explicit checks in the instruction to detect or prevent weak keys. When AES XTS-128 is used, the upper 48B are

treated as reserved and must be zeroed out by software before executing the instruction.

• KEY_FIELD_2: This field carries the software supplied tweak key to be used for the KeyID if the direct key

programming option is used (KEYID_SET_KEY_DIRECT). When the random key programming option is used

(KEYID_SET_KEY_RANDOM), this field carries the software supplied entropy to be mixed in the CPU generated

random tweak key. It is software's responsibility to ensure that the key supplied for the direct programming

option or the entropy supplied for the random programming option does not result in weak keys. There are no

explicit checks in the instruction to detect or prevent weak keys. When AES XTS-128 is used, the upper 48B are

treated as reserved and must be zeroed out by software before executing the instruction.

All KeyIDs default to TME behavior (encrypt with TME key or bypass encryption) on MKTME activation.

Software can at any point decide to change the key for a KeyID using the PCONFIG instruction. Change of

4-278

Vol. 2B

PCONFIG—Platform Configuration

INSTRUCTION SET REFERENCE, M-U

keys for a KeyID does NOT change the state of the TLB caches or memory pipeline. It is software's responsi-

bility to take appropriate actions to ensure correct behavior.

Table 4-19 shows the return values associated with the MKTME_KEY_PROGRAM leaf of PCONFIG. On

instruction execution, RAX is populated with the return value.

Table 4-19. Supported Key Error Codes

Return Value

Encoding

Description

PROG_SUCCESS

0

KeyID was successfully programmed.

INVALID_PROG_CMD

1

Invalid KeyID programming command.

ENTROPY_ERROR

2

Insufficient entropy.

INVALID_KEYID

3

KeyID not valid.

INVALID_ENC_ALG

4

Invalid encryption algorithm chosen (not supported).

DEVICE_BUSY

5

Failure to access key table.

PCONFIG Concurrency

In a scenario where the MKTME_KEY_PROGRAM leaf of PCONFIG is executed concurrently on multiple logical

processors, only one logical processor will succeed in updating the key table. PCONFIG execution will return with

an error code (DEVICE_BUSY) on other logical processors and software must retry. In cases where the instruction

execution fails with a DEVICE_BUSY error code, the key table is not updated, thereby ensuring that either the key

table is updated in its entirety with the information for a KeyID, or it is not updated at all. In order to accomplish

this, the MKTME_KEY_PROGRAM leaf of PCONFIG maintains a writer lock for updating the key table. This lock is

referred to as the Key table lock and denoted in the instruction flows as KEY_TABLE_LOCK. The lock can either be

unlocked, when no logical processor is holding the lock (also the initial state of the lock) or be in an exclusive state

where a logical processor is trying to update the key table. There can be only one logical processor holding the lock

in exclusive state. The lock, being exclusive, can only be acquired when the lock is in unlocked state.

PCONFIG uses the following syntax to acquire KEY_TABLE_LOCK in exclusive mode and release the lock:

• KEY_TABLE_LOCK.ACQUIRE(WRITE)

• KEY_TABLE_LOCK.RELEASE()

Operation

Table 4-20. PCONFIG Operation Variables

Variable Name

Type

Size

Description

(Bytes)

TMP_KEY_PROGRAM_STRUCT

MKTME_KEY_PROGRAM_STRUCT

192

Structure holding the key programming structure.

TMP_RND_DATA_KEY

UINT128

16

Random data key generated for random key

programming option.

TMP_RND_TWEAK_KEY

UINT128

16

Random tweak key generated for random key

programming option.

PCONFIG—Platform Configuration

Vol. 2B

4-279

INSTRUCTION SET REFERENCE, M-U

PDEP—Parallel Bits Deposit

Opcode/

Op/

64/32

CPUID

Description

Instruction

En

-bit

Feature

Mode

Flag

VEX.LZ.F2.0F38.W0 F5 /r

RVM

V/V

BMI2

Parallel deposit of bits from r32b using mask in r/m32, result is writ-

PDEP r32a, r32b, r/m32

ten to r32a.

VEX.LZ.F2.0F38.W1 F5 /r

RVM

V/N.E.

BMI2

Parallel deposit of bits from r64b using mask in r/m64, result is writ-

PDEP r64a, r64b, r/m64

ten to r64a.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RVM

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

PDEP uses a mask in the second source operand (the third operand) to transfer/scatter contiguous low order bits in

the first source operand (the second operand) into the destination (the first operand). PDEP takes the low bits from

the first source operand and deposit them in the destination operand at the corresponding bit locations that are set

in the second source operand (mask). All other bits (bits not set in mask) in destination are set to zero.

SRC1

S₃₁

S₃₀

S₂₉ S₂₈

S₂₇

S₇

S₆

S₅

S₄

S₃

S₂

S₁

S

0

SRC2

0

0

0

1

0

1

0

1

0

0

1

0

0

(mask)

DEST

0

0

0

S₃

0

S₂

0

S₁

0

0

S₀

0

0

bit 0

bit 31

Figure 4-8. PDEP Example

This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in

64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt

to execute this instruction with VEX.L not equal to 0 will cause #UD.

Operation

TEMP := SRC1;

MASK := SRC2;

DEST := 0 ;

m := 0, k := 0;

DO WHILE m < OperandSize

IF MASK[ m] = 1 THEN

DEST[ m] := TEMP[ k];

k := k+ 1;

FI

m := m+ 1;

OD

4-284

Vol. 2B

PDEP—Parallel Bits Deposit

INSTRUCTION SET REFERENCE, M-U

PEXT—Parallel Bits Extract

Opcode/

Op/

64/32

CPUID

Description

Instruction

En

-bit

Feature

Mode

Flag

VEX.LZ.F3.0F38.W0 F5 /r

RVM

V/V

BMI2

Parallel extract of bits from r32b using mask in r/m32, result is writ-

PEXT r32a, r32b, r/m32

ten to r32a.

VEX.LZ.F3.0F38.W1 F5 /r

RVM

V/N.E.

BMI2

Parallel extract of bits from r64b using mask in r/m64, result is writ-

PEXT r64a, r64b, r/m64

ten to r64a.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RVM

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

PEXT uses a mask in the second source operand (the third operand) to transfer either contiguous or non-contig-

uous bits in the first source operand (the second operand) to contiguous low order bit positions in the destination

(the first operand). For each bit set in the MASK, PEXT extracts the corresponding bits from the first source operand

and writes them into contiguous lower bits of destination operand. The remaining upper bits of destination are

zeroed.

SRC1

S₃₁

S₃₀

S₂₉ S₂₈

S₂₇

S₇

S₆

S₅

S₄

S₃

S₂

S₁

S₀

SRC2

0

0

0

1

0

1

0

1

0

0

1

0

0

(mask)

DEST

0

0

0

0

0

0

0

0

0

S₂₈

S₇

S₅

S₂

bit 0

bit 31

Figure 4-9. PEXT Example

This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in

64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt

to execute this instruction with VEX.L not equal to 0 will cause #UD.

4-286

Vol. 2B

PEXT—Parallel Bits Extract

INSTRUCTION SET REFERENCE, M-U

PEXTRB/PEXTRD/PEXTRQ—Extract Byte/Dword/Qword

Opcode/

Op/ En

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

66 0F 3A 14 /r ib

A

V/V

SSE4_1

Extract a byte integer value from xmm2 at the

PEXTRB reg/m8, xmm2, imm8

source byte offset specified by imm8 into reg or

m8. The upper bits of r32 or r64 are zeroed.

66 0F 3A 16 /r ib

A

V/V

SSE4_1

Extract a dword integer value from xmm2 at the

PEXTRD r/m32, xmm2, imm8

source dword offset specified by imm8 into r/m32.

66 REX.W 0F 3A 16 /r ib

A

V/N.E.

SSE4_1

Extract a qword integer value from xmm2 at the

PEXTRQ r/m64, xmm2, imm8

source qword offset specified by imm8 into r/m64.

VEX.128.66.0F3A.W0 14 /r ib

A

V¹/V

AVX

Extract a byte integer value from xmm2 at the

VPEXTRB reg/m8, xmm2, imm8

source byte offset specified by imm8 into reg or

m8. The upper bits of r64/r32 is filled with zeros.

VEX.128.66.0F3A.W0 16 /r ib

A

V/V

AVX

Extract a dword integer value from xmm2 at the

VPEXTRD r32/m32, xmm2, imm8

source dword offset specified by imm8 into

r32/m32.

VEX.128.66.0F3A.W1 16 /r ib

A

V/I²

AVX

Extract a qword integer value from xmm2 at the

VPEXTRQ r64/m64, xmm2, imm8

source dword offset specified by imm8 into

r64/m64.

EVEX.128.66.0F3A.WIG 14 /r ib

B

V/V

AVX512BW

Extract a byte integer value from xmm2 at the

VPEXTRB reg/m8, xmm2, imm8

source byte offset specified by imm8 into reg or

m8. The upper bits of r64/r32 is filled with zeros.

EVEX.128.66.0F3A.W0 16 /r ib

B

V/V

AVX512DQ

Extract a dword integer value from xmm2 at the

VPEXTRD r32/m32, xmm2, imm8

source dword offset specified by imm8 into

r32/m32.

EVEX.128.66.0F3A.W1 16 /r ib

B

V/N.E.²

AVX512DQ

Extract a qword integer value from xmm2 at the

VPEXTRQ r64/m64, xmm2, imm8

source dword offset specified by imm8 into

r64/m64.

NOTES:

1. In 64-bit mode, VEX.W1 is ignored for VPEXTRB (similar to legacy REX.W=1 prefix in PEXTRB).

2. VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is used.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:r/m (w)

ModRM:reg (r)

imm8

N/A

B

Tuple1 Scalar

ModRM:r/m (w)

ModRM:reg (r)

imm8

N/A

Description

Extract a byte/dword/qword integer value from the source XMM register at a byte/dword/qword offset determined

from imm8[3:0]. The destination can be a register or byte/dword/qword memory location. If the destination is a

register, the upper bits of the register are zero extended.

In legacy non-VEX encoded version and if the destination operand is a register, the default operand size in 64-bit

mode for PEXTRB/PEXTRD is 64 bits, the bits above the least significant byte/dword data are filled with zeros.

PEXTRQ is not encodable in non-64-bit modes and requires REX.W in 64-bit mode.

Note: In VEX.128 encoded versions, VEX.vvvv is reserved and must be 1111b, VEX.L must be 0, otherwise the

instruction will #UD. In EVEX.128 encoded versions, EVEX.vvvv is reserved and must be 1111b, EVEX.L”L must be

0, otherwise the instruction will #UD. If the destination operand is a register, the default operand size in 64-bit

mode for VPEXTRB/VPEXTRD is 64 bits, the bits above the least significant byte/word/dword data are filled with

zeros.

4-288

Vol. 2B

PEXTRB/PEXTRD/PEXTRQ—Extract Byte/Dword/Qword

INSTRUCTION SET REFERENCE, M-U

PEXTRW—Extract Word

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

En

Mode

Feature Flag

Support

NP 0F C5 /r ib¹

A

V/V

SSE

Extract the word specified by imm8 from mm and

move it to reg, bits 15-0. The upper bits of r32 or

PEXTRW reg, mm, imm8

r64 is zeroed.

66 0F C5 /r ib

A

V/V

SSE2

Extract the word specified by imm8 from xmm

and move it to reg, bits 15-0. The upper bits of

PEXTRW reg, xmm, imm8

r32 or r64 is zeroed.

66 0F 3A 15 /r ib

B

V/V

SSE4_1

Extract the word specified by imm8 from xmm

PEXTRW reg/m16, xmm, imm8

and copy it to lowest 16 bits of reg or m16. Zero-

extend the result in the destination, r32 or r64.

VEX.128.66.0F.W0 C5 /r ib

A

V²/V

AVX

Extract the word specified by imm8 from xmm1

VPEXTRW reg, xmm1, imm8

and move it to reg, bits 15:0. Zero-extend the

result. The upper bits of r64/r32 is filled with

zeros.

VEX.128.66.0F3A.W0 15 /r ib

B

V/V

AVX

Extract a word integer value from xmm2 at the

VPEXTRW reg/m16, xmm2, imm8

source word offset specified by imm8 into reg or

m16. The upper bits of r64/r32 is filled with zeros.

EVEX.128.66.0F.WIG C5 /r ib

A

V/V

AVX512BW

Extract the word specified by imm8 from xmm1

VPEXTRW reg, xmm1, imm8

and move it to reg, bits 15:0. Zero-extend the

result. The upper bits of r64/r32 is filled with

zeros.

EVEX.128.66.0F3A.WIG 15 /r ib

C

V/V

AVX512BW

Extract a word integer value from xmm2 at the

VPEXTRW reg/m16, xmm2, imm8

source word offset specified by imm8 into reg or

m16. The upper bits of r64/r32 is filled with zeros.

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2A and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX

Registers” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

2. In 64-bit mode, VEX.W1 is ignored for VPEXTRW (similar to legacy REX.W=1 prefix in PEXTRW).

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (w)

ModRM:r/m (r)

imm8

N/A

B

N/A

ModRM:r/m (w)

ModRM:reg (r)

imm8

N/A

C

Tuple1 Scalar

ModRM:r/m (w)

ModRM:reg (r)

imm8

N/A

Description

Copies the word in the source operand (second operand) specified by the count operand (third operand) to the

destination operand (first operand). The source operand can be an MMX technology register or an XMM register.

The destination operand can be the low word of a general-purpose register or a 16-bit memory address. The count

operand is an 8-bit immediate. When specifying a word location in an MMX technology register, the 2 least-signifi-

cant bits of the count operand specify the location; for an XMM register, the 3 least-significant bits specify the loca-

tion. The content of the destination register above bit 16 is cleared (set to all 0s).

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers

(XMM8-XMM15, R8-15). If the destination operand is a general-purpose register, the default operand size is 64-bits

in 64-bit mode.

PEXTRW—Extract Word

Vol. 2B

4-291

INSTRUCTION SET REFERENCE, M-U

PHADDW/PHADDD—Packed Horizontal Add

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

En

Mode

Feature

Support

Flag

NP 0F 38 01 /r¹

RM

V/V

SSSE3

Add 16-bit integers horizontally, pack to mm1.

PHADDW mm1, mm2/m64

66 0F 38 01 /r

RM

V/V

SSSE3

Add 16-bit integers horizontally, pack to

xmm1.

PHADDW xmm1, xmm2/m128

NP 0F 38 02 /r

RM

V/V

SSSE3

Add 32-bit integers horizontally, pack to mm1.

PHADDD mm1, mm2/m64

66 0F 38 02 /r

RM

V/V

SSSE3

Add 32-bit integers horizontally, pack to

xmm1.

PHADDD xmm1, xmm2/m128

VEX.128.66.0F38.WIG 01 /r

RVM

V/V

AVX

Add 16-bit integers horizontally, pack to

xmm1.

VPHADDW xmm1, xmm2, xmm3/m128

VEX.128.66.0F38.WIG 02 /r

RVM

V/V

AVX

Add 32-bit integers horizontally, pack to

xmm1.

VPHADDD xmm1, xmm2, xmm3/m128

VEX.256.66.0F38.WIG 01 /r

RVM

V/V

AVX2

Add 16-bit signed integers horizontally, pack

to ymm1.

VPHADDW ymm1, ymm2, ymm3/m256

VEX.256.66.0F38.WIG 02 /r

RVM

V/V

AVX2

Add 32-bit signed integers horizontally, pack

to ymm1.

VPHADDD ymm1, ymm2, ymm3/m256

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2A and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Reg-

isters” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RM

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

N/A

RVM

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

(V)PHADDW adds two adjacent 16-bit signed integers horizontally from the source and destination operands and

packs the 16-bit signed results to the destination operand (first operand). (V)PHADDD adds two adjacent 32-bit

signed integers horizontally from the source and destination operands and packs the 32-bit signed results to the

destination operand (first operand). When the source operand is a 128-bit memory operand, the operand must be

aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.

Note that these instructions can operate on either unsigned or signed (two’s complement notation) integers;

however, it does not set bits in the EFLAGS register to indicate overflow and/or a carry. To prevent undetected over-

flow conditions, software must control the ranges of the values operated on.

Legacy SSE instructions: Both operands can be MMX registers. The second source operand can be an MMX register

or a 64-bit memory location.

128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source

operand can be an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding YMM

destination register remain unchanged.

In 64-bit mode, use the REX prefix to access additional registers.

4-294

Vol. 2B

PHADDW/PHADDD—Packed Horizontal Add

INSTRUCTION SET REFERENCE, M-U

VEX.128 encoded version: The first source and destination operands are XMM registers. The second source

operand can be an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding YMM

register are zeroed.

VEX.256 encoded version: Horizontal addition of two adjacent data elements of the low 16-bytes of the first and

second source operands are packed into the low 16-bytes of the destination operand. Horizontal addition of two

adjacent data elements of the high 16-bytes of the first and second source operands are packed into the high 16-

bytes of the destination operand. The first source and destination operands are YMM registers. The second source

operand can be an YMM register or a 256-bit memory location.

SRC2

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

X7

X6

X5

X4

X3

X2

X1

X0

SRC1

S7

S3

S3

S4

S3

S2

S1

S0

255

0

Dest

Figure 4-10. 256-bit VPHADDD Instruction Operation

Operation

PHADDW (with 64-bit operands)

mm1[15-0] = mm1[31-16] + mm1[15-0];

mm1[31-16] = mm1[63-48] + mm1[47-32];

mm1[47-32] = mm2/m64[31-16] + mm2/m64[15-0];

mm1[63-48] = mm2/m64[63-48] + mm2/m64[47-32];

PHADDW (with 128-bit operands)

xmm1[15-0] = xmm1[31-16] + xmm1[15-0];

xmm1[31-16] = xmm1[63-48] + xmm1[47-32];

xmm1[47-32] = xmm1[95-80] + xmm1[79-64];

xmm1[63-48] = xmm1[127-112] + xmm1[111-96];

xmm1[79-64] = xmm2/m128[31-16] + xmm2/m128[15-0];

xmm1[95-80] = xmm2/m128[63-48] + xmm2/m128[47-32];

xmm1[111-96] = xmm2/m128[95-80] + xmm2/m128[79-64];

xmm1[127-112] = xmm2/m128[127-112] + xmm2/m128[111-96];

VPHADDW (VEX.128 encoded version)

DEST[15:0] := SRC1[31:16] + SRC1[15:0]

DEST[31:16] := SRC1[63:48] + SRC1[47:32]

DEST[47:32] := SRC1[95:80] + SRC1[79:64]

DEST[63:48] := SRC1[127:112] + SRC1[111:96]

DEST[79:64] := SRC2[31:16] + SRC2[15:0]

DEST[95:80] := SRC2[63:48] + SRC2[47:32]

DEST[111:96] := SRC2[95:80] + SRC2[79:64]

DEST[127:112] := SRC2[127:112] + SRC2[111:96]

DEST[MAXVL-1:128] := 0

PHADDW/PHADDD—Packed Horizontal Add

Vol. 2B

4-295

INSTRUCTION SET REFERENCE, M-U

PHADDSW—Packed Horizontal Add and Saturate

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

En

Mode

Feature

Support

Flag

NP 0F 38 03 /r¹

RM

V/V

SSSE3

Add 16-bit signed integers horizontally, pack

saturated integers to mm1.

PHADDSW mm1, mm2/m64

66 0F 38 03 /r

RM

V/V

SSSE3

Add 16-bit signed integers horizontally, pack

saturated integers to xmm1.

PHADDSW xmm1, xmm2/m128

VEX.128.66.0F38.WIG 03 /r

RVM

V/V

AVX

Add 16-bit signed integers horizontally, pack

saturated integers to xmm1.

VPHADDSW xmm1, xmm2, xmm3/m128

VEX.256.66.0F38.WIG 03 /r

RVM

V/V

AVX2

Add 16-bit signed integers horizontally, pack

saturated integers to ymm1.

VPHADDSW ymm1, ymm2, ymm3/m256

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2A and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX

Registers” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RM

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

N/A

RVM

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

(V)PHADDSW adds two adjacent signed 16-bit integers horizontally from the source and destination operands and

saturates the signed results; packs the signed, saturated 16-bit results to the destination operand (first operand)

When the source operand is a 128-bit memory operand, the operand must be aligned on a 16-byte boundary or a

general-protection exception (#GP) will be generated.

Legacy SSE version: Both operands can be MMX registers. The second source operand can be an MMX register or a

64-bit memory location.

128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source

operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding YMM destina-

tion register remain unchanged.

In 64-bit mode, use the REX prefix to access additional registers.

VEX.128 encoded version: The first source and destination operands are XMM registers. The second source

operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the destination YMM register are

zeroed.

VEX.256 encoded version: The first source and destination operands are YMM registers. The second source

operand can be an YMM register or a 256-bit memory location.

Operation

PHADDSW (with 64-bit operands)

mm1[15-0] = SaturateToSignedWord((mm1[31-16] + mm1[15-0]);

mm1[31-16] = SaturateToSignedWord(mm1[63-48] + mm1[47-32]);

mm1[47-32] = SaturateToSignedWord(mm2/m64[31-16] + mm2/m64[15-0]);

mm1[63-48] = SaturateToSignedWord(mm2/m64[63-48] + mm2/m64[47-32]);

4-298

Vol. 2B

PHADDSW—Packed Horizontal Add and Saturate

INSTRUCTION SET REFERENCE, M-U

PHMINPOSUW—Packed Horizontal Word Minimum

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

En

Mode

Feature

Support

Flag

66 0F 38 41 /r

RM

V/V

SSE4_1

Find the minimum unsigned word in

PHMINPOSUW xmm1, xmm2/m128

xmm2/m128 and place its value in the low

word of xmm1 and its index in the second-

lowest word of xmm1.

VEX.128.66.0F38.WIG 41 /r

RM

V/V

AVX

Find the minimum unsigned word in

VPHMINPOSUW xmm1, xmm2/m128

xmm2/m128 and place its value in the low

word of xmm1 and its index in the second-

lowest word of xmm1.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RM

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

Description

Determine the minimum unsigned word value in the source operand (second operand) and place the unsigned

word in the low word (bits 0-15) of the destination operand (first operand). The word index of the minimum value

is stored in bits 16-18 of the destination operand. The remaining upper bits of the destination are set to zero.

128-bit Legacy SSE version: Bits (MAXVL-1:128) of the corresponding XMM destination register remain

unchanged.

VEX.128 encoded version: Bits (MAXVL-1:128) of the destination XMM register are zeroed. VEX.vvvv is reserved

and must be 1111b, VEX.L must be 0, otherwise the instruction will #UD.

Operation

PHMINPOSUW (128-bit Legacy SSE version)

INDEX := 0;

MIN := SRC[15:0]

IF (SRC[31:16] < MIN)

THEN INDEX := 1; MIN := SRC[31:16]; FI;

IF (SRC[47:32] < MIN)

THEN INDEX := 2; MIN := SRC[47:32]; FI;

* Repeat operation for words 3 through 6

IF (SRC[127:112] < MIN)

THEN INDEX := 7; MIN := SRC[127:112]; FI;

DEST[15:0] := MIN;

DEST[18:16] := INDEX;

DEST[127:19] := 0000000000000000000000000000H;

4-300

Vol. 2B

PHMINPOSUW—Packed Horizontal Word Minimum

INSTRUCTION SET REFERENCE, M-U

PHSUBW/PHSUBD—Packed Horizontal Subtract

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

En

Mode

Feature

Support

Flag

NP 0F 38 05 /r¹

RM

V/V

SSSE3

Subtract 16-bit signed integers horizontally,

pack to mm1.

PHSUBW mm1, mm2/m64

66 0F 38 05 /r

RM

V/V

SSSE3

Subtract 16-bit signed integers horizontally,

pack to xmm1.

PHSUBW xmm1, xmm2/m128

NP 0F 38 06 /r

RM

V/V

SSSE3

Subtract 32-bit signed integers horizontally,

pack to mm1.

PHSUBD mm1, mm2/m64

66 0F 38 06 /r

RM

V/V

SSSE3

Subtract 32-bit signed integers horizontally,

pack to xmm1.

PHSUBD xmm1, xmm2/m128

VEX.128.66.0F38.WIG 05 /r

RVM

V/V

AVX

Subtract 16-bit signed integers horizontally,

pack to xmm1.

VPHSUBW xmm1, xmm2, xmm3/m128

VEX.128.66.0F38.WIG 06 /r

RVM

V/V

AVX

Subtract 32-bit signed integers horizontally,

pack to xmm1.

VPHSUBD xmm1, xmm2, xmm3/m128

VEX.256.66.0F38.WIG 05 /r

RVM

V/V

AVX2

Subtract 16-bit signed integers horizontally,

pack to ymm1.

VPHSUBW ymm1, ymm2, ymm3/m256

VEX.256.66.0F38.WIG 06 /r

RVM

V/V

AVX2

Subtract 32-bit signed integers horizontally,

pack to ymm1.

VPHSUBD ymm1, ymm2, ymm3/m256

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2A and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX

Registers” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RM

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

N/A

RVM

ModRM:reg (r, w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

(V)PHSUBW performs horizontal subtraction on each adjacent pair of 16-bit signed integers by subtracting the

most significant word from the least significant word of each pair in the source and destination operands, and packs

the signed 16-bit results to the destination operand (first operand). (V)PHSUBD performs horizontal subtraction on

each adjacent pair of 32-bit signed integers by subtracting the most significant doubleword from the least signifi-

cant doubleword of each pair, and packs the signed 32-bit result to the destination operand. When the source

operand is a 128-bit memory operand, the operand must be aligned on a 16-byte boundary or a general-protection

exception (#GP) will be generated.

Legacy SSE version: Both operands can be MMX registers. The second source operand can be an MMX register or a

64-bit memory location.

128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source

operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding YMM destina-

tion register remain unchanged.

In 64-bit mode, use the REX prefix to access additional registers.

VEX.128 encoded version: The first source and destination operands are XMM registers. The second source

operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the destination YMM register are

zeroed.

4-302

Vol. 2B

PHSUBW/PHSUBD—Packed Horizontal Subtract

INSTRUCTION SET REFERENCE, M-U

PHSUBSW—Packed Horizontal Subtract and Saturate

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

En

Mode

Feature

Support

Flag

NP 0F 38 07 /r¹

RM

V/V

SSSE3

Subtract 16-bit signed integer horizontally,

pack saturated integers to mm1.

PHSUBSW mm1, mm2/m64

66 0F 38 07 /r

RM

V/V

SSSE3

Subtract 16-bit signed integer horizontally,

pack saturated integers to xmm1.

PHSUBSW xmm1, xmm2/m128

VEX.128.66.0F38.WIG 07 /r

RVM

V/V

AVX

Subtract 16-bit signed integer horizontally,

pack saturated integers to xmm1.

VPHSUBSW xmm1, xmm2, xmm3/m128

VEX.256.66.0F38.WIG 07 /r

RVM

V/V

AVX2

Subtract 16-bit signed integer horizontally,

pack saturated integers to ymm1.

VPHSUBSW ymm1, ymm2, ymm3/m256

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2A and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX

Registers” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RM

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

N/A

RVM

ModRM:reg (r, w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

(V)PHSUBSW performs horizontal subtraction on each adjacent pair of 16-bit signed integers by subtracting the

most significant word from the least significant word of each pair in the source and destination operands. The

signed, saturated 16-bit results are packed to the destination operand (first operand). When the source operand is

a 128-bit memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception

(#GP) will be generated.

Legacy SSE version: Both operands can be MMX registers. The second source operand can be an MMX register or

a 64-bit memory location.

128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source

operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding YMM destina-

tion register remain unchanged.

In 64-bit mode, use the REX prefix to access additional registers.

VEX.128 encoded version: The first source and destination operands are XMM registers. The second source

operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the destination YMM register are

zeroed.

VEX.256 encoded version: The first source and destination operands are YMM registers. The second source

operand can be an YMM register or a 256-bit memory location.

Operation

PHSUBSW (with 64-bit operands)

mm1[15-0] = SaturateToSignedWord(mm1[15-0] - mm1[31-16]);

mm1[31-16] = SaturateToSignedWord(mm1[47-32] - mm1[63-48]);

mm1[47-32] = SaturateToSignedWord(mm2/m64[15-0] - mm2/m64[31-16]);

mm1[63-48] = SaturateToSignedWord(mm2/m64[47-32] - mm2/m64[63-48]);

PHSUBSW—Packed Horizontal Subtract and Saturate

Vol. 2B

4-305

INSTRUCTION SET REFERENCE, M-U

PINSRB/PINSRD/PINSRQ—Insert Byte/Dword/Qword

Opcode/

Op/ En

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

66 0F 3A 20 /r ib

A

V/V

SSE4_1

Insert a byte integer value from r32/m8 into

PINSRB xmm1, r32/m8, imm8

xmm1 at the destination element in xmm1

specified by imm8.

66 0F 3A 22 /r ib

A

V/V

SSE4_1

Insert a dword integer value from r/m32 into

PINSRD xmm1, r/m32, imm8

the xmm1 at the destination element

specified by imm8.

66 REX.W 0F 3A 22 /r ib

A

V/N. E.

SSE4_1

Insert a qword integer value from r/m64 into

PINSRQ xmm1, r/m64, imm8

the xmm1 at the destination element

specified by imm8.

VEX.128.66.0F3A.W0 20 /r ib

B

V¹/V

AVX

Merge a byte integer value from r32/m8 and

VPINSRB xmm1, xmm2, r32/m8, imm8

rest from xmm2 into xmm1 at the byte offset

in imm8.

VEX.128.66.0F3A.W0 22 /r ib

B

V/V

AVX

Insert a dword integer value from r32/m32

VPINSRD xmm1, xmm2, r/m32, imm8

and rest from xmm2 into xmm1 at the dword

offset in imm8.

VEX.128.66.0F3A.W1 22 /r ib

B

V/I²

AVX

Insert a qword integer value from r64/m64

VPINSRQ xmm1, xmm2, r/m64, imm8

and rest from xmm2 into xmm1 at the qword

offset in imm8.

EVEX.128.66.0F3A.WIG 20 /r ib

C

V/V

AVX512BW

Merge a byte integer value from r32/m8 and

VPINSRB xmm1, xmm2, r32/m8, imm8

rest from xmm2 into xmm1 at the byte offset

in imm8.

EVEX.128.66.0F3A.W0 22 /r ib

C

V/V

AVX512DQ

Insert a dword integer value from r32/m32

VPINSRD xmm1, xmm2, r32/m32, imm8

and rest from xmm2 into xmm1 at the dword

offset in imm8.

EVEX.128.66.0F3A.W1 22 /r ib

C

V/N.E.²

AVX512DQ

Insert a qword integer value from r64/m64

VPINSRQ xmm1, xmm2, r64/m64, imm8

and rest from xmm2 into xmm1 at the qword

offset in imm8.

NOTES:

1. In 64-bit mode, VEX.W1 is ignored for VPINSRB (similar to legacy REX.W=1 prefix with PINSRB).

2. VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is used.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (w)

ModRM:r/m (r)

imm8

N/A

B

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

imm8

C

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

imm8

Description

Copies a byte/dword/qword from the source operand (second operand) and inserts it in the destination operand

(first operand) at the location specified with the count operand (third operand). (The other elements in the desti-

nation register are left untouched.) The source operand can be a general-purpose register or a memory location.

(When the source operand is a general-purpose register, PINSRB copies the low byte of the register.) The destina-

tion operand is an XMM register. The count operand is an 8-bit immediate. When specifying a qword[dword, byte]

location in an XMM register, the [2, 4] least-significant bit(s) of the count operand specify the location.

PINSRB/PINSRD/PINSRQ—Insert Byte/Dword/Qword

Vol. 2B

4-307

INSTRUCTION SET REFERENCE, M-U

PINSRW—Insert Word

Opcode/

Op/ En

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

NP 0F C4 /r ib¹

A

V/V

SSE

Insert the low word from r32 or from m16

into mm at the word position specified by

PINSRW mm, r32/m16, imm8

imm8.

66 0F C4 /r ib

A

V/V

SSE2

Move the low word of r32 or from m16 into

xmm at the word position specified by imm8.

PINSRW xmm, r32/m16, imm8

VEX.128.66.0F.W0 C4 /r ib

B

V²/V

AVX

Insert the word from r32/m16 at the offset

indicated by imm8 into the value from xmm2

VPINSRW xmm1, xmm2, r32/m16, imm8

and store result in xmm1.

EVEX.128.66.0F.WIG C4 /r ib

C

V/V

AVX512BW

Insert the word from r32/m16 at the offset

VPINSRW xmm1, xmm2, r32/m16, imm8

indicated by imm8 into the value from xmm2

and store result in xmm1.

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures

Software Developer’s Manual, Volume 2A and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX

Registers” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

2. In 64-bit mode, VEX.W1 is ignored for VPINSRW (similar to legacy REX.W=1 prefix in PINSRW).

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (w)

ModRM:r/m (r)

imm8

N/A

B

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

imm8

C

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

imm8

Description

Three operand MMX and SSE instructions:

Copies a word from the source operand and inserts it in the destination operand at the location specified with the

count operand. (The other words in the destination register are left untouched.) The source operand can be a

general-purpose register or a 16-bit memory location. (When the source operand is a general-purpose register, the

low word of the register is copied.) The destination operand can be an MMX technology register or an XMM register.

The count operand is an 8-bit immediate. When specifying a word location in an MMX technology register, the 2

least-significant bits of the count operand specify the location; for an XMM register, the 3 least-significant bits

specify the location.

Bits (MAXVL-1:128) of the corresponding YMM destination register remain unchanged.

Four operand AVX and AVX-512 instructions:

Combines a word from the first source operand with the second source operand, and inserts it in the destination

operand at the location specified with the count operand. The second source operand can be a general-purpose

register or a 16-bit memory location. (When the source operand is a general-purpose register, the low word of the

register is copied.) The first source and destination operands are XMM registers. The count operand is an 8-bit

immediate. When specifying a word location, the 3 least-significant bits specify the location.

Bits (MAXVL-1:128) of the destination YMM register are zeroed. VEX.L/EVEX.L’L must be 0, otherwise the instruc-

tion will #UD.

4-310

Vol. 2B

PINSRW—Insert Word

INSTRUCTION SET REFERENCE, M-U

PMADDUBSW—Multiply and Add Packed Signed and Unsigned Bytes

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

En

Mode

Feature

Support

Flag

NP 0F 38 04 /r¹

A

V/V

SSSE3

Multiply signed and unsigned bytes, add

horizontal pair of signed words, pack

PMADDUBSW mm1, mm2/m64

saturated signed-words to mm1.

66 0F 38 04 /r

A

V/V

SSSE3

Multiply signed and unsigned bytes, add

horizontal pair of signed words, pack

PMADDUBSW xmm1, xmm2/m128

saturated signed-words to xmm1.

VEX.128.66.0F38.WIG 04 /r

B

V/V

AVX

Multiply signed and unsigned bytes, add

horizontal pair of signed words, pack

VPMADDUBSW xmm1, xmm2, xmm3/m128

saturated signed-words to xmm1.

VEX.256.66.0F38.WIG 04 /r

B

V/V

AVX2

Multiply signed and unsigned bytes, add

horizontal pair of signed words, pack

VPMADDUBSW ymm1, ymm2, ymm3/m256

saturated signed-words to ymm1.

EVEX.128.66.0F38.WIG 04 /r

C

V/V

AVX512VL

Multiply signed and unsigned bytes, add

VPMADDUBSW xmm1 {k1}{z}, xmm2, xmm3/m128

AVX512BW

horizontal pair of signed words, pack

saturated signed-words to xmm1 under

writemask k1.

EVEX.256.66.0F38.WIG 04 /r

C

V/V

AVX512VL

Multiply signed and unsigned bytes, add

VPMADDUBSW ymm1 {k1}{z}, ymm2, ymm3/m256

AVX512BW

horizontal pair of signed words, pack

saturated signed-words to ymm1 under

writemask k1.

EVEX.512.66.0F38.WIG 04 /r

C

V/V

AVX512BW

Multiply signed and unsigned bytes, add

VPMADDUBSW zmm1 {k1}{z}, zmm2, zmm3/m512

horizontal pair of signed words, pack

saturated signed-words to zmm1 under

writemask k1.

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2A and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Reg-

isters” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

N/A

B

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

C

Full Mem

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

(V)PMADDUBSW multiplies vertically each unsigned byte of the destination operand (first operand) with the corre-

sponding signed byte of the source operand (second operand), producing intermediate signed 16-bit integers. Each

adjacent pair of signed words is added and the saturated result is packed to the destination operand. For example,

the lowest-order bytes (bits 7-0) in the source and destination operands are multiplied and the intermediate signed

word result is added with the corresponding intermediate result from the 2nd lowest-order bytes (bits 15-8) of the

operands; the sign-saturated result is stored in the lowest word of the destination register (15-0). The same oper-

ation is performed on the other pairs of adjacent bytes. Both operands can be MMX register or XMM registers. When

the source operand is a 128-bit memory operand, the operand must be aligned on a 16-byte boundary or a

general-protection exception (#GP) will be generated.

In 64-bit mode and not encoded with VEX/EVEX, use the REX prefix to access XMM8-XMM15.

4-312

Vol. 2B

PMADDUBSW—Multiply and Add Packed Signed and Unsigned Bytes

INSTRUCTION SET REFERENCE, M-U

PMADDWD—Multiply and Add Packed Integers

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

En

Mode

Feature

Support

Flag

NP 0F F5 /r¹

A

V/V

MMX

Multiply the packed words in mm by the packed

words in mm/m64, add adjacent doubleword

PMADDWD mm, mm/m64

results, and store in mm.

66 0F F5 /r

A

V/V

SSE2

Multiply the packed word integers in xmm1 by

the packed word integers in xmm2/m128, add

PMADDWD xmm1, xmm2/m128

adjacent doubleword results, and store in

xmm1.

VEX.128.66.0F.WIG F5 /r

B

V/V

AVX

Multiply the packed word integers in xmm2 by

the packed word integers in xmm3/m128, add

VPMADDWD xmm1, xmm2, xmm3/m128

adjacent doubleword results, and store in

xmm1.

VEX.256.66.0F.WIG F5 /r

B

V/V

AVX2

Multiply the packed word integers in ymm2 by

the packed word integers in ymm3/m256, add

VPMADDWD ymm1, ymm2, ymm3/m256

adjacent doubleword results, and store in

ymm1.

EVEX.128.66.0F.WIG F5 /r

C

V/V

AVX512VL

Multiply the packed word integers in xmm2 by

VPMADDWD xmm1 {k1}{z}, xmm2, xmm3/m128

AVX512BW

the packed word integers in xmm3/m128, add

adjacent doubleword results, and store in

xmm1 under writemask k1.

EVEX.256.66.0F.WIG F5 /r

C

V/V

AVX512VL

Multiply the packed word integers in ymm2 by

VPMADDWD ymm1 {k1}{z}, ymm2, ymm3/m256

AVX512BW

the packed word integers in ymm3/m256, add

adjacent doubleword results, and store in

ymm1 under writemask k1.

EVEX.512.66.0F.WIG F5 /r

C

V/V

AVX512BW

Multiply the packed word integers in zmm2 by

VPMADDWD zmm1 {k1}{z}, zmm2, zmm3/m512

the packed word integers in zmm3/m512, add

adjacent doubleword results, and store in

zmm1 under writemask k1.

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2A and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Reg-

isters” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

N/A

B

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

C

Full Mem

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Multiplies the individual signed words of the destination operand (first operand) by the corresponding signed words

of the source operand (second operand), producing temporary signed, doubleword results. The adjacent double-

word results are then summed and stored in the destination operand. For example, the corresponding low-order

words (15-0) and (31-16) in the source and destination operands are multiplied by one another and the double-

word results are added together and stored in the low doubleword of the destination register (31-0). The same

operation is performed on the other pairs of adjacent words. (Figure 4-11 shows this operation when using 64-bit

operands).

PMADDWD—Multiply and Add Packed Integers

Vol. 2B

4-315

INSTRUCTION SET REFERENCE, M-U

The (V)PMADDWD instruction wraps around only in one situation: when the 2 pairs of words being operated on in

a group are all 8000H. In this case, the result wraps around to 80000000H.

In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to

access additional registers (XMM8-XMM15).

Legacy SSE version: The first source and destination operands are MMX registers. The second source operand is an

MMX register or a 64-bit memory location.

128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source

operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding YMM destina-

tion register remain unchanged.

VEX.128 encoded version: The first source and destination operands are XMM registers. The second source

operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the destination YMM register are

zeroed.

VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The

first source and destination operands are YMM registers.

EVEX.512 encoded version: The second source operand can be an ZMM register or a 512-bit memory location. The

first source and destination operands are ZMM registers.

SRC

X3

X2

X1

X0

DEST

Y3

Y2

Y1

Y0

TEMP

X3 ∗ Y3

X2 ∗ Y2

X1 ∗ Y1

X0 ∗ Y0

DEST

(X3∗Y3) + (X2∗Y2)

(X1∗Y1) + (X0∗Y0)

Figure 4-11. PMADDWD Execution Model Using 64-bit Operands

Operation

PMADDWD (with 64-bit operands)

DEST[31:0] := (DEST[15:0] ∗ SRC[15:0]) + (DEST[31:16] ∗ SRC[31:16]);

DEST[63:32] := (DEST[47:32] ∗ SRC[47:32]) + (DEST[63:48] ∗ SRC[63:48]);

PMADDWD (with 128-bit operands)

DEST[31:0] := (DEST[15:0] ∗ SRC[15:0]) + (DEST[31:16] ∗ SRC[31:16]);

DEST[63:32] := (DEST[47:32] ∗ SRC[47:32]) + (DEST[63:48] ∗ SRC[63:48]);

DEST[95:64] := (DEST[79:64] ∗ SRC[79:64]) + (DEST[95:80] ∗ SRC[95:80]);

DEST[127:96] := (DEST[111:96] ∗ SRC[111:96]) + (DEST[127:112] ∗ SRC[127:112]);

VPMADDWD (VEX.128 encoded version)

DEST[31:0] := (SRC1[15:0] * SRC2[15:0]) + (SRC1[31:16] * SRC2[31:16])

DEST[63:32] := (SRC1[47:32] * SRC2[47:32]) + (SRC1[63:48] * SRC2[63:48])

DEST[95:64] := (SRC1[79:64] * SRC2[79:64]) + (SRC1[95:80] * SRC2[95:80])

DEST[127:96] := (SRC1[111:96] * SRC2[111:96]) + (SRC1[127:112] * SRC2[127:112])

DEST[MAXVL-1:128] := 0

4-316

Vol. 2B

PMADDWD—Multiply and Add Packed Integers

Content      ..     80      81      82      83     ..