Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023)

INSTRUCTION SET REFERENCE, M-U

NEG—Two's Complement Negation

Opcode

Instruction

Op/

64-Bit

Compat/

Description

Mode

Leg Mode

F6 /3

NEG r/m8

Valid

Two's complement negate r/m8.

REX + F6 /3

NEG r/m8¹

Valid

N.E.

Two's complement negate r/m8.

F7 /3

NEG r/m16

Valid

Two's complement negate r/m16.

F7 /3

NEG r/m32

Valid

Two's complement negate r/m32.

REX.W + F7 /3

NEG r/m64

Valid

N.E.

Two's complement negate r/m64.

NOTES:

1. In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:r/m (r, w)

N/A

Description

Replaces the value of operand (the destination operand) with its two's complement. (This operation is equivalent

to subtracting the operand from 0.) The destination operand is located in a general-purpose register or a memory

location.

This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.

In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits

access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See

the summary chart at the beginning of this section for encoding data and limits.

Operation

IF DEST = 0

THEN CF := 0;

ELSE CF := 1;

FI;

DEST := [- (DEST)]

Flags Affected

The CF flag set to 0 if the source operand is 0; otherwise it is set to 1. The OF, SF, ZF, AF, and PF flags are set

according to the result.

Protected Mode Exceptions

#GP(0)

If the destination is located in a non-writable segment.

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

If the DS, ES, FS, or GS register contains a NULL segment selector.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If the LOCK prefix is used but the destination is not a memory operand.

NEG—Two's Complement Negation

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INSTRUCTION SET REFERENCE, M-U

Real-Address Mode Exceptions

#GP

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS

If a memory operand effective address is outside the SS segment limit.

#UD

If the LOCK prefix is used but the destination is not a memory operand.

Virtual-8086 Mode Exceptions

#GP(0)

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made.

#UD

If the LOCK prefix is used but the destination is not a memory operand.

Compatibility Mode Exceptions

Same as for protected mode exceptions.

64-Bit Mode Exceptions

#SS(0)

If a memory address referencing the SS segment is in a non-canonical form.

#GP(0)

If the memory address is in a non-canonical form.

#PF(fault-code)

For a page fault.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If the LOCK prefix is used but the destination is not a memory operand.

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NEG—Two's Complement Negation

INSTRUCTION SET REFERENCE, M-U

NOP—No Operation

Opcode

Instruction

Op/

64-Bit

Compat/

Description

Mode

Leg Mode

NP 90

NOP

Valid

One byte no-operation instruction.

NP 0F 1F /0

NOP r/m16

Valid

Multi-byte no-operation instruction.

NP 0F 1F /0

NOP r/m32

Valid

Multi-byte no-operation instruction.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:r/m (r)

N/A

Description

This instruction performs no operation. It is a one-byte or multi-byte NOP that takes up space in the instruction

stream but does not impact machine context, except for the EIP register.

The multi-byte form of NOP is available on processors with model encoding:

• CPUID.01H.EAX[Bytes 11:8] = 0110B or 1111B

The multi-byte NOP instruction does not alter the content of a register and will not issue a memory operation. The

instruction’s operation is the same in non-64-bit modes and 64-bit mode.

Operation

The one-byte NOP instruction is an alias mnemonic for the XCHG (E)AX, (E)AX instruction.

The multi-byte NOP instruction performs no operation on supported processors and generates undefined opcode

exception on processors that do not support the multi-byte NOP instruction.

The memory operand form of the instruction allows software to create a byte sequence of “no operation” as one

instruction. For situations where multiple-byte NOPs are needed, the recommended operations (32-bit mode and

64-bit mode) are:

Table 4-12. Recommended Multi-Byte Sequence of NOP Instruction

Length

Assembly

Byte Sequence

2 bytes

66 NOP

66 90H

3 bytes

NOP DWORD ptr [EAX]

0F 1F 00H

4 bytes

NOP DWORD ptr [EAX + 00H]

0F 1F 40 00H

5 bytes

NOP DWORD ptr [EAX + EAX*1 + 00H]

0F 1F 44 00 00H

6 bytes

66 NOP DWORD ptr [EAX + EAX*1 + 00H]

66 0F 1F 44 00 00H

7 bytes

NOP DWORD ptr [EAX + 00000000H]

0F 1F 80 00 00 00 00H

8 bytes

NOP DWORD ptr [EAX + EAX*1 + 00000000H]

0F 1F 84 00 00 00 00 00H

9 bytes

66 NOP DWORD ptr [EAX + EAX*1 + 00000000H]

66 0F 1F 84 00 00 00 00 00H

Flags Affected

None

Exceptions (All Operating Modes)

#UD

If the LOCK prefix is used.

NOP—No Operation

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INSTRUCTION SET REFERENCE, M-U

NOT—One's Complement Negation

Opcode

Instruction

Op/

64-Bit

Compat/

Description

Mode

Leg Mode

F6 /2

NOT r/m8

Valid

Reverse each bit of r/m8.

REX + F6 /2

NOT r/m8¹

Valid

N.E.

Reverse each bit of r/m8.

F7 /2

NOT r/m16

Valid

Reverse each bit of r/m16.

F7 /2

NOT r/m32

Valid

Reverse each bit of r/m32.

REX.W + F7 /2

NOT r/m64

Valid

N.E.

Reverse each bit of r/m64.

NOTES:

1. In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:r/m (r, w)

N/A

Description

Performs a bitwise NOT operation (each 1 is set to 0, and each 0 is set to 1) on the destination operand and stores

the result in the destination operand location. The destination operand can be a register or a memory location.

This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.

In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits

access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See

the summary chart at the beginning of this section for encoding data and limits.

Operation

DEST := NOT DEST;

Flags Affected

None

Protected Mode Exceptions

#GP(0)

If the destination operand points to a non-writable segment.

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

If the DS, ES, FS, or GS register contains a NULL segment selector.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If the LOCK prefix is used but the destination is not a memory operand.

Real-Address Mode Exceptions

#GP

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS

If a memory operand effective address is outside the SS segment limit.

#UD

If the LOCK prefix is used but the destination is not a memory operand.

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NOT—One's Complement Negation

INSTRUCTION SET REFERENCE, M-U

Virtual-8086 Mode Exceptions

#GP(0)

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made.

#UD

If the LOCK prefix is used but the destination is not a memory operand.

Compatibility Mode Exceptions

Same as for protected mode exceptions.

64-Bit Mode Exceptions

#SS(0)

If a memory address referencing the SS segment is in a non-canonical form.

#GP(0)

If the memory address is in a non-canonical form.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If the LOCK prefix is used but the destination is not a memory operand.

NOT—One's Complement Negation

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INSTRUCTION SET REFERENCE, M-U

OR—Logical Inclusive OR

Opcode

Instruction

Op/

64-Bit

Compat/

Description

Mode

Leg Mode

0C ib

OR AL, imm8

Valid

AL OR imm8.

0D iw

OR AX, imm16

Valid

AX OR imm16.

0D id

OR EAX, imm32

Valid

EAX OR imm32.

REX.W + 0D id

OR RAX, imm32

Valid

N.E.

RAX OR imm32 (sign-extended).

80 /1 ib

OR r/m8, imm8

Valid

r/m8 OR imm8.

REX + 80 /1 ib

OR r/m8¹, imm8

Valid

N.E.

r/m8 OR imm8.

81 /1 iw

OR r/m16, imm16

Valid

r/m16 OR imm16.

81 /1 id

OR r/m32, imm32

Valid

r/m32 OR imm32.

REX.W + 81 /1 id

OR r/m64, imm32

Valid

N.E.

r/m64 OR imm32 (sign-extended).

83 /1 ib

OR r/m16, imm8

Valid

r/m16 OR imm8 (sign-extended).

83 /1 ib

OR r/m32, imm8

Valid

r/m32 OR imm8 (sign-extended).

REX.W + 83 /1 ib

OR r/m64, imm8

Valid

N.E.

r/m64 OR imm8 (sign-extended).

08 /r

OR r/m8, r8

Valid

r/m8 OR r8.

REX + 08 /r

OR r/m8¹, r8¹

Valid

N.E.

r/m8 OR r8.

09 /r

OR r/m16, r16

Valid

r/m16 OR r16.

09 /r

OR r/m32, r32

Valid

r/m32 OR r32.

REX.W + 09 /r

OR r/m64, r64

Valid

N.E.

r/m64 OR r64.

0A /r

OR r8, r/m8

Valid

r8 OR r/m8.

REX + 0A /r

OR r8¹, r/m8¹

Valid

N.E.

r8 OR r/m8.

0B /r

OR r16, r/m16

Valid

r16 OR r/m16.

0B /r

OR r32, r/m32

Valid

r32 OR r/m32.

REX.W + 0B /r

OR r64, r/m64

Valid

N.E.

r64 OR r/m64.

NOTES:

1. In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

AL/AX/EAX/RAX

imm8/16/32

N/A

ModRM:r/m (r, w)

imm8/16/32

N/A

ModRM:r/m (r, w)

ModRM:reg (r)

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

Description

Performs a bitwise inclusive OR operation between the destination (first) and source (second) operands and stores

the result in the destination operand location. The source operand can be an immediate, a register, or a memory

location; the destination operand can be a register or a memory location. (However, two memory operands cannot

be used in one instruction.) Each bit of the result of the OR instruction is set to 0 if both corresponding bits of the

first and second operands are 0; otherwise, each bit is set to 1.

This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.

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OR—Logical Inclusive OR

INSTRUCTION SET REFERENCE, M-U

In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits

access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See

the summary chart at the beginning of this section for encoding data and limits.

Operation

DEST := DEST OR SRC;

Flags Affected

The OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result. The state of the AF flag is

undefined.

Protected Mode Exceptions

#GP(0)

If the destination operand points to a non-writable segment.

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

If the DS, ES, FS, or GS register contains a NULL segment selector.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If the LOCK prefix is used but the destination is not a memory operand.

Real-Address Mode Exceptions

#GP

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS

If a memory operand effective address is outside the SS segment limit.

#UD

If the LOCK prefix is used but the destination is not a memory operand.

Virtual-8086 Mode Exceptions

#GP(0)

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made.

#UD

If the LOCK prefix is used but the destination is not a memory operand.

Compatibility Mode Exceptions

Same as for protected mode exceptions.

64-Bit Mode Exceptions

#SS(0)

If a memory address referencing the SS segment is in a non-canonical form.

#GP(0)

If the memory address is in a non-canonical form.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If the LOCK prefix is used but the destination is not a memory operand.

OR—Logical Inclusive OR

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INSTRUCTION SET REFERENCE, M-U

ORPD—Bitwise Logical OR of Packed Double Precision Floating-Point Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

66 0F 56/r

V/V

SSE2

Return the bitwise logical OR of packed double precision

ORPD xmm1, xmm2/m128

floating-point values in xmm1 and xmm2/mem.

VEX.128.66.0F 56 /r

V/V

AVX

Return the bitwise logical OR of packed double precision

VORPD xmm1,xmm2, xmm3/m128

floating-point values in xmm2 and xmm3/mem.

VEX.256.66.0F 56 /r

V/V

AVX

Return the bitwise logical OR of packed double precision

VORPD ymm1, ymm2, ymm3/m256

floating-point values in ymm2 and ymm3/mem.

EVEX.128.66.0F.W1 56 /r

V/V

AVX512VL

Return the bitwise logical OR of packed double precision

VORPD xmm1 {k1}{z}, xmm2,

AVX512DQ

floating-point values in xmm2 and xmm3/m128/m64bcst

xmm3/m128/m64bcst

subject to writemask k1.

EVEX.256.66.0F.W1 56 /r

V/V

AVX512VL

Return the bitwise logical OR of packed double precision

VORPD ymm1 {k1}{z}, ymm2,

AVX512DQ

floating-point values in ymm2 and ymm3/m256/m64bcst

ymm3/m256/m64bcst

subject to writemask k1.

EVEX.512.66.0F.W1 56 /r

V/V

AVX512DQ

Return the bitwise logical OR of packed double precision

VORPD zmm1 {k1}{z}, zmm2,

floating-point values in zmm2 and zmm3/m512/m64bcst

zmm3/m512/m64bcst

subject to writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs a bitwise logical OR of the two, four or eight packed double precision floating-point values from the first

source operand and the second source operand, and stores the result in the destination operand.

EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be

a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a

32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with

writemask k1.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register

or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAXVL-1:256) of the

corresponding ZMM register destination are zeroed.

VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM

the corresponding ZMM register destination are zeroed.

128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-

nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding

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ORPD—Bitwise Logical OR of Packed Double Precision Floating-Point Values

INSTRUCTION SET REFERENCE, M-U

Operation

VORPD (EVEX encoded versions)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b == 1) AND (SRC2 *is memory*)

THEN

DEST[i+63:i] := SRC1[i+63:i] BITWISE OR SRC2[63:0]

ELSE

DEST[i+63:i] := SRC1[i+63:i] BITWISE OR SRC2[i+63:i]

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VORPD (VEX.256 encoded version)

DEST[63:0] := SRC1[63:0] BITWISE OR SRC2[63:0]

DEST[127:64] := SRC1[127:64] BITWISE OR SRC2[127:64]

DEST[191:128] := SRC1[191:128] BITWISE OR SRC2[191:128]

DEST[255:192] := SRC1[255:192] BITWISE OR SRC2[255:192]

DEST[MAXVL-1:256] := 0

VORPD (VEX.128 encoded version)

DEST[63:0] := SRC1[63:0] BITWISE OR SRC2[63:0]

DEST[127:64] := SRC1[127:64] BITWISE OR SRC2[127:64]

DEST[MAXVL-1:128] := 0

ORPD (128-bit Legacy SSE version)

DEST[63:0] := DEST[63:0] BITWISE OR SRC[63:0]

DEST[127:64] := DEST[127:64] BITWISE OR SRC[127:64]

DEST[MAXVL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

VORPD __m512d _mm512_or_pd ( __m512d a, __m512d b);

VORPD __m512d _mm512_mask_or_pd ( __m512d s, __mmask8 k, __m512d a, __m512d b);

VORPD __m512d _mm512_maskz_or_pd (__mmask8 k, __m512d a, __m512d b);

VORPD __m256d _mm256_mask_or_pd (__m256d s, ___mmask8 k, __m256d a, __m256d b);

VORPD __m256d _mm256_maskz_or_pd (__mmask8 k, __m256d a, __m256d b);

VORPD __m128d _mm_mask_or_pd ( __m128d s, __mmask8 k, __m128d a, __m128d b);

VORPD __m128d _mm_maskz_or_pd (__mmask8 k, __m128d a, __m128d b);

VORPD __m256d _mm256_or_pd (__m256d a, __m256d b);

ORPD __m128d _mm_or_pd (__m128d a, __m128d b);

ORPD—Bitwise Logical OR of Packed Double Precision Floating-Point Values

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INSTRUCTION SET REFERENCE, M-U

ORPS—Bitwise Logical OR of Packed Single Precision Floating-Point Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

NP 0F 56 /r

V/V

SSE

Return the bitwise logical OR of packed single precision

ORPS xmm1, xmm2/m128

floating-point values in xmm1 and xmm2/mem.

VEX.128.0F 56 /r

V/V

AVX

Return the bitwise logical OR of packed single precision

VORPS xmm1,xmm2, xmm3/m128

floating-point values in xmm2 and xmm3/mem.

VEX.256.0F 56 /r

V/V

AVX

Return the bitwise logical OR of packed single precision

VORPS ymm1, ymm2, ymm3/m256

floating-point values in ymm2 and ymm3/mem.

EVEX.128.0F.W0 56 /r

V/V

AVX512VL

Return the bitwise logical OR of packed single precision

VORPS xmm1 {k1}{z}, xmm2,

AVX512DQ

floating-point values in xmm2 and xmm3/m128/m32bcst

xmm3/m128/m32bcst

subject to writemask k1.

EVEX.256.0F.W0 56 /r

V/V

AVX512VL

Return the bitwise logical OR of packed single precision

VORPS ymm1 {k1}{z}, ymm2,

AVX512DQ

floating-point values in ymm2 and ymm3/m256/m32bcst

ymm3/m256/m32bcst

subject to writemask k1.

EVEX.512.0F.W0 56 /r

V/V

AVX512DQ

Return the bitwise logical OR of packed single precision

VORPS zmm1 {k1}{z}, zmm2,

floating-point values in zmm2 and zmm3/m512/m32bcst

zmm3/m512/m32bcst

subject to writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs a bitwise logical OR of the four, eight or sixteen packed single precision floating-point values from the first

source operand and the second source operand, and stores the result in the destination operand

EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be

a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a

32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with

writemask k1.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register

or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAXVL-1:256) of the

corresponding ZMM register destination are zeroed.

VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM

the corresponding ZMM register destination are zeroed.

128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-

nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding

ORPS—Bitwise Logical OR of Packed Single Precision Floating-Point Values

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4-177

INSTRUCTION SET REFERENCE, M-U

Operation

VORPS (EVEX encoded versions)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b == 1) AND (SRC2 *is memory*)

THEN

DEST[i+31:i] := SRC1[i+31:i] BITWISE OR SRC2[31:0]

ELSE

DEST[i+31:i] := SRC1[i+31:i] BITWISE OR SRC2[i+31:i]

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VORPS (VEX.256 encoded version)

DEST[31:0] := SRC1[31:0] BITWISE OR SRC2[31:0]

DEST[63:32] := SRC1[63:32] BITWISE OR SRC2[63:32]

DEST[95:64] := SRC1[95:64] BITWISE OR SRC2[95:64]

DEST[127:96] := SRC1[127:96] BITWISE OR SRC2[127:96]

DEST[159:128] := SRC1[159:128] BITWISE OR SRC2[159:128]

DEST[191:160] := SRC1[191:160] BITWISE OR SRC2[191:160]

DEST[223:192] := SRC1[223:192] BITWISE OR SRC2[223:192]

DEST[255:224] := SRC1[255:224] BITWISE OR SRC2[255:224].

DEST[MAXVL-1:256] := 0

VORPS (VEX.128 encoded version)

DEST[31:0] := SRC1[31:0] BITWISE OR SRC2[31:0]

DEST[63:32] := SRC1[63:32] BITWISE OR SRC2[63:32]

DEST[95:64] := SRC1[95:64] BITWISE OR SRC2[95:64]

DEST[127:96] := SRC1[127:96] BITWISE OR SRC2[127:96]

DEST[MAXVL-1:128] := 0

ORPS (128-bit Legacy SSE version)

DEST[31:0] := SRC1[31:0] BITWISE OR SRC2[31:0]

DEST[63:32] := SRC1[63:32] BITWISE OR SRC2[63:32]

DEST[95:64] := SRC1[95:64] BITWISE OR SRC2[95:64]

DEST[127:96] := SRC1[127:96] BITWISE OR SRC2[127:96]

DEST[MAXVL-1:128] (Unmodified)

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ORPS—Bitwise Logical OR of Packed Single Precision Floating-Point Values

INSTRUCTION SET REFERENCE, M-U

Intel C/C++ Compiler Intrinsic Equivalent

VORPS __m512 _mm512_or_ps ( __m512 a, __m512 b);

VORPS __m512 _mm512_mask_or_ps ( __m512 s, __mmask16 k, __m512 a, __m512 b);

VORPS __m512 _mm512_maskz_or_ps (__mmask16 k, __m512 a, __m512 b);

VORPS __m256 _mm256_mask_or_ps (__m256 s, ___mmask8 k, __m256 a, __m256 b);

VORPS __m256 _mm256_maskz_or_ps (__mmask8 k, __m256 a, __m256 b);

VORPS __m128 _mm_mask_or_ps ( __m128 s, __mmask8 k, __m128 a, __m128 b);

VORPS __m128 _mm_maskz_or_ps (__mmask8 k, __m128 a, __m128 b);

VORPS __m256 _mm256_or_ps (__m256 a, __m256 b);

ORPS __m128 _mm_or_ps (__m128 a, __m128 b);

SIMD Floating-Point Exceptions

None

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions”.

EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions”.

ORPS—Bitwise Logical OR of Packed Single Precision Floating-Point Values

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4-179

INSTRUCTION SET REFERENCE, M-U

OUT—Output to Port

Opcode¹

Instruction

Op/

64-Bit

Compat/

Description

Mode

Leg Mode

E6 ib

OUT imm8, AL

Valid

Output byte in AL to I/O port address imm8.

E7 ib

OUT imm8, AX

Valid

Output word in AX to I/O port address imm8.

E7 ib

OUT imm8, EAX

Valid

Output doubleword in EAX to I/O port address

imm8.

OUT DX, AL

Valid

Output byte in AL to I/O port address in DX.

OUT DX, AX

Valid

Output word in AX to I/O port address in DX.

OUT DX, EAX

Valid

Output doubleword in EAX to I/O port address

in DX.

NOTES:

1. See the IA-32 Architecture Compatibility section below.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

imm8

N/A

Description

Copies the value from the second operand (source operand) to the I/O port specified with the destination operand

(first operand). The source operand can be register AL, AX, or EAX, depending on the size of the port being

accessed (8, 16, or 32 bits, respectively); the destination operand can be a byte-immediate or the DX register.

Using a byte immediate allows I/O port addresses 0 to 255 to be accessed; using the DX register as a source

operand allows I/O ports from 0 to 65,535 to be accessed.

The size of the I/O port being accessed is determined by the opcode for an 8-bit I/O port or by the operand-size

attribute of the instruction for a 16- or 32-bit I/O port.

At the machine code level, I/O instructions are shorter when accessing 8-bit I/O ports. Here, the upper eight bits

of the port address will be 0.

This instruction is only useful for accessing I/O ports located in the processor’s I/O address space. See Chapter 19,

“Input/Output,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for more infor-

mation on accessing I/O ports in the I/O address space.

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

IA-32 Architecture Compatibility

After executing an OUT instruction, the Pentium^® processor ensures that the EWBE# pin has been sampled active

before it begins to execute the next instruction. (Note that the instruction can be prefetched if EWBE# is not active,

but it will not be executed until the EWBE# pin is sampled active.) Only the Pentium processor family has the

EWBE# pin.

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OUT—Output to Port

INSTRUCTION SET REFERENCE, M-U

Operation

IF ((PE = 1) and ((CPL > IOPL) or (VM = 1)))

THEN (* Protected mode with CPL > IOPL or virtual-8086 mode *)

IF (Any I/O Permission Bit for I/O port being accessed = 1)

THEN (* I/O operation is not allowed *)

#GP(0);

ELSE ( * I/O operation is allowed *)

DEST := SRC; (* Writes to selected I/O port *)

FI;

ELSE (Real Mode or Protected Mode with CPL ≤ IOPL *)

DEST := SRC; (* Writes to selected I/O port *)

FI;

Flags Affected

None

Protected Mode Exceptions

#GP(0)

If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the

corresponding I/O permission bits in TSS for the I/O port being accessed is 1.

#UD

If the LOCK prefix is used.

Real-Address Mode Exceptions

#UD

If the LOCK prefix is used.

Virtual-8086 Mode Exceptions

#GP(0)

If any of the I/O permission bits in the TSS for the I/O port being accessed is 1.

#PF(fault-code)

If a page fault occurs.

#UD

If the LOCK prefix is used.

Compatibility Mode Exceptions

Same as protected mode exceptions.

64-Bit Mode Exceptions

Same as protected mode exceptions.

OUT—Output to Port

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INSTRUCTION SET REFERENCE, M-U

OUTS/OUTSB/OUTSW/OUTSD—Output String to Port

Opcode¹

Instruction

Op/

64-Bit

Compat/

Description

Mode

Leg Mode

OUTS DX, m8

Valid

Output byte from memory location specified

in DS:(E)SI or RSI to I/O port specified in DX².

OUTS DX, m16

Valid

Output word from memory location specified

in DS:(E)SI or RSI to I/O port specified in DX².

OUTS DX, m32

Valid

Output doubleword from memory location

specified in DS:(E)SI or RSI to I/O port specified

in DX².

OUTSB

Valid

Output byte from memory location specified

in DS:(E)SI or RSI to I/O port specified in DX².

OUTSW

Valid

Output word from memory location specified

in DS:(E)SI or RSI to I/O port specified in DX².

OUTSD

Valid

Output doubleword from memory location

specified in DS:(E)SI or RSI to I/O port specified

in DX².

NOTES:

1. See the IA-32 Architecture Compatibility section below.

2. In 64-bit mode, only 64-bit (RSI) and 32-bit (ESI) address sizes are supported. In non-64-bit mode, only 32-bit (ESI) and 16-bit (SI)

address sizes are supported.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

N/A

Description

Copies data from the source operand (second operand) to the I/O port specified with the destination operand (first

operand). The source operand is a memory location, the address of which is read from either the DS:SI, DS:ESI or

the RSI registers (depending on the address-size attribute of the instruction, 16, 32 or 64, respectively). (The DS

segment may be overridden with a segment override prefix.) The destination operand is an I/O port address (from

0 to 65,535) that is read from the DX register. The size of the I/O port being accessed (that is, the size of the source

and destination operands) is determined by the opcode for an 8-bit I/O port or by the operand-size attribute of the

instruction for a 16- or 32-bit I/O port.

At the assembly-code level, two forms of this instruction are allowed: the “explicit-operands” form and the “no-

operands” form. The explicit-operands form (specified with the OUTS mnemonic) allows the source and destination

operands to be specified explicitly. Here, the source operand should be a symbol that indicates the size of the I/O

port and the source address, and the destination operand must be DX. This explicit-operands form is provided to

allow documentation; however, note that the documentation provided by this form can be misleading. That is, the

source operand symbol must specify the correct type (size) of the operand (byte, word, or doubleword), but it does

not have to specify the correct location. The location is always specified by the DS:(E)SI or RSI registers, which

must be loaded correctly before the OUTS instruction is executed.

The no-operands form provides “short forms” of the byte, word, and doubleword versions of the OUTS instructions.

Here also DS:(E)SI is assumed to be the source operand and DX is assumed to be the destination operand. The size

of the I/O port is specified with the choice of mnemonic: OUTSB (byte), OUTSW (word), or OUTSD (doubleword).

After the byte, word, or doubleword is transferred from the memory location to the I/O port, the SI/ESI/RSI

(If the DF flag is 0, the (E)SI register is incremented; if the DF flag is 1, the SI/ESI/RSI register is decremented.)

The SI/ESI/RSI register is incremented or decremented by 1 for byte operations, by 2 for word operations, and by

4 for doubleword operations.

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OUTS/OUTSB/OUTSW/OUTSD—Output String to Port

INSTRUCTION SET REFERENCE, M-U

The OUTS, OUTSB, OUTSW, and OUTSD instructions can be preceded by the REP prefix for block input of ECX

bytes, words, or doublewords. See “REP/REPE/REPZ /REPNE/REPNZ—Repeat String Operation Prefix” in this

chapter for a description of the REP prefix. This instruction is only useful for accessing I/O ports located in the

processor’s I/O address space. See Chapter 19, “Input/Output,” in the Intel® 64 and IA-32 Architectures Software

Developer’s Manual, Volume 1, for more information on accessing I/O ports in the I/O address space.

In 64-bit mode, the default operand size is 32 bits; operand size is not promoted by the use of REX.W. In 64-bit

mode, the default address size is 64 bits, and 64-bit address is specified using RSI by default. 32-bit address using

ESI is support using the prefix 67H, but 16-bit address is not supported in 64-bit mode.

IA-32 Architecture Compatibility

After executing an OUTS, OUTSB, OUTSW, or OUTSD instruction, the Pentium processor ensures that the EWBE#

pin has been sampled active before it begins to execute the next instruction. (Note that the instruction can be

prefetched if EWBE# is not active, but it will not be executed until the EWBE# pin is sampled active.) Only the

Pentium processor family has the EWBE# pin.

For the Pentium 4, Intel^® Xeon^®, and P6 processor family, upon execution of an OUTS, OUTSB, OUTSW, or OUTSD

instruction, the processor will not execute the next instruction until the data phase of the transaction is complete.

Operation

IF ((PE = 1) and ((CPL > IOPL) or (VM = 1)))

THEN (* Protected mode with CPL > IOPL or virtual-8086 mode *)

IF (Any I/O Permission Bit for I/O port being accessed = 1)

THEN (* I/O operation is not allowed *)

#GP(0);

ELSE (* I/O operation is allowed *)

DEST := SRC; (* Writes to I/O port *)

FI;

ELSE (Real Mode or Protected Mode or 64-Bit Mode with CPL ≤ IOPL *)

DEST := SRC; (* Writes to I/O port *)

FI;

Byte transfer:

IF 64-bit mode

Then

IF 64-Bit Address Size

THEN

IF DF = 0

THEN RSI := RSI RSI + 1;

ELSE RSI := RSI or - 1;

FI;

ELSE (* 32-Bit Address Size *)

IF DF = 0

THEN ESI := ESI + 1;

ELSE

ESI := ESI - 1;

FI;

ELSE

IF DF = 0

THEN

(E)SI := (E)SI + 1;

ELSE (E)SI := (E)SI - 1;

FI;

Word transfer:

IF 64-bit mode

OUTS/OUTSB/OUTSW/OUTSD—Output String to Port

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INSTRUCTION SET REFERENCE, M-U

Protected Mode Exceptions

#GP(0)

If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the

corresponding I/O permission bits in TSS for the I/O port being accessed is 1.

If a memory operand effective address is outside the limit of the CS, DS, ES, FS, or GS

segment.

If the segment register contains a NULL segment selector.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If the LOCK prefix is used.

Real-Address Mode Exceptions

#GP

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS

If a memory operand effective address is outside the SS segment limit.

#UD

If the LOCK prefix is used.

Virtual-8086 Mode Exceptions

#GP(0)

If any of the I/O permission bits in the TSS for the I/O port being accessed is 1.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made.

#UD

If the LOCK prefix is used.

Compatibility Mode Exceptions

Same as for protected mode exceptions.

64-Bit Mode Exceptions

#SS(0)

If a memory address referencing the SS segment is in a non-canonical form.

#GP(0)

If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the

corresponding I/O permission bits in TSS for the I/O port being accessed is 1.

If the memory address is in a non-canonical form.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If the LOCK prefix is used.

OUTS/OUTSB/OUTSW/OUTSD—Output String to Port

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INSTRUCTION SET REFERENCE, M-U

PABSB/PABSW/PABSD/PABSQ—Packed Absolute Value

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

NP 0F 38 1C /r¹

V/V

SSSE3

Compute the absolute value of bytes in

mm2/m64 and store UNSIGNED result in mm1.

PABSB mm1, mm2/m64

66 0F 38 1C /r

V/V

SSSE3

Compute the absolute value of bytes in

xmm2/m128 and store UNSIGNED result in

PABSB xmm1, xmm2/m128

xmm1.

NP 0F 38 1D /r¹

V/V

SSSE3

Compute the absolute value of 16-bit integers

in mm2/m64 and store UNSIGNED result in

PABSW mm1, mm2/m64

mm1.

66 0F 38 1D /r

V/V

SSSE3

Compute the absolute value of 16-bit integers

in xmm2/m128 and store UNSIGNED result in

PABSW xmm1, xmm2/m128

xmm1.

NP 0F 38 1E /r¹

V/V

SSSE3

Compute the absolute value of 32-bit integers

in mm2/m64 and store UNSIGNED result in

PABSD mm1, mm2/m64

mm1.

66 0F 38 1E /r

V/V

SSSE3

Compute the absolute value of 32-bit integers

in xmm2/m128 and store UNSIGNED result in

PABSD xmm1, xmm2/m128

xmm1.

VEX.128.66.0F38.WIG 1C /r

V/V

AVX

Compute the absolute value of bytes in

xmm2/m128 and store UNSIGNED result in

VPABSB xmm1, xmm2/m128

xmm1.

VEX.128.66.0F38.WIG 1D /r

V/V

AVX

Compute the absolute value of 16- bit

integers in xmm2/m128 and store UNSIGNED

VPABSW xmm1, xmm2/m128

result in xmm1.

VEX.128.66.0F38.WIG 1E /r

V/V

AVX

Compute the absolute value of 32- bit

integers in xmm2/m128 and store UNSIGNED

VPABSD xmm1, xmm2/m128

result in xmm1.

VEX.256.66.0F38.WIG 1C /r

V/V

AVX2

Compute the absolute value of bytes in

VPABSB ymm1, ymm2/m256

ymm2/m256 and store UNSIGNED result in

ymm1.

VEX.256.66.0F38.WIG 1D /r

V/V

AVX2

Compute the absolute value of 16-bit integers

in ymm2/m256 and store UNSIGNED result in

VPABSW ymm1, ymm2/m256

ymm1.

VEX.256.66.0F38.WIG 1E /r

V/V

AVX2

Compute the absolute value of 32-bit integers

in ymm2/m256 and store UNSIGNED result in

VPABSD ymm1, ymm2/m256

ymm1.

EVEX.128.66.0F38.WIG 1C /r

V/V

AVX512VL

Compute the absolute value of bytes in

VPABSB xmm1 {k1}{z}, xmm2/m128

AVX512BW

xmm2/m128 and store UNSIGNED result in

xmm1 using writemask k1.

EVEX.256.66.0F38.WIG 1C /r

V/V

AVX512VL

Compute the absolute value of bytes in

VPABSB ymm1 {k1}{z}, ymm2/m256

AVX512BW

ymm2/m256 and store UNSIGNED result in

ymm1 using writemask k1.

EVEX.512.66.0F38.WIG 1C /r

V/V

AVX512BW

Compute the absolute value of bytes in

VPABSB zmm1 {k1}{z}, zmm2/m512

zmm2/m512 and store UNSIGNED result in

zmm1 using writemask k1.

EVEX.128.66.0F38.WIG 1D /r

V/V

AVX512VL

Compute the absolute value of 16-bit integers

VPABSW xmm1 {k1}{z}, xmm2/m128

AVX512BW

in xmm2/m128 and store UNSIGNED result in

xmm1 using writemask k1.

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PABSB/PABSW/PABSD/PABSQ—Packed Absolute Value

INSTRUCTION SET REFERENCE, M-U

EVEX.256.66.0F38.WIG 1D /r

V/V

AVX512VL

Compute the absolute value of 16-bit integers

VPABSW ymm1 {k1}{z}, ymm2/m256

AVX512BW

in ymm2/m256 and store UNSIGNED result in

ymm1 using writemask k1.

EVEX.512.66.0F38.WIG 1D /r

V/V

AVX512BW

Compute the absolute value of 16-bit integers

VPABSW zmm1 {k1}{z}, zmm2/m512

in zmm2/m512 and store UNSIGNED result in

zmm1 using writemask k1.

EVEX.128.66.0F38.W0 1E /r

V/V

AVX512VL

Compute the absolute value of 32-bit integers

VPABSD xmm1 {k1}{z}, xmm2/m128/m32bcst

AVX512F

in xmm2/m128/m32bcst and store UNSIGNED

result in xmm1 using writemask k1.

EVEX.256.66.0F38.W0 1E /r

V/V

AVX512VL

Compute the absolute value of 32-bit integers

VPABSD ymm1 {k1}{z}, ymm2/m256/m32bcst

AVX512F

in ymm2/m256/m32bcst and store UNSIGNED

result in ymm1 using writemask k1.

EVEX.512.66.0F38.W0 1E /r

V/V

AVX512F

Compute the absolute value of 32-bit integers

VPABSD zmm1 {k1}{z}, zmm2/m512/m32bcst

in zmm2/m512/m32bcst and store UNSIGNED

result in zmm1 using writemask k1.

EVEX.128.66.0F38.W1 1F /r

V/V

AVX512VL

Compute the absolute value of 64-bit integers

VPABSQ xmm1 {k1}{z}, xmm2/m128/m64bcst

AVX512F

in xmm2/m128/m64bcst and store UNSIGNED

result in xmm1 using writemask k1.

EVEX.256.66.0F38.W1 1F /r

V/V

AVX512VL

Compute the absolute value of 64-bit integers

VPABSQ ymm1 {k1}{z}, ymm2/m256/m64bcst

AVX512F

in ymm2/m256/m64bcst and store UNSIGNED

result in ymm1 using writemask k1.

EVEX.512.66.0F38.W1 1F /r

V/V

AVX512F

Compute the absolute value of 64-bit integers

VPABSQ zmm1 {k1}{z}, zmm2/m512/m64bcst

in zmm2/m512/m64bcst and store UNSIGNED

result in zmm1 using writemask k1.

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2A and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Reg-

isters” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

Full Mem

ModRM:reg (w)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

PABSB/W/D computes the absolute value of each data element of the source operand (the second operand) and

stores the UNSIGNED results in the destination operand (the first operand). PABSB operates on signed bytes,

PABSW operates on signed 16-bit words, and PABSD operates on signed 32-bit integers.

EVEX encoded VPABSD/Q: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location,

or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The destination operand is a

ZMM/YMM/XMM register updated according to the writemask.

EVEX encoded VPABSB/W: The source operand is a ZMM/YMM/XMM register, or a 512/256/128-bit memory loca-

tion. The destination operand is a ZMM/YMM/XMM register updated according to the writemask.

VEX.256 encoded versions: The source operand is a YMM register or a 256-bit memory location. The destination

operand is a YMM register. The upper bits (MAXVL-1:256) of the corresponding register destination are zeroed.

VEX.128 encoded versions: The source operand is an XMM register or 128-bit memory location. The destination

operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding register destination are zeroed.

PABSB/PABSW/PABSD/PABSQ—Packed Absolute Value

Vol. 2B

4-187

INSTRUCTION SET REFERENCE, M-U

128-bit Legacy SSE version: The source operand can be an XMM register or an 128-bit memory location. The desti-

nation is an XMM register. The upper bits (VL_MAX-1:128) of the corresponding register destination are unmodi-

fied.

VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.

Operation

PABSB with 128 bit operands:

Unsigned DEST[7:0] := ABS(SRC[7: 0])

Repeat operation for 2nd through 15th bytes

Unsigned DEST[127:120] := ABS(SRC[127:120])

VPABSB with 128 bit operands:

Unsigned DEST[7:0] := ABS(SRC[7: 0])

Repeat operation for 2nd through 15th bytes

Unsigned DEST[127:120] := ABS(SRC[127:120])

VPABSB with 256 bit operands:

Unsigned DEST[7:0] := ABS(SRC[7: 0])

Repeat operation for 2nd through 31st bytes

Unsigned DEST[255:248] := ABS(SRC[255:248])

VPABSB (EVEX encoded versions)

(KL, VL) = (16, 128), (32, 256), (64, 512)

FOR j := 0 TO KL-1

i := j * 8

IF k1[j] OR *no writemask*

THEN

Unsigned DEST[i+7:i] := ABS(SRC[i+7:i])

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+7:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+7:i] := 0

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

PABSW with 128 bit operands:

Unsigned DEST[15:0] := ABS(SRC[15:0])

Repeat operation for 2nd through 7th 16-bit words

Unsigned DEST[127:112] := ABS(SRC[127:112])

VPABSW with 128 bit operands:

Unsigned DEST[15:0] := ABS(SRC[15:0])

Repeat operation for 2nd through 7th 16-bit words

Unsigned DEST[127:112] := ABS(SRC[127:112])

VPABSW with 256 bit operands:

Unsigned DEST[15:0] := ABS(SRC[15:0])

Repeat operation for 2nd through 15th 16-bit words

Unsigned DEST[255:240] := ABS(SRC[255:240])

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PABSB/PABSW/PABSD/PABSQ—Packed Absolute Value

INSTRUCTION SET REFERENCE, M-U

VPABSW (EVEX encoded versions)

(KL, VL) = (8, 128), (16, 256), (32, 512)

FOR j := 0 TO KL-1

i := j * 16

IF k1[j] OR *no writemask*

THEN

Unsigned DEST[i+15:i] := ABS(SRC[i+15:i])

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+15:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+15:i] := 0

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

PABSD with 128 bit operands:

Unsigned DEST[31:0] := ABS(SRC[31:0])

Repeat operation for 2nd through 3rd 32-bit double words

Unsigned DEST[127:96] := ABS(SRC[127:96])

VPABSD with 128 bit operands:

Unsigned DEST[31:0] := ABS(SRC[31:0])

Repeat operation for 2nd through 3rd 32-bit double words

Unsigned DEST[127:96] := ABS(SRC[127:96])

VPABSD with 256 bit operands:

Unsigned DEST[31:0] := ABS(SRC[31:0])

Repeat operation for 2nd through 7th 32-bit double words

Unsigned DEST[255:224] := ABS(SRC[255:224])

VPABSD (EVEX encoded versions)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b = 1) AND (SRC *is memory*)

THEN

Unsigned DEST[i+31:i] := ABS(SRC[31:0])

ELSE

Unsigned DEST[i+31:i] := ABS(SRC[i+31:i])

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

PABSB/PABSW/PABSD/PABSQ—Packed Absolute Value

Vol. 2B

4-189

INSTRUCTION SET REFERENCE, M-U

VPABSQ (EVEX encoded versions)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b = 1) AND (SRC *is memory*)

THEN

Unsigned DEST[i+63:i] := ABS(SRC[63:0])

ELSE

Unsigned DEST[i+63:i] := ABS(SRC[i+63:i])

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

Intel C/C++ Compiler Intrinsic Equivalents

VPABSB__m512i _mm512_abs_epi8 ( __m512i a)

VPABSW__m512i _mm512_abs_epi16 ( __m512i a)

VPABSB__m512i _mm512_mask_abs_epi8 ( __m512i s, __mmask64 m, __m512i a)

VPABSW__m512i _mm512_mask_abs_epi16 ( __m512i s, __mmask32 m, __m512i a)

VPABSB__m512i _mm512_maskz_abs_epi8 (__mmask64 m, __m512i a)

VPABSW__m512i _mm512_maskz_abs_epi16 (__mmask32 m, __m512i a)

VPABSB__m256i _mm256_mask_abs_epi8 (__m256i s, __mmask32 m, __m256i a)

VPABSW__m256i _mm256_mask_abs_epi16 (__m256i s, __mmask16 m, __m256i a)

VPABSB__m256i _mm256_maskz_abs_epi8 (__mmask32 m, __m256i a)

VPABSW__m256i _mm256_maskz_abs_epi16 (__mmask16 m, __m256i a)

VPABSB__m128i _mm_mask_abs_epi8 (__m128i s, __mmask16 m, __m128i a)

VPABSW__m128i _mm_mask_abs_epi16 (__m128i s, __mmask8 m, __m128i a)

VPABSB__m128i _mm_maskz_abs_epi8 (__mmask16 m, __m128i a)

VPABSW__m128i _mm_maskz_abs_epi16 (__mmask8 m, __m128i a)

VPABSD __m256i _mm256_mask_abs_epi32(__m256i s, __mmask8 k, __m256i a);

VPABSD __m256i _mm256_maskz_abs_epi32( __mmask8 k, __m256i a);

VPABSD __m128i _mm_mask_abs_epi32(__m128i s, __mmask8 k, __m128i a);

VPABSD __m128i _mm_maskz_abs_epi32( __mmask8 k, __m128i a);

VPABSD __m512i _mm512_abs_epi32( __m512i a);

VPABSD __m512i _mm512_mask_abs_epi32(__m512i s, __mmask16 k, __m512i a);

VPABSD __m512i _mm512_maskz_abs_epi32( __mmask16 k, __m512i a);

VPABSQ __m512i _mm512_abs_epi64( __m512i a);

VPABSQ __m512i _mm512_mask_abs_epi64(__m512i s, __mmask8 k, __m512i a);

VPABSQ __m512i _mm512_maskz_abs_epi64( __mmask8 k, __m512i a);

VPABSQ __m256i _mm256_mask_abs_epi64(__m256i s, __mmask8 k, __m256i a);

VPABSQ __m256i _mm256_maskz_abs_epi64( __mmask8 k, __m256i a);

VPABSQ __m128i _mm_mask_abs_epi64(__m128i s, __mmask8 k, __m128i a);

VPABSQ __m128i _mm_maskz_abs_epi64( __mmask8 k, __m128i a);

PABSB __m128i _mm_abs_epi8 (__m128i a)

VPABSB __m128i _mm_abs_epi8 (__m128i a)

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PABSB/PABSW/PABSD/PABSQ—Packed Absolute Value

INSTRUCTION SET REFERENCE, M-U

PACKSSWB/PACKSSDW—Pack With Signed Saturation

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature Flag

Support

NP 0F 63 /r¹

V/V

MMX

Converts 4 packed signed word integers from

mm1 and from mm2/m64 into 8 packed

PACKSSWB mm1, mm2/m64

signed byte integers in mm1 using signed

saturation.

66 0F 63 /r

V/V

SSE2

Converts 8 packed signed word integers from

xmm1 and from xmm2/m128 into 16 packed

PACKSSWB xmm1, xmm2/m128

signed byte integers in xmm1 using signed

saturation.

NP 0F 6B /r¹

V/V

MMX

Converts 2 packed signed doubleword

integers from mm1 and from mm2/m64 into 4

PACKSSDW mm1, mm2/m64

packed signed word integers in mm1 using

signed saturation.

66 0F 6B /r

V/V

SSE2

Converts 4 packed signed doubleword

integers from xmm1 and from xmm2/m128

PACKSSDW xmm1, xmm2/m128

into 8 packed signed word integers in xmm1

using signed saturation.

VEX.128.66.0F.WIG 63 /r

V/V

AVX

Converts 8 packed signed word integers from

xmm2 and from xmm3/m128 into 16 packed

VPACKSSWB xmm1,xmm2, xmm3/m128

signed byte integers in xmm1 using signed

saturation.

VEX.128.66.0F.WIG 6B /r

V/V

AVX

Converts 4 packed signed doubleword

integers from xmm2 and from xmm3/m128

VPACKSSDW xmm1,xmm2, xmm3/m128

into 8 packed signed word integers in xmm1

using signed saturation.

VEX.256.66.0F.WIG 63 /r

V/V

AVX2

Converts 16 packed signed word integers

VPACKSSWB ymm1, ymm2, ymm3/m256

from ymm2 and from ymm3/m256 into 32

packed signed byte integers in ymm1 using

signed saturation.

VEX.256.66.0F.WIG 6B /r

V/V

AVX2

Converts 8 packed signed doubleword

VPACKSSDW ymm1, ymm2, ymm3/m256

integers from ymm2 and from ymm3/m256

into 16 packed signed word integers in

ymm1using signed saturation.

EVEX.128.66.0F.WIG 63 /r

V/V

AVX512VL

Converts packed signed word integers from

VPACKSSWB xmm1 {k1}{z}, xmm2, xmm3/m128

AVX512BW

xmm2 and from xmm3/m128 into packed

signed byte integers in xmm1 using signed

saturation under writemask k1.

EVEX.256.66.0F.WIG 63 /r

V/V

AVX512VL

Converts packed signed word integers from

VPACKSSWB ymm1 {k1}{z}, ymm2, ymm3/m256

AVX512BW

ymm2 and from ymm3/m256 into packed

signed byte integers in ymm1 using signed

saturation under writemask k1.

EVEX.512.66.0F.WIG 63 /r

V/V

AVX512BW

Converts packed signed word integers from

VPACKSSWB zmm1 {k1}{z}, zmm2, zmm3/m512

zmm2 and from zmm3/m512 into packed

signed byte integers in zmm1 using signed

saturation under writemask k1.

EVEX.128.66.0F.W0 6B /r

V/V

AVX512VL

Converts packed signed doubleword integers

VPACKSSDW xmm1 {k1}{z}, xmm2,

AVX512BW

from xmm2 and from xmm3/m128/m32bcst

xmm3/m128/m32bcst

into packed signed word integers in xmm1

using signed saturation under writemask k1.

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PACKSSWB/PACKSSDW—Pack With Signed Saturation

INSTRUCTION SET REFERENCE, M-U

EVEX.256.66.0F.W0 6B /r

V/V

AVX512VL

Converts packed signed doubleword integers

VPACKSSDW ymm1 {k1}{z}, ymm2,

AVX512BW

from ymm2 and from ymm3/m256/m32bcst

ymm3/m256/m32bcst

into packed signed word integers in ymm1

using signed saturation under writemask k1.

EVEX.512.66.0F.W0 6B /r

V/V

AVX512BW

Converts packed signed doubleword integers

VPACKSSDW zmm1 {k1}{z}, zmm2,

from zmm2 and from zmm3/m512/m32bcst

zmm3/m512/m32bcst

into packed signed word integers in zmm1

using signed saturation under writemask k1.

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2A and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Reg-

isters” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full Mem

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Converts packed signed word integers into packed signed byte integers (PACKSSWB) or converts packed signed

doubleword integers into packed signed word integers (PACKSSDW), using saturation to handle overflow condi-

tions. See Figure 4-6 for an example of the packing operation.

64-Bit SRC

64-Bit DEST

D’

C’

B’

A’

64-Bit DEST

Figure 4-6. Operation of the PACKSSDW Instruction Using 64-Bit Operands

PACKSSWB converts packed signed word integers in the first and second source operands into packed signed byte

integers using signed saturation to handle overflow conditions beyond the range of signed byte integers. If the

signed word value is beyond the range of a signed byte value (i.e., greater than 7FH or less than 80H), the satu-

rated signed byte integer value of 7FH or 80H, respectively, is stored in the destination. PACKSSDW converts

packed signed doubleword integers in the first and second source operands into packed signed word integers using

signed saturation to handle overflow conditions beyond 7FFFH and 8000H.

EVEX encoded PACKSSWB: The first source operand is a ZMM/YMM/XMM register. The second source operand is a

ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand is a ZMM/YMM/XMM

EVEX encoded PACKSSDW: The first source operand is a ZMM/YMM/XMM register. The second source operand is a

ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 32-

bit memory location. The destination operand is a ZMM/YMM/XMM register, updated conditional under the

writemask k1.

PACKSSWB/PACKSSDW—Pack With Signed Saturation

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4-193

INSTRUCTION SET REFERENCE, M-U

VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register

or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAXVL-1:256) of the

corresponding ZMM register destination are zeroed.

VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM

the corresponding ZMM register destination are zeroed.

128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM

upper bits (MAXVL-1:128) of the corresponding ZMM destination register destination are unmodified.

Operation

PACKSSWB instruction (128-bit Legacy SSE version)

DEST[7:0] := SaturateSignedWordToSignedByte (DEST[15:0]);

DEST[15:8] := SaturateSignedWordToSignedByte (DEST[31:16]);

DEST[23:16] := SaturateSignedWordToSignedByte (DEST[47:32]);

DEST[31:24] := SaturateSignedWordToSignedByte (DEST[63:48]);

DEST[39:32] := SaturateSignedWordToSignedByte (DEST[79:64]);

DEST[47:40] := SaturateSignedWordToSignedByte (DEST[95:80]);

DEST[55:48] := SaturateSignedWordToSignedByte (DEST[111:96]);

DEST[63:56] := SaturateSignedWordToSignedByte (DEST[127:112]);

DEST[71:64] := SaturateSignedWordToSignedByte (SRC[15:0]);

DEST[79:72] := SaturateSignedWordToSignedByte (SRC[31:16]);

DEST[87:80] := SaturateSignedWordToSignedByte (SRC[47:32]);

DEST[95:88] := SaturateSignedWordToSignedByte (SRC[63:48]);

DEST[103:96] := SaturateSignedWordToSignedByte (SRC[79:64]);

DEST[111:104] := SaturateSignedWordToSignedByte (SRC[95:80]);

DEST[119:112] := SaturateSignedWordToSignedByte (SRC[111:96]);

DEST[127:120] := SaturateSignedWordToSignedByte (SRC[127:112]);

DEST[MAXVL-1:128] (Unmodified)

PACKSSDW instruction (128-bit Legacy SSE version)

DEST[15:0] := SaturateSignedDwordToSignedWord (DEST[31:0]);

DEST[31:16] := SaturateSignedDwordToSignedWord (DEST[63:32]);

DEST[47:32] := SaturateSignedDwordToSignedWord (DEST[95:64]);

DEST[63:48] := SaturateSignedDwordToSignedWord (DEST[127:96]);

DEST[79:64] := SaturateSignedDwordToSignedWord (SRC[31:0]);

DEST[95:80] := SaturateSignedDwordToSignedWord (SRC[63:32]);

DEST[111:96] := SaturateSignedDwordToSignedWord (SRC[95:64]);

DEST[127:112] := SaturateSignedDwordToSignedWord (SRC[127:96]);

DEST[MAXVL-1:128] (Unmodified)

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PACKSSWB/PACKSSDW—Pack With Signed Saturation

INSTRUCTION SET REFERENCE, M-U

VPACKSSWB instruction (VEX.128 encoded version)

DEST[7:0] := SaturateSignedWordToSignedByte (SRC1[15:0]);

DEST[15:8] := SaturateSignedWordToSignedByte (SRC1[31:16]);

DEST[23:16] := SaturateSignedWordToSignedByte (SRC1[47:32]);

DEST[31:24] := SaturateSignedWordToSignedByte (SRC1[63:48]);

DEST[39:32] := SaturateSignedWordToSignedByte (SRC1[79:64]);

DEST[47:40] := SaturateSignedWordToSignedByte (SRC1[95:80]);

DEST[55:48] := SaturateSignedWordToSignedByte (SRC1[111:96]);

DEST[63:56] := SaturateSignedWordToSignedByte (SRC1[127:112]);

DEST[71:64] := SaturateSignedWordToSignedByte (SRC2[15:0]);

DEST[79:72] := SaturateSignedWordToSignedByte (SRC2[31:16]);

DEST[87:80] := SaturateSignedWordToSignedByte (SRC2[47:32]);

DEST[95:88] := SaturateSignedWordToSignedByte (SRC2[63:48]);

DEST[103:96] := SaturateSignedWordToSignedByte (SRC2[79:64]);

DEST[111:104] := SaturateSignedWordToSignedByte (SRC2[95:80]);

DEST[119:112] := SaturateSignedWordToSignedByte (SRC2[111:96]);

DEST[127:120] := SaturateSignedWordToSignedByte (SRC2[127:112]);

DEST[MAXVL-1:128] := 0;

VPACKSSDW instruction (VEX.128 encoded version)

DEST[15:0] := SaturateSignedDwordToSignedWord (SRC1[31:0]);

DEST[31:16] := SaturateSignedDwordToSignedWord (SRC1[63:32]);

DEST[47:32] := SaturateSignedDwordToSignedWord (SRC1[95:64]);

DEST[63:48] := SaturateSignedDwordToSignedWord (SRC1[127:96]);

DEST[79:64] := SaturateSignedDwordToSignedWord (SRC2[31:0]);

DEST[95:80] := SaturateSignedDwordToSignedWord (SRC2[63:32]);

DEST[111:96] := SaturateSignedDwordToSignedWord (SRC2[95:64]);

DEST[127:112] := SaturateSignedDwordToSignedWord (SRC2[127:96]);

DEST[MAXVL-1:128] := 0;

VPACKSSWB instruction (VEX.256 encoded version)

DEST[7:0] := SaturateSignedWordToSignedByte (SRC1[15:0]);

DEST[15:8] := SaturateSignedWordToSignedByte (SRC1[31:16]);

DEST[23:16] := SaturateSignedWordToSignedByte (SRC1[47:32]);

DEST[31:24] := SaturateSignedWordToSignedByte (SRC1[63:48]);

DEST[39:32] := SaturateSignedWordToSignedByte (SRC1[79:64]);

DEST[47:40] := SaturateSignedWordToSignedByte (SRC1[95:80]);

DEST[55:48] := SaturateSignedWordToSignedByte (SRC1[111:96]);

DEST[63:56] := SaturateSignedWordToSignedByte (SRC1[127:112]);

DEST[71:64] := SaturateSignedWordToSignedByte (SRC2[15:0]);

DEST[79:72] := SaturateSignedWordToSignedByte (SRC2[31:16]);

DEST[87:80] := SaturateSignedWordToSignedByte (SRC2[47:32]);

DEST[95:88] := SaturateSignedWordToSignedByte (SRC2[63:48]);

DEST[103:96] := SaturateSignedWordToSignedByte (SRC2[79:64]);

DEST[111:104] := SaturateSignedWordToSignedByte (SRC2[95:80]);

DEST[119:112] := SaturateSignedWordToSignedByte (SRC2[111:96]);

DEST[127:120] := SaturateSignedWordToSignedByte (SRC2[127:112]);

DEST[135:128] := SaturateSignedWordToSignedByte (SRC1[143:128]);

DEST[143:136] := SaturateSignedWordToSignedByte (SRC1[159:144]);

DEST[151:144] := SaturateSignedWordToSignedByte (SRC1[175:160]);

DEST[159:152] := SaturateSignedWordToSignedByte (SRC1[191:176]);

DEST[167:160] := SaturateSignedWordToSignedByte (SRC1[207:192]);

DEST[175:168] := SaturateSignedWordToSignedByte (SRC1[223:208]);

DEST[183:176] := SaturateSignedWordToSignedByte (SRC1[239:224]);

PACKSSWB/PACKSSDW—Pack With Signed Saturation

Vol. 2B

4-195

INSTRUCTION SET REFERENCE, M-U

DEST[191:184] := SaturateSignedWordToSignedByte (SRC1[255:240]);

DEST[199:192] := SaturateSignedWordToSignedByte (SRC2[143:128]);

DEST[207:200] := SaturateSignedWordToSignedByte (SRC2[159:144]);

DEST[215:208] := SaturateSignedWordToSignedByte (SRC2[175:160]);

DEST[223:216] := SaturateSignedWordToSignedByte (SRC2[191:176]);

DEST[231:224] := SaturateSignedWordToSignedByte (SRC2[207:192]);

DEST[239:232] := SaturateSignedWordToSignedByte (SRC2[223:208]);

DEST[247:240] := SaturateSignedWordToSignedByte (SRC2[239:224]);

DEST[255:248] := SaturateSignedWordToSignedByte (SRC2[255:240]);

DEST[MAXVL-1:256] := 0;

VPACKSSDW instruction (VEX.256 encoded version)

DEST[15:0] := SaturateSignedDwordToSignedWord (SRC1[31:0]);

DEST[31:16] := SaturateSignedDwordToSignedWord (SRC1[63:32]);

DEST[47:32] := SaturateSignedDwordToSignedWord (SRC1[95:64]);

DEST[63:48] := SaturateSignedDwordToSignedWord (SRC1[127:96]);

DEST[79:64] := SaturateSignedDwordToSignedWord (SRC2[31:0]);

DEST[95:80] := SaturateSignedDwordToSignedWord (SRC2[63:32]);

DEST[111:96] := SaturateSignedDwordToSignedWord (SRC2[95:64]);

DEST[127:112] := SaturateSignedDwordToSignedWord (SRC2[127:96]);

DEST[143:128] := SaturateSignedDwordToSignedWord (SRC1[159:128]);

DEST[159:144] := SaturateSignedDwordToSignedWord (SRC1[191:160]);

DEST[175:160] := SaturateSignedDwordToSignedWord (SRC1[223:192]);

DEST[191:176] := SaturateSignedDwordToSignedWord (SRC1[255:224]);

DEST[207:192] := SaturateSignedDwordToSignedWord (SRC2[159:128]);

DEST[223:208] := SaturateSignedDwordToSignedWord (SRC2[191:160]);

DEST[239:224] := SaturateSignedDwordToSignedWord (SRC2[223:192]);

DEST[255:240] := SaturateSignedDwordToSignedWord (SRC2[255:224]);

DEST[MAXVL-1:256] := 0;

VPACKSSWB (EVEX encoded versions)

(KL, VL) = (16, 128), (32, 256), (64, 512)

TMP_DEST[7:0] := SaturateSignedWordToSignedByte (SRC1[15:0]);

TMP_DEST[15:8] := SaturateSignedWordToSignedByte (SRC1[31:16]);

TMP_DEST[23:16] := SaturateSignedWordToSignedByte (SRC1[47:32]);

TMP_DEST[31:24] := SaturateSignedWordToSignedByte (SRC1[63:48]);

TMP_DEST[39:32] := SaturateSignedWordToSignedByte (SRC1[79:64]);

TMP_DEST[47:40] := SaturateSignedWordToSignedByte (SRC1[95:80]);

TMP_DEST[55:48] := SaturateSignedWordToSignedByte (SRC1[111:96]);

TMP_DEST[63:56] := SaturateSignedWordToSignedByte (SRC1[127:112]);

TMP_DEST[71:64] := SaturateSignedWordToSignedByte (SRC2[15:0]);

TMP_DEST[79:72] := SaturateSignedWordToSignedByte (SRC2[31:16]);

TMP_DEST[87:80] := SaturateSignedWordToSignedByte (SRC2[47:32]);

TMP_DEST[95:88] := SaturateSignedWordToSignedByte (SRC2[63:48]);

TMP_DEST[103:96] := SaturateSignedWordToSignedByte (SRC2[79:64]);

TMP_DEST[111:104] := SaturateSignedWordToSignedByte (SRC2[95:80]);

TMP_DEST[119:112] := SaturateSignedWordToSignedByte (SRC2[111:96]);

TMP_DEST[127:120] := SaturateSignedWordToSignedByte (SRC2[127:112]);

IF VL >= 256

TMP_DEST[135:128] := SaturateSignedWordToSignedByte (SRC1[143:128]);

TMP_DEST[143:136] := SaturateSignedWordToSignedByte (SRC1[159:144]);

TMP_DEST[151:144] := SaturateSignedWordToSignedByte (SRC1[175:160]);

TMP_DEST[159:152] := SaturateSignedWordToSignedByte (SRC1[191:176]);

TMP_DEST[167:160] := SaturateSignedWordToSignedByte (SRC1[207:192]);

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INSTRUCTION SET REFERENCE, M-U

TMP_DEST[175:168] := SaturateSignedWordToSignedByte (SRC1[223:208]);

TMP_DEST[183:176] := SaturateSignedWordToSignedByte (SRC1[239:224]);

TMP_DEST[191:184] := SaturateSignedWordToSignedByte (SRC1[255:240]);

TMP_DEST[199:192] := SaturateSignedWordToSignedByte (SRC2[143:128]);

TMP_DEST[207:200] := SaturateSignedWordToSignedByte (SRC2[159:144]);

TMP_DEST[215:208] := SaturateSignedWordToSignedByte (SRC2[175:160]);

TMP_DEST[223:216] := SaturateSignedWordToSignedByte (SRC2[191:176]);

TMP_DEST[231:224] := SaturateSignedWordToSignedByte (SRC2[207:192]);

TMP_DEST[239:232] := SaturateSignedWordToSignedByte (SRC2[223:208]);

TMP_DEST[247:240] := SaturateSignedWordToSignedByte (SRC2[239:224]);

TMP_DEST[255:248] := SaturateSignedWordToSignedByte (SRC2[255:240]);

FI;

IF VL >= 512

TMP_DEST[263:256] := SaturateSignedWordToSignedByte (SRC1[271:256]);

TMP_DEST[271:264] := SaturateSignedWordToSignedByte (SRC1[287:272]);

TMP_DEST[279:272] := SaturateSignedWordToSignedByte (SRC1[303:288]);

TMP_DEST[287:280] := SaturateSignedWordToSignedByte (SRC1[319:304]);

TMP_DEST[295:288] := SaturateSignedWordToSignedByte (SRC1[335:320]);

TMP_DEST[303:296] := SaturateSignedWordToSignedByte (SRC1[351:336]);

TMP_DEST[311:304] := SaturateSignedWordToSignedByte (SRC1[367:352]);

TMP_DEST[319:312] := SaturateSignedWordToSignedByte (SRC1[383:368]);

TMP_DEST[327:320] := SaturateSignedWordToSignedByte (SRC2[271:256]);

TMP_DEST[335:328] := SaturateSignedWordToSignedByte (SRC2[287:272]);

TMP_DEST[343:336] := SaturateSignedWordToSignedByte (SRC2[303:288]);

TMP_DEST[351:344] := SaturateSignedWordToSignedByte (SRC2[319:304]);

TMP_DEST[359:352] := SaturateSignedWordToSignedByte (SRC2[335:320]);

TMP_DEST[367:360] := SaturateSignedWordToSignedByte (SRC2[351:336]);

TMP_DEST[375:368] := SaturateSignedWordToSignedByte (SRC2[367:352]);

TMP_DEST[383:376] := SaturateSignedWordToSignedByte (SRC2[383:368]);

TMP_DEST[391:384] := SaturateSignedWordToSignedByte (SRC1[399:384]);

TMP_DEST[399:392] := SaturateSignedWordToSignedByte (SRC1[415:400]);

TMP_DEST[407:400] := SaturateSignedWordToSignedByte (SRC1[431:416]);

TMP_DEST[415:408] := SaturateSignedWordToSignedByte (SRC1[447:432]);

TMP_DEST[423:416] := SaturateSignedWordToSignedByte (SRC1[463:448]);

TMP_DEST[431:424] := SaturateSignedWordToSignedByte (SRC1[479:464]);

TMP_DEST[439:432] := SaturateSignedWordToSignedByte (SRC1[495:480]);

TMP_DEST[447:440] := SaturateSignedWordToSignedByte (SRC1[511:496]);

TMP_DEST[455:448] := SaturateSignedWordToSignedByte (SRC2[399:384]);

TMP_DEST[463:456] := SaturateSignedWordToSignedByte (SRC2[415:400]);

TMP_DEST[471:464] := SaturateSignedWordToSignedByte (SRC2[431:416]);

TMP_DEST[479:472] := SaturateSignedWordToSignedByte (SRC2[447:432]);

TMP_DEST[487:480] := SaturateSignedWordToSignedByte (SRC2[463:448]);

TMP_DEST[495:488] := SaturateSignedWordToSignedByte (SRC2[479:464]);

TMP_DEST[503:496] := SaturateSignedWordToSignedByte (SRC2[495:480]);

TMP_DEST[511:504] := SaturateSignedWordToSignedByte (SRC2[511:496]);

FI;

FOR j := 0 TO KL-1

i := j * 8

IF k1[j] OR *no writemask*

THEN

DEST[i+7:i] := TMP_DEST[i+7:i]

PACKSSWB/PACKSSDW—Pack With Signed Saturation

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INSTRUCTION SET REFERENCE, M-U

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+7:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+7:i] := 0

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

VPACKSSDW (EVEX encoded versions)

(KL, VL) = (8, 128), (16, 256), (32, 512)

FOR j := 0 TO ((KL/2) - 1)

i := j * 32

IF (EVEX.b == 1) AND (SRC2 *is memory*)

THEN

TMP_SRC2[i+31:i] := SRC2[31:0]

ELSE

TMP_SRC2[i+31:i] := SRC2[i+31:i]

FI;

ENDFOR;

TMP_DEST[15:0] := SaturateSignedDwordToSignedWord (SRC1[31:0]);

TMP_DEST[31:16] := SaturateSignedDwordToSignedWord (SRC1[63:32]);

TMP_DEST[47:32] := SaturateSignedDwordToSignedWord (SRC1[95:64]);

TMP_DEST[63:48] := SaturateSignedDwordToSignedWord (SRC1[127:96]);

TMP_DEST[79:64] := SaturateSignedDwordToSignedWord (TMP_SRC2[31:0]);

TMP_DEST[95:80] := SaturateSignedDwordToSignedWord (TMP_SRC2[63:32]);

TMP_DEST[111:96] := SaturateSignedDwordToSignedWord (TMP_SRC2[95:64]);

TMP_DEST[127:112] := SaturateSignedDwordToSignedWord (TMP_SRC2[127:96]);

IF VL >= 256

TMP_DEST[143:128] := SaturateSignedDwordToSignedWord (SRC1[159:128]);

TMP_DEST[159:144] := SaturateSignedDwordToSignedWord (SRC1[191:160]);

TMP_DEST[175:160] := SaturateSignedDwordToSignedWord (SRC1[223:192]);

TMP_DEST[191:176] := SaturateSignedDwordToSignedWord (SRC1[255:224]);

TMP_DEST[207:192] := SaturateSignedDwordToSignedWord (TMP_SRC2[159:128]);

TMP_DEST[223:208] := SaturateSignedDwordToSignedWord (TMP_SRC2[191:160]);

TMP_DEST[239:224] := SaturateSignedDwordToSignedWord (TMP_SRC2[223:192]);

TMP_DEST[255:240] := SaturateSignedDwordToSignedWord (TMP_SRC2[255:224]);

FI;

IF VL >= 512

TMP_DEST[271:256] := SaturateSignedDwordToSignedWord (SRC1[287:256]);

TMP_DEST[287:272] := SaturateSignedDwordToSignedWord (SRC1[319:288]);

TMP_DEST[303:288] := SaturateSignedDwordToSignedWord (SRC1[351:320]);

TMP_DEST[319:304] := SaturateSignedDwordToSignedWord (SRC1[383:352]);

TMP_DEST[335:320] := SaturateSignedDwordToSignedWord (TMP_SRC2[287:256]);

TMP_DEST[351:336] := SaturateSignedDwordToSignedWord (TMP_SRC2[319:288]);

TMP_DEST[367:352] := SaturateSignedDwordToSignedWord (TMP_SRC2[351:320]);

TMP_DEST[383:368] := SaturateSignedDwordToSignedWord (TMP_SRC2[383:352]);

TMP_DEST[399:384] := SaturateSignedDwordToSignedWord (SRC1[415:384]);

TMP_DEST[415:400] := SaturateSignedDwordToSignedWord (SRC1[447:416]);

TMP_DEST[431:416] := SaturateSignedDwordToSignedWord (SRC1[479:448]);

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INSTRUCTION SET REFERENCE, M-U

TMP_DEST[447:432] := SaturateSignedDwordToSignedWord (SRC1[511:480]);

TMP_DEST[463:448] := SaturateSignedDwordToSignedWord (TMP_SRC2[415:384]);

TMP_DEST[479:464] := SaturateSignedDwordToSignedWord (TMP_SRC2[447:416]);

TMP_DEST[495:480] := SaturateSignedDwordToSignedWord (TMP_SRC2[479:448]);

TMP_DEST[511:496] := SaturateSignedDwordToSignedWord (TMP_SRC2[511:480]);

FI;

FOR j := 0 TO KL-1

i := j * 16

IF k1[j] OR *no writemask*

THEN DEST[i+15:i] := TMP_DEST[i+15:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+15:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+15:i] := 0

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

Intel C/C++ Compiler Intrinsic Equivalents

VPACKSSDW__m512i _mm512_packs_epi32(__m512i m1, __m512i m2);

VPACKSSDW__m512i _mm512_mask_packs_epi32(__m512i s, __mmask32 k, __m512i m1, __m512i m2);

VPACKSSDW__m512i _mm512_maskz_packs_epi32( __mmask32 k, __m512i m1, __m512i m2);

VPACKSSDW__m256i _mm256_mask_packs_epi32( __m256i s, __mmask16 k, __m256i m1, __m256i m2);

VPACKSSDW__m256i _mm256_maskz_packs_epi32( __mmask16 k, __m256i m1, __m256i m2);

VPACKSSDW__m128i _mm_mask_packs_epi32( __m128i s, __mmask8 k, __m128i m1, __m128i m2);

VPACKSSDW__m128i _mm_maskz_packs_epi32( __mmask8 k, __m128i m1, __m128i m2);

VPACKSSWB__m512i _mm512_packs_epi16(__m512i m1, __m512i m2);

VPACKSSWB__m512i _mm512_mask_packs_epi16(__m512i s, __mmask32 k, __m512i m1, __m512i m2);

VPACKSSWB__m512i _mm512_maskz_packs_epi16( __mmask32 k, __m512i m1, __m512i m2);

VPACKSSWB__m256i _mm256_mask_packs_epi16( __m256i s, __mmask16 k, __m256i m1, __m256i m2);

VPACKSSWB__m256i _mm256_maskz_packs_epi16( __mmask16 k, __m256i m1, __m256i m2);

VPACKSSWB__m128i _mm_mask_packs_epi16( __m128i s, __mmask8 k, __m128i m1, __m128i m2);

VPACKSSWB__m128i _mm_maskz_packs_epi16( __mmask8 k, __m128i m1, __m128i m2);

PACKSSWB __m128i _mm_packs_epi16(__m128i m1, __m128i m2)

PACKSSDW __m128i _mm_packs_epi32(__m128i m1, __m128i m2)

VPACKSSWB __m256i _mm256_packs_epi16(__m256i m1, __m256i m2)

VPACKSSDW __m256i _mm256_packs_epi32(__m256i m1, __m256i m2)

SIMD Floating-Point Exceptions

None

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions”.

EVEX-encoded VPACKSSDW, see Table 2-50, “Type E4NF Class Exception Conditions”.

EVEX-encoded VPACKSSWB, see Exceptions Type E4NF.nb in Table 2-50, “Type E4NF Class Exception Conditions”.

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INSTRUCTION SET REFERENCE, M-U

PACKUSDW—Pack With Unsigned Saturation

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

66 0F 38 2B /r

V/V

SSE4_1

Convert 4 packed signed doubleword integers from xmm1

PACKUSDW xmm1, xmm2/m128

and 4 packed signed doubleword integers from

xmm2/m128 into 8 packed unsigned word integers in

xmm1 using unsigned saturation.

VEX.128.66.0F38 2B /r

V/V

AVX

Convert 4 packed signed doubleword integers from xmm2

VPACKUSDW xmm1,xmm2,

and 4 packed signed doubleword integers from

xmm3/m128

xmm3/m128 into 8 packed unsigned word integers in

xmm1 using unsigned saturation.

VEX.256.66.0F38 2B /r

V/V

AVX2

Convert 8 packed signed doubleword integers from ymm2

VPACKUSDW ymm1, ymm2,

and 8 packed signed doubleword integers from

ymm3/m256

ymm3/m256 into 16 packed unsigned word integers in

ymm1 using unsigned saturation.

EVEX.128.66.0F38.W0 2B /r

V/V

AVX512VL

Convert packed signed doubleword integers from xmm2

VPACKUSDW xmm1{k1}{z},

AVX512BW

and packed signed doubleword integers from

xmm2, xmm3/m128/m32bcst

xmm3/m128/m32bcst into packed unsigned word integers

in xmm1 using unsigned saturation under writemask k1.

EVEX.256.66.0F38.W0 2B /r

V/V

AVX512VL

Convert packed signed doubleword integers from ymm2

VPACKUSDW ymm1{k1}{z},

AVX512BW

and packed signed doubleword integers from

ymm2, ymm3/m256/m32bcst

ymm3/m256/m32bcst into packed unsigned word integers

in ymm1 using unsigned saturation under writemask k1.

EVEX.512.66.0F38.W0 2B /r

V/V

AVX512BW

Convert packed signed doubleword integers from zmm2

VPACKUSDW zmm1{k1}{z},

and packed signed doubleword integers from

zmm2, zmm3/m512/m32bcst

zmm3/m512/m32bcst into packed unsigned word integers

in zmm1 using unsigned saturation under writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Converts packed signed doubleword integers in the first and second source operands into packed unsigned word

integers using unsigned saturation to handle overflow conditions. If the signed doubleword value is beyond the

range of an unsigned word (that is, greater than FFFFH or less than 0000H), the saturated unsigned word integer

value of FFFFH or 0000H, respectively, is stored in the destination.

EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand is a

ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 32-

bit memory location. The destination operand is a ZMM register, updated conditionally under the writemask k1.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register

or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAXVL-1:256) of the

corresponding ZMM register destination are zeroed.

VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM

the corresponding ZMM register destination are zeroed.

128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM

upper bits (MAXVL-1:128) of the corresponding destination register destination are unmodified.

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PACKUSDW—Pack With Unsigned Saturation

INSTRUCTION SET REFERENCE, M-U

Operation

PACKUSDW (Legacy SSE instruction)

TMP[15:0] := (DEST[31:0] < 0) ? 0 : DEST[15:0];

DEST[15:0] := (DEST[31:0] > FFFFH) ? FFFFH : TMP[15:0] ;

TMP[31:16] := (DEST[63:32] < 0) ? 0 : DEST[47:32];

DEST[31:16] := (DEST[63:32] > FFFFH) ? FFFFH : TMP[31:16] ;

TMP[47:32] := (DEST[95:64] < 0) ? 0 : DEST[79:64];

DEST[47:32] := (DEST[95:64] > FFFFH) ? FFFFH : TMP[47:32] ;

TMP[63:48] := (DEST[127:96] < 0) ? 0 : DEST[111:96];

DEST[63:48] := (DEST[127:96] > FFFFH) ? FFFFH : TMP[63:48] ;

TMP[79:64] := (SRC[31:0] < 0) ? 0 : SRC[15:0];

DEST[79:64] := (SRC[31:0] > FFFFH) ? FFFFH : TMP[79:64] ;

TMP[95:80] := (SRC[63:32] < 0) ? 0 : SRC[47:32];

DEST[95:80] := (SRC[63:32] > FFFFH) ? FFFFH : TMP[95:80] ;

TMP[111:96] := (SRC[95:64] < 0) ? 0 : SRC[79:64];

DEST[111:96] := (SRC[95:64] > FFFFH) ? FFFFH : TMP[111:96] ;

TMP[127:112] := (SRC[127:96] < 0) ? 0 : SRC[111:96];

DEST[127:112] := (SRC[127:96] > FFFFH) ? FFFFH : TMP[127:112] ;

DEST[MAXVL-1:128] (Unmodified)

PACKUSDW (VEX.128 encoded version)

TMP[15:0] := (SRC1[31:0] < 0) ? 0 : SRC1[15:0];

DEST[15:0] := (SRC1[31:0] > FFFFH) ? FFFFH : TMP[15:0] ;

TMP[31:16] := (SRC1[63:32] < 0) ? 0 : SRC1[47:32];

DEST[31:16] := (SRC1[63:32] > FFFFH) ? FFFFH : TMP[31:16] ;

TMP[47:32] := (SRC1[95:64] < 0) ? 0 : SRC1[79:64];

DEST[47:32] := (SRC1[95:64] > FFFFH) ? FFFFH : TMP[47:32] ;

TMP[63:48] := (SRC1[127:96] < 0) ? 0 : SRC1[111:96];

DEST[63:48] := (SRC1[127:96] > FFFFH) ? FFFFH : TMP[63:48] ;

TMP[79:64] := (SRC2[31:0] < 0) ? 0 : SRC2[15:0];

DEST[79:64] := (SRC2[31:0] > FFFFH) ? FFFFH : TMP[79:64] ;

TMP[95:80] := (SRC2[63:32] < 0) ? 0 : SRC2[47:32];

DEST[95:80] := (SRC2[63:32] > FFFFH) ? FFFFH : TMP[95:80] ;

TMP[111:96] := (SRC2[95:64] < 0) ? 0 : SRC2[79:64];

DEST[111:96] := (SRC2[95:64] > FFFFH) ? FFFFH : TMP[111:96] ;

TMP[127:112] := (SRC2[127:96] < 0) ? 0 : SRC2[111:96];

DEST[127:112] := (SRC2[127:96] > FFFFH) ? FFFFH : TMP[127:112];

DEST[MAXVL-1:128] := 0;

VPACKUSDW (VEX.256 encoded version)

TMP[15:0] := (SRC1[31:0] < 0) ? 0 : SRC1[15:0];

DEST[15:0] := (SRC1[31:0] > FFFFH) ? FFFFH : TMP[15:0] ;

TMP[31:16] := (SRC1[63:32] < 0) ? 0 : SRC1[47:32];

DEST[31:16] := (SRC1[63:32] > FFFFH) ? FFFFH : TMP[31:16] ;

TMP[47:32] := (SRC1[95:64] < 0) ? 0 : SRC1[79:64];

DEST[47:32] := (SRC1[95:64] > FFFFH) ? FFFFH : TMP[47:32] ;

TMP[63:48] := (SRC1[127:96] < 0) ? 0 : SRC1[111:96];

DEST[63:48] := (SRC1[127:96] > FFFFH) ? FFFFH : TMP[63:48] ;

TMP[79:64] := (SRC2[31:0] < 0) ? 0 : SRC2[15:0];

DEST[79:64] := (SRC2[31:0] > FFFFH) ? FFFFH : TMP[79:64] ;

TMP[95:80] := (SRC2[63:32] < 0) ? 0 : SRC2[47:32];

DEST[95:80] := (SRC2[63:32] > FFFFH) ? FFFFH : TMP[95:80] ;

TMP[111:96] := (SRC2[95:64] < 0) ? 0 : SRC2[79:64];

DEST[111:96] := (SRC2[95:64] > FFFFH) ? FFFFH : TMP[111:96] ;

PACKUSDW—Pack With Unsigned Saturation

Vol. 2B

4-201

INSTRUCTION SET REFERENCE, M-U

TMP[127:112] := (SRC2[127:96] < 0) ? 0 : SRC2[111:96];

DEST[127:112] := (SRC2[127:96] > FFFFH) ? FFFFH : TMP[127:112] ;

TMP[143:128] := (SRC1[159:128] < 0) ? 0 : SRC1[143:128];

DEST[143:128] := (SRC1[159:128] > FFFFH) ? FFFFH : TMP[143:128] ;

TMP[159:144] := (SRC1[191:160] < 0) ? 0 : SRC1[175:160];

DEST[159:144] := (SRC1[191:160] > FFFFH) ? FFFFH : TMP[159:144] ;

TMP[175:160] := (SRC1[223:192] < 0) ? 0 : SRC1[207:192];

DEST[175:160] := (SRC1[223:192] > FFFFH) ? FFFFH : TMP[175:160] ;

TMP[191:176] := (SRC1[255:224] < 0) ? 0 : SRC1[239:224];

DEST[191:176] := (SRC1[255:224] > FFFFH) ? FFFFH : TMP[191:176] ;

TMP[207:192] := (SRC2[159:128] < 0) ? 0 : SRC2[143:128];

DEST[207:192] := (SRC2[159:128] > FFFFH) ? FFFFH : TMP[207:192] ;

TMP[223:208] := (SRC2[191:160] < 0) ? 0 : SRC2[175:160];

DEST[223:208] := (SRC2[191:160] > FFFFH) ? FFFFH : TMP[223:208] ;

TMP[239:224] := (SRC2[223:192] < 0) ? 0 : SRC2[207:192];

DEST[239:224] := (SRC2[223:192] > FFFFH) ? FFFFH : TMP[239:224] ;

TMP[255:240] := (SRC2[255:224] < 0) ? 0 : SRC2[239:224];

DEST[255:240] := (SRC2[255:224] > FFFFH) ? FFFFH : TMP[255:240] ;

DEST[MAXVL-1:256] := 0;

VPACKUSDW (EVEX encoded versions)

(KL, VL) = (8, 128), (16, 256), (32, 512)

FOR j := 0 TO ((KL/2) - 1)

i := j * 32

IF (EVEX.b == 1) AND (SRC2 *is memory*)

THEN

TMP_SRC2[i+31:i] := SRC2[31:0]

ELSE

TMP_SRC2[i+31:i] := SRC2[i+31:i]

FI;

ENDFOR;

TMP[15:0] := (SRC1[31:0] < 0) ? 0 : SRC1[15:0];

DEST[15:0] := (SRC1[31:0] > FFFFH) ? FFFFH : TMP[15:0] ;

TMP[31:16] := (SRC1[63:32] < 0) ? 0 : SRC1[47:32];

DEST[31:16] := (SRC1[63:32] > FFFFH) ? FFFFH : TMP[31:16] ;

TMP[47:32] := (SRC1[95:64] < 0) ? 0 : SRC1[79:64];

DEST[47:32] := (SRC1[95:64] > FFFFH) ? FFFFH : TMP[47:32] ;

TMP[63:48] := (SRC1[127:96] < 0) ? 0 : SRC1[111:96];

DEST[63:48] := (SRC1[127:96] > FFFFH) ? FFFFH : TMP[63:48] ;

TMP[79:64] := (TMP_SRC2[31:0] < 0) ? 0 : TMP_SRC2[15:0];

DEST[79:64] := (TMP_SRC2[31:0] > FFFFH) ? FFFFH : TMP[79:64] ;

TMP[95:80] := (TMP_SRC2[63:32] < 0) ? 0 : TMP_SRC2[47:32];

DEST[95:80] := (TMP_SRC2[63:32] > FFFFH) ? FFFFH : TMP[95:80] ;

TMP[111:96] := (TMP_SRC2[95:64] < 0) ? 0 : TMP_SRC2[79:64];

DEST[111:96] := (TMP_SRC2[95:64] > FFFFH) ? FFFFH : TMP[111:96] ;

TMP[127:112] := (TMP_SRC2[127:96] < 0) ? 0 : TMP_SRC2[111:96];

DEST[127:112] := (TMP_SRC2[127:96] > FFFFH) ? FFFFH : TMP[127:112] ;

IF VL >= 256

TMP[143:128] := (SRC1[159:128] < 0) ? 0 : SRC1[143:128];

DEST[143:128] := (SRC1[159:128] > FFFFH) ? FFFFH : TMP[143:128] ;

TMP[159:144] := (SRC1[191:160] < 0) ? 0 : SRC1[175:160];

DEST[159:144] := (SRC1[191:160] > FFFFH) ? FFFFH : TMP[159:144] ;

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PACKUSDW—Pack With Unsigned Saturation

INSTRUCTION SET REFERENCE, M-U

TMP[175:160] := (SRC1[223:192] < 0) ? 0 : SRC1[207:192];

DEST[175:160] := (SRC1[223:192] > FFFFH) ? FFFFH : TMP[175:160] ;

TMP[191:176] := (SRC1[255:224] < 0) ? 0 : SRC1[239:224];

DEST[191:176] := (SRC1[255:224] > FFFFH) ? FFFFH : TMP[191:176] ;

TMP[207:192] := (TMP_SRC2[159:128] < 0) ? 0 : TMP_SRC2[143:128];

DEST[207:192] := (TMP_SRC2[159:128] > FFFFH) ? FFFFH : TMP[207:192] ;

TMP[223:208] := (TMP_SRC2[191:160] < 0) ? 0 : TMP_SRC2[175:160];

DEST[223:208] := (TMP_SRC2[191:160] > FFFFH) ? FFFFH : TMP[223:208] ;

TMP[239:224] := (TMP_SRC2[223:192] < 0) ? 0 : TMP_SRC2[207:192];

DEST[239:224] := (TMP_SRC2[223:192] > FFFFH) ? FFFFH : TMP[239:224] ;

TMP[255:240] := (TMP_SRC2[255:224] < 0) ? 0 : TMP_SRC2[239:224];

DEST[255:240] := (TMP_SRC2[255:224] > FFFFH) ? FFFFH : TMP[255:240] ;

FI;

IF VL >= 512

TMP[271:256] := (SRC1[287:256] < 0) ? 0 : SRC1[271:256];

DEST[271:256] := (SRC1[287:256] > FFFFH) ? FFFFH : TMP[271:256] ;

TMP[287:272] := (SRC1[319:288] < 0) ? 0 : SRC1[303:288];

DEST[287:272] := (SRC1[319:288] > FFFFH) ? FFFFH : TMP[287:272] ;

TMP[303:288] := (SRC1[351:320] < 0) ? 0 : SRC1[335:320];

DEST[303:288] := (SRC1[351:320] > FFFFH) ? FFFFH : TMP[303:288] ;

TMP[319:304] := (SRC1[383:352] < 0) ? 0 : SRC1[367:352];

DEST[319:304] := (SRC1[383:352] > FFFFH) ? FFFFH : TMP[319:304] ;

TMP[335:320] := (TMP_SRC2[287:256] < 0) ? 0 : TMP_SRC2[271:256];

DEST[335:304] := (TMP_SRC2[287:256] > FFFFH) ? FFFFH : TMP[79:64] ;

TMP[351:336] := (TMP_SRC2[319:288] < 0) ? 0 : TMP_SRC2[303:288];

DEST[351:336] := (TMP_SRC2[319:288] > FFFFH) ? FFFFH : TMP[351:336] ;

TMP[367:352] := (TMP_SRC2[351:320] < 0) ? 0 : TMP_SRC2[315:320];

DEST[367:352] := (TMP_SRC2[351:320] > FFFFH) ? FFFFH : TMP[367:352] ;

TMP[383:368] := (TMP_SRC2[383:352] < 0) ? 0 : TMP_SRC2[367:352];

DEST[383:368] := (TMP_SRC2[383:352] > FFFFH) ? FFFFH : TMP[383:368] ;

TMP[399:384] := (SRC1[415:384] < 0) ? 0 : SRC1[399:384];

DEST[399:384] := (SRC1[415:384] > FFFFH) ? FFFFH : TMP[399:384] ;

TMP[415:400] := (SRC1[447:416] < 0) ? 0 : SRC1[431:416];

DEST[415:400] := (SRC1[447:416] > FFFFH) ? FFFFH : TMP[415:400] ;

TMP[431:416] := (SRC1[479:448] < 0) ? 0 : SRC1[463:448];

DEST[431:416] := (SRC1[479:448] > FFFFH) ? FFFFH : TMP[431:416] ;

TMP[447:432] := (SRC1[511:480] < 0) ? 0 : SRC1[495:480];

DEST[447:432] := (SRC1[511:480] > FFFFH) ? FFFFH : TMP[447:432] ;

TMP[463:448] := (TMP_SRC2[415:384] < 0) ? 0 : TMP_SRC2[399:384];

DEST[463:448] := (TMP_SRC2[415:384] > FFFFH) ? FFFFH : TMP[463:448] ;

TMP[475:464] := (TMP_SRC2[447:416] < 0) ? 0 : TMP_SRC2[431:416];

DEST[475:464] := (TMP_SRC2[447:416] > FFFFH) ? FFFFH : TMP[475:464] ;

TMP[491:476] := (TMP_SRC2[479:448] < 0) ? 0 : TMP_SRC2[463:448];

DEST[491:476] := (TMP_SRC2[479:448] > FFFFH) ? FFFFH : TMP[491:476] ;

TMP[511:492] := (TMP_SRC2[511:480] < 0) ? 0 : TMP_SRC2[495:480];

DEST[511:492] := (TMP_SRC2[511:480] > FFFFH) ? FFFFH : TMP[511:492] ;

FI;

FOR j := 0 TO KL-1

i := j * 16

IF k1[j] OR *no writemask*

THEN

DEST[i+15:i] := TMP_DEST[i+15:i]

ELSE

IF *merging-masking*

; merging-masking

PACKUSDW—Pack With Unsigned Saturation

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INSTRUCTION SET REFERENCE, M-U

THEN *DEST[i+15:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+15:i] := 0

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

Intel C/C++ Compiler Intrinsic Equivalents

VPACKUSDW__m512i _mm512_packus_epi32(__m512i m1, __m512i m2);

VPACKUSDW__m512i _mm512_mask_packus_epi32(__m512i s, __mmask32 k, __m512i m1, __m512i m2);

VPACKUSDW__m512i _mm512_maskz_packus_epi32( __mmask32 k, __m512i m1, __m512i m2);

VPACKUSDW__m256i _mm256_mask_packus_epi32( __m256i s, __mmask16 k, __m256i m1, __m256i m2);

VPACKUSDW__m256i _mm256_maskz_packus_epi32( __mmask16 k, __m256i m1, __m256i m2);

VPACKUSDW__m128i _mm_mask_packus_epi32( __m128i s, __mmask8 k, __m128i m1, __m128i m2);

VPACKUSDW__m128i _mm_maskz_packus_epi32( __mmask8 k, __m128i m1, __m128i m2);

PACKUSDW__m128i _mm_packus_epi32(__m128i m1, __m128i m2);

VPACKUSDW__m256i _mm256_packus_epi32(__m256i m1, __m256i m2);

SIMD Floating-Point Exceptions

None

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions”.

EVEX-encoded instruction, see Table 2-50, “Type E4NF Class Exception Conditions”.

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INSTRUCTION SET REFERENCE, M-U

PACKUSWB—Pack With Unsigned Saturation

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature Flag

Support

NP 0F 67 /r¹

V/V

MMX

Converts 4 signed word integers from mm and

4 signed word integers from mm/m64 into 8

PACKUSWB mm, mm/m64

unsigned byte integers in mm using unsigned

saturation.

66 0F 67 /r

V/V

SSE2

Converts 8 signed word integers from xmm1

and 8 signed word integers from xmm2/m128

PACKUSWB xmm1, xmm2/m128

into 16 unsigned byte integers in xmm1 using

unsigned saturation.

VEX.128.66.0F.WIG 67 /r

V/V

AVX

Converts 8 signed word integers from xmm2

and 8 signed word integers from xmm3/m128

VPACKUSWB xmm1, xmm2, xmm3/m128

into 16 unsigned byte integers in xmm1 using

unsigned saturation.

VEX.256.66.0F.WIG 67 /r

V/V

AVX2

Converts 16 signed word integers from ymm2

and 16signed word integers from

VPACKUSWB ymm1, ymm2, ymm3/m256

ymm3/m256 into 32 unsigned byte integers

in ymm1 using unsigned saturation.

EVEX.128.66.0F.WIG 67 /r

V/V

AVX512VL

Converts signed word integers from xmm2

VPACKUSWB xmm1{k1}{z}, xmm2, xmm3/m128

AVX512BW

and signed word integers from xmm3/m128

into unsigned byte integers in xmm1 using

unsigned saturation under writemask k1.

EVEX.256.66.0F.WIG 67 /r

V/V

AVX512VL

Converts signed word integers from ymm2

VPACKUSWB ymm1{k1}{z}, ymm2, ymm3/m256

AVX512BW

and signed word integers from ymm3/m256

into unsigned byte integers in ymm1 using

unsigned saturation under writemask k1.

EVEX.512.66.0F.WIG 67 /r

V/V

AVX512BW

Converts signed word integers from zmm2

VPACKUSWB zmm1{k1}{z}, zmm2, zmm3/m512

and signed word integers from zmm3/m512

into unsigned byte integers in zmm1 using

unsigned saturation under writemask k1.

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2A and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Reg-

isters” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full Mem

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Converts 4, 8, 16 or 32 signed word integers from the destination operand (first operand) and 4, 8, 16 or 32 signed

word integers from the source operand (second operand) into 8, 16, 32 or 64 unsigned byte integers and stores the

result in the destination operand. (See Figure 4-6 for an example of the packing operation.) If a signed word

integer value is beyond the range of an unsigned byte integer (that is, greater than FFH or less than 00H), the satu-

rated unsigned byte integer value of FFH or 00H, respectively, is stored in the destination.

EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM

PACKUSWB—Pack With Unsigned Saturation

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INSTRUCTION SET REFERENCE, M-U

VEX.256 and EVEX.256 encoded versions: The first source operand is a YMM register. The second source operand

is a YMM register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAXVL-

1:256) of the corresponding ZMM register destination are zeroed.

VEX.128 and EVEX.128 encoded versions: The first source operand is an XMM register. The second source operand

is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-

1:128) of the corresponding register destination are zeroed.

128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM

upper bits (MAXVL-1:128) of the corresponding register destination are unmodified.

Operation

PACKUSWB (with 64-bit operands)

DEST[7:0] := SaturateSignedWordToUnsignedByte DEST[15:0];

DEST[15:8] := SaturateSignedWordToUnsignedByte DEST[31:16];

DEST[23:16] := SaturateSignedWordToUnsignedByte DEST[47:32];

DEST[31:24] := SaturateSignedWordToUnsignedByte DEST[63:48];

DEST[39:32] := SaturateSignedWordToUnsignedByte SRC[15:0];

DEST[47:40] := SaturateSignedWordToUnsignedByte SRC[31:16];

DEST[55:48] := SaturateSignedWordToUnsignedByte SRC[47:32];

DEST[63:56] := SaturateSignedWordToUnsignedByte SRC[63:48];

PACKUSWB (Legacy SSE instruction)

DEST[7:0] := SaturateSignedWordToUnsignedByte (DEST[15:0]);

DEST[15:8] := SaturateSignedWordToUnsignedByte (DEST[31:16]);

DEST[23:16] := SaturateSignedWordToUnsignedByte (DEST[47:32]);

DEST[31:24] := SaturateSignedWordToUnsignedByte (DEST[63:48]);

DEST[39:32] := SaturateSignedWordToUnsignedByte (DEST[79:64]);

DEST[47:40] := SaturateSignedWordToUnsignedByte (DEST[95:80]);

DEST[55:48] := SaturateSignedWordToUnsignedByte (DEST[111:96]);

DEST[63:56] := SaturateSignedWordToUnsignedByte (DEST[127:112]);

DEST[71:64] := SaturateSignedWordToUnsignedByte (SRC[15:0]);

DEST[79:72] := SaturateSignedWordToUnsignedByte (SRC[31:16]);

DEST[87:80] := SaturateSignedWordToUnsignedByte (SRC[47:32]);

DEST[95:88] := SaturateSignedWordToUnsignedByte (SRC[63:48]);

DEST[103:96] := SaturateSignedWordToUnsignedByte (SRC[79:64]);

DEST[111:104] := SaturateSignedWordToUnsignedByte (SRC[95:80]);

DEST[119:112] := SaturateSignedWordToUnsignedByte (SRC[111:96]);

DEST[127:120] := SaturateSignedWordToUnsignedByte (SRC[127:112]);

PACKUSWB (VEX.128 encoded version)

DEST[7:0] := SaturateSignedWordToUnsignedByte (SRC1[15:0]);

DEST[15:8] := SaturateSignedWordToUnsignedByte (SRC1[31:16]);

DEST[23:16] := SaturateSignedWordToUnsignedByte (SRC1[47:32]);

DEST[31:24] := SaturateSignedWordToUnsignedByte (SRC1[63:48]);

DEST[39:32] := SaturateSignedWordToUnsignedByte (SRC1[79:64]);

DEST[47:40] := SaturateSignedWordToUnsignedByte (SRC1[95:80]);

DEST[55:48] := SaturateSignedWordToUnsignedByte (SRC1[111:96]);

DEST[63:56] := SaturateSignedWordToUnsignedByte (SRC1[127:112]);

DEST[71:64] := SaturateSignedWordToUnsignedByte (SRC2[15:0]);

DEST[79:72] := SaturateSignedWordToUnsignedByte (SRC2[31:16]);

DEST[87:80] := SaturateSignedWordToUnsignedByte (SRC2[47:32]);

DEST[95:88] := SaturateSignedWordToUnsignedByte (SRC2[63:48]);

DEST[103:96] := SaturateSignedWordToUnsignedByte (SRC2[79:64]);

DEST[111:104] := SaturateSignedWordToUnsignedByte (SRC2[95:80]);

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PACKUSWB—Pack With Unsigned Saturation

INSTRUCTION SET REFERENCE, M-U

DEST[119:112] := SaturateSignedWordToUnsignedByte (SRC2[111:96]);

DEST[127:120] := SaturateSignedWordToUnsignedByte (SRC2[127:112]);

DEST[MAXVL-1:128] := 0;

VPACKUSWB (VEX.256 encoded version)